From 27a5bd6457c8ce38151250530152e15f76b697a8 Mon Sep 17 00:00:00 2001 From: David Daney <ddaney@caviumnetworks.com> Date: Wed, 10 Feb 2010 15:12:49 -0800 Subject: MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 425e708d4fb..bbf05404239 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,6 +58,9 @@ #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 + +#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) + #define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 -- cgit v1.2.3-70-g09d2