From a48cf37ac8a77ddd2370be3c9af411c622ebc425 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 4 May 2012 10:50:13 +0200 Subject: MIPS: pci: parse memory ranges from devicetree Implement pci_load_of_ranges on MIPS. Due to lack of test hardware only 32bit bus width is supported. This function is based on pci_process_bridge_OF_ranges from powerpc. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3729/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/pci.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index fcd4060f642..90bf3b3fce1 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -17,6 +17,7 @@ */ #include +#include /* * Each pci channel is a top-level PCI bus seem by CPU. A machine with @@ -26,6 +27,7 @@ struct pci_controller { struct pci_controller *next; struct pci_bus *bus; + struct device_node *of_node; struct pci_ops *pci_ops; struct resource *mem_resource; @@ -142,4 +144,8 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) extern char * (*pcibios_plat_setup)(char *str); +/* this function parses memory ranges from a device node */ +extern void __devinit pci_load_of_ranges(struct pci_controller *hose, + struct device_node *node); + #endif /* _ASM_PCI_H */ -- cgit v1.2.3-70-g09d2