From 1b362e3e350f72c6cb4b3346f6ba92a529082a09 Mon Sep 17 00:00:00 2001 From: David Daney Date: Fri, 22 Jan 2010 14:41:15 -0800 Subject: MIPS: Decode c0_config4 for large TLBs. For processors that have more than 64 TLBs, we need to decode both config1 and config4 to determine the total number TLBs. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/866/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 758ad426c57..323395081b2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -700,6 +700,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) return config3 & MIPS_CONF_M; } +static inline unsigned int decode_config4(struct cpuinfo_mips *c) +{ + unsigned int config4; + + config4 = read_c0_config4(); + + if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT + && cpu_has_tlb) + c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; + + return config4 & MIPS_CONF_M; +} + static void __cpuinit decode_configs(struct cpuinfo_mips *c) { int ok; @@ -718,6 +731,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) ok = decode_config2(c); if (ok) ok = decode_config3(c); + if (ok) + ok = decode_config4(c); mips_probe_watch_registers(c); } -- cgit v1.2.3-70-g09d2 From 2fe062608086f9b74a80f16272c5a59a3e05722f Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Wed, 20 Jan 2010 00:59:27 +0100 Subject: MIPS: Cleanup switches with cases that can be merged Signed-off-by: Roel Kluin To: linux-mips@linux-mips.org To: Andrew Morton To: LKML Patchwork: http://patchwork.linux-mips.org/patch/860/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/octeon/octeon-feature.h | 8 ++------ arch/mips/kernel/cpu-probe.c | 3 --- arch/mips/math-emu/ieee754dp.c | 1 - arch/mips/math-emu/ieee754sp.c | 1 - arch/mips/pci/pci-octeon.c | 6 ++---- arch/mips/powertv/asic/asic_devices.c | 4 ---- arch/mips/sgi-ip32/ip32-irq.c | 9 +-------- 7 files changed, 5 insertions(+), 27 deletions(-) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index ef24a7b4ea5..cba6fbed9f4 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -99,6 +99,8 @@ static inline int octeon_has_feature(enum octeon_feature feature) return !cvmx_fuse_read(90); case OCTEON_FEATURE_PCIE: + case OCTEON_FEATURE_MGMT_PORT: + case OCTEON_FEATURE_RAID: return OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX); @@ -110,12 +112,6 @@ static inline int octeon_has_feature(enum octeon_feature feature) case OCTEON_FEATURE_TRA: return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); - case OCTEON_FEATURE_MGMT_PORT: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); - case OCTEON_FEATURE_RAID: - return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); case OCTEON_FEATURE_USB: return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)); diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 323395081b2..1773544e3db 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -746,9 +746,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "MIPS 4Kc"; break; case PRID_IMP_4KEC: - c->cputype = CPU_4KEC; - __cpu_name[cpu] = "MIPS 4KEc"; - break; case PRID_IMP_4KECR2: c->cputype = CPU_4KEC; __cpu_name[cpu] = "MIPS 4KEc"; diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c index 6d2d89f3247..2f22fd7fd78 100644 --- a/arch/mips/math-emu/ieee754dp.c +++ b/arch/mips/math-emu/ieee754dp.c @@ -148,7 +148,6 @@ ieee754dp ieee754dp_format(int sn, int xe, u64 xm) switch(ieee754_csr.rm) { case IEEE754_RN: - return ieee754dp_zero(sn); case IEEE754_RZ: return ieee754dp_zero(sn); case IEEE754_RU: /* toward +Infinity */ diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c index 463534045ab..a19b72185ab 100644 --- a/arch/mips/math-emu/ieee754sp.c +++ b/arch/mips/math-emu/ieee754sp.c @@ -149,7 +149,6 @@ ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) switch(ieee754_csr.rm) { case IEEE754_RN: - return ieee754sp_zero(sn); case IEEE754_RZ: return ieee754sp_zero(sn); case IEEE754_RU: /* toward +Infinity */ diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c index 9cb0c807f56..d248b707eff 100644 --- a/arch/mips/pci/pci-octeon.c +++ b/arch/mips/pci/pci-octeon.c @@ -209,16 +209,14 @@ const char *octeon_get_pci_interrupts(void) case CVMX_BOARD_TYPE_NAO38: /* This is really the NAC38 */ return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; - case CVMX_BOARD_TYPE_THUNDER: - return ""; - case CVMX_BOARD_TYPE_EBH3000: - return ""; case CVMX_BOARD_TYPE_EBH3100: case CVMX_BOARD_TYPE_CN3010_EVB_HS5: case CVMX_BOARD_TYPE_CN3005_EVB_HS5: return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; case CVMX_BOARD_TYPE_BBGW_REF: return "AABCD"; + case CVMX_BOARD_TYPE_THUNDER: + case CVMX_BOARD_TYPE_EBH3000: default: return ""; } diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c index 6a882194e06..217424231eb 100644 --- a/arch/mips/powertv/asic/asic_devices.c +++ b/arch/mips/powertv/asic/asic_devices.c @@ -340,10 +340,6 @@ static void __init platform_configure_usb(void) switch (asic) { case ASIC_ZEUS: - fs_update(0x0000, 0x11, 0x02, 0); - bcm1_usb2_ctl = 0x803; - break; - case ASIC_CRONUS: case ASIC_CRONUSLITE: fs_update(0x0000, 0x11, 0x02, 0); diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 5c2bf111ca6..d8b65204d28 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -512,10 +512,6 @@ void __init arch_init_irq(void) "level"); break; - case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: - set_irq_chip_and_handler_name(irq, - &crime_edge_interrupt, handle_edge_irq, "edge"); - break; case CRIME_CPUERR_IRQ: case CRIME_MEMERR_IRQ: set_irq_chip_and_handler_name(irq, @@ -523,12 +519,9 @@ void __init arch_init_irq(void) "level"); break; + case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ: case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ: case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ: - set_irq_chip_and_handler_name(irq, - &crime_edge_interrupt, handle_edge_irq, "edge"); - break; - case CRIME_VICE_IRQ: set_irq_chip_and_handler_name(irq, &crime_edge_interrupt, handle_edge_irq, "edge"); -- cgit v1.2.3-70-g09d2 From 874fd3b5acc20f2a464409045aef3b2288069787 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 28 Jan 2010 16:52:12 -0800 Subject: MIPS: Allow the auxv's elf_platform entry to be set. The userspace runtime linker uses the elf_platform to find the libraries optimized for the current CPU archecture variant. First we need to allow it to be set to something other than NULL. Follow-on patches will set some values for specific CPUs. GLIBC already does the right thing. The kernel just needs to supply good data. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/891/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/elf.h | 14 +++++++------- arch/mips/kernel/cpu-probe.c | 1 + 2 files changed, 8 insertions(+), 7 deletions(-) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index 7a6a35dbe52..e53d7bed5cd 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -334,14 +334,14 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_HWCAP (0) -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. - - For the moment, we have only optimizations for the Intel generations, - but that could change... */ +/* + * This yields a string that ld.so will use to load implementation + * specific libraries for optimization. This is more specific in + * intent than poking at uname or /proc/cpuinfo. + */ -#define ELF_PLATFORM (NULL) +#define ELF_PLATFORM __elf_platform +extern const char *__elf_platform; /* * See comments in asm-alpha/elf.h, this is the same thing diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1773544e3db..494e8ab48d6 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -926,6 +926,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) } const char *__cpu_name[NR_CPUS]; +const char *__elf_platform; __cpuinit void cpu_probe(void) { -- cgit v1.2.3-70-g09d2 From 368bf8ef304f426be0a8a0be5b0e437747598c10 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 28 Jan 2010 16:52:13 -0800 Subject: MIPS: Set __elf_platform for Octeon. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/892/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/cpu-probe.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 494e8ab48d6..9ea5ca89e85 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -917,6 +917,8 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN52XX: c->cputype = CPU_CAVIUM_OCTEON; __cpu_name[cpu] = "Cavium Octeon"; + if (cpu == 0) + __elf_platform = "octeon"; break; default: printk(KERN_INFO "Unknown Octeon chip!\n"); -- cgit v1.2.3-70-g09d2 From 6f329468f3086e9d8f3832930fdb09ab3769176b Mon Sep 17 00:00:00 2001 From: David Daney Date: Wed, 10 Feb 2010 15:12:48 -0800 Subject: MIPS: Give Octeon+ CPUs their own cputype. This allows us to treat them differently at runtime. Signed-off-by: David Daney To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/cpu.h | 2 +- arch/mips/kernel/cpu-probe.c | 9 +++++++-- arch/mips/mm/c-octeon.c | 7 ++++--- 3 files changed, 12 insertions(+), 6 deletions(-) (limited to 'arch/mips/kernel/cpu-probe.c') diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index cf373a95fe4..a5acda41694 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -224,7 +224,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9ea5ca89e85..be5bb16be4e 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -162,6 +162,7 @@ void __init check_wait(void) case CPU_BCM6348: case CPU_BCM6358: case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: cpu_wait = r4k_wait; break; @@ -911,12 +912,16 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: + c->cputype = CPU_CAVIUM_OCTEON; + __cpu_name[cpu] = "Cavium Octeon"; + goto platform; case PRID_IMP_CAVIUM_CN58XX: case PRID_IMP_CAVIUM_CN56XX: case PRID_IMP_CAVIUM_CN50XX: case PRID_IMP_CAVIUM_CN52XX: - c->cputype = CPU_CAVIUM_OCTEON; - __cpu_name[cpu] = "Cavium Octeon"; + c->cputype = CPU_CAVIUM_OCTEON_PLUS; + __cpu_name[cpu] = "Cavium Octeon+"; +platform: if (cpu == 0) __elf_platform = "octeon"; break; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index af85959e59f..0f9c488044d 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; -- cgit v1.2.3-70-g09d2