From 2af59f7d5c3e342db4bdd28c59090aee05577aef Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 7 Dec 2007 09:23:05 +1100 Subject: [POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper This patch adds support for 405GPr processors with optional new mode strapping. ibm405gp_fixup_clocks() can now be used for 405GP and 405GPr CPUs. This is in preparation of porting the cpci405 platform support from arch/ppc to arch/powerpc. This patch also adds ibm405ep_fixup_clocks() to support 405EP CPUs from the boot wrapper. Signed-off-by: Matthias Fuchs Signed-off-by: Josh Boyer --- arch/powerpc/boot/dcr.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/powerpc/boot/dcr.h') diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 55655f78505..95b9f534401 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -146,7 +146,12 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, #define DCRN_CPC0_PLLMR 0xb0 #define DCRN_405_CPC0_CR0 0xb1 #define DCRN_405_CPC0_CR1 0xb2 +#define DCRN_405_CPC0_PSR 0xb4 +/* 405EP Clocking/Power Management/Chip Control regs */ +#define DCRN_CPC0_PLLMR0 0xf0 +#define DCRN_CPC0_PLLMR1 0xf4 +#define DCRN_CPC0_UCR 0xf5 /* 440GX Clock control etc */ -- cgit v1.2.3-70-g09d2