From b74a7e50cc87dea1b86d35860ace81412cb49886 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 30 Jan 2008 12:46:19 -0600 Subject: [POWERPC] 83xx: configure USB clock for MPC8315E SCCR USB bits are in a different location on the mpc8315. Signed-off-by: Jerry Huang Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8315erdb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts index b582032ba3d..d7a1ececa30 100644 --- a/arch/powerpc/boot/dts/mpc8315erdb.dts +++ b/arch/powerpc/boot/dts/mpc8315erdb.dts @@ -96,7 +96,7 @@ #address-cells = <1>; #size-cells = <1>; device_type = "soc"; - compatible = "simple-bus"; + compatible = "fsl,mpc8315-immr", "simple-bus"; ranges = <0 0xe0000000 0x00100000>; reg = <0xe0000000 0x00000200>; bus-frequency = <0>; -- cgit v1.2.3-70-g09d2 From b277b02588ec7534a033ff1cb0f947c18a4d3b54 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 31 Jan 2008 12:56:58 -0600 Subject: [POWERPC] 83xx: Correct 2nd PCI controller interrupt value in mpc834x_mds dts According to the 8349EA ref man, the second PCI PHB IRQ is 67. Thanks to Peter Van Ackeren for finding this. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc834x_mds.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc834x_mds.dts b/arch/powerpc/boot/dts/mpc834x_mds.dts index 7480edae85e..0199c5c548d 100644 --- a/arch/powerpc/boot/dts/mpc834x_mds.dts +++ b/arch/powerpc/boot/dts/mpc834x_mds.dts @@ -332,7 +332,7 @@ 0xc000 0x0 0x0 0x3 &ipic 23 0x8 0xc000 0x0 0x0 0x4 &ipic 20 0x8>; interrupt-parent = <&ipic>; - interrupts = <66 0x8>; + interrupts = <67 0x8>; bus-range = <0 0>; ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 -- cgit v1.2.3-70-g09d2 From 5cfade1829440af45cd24ea7483d2e16876fc602 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Thu, 31 Jan 2008 19:40:05 -0600 Subject: [POWERPC] 83xx: Add rtc node to mpc8313erdb dts The 8313 rdb has a ds1339 at address 0x68. Signed-off-by: Kim Phillips Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8313erdb.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts index 2d6653fe72f..e1f0dca8ac3 100644 --- a/arch/powerpc/boot/dts/mpc8313erdb.dts +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts @@ -118,6 +118,10 @@ interrupts = <14 0x8>; interrupt-parent = <&ipic>; dfsrr; + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; }; i2c@3100 { -- cgit v1.2.3-70-g09d2 From 03bbfe8b97eb277f1af27fef5a14224f7878a983 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sun, 3 Feb 2008 23:21:29 +0000 Subject: [POWERPC] 8xx: Add clock-frequency to adder875 and mpc885ads dts cpm_uart_core has a dependency on fsl,cpm-brg/clock-frequency, this means that a .dts that uses the cpm uart driver needs to supply a clock-frequency entry for get_brgfreq to return a meaningful number. Signed-off-by: Bryan O'Donoghue Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/adder875-redboot.dts | 1 + arch/powerpc/boot/dts/adder875-uboot.dts | 1 + arch/powerpc/boot/dts/mpc885ads.dts | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/adder875-redboot.dts b/arch/powerpc/boot/dts/adder875-redboot.dts index 930bfb3894e..28e9cd3d7a2 100644 --- a/arch/powerpc/boot/dts/adder875-redboot.dts +++ b/arch/powerpc/boot/dts/adder875-redboot.dts @@ -151,6 +151,7 @@ compatible = "fsl,mpc875-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <50000000>; reg = <0x9f0 0x10>; }; diff --git a/arch/powerpc/boot/dts/adder875-uboot.dts b/arch/powerpc/boot/dts/adder875-uboot.dts index 0197242dacf..54fb60ec03e 100644 --- a/arch/powerpc/boot/dts/adder875-uboot.dts +++ b/arch/powerpc/boot/dts/adder875-uboot.dts @@ -150,6 +150,7 @@ compatible = "fsl,mpc875-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <50000000>; reg = <0x9f0 0x10>; }; diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts index 8848e637293..d84a012c2aa 100644 --- a/arch/powerpc/boot/dts/mpc885ads.dts +++ b/arch/powerpc/boot/dts/mpc885ads.dts @@ -166,6 +166,7 @@ compatible = "fsl,mpc885-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <0>; reg = <9f0 10>; }; -- cgit v1.2.3-70-g09d2 From 0367aad1ad5f8085ed15e9e30604f50108a1ea06 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sat, 2 Feb 2008 13:02:51 -0600 Subject: [POWERPC] Fix storcenter DTS typos, feedback, IRQs. Cleaned up IRQ layout and removed unsused ISU allocations. Fixed RTC address typo from /dts-v1/ conversion. Incorporated list suggestions to use an "iomega," vendor prefix, and to use a node reference rather than a hard path. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/storcenter.dts | 12 ++++++------ arch/powerpc/platforms/embedded6xx/storcenter.c | 25 +++++-------------------- 2 files changed, 11 insertions(+), 26 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/storcenter.dts b/arch/powerpc/boot/dts/storcenter.dts index 2204874ac5f..5893816c0bc 100644 --- a/arch/powerpc/boot/dts/storcenter.dts +++ b/arch/powerpc/boot/dts/storcenter.dts @@ -15,7 +15,7 @@ / { model = "StorCenter"; - compatible = "storcenter"; + compatible = "iomega,storcenter"; #address-cells = <1>; #size-cells = <1>; @@ -62,12 +62,12 @@ #size-cells = <0>; compatible = "fsl-i2c"; reg = <0x3000 0x100>; - interrupts = <5 2>; + interrupts = <17 2>; interrupt-parent = <&mpic>; rtc@68 { compatible = "dallas,ds1337"; - reg = <68>; + reg = <0x68>; }; }; @@ -78,7 +78,7 @@ reg = <0x4500 0x20>; clock-frequency = <97553800>; /* Hz */ current-speed = <115200>; - interrupts = <9 2>; + interrupts = <25 2>; interrupt-parent = <&mpic>; }; @@ -89,7 +89,7 @@ reg = <0x4600 0x20>; clock-frequency = <97553800>; /* Hz */ current-speed = <9600>; - interrupts = <10 2>; + interrupts = <26 2>; interrupt-parent = <&mpic>; }; @@ -136,6 +136,6 @@ }; chosen { - linux,stdout-path = "/soc/serial@4500"; + linux,stdout-path = &serial0; }; }; diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c index e12e9d29871..8864e488498 100644 --- a/arch/powerpc/platforms/embedded6xx/storcenter.c +++ b/arch/powerpc/platforms/embedded6xx/storcenter.c @@ -132,33 +132,18 @@ static void __init storcenter_init_IRQ(void) paddr = (phys_addr_t)of_translate_address(dnp, prop); mpic = mpic_alloc(dnp, paddr, MPIC_PRIMARY | MPIC_WANTS_RESET, - 4, 32, " EPIC "); + 16, 32, " OpenPIC "); of_node_put(dnp); BUG_ON(mpic == NULL); - /* PCI IRQs */ /* - * 2.6.12 patch: - * openpic_set_sources(0, 5, OpenPIC_Addr + 0x10200); - * openpic_set_sources(5, 2, OpenPIC_Addr + 0x11120); - * first_irq, num_irqs, __iomem first_ISR - * o_ss: i, src: 0, fdf50200 - * o_ss: i, src: 1, fdf50220 - * o_ss: i, src: 2, fdf50240 - * o_ss: i, src: 3, fdf50260 - * o_ss: i, src: 4, fdf50280 - * o_ss: i, src: 5, fdf51120 - * o_ss: i, src: 6, fdf51140 + * 16 Serial Interrupts followed by 16 Internal Interrupts. + * I2C is the second internal, so it is at 17, 0x11020. */ mpic_assign_isu(mpic, 0, paddr + 0x10200); - mpic_assign_isu(mpic, 1, paddr + 0x10220); - mpic_assign_isu(mpic, 2, paddr + 0x10240); - mpic_assign_isu(mpic, 3, paddr + 0x10260); - mpic_assign_isu(mpic, 4, paddr + 0x10280); - mpic_assign_isu(mpic, 5, paddr + 0x11120); - mpic_assign_isu(mpic, 6, paddr + 0x11140); + mpic_assign_isu(mpic, 1, paddr + 0x11000); mpic_init(mpic); } @@ -178,7 +163,7 @@ static int __init storcenter_probe(void) { unsigned long root = of_get_flat_dt_root(); - return of_flat_dt_is_compatible(root, "storcenter"); + return of_flat_dt_is_compatible(root, "iomega,storcenter"); } define_machine(storcenter){ -- cgit v1.2.3-70-g09d2 From 7e25867fe8d705bcf707ef52004b669eb795d06d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 5 Feb 2008 23:58:30 -0600 Subject: [POWERPC] 85xx: Add second cpu to 8572 dts The 8572 is a dual core processor, not reason not to describe both cores in the device tree. Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/mpc8572ds.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts index 813c259abbe..db37214aee3 100644 --- a/arch/powerpc/boot/dts/mpc8572ds.dts +++ b/arch/powerpc/boot/dts/mpc8572ds.dts @@ -42,6 +42,18 @@ bus-frequency = <0>; clock-frequency = <0>; }; + + PowerPC,8572@1 { + device_type = "cpu"; + reg = <1>; + d-cache-line-size = <20>; // 32 bytes + i-cache-line-size = <20>; // 32 bytes + d-cache-size = <8000>; // L1, 32K + i-cache-size = <8000>; // L1, 32K + timebase-frequency = <0>; + bus-frequency = <0>; + clock-frequency = <0>; + }; }; memory { -- cgit v1.2.3-70-g09d2 From bd05f91f95b6ca692097f95244bdda25bd929216 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Tue, 29 Jan 2008 04:28:54 +1100 Subject: [POWERPC] mpc512x: Device tree for MPC5121 ADS Minimal /dts-v1/ device tree for mpc5121 ads. port-number property in uart nodes will go away after the driver learns to use aliases Signed-off-by: John Rigby Signed-off-by: Grant Likely --- arch/powerpc/boot/dts/mpc5121ads.dts | 122 +++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/powerpc/boot/dts/mpc5121ads.dts (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts new file mode 100644 index 00000000000..94ad7b2b241 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc5121ads.dts @@ -0,0 +1,122 @@ +/* + * MPC5121E MDS Device Tree Source + * + * Copyright 2007 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +/ { + model = "mpc5121ads"; + compatible = "fsl,mpc5121ads"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,5121@0 { + device_type = "cpu"; + reg = <0>; + d-cache-line-size = <0x20>; // 32 bytes + i-cache-line-size = <0x20>; // 32 bytes + d-cache-size = <0x8000>; // L1, 32K + i-cache-size = <0x8000>; // L1, 32K + timebase-frequency = <49500000>;// 49.5 MHz (csb/4) + bus-frequency = <198000000>; // 198 MHz csb bus + clock-frequency = <396000000>; // 396 MHz ppc core + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; // 256MB at 0 + }; + + localbus@80000020 { + compatible = "fsl,mpc5121ads-localbus"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x80000020 0x40>; + + ranges = <0x0 0x0 0xfc000000 0x04000000 + 0x2 0x0 0x82000000 0x00008000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x4000000>; + bank-width = <4>; + device-width = <1>; + }; + + board-control@2,0 { + compatible = "fsl,mpc5121ads-cpld"; + reg = <0x2 0x0 0x8000>; + }; + }; + + soc@80000000 { + compatible = "fsl,mpc5121-immr"; + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <2>; + ranges = <0x0 0x80000000 0x400000>; + reg = <0x80000000 0x400000>; + bus-frequency = <66000000>; // 66 MHz ips bus + + + // IPIC + // interrupts cell = + // sense values match linux IORESOURCE_IRQ_* defines: + // sense == 8: Level, low assertion + // sense == 2: Edge, high-to-low change + // + ipic: interrupt-controller@c00 { + compatible = "fsl,mpc5121-ipic", "fsl,ipic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0xc00 0x100>; + }; + + // 512x PSCs are not 52xx PSCs compatible + // PSC3 serial port A aka ttyPSC0 + serial@11300 { + device_type = "serial"; + compatible = "fsl,mpc5121-psc-uart"; + // Logical port assignment needed until driver + // learns to use aliases + port-number = <0>; + cell-index = <3>; + reg = <0x11300 0x100>; + interrupts = <0x28 0x8>; // actually the fifo irq + interrupt-parent = < &ipic >; + }; + + // PSC4 serial port B aka ttyPSC1 + serial@11400 { + device_type = "serial"; + compatible = "fsl,mpc5121-psc-uart"; + // Logical port assignment needed until driver + // learns to use aliases + port-number = <1>; + cell-index = <4>; + reg = <0x11400 0x100>; + interrupts = <0x28 0x8>; // actually the fifo irq + interrupt-parent = < &ipic >; + }; + + pscsfifo@11f00 { + compatible = "fsl,mpc5121-psc-fifo"; + reg = <0x11f00 0x100>; + interrupts = <0x28 0x8>; + interrupt-parent = < &ipic >; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 3c0c6cb5eb2931712d5d750bf27d27d37a44d75e Mon Sep 17 00:00:00 2001 From: Valentine Barshak Date: Tue, 25 Sep 2007 05:29:52 +1000 Subject: [POWERPC] 4xx: Add 440EPx Sequoia ehci dts entry Adds USB EHCI entry to PowerPC 440EPx Sequoia DTS. Signed-off-by: Valentine Barshak Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/sequoia.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index d9046c1adcb..5c13d46f441 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -138,6 +138,14 @@ interrupts = <15 8>; }; + USB0: ehci@e0000300 { + compatible = "ibm,usb-ehci-440epx", "usb-ehci"; + interrupt-parent = <&UIC0>; + interrupts = <1a 4>; + reg = <0 e0000300 90 0 e0000390 70>; + big-endian; + }; + POB0: opb { compatible = "ibm,opb-440epx", "ibm,opb"; #address-cells = <1>; -- cgit v1.2.3-70-g09d2