From fe671772ab1bf5624f2c4dbe2295e6ebeb8055fc Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 31 Mar 2009 08:46:25 -0500 Subject: powerpc/85xx: Use fsl,mpc85.. as prefix for memory ctrl & l2-cache nodes Older devices tree's used "fsl,85.." instead of the preferred "fsl,mpc85.." for the memory controller & l2 cache controller nodes. The EDAC code is the only use of these and has been updated for some time to support both "fsl,85.." and "fsl,mpc85.." Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/ksi8560.dts | 4 ++-- arch/powerpc/boot/dts/sbc8548.dts | 4 ++-- arch/powerpc/boot/dts/sbc8560.dts | 4 ++-- arch/powerpc/boot/dts/stx_gp3_8560.dts | 4 ++-- arch/powerpc/boot/dts/tqm8540.dts | 4 ++-- arch/powerpc/boot/dts/tqm8541.dts | 4 ++-- arch/powerpc/boot/dts/tqm8555.dts | 4 ++-- arch/powerpc/boot/dts/tqm8560.dts | 4 ++-- 8 files changed, 16 insertions(+), 16 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/ksi8560.dts b/arch/powerpc/boot/dts/ksi8560.dts index 308fe7c29de..c9cfd374bff 100644 --- a/arch/powerpc/boot/dts/ksi8560.dts +++ b/arch/powerpc/boot/dts/ksi8560.dts @@ -57,14 +57,14 @@ bus-frequency = <0>; /* Fixed by bootwrapper */ memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; /* 32 bytes */ cache-size = <0x40000>; /* L2, 256K */ diff --git a/arch/powerpc/boot/dts/sbc8548.dts b/arch/powerpc/boot/dts/sbc8548.dts index 9c5079fec4f..b1f1416ac99 100644 --- a/arch/powerpc/boot/dts/sbc8548.dts +++ b/arch/powerpc/boot/dts/sbc8548.dts @@ -156,14 +156,14 @@ compatible = "simple-bus"; memory-controller@2000 { - compatible = "fsl,8548-memory-controller"; + compatible = "fsl,mpc8548-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8548-l2-cache-controller"; + compatible = "fsl,mpc8548-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x80000>; // L2, 512K diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts index b772405a9a0..c4564b81e47 100644 --- a/arch/powerpc/boot/dts/sbc8560.dts +++ b/arch/powerpc/boot/dts/sbc8560.dts @@ -61,14 +61,14 @@ clock-frequency = <0>; memory-controller@2000 { - compatible = "fsl,8560-memory-controller"; + compatible = "fsl,mpc8560-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <0x12 0x2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8560-l2-cache-controller"; + compatible = "fsl,mpc8560-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <0x20>; // 32 bytes cache-size = <0x40000>; // L2, 256K diff --git a/arch/powerpc/boot/dts/stx_gp3_8560.dts b/arch/powerpc/boot/dts/stx_gp3_8560.dts index 8b173957fb5..ea6b15152de 100644 --- a/arch/powerpc/boot/dts/stx_gp3_8560.dts +++ b/arch/powerpc/boot/dts/stx_gp3_8560.dts @@ -57,14 +57,14 @@ compatible = "fsl,mpc8560-immr", "simple-bus"; memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; cache-size = <0x40000>; // L2, 256K diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts index ac9413a29f9..231bae75663 100644 --- a/arch/powerpc/boot/dts/tqm8540.dts +++ b/arch/powerpc/boot/dts/tqm8540.dts @@ -59,14 +59,14 @@ compatible = "fsl,mpc8540-immr", "simple-bus"; memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; cache-size = <0x40000>; // L2, 256K diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts index c71bb5dd5e5..4356a1f0829 100644 --- a/arch/powerpc/boot/dts/tqm8541.dts +++ b/arch/powerpc/boot/dts/tqm8541.dts @@ -58,14 +58,14 @@ compatible = "fsl,mpc8541-immr", "simple-bus"; memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; cache-size = <0x40000>; // L2, 256K diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts index a133ded6ddd..06d366ebbda 100644 --- a/arch/powerpc/boot/dts/tqm8555.dts +++ b/arch/powerpc/boot/dts/tqm8555.dts @@ -58,14 +58,14 @@ compatible = "fsl,mpc8555-immr", "simple-bus"; memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; cache-size = <0x40000>; // L2, 256K diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts index 649e2e57626..feff915e049 100644 --- a/arch/powerpc/boot/dts/tqm8560.dts +++ b/arch/powerpc/boot/dts/tqm8560.dts @@ -60,14 +60,14 @@ compatible = "fsl,mpc8560-immr", "simple-bus"; memory-controller@2000 { - compatible = "fsl,8540-memory-controller"; + compatible = "fsl,mpc8540-memory-controller"; reg = <0x2000 0x1000>; interrupt-parent = <&mpic>; interrupts = <18 2>; }; L2: l2-cache-controller@20000 { - compatible = "fsl,8540-l2-cache-controller"; + compatible = "fsl,mpc8540-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; cache-size = <0x40000>; // L2, 256K -- cgit v1.2.3-70-g09d2 From 212f8c6d67634b133b2bc816e4aa6ca82fbd334c Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Thu, 2 Apr 2009 20:50:56 +0200 Subject: powerpc/85xx: Re-add the device_type soc to socrates.dts The device_type "soc" is still required for MPC85xx boards. Signed-off-by: Wolfgang Grandegger Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/socrates.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/socrates.dts b/arch/powerpc/boot/dts/socrates.dts index b8d0fc6f004..04c398862e0 100644 --- a/arch/powerpc/boot/dts/socrates.dts +++ b/arch/powerpc/boot/dts/socrates.dts @@ -52,6 +52,7 @@ soc8544@e0000000 { #address-cells = <1>; #size-cells = <1>; + device_type = "soc"; ranges = <0x00000000 0xe0000000 0x00100000>; reg = <0xe0000000 0x00001000>; // CCSRBAR 1M -- cgit v1.2.3-70-g09d2 From 65cc0fa3bde00e81f83348ef162a83ab9fff2079 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 3 Apr 2009 15:58:46 -0500 Subject: powerpc/pq2fads: Update device tree for use with device-tree-aware u-boot. Add aliases, and correct CS0 offset to match how u-boot programs it (this was not a problem with cuImage because the wrapper would reprogram the localbus to match the device tree). Signed-off-by: Scott Wood Signed-off-by: Kumar Gala --- arch/powerpc/boot/dts/pq2fads.dts | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'arch/powerpc/boot/dts') diff --git a/arch/powerpc/boot/dts/pq2fads.dts b/arch/powerpc/boot/dts/pq2fads.dts index b2d61091b36..0bb66937674 100644 --- a/arch/powerpc/boot/dts/pq2fads.dts +++ b/arch/powerpc/boot/dts/pq2fads.dts @@ -17,6 +17,14 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + serial0 = &serial0; + serial1 = &serial1; + pci0 = &pci0; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -45,7 +53,7 @@ #size-cells = <1>; reg = <0xf0010100 0x60>; - ranges = <0x0 0x0 0xfe000000 0x800000 + ranges = <0x0 0x0 0xff800000 0x800000 0x1 0x0 0xf4500000 0x8000 0x8 0x0 0xf8200000 0x8000>; @@ -71,7 +79,7 @@ }; }; - pci@f0010800 { + pci0: pci@f0010800 { device_type = "pci"; reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>; compatible = "fsl,mpc8280-pci", "fsl,pq2-pci"; @@ -142,7 +150,7 @@ reg = <0x119f0 0x10 0x115f0 0x10>; }; - serial@11a00 { + serial0: serial@11a00 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; @@ -153,7 +161,7 @@ fsl,cpm-command = <0x800000>; }; - serial@11a20 { + serial1: serial@11a20 { device_type = "serial"; compatible = "fsl,mpc8280-scc-uart", "fsl,cpm2-scc-uart"; @@ -164,7 +172,7 @@ fsl,cpm-command = <0x4a00000>; }; - ethernet@11320 { + enet0: ethernet@11320 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; @@ -176,7 +184,7 @@ fsl,cpm-command = <0x16200300>; }; - ethernet@11340 { + enet1: ethernet@11340 { device_type = "network"; compatible = "fsl,mpc8280-fcc-enet", "fsl,cpm2-fcc-enet"; -- cgit v1.2.3-70-g09d2