From 6fbc779c03591ee536fef9efb7d7e20f281d0b5c Mon Sep 17 00:00:00 2001 From: Victor Gallardo Date: Thu, 18 Sep 2008 12:41:26 +0000 Subject: ibm_newemac: Fix EMAC soft reset on 460EX/GT This patch fixes EMAC soft reset on 460EX/GT when no external clock is available. Signed-off-by: Victor Gallardo Signed-off-by: David S. Miller --- arch/powerpc/include/asm/dcr-regs.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/powerpc/include') diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 29b0ecef980..f15296cf359 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -68,6 +68,10 @@ #define SDR0_UART3 0x0123 #define SDR0_CUST0 0x4000 +/* SDRs (460EX/460GT) */ +#define SDR0_ETH_CFG 0x4103 +#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ + /* * All those DCR register addresses are offsets from the base address * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is -- cgit v1.2.3-70-g09d2