From 2fce1225af6f2d3bb9ffb4e6253400db61278594 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 3 Oct 2007 23:37:33 -0500 Subject: [POWERPC] FSL: Access PCIe LTSSM register with correct size The LTSSM register is actual 32-bits wide so we should be doing a dword access. Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/powerpc/sysdev/fsl_pci.c') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 98290f4ef3d..af090c93be1 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -160,8 +160,8 @@ static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev) int __init fsl_pcie_check_link(struct pci_controller *hose) { - u16 val; - early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); + u32 val; + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); if (val < PCIE_LTSSM_L0) return 1; return 0; -- cgit v1.2.3-70-g09d2