From cc6ea0dd28d450925dd43135647fcb73f171c748 Mon Sep 17 00:00:00 2001 From: Roy ZANG Date: Fri, 21 Sep 2012 04:12:52 +0000 Subject: powerpc/85xx: Add support for FSL PCIe controller v3.0 The T4240 utilizes a new PCIe controller block that has some minor programming model differences from previous versions. The major one that impacts initialization is how we determine the link state. On the 3.x controllers we have a memory mapped SoC register instead of a PCI config register that reports the link state. Signed-off-by: Roy Zang Signed-off-by: Andy Fleming Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.h') diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c495c00c874..c81bf4407b5 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -17,6 +17,7 @@ #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ +#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */ #define PIWAR_EN 0x80000000 /* Enable */ #define PIWAR_PF 0x20000000 /* prefetch */ #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ @@ -89,6 +90,16 @@ struct ccsr_pci { __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ + u8 res_e38[200]; + __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */ + u8 res_f04[16]; + __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/ +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 +#define PEX_CSR0_LTSSM_L0 0x11 + __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/ + u8 res_f1c[228]; + }; extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); -- cgit v1.2.3-70-g09d2 From c7417202569ff31c4ddc88811b30925263951da1 Mon Sep 17 00:00:00 2001 From: Jia Hongtao Date: Fri, 15 Mar 2013 14:14:58 +0800 Subject: powerpc/85xx: Add platform_device declaration to fsl_pci.h mpc85xx_pci_err_probe(struct platform_device *op) need platform_device declaration for definition. Otherwise, it will cause compile error if any files including fsl_pci.h without declaration of platform_device. Signed-off-by: Jia Hongtao Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/powerpc/sysdev/fsl_pci.h') diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index c81bf4407b5..72b5625330e 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -14,6 +14,8 @@ #ifndef __POWERPC_FSL_PCI_H #define __POWERPC_FSL_PCI_H +struct platform_device; + #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ -- cgit v1.2.3-70-g09d2