From f50b153b1966230e78034d5ab1641ca4bb5db56d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 16 Apr 2005 15:24:22 -0700 Subject: [PATCH] ppc32: Support 36-bit physical addressing on e500 To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/syslib/ppc85xx_common.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/ppc/syslib') diff --git a/arch/ppc/syslib/ppc85xx_common.c b/arch/ppc/syslib/ppc85xx_common.c index e83f2f8686d..da841dacdc1 100644 --- a/arch/ppc/syslib/ppc85xx_common.c +++ b/arch/ppc/syslib/ppc85xx_common.c @@ -31,3 +31,11 @@ get_ccsrbar(void) } EXPORT_SYMBOL(get_ccsrbar); + +/* For now this is a pass through */ +phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size) +{ + return addr; +}; +EXPORT_SYMBOL(fixup_bigphys_addr); + -- cgit v1.2.3-70-g09d2