From a77b5ac0ea8e47c77008d3a9a9976dcfbc01c42a Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 13 May 2009 17:55:00 +0900 Subject: sh: clkfwk: Update SH7785 for refactored clock framework. This updates the SH7785 CPU code as well as the SH7785LCR board support code for making use of the newly refactored clock framework. Support for the legacy CPG clocks is dropped at this point, with the extal frequency fed in from the board code. Signed-off-by: Paul Mundt --- arch/sh/boards/board-sh7785lcr.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'arch/sh/boards/board-sh7785lcr.c') diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index 6f94f17adc4..33b194b0454 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -2,12 +2,12 @@ * Renesas Technology Corp. R0P7785LC0011RL Support. * * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ - #include #include #include @@ -19,8 +19,11 @@ #include #include #include -#include +#include +#include #include +#include +#include /* * NOTE: This board has 2 physical memory maps. @@ -273,6 +276,20 @@ void __init init_sh7785lcr_IRQ(void) plat_irq_setup_pins(IRQ_MODE_IRQ3210); } +static int sh7785lcr_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (!clk || IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + static void sh7785lcr_power_off(void) { unsigned char *p; @@ -309,6 +326,7 @@ static void __init sh7785lcr_setup(char **cmdline_p) static struct sh_machine_vector mv_sh7785lcr __initmv = { .mv_name = "SH7785LCR", .mv_setup = sh7785lcr_setup, + .mv_clk_init = sh7785lcr_clk_init, .mv_init_irq = init_sh7785lcr_IRQ, }; -- cgit v1.2.3-70-g09d2 From 63d12e23235d982d8f55696e09b2ff91e3ba0042 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 May 2009 12:00:25 +0000 Subject: sh: sh7785lcr mode pin configuration This patch adds mode pin support to the sh7785lcr board. The harware allows the user to control the mode pins using dip switches S1 and S2, but from the software the pins are fixed to the factory default since we have no way to reading out this configuration from software. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/boards/board-sh7785lcr.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/sh/boards/board-sh7785lcr.c') diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index 33b194b0454..c2894c5b71e 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -24,6 +24,7 @@ #include #include #include +#include /* * NOTE: This board has 2 physical memory maps. @@ -320,6 +321,26 @@ static void __init sh7785lcr_setup(char **cmdline_p) writel(0x000307c2, sm501_reg); } +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */ + value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */ + value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */ + value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */ + value |= 1 << MODE_PIN_MODE8; /* Little Endian */ + value |= 1 << MODE_PIN_MODE9; /* Master Mode */ + value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */ + + return value; +} + /* * The Machine Vector */ @@ -328,5 +349,6 @@ static struct sh_machine_vector mv_sh7785lcr __initmv = { .mv_setup = sh7785lcr_setup, .mv_clk_init = sh7785lcr_clk_init, .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, }; -- cgit v1.2.3-70-g09d2 From 0d4fdbb64f472ef31195714993f1263f77cf85ca Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 2 Jun 2009 09:22:02 +0000 Subject: sh: rework mode pin code This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/boards/board-sh7785lcr.c | 14 ++++++------ arch/sh/include/asm/processor.h | 17 +++++++++++++++ arch/sh/include/cpu-sh4/cpu/sh7785.h | 39 +++++++++++++++++----------------- arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 2 +- arch/sh/kernel/setup.c | 2 +- 5 files changed, 46 insertions(+), 28 deletions(-) (limited to 'arch/sh/boards/board-sh7785lcr.c') diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index c2894c5b71e..7be56fb06c1 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -330,13 +330,13 @@ static int sh7785lcr_mode_pins(void) * If you change these dip switches then you will need to * adjust the values below as well. */ - value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */ - value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */ - value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */ - value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */ - value |= 1 << MODE_PIN_MODE8; /* Little Endian */ - value |= 1 << MODE_PIN_MODE9; /* Master Mode */ - value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ return value; } diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index fb67482e47e..ff7daaf9a62 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -95,6 +95,23 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c); extern const struct seq_operations cpuinfo_op; /* processor boot mode configuration */ +#define MODE_PIN0 (1 << 0) +#define MODE_PIN1 (1 << 1) +#define MODE_PIN2 (1 << 2) +#define MODE_PIN3 (1 << 3) +#define MODE_PIN4 (1 << 4) +#define MODE_PIN5 (1 << 5) +#define MODE_PIN6 (1 << 6) +#define MODE_PIN7 (1 << 7) +#define MODE_PIN8 (1 << 8) +#define MODE_PIN9 (1 << 9) +#define MODE_PIN10 (1 << 10) +#define MODE_PIN11 (1 << 11) +#define MODE_PIN12 (1 << 12) +#define MODE_PIN13 (1 << 13) +#define MODE_PIN14 (1 << 14) +#define MODE_PIN15 (1 << 15) + int generic_mode_pins(void); int test_mode_pin(int pin); diff --git a/arch/sh/include/cpu-sh4/cpu/sh7785.h b/arch/sh/include/cpu-sh4/cpu/sh7785.h index 89afaa6dc2d..9dc9d91e0a8 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7785.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7785.h @@ -1,25 +1,26 @@ #ifndef __ASM_SH7785_H__ #define __ASM_SH7785_H__ -/* Boot Mode Pins, more information in sh7785 manual Rev.1.00, page 1628 */ -enum { - MODE_PIN_MODE0, /* CPG - Initial Pck/Bck Frequency [FRQMR1] */ - MODE_PIN_MODE1, /* CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] */ - MODE_PIN_MODE2, /* CPG - Reserved (L: Normal operation) */ - MODE_PIN_MODE3, /* CPG - Reserved (L: Normal operation) */ - MODE_PIN_MODE4, /* CPG - Initial PLL setting (72x/36x) */ - MODE_PIN_MODE5, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] */ - MODE_PIN_MODE6, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] */ - MODE_PIN_MODE7, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] */ - MODE_PIN_MODE8, /* LBSC - Endian Mode (L: Big, H: Little) [BCR.31] */ - MODE_PIN_MODE9, /* LBSC - Master/Slave Mode (L: Slave) [BCR.30] */ - MODE_PIN_MODE10, /* CPG - Clock Input (L: Ext Clk, H: Crystal) */ - MODE_PIN_MODE11, /* PCI - Pin Mode (LL: PCI host, LH: PCI slave) */ - MODE_PIN_MODE12, /* PCI - Pin Mode (HL: Local bus, HH: DU) */ - MODE_PIN_MODE13, /* Boot Address Mode (L: 29-bit, H: 32-bit) */ - MODE_PIN_MODE14, /* Reserved (H: Normal operation) */ - MODE_PIN_MPMD, /* Emulation Mode (L: Emulation mode, H: LSI mode) */ -}; +/* Boot Mode Pins: + * + * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1] + * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] + * MODE2: CPG - Reserved (L: Normal operation) + * MODE3: CPG - Reserved (L: Normal operation) + * MODE4: CPG - Initial PLL setting (72x/36x) + * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] + * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] + * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] + * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31] + * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30] + * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal) + * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave) + * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU) + * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit) + * MODE14: Reserved (H: Normal operation) + * + * More information in sh7785 manual Rev.1.00, page 1628. + */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index dae20aca536..73abfbf2f16 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -32,7 +32,7 @@ static unsigned long pll_recalc(struct clk *clk) { int multiplier; - multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72; + multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; return clk->parent->rate * multiplier; } diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 050131eec77..dd38338553e 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -429,7 +429,7 @@ int generic_mode_pins(void) int test_mode_pin(int pin) { - return sh_mv.mv_mode_pins() & (1 << pin); + return sh_mv.mv_mode_pins() & pin; } static const char *cpu_name[] = { -- cgit v1.2.3-70-g09d2