From da2014a2b080e7f3024a4eb6917d47069ad9620b Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 29 Jul 2008 21:01:19 +0900 Subject: sh: Shuffle the board directories in to mach groups. This flattens out the board directories in to individual mach groups, we will use this for getting rid of unneeded directories, simplifying the build system, and becoming more coherent with the refactored arch/sh/include topology. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7206/Makefile | 5 + arch/sh/boards/mach-se/7206/io.c | 104 +++++++++++++ arch/sh/boards/mach-se/7206/irq.c | 146 +++++++++++++++++++ arch/sh/boards/mach-se/7206/setup.c | 108 ++++++++++++++ arch/sh/boards/mach-se/7343/Makefile | 5 + arch/sh/boards/mach-se/7343/io.c | 273 +++++++++++++++++++++++++++++++++++ arch/sh/boards/mach-se/7343/irq.c | 80 ++++++++++ arch/sh/boards/mach-se/7343/setup.c | 152 +++++++++++++++++++ arch/sh/boards/mach-se/7619/Makefile | 5 + arch/sh/boards/mach-se/7619/setup.c | 21 +++ arch/sh/boards/mach-se/770x/Makefile | 5 + arch/sh/boards/mach-se/770x/io.c | 156 ++++++++++++++++++++ arch/sh/boards/mach-se/770x/irq.c | 108 ++++++++++++++ arch/sh/boards/mach-se/770x/setup.c | 222 ++++++++++++++++++++++++++++ arch/sh/boards/mach-se/7721/Makefile | 1 + arch/sh/boards/mach-se/7721/irq.c | 45 ++++++ arch/sh/boards/mach-se/7721/setup.c | 99 +++++++++++++ arch/sh/boards/mach-se/7722/Makefile | 10 ++ arch/sh/boards/mach-se/7722/irq.c | 76 ++++++++++ arch/sh/boards/mach-se/7722/setup.c | 194 +++++++++++++++++++++++++ arch/sh/boards/mach-se/7751/Makefile | 7 + arch/sh/boards/mach-se/7751/io.c | 135 +++++++++++++++++ arch/sh/boards/mach-se/7751/irq.c | 50 +++++++ arch/sh/boards/mach-se/7751/pci.c | 147 +++++++++++++++++++ arch/sh/boards/mach-se/7751/setup.c | 78 ++++++++++ arch/sh/boards/mach-se/7780/Makefile | 10 ++ arch/sh/boards/mach-se/7780/irq.c | 46 ++++++ arch/sh/boards/mach-se/7780/setup.c | 124 ++++++++++++++++ 28 files changed, 2412 insertions(+) create mode 100644 arch/sh/boards/mach-se/7206/Makefile create mode 100644 arch/sh/boards/mach-se/7206/io.c create mode 100644 arch/sh/boards/mach-se/7206/irq.c create mode 100644 arch/sh/boards/mach-se/7206/setup.c create mode 100644 arch/sh/boards/mach-se/7343/Makefile create mode 100644 arch/sh/boards/mach-se/7343/io.c create mode 100644 arch/sh/boards/mach-se/7343/irq.c create mode 100644 arch/sh/boards/mach-se/7343/setup.c create mode 100644 arch/sh/boards/mach-se/7619/Makefile create mode 100644 arch/sh/boards/mach-se/7619/setup.c create mode 100644 arch/sh/boards/mach-se/770x/Makefile create mode 100644 arch/sh/boards/mach-se/770x/io.c create mode 100644 arch/sh/boards/mach-se/770x/irq.c create mode 100644 arch/sh/boards/mach-se/770x/setup.c create mode 100644 arch/sh/boards/mach-se/7721/Makefile create mode 100644 arch/sh/boards/mach-se/7721/irq.c create mode 100644 arch/sh/boards/mach-se/7721/setup.c create mode 100644 arch/sh/boards/mach-se/7722/Makefile create mode 100644 arch/sh/boards/mach-se/7722/irq.c create mode 100644 arch/sh/boards/mach-se/7722/setup.c create mode 100644 arch/sh/boards/mach-se/7751/Makefile create mode 100644 arch/sh/boards/mach-se/7751/io.c create mode 100644 arch/sh/boards/mach-se/7751/irq.c create mode 100644 arch/sh/boards/mach-se/7751/pci.c create mode 100644 arch/sh/boards/mach-se/7751/setup.c create mode 100644 arch/sh/boards/mach-se/7780/Makefile create mode 100644 arch/sh/boards/mach-se/7780/irq.c create mode 100644 arch/sh/boards/mach-se/7780/setup.c (limited to 'arch/sh/boards/mach-se') diff --git a/arch/sh/boards/mach-se/7206/Makefile b/arch/sh/boards/mach-se/7206/Makefile new file mode 100644 index 00000000000..63e7ed699f3 --- /dev/null +++ b/arch/sh/boards/mach-se/7206/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the 7206 SolutionEngine specific parts of the kernel +# + +obj-y := setup.o io.o irq.o diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c new file mode 100644 index 00000000000..1308e618e04 --- /dev/null +++ b/arch/sh/boards/mach-se/7206/io.c @@ -0,0 +1,104 @@ +/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $ + * + * linux/arch/sh/boards/se/7206/io.c + * + * Copyright (C) 2006 Yoshinori Sato + * + * I/O routine for Hitachi 7206 SolutionEngine. + * + */ + +#include +#include +#include +#include + + +static inline void delay(void) +{ + ctrl_inw(0x20000000); /* P2 ROM Area */ +} + +/* MS7750 requires special versions of in*, out* routines, since + PC-like io ports are located at upper half byte of 16-bit word which + can be accessed only with 16-bit wide. */ + +static inline volatile __u16 * +port2adr(unsigned int port) +{ + if (port >= 0x2000 && port < 0x2020) + return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); + else if (port >= 0x300 && port < 0x310) + return (volatile __u16 *) (PA_SMSC + (port - 0x300)); + + return (volatile __u16 *)port; +} + +unsigned char se7206_inb(unsigned long port) +{ + return (*port2adr(port)) & 0xff; +} + +unsigned char se7206_inb_p(unsigned long port) +{ + unsigned long v; + + v = (*port2adr(port)) & 0xff; + delay(); + return v; +} + +unsigned short se7206_inw(unsigned long port) +{ + return *port2adr(port);; +} + +void se7206_outb(unsigned char value, unsigned long port) +{ + *(port2adr(port)) = value; +} + +void se7206_outb_p(unsigned char value, unsigned long port) +{ + *(port2adr(port)) = value; + delay(); +} + +void se7206_outw(unsigned short value, unsigned long port) +{ + *port2adr(port) = value; +} + +void se7206_insb(unsigned long port, void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + __u8 *ap = addr; + + while (count--) + *ap++ = *p; +} + +void se7206_insw(unsigned long port, void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + __u16 *ap = addr; + while (count--) + *ap++ = *p; +} + +void se7206_outsb(unsigned long port, const void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + const __u8 *ap = addr; + + while (count--) + *p = *ap++; +} + +void se7206_outsw(unsigned long port, const void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + const __u16 *ap = addr; + while (count--) + *p = *ap++; +} diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c new file mode 100644 index 00000000000..9d5bfc77d0d --- /dev/null +++ b/arch/sh/boards/mach-se/7206/irq.c @@ -0,0 +1,146 @@ +/* + * linux/arch/sh/boards/se/7206/irq.c + * + * Copyright (C) 2005,2006 Yoshinori Sato + * + * Hitachi SolutionEngine Support. + * + */ +#include +#include +#include +#include +#include + +#define INTSTS0 0x31800000 +#define INTSTS1 0x31800002 +#define INTMSK0 0x31800004 +#define INTMSK1 0x31800006 +#define INTSEL 0x31800008 + +#define IRQ0_IRQ 64 +#define IRQ1_IRQ 65 +#define IRQ3_IRQ 67 + +#define INTC_IPR01 0xfffe0818 +#define INTC_ICR1 0xfffe0802 + +static void disable_se7206_irq(unsigned int irq) +{ + unsigned short val; + unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq))); + unsigned short msk0,msk1; + + /* Set the priority in IPR to 0 */ + val = ctrl_inw(INTC_IPR01); + val &= mask; + ctrl_outw(val, INTC_IPR01); + /* FPGA mask set */ + msk0 = ctrl_inw(INTMSK0); + msk1 = ctrl_inw(INTMSK1); + + switch (irq) { + case IRQ0_IRQ: + msk0 |= 0x0010; + break; + case IRQ1_IRQ: + msk0 |= 0x000f; + break; + case IRQ3_IRQ: + msk0 |= 0x0f00; + msk1 |= 0x00ff; + break; + } + ctrl_outw(msk0, INTMSK0); + ctrl_outw(msk1, INTMSK1); +} + +static void enable_se7206_irq(unsigned int irq) +{ + unsigned short val; + unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq))); + unsigned short msk0,msk1; + + /* Set priority in IPR back to original value */ + val = ctrl_inw(INTC_IPR01); + val |= value; + ctrl_outw(val, INTC_IPR01); + + /* FPGA mask reset */ + msk0 = ctrl_inw(INTMSK0); + msk1 = ctrl_inw(INTMSK1); + + switch (irq) { + case IRQ0_IRQ: + msk0 &= ~0x0010; + break; + case IRQ1_IRQ: + msk0 &= ~0x000f; + break; + case IRQ3_IRQ: + msk0 &= ~0x0f00; + msk1 &= ~0x00ff; + break; + } + ctrl_outw(msk0, INTMSK0); + ctrl_outw(msk1, INTMSK1); +} + +static void eoi_se7206_irq(unsigned int irq) +{ + unsigned short sts0,sts1; + + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) + enable_se7206_irq(irq); + /* FPGA isr clear */ + sts0 = ctrl_inw(INTSTS0); + sts1 = ctrl_inw(INTSTS1); + + switch (irq) { + case IRQ0_IRQ: + sts0 &= ~0x0010; + break; + case IRQ1_IRQ: + sts0 &= ~0x000f; + break; + case IRQ3_IRQ: + sts0 &= ~0x0f00; + sts1 &= ~0x00ff; + break; + } + ctrl_outw(sts0, INTSTS0); + ctrl_outw(sts1, INTSTS1); +} + +static struct irq_chip se7206_irq_chip __read_mostly = { + .name = "SE7206-FPGA", + .mask = disable_se7206_irq, + .unmask = enable_se7206_irq, + .mask_ack = disable_se7206_irq, + .eoi = eoi_se7206_irq, +}; + +static void make_se7206_irq(unsigned int irq) +{ + disable_irq_nosync(irq); + set_irq_chip_and_handler_name(irq, &se7206_irq_chip, + handle_level_irq, "level"); + disable_se7206_irq(irq); +} + +/* + * Initialize IRQ setting + */ +void __init init_se7206_IRQ(void) +{ + make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */ + make_se7206_irq(IRQ1_IRQ); /* ATA */ + make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */ + ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */ + + /* FPGA System register setup*/ + ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */ + ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */ + /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */ + ctrl_outw(0x0001,INTSEL); +} diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c new file mode 100644 index 00000000000..4fe84cc0840 --- /dev/null +++ b/arch/sh/boards/mach-se/7206/setup.c @@ -0,0 +1,108 @@ +/* + * + * linux/arch/sh/boards/se/7206/setup.c + * + * Copyright (C) 2006 Yoshinori Sato + * Copyright (C) 2007 - 2008 Paul Mundt + * + * Hitachi 7206 SolutionEngine Support. + */ +#include +#include +#include +#include +#include +#include +#include + +static struct resource smc91x_resources[] = { + [0] = { + .name = "smc91x-regs", + .start = PA_SMSC + 0x300, + .end = PA_SMSC + 0x300 + 0x020 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 64, + .end = 64, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .regsize = 32, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se7206_devices[] __initdata = { + &smc91x_device, + &heartbeat_device, +}; + +static int __init se7206_devices_setup(void) +{ + return platform_add_devices(se7206_devices, ARRAY_SIZE(se7206_devices)); +} +__initcall(se7206_devices_setup); + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_se __initmv = { + .mv_name = "SolutionEngine", + .mv_nr_irqs = 256, + .mv_inb = se7206_inb, + .mv_inw = se7206_inw, + .mv_outb = se7206_outb, + .mv_outw = se7206_outw, + + .mv_inb_p = se7206_inb_p, + .mv_inw_p = se7206_inw, + .mv_outb_p = se7206_outb_p, + .mv_outw_p = se7206_outw, + + .mv_insb = se7206_insb, + .mv_insw = se7206_insw, + .mv_outsb = se7206_outsb, + .mv_outsw = se7206_outsw, + + .mv_init_irq = init_se7206_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7343/Makefile b/arch/sh/boards/mach-se/7343/Makefile new file mode 100644 index 00000000000..3024796c620 --- /dev/null +++ b/arch/sh/boards/mach-se/7343/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the 7343 SolutionEngine specific parts of the kernel +# + +obj-y := setup.o io.o irq.o diff --git a/arch/sh/boards/mach-se/7343/io.c b/arch/sh/boards/mach-se/7343/io.c new file mode 100644 index 00000000000..e2fae32d27d --- /dev/null +++ b/arch/sh/boards/mach-se/7343/io.c @@ -0,0 +1,273 @@ +/* + * arch/sh/boards/se/7343/io.c + * + * I/O routine for SH-Mobile3AS 7343 SolutionEngine. + * + */ +#include +#include +#include + +#define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a) + +struct iop { + unsigned long start, end; + unsigned long base; + struct iop *(*check) (struct iop * p, unsigned long port); + unsigned char (*inb) (struct iop * p, unsigned long port); + unsigned short (*inw) (struct iop * p, unsigned long port); + void (*outb) (struct iop * p, unsigned char value, unsigned long port); + void (*outw) (struct iop * p, unsigned short value, unsigned long port); +}; + +struct iop * +simple_check(struct iop *p, unsigned long port) +{ + static int count; + + if (count < 100) + count++; + + port &= 0xFFFF; + + if ((p->start <= port) && (port <= p->end)) + return p; + else + badio(check, port); +} + +struct iop * +ide_check(struct iop *p, unsigned long port) +{ + if (((0x1f0 <= port) && (port <= 0x1f7)) || (port == 0x3f7)) + return p; + return NULL; +} + +unsigned char +simple_inb(struct iop *p, unsigned long port) +{ + return *(unsigned char *) (p->base + port); +} + +unsigned short +simple_inw(struct iop *p, unsigned long port) +{ + return *(unsigned short *) (p->base + port); +} + +void +simple_outb(struct iop *p, unsigned char value, unsigned long port) +{ + *(unsigned char *) (p->base + port) = value; +} + +void +simple_outw(struct iop *p, unsigned short value, unsigned long port) +{ + *(unsigned short *) (p->base + port) = value; +} + +unsigned char +pcc_inb(struct iop *p, unsigned long port) +{ + unsigned long addr = p->base + port + 0x40000; + unsigned long v; + + if (port & 1) + addr += 0x00400000; + v = *(volatile unsigned char *) addr; + return v; +} + +void +pcc_outb(struct iop *p, unsigned char value, unsigned long port) +{ + unsigned long addr = p->base + port + 0x40000; + + if (port & 1) + addr += 0x00400000; + *(volatile unsigned char *) addr = value; +} + +unsigned char +bad_inb(struct iop *p, unsigned long port) +{ + badio(inb, port); +} + +void +bad_outb(struct iop *p, unsigned char value, unsigned long port) +{ + badio(inw, port); +} + +#ifdef CONFIG_SMC91X +/* MSTLANEX01 LAN at 0xb400:0000 */ +static struct iop laniop = { + .start = 0x00, + .end = 0x0F, + .base = 0x04000000, + .check = simple_check, + .inb = simple_inb, + .inw = simple_inw, + .outb = simple_outb, + .outw = simple_outw, +}; +#endif + +#ifdef CONFIG_NE2000 +/* NE2000 pc card NIC */ +static struct iop neiop = { + .start = 0x280, + .end = 0x29f, + .base = 0xb0600000 + 0x80, /* soft 0x280 -> hard 0x300 */ + .check = simple_check, + .inb = pcc_inb, + .inw = simple_inw, + .outb = pcc_outb, + .outw = simple_outw, +}; +#endif + +#ifdef CONFIG_IDE +/* CF in CF slot */ +static struct iop cfiop = { + .base = 0xb0600000, + .check = ide_check, + .inb = pcc_inb, + .inw = simple_inw, + .outb = pcc_outb, + .outw = simple_outw, +}; +#endif + +static __inline__ struct iop * +port2iop(unsigned long port) +{ + if (0) ; +#if defined(CONFIG_SMC91X) + else if (laniop.check(&laniop, port)) + return &laniop; +#endif +#if defined(CONFIG_NE2000) + else if (neiop.check(&neiop, port)) + return &neiop; +#endif +#if defined(CONFIG_IDE) + else if (cfiop.check(&cfiop, port)) + return &cfiop; +#endif + else + return NULL; +} + +static inline void +delay(void) +{ + ctrl_inw(0xac000000); + ctrl_inw(0xac000000); +} + +unsigned char +sh7343se_inb(unsigned long port) +{ + struct iop *p = port2iop(port); + return (p->inb) (p, port); +} + +unsigned char +sh7343se_inb_p(unsigned long port) +{ + unsigned char v = sh7343se_inb(port); + delay(); + return v; +} + +unsigned short +sh7343se_inw(unsigned long port) +{ + struct iop *p = port2iop(port); + return (p->inw) (p, port); +} + +unsigned int +sh7343se_inl(unsigned long port) +{ + badio(inl, port); +} + +void +sh7343se_outb(unsigned char value, unsigned long port) +{ + struct iop *p = port2iop(port); + (p->outb) (p, value, port); +} + +void +sh7343se_outb_p(unsigned char value, unsigned long port) +{ + sh7343se_outb(value, port); + delay(); +} + +void +sh7343se_outw(unsigned short value, unsigned long port) +{ + struct iop *p = port2iop(port); + (p->outw) (p, value, port); +} + +void +sh7343se_outl(unsigned int value, unsigned long port) +{ + badio(outl, port); +} + +void +sh7343se_insb(unsigned long port, void *addr, unsigned long count) +{ + unsigned char *a = addr; + struct iop *p = port2iop(port); + while (count--) + *a++ = (p->inb) (p, port); +} + +void +sh7343se_insw(unsigned long port, void *addr, unsigned long count) +{ + unsigned short *a = addr; + struct iop *p = port2iop(port); + while (count--) + *a++ = (p->inw) (p, port); +} + +void +sh7343se_insl(unsigned long port, void *addr, unsigned long count) +{ + badio(insl, port); +} + +void +sh7343se_outsb(unsigned long port, const void *addr, unsigned long count) +{ + unsigned char *a = (unsigned char *) addr; + struct iop *p = port2iop(port); + while (count--) + (p->outb) (p, *a++, port); +} + +void +sh7343se_outsw(unsigned long port, const void *addr, unsigned long count) +{ + unsigned short *a = (unsigned short *) addr; + struct iop *p = port2iop(port); + while (count--) + (p->outw) (p, *a++, port); +} + +void +sh7343se_outsl(unsigned long port, const void *addr, unsigned long count) +{ + badio(outsw, port); +} diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c new file mode 100644 index 00000000000..1112e86aa93 --- /dev/null +++ b/arch/sh/boards/mach-se/7343/irq.c @@ -0,0 +1,80 @@ +/* + * linux/arch/sh/boards/se/7343/irq.c + * + * Copyright (C) 2008 Yoshihiro Shimoda + * + * Based on linux/arch/sh/boards/se/7722/irq.c + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +static void disable_se7343_irq(unsigned int irq) +{ + unsigned int bit = irq - SE7343_FPGA_IRQ_BASE; + ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK); +} + +static void enable_se7343_irq(unsigned int irq) +{ + unsigned int bit = irq - SE7343_FPGA_IRQ_BASE; + ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK); +} + +static struct irq_chip se7343_irq_chip __read_mostly = { + .name = "SE7343-FPGA", + .mask = disable_se7343_irq, + .unmask = enable_se7343_irq, + .mask_ack = disable_se7343_irq, +}; + +static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + unsigned short intv = ctrl_inw(PA_CPLD_ST); + struct irq_desc *ext_desc; + unsigned int ext_irq = SE7343_FPGA_IRQ_BASE; + + intv &= (1 << SE7343_FPGA_IRQ_NR) - 1; + + while (intv) { + if (intv & 1) { + ext_desc = irq_desc + ext_irq; + handle_level_irq(ext_irq, ext_desc); + } + intv >>= 1; + ext_irq++; + } +} + +/* + * Initialize IRQ setting + */ +void __init init_7343se_IRQ(void) +{ + int i; + + ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */ + ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ + + for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) + set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i, + &se7343_irq_chip, + handle_level_irq, "level"); + + set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux); + set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux); + set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux); + set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW); + set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux); + set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW); +} diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c new file mode 100644 index 00000000000..59dc92e20f6 --- /dev/null +++ b/arch/sh/boards/mach-se/7343/setup.c @@ -0,0 +1,152 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x10000000, + .end = 0x1000000F, + .flags = IORESOURCE_MEM, + }, + [1] = { + /* + * shared with other devices via externel + * interrupt controller in FPGA... + */ + .start = SMC_IRQ, + .end = SMC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .regsize = 16, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 128 * 1024, + }, + { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = 31 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x01ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct platform_device *sh7343se_platform_devices[] __initdata = { + &smc91x_device, + &heartbeat_device, + &nor_flash_device, +}; + +static int __init sh7343se_devices_setup(void) +{ + return platform_add_devices(sh7343se_platform_devices, + ARRAY_SIZE(sh7343se_platform_devices)); +} +device_initcall(sh7343se_devices_setup); + +/* + * Initialize the board + */ +static void __init sh7343se_setup(char **cmdline_p) +{ + ctrl_outw(0xf900, FPGA_OUT); /* FPGA */ + + ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */ + ctrl_outw(0x0020, PORT_PSELD); + + printk(KERN_INFO "MS7343CP01 Setup...done\n"); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_7343se __initmv = { + .mv_name = "SolutionEngine 7343", + .mv_setup = sh7343se_setup, + .mv_nr_irqs = 108, + .mv_inb = sh7343se_inb, + .mv_inw = sh7343se_inw, + .mv_inl = sh7343se_inl, + .mv_outb = sh7343se_outb, + .mv_outw = sh7343se_outw, + .mv_outl = sh7343se_outl, + + .mv_inb_p = sh7343se_inb_p, + .mv_inw_p = sh7343se_inw, + .mv_inl_p = sh7343se_inl, + .mv_outb_p = sh7343se_outb_p, + .mv_outw_p = sh7343se_outw, + .mv_outl_p = sh7343se_outl, + + .mv_insb = sh7343se_insb, + .mv_insw = sh7343se_insw, + .mv_insl = sh7343se_insl, + .mv_outsb = sh7343se_outsb, + .mv_outsw = sh7343se_outsw, + .mv_outsl = sh7343se_outsl, + + .mv_init_irq = init_7343se_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7619/Makefile b/arch/sh/boards/mach-se/7619/Makefile new file mode 100644 index 00000000000..d21775c28cd --- /dev/null +++ b/arch/sh/boards/mach-se/7619/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the 7619 SolutionEngine specific parts of the kernel +# + +obj-y := setup.o diff --git a/arch/sh/boards/mach-se/7619/setup.c b/arch/sh/boards/mach-se/7619/setup.c new file mode 100644 index 00000000000..1d0ef7faa10 --- /dev/null +++ b/arch/sh/boards/mach-se/7619/setup.c @@ -0,0 +1,21 @@ +/* + * arch/sh/boards/se/7619/setup.c + * + * Copyright (C) 2006 Yoshinori Sato + * + * Hitachi SH7619 SolutionEngine Support. + */ + +#include +#include +#include +#include + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_se __initmv = { + .mv_name = "SolutionEngine", + .mv_nr_irqs = 108, +}; diff --git a/arch/sh/boards/mach-se/770x/Makefile b/arch/sh/boards/mach-se/770x/Makefile new file mode 100644 index 00000000000..8e624b06d5e --- /dev/null +++ b/arch/sh/boards/mach-se/770x/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the 770x SolutionEngine specific parts of the kernel +# + +obj-y := setup.o io.o irq.o diff --git a/arch/sh/boards/mach-se/770x/io.c b/arch/sh/boards/mach-se/770x/io.c new file mode 100644 index 00000000000..b1ec085b867 --- /dev/null +++ b/arch/sh/boards/mach-se/770x/io.c @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2000 Kazumoto Kojima + * + * I/O routine for Hitachi SolutionEngine. + */ +#include +#include +#include +#include + +/* MS7750 requires special versions of in*, out* routines, since + PC-like io ports are located at upper half byte of 16-bit word which + can be accessed only with 16-bit wide. */ + +static inline volatile __u16 * +port2adr(unsigned int port) +{ + if (port & 0xff000000) + return ( volatile __u16 *) port; + if (port >= 0x2000) + return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); + else if (port >= 0x1000) + return (volatile __u16 *) (PA_83902 + (port << 1)); + else + return (volatile __u16 *) (PA_SUPERIO + (port << 1)); +} + +static inline int +shifted_port(unsigned long port) +{ + /* For IDE registers, value is not shifted */ + if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) + return 0; + else + return 1; +} + +unsigned char se_inb(unsigned long port) +{ + if (shifted_port(port)) + return (*port2adr(port) >> 8); + else + return (*port2adr(port))&0xff; +} + +unsigned char se_inb_p(unsigned long port) +{ + unsigned long v; + + if (shifted_port(port)) + v = (*port2adr(port) >> 8); + else + v = (*port2adr(port))&0xff; + ctrl_delay(); + return v; +} + +unsigned short se_inw(unsigned long port) +{ + if (port >= 0x2000) + return *port2adr(port); + else + maybebadio(port); + return 0; +} + +unsigned int se_inl(unsigned long port) +{ + maybebadio(port); + return 0; +} + +void se_outb(unsigned char value, unsigned long port) +{ + if (shifted_port(port)) + *(port2adr(port)) = value << 8; + else + *(port2adr(port)) = value; +} + +void se_outb_p(unsigned char value, unsigned long port) +{ + if (shifted_port(port)) + *(port2adr(port)) = value << 8; + else + *(port2adr(port)) = value; + ctrl_delay(); +} + +void se_outw(unsigned short value, unsigned long port) +{ + if (port >= 0x2000) + *port2adr(port) = value; + else + maybebadio(port); +} + +void se_outl(unsigned int value, unsigned long port) +{ + maybebadio(port); +} + +void se_insb(unsigned long port, void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + __u8 *ap = addr; + + if (shifted_port(port)) { + while (count--) + *ap++ = *p >> 8; + } else { + while (count--) + *ap++ = *p; + } +} + +void se_insw(unsigned long port, void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + __u16 *ap = addr; + while (count--) + *ap++ = *p; +} + +void se_insl(unsigned long port, void *addr, unsigned long count) +{ + maybebadio(port); +} + +void se_outsb(unsigned long port, const void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + const __u8 *ap = addr; + + if (shifted_port(port)) { + while (count--) + *p = *ap++ << 8; + } else { + while (count--) + *p = *ap++; + } +} + +void se_outsw(unsigned long port, const void *addr, unsigned long count) +{ + volatile __u16 *p = port2adr(port); + const __u16 *ap = addr; + + while (count--) + *p = *ap++; +} + +void se_outsl(unsigned long port, const void *addr, unsigned long count) +{ + maybebadio(port); +} diff --git a/arch/sh/boards/mach-se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c new file mode 100644 index 00000000000..cdb0807928a --- /dev/null +++ b/arch/sh/boards/mach-se/770x/irq.c @@ -0,0 +1,108 @@ +/* + * linux/arch/sh/boards/se/770x/irq.c + * + * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2006 Nobuhiro Iwamatsu + * + * Hitachi SolutionEngine Support. + * + */ + +#include +#include +#include +#include +#include +#include + +static struct ipr_data ipr_irq_table[] = { + /* + * Super I/O (Just mimic PC): + * 1: keyboard + * 3: serial 0 + * 4: serial 1 + * 5: printer + * 6: floppy + * 8: rtc + * 12: mouse + * 14: ide0 + */ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) + /* This is default value */ + { 13, 0, 8, 0x0f-13, }, + { 5 , 0, 4, 0x0f- 5, }, + { 10, 1, 0, 0x0f-10, }, + { 7 , 2, 4, 0x0f- 7, }, + { 3 , 2, 0, 0x0f- 3, }, + { 1 , 3, 12, 0x0f- 1, }, + { 12, 3, 4, 0x0f-12, }, /* LAN */ + { 2 , 4, 8, 0x0f- 2, }, /* PCIRQ2 */ + { 6 , 4, 4, 0x0f- 6, }, /* PCIRQ1 */ + { 14, 4, 0, 0x0f-14, }, /* PCIRQ0 */ + { 0 , 5, 12, 0x0f , }, + { 4 , 5, 4, 0x0f- 4, }, + { 8 , 6, 12, 0x0f- 8, }, + { 9 , 6, 8, 0x0f- 9, }, + { 11, 6, 4, 0x0f-11, }, +#else + { 14, 0, 8, 0x0f-14, }, + { 12, 0, 4, 0x0f-12, }, + { 8, 1, 4, 0x0f- 8, }, + { 6, 2, 12, 0x0f- 6, }, + { 5, 2, 8, 0x0f- 5, }, + { 4, 2, 4, 0x0f- 4, }, + { 3, 2, 0, 0x0f- 3, }, + { 1, 3, 12, 0x0f- 1, }, +#if defined(CONFIG_STNIC) + /* ST NIC */ + { 10, 3, 4, 0x0f-10, }, /* LAN */ +#endif + /* MRSHPC IRQs setting */ + { 0, 4, 12, 0x0f- 0, }, /* PCIRQ3 */ + { 11, 4, 8, 0x0f-11, }, /* PCIRQ2 */ + { 9, 4, 4, 0x0f- 9, }, /* PCIRQ1 */ + { 7, 4, 0, 0x0f- 7, }, /* PCIRQ0 */ + /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ + /* NOTE: #2 and #13 are not used on PC */ + { 13, 6, 4, 0x0f-13, }, /* SLOTIRQ2 */ + { 2, 6, 0, 0x0f- 2, }, /* SLOTIRQ1 */ +#endif +}; + +static unsigned long ipr_offsets[] = { + BCR_ILCRA, + BCR_ILCRB, + BCR_ILCRC, + BCR_ILCRD, + BCR_ILCRE, + BCR_ILCRF, + BCR_ILCRG, +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + .chip = { + .name = "IPR-se770x", + }, +}; + +/* + * Initialize IRQ setting + */ +void __init init_se_IRQ(void) +{ + /* Disable all interrupts */ + ctrl_outw(0, BCR_ILCRA); + ctrl_outw(0, BCR_ILCRB); + ctrl_outw(0, BCR_ILCRC); + ctrl_outw(0, BCR_ILCRD); + ctrl_outw(0, BCR_ILCRE); + ctrl_outw(0, BCR_ILCRF); + ctrl_outw(0, BCR_ILCRG); + + register_ipr_controller(&ipr_irq_desc); +} diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c new file mode 100644 index 00000000000..6c64d774da3 --- /dev/null +++ b/arch/sh/boards/mach-se/770x/setup.c @@ -0,0 +1,222 @@ +/* + * linux/arch/sh/boards/se/770x/setup.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * Configure the Super I/O chip + */ +static void __init smsc_config(int index, int data) +{ + outb_p(index, INDEX_PORT); + outb_p(data, DATA_PORT); +} + +/* XXX: Another candidate for a more generic cchip machine vector */ +static void __init smsc_setup(char **cmdline_p) +{ + outb_p(CONFIG_ENTER, CONFIG_PORT); + outb_p(CONFIG_ENTER, CONFIG_PORT); + + /* FDC */ + smsc_config(CURRENT_LDN_INDEX, LDN_FDC); + smsc_config(ACTIVATE_INDEX, 0x01); + smsc_config(IRQ_SELECT_INDEX, 6); /* IRQ6 */ + + /* AUXIO (GPIO): to use IDE1 */ + smsc_config(CURRENT_LDN_INDEX, LDN_AUXIO); + smsc_config(GPIO46_INDEX, 0x00); /* nIOROP */ + smsc_config(GPIO47_INDEX, 0x00); /* nIOWOP */ + + /* COM1 */ + smsc_config(CURRENT_LDN_INDEX, LDN_COM1); + smsc_config(ACTIVATE_INDEX, 0x01); + smsc_config(IO_BASE_HI_INDEX, 0x03); + smsc_config(IO_BASE_LO_INDEX, 0xf8); + smsc_config(IRQ_SELECT_INDEX, 4); /* IRQ4 */ + + /* COM2 */ + smsc_config(CURRENT_LDN_INDEX, LDN_COM2); + smsc_config(ACTIVATE_INDEX, 0x01); + smsc_config(IO_BASE_HI_INDEX, 0x02); + smsc_config(IO_BASE_LO_INDEX, 0xf8); + smsc_config(IRQ_SELECT_INDEX, 3); /* IRQ3 */ + + /* RTC */ + smsc_config(CURRENT_LDN_INDEX, LDN_RTC); + smsc_config(ACTIVATE_INDEX, 0x01); + smsc_config(IRQ_SELECT_INDEX, 8); /* IRQ8 */ + + /* XXX: PARPORT, KBD, and MOUSE will come here... */ + outb_p(CONFIG_EXIT, CONFIG_PORT); +} + + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_CFCARD, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .regsize = 16, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ + defined(CONFIG_CPU_SUBTYPE_SH7712) +/* SH771X Ethernet driver */ +static struct resource sh_eth0_resources[] = { + [0] = { + .start = SH_ETH0_BASE, + .end = SH_ETH0_BASE + 0x1B8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SH_ETH0_IRQ, + .end = SH_ETH0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_eth0_device = { + .name = "sh-eth", + .id = 0, + .dev = { + .platform_data = PHY_ID, + }, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .resource = sh_eth0_resources, +}; + +static struct resource sh_eth1_resources[] = { + [0] = { + .start = SH_ETH1_BASE, + .end = SH_ETH1_BASE + 0x1B8, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SH_ETH1_IRQ, + .end = SH_ETH1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_eth1_device = { + .name = "sh-eth", + .id = 1, + .dev = { + .platform_data = PHY_ID, + }, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .resource = sh_eth1_resources, +}; +#endif + +static struct platform_device *se_devices[] __initdata = { + &heartbeat_device, + &cf_ide_device, +#if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\ + defined(CONFIG_CPU_SUBTYPE_SH7712) + &sh_eth0_device, + &sh_eth1_device, +#endif +}; + +static int __init se_devices_setup(void) +{ + return platform_add_devices(se_devices, ARRAY_SIZE(se_devices)); +} +device_initcall(se_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_se __initmv = { + .mv_name = "SolutionEngine", + .mv_setup = smsc_setup, +#if defined(CONFIG_CPU_SH4) + .mv_nr_irqs = 48, +#elif defined(CONFIG_CPU_SUBTYPE_SH7708) + .mv_nr_irqs = 32, +#elif defined(CONFIG_CPU_SUBTYPE_SH7709) + .mv_nr_irqs = 61, +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) + .mv_nr_irqs = 86, +#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) + .mv_nr_irqs = 104, +#endif + + .mv_inb = se_inb, + .mv_inw = se_inw, + .mv_inl = se_inl, + .mv_outb = se_outb, + .mv_outw = se_outw, + .mv_outl = se_outl, + + .mv_inb_p = se_inb_p, + .mv_inw_p = se_inw, + .mv_inl_p = se_inl, + .mv_outb_p = se_outb_p, + .mv_outw_p = se_outw, + .mv_outl_p = se_outl, + + .mv_insb = se_insb, + .mv_insw = se_insw, + .mv_insl = se_insl, + .mv_outsb = se_outsb, + .mv_outsw = se_outsw, + .mv_outsl = se_outsl, + + .mv_init_irq = init_se_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7721/Makefile b/arch/sh/boards/mach-se/7721/Makefile new file mode 100644 index 00000000000..7f09030980b --- /dev/null +++ b/arch/sh/boards/mach-se/7721/Makefile @@ -0,0 +1 @@ +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c new file mode 100644 index 00000000000..c4fdd622bf8 --- /dev/null +++ b/arch/sh/boards/mach-se/7721/irq.c @@ -0,0 +1,45 @@ +/* + * linux/arch/sh/boards/se/7721/irq.c + * + * Copyright (C) 2008 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +enum { + UNUSED = 0, + + /* board specific interrupt sources */ + MRSHPC, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(MRSHPC, MRSHPC_IRQ0), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { FPGA_ILSR6, 0, 8, 4, /* IRLMSK */ + { 0, MRSHPC } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors, + NULL, NULL, prio_registers, NULL); + +/* + * Initialize IRQ setting + */ +void __init init_se7721_IRQ(void) +{ + /* PPCR */ + ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118); + + register_intc_controller(&intc_desc); + intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0); +} diff --git a/arch/sh/boards/mach-se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c new file mode 100644 index 00000000000..1be3e92752f --- /dev/null +++ b/arch/sh/boards/mach-se/7721/setup.c @@ -0,0 +1,99 @@ +/* + * linux/arch/sh/boards/se/7721/setup.c + * + * Copyright (C) 2008 Renesas Solutions Corp. + * + * Hitachi UL SolutionEngine 7721 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include +#include +#include +#include +#include +#include + +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .regsize = 16, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8 , + .flags = IORESOURCE_IO, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 + 8 + 0x206 + 8, + .flags = IORESOURCE_IO, + }, + [2] = { + .start = MRSHPC_IRQ0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct platform_device *se7721_devices[] __initdata = { + &cf_ide_device, + &heartbeat_device +}; + +static int __init se7721_devices_setup(void) +{ + return platform_add_devices(se7721_devices, + ARRAY_SIZE(se7721_devices)); +} +device_initcall(se7721_devices_setup); + +static void __init se7721_setup(char **cmdline_p) +{ + /* for USB */ + ctrl_outw(0x0000, 0xA405010C); /* PGCR */ + ctrl_outw(0x0000, 0xA405010E); /* PHCR */ + ctrl_outw(0x00AA, 0xA4050118); /* PPCR */ + ctrl_outw(0x0000, 0xA4050124); /* PSELA */ +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_se7721 __initmv = { + .mv_name = "Solution Engine 7721", + .mv_setup = se7721_setup, + .mv_nr_irqs = 109, + .mv_init_irq = init_se7721_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7722/Makefile b/arch/sh/boards/mach-se/7722/Makefile new file mode 100644 index 00000000000..8694373389e --- /dev/null +++ b/arch/sh/boards/mach-se/7722/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the HITACHI UL SolutionEngine 7722 specific parts of the kernel +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# + +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c new file mode 100644 index 00000000000..0b03f3f610b --- /dev/null +++ b/arch/sh/boards/mach-se/7722/irq.c @@ -0,0 +1,76 @@ +/* + * linux/arch/sh/boards/se/7722/irq.c + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7722 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +static void disable_se7722_irq(unsigned int irq) +{ + unsigned int bit = irq - SE7722_FPGA_IRQ_BASE; + ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK); +} + +static void enable_se7722_irq(unsigned int irq) +{ + unsigned int bit = irq - SE7722_FPGA_IRQ_BASE; + ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); +} + +static struct irq_chip se7722_irq_chip __read_mostly = { + .name = "SE7722-FPGA", + .mask = disable_se7722_irq, + .unmask = enable_se7722_irq, + .mask_ack = disable_se7722_irq, +}; + +static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) +{ + unsigned short intv = ctrl_inw(IRQ01_STS); + struct irq_desc *ext_desc; + unsigned int ext_irq = SE7722_FPGA_IRQ_BASE; + + intv &= (1 << SE7722_FPGA_IRQ_NR) - 1; + + while (intv) { + if (intv & 1) { + ext_desc = irq_desc + ext_irq; + handle_level_irq(ext_irq, ext_desc); + } + intv >>= 1; + ext_irq++; + } +} + +/* + * Initialize IRQ setting + */ +void __init init_se7722_IRQ(void) +{ + int i; + + ctrl_outw(0, IRQ01_MASK); /* disable all irqs */ + ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ + + for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) + set_irq_chip_and_handler_name(SE7722_FPGA_IRQ_BASE + i, + &se7722_irq_chip, + handle_level_irq, "level"); + + set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux); + set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); + + set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux); + set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); +} diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c new file mode 100644 index 00000000000..6e228ea5978 --- /dev/null +++ b/arch/sh/boards/mach-se/7722/setup.c @@ -0,0 +1,194 @@ +/* + * linux/arch/sh/boards/se/7722/setup.c + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7722 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Heartbeat */ +static struct heartbeat_data heartbeat_data = { + .regsize = 16, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +/* SMC91x */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "smc91x-regs" , + .start = PA_LAN + 0x300, + .end = PA_LAN + 0x300 + 0x10 , + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SMC_IRQ, + .end = SMC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .id = 0, + .dev = { + .dma_mask = NULL, /* don't use dma */ + .coherent_dma_mask = 0xffffffff, + .platform_data = &smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, +}; + +static struct resource cf_ide_resources[] = { + [0] = { + .start = PA_MRSHPC_IO + 0x1f0, + .end = PA_MRSHPC_IO + 0x1f0 + 8 , + .flags = IORESOURCE_IO, + }, + [1] = { + .start = PA_MRSHPC_IO + 0x1f0 + 0x206, + .end = PA_MRSHPC_IO + 0x1f0 +8 + 0x206 + 8, + .flags = IORESOURCE_IO, + }, + [2] = { + .start = MRSHPC_IRQ0, + .end = MRSHPC_IRQ0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_ide_device = { + .name = "pata_platform", + .id = -1, + .num_resources = ARRAY_SIZE(cf_ide_resources), + .resource = cf_ide_resources, +}; + +static struct sh_keysc_info sh_keysc_info = { + .mode = SH_KEYSC_MODE_1, /* KEYOUT0->5, KEYIN0->4 */ + .scan_timing = 3, + .delay = 5, + .keycodes = { /* SW1 -> SW30 */ + KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, + KEY_F, KEY_G, KEY_H, KEY_I, KEY_J, + KEY_K, KEY_L, KEY_M, KEY_N, KEY_O, + KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, + KEY_U, KEY_V, KEY_W, KEY_X, KEY_Y, + KEY_Z, + KEY_HOME, KEY_SLEEP, KEY_WAKEUP, KEY_COFFEE, /* life */ + }, +}; + +static struct resource sh_keysc_resources[] = { + [0] = { + .start = 0x044b0000, + .end = 0x044b000f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 79, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh_keysc_device = { + .name = "sh_keysc", + .num_resources = ARRAY_SIZE(sh_keysc_resources), + .resource = sh_keysc_resources, + .dev = { + .platform_data = &sh_keysc_info, + }, +}; + +static struct platform_device *se7722_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &cf_ide_device, + &sh_keysc_device, +}; + +static int __init se7722_devices_setup(void) +{ + clk_always_enable("mstp214"); /* KEYSC */ + + return platform_add_devices(se7722_devices, + ARRAY_SIZE(se7722_devices)); +} +device_initcall(se7722_devices_setup); + +static void __init se7722_setup(char **cmdline_p) +{ + ctrl_outw(0x010D, FPGA_OUT); /* FPGA */ + + ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ + ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ + + /* LCDC I/O */ + ctrl_outw(0x0020, PORT_PSELD); + + /* SIOF1*/ + ctrl_outw(0x0003, PORT_PSELB); + ctrl_outw(0xe000, PORT_PSELC); + ctrl_outw(0x0000, PORT_PKCR); + + /* LCDC */ + ctrl_outw(0x4020, PORT_PHCR); + ctrl_outw(0x0000, PORT_PLCR); + ctrl_outw(0x0000, PORT_PMCR); + ctrl_outw(0x0002, PORT_PRCR); + ctrl_outw(0x0000, PORT_PXCR); /* LCDC,CS6A */ + + /* KEYSC */ + ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */ + ctrl_outw(0x0000, PORT_PYCR); + ctrl_outw(0x0000, PORT_PZCR); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); + ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_se7722 __initmv = { + .mv_name = "Solution Engine 7722" , + .mv_setup = se7722_setup , + .mv_nr_irqs = SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_NR, + .mv_init_irq = init_se7722_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile new file mode 100644 index 00000000000..dbc29f3a9de --- /dev/null +++ b/arch/sh/boards/mach-se/7751/Makefile @@ -0,0 +1,7 @@ +# +# Makefile for the 7751 SolutionEngine specific parts of the kernel +# + +obj-y := setup.o io.o irq.o + +obj-$(CONFIG_PCI) += pci.o diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c new file mode 100644 index 00000000000..e8d846cec89 --- /dev/null +++ b/arch/sh/boards/mach-se/7751/io.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2001 Ian da Silva, Jeremy Siegel + * Based largely on io_se.c. + * + * I/O routine for Hitachi 7751 SolutionEngine. + * + * Initial version only to support LAN access; some + * placeholder code from io_se.c left in with the + * expectation of later SuperIO and PCMCIA access. + */ +#include +#include +#include +#include +#include +#include + +static inline volatile u16 *port2adr(unsigned int port) +{ + if (port >= 0x2000) + return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); + maybebadio((unsigned long)port); + return (volatile __u16*)port; +} + +/* + * General outline: remap really low stuff [eventually] to SuperIO, + * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) + * is mapped through the PCI IO window. Stuff with high bits (PXSEG) + * should be way beyond the window, and is used w/o translation for + * compatibility. + */ +unsigned char sh7751se_inb(unsigned long port) +{ + if (PXSEG(port)) + return *(volatile unsigned char *)port; + else if (is_pci_ioaddr(port)) + return *(volatile unsigned char *)pci_ioaddr(port); + else + return (*port2adr(port)) & 0xff; +} + +unsigned char sh7751se_inb_p(unsigned long port) +{ + unsigned char v; + + if (PXSEG(port)) + v = *(volatile unsigned char *)port; + else if (is_pci_ioaddr(port)) + v = *(volatile unsigned char *)pci_ioaddr(port); + else + v = (*port2adr(port)) & 0xff; + ctrl_delay(); + return v; +} + +unsigned short sh7751se_inw(unsigned long port) +{ + if (PXSEG(port)) + return *(volatile unsigned short *)port; + else if (is_pci_ioaddr(port)) + return *(volatile unsigned short *)pci_ioaddr(port); + else if (port >= 0x2000) + return *port2adr(port); + else + maybebadio(port); + return 0; +} + +unsigned int sh7751se_inl(unsigned long port) +{ + if (PXSEG(port)) + return *(volatile unsigned long *)port; + else if (is_pci_ioaddr(port)) + return *(volatile unsigned int *)pci_ioaddr(port); + else if (port >= 0x2000) + return *port2adr(port); + else + maybebadio(port); + return 0; +} + +void sh7751se_outb(unsigned char value, unsigned long port) +{ + + if (PXSEG(port)) + *(volatile unsigned char *)port = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; + else + *(port2adr(port)) = value; +} + +void sh7751se_outb_p(unsigned char value, unsigned long port) +{ + if (PXSEG(port)) + *(volatile unsigned char *)port = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; + else + *(port2adr(port)) = value; + ctrl_delay(); +} + +void sh7751se_outw(unsigned short value, unsigned long port) +{ + if (PXSEG(port)) + *(volatile unsigned short *)port = value; + else if (is_pci_ioaddr(port)) + *((unsigned short *)pci_ioaddr(port)) = value; + else if (port >= 0x2000) + *port2adr(port) = value; + else + maybebadio(port); +} + +void sh7751se_outl(unsigned int value, unsigned long port) +{ + if (PXSEG(port)) + *(volatile unsigned long *)port = value; + else if (is_pci_ioaddr(port)) + *((unsigned long*)pci_ioaddr(port)) = value; + else + maybebadio(port); +} + +void sh7751se_insl(unsigned long port, void *addr, unsigned long count) +{ + maybebadio(port); +} + +void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count) +{ + maybebadio(port); +} diff --git a/arch/sh/boards/mach-se/7751/irq.c b/arch/sh/boards/mach-se/7751/irq.c new file mode 100644 index 00000000000..c3d12590e5d --- /dev/null +++ b/arch/sh/boards/mach-se/7751/irq.c @@ -0,0 +1,50 @@ +/* + * linux/arch/sh/boards/se/7751/irq.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ + +#include +#include +#include +#include + +static struct ipr_data ipr_irq_table[] = { + { 13, 3, 3, 2 }, + /* Add additional entries here as drivers are added and tested. */ +}; + +static unsigned long ipr_offsets[] = { + BCR_ILCRA, + BCR_ILCRB, + BCR_ILCRC, + BCR_ILCRD, + BCR_ILCRE, + BCR_ILCRF, + BCR_ILCRG, +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + + .chip = { + .name = "IPR-se7751", + }, +}; + +/* + * Initialize IRQ setting + */ +void __init init_7751se_IRQ(void) +{ + register_ipr_controller(&ipr_irq_desc); +} diff --git a/arch/sh/boards/mach-se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c new file mode 100644 index 00000000000..203b2923fe7 --- /dev/null +++ b/arch/sh/boards/mach-se/7751/pci.c @@ -0,0 +1,147 @@ +/* + * linux/arch/sh/boards/se/7751/pci.c + * + * Author: Ian DaSilva (idasilva@mvista.com) + * + * Highly leveraged from pci-bigsur.c, written by Dustin McIntire. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01) + */ + +#include +#include +#include +#include +#include + +#include +#include "../../../drivers/pci/pci-sh7751.h" + +#define PCIMCR_MRSET_OFF 0xBFFFFFFF +#define PCIMCR_RFSH_OFF 0xFFFFFFFB + +/* + * Only long word accesses of the PCIC's internal local registers and the + * configuration registers from the CPU is supported. + */ +#define PCIC_WRITE(x,v) writel((v), PCI_REG(x)) +#define PCIC_READ(x) readl(PCI_REG(x)) + +/* + * Description: This function sets up and initializes the pcic, sets + * up the BARS, maps the DRAM into the address space etc, etc. + */ +int __init pcibios_init_platform(void) +{ + unsigned long bcr1, wcr1, wcr2, wcr3, mcr; + unsigned short bcr2; + + /* + * Initialize the slave bus controller on the pcic. The values used + * here should not be hardcoded, but they should be taken from the bsc + * on the processor, to make this function as generic as possible. + * (i.e. Another sbc may usr different SDRAM timing settings -- in order + * for the pcic to work, its settings need to be exactly the same.) + */ + bcr1 = (*(volatile unsigned long*)(SH7751_BCR1)); + bcr2 = (*(volatile unsigned short*)(SH7751_BCR2)); + wcr1 = (*(volatile unsigned long*)(SH7751_WCR1)); + wcr2 = (*(volatile unsigned long*)(SH7751_WCR2)); + wcr3 = (*(volatile unsigned long*)(SH7751_WCR3)); + mcr = (*(volatile unsigned long*)(SH7751_MCR)); + + bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */ + (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1; + + bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ + PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */ + PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */ + PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */ + PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */ + PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */ + mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; + PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ + + + /* Enable all interrupts, so we know what to fix */ + PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff); + PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f); + + /* Set up standard PCI config registers */ + PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */ + PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */ + PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */ + PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */ + PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */ + PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */ + PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */ + PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */ + PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */ + PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */ + + /* Now turn it on... */ + PCIC_WRITE(SH7751_PCICR, 0xa5000001); + + /* + * Set PCIMBR and PCIIOBR here, assuming a single window + * (16M MEM, 256K IO) is enough. If a larger space is + * needed, the readx/writex and inx/outx functions will + * have to do more (e.g. setting registers for each call). + */ + + /* + * Set the MBR so PCI address is one-to-one with window, + * meaning all calls go straight through... use BUG_ON to + * catch erroneous assumption. + */ + BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE); + + PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM); + + /* Set IOBR for window containing area specified in pci.h */ + PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK)); + + /* All done, may as well say so... */ + printk("SH7751 PCI: Finished initialization of the PCI controller\n"); + + return 1; +} + +int __init pcibios_map_platform_irq(u8 slot, u8 pin) +{ + switch (slot) { + case 0: return 13; + case 1: return 13; /* AMD Ethernet controller */ + case 2: return -1; + case 3: return -1; + case 4: return -1; + default: + printk("PCI: Bad IRQ mapping request for slot %d\n", slot); + return -1; + } +} + +static struct resource sh7751_io_resource = { + .name = "SH7751 IO", + .start = SH7751_PCI_IO_BASE, + .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO +}; + +static struct resource sh7751_mem_resource = { + .name = "SH7751 mem", + .start = SH7751_PCI_MEMORY_BASE, + .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +extern struct pci_ops sh7751_pci_ops; + +struct pci_channel board_pci_channels[] = { + { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { NULL, NULL, NULL, 0, 0 }, +}; + diff --git a/arch/sh/boards/mach-se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c new file mode 100644 index 00000000000..deefbfd9259 --- /dev/null +++ b/arch/sh/boards/mach-se/7751/setup.c @@ -0,0 +1,78 @@ +/* + * linux/arch/sh/boards/se/7751/setup.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ +#include +#include +#include +#include +#include +#include + +static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct platform_device *se7751_devices[] __initdata = { + &heartbeat_device, +}; + +static int __init se7751_devices_setup(void) +{ + return platform_add_devices(se7751_devices, ARRAY_SIZE(se7751_devices)); +} +__initcall(se7751_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_7751se __initmv = { + .mv_name = "7751 SolutionEngine", + .mv_nr_irqs = 72, + + .mv_inb = sh7751se_inb, + .mv_inw = sh7751se_inw, + .mv_inl = sh7751se_inl, + .mv_outb = sh7751se_outb, + .mv_outw = sh7751se_outw, + .mv_outl = sh7751se_outl, + + .mv_inb_p = sh7751se_inb_p, + .mv_inw_p = sh7751se_inw, + .mv_inl_p = sh7751se_inl, + .mv_outb_p = sh7751se_outb_p, + .mv_outw_p = sh7751se_outw, + .mv_outl_p = sh7751se_outl, + + .mv_insl = sh7751se_insl, + .mv_outsl = sh7751se_outsl, + + .mv_init_irq = init_7751se_IRQ, +}; diff --git a/arch/sh/boards/mach-se/7780/Makefile b/arch/sh/boards/mach-se/7780/Makefile new file mode 100644 index 00000000000..6b88adae3ec --- /dev/null +++ b/arch/sh/boards/mach-se/7780/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the HITACHI UL SolutionEngine 7780 specific parts of the kernel +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# + +obj-y := setup.o irq.o diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c new file mode 100644 index 00000000000..6bd70da6bb4 --- /dev/null +++ b/arch/sh/boards/mach-se/7780/irq.c @@ -0,0 +1,46 @@ +/* + * linux/arch/sh/boards/se/7780/irq.c + * + * Copyright (C) 2006,2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7780 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +/* + * Initialize IRQ setting + */ +void __init init_se7780_IRQ(void) +{ + /* enable all interrupt at FPGA */ + ctrl_outw(0, FPGA_INTMSK1); + /* mask SM501 interrupt */ + ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); + /* enable all interrupt at FPGA */ + ctrl_outw(0, FPGA_INTMSK2); + + /* set FPGA INTSEL register */ + /* FPGA + 0x06 */ + ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) | + (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1); + + /* FPGA + 0x08 */ + ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | + (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) | + (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) | + (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2); + + /* FPGA + 0x0A */ + ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); + + plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ +} diff --git a/arch/sh/boards/mach-se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c new file mode 100644 index 00000000000..0f08ab3b2be --- /dev/null +++ b/arch/sh/boards/mach-se/7780/setup.c @@ -0,0 +1,124 @@ +/* + * linux/arch/sh/boards/se/7780/setup.c + * + * Copyright (C) 2006,2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7780 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include + +/* Heartbeat */ +static struct heartbeat_data heartbeat_data = { + .regsize = 16, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +/* SMC91x */ +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "smc91x-regs" , + .start = PA_LAN + 0x300, + .end = PA_LAN + 0x300 + 0x10 , + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SMC_IRQ, + .end = SMC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .id = 0, + .dev = { + .dma_mask = NULL, /* don't use dma */ + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, +}; + +static struct platform_device *se7780_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, +}; + +static int __init se7780_devices_setup(void) +{ + return platform_add_devices(se7780_devices, + ARRAY_SIZE(se7780_devices)); +} +device_initcall(se7780_devices_setup); + +#define GPIO_PHCR 0xFFEA000E +#define GPIO_PMSELR 0xFFEA0080 +#define GPIO_PECR 0xFFEA0008 + +static void __init se7780_setup(char **cmdline_p) +{ + /* "SH-Linux" on LED Display */ + ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); + ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); + ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); + ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); + ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); + ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); + ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); + ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); + + printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n"); + + /* + * PCI REQ/GNT setting + * REQ0/GNT0 -> USB + * REQ1/GNT1 -> PC Card + * REQ2/GNT2 -> Serial ATA + * REQ3/GNT3 -> PCI slot + */ + ctrl_outw(0x0213, FPGA_REQSEL); + + /* GPIO setting */ + ctrl_outw(0x0000, GPIO_PECR); + ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR); + ctrl_outw(0x0c00, GPIO_PMSELR); + + /* iVDR Power ON */ + ctrl_outw(0x0001, FPGA_IVDRPW); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_se7780 __initmv = { + .mv_name = "Solution Engine 7780" , + .mv_setup = se7780_setup , + .mv_nr_irqs = 111 , + .mv_init_irq = init_se7780_IRQ, +}; -- cgit v1.2.3-70-g09d2 From 939a24a6df24649cea9fd0ff54fe71ee0dc1d61e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 29 Jul 2008 21:41:37 +0900 Subject: sh: Move out the solution engine headers to arch/sh/include/mach-se/ Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 247 +--------------------------------- arch/sh/Makefile | 15 +-- arch/sh/boards/Kconfig | 245 +++++++++++++++++++++++++++++++++ arch/sh/boards/mach-se/7206/io.c | 2 +- arch/sh/boards/mach-se/7206/irq.c | 2 +- arch/sh/boards/mach-se/7206/setup.c | 2 +- arch/sh/boards/mach-se/7343/irq.c | 6 +- arch/sh/boards/mach-se/7343/setup.c | 4 +- arch/sh/boards/mach-se/770x/io.c | 2 +- arch/sh/boards/mach-se/770x/irq.c | 2 +- arch/sh/boards/mach-se/770x/setup.c | 2 +- arch/sh/boards/mach-se/7721/irq.c | 2 +- arch/sh/boards/mach-se/7721/setup.c | 2 +- arch/sh/boards/mach-se/7722/irq.c | 2 +- arch/sh/boards/mach-se/7722/setup.c | 2 +- arch/sh/boards/mach-se/7751/io.c | 2 +- arch/sh/boards/mach-se/7751/irq.c | 2 +- arch/sh/boards/mach-se/7751/setup.c | 2 +- arch/sh/boards/mach-se/7780/irq.c | 2 +- arch/sh/boards/mach-se/7780/setup.c | 2 +- arch/sh/boards/mach-se/Makefile | 8 ++ arch/sh/drivers/pci/ops-se7780.c | 2 +- arch/sh/include/asm/se.h | 99 -------------- arch/sh/include/asm/se7206.h | 13 -- arch/sh/include/asm/se7343.h | 149 -------------------- arch/sh/include/asm/se7721.h | 70 ---------- arch/sh/include/asm/se7722.h | 112 --------------- arch/sh/include/asm/se7751.h | 73 ---------- arch/sh/include/asm/se7780.h | 108 --------------- arch/sh/include/mach-se/mach/se.h | 99 ++++++++++++++ arch/sh/include/mach-se/mach/se7206.h | 13 ++ arch/sh/include/mach-se/mach/se7343.h | 149 ++++++++++++++++++++ arch/sh/include/mach-se/mach/se7721.h | 70 ++++++++++ arch/sh/include/mach-se/mach/se7722.h | 112 +++++++++++++++ arch/sh/include/mach-se/mach/se7751.h | 73 ++++++++++ arch/sh/include/mach-se/mach/se7780.h | 108 +++++++++++++++ arch/sh/kernel/cf-enabler.c | 6 +- 37 files changed, 906 insertions(+), 905 deletions(-) create mode 100644 arch/sh/boards/Kconfig create mode 100644 arch/sh/boards/mach-se/Makefile delete mode 100644 arch/sh/include/asm/se.h delete mode 100644 arch/sh/include/asm/se7206.h delete mode 100644 arch/sh/include/asm/se7343.h delete mode 100644 arch/sh/include/asm/se7721.h delete mode 100644 arch/sh/include/asm/se7722.h delete mode 100644 arch/sh/include/asm/se7751.h delete mode 100644 arch/sh/include/asm/se7780.h create mode 100644 arch/sh/include/mach-se/mach/se.h create mode 100644 arch/sh/include/mach-se/mach/se7206.h create mode 100644 arch/sh/include/mach-se/mach/se7343.h create mode 100644 arch/sh/include/mach-se/mach/se7721.h create mode 100644 arch/sh/include/mach-se/mach/se7722.h create mode 100644 arch/sh/include/mach-se/mach/se7751.h create mode 100644 arch/sh/include/mach-se/mach/se7780.h (limited to 'arch/sh/boards/mach-se') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 83d170ccb0f..2b742206ba0 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -352,253 +352,10 @@ config CPU_SUBTYPE_SH5_103 endchoice source "arch/sh/mm/Kconfig" + source "arch/sh/Kconfig.cpu" -menu "Board support" - -config SOLUTION_ENGINE - bool - -config SH_SOLUTION_ENGINE - bool "SolutionEngine" - select SOLUTION_ENGINE - select CPU_HAS_IPR_IRQ - depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ - CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ - CPU_SUBTYPE_SH7750R - help - Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, - SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. - -config SH_7206_SOLUTION_ENGINE - bool "SolutionEngine7206" - select SOLUTION_ENGINE - depends on CPU_SUBTYPE_SH7206 - help - Select 7206 SolutionEngine if configuring for a Hitachi SH7206 - evaluation board. - -config SH_7619_SOLUTION_ENGINE - bool "SolutionEngine7619" - select SOLUTION_ENGINE - depends on CPU_SUBTYPE_SH7619 - help - Select 7619 SolutionEngine if configuring for a Hitachi SH7619 - evaluation board. - -config SH_7721_SOLUTION_ENGINE - bool "SolutionEngine7721" - select SOLUTION_ENGINE - depends on CPU_SUBTYPE_SH7721 - help - Select 7721 SolutionEngine if configuring for a Hitachi SH7721 - evaluation board. - -config SH_7722_SOLUTION_ENGINE - bool "SolutionEngine7722" - select SOLUTION_ENGINE - depends on CPU_SUBTYPE_SH7722 - help - Select 7722 SolutionEngine if configuring for a Hitachi SH772 - evaluation board. - -config SH_7751_SOLUTION_ENGINE - bool "SolutionEngine7751" - select SOLUTION_ENGINE - select CPU_HAS_IPR_IRQ - depends on CPU_SUBTYPE_SH7751 - help - Select 7751 SolutionEngine if configuring for a Hitachi SH7751 - evaluation board. - -config SH_7780_SOLUTION_ENGINE - bool "SolutionEngine7780" - select SOLUTION_ENGINE - select SYS_SUPPORTS_PCI - depends on CPU_SUBTYPE_SH7780 - help - Select 7780 SolutionEngine if configuring for a Renesas SH7780 - evaluation board. - -config SH_7343_SOLUTION_ENGINE - bool "SolutionEngine7343" - select SOLUTION_ENGINE - depends on CPU_SUBTYPE_SH7343 - help - Select 7343 SolutionEngine if configuring for a Hitachi - SH7343 (SH-Mobile 3AS) evaluation board. - -config SH_7751_SYSTEMH - bool "SystemH7751R" - depends on CPU_SUBTYPE_SH7751R - help - Select SystemH if you are configuring for a Renesas SystemH - 7751R evaluation board. - -config SH_HP6XX - bool "HP6XX" - select SYS_SUPPORTS_APM_EMULATION - select HD6446X_SERIES - depends on CPU_SUBTYPE_SH7709 - help - Select HP6XX if configuring for a HP jornada HP6xx. - More information (hardware only) at - . - -config SH_DREAMCAST - bool "Dreamcast" - select SYS_SUPPORTS_PCI - depends on CPU_SUBTYPE_SH7091 - help - Select Dreamcast if configuring for a SEGA Dreamcast. - More information at - -config SH_SH03 - bool "Interface CTP/PCI-SH03" - depends on CPU_SUBTYPE_SH7751 - select CPU_HAS_IPR_IRQ - select SYS_SUPPORTS_PCI - help - CTP/PCI-SH03 is a CPU module computer that is produced - by Interface Corporation. - More information at - -config SH_SECUREEDGE5410 - bool "SecureEdge5410" - depends on CPU_SUBTYPE_SH7751R - select CPU_HAS_IPR_IRQ - select SYS_SUPPORTS_PCI - help - Select SecureEdge5410 if configuring for a SnapGear SH board. - This includes both the OEM SecureEdge products as well as the - SME product line. - -config SH_RTS7751R2D - bool "RTS7751R2D" - depends on CPU_SUBTYPE_SH7751R - select SYS_SUPPORTS_PCI - select IO_TRAPPED - help - Select RTS7751R2D if configuring for a Renesas Technology - Sales SH-Graphics board. - -config SH_RSK7203 - bool "RSK7203" - depends on CPU_SUBTYPE_SH7203 - -config SH_SDK7780 - bool "SDK7780R3" - depends on CPU_SUBTYPE_SH7780 - select SYS_SUPPORTS_PCI - help - Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 - evaluation board. - -config SH_HIGHLANDER - bool "Highlander" - depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 - select SYS_SUPPORTS_PCI - select IO_TRAPPED - -config SH_SH7785LCR - bool "SH7785LCR" - depends on CPU_SUBTYPE_SH7785 - select SYS_SUPPORTS_PCI - select IO_TRAPPED - -config SH_SH7785LCR_29BIT_PHYSMAPS - bool "SH7785LCR 29bit physmaps" - depends on SH_SH7785LCR - default y - help - This board has 2 physical memory maps. It can be changed with - DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, - you can access all on-board device in 29bit address mode. - -config SH_MIGOR - bool "Migo-R" - depends on CPU_SUBTYPE_SH7722 - help - Select Migo-R if configuring for the SH7722 Migo-R platform - by Renesas System Solutions Asia Pte. Ltd. - -config SH_AP325RXA - bool "AP-325RXA" - depends on CPU_SUBTYPE_SH7723 - help - Renesas "AP-325RXA" support. - Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" - -config SH_SH7763RDP - bool "SH7763RDP" - depends on CPU_SUBTYPE_SH7763 - help - Select SH7763RDP if configuring for a Renesas SH7763 - evaluation board. - -config SH_EDOSK7705 - bool "EDOSK7705" - depends on CPU_SUBTYPE_SH7705 - -config SH_SH4202_MICRODEV - bool "SH4-202 MicroDev" - depends on CPU_SUBTYPE_SH4_202 - help - Select SH4-202 MicroDev if configuring for a SuperH MicroDev board - with an SH4-202 CPU. - -config SH_LANDISK - bool "LANDISK" - depends on CPU_SUBTYPE_SH7751R - select SYS_SUPPORTS_PCI - help - I-O DATA DEVICE, INC. "LANDISK Series" support. - -config SH_TITAN - bool "TITAN" - depends on CPU_SUBTYPE_SH7751R - select CPU_HAS_IPR_IRQ - select SYS_SUPPORTS_PCI - help - Select Titan if you are configuring for a Nimble Microsystems - NetEngine NP51R. - -config SH_SHMIN - bool "SHMIN" - depends on CPU_SUBTYPE_SH7706 - select CPU_HAS_IPR_IRQ - help - Select SHMIN if configuring for the SHMIN board. - -config SH_LBOX_RE2 - bool "L-BOX RE2" - depends on CPU_SUBTYPE_SH7751R - select SYS_SUPPORTS_PCI - help - Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. - -config SH_X3PROTO - bool "SH-X3 Prototype board" - depends on CPU_SUBTYPE_SHX3 - -config SH_MAGIC_PANEL_R2 - bool "Magic Panel R2" - depends on CPU_SUBTYPE_SH7720 - help - Select Magic Panel R2 if configuring for Magic Panel R2. - -config SH_CAYMAN - bool "Hitachi Cayman" - depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 - select SYS_SUPPORTS_PCI - -endmenu - -source "arch/sh/boards/mach-r2d/Kconfig" -source "arch/sh/boards/mach-highlander/Kconfig" -source "arch/sh/boards/mach-sdk7780/Kconfig" -source "arch/sh/boards/mach-migor/Kconfig" -source "arch/sh/boards/mach-magicpanelr2/Kconfig" +source "arch/sh/boards/Kconfig" menu "Timer and clock configuration" diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 47bbfd8ae66..fb3b65ed291 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -101,15 +101,8 @@ LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) core-y += arch/sh/kernel/ arch/sh/mm/ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ -# Boards -machdir-$(CONFIG_SH_SOLUTION_ENGINE) += mach-se/770x -machdir-$(CONFIG_SH_7206_SOLUTION_ENGINE) += mach-se/7206 -machdir-$(CONFIG_SH_7619_SOLUTION_ENGINE) += mach-se/7619 -machdir-$(CONFIG_SH_7722_SOLUTION_ENGINE) += mach-se/7722 -machdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) += mach-se/7751 -machdir-$(CONFIG_SH_7780_SOLUTION_ENGINE) += mach-se/7780 -machdir-$(CONFIG_SH_7343_SOLUTION_ENGINE) += mach-se/7343 -machdir-$(CONFIG_SH_7721_SOLUTION_ENGINE) += mach-se/7721 +# Boards and Mach groups +machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast machdir-$(CONFIG_SH_SH03) += mach-sh03 @@ -133,8 +126,6 @@ machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2 machdir-$(CONFIG_SH_MAGIC_PANEL_R2) += mach-magicpanelr2 machdir-$(CONFIG_SH_CAYMAN) += mach-cayman -incdir-y := $(notdir $(machdir-y)) - ifneq ($(machdir-y),) core-y += $(addprefix arch/sh/boards/, \ $(filter-out ., $(patsubst %,%/,$(machdir-y)))) @@ -159,7 +150,7 @@ drivers-$(CONFIG_OPROFILE) += arch/sh/oprofile/ boot := arch/sh/boot cflags-y += -Iarch/sh/include/$(cpuincdir-y) -cflags-y += $(foreach d, $(incdir-y), -Iarch/sh/include/mach-$(d)) +cflags-y += $(foreach d, $(machdir-y), -Iarch/sh/include/$(d)) KBUILD_CFLAGS += -pipe $(cflags-y) KBUILD_CPPFLAGS += $(cflags-y) diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig new file mode 100644 index 00000000000..324c25ac95c --- /dev/null +++ b/arch/sh/boards/Kconfig @@ -0,0 +1,245 @@ +menu "Board support" + +config SOLUTION_ENGINE + bool + +config SH_SOLUTION_ENGINE + bool "SolutionEngine" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ + CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R + help + Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, + SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. + +config SH_7206_SOLUTION_ENGINE + bool "SolutionEngine7206" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7206 + help + Select 7206 SolutionEngine if configuring for a Hitachi SH7206 + evaluation board. + +config SH_7619_SOLUTION_ENGINE + bool "SolutionEngine7619" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7619 + help + Select 7619 SolutionEngine if configuring for a Hitachi SH7619 + evaluation board. + +config SH_7721_SOLUTION_ENGINE + bool "SolutionEngine7721" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7721 + help + Select 7721 SolutionEngine if configuring for a Hitachi SH7721 + evaluation board. + +config SH_7722_SOLUTION_ENGINE + bool "SolutionEngine7722" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7722 + help + Select 7722 SolutionEngine if configuring for a Hitachi SH772 + evaluation board. + +config SH_7751_SOLUTION_ENGINE + bool "SolutionEngine7751" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7751 + help + Select 7751 SolutionEngine if configuring for a Hitachi SH7751 + evaluation board. + +config SH_7780_SOLUTION_ENGINE + bool "SolutionEngine7780" + select SOLUTION_ENGINE + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7780 + help + Select 7780 SolutionEngine if configuring for a Renesas SH7780 + evaluation board. + +config SH_7343_SOLUTION_ENGINE + bool "SolutionEngine7343" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7343 + help + Select 7343 SolutionEngine if configuring for a Hitachi + SH7343 (SH-Mobile 3AS) evaluation board. + +config SH_7751_SYSTEMH + bool "SystemH7751R" + depends on CPU_SUBTYPE_SH7751R + help + Select SystemH if you are configuring for a Renesas SystemH + 7751R evaluation board. + +config SH_HP6XX + bool "HP6XX" + select SYS_SUPPORTS_APM_EMULATION + select HD6446X_SERIES + depends on CPU_SUBTYPE_SH7709 + help + Select HP6XX if configuring for a HP jornada HP6xx. + More information (hardware only) at + . + +config SH_DREAMCAST + bool "Dreamcast" + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7091 + help + Select Dreamcast if configuring for a SEGA Dreamcast. + More information at + +config SH_SH03 + bool "Interface CTP/PCI-SH03" + depends on CPU_SUBTYPE_SH7751 + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + CTP/PCI-SH03 is a CPU module computer that is produced + by Interface Corporation. + More information at + +config SH_SECUREEDGE5410 + bool "SecureEdge5410" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select SecureEdge5410 if configuring for a SnapGear SH board. + This includes both the OEM SecureEdge products as well as the + SME product line. + +config SH_RTS7751R2D + bool "RTS7751R2D" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + select IO_TRAPPED + help + Select RTS7751R2D if configuring for a Renesas Technology + Sales SH-Graphics board. + +config SH_RSK7203 + bool "RSK7203" + depends on CPU_SUBTYPE_SH7203 + +config SH_SDK7780 + bool "SDK7780R3" + depends on CPU_SUBTYPE_SH7780 + select SYS_SUPPORTS_PCI + help + Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 + evaluation board. + +config SH_HIGHLANDER + bool "Highlander" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + select IO_TRAPPED + +config SH_SH7785LCR + bool "SH7785LCR" + depends on CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + select IO_TRAPPED + +config SH_SH7785LCR_29BIT_PHYSMAPS + bool "SH7785LCR 29bit physmaps" + depends on SH_SH7785LCR + default y + help + This board has 2 physical memory maps. It can be changed with + DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, + you can access all on-board device in 29bit address mode. + +config SH_MIGOR + bool "Migo-R" + depends on CPU_SUBTYPE_SH7722 + help + Select Migo-R if configuring for the SH7722 Migo-R platform + by Renesas System Solutions Asia Pte. Ltd. + +config SH_AP325RXA + bool "AP-325RXA" + depends on CPU_SUBTYPE_SH7723 + help + Renesas "AP-325RXA" support. + Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" + +config SH_SH7763RDP + bool "SH7763RDP" + depends on CPU_SUBTYPE_SH7763 + help + Select SH7763RDP if configuring for a Renesas SH7763 + evaluation board. + +config SH_EDOSK7705 + bool "EDOSK7705" + depends on CPU_SUBTYPE_SH7705 + +config SH_SH4202_MICRODEV + bool "SH4-202 MicroDev" + depends on CPU_SUBTYPE_SH4_202 + help + Select SH4-202 MicroDev if configuring for a SuperH MicroDev board + with an SH4-202 CPU. + +config SH_LANDISK + bool "LANDISK" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + I-O DATA DEVICE, INC. "LANDISK Series" support. + +config SH_TITAN + bool "TITAN" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select Titan if you are configuring for a Nimble Microsystems + NetEngine NP51R. + +config SH_SHMIN + bool "SHMIN" + depends on CPU_SUBTYPE_SH7706 + select CPU_HAS_IPR_IRQ + help + Select SHMIN if configuring for the SHMIN board. + +config SH_LBOX_RE2 + bool "L-BOX RE2" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. + +config SH_X3PROTO + bool "SH-X3 Prototype board" + depends on CPU_SUBTYPE_SHX3 + +config SH_MAGIC_PANEL_R2 + bool "Magic Panel R2" + depends on CPU_SUBTYPE_SH7720 + help + Select Magic Panel R2 if configuring for Magic Panel R2. + +config SH_CAYMAN + bool "Hitachi Cayman" + depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 + select SYS_SUPPORTS_PCI + +endmenu + +source "arch/sh/boards/mach-r2d/Kconfig" +source "arch/sh/boards/mach-highlander/Kconfig" +source "arch/sh/boards/mach-sdk7780/Kconfig" +source "arch/sh/boards/mach-migor/Kconfig" +source "arch/sh/boards/mach-magicpanelr2/Kconfig" diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c index 1308e618e04..9c3a33210d6 100644 --- a/arch/sh/boards/mach-se/7206/io.c +++ b/arch/sh/boards/mach-se/7206/io.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include static inline void delay(void) diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c index 9d5bfc77d0d..aef7f052851 100644 --- a/arch/sh/boards/mach-se/7206/irq.c +++ b/arch/sh/boards/mach-se/7206/irq.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #define INTSTS0 0x31800000 #define INTSTS1 0x31800002 diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c index 4fe84cc0840..f5466384972 100644 --- a/arch/sh/boards/mach-se/7206/setup.c +++ b/arch/sh/boards/mach-se/7206/setup.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c index 1112e86aa93..5d96e2eef82 100644 --- a/arch/sh/boards/mach-se/7343/irq.c +++ b/arch/sh/boards/mach-se/7343/irq.c @@ -13,9 +13,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include static void disable_se7343_irq(unsigned int irq) { diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c index 59dc92e20f6..486f40bf927 100644 --- a/arch/sh/boards/mach-se/7343/setup.c +++ b/arch/sh/boards/mach-se/7343/setup.c @@ -1,8 +1,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/arch/sh/boards/mach-se/770x/io.c b/arch/sh/boards/mach-se/770x/io.c index b1ec085b867..28833c8786e 100644 --- a/arch/sh/boards/mach-se/770x/io.c +++ b/arch/sh/boards/mach-se/770x/io.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include /* MS7750 requires special versions of in*, out* routines, since PC-like io ports are located at upper half byte of 16-bit word which diff --git a/arch/sh/boards/mach-se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c index cdb0807928a..ec1fea571b5 100644 --- a/arch/sh/boards/mach-se/770x/irq.c +++ b/arch/sh/boards/mach-se/770x/irq.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include static struct ipr_data ipr_irq_table[] = { /* diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c index 6c64d774da3..9123d9687bf 100644 --- a/arch/sh/boards/mach-se/770x/setup.c +++ b/arch/sh/boards/mach-se/770x/setup.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/sh/boards/mach-se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c index c4fdd622bf8..b417acc4dad 100644 --- a/arch/sh/boards/mach-se/7721/irq.c +++ b/arch/sh/boards/mach-se/7721/irq.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include enum { UNUSED = 0, diff --git a/arch/sh/boards/mach-se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c index 1be3e92752f..d3fc80ff4d8 100644 --- a/arch/sh/boards/mach-se/7721/setup.c +++ b/arch/sh/boards/mach-se/7721/setup.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c index 0b03f3f610b..02d21a3e2a8 100644 --- a/arch/sh/boards/mach-se/7722/irq.c +++ b/arch/sh/boards/mach-se/7722/irq.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include static void disable_se7722_irq(unsigned int irq) { diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c index 6e228ea5978..fe6f96517e1 100644 --- a/arch/sh/boards/mach-se/7722/setup.c +++ b/arch/sh/boards/mach-se/7722/setup.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c index e8d846cec89..6287ae57031 100644 --- a/arch/sh/boards/mach-se/7751/io.c +++ b/arch/sh/boards/mach-se/7751/io.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include static inline volatile u16 *port2adr(unsigned int port) diff --git a/arch/sh/boards/mach-se/7751/irq.c b/arch/sh/boards/mach-se/7751/irq.c index c3d12590e5d..5c9847ea1e7 100644 --- a/arch/sh/boards/mach-se/7751/irq.c +++ b/arch/sh/boards/mach-se/7751/irq.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include static struct ipr_data ipr_irq_table[] = { { 13, 3, 3, 2 }, diff --git a/arch/sh/boards/mach-se/7751/setup.c b/arch/sh/boards/mach-se/7751/setup.c index deefbfd9259..50572512e3e 100644 --- a/arch/sh/boards/mach-se/7751/setup.c +++ b/arch/sh/boards/mach-se/7751/setup.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c index 6bd70da6bb4..66ad292c9fc 100644 --- a/arch/sh/boards/mach-se/7780/irq.c +++ b/arch/sh/boards/mach-se/7780/irq.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include /* * Initialize IRQ setting diff --git a/arch/sh/boards/mach-se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c index 0f08ab3b2be..1d3a867e94e 100644 --- a/arch/sh/boards/mach-se/7780/setup.c +++ b/arch/sh/boards/mach-se/7780/setup.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile new file mode 100644 index 00000000000..ad2b38ef65d --- /dev/null +++ b/arch/sh/boards/mach-se/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_SH_SOLUTION_ENGINE) += 770x/ +obj-$(CONFIG_SH_7206_SOLUTION_ENGINE) += 7206/ +obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += 7619/ +obj-$(CONFIG_SH_7722_SOLUTION_ENGINE) += 7722/ +obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/ +obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ +obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/ +obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/ diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c index bbdb48c124a..3145c62484d 100644 --- a/arch/sh/drivers/pci/ops-se7780.c +++ b/arch/sh/drivers/pci/ops-se7780.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include "pci-sh4.h" diff --git a/arch/sh/include/asm/se.h b/arch/sh/include/asm/se.h deleted file mode 100644 index eb23000e1bb..00000000000 --- a/arch/sh/include/asm/se.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE_H -#define __ASM_SH_HITACHI_SE_H - -/* - * linux/include/asm-sh/hitachi_se.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SolutionEngine support - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_83902 0xb0000000 /* DP83902A */ -#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ -#define PA_83902_RST 0xb0080000 /* DP83902A reset port */ - -#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ -#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ -#define PA_LED 0xb0c00000 /* LED */ -#if defined(CONFIG_CPU_SUBTYPE_SH7705) -#define PA_BCR 0xb0e00000 -#else -#define PA_BCR 0xb1400000 /* FPGA */ -#endif - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#if defined(CONFIG_CPU_SUBTYPE_SH7705) -#define IRQ_STNIC 12 -#define IRQ_CFCARD 14 -#else -#define IRQ_STNIC 10 -#define IRQ_CFCARD 7 -#endif - -/* SH Ether support (SH7710/SH7712) */ -/* Base address */ -#define SH_ETH0_BASE 0xA7000000 -#define SH_ETH1_BASE 0xA7000400 -/* PHY ID */ -#if defined(CONFIG_CPU_SUBTYPE_SH7710) -# define PHY_ID 0x00 -#elif defined(CONFIG_CPU_SUBTYPE_SH7712) -# define PHY_ID 0x01 -#endif -/* Ether IRQ */ -#define SH_ETH0_IRQ 80 -#define SH_ETH1_IRQ 81 -#define SH_TSU_IRQ 82 - -void init_se_IRQ(void); - -#define __IO_PREFIX se -#include - -#endif /* __ASM_SH_HITACHI_SE_H */ diff --git a/arch/sh/include/asm/se7206.h b/arch/sh/include/asm/se7206.h deleted file mode 100644 index 698eb80389a..00000000000 --- a/arch/sh/include/asm/se7206.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ASM_SH_SE7206_H -#define __ASM_SH_SE7206_H - -#define PA_SMSC 0x30000000 -#define PA_MRSHPC 0x34000000 -#define PA_LED 0x31400000 - -void init_se7206_IRQ(void); - -#define __IO_PREFIX se7206 -#include - -#endif /* __ASM_SH_SE7206_H */ diff --git a/arch/sh/include/asm/se7343.h b/arch/sh/include/asm/se7343.h deleted file mode 100644 index 98458460e63..00000000000 --- a/arch/sh/include/asm/se7343.h +++ /dev/null @@ -1,149 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE7343_H -#define __ASM_SH_HITACHI_SE7343_H - -/* - * include/asm-sh/se/se7343.h - * - * Copyright (C) 2003 Takashi Kusuda - * - * SH-Mobile SolutionEngine 7343 support - */ - -/* Box specific addresses. */ - -/* Area 0 */ -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ -#define PA_FROM 0x00400000 /* Flash ROM */ -#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ -#define PA_SRAM 0x00800000 /* SRAM */ -#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ -/* Area 1 */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -/* Area 2 */ -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -/* Area 3 */ -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 -/* Area 4 */ -#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) -#define PA_LED 0xb0C00000 /* LED */ -#define LED_SHIFT 0 -#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ -#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */ -#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */ -#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */ -/* Area 5 */ -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -/* Area 6 */ -#define PA_LCD1 0xb8000000 -#define PA_LCD2 0xb8800000 - -#define PORT_PACR 0xA4050100 -#define PORT_PBCR 0xA4050102 -#define PORT_PCCR 0xA4050104 -#define PORT_PDCR 0xA4050106 -#define PORT_PECR 0xA4050108 -#define PORT_PFCR 0xA405010A -#define PORT_PGCR 0xA405010C -#define PORT_PHCR 0xA405010E -#define PORT_PJCR 0xA4050110 -#define PORT_PKCR 0xA4050112 -#define PORT_PLCR 0xA4050114 -#define PORT_PMCR 0xA4050116 -#define PORT_PNCR 0xA4050118 -#define PORT_PQCR 0xA405011A -#define PORT_PRCR 0xA405011C -#define PORT_PSCR 0xA405011E -#define PORT_PTCR 0xA4050140 -#define PORT_PUCR 0xA4050142 -#define PORT_PVCR 0xA4050144 -#define PORT_PWCR 0xA4050146 -#define PORT_PYCR 0xA4050148 -#define PORT_PZCR 0xA405014A - -#define PORT_PSELA 0xA405014C -#define PORT_PSELB 0xA405014E -#define PORT_PSELC 0xA4050150 -#define PORT_PSELD 0xA4050152 -#define PORT_PSELE 0xA4050154 - -#define PORT_HIZCRA 0xA4050156 -#define PORT_HIZCRB 0xA4050158 -#define PORT_HIZCRC 0xA405015C - -#define PORT_DRVCR 0xA4050180 - -#define PORT_PADR 0xA4050120 -#define PORT_PBDR 0xA4050122 -#define PORT_PCDR 0xA4050124 -#define PORT_PDDR 0xA4050126 -#define PORT_PEDR 0xA4050128 -#define PORT_PFDR 0xA405012A -#define PORT_PGDR 0xA405012C -#define PORT_PHDR 0xA405012E -#define PORT_PJDR 0xA4050130 -#define PORT_PKDR 0xA4050132 -#define PORT_PLDR 0xA4050134 -#define PORT_PMDR 0xA4050136 -#define PORT_PNDR 0xA4050138 -#define PORT_PQDR 0xA405013A -#define PORT_PRDR 0xA405013C -#define PORT_PTDR 0xA4050160 -#define PORT_PUDR 0xA4050162 -#define PORT_PVDR 0xA4050164 -#define PORT_PWDR 0xA4050166 -#define PORT_PYDR 0xA4050168 - -#define FPGA_IN 0xb1400000 -#define FPGA_OUT 0xb1400002 - -#define __IO_PREFIX sh7343se -#include - -#define IRQ0_IRQ 32 -#define IRQ1_IRQ 33 -#define IRQ4_IRQ 36 -#define IRQ5_IRQ 37 - -#define SE7343_FPGA_IRQ_MRSHPC0 0 -#define SE7343_FPGA_IRQ_MRSHPC1 1 -#define SE7343_FPGA_IRQ_MRSHPC2 2 -#define SE7343_FPGA_IRQ_MRSHPC3 3 -#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ -#define SE7343_FPGA_IRQ_USB 8 - -#define SE7343_FPGA_IRQ_NR 11 -#define SE7343_FPGA_IRQ_BASE 120 - -#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3) -#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2) -#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1) -#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0) -#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC) -#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB) - -/* arch/sh/boards/se/7343/irq.c */ -void init_7343se_IRQ(void); - -#endif /* __ASM_SH_HITACHI_SE7343_H */ diff --git a/arch/sh/include/asm/se7721.h b/arch/sh/include/asm/se7721.h deleted file mode 100644 index b957f604119..00000000000 --- a/arch/sh/include/asm/se7721.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * - * Hitachi UL SolutionEngine 7721 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ - -#ifndef __ASM_SH_SE7721_H -#define __ASM_SH_SE7721_H -#include - -/* Box specific addresses. */ -#define SE_AREA0_WIDTH 2 /* Area0: 32bit */ -#define PA_ROM 0xa0000000 /* EPROM */ -#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ -#define PA_FROM 0xa1000000 /* Flash-ROM */ -#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ -#define PA_EXT1 0xa4000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */ -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0xb0000000 -#define PA_EXT4_SIZE 0x04000000 - -#define PA_PERIPHERAL 0xB8000000 - -#define PA_PCIC PA_PERIPHERAL -#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) -#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) -#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) -#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define PA_LED 0xB6800000 /* 8bit LED */ -#define PA_FPGA 0xB7000000 /* FPGA base address */ - -#define MRSHPC_IRQ0 10 - -#define FPGA_ILSR1 (PA_FPGA + 0x02) -#define FPGA_ILSR2 (PA_FPGA + 0x03) -#define FPGA_ILSR3 (PA_FPGA + 0x04) -#define FPGA_ILSR4 (PA_FPGA + 0x05) -#define FPGA_ILSR5 (PA_FPGA + 0x06) -#define FPGA_ILSR6 (PA_FPGA + 0x07) -#define FPGA_ILSR7 (PA_FPGA + 0x08) -#define FPGA_ILSR8 (PA_FPGA + 0x09) - -void init_se7721_IRQ(void); - -#define __IO_PREFIX se7721 -#include - -#endif /* __ASM_SH_SE7721_H */ diff --git a/arch/sh/include/asm/se7722.h b/arch/sh/include/asm/se7722.h deleted file mode 100644 index e971d9a82f4..00000000000 --- a/arch/sh/include/asm/se7722.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef __ASM_SH_SE7722_H -#define __ASM_SH_SE7722_H - -/* - * linux/include/asm-sh/se7722.h - * - * Copyright (C) 2007 Nobuhiro Iwamatsu - * - * Hitachi UL SolutionEngine 7722 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#include - -/* Box specific addresses. */ -#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ -#define PA_ROM 0xa0000000 /* EPROM */ -#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ -#define PA_FROM 0xa1000000 /* Flash-ROM */ -#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ -#define PA_EXT1 0xa4000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0xb0000000 -#define PA_EXT4_SIZE 0x04000000 - -#define PA_PERIPHERAL 0xB0000000 - -#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ -#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ - -#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ -/* GPIO */ -#define FPGA_IN 0xb1840000UL -#define FPGA_OUT 0xb1840004UL - -#define PORT_PECR 0xA4050108UL -#define PORT_PJCR 0xA4050110UL -#define PORT_PSELD 0xA4050154UL -#define PORT_PSELB 0xA4050150UL - -#define PORT_PSELC 0xA4050152UL -#define PORT_PKCR 0xA4050112UL -#define PORT_PHCR 0xA405010EUL -#define PORT_PLCR 0xA4050114UL -#define PORT_PMCR 0xA4050116UL -#define PORT_PRCR 0xA405011CUL -#define PORT_PXCR 0xA4050148UL -#define PORT_PSELA 0xA405014EUL -#define PORT_PYCR 0xA405014AUL -#define PORT_PZCR 0xA405014CUL -#define PORT_HIZCRA 0xA4050158UL -#define PORT_HIZCRC 0xA405015CUL - -/* IRQ */ -#define IRQ0_IRQ 32 -#define IRQ1_IRQ 33 - -#define IRQ01_MODE 0xb1800000 -#define IRQ01_STS 0xb1800004 -#define IRQ01_MASK 0xb1800008 - -/* Bits in IRQ01_* registers */ - -#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ -#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ -#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ -#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ -#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ -#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ - -#define SE7722_FPGA_IRQ_NR 6 -#define SE7722_FPGA_IRQ_BASE 110 - -#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3) -#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2) -#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1) -#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0) -#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC) -#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB) - -/* arch/sh/boards/se/7722/irq.c */ -void init_se7722_IRQ(void); - -#define __IO_PREFIX se7722 -#include - -#endif /* __ASM_SH_SE7722_H */ diff --git a/arch/sh/include/asm/se7751.h b/arch/sh/include/asm/se7751.h deleted file mode 100644 index b36792ac5d6..00000000000 --- a/arch/sh/include/asm/se7751.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef __ASM_SH_HITACHI_7751SE_H -#define __ASM_SH_HITACHI_7751SE_H - -/* - * linux/include/asm-sh/hitachi_7751se.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SolutionEngine support - - * Modified for 7751 Solution Engine by - * Ian da Silva and Jeremy Siegel, 2001. - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ -#define PA_LED 0xba000000 /* LED */ -#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_MODE (PA_MRSHPC + 4) -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#define IRQ_79C973 13 - -void init_7751se_IRQ(void); - -#define __IO_PREFIX sh7751se -#include - -#endif /* __ASM_SH_HITACHI_7751SE_H */ diff --git a/arch/sh/include/asm/se7780.h b/arch/sh/include/asm/se7780.h deleted file mode 100644 index 40e9b41458c..00000000000 --- a/arch/sh/include/asm/se7780.h +++ /dev/null @@ -1,108 +0,0 @@ -#ifndef __ASM_SH_SE7780_H -#define __ASM_SH_SE7780_H - -/* - * linux/include/asm-sh/se7780.h - * - * Copyright (C) 2006,2007 Nobuhiro Iwamatsu - * - * Hitachi UL SolutionEngine 7780 Support. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include - -/* Box specific addresses. */ -#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ -#define PA_ROM 0xa0000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0xa1000000 /* Flash-ROM */ -#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ -#define PA_EXT1 0xa4000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */ -#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */ -#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ -#define PA_SDRAM_SIZE 0x08000000 - -#define PA_EXT4 0xb0000000 -#define PA_EXT4_SIZE 0x04000000 -#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */ - -#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */ - -#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */ -#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */ -#define DISP_CHAR_RAM (7 << 3) -#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0) -#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1) -#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2) -#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3) -#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4) -#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5) -#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6) -#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7) - -#define DISP_UDC_RAM (5 << 3) -#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ - -/* FPGA register address and bit */ -#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ -#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ -#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ -#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ -#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ -#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ -#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ -#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ -#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ -#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ -#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ -#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ -#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ -#define PA_LED FPGA_DBG_LED -#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ -#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ -#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */ - -/* FPGA INTSEL position */ -/* INTSEL1 */ -#define IRQPOS_SMC91CX (0 * 4) -#define IRQPOS_SM501 (1 * 4) -/* INTSEL2 */ -#define IRQPOS_EXTINT1 (0 * 4) -#define IRQPOS_EXTINT2 (1 * 4) -#define IRQPOS_EXTINT3 (2 * 4) -#define IRQPOS_EXTINT4 (3 * 4) -/* INTSEL3 */ -#define IRQPOS_PCCPW (0 * 4) - -/* IDE interrupt */ -#define IRQ_IDE0 67 /* iVDR */ - -/* SMC interrupt */ -#define SMC_IRQ 8 - -/* SM501 interrupt */ -#define SM501_IRQ 0 - -/* interrupt pin */ -#define IRQPIN_EXTINT1 0 /* IRQ0 pin */ -#define IRQPIN_EXTINT2 1 /* IRQ1 pin */ -#define IRQPIN_EXTINT3 2 /* IRQ2 pin */ -#define IRQPIN_SMC91CX 3 /* IRQ3 pin */ -#define IRQPIN_EXTINT4 4 /* IRQ4 pin */ -#define IRQPIN_PCC0 5 /* IRQ5 pin */ -#define IRQPIN_PCC2 6 /* IRQ6 pin */ -#define IRQPIN_SM501 7 /* IRQ7 pin */ -#define IRQPIN_PCCPW 7 /* IRQ7 pin */ - -/* arch/sh/boards/se/7780/irq.c */ -void init_se7780_IRQ(void); - -#define __IO_PREFIX se7780 -#include - -#endif /* __ASM_SH_SE7780_H */ diff --git a/arch/sh/include/mach-se/mach/se.h b/arch/sh/include/mach-se/mach/se.h new file mode 100644 index 00000000000..eb23000e1bb --- /dev/null +++ b/arch/sh/include/mach-se/mach/se.h @@ -0,0 +1,99 @@ +#ifndef __ASM_SH_HITACHI_SE_H +#define __ASM_SH_HITACHI_SE_H + +/* + * linux/include/asm-sh/hitachi_se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_83902 0xb0000000 /* DP83902A */ +#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ +#define PA_83902_RST 0xb0080000 /* DP83902A reset port */ + +#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ +#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ +#define PA_LED 0xb0c00000 /* LED */ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define PA_BCR 0xb0e00000 +#else +#define PA_BCR 0xb1400000 /* FPGA */ +#endif + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define IRQ_STNIC 12 +#define IRQ_CFCARD 14 +#else +#define IRQ_STNIC 10 +#define IRQ_CFCARD 7 +#endif + +/* SH Ether support (SH7710/SH7712) */ +/* Base address */ +#define SH_ETH0_BASE 0xA7000000 +#define SH_ETH1_BASE 0xA7000400 +/* PHY ID */ +#if defined(CONFIG_CPU_SUBTYPE_SH7710) +# define PHY_ID 0x00 +#elif defined(CONFIG_CPU_SUBTYPE_SH7712) +# define PHY_ID 0x01 +#endif +/* Ether IRQ */ +#define SH_ETH0_IRQ 80 +#define SH_ETH1_IRQ 81 +#define SH_TSU_IRQ 82 + +void init_se_IRQ(void); + +#define __IO_PREFIX se +#include + +#endif /* __ASM_SH_HITACHI_SE_H */ diff --git a/arch/sh/include/mach-se/mach/se7206.h b/arch/sh/include/mach-se/mach/se7206.h new file mode 100644 index 00000000000..698eb80389a --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7206.h @@ -0,0 +1,13 @@ +#ifndef __ASM_SH_SE7206_H +#define __ASM_SH_SE7206_H + +#define PA_SMSC 0x30000000 +#define PA_MRSHPC 0x34000000 +#define PA_LED 0x31400000 + +void init_se7206_IRQ(void); + +#define __IO_PREFIX se7206 +#include + +#endif /* __ASM_SH_SE7206_H */ diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h new file mode 100644 index 00000000000..98458460e63 --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7343.h @@ -0,0 +1,149 @@ +#ifndef __ASM_SH_HITACHI_SE7343_H +#define __ASM_SH_HITACHI_SE7343_H + +/* + * include/asm-sh/se/se7343.h + * + * Copyright (C) 2003 Takashi Kusuda + * + * SH-Mobile SolutionEngine 7343 support + */ + +/* Box specific addresses. */ + +/* Area 0 */ +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ +#define PA_FROM 0x00400000 /* Flash ROM */ +#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ +#define PA_SRAM 0x00800000 /* SRAM */ +#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ +/* Area 1 */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +/* Area 2 */ +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +/* Area 3 */ +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 +/* Area 4 */ +#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) +#define PA_LED 0xb0C00000 /* LED */ +#define LED_SHIFT 0 +#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ +#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */ +#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */ +#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */ +/* Area 5 */ +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +/* Area 6 */ +#define PA_LCD1 0xb8000000 +#define PA_LCD2 0xb8800000 + +#define PORT_PACR 0xA4050100 +#define PORT_PBCR 0xA4050102 +#define PORT_PCCR 0xA4050104 +#define PORT_PDCR 0xA4050106 +#define PORT_PECR 0xA4050108 +#define PORT_PFCR 0xA405010A +#define PORT_PGCR 0xA405010C +#define PORT_PHCR 0xA405010E +#define PORT_PJCR 0xA4050110 +#define PORT_PKCR 0xA4050112 +#define PORT_PLCR 0xA4050114 +#define PORT_PMCR 0xA4050116 +#define PORT_PNCR 0xA4050118 +#define PORT_PQCR 0xA405011A +#define PORT_PRCR 0xA405011C +#define PORT_PSCR 0xA405011E +#define PORT_PTCR 0xA4050140 +#define PORT_PUCR 0xA4050142 +#define PORT_PVCR 0xA4050144 +#define PORT_PWCR 0xA4050146 +#define PORT_PYCR 0xA4050148 +#define PORT_PZCR 0xA405014A + +#define PORT_PSELA 0xA405014C +#define PORT_PSELB 0xA405014E +#define PORT_PSELC 0xA4050150 +#define PORT_PSELD 0xA4050152 +#define PORT_PSELE 0xA4050154 + +#define PORT_HIZCRA 0xA4050156 +#define PORT_HIZCRB 0xA4050158 +#define PORT_HIZCRC 0xA405015C + +#define PORT_DRVCR 0xA4050180 + +#define PORT_PADR 0xA4050120 +#define PORT_PBDR 0xA4050122 +#define PORT_PCDR 0xA4050124 +#define PORT_PDDR 0xA4050126 +#define PORT_PEDR 0xA4050128 +#define PORT_PFDR 0xA405012A +#define PORT_PGDR 0xA405012C +#define PORT_PHDR 0xA405012E +#define PORT_PJDR 0xA4050130 +#define PORT_PKDR 0xA4050132 +#define PORT_PLDR 0xA4050134 +#define PORT_PMDR 0xA4050136 +#define PORT_PNDR 0xA4050138 +#define PORT_PQDR 0xA405013A +#define PORT_PRDR 0xA405013C +#define PORT_PTDR 0xA4050160 +#define PORT_PUDR 0xA4050162 +#define PORT_PVDR 0xA4050164 +#define PORT_PWDR 0xA4050166 +#define PORT_PYDR 0xA4050168 + +#define FPGA_IN 0xb1400000 +#define FPGA_OUT 0xb1400002 + +#define __IO_PREFIX sh7343se +#include + +#define IRQ0_IRQ 32 +#define IRQ1_IRQ 33 +#define IRQ4_IRQ 36 +#define IRQ5_IRQ 37 + +#define SE7343_FPGA_IRQ_MRSHPC0 0 +#define SE7343_FPGA_IRQ_MRSHPC1 1 +#define SE7343_FPGA_IRQ_MRSHPC2 2 +#define SE7343_FPGA_IRQ_MRSHPC3 3 +#define SE7343_FPGA_IRQ_SMC 6 /* EXT_IRQ2 */ +#define SE7343_FPGA_IRQ_USB 8 + +#define SE7343_FPGA_IRQ_NR 11 +#define SE7343_FPGA_IRQ_BASE 120 + +#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3) +#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2) +#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1) +#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0) +#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC) +#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB) + +/* arch/sh/boards/se/7343/irq.c */ +void init_7343se_IRQ(void); + +#endif /* __ASM_SH_HITACHI_SE7343_H */ diff --git a/arch/sh/include/mach-se/mach/se7721.h b/arch/sh/include/mach-se/mach/se7721.h new file mode 100644 index 00000000000..b957f604119 --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7721.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * + * Hitachi UL SolutionEngine 7721 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ + +#ifndef __ASM_SH_SE7721_H +#define __ASM_SH_SE7721_H +#include + +/* Box specific addresses. */ +#define SE_AREA0_WIDTH 2 /* Area0: 32bit */ +#define PA_ROM 0xa0000000 /* EPROM */ +#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ +#define PA_FROM 0xa1000000 /* Flash-ROM */ +#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ +#define PA_EXT1 0xa4000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_SDRAM 0xaC000000 /* SDRAM(Area3) 64MB */ +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0xb0000000 +#define PA_EXT4_SIZE 0x04000000 + +#define PA_PERIPHERAL 0xB8000000 + +#define PA_PCIC PA_PERIPHERAL +#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) +#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) +#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) +#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define PA_LED 0xB6800000 /* 8bit LED */ +#define PA_FPGA 0xB7000000 /* FPGA base address */ + +#define MRSHPC_IRQ0 10 + +#define FPGA_ILSR1 (PA_FPGA + 0x02) +#define FPGA_ILSR2 (PA_FPGA + 0x03) +#define FPGA_ILSR3 (PA_FPGA + 0x04) +#define FPGA_ILSR4 (PA_FPGA + 0x05) +#define FPGA_ILSR5 (PA_FPGA + 0x06) +#define FPGA_ILSR6 (PA_FPGA + 0x07) +#define FPGA_ILSR7 (PA_FPGA + 0x08) +#define FPGA_ILSR8 (PA_FPGA + 0x09) + +void init_se7721_IRQ(void); + +#define __IO_PREFIX se7721 +#include + +#endif /* __ASM_SH_SE7721_H */ diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h new file mode 100644 index 00000000000..e971d9a82f4 --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7722.h @@ -0,0 +1,112 @@ +#ifndef __ASM_SH_SE7722_H +#define __ASM_SH_SE7722_H + +/* + * linux/include/asm-sh/se7722.h + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7722 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include + +/* Box specific addresses. */ +#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ +#define PA_ROM 0xa0000000 /* EPROM */ +#define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ +#define PA_FROM 0xa1000000 /* Flash-ROM */ +#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ +#define PA_EXT1 0xa4000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0xb0000000 +#define PA_EXT4_SIZE 0x04000000 + +#define PA_PERIPHERAL 0xB0000000 + +#define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ +#define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ + +#define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ +/* GPIO */ +#define FPGA_IN 0xb1840000UL +#define FPGA_OUT 0xb1840004UL + +#define PORT_PECR 0xA4050108UL +#define PORT_PJCR 0xA4050110UL +#define PORT_PSELD 0xA4050154UL +#define PORT_PSELB 0xA4050150UL + +#define PORT_PSELC 0xA4050152UL +#define PORT_PKCR 0xA4050112UL +#define PORT_PHCR 0xA405010EUL +#define PORT_PLCR 0xA4050114UL +#define PORT_PMCR 0xA4050116UL +#define PORT_PRCR 0xA405011CUL +#define PORT_PXCR 0xA4050148UL +#define PORT_PSELA 0xA405014EUL +#define PORT_PYCR 0xA405014AUL +#define PORT_PZCR 0xA405014CUL +#define PORT_HIZCRA 0xA4050158UL +#define PORT_HIZCRC 0xA405015CUL + +/* IRQ */ +#define IRQ0_IRQ 32 +#define IRQ1_IRQ 33 + +#define IRQ01_MODE 0xb1800000 +#define IRQ01_STS 0xb1800004 +#define IRQ01_MASK 0xb1800008 + +/* Bits in IRQ01_* registers */ + +#define SE7722_FPGA_IRQ_USB 0 /* IRQ0 */ +#define SE7722_FPGA_IRQ_SMC 1 /* IRQ0 */ +#define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC1 3 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC2 4 /* IRQ1 */ +#define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */ + +#define SE7722_FPGA_IRQ_NR 6 +#define SE7722_FPGA_IRQ_BASE 110 + +#define MRSHPC_IRQ3 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC3) +#define MRSHPC_IRQ2 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC2) +#define MRSHPC_IRQ1 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC1) +#define MRSHPC_IRQ0 (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_MRSHPC0) +#define SMC_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_SMC) +#define USB_IRQ (SE7722_FPGA_IRQ_BASE + SE7722_FPGA_IRQ_USB) + +/* arch/sh/boards/se/7722/irq.c */ +void init_se7722_IRQ(void); + +#define __IO_PREFIX se7722 +#include + +#endif /* __ASM_SH_SE7722_H */ diff --git a/arch/sh/include/mach-se/mach/se7751.h b/arch/sh/include/mach-se/mach/se7751.h new file mode 100644 index 00000000000..b36792ac5d6 --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7751.h @@ -0,0 +1,73 @@ +#ifndef __ASM_SH_HITACHI_7751SE_H +#define __ASM_SH_HITACHI_7751SE_H + +/* + * linux/include/asm-sh/hitachi_7751se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ +#define PA_LED 0xba000000 /* LED */ +#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_MODE (PA_MRSHPC + 4) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#define IRQ_79C973 13 + +void init_7751se_IRQ(void); + +#define __IO_PREFIX sh7751se +#include + +#endif /* __ASM_SH_HITACHI_7751SE_H */ diff --git a/arch/sh/include/mach-se/mach/se7780.h b/arch/sh/include/mach-se/mach/se7780.h new file mode 100644 index 00000000000..40e9b41458c --- /dev/null +++ b/arch/sh/include/mach-se/mach/se7780.h @@ -0,0 +1,108 @@ +#ifndef __ASM_SH_SE7780_H +#define __ASM_SH_SE7780_H + +/* + * linux/include/asm-sh/se7780.h + * + * Copyright (C) 2006,2007 Nobuhiro Iwamatsu + * + * Hitachi UL SolutionEngine 7780 Support. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include + +/* Box specific addresses. */ +#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ +#define PA_ROM 0xa0000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0xa1000000 /* Flash-ROM */ +#define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ +#define PA_EXT1 0xa4000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_SM501 PA_EXT1 /* Graphic IC (SM501) */ +#define PA_SM501_SIZE PA_EXT1_SIZE /* Graphic IC (SM501) */ +#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ +#define PA_SDRAM_SIZE 0x08000000 + +#define PA_EXT4 0xb0000000 +#define PA_EXT4_SIZE 0x04000000 +#define PA_EXT_FLASH PA_EXT4 /* Expansion Flash-ROM */ + +#define PA_PERIPHERAL PA_AREA6_IO /* SW6-6=ON */ + +#define PA_LAN (PA_PERIPHERAL + 0) /* SMC LAN91C111 */ +#define PA_LED_DISP (PA_PERIPHERAL + 0x02000000) /* 8words LED Display */ +#define DISP_CHAR_RAM (7 << 3) +#define DISP_SEL0_ADDR (DISP_CHAR_RAM + 0) +#define DISP_SEL1_ADDR (DISP_CHAR_RAM + 1) +#define DISP_SEL2_ADDR (DISP_CHAR_RAM + 2) +#define DISP_SEL3_ADDR (DISP_CHAR_RAM + 3) +#define DISP_SEL4_ADDR (DISP_CHAR_RAM + 4) +#define DISP_SEL5_ADDR (DISP_CHAR_RAM + 5) +#define DISP_SEL6_ADDR (DISP_CHAR_RAM + 6) +#define DISP_SEL7_ADDR (DISP_CHAR_RAM + 7) + +#define DISP_UDC_RAM (5 << 3) +#define PA_FPGA (PA_PERIPHERAL + 0x03000000) /* FPGA base address */ + +/* FPGA register address and bit */ +#define FPGA_SFTRST (PA_FPGA + 0) /* Soft reset register */ +#define FPGA_INTMSK1 (PA_FPGA + 2) /* Interrupt Mask register 1 */ +#define FPGA_INTMSK2 (PA_FPGA + 4) /* Interrupt Mask register 2 */ +#define FPGA_INTSEL1 (PA_FPGA + 6) /* Interrupt select register 1 */ +#define FPGA_INTSEL2 (PA_FPGA + 8) /* Interrupt select register 2 */ +#define FPGA_INTSEL3 (PA_FPGA + 10) /* Interrupt select register 3 */ +#define FPGA_PCI_INTSEL1 (PA_FPGA + 12) /* PCI Interrupt select register 1 */ +#define FPGA_PCI_INTSEL2 (PA_FPGA + 14) /* PCI Interrupt select register 2 */ +#define FPGA_INTSET (PA_FPGA + 16) /* IRQ/IRL select register */ +#define FPGA_INTSTS1 (PA_FPGA + 18) /* Interrupt status register 1 */ +#define FPGA_INTSTS2 (PA_FPGA + 20) /* Interrupt status register 2 */ +#define FPGA_REQSEL (PA_FPGA + 22) /* REQ/GNT select register */ +#define FPGA_DBG_LED (PA_FPGA + 32) /* Debug LED(D-LED[8:1] */ +#define PA_LED FPGA_DBG_LED +#define FPGA_IVDRID (PA_FPGA + 36) /* iVDR ID Register */ +#define FPGA_IVDRPW (PA_FPGA + 38) /* iVDR Power ON Register */ +#define FPGA_MMCID (PA_FPGA + 40) /* MMC ID Register */ + +/* FPGA INTSEL position */ +/* INTSEL1 */ +#define IRQPOS_SMC91CX (0 * 4) +#define IRQPOS_SM501 (1 * 4) +/* INTSEL2 */ +#define IRQPOS_EXTINT1 (0 * 4) +#define IRQPOS_EXTINT2 (1 * 4) +#define IRQPOS_EXTINT3 (2 * 4) +#define IRQPOS_EXTINT4 (3 * 4) +/* INTSEL3 */ +#define IRQPOS_PCCPW (0 * 4) + +/* IDE interrupt */ +#define IRQ_IDE0 67 /* iVDR */ + +/* SMC interrupt */ +#define SMC_IRQ 8 + +/* SM501 interrupt */ +#define SM501_IRQ 0 + +/* interrupt pin */ +#define IRQPIN_EXTINT1 0 /* IRQ0 pin */ +#define IRQPIN_EXTINT2 1 /* IRQ1 pin */ +#define IRQPIN_EXTINT3 2 /* IRQ2 pin */ +#define IRQPIN_SMC91CX 3 /* IRQ3 pin */ +#define IRQPIN_EXTINT4 4 /* IRQ4 pin */ +#define IRQPIN_PCC0 5 /* IRQ5 pin */ +#define IRQPIN_PCC2 6 /* IRQ6 pin */ +#define IRQPIN_SM501 7 /* IRQ7 pin */ +#define IRQPIN_PCCPW 7 /* IRQ7 pin */ + +/* arch/sh/boards/se/7780/irq.c */ +void init_se7780_IRQ(void); + +#define __IO_PREFIX se7780 +#include + +#endif /* __ASM_SH_SE7780_H */ diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c index d3d9f320423..bea40339919 100644 --- a/arch/sh/kernel/cf-enabler.c +++ b/arch/sh/kernel/cf-enabler.c @@ -80,11 +80,11 @@ static int __init cf_init_default(void) } #if defined(CONFIG_SH_SOLUTION_ENGINE) -#include +#include #elif defined(CONFIG_SH_7722_SOLUTION_ENGINE) -#include +#include #elif defined(CONFIG_SH_7721_SOLUTION_ENGINE) -#include +#include #endif /* -- cgit v1.2.3-70-g09d2 From 0764bff445bb13cd17e41b6ab196ef83c23c6c17 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 29 Jul 2008 22:10:01 +0900 Subject: sh: More header path fixups for mach dir refactoring. Signed-off-by: Paul Mundt --- arch/sh/boards/mach-highlander/psw.c | 2 +- arch/sh/boards/mach-landisk/gio.c | 4 ++-- arch/sh/boards/mach-landisk/irq.c | 2 +- arch/sh/boards/mach-landisk/psw.c | 2 +- arch/sh/boards/mach-landisk/setup.c | 2 +- arch/sh/boards/mach-se/7343/io.c | 2 +- arch/sh/boards/mach-sh03/setup.c | 4 ++-- arch/sh/include/mach-dreamcast/mach/pci.h | 2 +- drivers/cdrom/gdrom.c | 4 ++-- drivers/input/keyboard/maple_keyb.c | 1 - drivers/video/pvr2fb.c | 6 +++--- 11 files changed, 15 insertions(+), 16 deletions(-) (limited to 'arch/sh/boards/mach-se') diff --git a/arch/sh/boards/mach-highlander/psw.c b/arch/sh/boards/mach-highlander/psw.c index 0b3e062e96c..be8d5477fc6 100644 --- a/arch/sh/boards/mach-highlander/psw.c +++ b/arch/sh/boards/mach-highlander/psw.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include static irqreturn_t psw_irq_handler(int irq, void *arg) diff --git a/arch/sh/boards/mach-landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c index edcde082032..25cdf735800 100644 --- a/arch/sh/boards/mach-landisk/gio.c +++ b/arch/sh/boards/mach-landisk/gio.c @@ -20,8 +20,8 @@ #include #include #include -#include -#include +#include +#include #define DEVCOUNT 4 #define GIO_MINOR 2 /* GIO minor no. */ diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c index d0f9378f6ff..7b284cde1f5 100644 --- a/arch/sh/boards/mach-landisk/irq.c +++ b/arch/sh/boards/mach-landisk/irq.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include static void disable_landisk_irq(unsigned int irq) { diff --git a/arch/sh/boards/mach-landisk/psw.c b/arch/sh/boards/mach-landisk/psw.c index 4bd502cbaee..e6b0efa098d 100644 --- a/arch/sh/boards/mach-landisk/psw.c +++ b/arch/sh/boards/mach-landisk/psw.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include static irqreturn_t psw_irq_handler(int irq, void *arg) diff --git a/arch/sh/boards/mach-landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c index 470c7811168..db22ea2e6d4 100644 --- a/arch/sh/boards/mach-landisk/setup.c +++ b/arch/sh/boards/mach-landisk/setup.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include void init_landisk_IRQ(void); diff --git a/arch/sh/boards/mach-se/7343/io.c b/arch/sh/boards/mach-se/7343/io.c index e2fae32d27d..8741abc1da7 100644 --- a/arch/sh/boards/mach-se/7343/io.c +++ b/arch/sh/boards/mach-se/7343/io.c @@ -6,7 +6,7 @@ */ #include #include -#include +#include #define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a) diff --git a/arch/sh/boards/mach-sh03/setup.c b/arch/sh/boards/mach-sh03/setup.c index cd9cff1ed34..5771219be3f 100644 --- a/arch/sh/boards/mach-sh03/setup.c +++ b/arch/sh/boards/mach-sh03/setup.c @@ -11,8 +11,8 @@ #include #include #include -#include -#include +#include +#include #include static void __init init_sh03_IRQ(void) diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h index 9264ff46c63..75fc9009e09 100644 --- a/arch/sh/include/mach-dreamcast/mach/pci.h +++ b/arch/sh/include/mach-dreamcast/mach/pci.h @@ -11,7 +11,7 @@ #ifndef __ASM_SH_DREAMCAST_PCI_H #define __ASM_SH_DREAMCAST_PCI_H -#include +#include #define GAPSPCI_REGS 0x01001400 #define GAPSPCI_DMA_BASE 0x01840000 diff --git a/drivers/cdrom/gdrom.c b/drivers/cdrom/gdrom.c index 71ec426ecff..1e0455bd6df 100644 --- a/drivers/cdrom/gdrom.c +++ b/drivers/cdrom/gdrom.c @@ -39,8 +39,8 @@ #include #include #include -#include -#include +#include +#include #define GDROM_DEV_NAME "gdrom" #define GD_SESSION_OFFSET 150 diff --git a/drivers/input/keyboard/maple_keyb.c b/drivers/input/keyboard/maple_keyb.c index 2b404284c28..7797ef6e5e6 100644 --- a/drivers/input/keyboard/maple_keyb.c +++ b/drivers/input/keyboard/maple_keyb.c @@ -27,7 +27,6 @@ #include #include #include -#include /* Very simple mutex to ensure proper cleanup */ static DEFINE_MUTEX(maple_keyb_mutex); diff --git a/drivers/video/pvr2fb.c b/drivers/video/pvr2fb.c index 8c863a7f654..0a0fd48a856 100644 --- a/drivers/video/pvr2fb.c +++ b/drivers/video/pvr2fb.c @@ -58,18 +58,18 @@ #ifdef CONFIG_SH_DREAMCAST #include -#include +#include #endif #ifdef CONFIG_SH_DMA #include -#include +#include #include #endif #ifdef CONFIG_SH_STORE_QUEUES #include -#include +#include #endif #ifndef PCI_DEVICE_ID_NEC_NEON250 -- cgit v1.2.3-70-g09d2 From c8b5d9dcbc94ae5e7d9ed647246df4454d25332e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 30 Jul 2008 00:13:39 +0900 Subject: sh: Move out individual boards without mach groups. Signed-off-by: Paul Mundt --- arch/sh/Makefile | 8 +- arch/sh/boards/Kconfig | 15 +- arch/sh/boards/Makefile | 8 + arch/sh/boards/board-ap325rxa.c | 317 ++++++++++++++++++++++++ arch/sh/boards/board-magicpanelr2.c | 394 ++++++++++++++++++++++++++++++ arch/sh/boards/board-rsk7203.c | 136 +++++++++++ arch/sh/boards/board-sh7785lcr.c | 302 +++++++++++++++++++++++ arch/sh/boards/board-shmin.c | 42 ++++ arch/sh/boards/mach-ap325rxa/Makefile | 1 - arch/sh/boards/mach-ap325rxa/setup.c | 317 ------------------------ arch/sh/boards/mach-magicpanelr2/Kconfig | 13 - arch/sh/boards/mach-magicpanelr2/Makefile | 5 - arch/sh/boards/mach-magicpanelr2/setup.c | 394 ------------------------------ arch/sh/boards/mach-rsk7203/Makefile | 1 - arch/sh/boards/mach-rsk7203/setup.c | 136 ----------- arch/sh/boards/mach-se/7619/Makefile | 5 - arch/sh/boards/mach-se/7619/setup.c | 21 -- arch/sh/boards/mach-se/Makefile | 3 +- arch/sh/boards/mach-se/board-se7619.c | 21 ++ arch/sh/boards/mach-sh7785lcr/Makefile | 1 - arch/sh/boards/mach-sh7785lcr/setup.c | 302 ----------------------- arch/sh/boards/mach-shmin/Makefile | 5 - arch/sh/boards/mach-shmin/setup.c | 42 ---- 23 files changed, 1238 insertions(+), 1251 deletions(-) create mode 100644 arch/sh/boards/Makefile create mode 100644 arch/sh/boards/board-ap325rxa.c create mode 100644 arch/sh/boards/board-magicpanelr2.c create mode 100644 arch/sh/boards/board-rsk7203.c create mode 100644 arch/sh/boards/board-sh7785lcr.c create mode 100644 arch/sh/boards/board-shmin.c delete mode 100644 arch/sh/boards/mach-ap325rxa/Makefile delete mode 100644 arch/sh/boards/mach-ap325rxa/setup.c delete mode 100644 arch/sh/boards/mach-magicpanelr2/Kconfig delete mode 100644 arch/sh/boards/mach-magicpanelr2/Makefile delete mode 100644 arch/sh/boards/mach-magicpanelr2/setup.c delete mode 100644 arch/sh/boards/mach-rsk7203/Makefile delete mode 100644 arch/sh/boards/mach-rsk7203/setup.c delete mode 100644 arch/sh/boards/mach-se/7619/Makefile delete mode 100644 arch/sh/boards/mach-se/7619/setup.c create mode 100644 arch/sh/boards/mach-se/board-se7619.c delete mode 100644 arch/sh/boards/mach-sh7785lcr/Makefile delete mode 100644 arch/sh/boards/mach-sh7785lcr/setup.c delete mode 100644 arch/sh/boards/mach-shmin/Makefile delete mode 100644 arch/sh/boards/mach-shmin/setup.c (limited to 'arch/sh/boards/mach-se') diff --git a/arch/sh/Makefile b/arch/sh/Makefile index fafc01236f6..6c93b948713 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -97,10 +97,10 @@ head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) -core-y += arch/sh/kernel/ arch/sh/mm/ +core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/ core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ -# Boards and Mach groups +# Mach groups machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast @@ -114,15 +114,11 @@ machdir-$(CONFIG_SH_MIGOR) += mach-migor machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780 machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto machdir-$(CONFIG_SH_RSK7203) += mach-rsk7203 -machdir-$(CONFIG_SH_AP325RXA) += mach-ap325rxa machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp -machdir-$(CONFIG_SH_SH7785LCR) += mach-sh7785lcr machdir-$(CONFIG_SH_SH4202_MICRODEV) += mach-microdev machdir-$(CONFIG_SH_LANDISK) += mach-landisk machdir-$(CONFIG_SH_TITAN) += mach-titan -machdir-$(CONFIG_SH_SHMIN) += mach-shmin machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2 -machdir-$(CONFIG_SH_MAGIC_PANEL_R2) += mach-magicpanelr2 machdir-$(CONFIG_SH_CAYMAN) += mach-cayman ifneq ($(machdir-y),) diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig index 324c25ac95c..ae194869fd6 100644 --- a/arch/sh/boards/Kconfig +++ b/arch/sh/boards/Kconfig @@ -242,4 +242,17 @@ source "arch/sh/boards/mach-r2d/Kconfig" source "arch/sh/boards/mach-highlander/Kconfig" source "arch/sh/boards/mach-sdk7780/Kconfig" source "arch/sh/boards/mach-migor/Kconfig" -source "arch/sh/boards/mach-magicpanelr2/Kconfig" + +if SH_MAGIC_PANEL_R2 + +menu "Magic Panel R2 options" + +config SH_MAGIC_PANEL_R2_VERSION + int SH_MAGIC_PANEL_R2_VERSION + default "3" + help + Set the version of the Magic Panel R2 + +endmenu + +endif diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile new file mode 100644 index 00000000000..ff9b93c5a91 --- /dev/null +++ b/arch/sh/boards/Makefile @@ -0,0 +1,8 @@ +# +# Specific board support, not covered by a mach group. +# +obj-$(CONFIG_SH_AP325RXA) += board-ap325rxa.o +obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_RSK7203) += board-rsk7203.o +obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o +obj-$(CONFIG_SH_SHMIN) += board-shmin..o diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c new file mode 100644 index 00000000000..9c71603d29a --- /dev/null +++ b/arch/sh/boards/board-ap325rxa.c @@ -0,0 +1,317 @@ +/* + * Renesas - AP-325RXA + * (Compatible with Algo System ., LTD. - AP-320A) + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Author : Yusuke Goda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smc911x_platdata smc911x_info = { + .flags = SMC911X_USE_32BIT, + .irq_flags = IRQF_TRIGGER_LOW, +}; + +static struct resource smc9118_resources[] = { + [0] = { + .start = 0xb6080000, + .end = 0xb60fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 35, + .end = 35, + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smc9118_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc9118_resources), + .resource = smc9118_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct mtd_partition ap325rxa_nor_flash_partitions[] = { + { + .name = "uboot", + .offset = 0, + .size = (1 * 1024 * 1024), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (2 * 1024 * 1024), + }, { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data ap325rxa_nor_flash_data = { + .width = 2, + .parts = ap325rxa_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), +}; + +static struct resource ap325rxa_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00ffffff, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device ap325rxa_nor_flash_device = { + .name = "physmap-flash", + .resource = ap325rxa_nor_flash_resources, + .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), + .dev = { + .platform_data = &ap325rxa_nor_flash_data, + }, +}; + +#define FPGA_LCDREG 0xB4100180 +#define FPGA_BKLREG 0xB4100212 +#define FPGA_LCDREG_VAL 0x0018 +#define PORT_PHCR 0xA405010E +#define PORT_PLCR 0xA4050114 +#define PORT_PMCR 0xA4050116 +#define PORT_PRCR 0xA405011C +#define PORT_PSCR 0xA405011E +#define PORT_PZCR 0xA405014C +#define PORT_HIZCRA 0xA4050158 +#define PORT_MSELCRB 0xA4050182 +#define PORT_PSDR 0xA405013E +#define PORT_PZDR 0xA405016C +#define PORT_PSELD 0xA4050154 + +static void ap320_wvga_power_on(void *board_data) +{ + msleep(100); + + /* ASD AP-320/325 LCD ON */ + ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); + + /* backlight */ + ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); + ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR); + ctrl_outw(0x100, FPGA_BKLREG); +} + +static struct sh_mobile_lcdc_info lcdc_info = { + .clock_source = LCDC_CLK_EXTERNAL, + .ch[0] = { + .chan = LCDC_CHAN_MAINLCD, + .bpp = 16, + .interface_type = RGB18, + .clock_divider = 1, + .lcd_cfg = { + .name = "LB070WV1", + .xres = 800, + .yres = 480, + .left_margin = 40, + .right_margin = 160, + .hsync_len = 8, + .upper_margin = 63, + .lower_margin = 80, + .vsync_len = 1, + .sync = 0, /* hsync and vsync are active low */ + }, + .board_cfg = { + .display_on = ap320_wvga_power_on, + }, + } +}; + +static struct resource lcdc_resources[] = { + [0] = { + .name = "LCDC", + .start = 0xfe940000, /* P4-only space */ + .end = 0xfe941fff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device lcdc_device = { + .name = "sh_mobile_lcdc_fb", + .num_resources = ARRAY_SIZE(lcdc_resources), + .resource = lcdc_resources, + .dev = { + .platform_data = &lcdc_info, + }, +}; + +#ifdef CONFIG_I2C +static unsigned char camera_ncm03j_magic[] = +{ + 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, + 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, + 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, + 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, + 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, + 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, + 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, + 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, + 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, + 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, + 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, + 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, + 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, + 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, + 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, + 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, +}; + +static int camera_set_capture(struct soc_camera_platform_info *info, + int enable) +{ + struct i2c_adapter *a = i2c_get_adapter(0); + struct i2c_msg msg; + int ret = 0; + int i; + + if (!enable) + return 0; /* no disable for now */ + + for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { + u_int8_t buf[8]; + + msg.addr = 0x6e; + msg.buf = buf; + msg.len = 2; + msg.flags = 0; + + buf[0] = camera_ncm03j_magic[i]; + buf[1] = camera_ncm03j_magic[i + 1]; + + ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); + } + + return ret; +} + +static struct soc_camera_platform_info camera_info = { + .iface = 0, + .format_name = "UYVY", + .format_depth = 16, + .format = { + .pixelformat = V4L2_PIX_FMT_UYVY, + .colorspace = V4L2_COLORSPACE_SMPTE170M, + .width = 640, + .height = 480, + }, + .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, + .set_capture = camera_set_capture, +}; + +static struct platform_device camera_device = { + .name = "soc_camera_platform", + .dev = { + .platform_data = &camera_info, + }, +}; +#endif /* CONFIG_I2C */ + +static struct sh_mobile_ceu_info sh_mobile_ceu_info = { + .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, +}; + +static struct resource ceu_resources[] = { + [0] = { + .name = "CEU", + .start = 0xfe910000, + .end = 0xfe91009f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 52, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* place holder for contiguous memory */ + }, +}; + +static struct platform_device ceu_device = { + .name = "sh_mobile_ceu", + .num_resources = ARRAY_SIZE(ceu_resources), + .resource = ceu_resources, + .dev = { + .platform_data = &sh_mobile_ceu_info, + }, +}; + +static struct platform_device *ap325rxa_devices[] __initdata = { + &smc9118_device, + &ap325rxa_nor_flash_device, + &lcdc_device, + &ceu_device, +#ifdef CONFIG_I2C + &camera_device, +#endif +}; + +static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { +}; + +static int __init ap325rxa_devices_setup(void) +{ + clk_always_enable("mstp200"); /* LCDC */ + clk_always_enable("mstp203"); /* CEU */ + + platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); + + i2c_register_board_info(0, ap325rxa_i2c_devices, + ARRAY_SIZE(ap325rxa_i2c_devices)); + + return platform_add_devices(ap325rxa_devices, + ARRAY_SIZE(ap325rxa_devices)); +} +device_initcall(ap325rxa_devices_setup); + +static void __init ap325rxa_setup(char **cmdline_p) +{ + /* LCDC configuration */ + ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR); + ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR); + ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR); + ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR); + ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA); + + /* CEU */ + ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); + ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD); + ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR); + ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR); +} + +static struct sh_machine_vector mv_ap325rxa __initmv = { + .mv_name = "AP-325RXA", + .mv_setup = ap325rxa_setup, +}; diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c new file mode 100644 index 00000000000..f3b8b07ea5d --- /dev/null +++ b/arch/sh/boards/board-magicpanelr2.c @@ -0,0 +1,394 @@ +/* + * linux/arch/sh/boards/magicpanel/setup.c + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Magic Panel Release 2 board setup + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL) + +/* Prefer cmdline over RedBoot */ +static const char *probes[] = { "cmdlinepart", "RedBoot", NULL }; + +/* Wait until reset finished. Timeout is 100ms. */ +static int __init ethernet_reset_finished(void) +{ + int i; + + if (LAN9115_READY) + return 1; + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (LAN9115_READY) + return 1; + } + + return 0; +} + +static void __init reset_ethernet(void) +{ + /* PMDR: LAN_RESET=on */ + CLRBITS_OUTB(0x10, PORT_PMDR); + + udelay(200); + + /* PMDR: LAN_RESET=off */ + SETBITS_OUTB(0x10, PORT_PMDR); +} + +static void __init setup_chip_select(void) +{ + /* CS2: LAN (0x08000000 - 0x0bffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + ctrl_outl(0x36db0400, CS2BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + ctrl_outl(0x000003c0, CS2WCR); + + /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + ctrl_outl(0x00000200, CS4BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + ctrl_outl(0x00100981, CS4WCR); + + /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + ctrl_outl(0x00000200, CS5ABCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + ctrl_outl(0x00100981, CS5AWCR); + + /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + ctrl_outl(0x00000200, CS5BBCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + ctrl_outl(0x00100981, CS5BWCR); + + /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + ctrl_outl(0x00000200, CS6ABCR); + /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ + ctrl_outl(0x001009C1, CS6AWCR); +} + +static void __init setup_port_multiplexing(void) +{ + /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); + * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); + */ + ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ + + /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); + * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); + */ + ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ + + /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); + * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; + */ + ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ + + /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); + * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); + */ + ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ + + /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; + * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; + */ + ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ + + /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; + * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); + */ + ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ + + /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); + * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); + */ + ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ + + /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); + * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; + */ + ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ + + /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; + * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; + */ + ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ + + /* K7 (x); K6 (x); K5 (x); K4 (x); + * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) + */ + ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ + + /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; + * L3 TCK; L2 (x); L1 (x); L0 (x); + */ + ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ + + /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); + * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); + * M1 CS5B(CAN3_CS); M0 GPI+(nc); + */ + ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ + + /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, + * LAN_RESET=off, BUZZER=off, LCD_BL=off + */ +#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 + ctrl_outb(0x30, PORT_PMDR); +#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 + ctrl_outb(0xF0, PORT_PMDR); +#else +#error Unknown revision of PLATFORM_MP_R2 +#endif + + /* P7 (x); P6 (x); P5 (x); + * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); + * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) + */ + ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ + ctrl_outb(0x10, PORT_PPDR); + + /* R7 A25; R6 A24; R5 A23; R4 A22; + * R3 A21; R2 A20; R1 A19; R0 A0; + */ + ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */ + + /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); + * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; + */ + ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ + + /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; + * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) + */ + ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ + + /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); + * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; + */ + ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ + + /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); + * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); + */ + ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ +} + +static void __init mpr2_setup(char **cmdline_p) +{ + __set_io_port_base(0xa0000000); + + /* set Pin Select Register A: + * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, + * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND + */ + ctrl_outw(0xAABC, PORT_PSELA); + /* set Pin Select Register B: + * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, + * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved + */ + ctrl_outw(0x3C00, PORT_PSELB); + /* set Pin Select Register C: + * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved + */ + ctrl_outw(0x0000, PORT_PSELC); + /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, + * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved + */ + ctrl_outw(0x0000, PORT_PSELD); + /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ + ctrl_outw(0x0101, PORT_UTRCTL); + /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ + ctrl_outw(0xA5C0, PORT_UCLKCR_W); + + setup_chip_select(); + + setup_port_multiplexing(); + + reset_ethernet(); + + printk(KERN_INFO "Magic Panel Release 2 A.%i\n", + CONFIG_SH_MAGIC_PANEL_R2_VERSION); + + if (ethernet_reset_finished() == 0) + printk(KERN_WARNING "Ethernet not ready\n"); +} + +static struct resource smc911x_resources[] = { + [0] = { + .start = 0xa8000000, + .end = 0xabffffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 35, + .end = 35, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc911x_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition *parsed_partitions; + +static struct mtd_partition mpr2_partitions[] = { + /* Reserved for bootloader, read-only */ + { + .name = "Bootloader", + .offset = 0x00000000UL, + .size = MPR2_MTD_BOOTLOADER_SIZE, + .mask_flags = MTD_WRITEABLE, + }, + /* Reserved for kernel image */ + { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = MPR2_MTD_KERNEL_SIZE, + }, + /* Rest is used for Flash FS */ + { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0x00000000, + .end = 0x2000000UL, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +static struct mtd_info *flash_mtd; + +static struct map_info mpr2_flash_map = { + .name = "Magic Panel R2 Flash", + .size = 0x2000000UL, + .bankwidth = 2, +}; + +static void __init set_mtd_partitions(void) +{ + int nr_parts = 0; + + simple_map_init(&mpr2_flash_map); + flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map); + nr_parts = parse_mtd_partitions(flash_mtd, probes, + &parsed_partitions, 0); + /* If there is no partition table, used the hard coded table */ + if (nr_parts <= 0) { + flash_data.parts = mpr2_partitions; + flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions); + } else { + flash_data.nr_parts = nr_parts; + flash_data.parts = parsed_partitions; + } +} + +/* + * Add all resources to the platform_device + */ + +static struct platform_device *mpr2_devices[] __initdata = { + &heartbeat_device, + &smc911x_device, + &flash_device, +}; + + +static int __init mpr2_devices_setup(void) +{ + set_mtd_partitions(); + return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); +} +device_initcall(mpr2_devices_setup); + +/* + * Initialize IRQ setting + */ +static void __init init_mpr2_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ + + set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + + intc_set_priority(32, 13); /* IRQ0 CAN1 */ + intc_set_priority(33, 13); /* IRQ0 CAN2 */ + intc_set_priority(34, 13); /* IRQ0 CAN3 */ + intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ +} + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_mpr2 __initmv = { + .mv_name = "mpr2", + .mv_setup = mpr2_setup, + .mv_init_irq = init_mpr2_IRQ, +}; diff --git a/arch/sh/boards/board-rsk7203.c b/arch/sh/boards/board-rsk7203.c new file mode 100644 index 00000000000..ffbedc59a97 --- /dev/null +++ b/arch/sh/boards/board-rsk7203.c @@ -0,0 +1,136 @@ +/* + * Renesas Technology Europe RSK+ 7203 Support. + * + * Copyright (C) 2008 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct smc911x_platdata smc911x_info = { + .flags = SMC911X_USE_16BIT, + .irq_flags = IRQF_TRIGGER_LOW, +}; + +static struct resource smc911x_resources[] = { + [0] = { + .start = 0x24000000, + .end = 0x24000000 + 0x100, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 64, + .end = 64, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc911x_device = { + .name = "smc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc911x_resources), + .resource = smc911x_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static const char *probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition *parsed_partitions; + +static struct mtd_partition rsk7203_partitions[] = { + { + .name = "Bootloader", + .offset = 0x00000000, + .size = 0x00040000, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = 0x001c0000, + }, { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0x20000000, + .end = 0x20400000, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +static struct mtd_info *flash_mtd; + +static struct map_info rsk7203_flash_map = { + .name = "RSK+ Flash", + .size = 0x400000, + .bankwidth = 2, +}; + +static void __init set_mtd_partitions(void) +{ + int nr_parts = 0; + + simple_map_init(&rsk7203_flash_map); + flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map); + nr_parts = parse_mtd_partitions(flash_mtd, probes, + &parsed_partitions, 0); + /* If there is no partition table, used the hard coded table */ + if (nr_parts <= 0) { + flash_data.parts = rsk7203_partitions; + flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions); + } else { + flash_data.nr_parts = nr_parts; + flash_data.parts = parsed_partitions; + } +} + + +static struct platform_device *rsk7203_devices[] __initdata = { + &smc911x_device, + &flash_device, +}; + +static int __init rsk7203_devices_setup(void) +{ + set_mtd_partitions(); + return platform_add_devices(rsk7203_devices, + ARRAY_SIZE(rsk7203_devices)); +} +device_initcall(rsk7203_devices_setup); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_rsk7203 __initmv = { + .mv_name = "RSK+7203", +}; diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c new file mode 100644 index 00000000000..b95d674ee70 --- /dev/null +++ b/arch/sh/boards/board-sh7785lcr.c @@ -0,0 +1,302 @@ +/* + * Renesas Technology Corp. R0P7785LC0011RL Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * NOTE: This board has 2 physical memory maps. + * Please look at include/asm-sh/sh7785lcr.h or hardware manual. + */ +static struct resource heartbeat_resources[] = { + [0] = { + .start = PLD_LEDCR, + .end = PLD_LEDCR, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .regsize = 8, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .name = "r8a66597_hcd", + .start = R8A66597_ADDR, + .end = R8A66597_ADDR + R8A66597_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "r8a66597_hcd", + .start = 2, + .end = 2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct resource sm501_resources[] = { + [0] = { + .start = SM107_MEM_ADDR, + .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SM107_REG_ADDR, + .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = 10, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fb_videomode sm501_default_mode_crt = { + .pixclock = 35714, /* 28MHz */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}; + +static struct fb_videomode sm501_default_mode_pnl = { + .pixclock = 40000, /* 25MHz */ + .xres = 640, + .yres = 480, + .left_margin = 2, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = 0, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_pnl, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_PANEL_NO_VBIASEN, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_crt, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT, +}; + +static struct sm501_platdata_fb sm501_fb_pdata = { + .fb_route = SM501_FB_OWN, + .fb_crt = &sm501_pdata_fbsub_crt, + .fb_pnl = &sm501_pdata_fbsub_pnl, +}; + +static struct sm501_initdata sm501_initdata = { + .gpio_high = { + .set = 0x00001fe0, + .mask = 0x0, + }, + .devices = 0, + .mclk = 84 * 1000000, + .m1xclk = 112 * 1000000, +}; + +static struct sm501_platdata sm501_platform_data = { + .init = &sm501_initdata, + .fb = &sm501_fb_pdata, +}; + +static struct platform_device sm501_device = { + .name = "sm501", + .id = -1, + .dev = { + .platform_data = &sm501_platform_data, + }, + .num_resources = ARRAY_SIZE(sm501_resources), + .resource = sm501_resources, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = PCA9564_ADDR, + .end = PCA9564_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = 12, + .end = 12, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pca9564_pf_platform_data i2c_platform_data = { + .gpio = 0, + .i2c_clock_speed = I2C_PCA_CON_330kHz, + .timeout = 100, +}; + +static struct platform_device i2c_device = { + .name = "i2c-pca-platform", + .id = -1, + .dev = { + .platform_data = &i2c_platform_data, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static struct platform_device *sh7785lcr_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &r8a66597_usb_host_device, + &sm501_device, + &i2c_device, +}; + +static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +static int __init sh7785lcr_devices_setup(void) +{ + i2c_register_board_info(0, sh7785lcr_i2c_devices, + ARRAY_SIZE(sh7785lcr_i2c_devices)); + + return platform_add_devices(sh7785lcr_devices, + ARRAY_SIZE(sh7785lcr_devices)); +} +__initcall(sh7785lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7785lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +static void sh7785lcr_power_off(void) +{ + ctrl_outb(0x01, P2SEGADDR(PLD_POFCR)); +} + +/* Initialize the board */ +static void __init sh7785lcr_setup(char **cmdline_p) +{ + void __iomem *sm501_reg; + + printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); + + pm_power_off = sh7785lcr_power_off; + + /* sm501 DRAM configuration */ + sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; + writel(0x000307c2, sm501_reg); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh7785lcr __initmv = { + .mv_name = "SH7785LCR", + .mv_setup = sh7785lcr_setup, + .mv_init_irq = init_sh7785lcr_IRQ, +}; + diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c new file mode 100644 index 00000000000..16e5dae8ecf --- /dev/null +++ b/arch/sh/boards/board-shmin.c @@ -0,0 +1,42 @@ +/* + * arch/sh/boards/shmin/setup.c + * + * Copyright (C) 2006 Takashi YOSHII + * + * SHMIN Support. + */ +#include +#include +#include +#include +#include +#include + +#define PFC_PHCR 0xa400010eUL +#define INTC_ICR1 0xa4000010UL + +static void __init init_shmin_irq(void) +{ + ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ + ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size) +{ + static int dummy; + + if ((port & ~0x1f) == SHMIN_NE_BASE) + return (void __iomem *)(SHMIN_IO_BASE + port); + + dummy = 0; + + return &dummy; + +} + +static struct sh_machine_vector mv_shmin __initmv = { + .mv_name = "SHMIN", + .mv_init_irq = init_shmin_irq, + .mv_ioport_map = shmin_ioport_map, +}; diff --git a/arch/sh/boards/mach-ap325rxa/Makefile b/arch/sh/boards/mach-ap325rxa/Makefile deleted file mode 100644 index f663768429f..00000000000 --- a/arch/sh/boards/mach-ap325rxa/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := setup.o diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c deleted file mode 100644 index 9c71603d29a..00000000000 --- a/arch/sh/boards/mach-ap325rxa/setup.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Renesas - AP-325RXA - * (Compatible with Algo System ., LTD. - AP-320A) - * - * Copyright (C) 2008 Renesas Solutions Corp. - * Author : Yusuke Goda - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct smc911x_platdata smc911x_info = { - .flags = SMC911X_USE_32BIT, - .irq_flags = IRQF_TRIGGER_LOW, -}; - -static struct resource smc9118_resources[] = { - [0] = { - .start = 0xb6080000, - .end = 0xb60fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 35, - .end = 35, - .flags = IORESOURCE_IRQ, - } -}; - -static struct platform_device smc9118_device = { - .name = "smc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smc9118_resources), - .resource = smc9118_resources, - .dev = { - .platform_data = &smc911x_info, - }, -}; - -static struct mtd_partition ap325rxa_nor_flash_partitions[] = { - { - .name = "uboot", - .offset = 0, - .size = (1 * 1024 * 1024), - .mask_flags = MTD_WRITEABLE, /* Read-only */ - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = (2 * 1024 * 1024), - }, { - .name = "other", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct physmap_flash_data ap325rxa_nor_flash_data = { - .width = 2, - .parts = ap325rxa_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions), -}; - -static struct resource ap325rxa_nor_flash_resources[] = { - [0] = { - .name = "NOR Flash", - .start = 0x00000000, - .end = 0x00ffffff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device ap325rxa_nor_flash_device = { - .name = "physmap-flash", - .resource = ap325rxa_nor_flash_resources, - .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources), - .dev = { - .platform_data = &ap325rxa_nor_flash_data, - }, -}; - -#define FPGA_LCDREG 0xB4100180 -#define FPGA_BKLREG 0xB4100212 -#define FPGA_LCDREG_VAL 0x0018 -#define PORT_PHCR 0xA405010E -#define PORT_PLCR 0xA4050114 -#define PORT_PMCR 0xA4050116 -#define PORT_PRCR 0xA405011C -#define PORT_PSCR 0xA405011E -#define PORT_PZCR 0xA405014C -#define PORT_HIZCRA 0xA4050158 -#define PORT_MSELCRB 0xA4050182 -#define PORT_PSDR 0xA405013E -#define PORT_PZDR 0xA405016C -#define PORT_PSELD 0xA4050154 - -static void ap320_wvga_power_on(void *board_data) -{ - msleep(100); - - /* ASD AP-320/325 LCD ON */ - ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); - - /* backlight */ - ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR); - ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR); - ctrl_outw(0x100, FPGA_BKLREG); -} - -static struct sh_mobile_lcdc_info lcdc_info = { - .clock_source = LCDC_CLK_EXTERNAL, - .ch[0] = { - .chan = LCDC_CHAN_MAINLCD, - .bpp = 16, - .interface_type = RGB18, - .clock_divider = 1, - .lcd_cfg = { - .name = "LB070WV1", - .xres = 800, - .yres = 480, - .left_margin = 40, - .right_margin = 160, - .hsync_len = 8, - .upper_margin = 63, - .lower_margin = 80, - .vsync_len = 1, - .sync = 0, /* hsync and vsync are active low */ - }, - .board_cfg = { - .display_on = ap320_wvga_power_on, - }, - } -}; - -static struct resource lcdc_resources[] = { - [0] = { - .name = "LCDC", - .start = 0xfe940000, /* P4-only space */ - .end = 0xfe941fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device lcdc_device = { - .name = "sh_mobile_lcdc_fb", - .num_resources = ARRAY_SIZE(lcdc_resources), - .resource = lcdc_resources, - .dev = { - .platform_data = &lcdc_info, - }, -}; - -#ifdef CONFIG_I2C -static unsigned char camera_ncm03j_magic[] = -{ - 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, - 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36, - 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F, - 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55, - 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12, - 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0, - 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F, - 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A, - 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A, - 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A, - 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56, - 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37, - 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A, - 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56, - 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC, - 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, -}; - -static int camera_set_capture(struct soc_camera_platform_info *info, - int enable) -{ - struct i2c_adapter *a = i2c_get_adapter(0); - struct i2c_msg msg; - int ret = 0; - int i; - - if (!enable) - return 0; /* no disable for now */ - - for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) { - u_int8_t buf[8]; - - msg.addr = 0x6e; - msg.buf = buf; - msg.len = 2; - msg.flags = 0; - - buf[0] = camera_ncm03j_magic[i]; - buf[1] = camera_ncm03j_magic[i + 1]; - - ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1); - } - - return ret; -} - -static struct soc_camera_platform_info camera_info = { - .iface = 0, - .format_name = "UYVY", - .format_depth = 16, - .format = { - .pixelformat = V4L2_PIX_FMT_UYVY, - .colorspace = V4L2_COLORSPACE_SMPTE170M, - .width = 640, - .height = 480, - }, - .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | - SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, - .set_capture = camera_set_capture, -}; - -static struct platform_device camera_device = { - .name = "soc_camera_platform", - .dev = { - .platform_data = &camera_info, - }, -}; -#endif /* CONFIG_I2C */ - -static struct sh_mobile_ceu_info sh_mobile_ceu_info = { - .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | - SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, -}; - -static struct resource ceu_resources[] = { - [0] = { - .name = "CEU", - .start = 0xfe910000, - .end = 0xfe91009f, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 52, - .flags = IORESOURCE_IRQ, - }, - [2] = { - /* place holder for contiguous memory */ - }, -}; - -static struct platform_device ceu_device = { - .name = "sh_mobile_ceu", - .num_resources = ARRAY_SIZE(ceu_resources), - .resource = ceu_resources, - .dev = { - .platform_data = &sh_mobile_ceu_info, - }, -}; - -static struct platform_device *ap325rxa_devices[] __initdata = { - &smc9118_device, - &ap325rxa_nor_flash_device, - &lcdc_device, - &ceu_device, -#ifdef CONFIG_I2C - &camera_device, -#endif -}; - -static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = { -}; - -static int __init ap325rxa_devices_setup(void) -{ - clk_always_enable("mstp200"); /* LCDC */ - clk_always_enable("mstp203"); /* CEU */ - - platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); - - i2c_register_board_info(0, ap325rxa_i2c_devices, - ARRAY_SIZE(ap325rxa_i2c_devices)); - - return platform_add_devices(ap325rxa_devices, - ARRAY_SIZE(ap325rxa_devices)); -} -device_initcall(ap325rxa_devices_setup); - -static void __init ap325rxa_setup(char **cmdline_p) -{ - /* LCDC configuration */ - ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR); - ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR); - ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR); - ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR); - ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA); - - /* CEU */ - ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); - ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD); - ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR); - ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR); -} - -static struct sh_machine_vector mv_ap325rxa __initmv = { - .mv_name = "AP-325RXA", - .mv_setup = ap325rxa_setup, -}; diff --git a/arch/sh/boards/mach-magicpanelr2/Kconfig b/arch/sh/boards/mach-magicpanelr2/Kconfig deleted file mode 100644 index b0abddc3e84..00000000000 --- a/arch/sh/boards/mach-magicpanelr2/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if SH_MAGIC_PANEL_R2 - -menu "Magic Panel R2 options" - -config SH_MAGIC_PANEL_R2_VERSION - int SH_MAGIC_PANEL_R2_VERSION - default "3" - help - Set the version of the Magic Panel R2 - -endmenu - -endif diff --git a/arch/sh/boards/mach-magicpanelr2/Makefile b/arch/sh/boards/mach-magicpanelr2/Makefile deleted file mode 100644 index 7a6d586b907..00000000000 --- a/arch/sh/boards/mach-magicpanelr2/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Magic Panel specific parts -# - -obj-y := setup.o \ No newline at end of file diff --git a/arch/sh/boards/mach-magicpanelr2/setup.c b/arch/sh/boards/mach-magicpanelr2/setup.c deleted file mode 100644 index f3b8b07ea5d..00000000000 --- a/arch/sh/boards/mach-magicpanelr2/setup.c +++ /dev/null @@ -1,394 +0,0 @@ -/* - * linux/arch/sh/boards/magicpanel/setup.c - * - * Copyright (C) 2007 Markus Brunner, Mark Jonas - * - * Magic Panel Release 2 board setup - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL) - -/* Prefer cmdline over RedBoot */ -static const char *probes[] = { "cmdlinepart", "RedBoot", NULL }; - -/* Wait until reset finished. Timeout is 100ms. */ -static int __init ethernet_reset_finished(void) -{ - int i; - - if (LAN9115_READY) - return 1; - - for (i = 0; i < 10; ++i) { - mdelay(10); - if (LAN9115_READY) - return 1; - } - - return 0; -} - -static void __init reset_ethernet(void) -{ - /* PMDR: LAN_RESET=on */ - CLRBITS_OUTB(0x10, PORT_PMDR); - - udelay(200); - - /* PMDR: LAN_RESET=off */ - SETBITS_OUTB(0x10, PORT_PMDR); -} - -static void __init setup_chip_select(void) -{ - /* CS2: LAN (0x08000000 - 0x0bffffff) */ - /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x36db0400, CS2BCR); - /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x000003c0, CS2WCR); - - /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ - /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS4BCR); - /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS4WCR); - - /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ - /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS5ABCR); - /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS5AWCR); - - /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ - /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS5BBCR); - /* (SW:1.5 WR:3 HW:1.5), ext. wait */ - ctrl_outl(0x00100981, CS5BWCR); - - /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ - /* no idle cycles, normal space, 8 bit data bus */ - ctrl_outl(0x00000200, CS6ABCR); - /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ - ctrl_outl(0x001009C1, CS6AWCR); -} - -static void __init setup_port_multiplexing(void) -{ - /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); - * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); - */ - ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ - - /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); - * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); - */ - ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ - - /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); - * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; - */ - ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ - - /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); - * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); - */ - ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ - - /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; - * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; - */ - ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ - - /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; - * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); - */ - ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ - - /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); - * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); - */ - ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ - - /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); - * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; - */ - ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ - - /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; - * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; - */ - ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ - - /* K7 (x); K6 (x); K5 (x); K4 (x); - * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) - */ - ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ - - /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; - * L3 TCK; L2 (x); L1 (x); L0 (x); - */ - ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ - - /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); - * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); - * M1 CS5B(CAN3_CS); M0 GPI+(nc); - */ - ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ - - /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, - * LAN_RESET=off, BUZZER=off, LCD_BL=off - */ -#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 - ctrl_outb(0x30, PORT_PMDR); -#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 - ctrl_outb(0xF0, PORT_PMDR); -#else -#error Unknown revision of PLATFORM_MP_R2 -#endif - - /* P7 (x); P6 (x); P5 (x); - * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); - * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) - */ - ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ - ctrl_outb(0x10, PORT_PPDR); - - /* R7 A25; R6 A24; R5 A23; R4 A22; - * R3 A21; R2 A20; R1 A19; R0 A0; - */ - ctrl_outw(0x0000, PORT_PRCR); /* 00 00 00 00 00 00 00 00 */ - - /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); - * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; - */ - ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ - - /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; - * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) - */ - ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ - - /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); - * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; - */ - ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ - - /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); - * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); - */ - ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ -} - -static void __init mpr2_setup(char **cmdline_p) -{ - __set_io_port_base(0xa0000000); - - /* set Pin Select Register A: - * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, - * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND - */ - ctrl_outw(0xAABC, PORT_PSELA); - /* set Pin Select Register B: - * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, - * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved - */ - ctrl_outw(0x3C00, PORT_PSELB); - /* set Pin Select Register C: - * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved - */ - ctrl_outw(0x0000, PORT_PSELC); - /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, - * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved - */ - ctrl_outw(0x0000, PORT_PSELD); - /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ - ctrl_outw(0x0101, PORT_UTRCTL); - /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ - ctrl_outw(0xA5C0, PORT_UCLKCR_W); - - setup_chip_select(); - - setup_port_multiplexing(); - - reset_ethernet(); - - printk(KERN_INFO "Magic Panel Release 2 A.%i\n", - CONFIG_SH_MAGIC_PANEL_R2_VERSION); - - if (ethernet_reset_finished() == 0) - printk(KERN_WARNING "Ethernet not ready\n"); -} - -static struct resource smc911x_resources[] = { - [0] = { - .start = 0xa8000000, - .end = 0xabffffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 35, - .end = 35, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc911x_device = { - .name = "smc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smc911x_resources), - .resource = smc911x_resources, -}; - -static struct resource heartbeat_resources[] = { - [0] = { - .start = PA_LED, - .end = PA_LED, - .flags = IORESOURCE_MEM, - }, -}; - -static struct heartbeat_data heartbeat_data = { - .flags = HEARTBEAT_INVERTED, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .dev = { - .platform_data = &heartbeat_data, - }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct mtd_partition *parsed_partitions; - -static struct mtd_partition mpr2_partitions[] = { - /* Reserved for bootloader, read-only */ - { - .name = "Bootloader", - .offset = 0x00000000UL, - .size = MPR2_MTD_BOOTLOADER_SIZE, - .mask_flags = MTD_WRITEABLE, - }, - /* Reserved for kernel image */ - { - .name = "Kernel", - .offset = MTDPART_OFS_NXTBLK, - .size = MPR2_MTD_KERNEL_SIZE, - }, - /* Rest is used for Flash FS */ - { - .name = "Flash_FS", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - } -}; - -static struct physmap_flash_data flash_data = { - .width = 2, -}; - -static struct resource flash_resource = { - .start = 0x00000000, - .end = 0x2000000UL, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device flash_device = { - .name = "physmap-flash", - .id = -1, - .resource = &flash_resource, - .num_resources = 1, - .dev = { - .platform_data = &flash_data, - }, -}; - -static struct mtd_info *flash_mtd; - -static struct map_info mpr2_flash_map = { - .name = "Magic Panel R2 Flash", - .size = 0x2000000UL, - .bankwidth = 2, -}; - -static void __init set_mtd_partitions(void) -{ - int nr_parts = 0; - - simple_map_init(&mpr2_flash_map); - flash_mtd = do_map_probe("cfi_probe", &mpr2_flash_map); - nr_parts = parse_mtd_partitions(flash_mtd, probes, - &parsed_partitions, 0); - /* If there is no partition table, used the hard coded table */ - if (nr_parts <= 0) { - flash_data.parts = mpr2_partitions; - flash_data.nr_parts = ARRAY_SIZE(mpr2_partitions); - } else { - flash_data.nr_parts = nr_parts; - flash_data.parts = parsed_partitions; - } -} - -/* - * Add all resources to the platform_device - */ - -static struct platform_device *mpr2_devices[] __initdata = { - &heartbeat_device, - &smc911x_device, - &flash_device, -}; - - -static int __init mpr2_devices_setup(void) -{ - set_mtd_partitions(); - return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); -} -device_initcall(mpr2_devices_setup); - -/* - * Initialize IRQ setting - */ -static void __init init_mpr2_IRQ(void) -{ - plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ - - set_irq_type(32, IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ - set_irq_type(33, IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ - set_irq_type(34, IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ - set_irq_type(35, IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ - set_irq_type(36, IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ - set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ - - intc_set_priority(32, 13); /* IRQ0 CAN1 */ - intc_set_priority(33, 13); /* IRQ0 CAN2 */ - intc_set_priority(34, 13); /* IRQ0 CAN3 */ - intc_set_priority(35, 6); /* IRQ3 SMSC9115 */ -} - -/* - * The Machine Vector - */ - -static struct sh_machine_vector mv_mpr2 __initmv = { - .mv_name = "mpr2", - .mv_setup = mpr2_setup, - .mv_init_irq = init_mpr2_IRQ, -}; diff --git a/arch/sh/boards/mach-rsk7203/Makefile b/arch/sh/boards/mach-rsk7203/Makefile deleted file mode 100644 index f663768429f..00000000000 --- a/arch/sh/boards/mach-rsk7203/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := setup.o diff --git a/arch/sh/boards/mach-rsk7203/setup.c b/arch/sh/boards/mach-rsk7203/setup.c deleted file mode 100644 index ffbedc59a97..00000000000 --- a/arch/sh/boards/mach-rsk7203/setup.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Renesas Technology Europe RSK+ 7203 Support. - * - * Copyright (C) 2008 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct smc911x_platdata smc911x_info = { - .flags = SMC911X_USE_16BIT, - .irq_flags = IRQF_TRIGGER_LOW, -}; - -static struct resource smc911x_resources[] = { - [0] = { - .start = 0x24000000, - .end = 0x24000000 + 0x100, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = 64, - .end = 64, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smc911x_device = { - .name = "smc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smc911x_resources), - .resource = smc911x_resources, - .dev = { - .platform_data = &smc911x_info, - }, -}; - -static const char *probes[] = { "cmdlinepart", NULL }; - -static struct mtd_partition *parsed_partitions; - -static struct mtd_partition rsk7203_partitions[] = { - { - .name = "Bootloader", - .offset = 0x00000000, - .size = 0x00040000, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "Kernel", - .offset = MTDPART_OFS_NXTBLK, - .size = 0x001c0000, - }, { - .name = "Flash_FS", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL, - } -}; - -static struct physmap_flash_data flash_data = { - .width = 2, -}; - -static struct resource flash_resource = { - .start = 0x20000000, - .end = 0x20400000, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device flash_device = { - .name = "physmap-flash", - .id = -1, - .resource = &flash_resource, - .num_resources = 1, - .dev = { - .platform_data = &flash_data, - }, -}; - -static struct mtd_info *flash_mtd; - -static struct map_info rsk7203_flash_map = { - .name = "RSK+ Flash", - .size = 0x400000, - .bankwidth = 2, -}; - -static void __init set_mtd_partitions(void) -{ - int nr_parts = 0; - - simple_map_init(&rsk7203_flash_map); - flash_mtd = do_map_probe("cfi_probe", &rsk7203_flash_map); - nr_parts = parse_mtd_partitions(flash_mtd, probes, - &parsed_partitions, 0); - /* If there is no partition table, used the hard coded table */ - if (nr_parts <= 0) { - flash_data.parts = rsk7203_partitions; - flash_data.nr_parts = ARRAY_SIZE(rsk7203_partitions); - } else { - flash_data.nr_parts = nr_parts; - flash_data.parts = parsed_partitions; - } -} - - -static struct platform_device *rsk7203_devices[] __initdata = { - &smc911x_device, - &flash_device, -}; - -static int __init rsk7203_devices_setup(void) -{ - set_mtd_partitions(); - return platform_add_devices(rsk7203_devices, - ARRAY_SIZE(rsk7203_devices)); -} -device_initcall(rsk7203_devices_setup); - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_rsk7203 __initmv = { - .mv_name = "RSK+7203", -}; diff --git a/arch/sh/boards/mach-se/7619/Makefile b/arch/sh/boards/mach-se/7619/Makefile deleted file mode 100644 index d21775c28cd..00000000000 --- a/arch/sh/boards/mach-se/7619/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the 7619 SolutionEngine specific parts of the kernel -# - -obj-y := setup.o diff --git a/arch/sh/boards/mach-se/7619/setup.c b/arch/sh/boards/mach-se/7619/setup.c deleted file mode 100644 index 1d0ef7faa10..00000000000 --- a/arch/sh/boards/mach-se/7619/setup.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * arch/sh/boards/se/7619/setup.c - * - * Copyright (C) 2006 Yoshinori Sato - * - * Hitachi SH7619 SolutionEngine Support. - */ - -#include -#include -#include -#include - -/* - * The Machine Vector - */ - -static struct sh_machine_vector mv_se __initmv = { - .mv_name = "SolutionEngine", - .mv_nr_irqs = 108, -}; diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile index ad2b38ef65d..2de42bae4b4 100644 --- a/arch/sh/boards/mach-se/Makefile +++ b/arch/sh/boards/mach-se/Makefile @@ -1,6 +1,7 @@ +obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += board-se7619.o + obj-$(CONFIG_SH_SOLUTION_ENGINE) += 770x/ obj-$(CONFIG_SH_7206_SOLUTION_ENGINE) += 7206/ -obj-$(CONFIG_SH_7619_SOLUTION_ENGINE) += 7619/ obj-$(CONFIG_SH_7722_SOLUTION_ENGINE) += 7722/ obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/ obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ diff --git a/arch/sh/boards/mach-se/board-se7619.c b/arch/sh/boards/mach-se/board-se7619.c new file mode 100644 index 00000000000..1d0ef7faa10 --- /dev/null +++ b/arch/sh/boards/mach-se/board-se7619.c @@ -0,0 +1,21 @@ +/* + * arch/sh/boards/se/7619/setup.c + * + * Copyright (C) 2006 Yoshinori Sato + * + * Hitachi SH7619 SolutionEngine Support. + */ + +#include +#include +#include +#include + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_se __initmv = { + .mv_name = "SolutionEngine", + .mv_nr_irqs = 108, +}; diff --git a/arch/sh/boards/mach-sh7785lcr/Makefile b/arch/sh/boards/mach-sh7785lcr/Makefile deleted file mode 100644 index 77037567633..00000000000 --- a/arch/sh/boards/mach-sh7785lcr/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := setup.o diff --git a/arch/sh/boards/mach-sh7785lcr/setup.c b/arch/sh/boards/mach-sh7785lcr/setup.c deleted file mode 100644 index b95d674ee70..00000000000 --- a/arch/sh/boards/mach-sh7785lcr/setup.c +++ /dev/null @@ -1,302 +0,0 @@ -/* - * Renesas Technology Corp. R0P7785LC0011RL Support. - * - * Copyright (C) 2008 Yoshihiro Shimoda - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * NOTE: This board has 2 physical memory maps. - * Please look at include/asm-sh/sh7785lcr.h or hardware manual. - */ -static struct resource heartbeat_resources[] = { - [0] = { - .start = PLD_LEDCR, - .end = PLD_LEDCR, - .flags = IORESOURCE_MEM, - }, -}; - -static struct heartbeat_data heartbeat_data = { - .regsize = 8, -}; - -static struct platform_device heartbeat_device = { - .name = "heartbeat", - .id = -1, - .dev = { - .platform_data = &heartbeat_data, - }, - .num_resources = ARRAY_SIZE(heartbeat_resources), - .resource = heartbeat_resources, -}; - -static struct mtd_partition nor_flash_partitions[] = { - { - .name = "loader", - .offset = 0x00000000, - .size = 512 * 1024, - }, - { - .name = "bootenv", - .offset = MTDPART_OFS_APPEND, - .size = 512 * 1024, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 4 * 1024 * 1024, - }, - { - .name = "data", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct physmap_flash_data nor_flash_data = { - .width = 4, - .parts = nor_flash_partitions, - .nr_parts = ARRAY_SIZE(nor_flash_partitions), -}; - -static struct resource nor_flash_resources[] = { - [0] = { - .start = NOR_FLASH_ADDR, - .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device nor_flash_device = { - .name = "physmap-flash", - .dev = { - .platform_data = &nor_flash_data, - }, - .num_resources = ARRAY_SIZE(nor_flash_resources), - .resource = nor_flash_resources, -}; - -static struct resource r8a66597_usb_host_resources[] = { - [0] = { - .name = "r8a66597_hcd", - .start = R8A66597_ADDR, - .end = R8A66597_ADDR + R8A66597_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .name = "r8a66597_hcd", - .start = 2, - .end = 2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device r8a66597_usb_host_device = { - .name = "r8a66597_hcd", - .id = -1, - .dev = { - .dma_mask = NULL, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), - .resource = r8a66597_usb_host_resources, -}; - -static struct resource sm501_resources[] = { - [0] = { - .start = SM107_MEM_ADDR, - .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SM107_REG_ADDR, - .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = 10, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct fb_videomode sm501_default_mode_crt = { - .pixclock = 35714, /* 28MHz */ - .xres = 640, - .yres = 480, - .left_margin = 105, - .right_margin = 16, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 39, - .vsync_len = 2, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -}; - -static struct fb_videomode sm501_default_mode_pnl = { - .pixclock = 40000, /* 25MHz */ - .xres = 640, - .yres = 480, - .left_margin = 2, - .right_margin = 16, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 39, - .vsync_len = 2, - .sync = 0, -}; - -static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { - .def_bpp = 16, - .def_mode = &sm501_default_mode_pnl, - .flags = SM501FB_FLAG_USE_INIT_MODE | - SM501FB_FLAG_USE_HWCURSOR | - SM501FB_FLAG_USE_HWACCEL | - SM501FB_FLAG_DISABLE_AT_EXIT | - SM501FB_FLAG_PANEL_NO_VBIASEN, -}; - -static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { - .def_bpp = 16, - .def_mode = &sm501_default_mode_crt, - .flags = SM501FB_FLAG_USE_INIT_MODE | - SM501FB_FLAG_USE_HWCURSOR | - SM501FB_FLAG_USE_HWACCEL | - SM501FB_FLAG_DISABLE_AT_EXIT, -}; - -static struct sm501_platdata_fb sm501_fb_pdata = { - .fb_route = SM501_FB_OWN, - .fb_crt = &sm501_pdata_fbsub_crt, - .fb_pnl = &sm501_pdata_fbsub_pnl, -}; - -static struct sm501_initdata sm501_initdata = { - .gpio_high = { - .set = 0x00001fe0, - .mask = 0x0, - }, - .devices = 0, - .mclk = 84 * 1000000, - .m1xclk = 112 * 1000000, -}; - -static struct sm501_platdata sm501_platform_data = { - .init = &sm501_initdata, - .fb = &sm501_fb_pdata, -}; - -static struct platform_device sm501_device = { - .name = "sm501", - .id = -1, - .dev = { - .platform_data = &sm501_platform_data, - }, - .num_resources = ARRAY_SIZE(sm501_resources), - .resource = sm501_resources, -}; - -static struct resource i2c_resources[] = { - [0] = { - .start = PCA9564_ADDR, - .end = PCA9564_ADDR + PCA9564_SIZE - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, - }, - [1] = { - .start = 12, - .end = 12, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct i2c_pca9564_pf_platform_data i2c_platform_data = { - .gpio = 0, - .i2c_clock_speed = I2C_PCA_CON_330kHz, - .timeout = 100, -}; - -static struct platform_device i2c_device = { - .name = "i2c-pca-platform", - .id = -1, - .dev = { - .platform_data = &i2c_platform_data, - }, - .num_resources = ARRAY_SIZE(i2c_resources), - .resource = i2c_resources, -}; - -static struct platform_device *sh7785lcr_devices[] __initdata = { - &heartbeat_device, - &nor_flash_device, - &r8a66597_usb_host_device, - &sm501_device, - &i2c_device, -}; - -static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { - { - I2C_BOARD_INFO("r2025sd", 0x32), - }, -}; - -static int __init sh7785lcr_devices_setup(void) -{ - i2c_register_board_info(0, sh7785lcr_i2c_devices, - ARRAY_SIZE(sh7785lcr_i2c_devices)); - - return platform_add_devices(sh7785lcr_devices, - ARRAY_SIZE(sh7785lcr_devices)); -} -__initcall(sh7785lcr_devices_setup); - -/* Initialize IRQ setting */ -void __init init_sh7785lcr_IRQ(void) -{ - plat_irq_setup_pins(IRQ_MODE_IRQ7654); - plat_irq_setup_pins(IRQ_MODE_IRQ3210); -} - -static void sh7785lcr_power_off(void) -{ - ctrl_outb(0x01, P2SEGADDR(PLD_POFCR)); -} - -/* Initialize the board */ -static void __init sh7785lcr_setup(char **cmdline_p) -{ - void __iomem *sm501_reg; - - printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); - - pm_power_off = sh7785lcr_power_off; - - /* sm501 DRAM configuration */ - sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; - writel(0x000307c2, sm501_reg); -} - -/* - * The Machine Vector - */ -static struct sh_machine_vector mv_sh7785lcr __initmv = { - .mv_name = "SH7785LCR", - .mv_setup = sh7785lcr_setup, - .mv_init_irq = init_sh7785lcr_IRQ, -}; - diff --git a/arch/sh/boards/mach-shmin/Makefile b/arch/sh/boards/mach-shmin/Makefile deleted file mode 100644 index 3190cc72430..00000000000 --- a/arch/sh/boards/mach-shmin/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the SHMIN board. -# - -obj-y := setup.o diff --git a/arch/sh/boards/mach-shmin/setup.c b/arch/sh/boards/mach-shmin/setup.c deleted file mode 100644 index 16e5dae8ecf..00000000000 --- a/arch/sh/boards/mach-shmin/setup.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * arch/sh/boards/shmin/setup.c - * - * Copyright (C) 2006 Takashi YOSHII - * - * SHMIN Support. - */ -#include -#include -#include -#include -#include -#include - -#define PFC_PHCR 0xa400010eUL -#define INTC_ICR1 0xa4000010UL - -static void __init init_shmin_irq(void) -{ - ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ - ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. - plat_irq_setup_pins(IRQ_MODE_IRQ); -} - -static void __iomem *shmin_ioport_map(unsigned long port, unsigned int size) -{ - static int dummy; - - if ((port & ~0x1f) == SHMIN_NE_BASE) - return (void __iomem *)(SHMIN_IO_BASE + port); - - dummy = 0; - - return &dummy; - -} - -static struct sh_machine_vector mv_shmin __initmv = { - .mv_name = "SHMIN", - .mv_init_irq = init_shmin_irq, - .mv_ioport_map = shmin_ioport_map, -}; -- cgit v1.2.3-70-g09d2 From c48e64ae574a1e30a23174701560a222a192e4c3 Mon Sep 17 00:00:00 2001 From: Huang Weiyi Date: Sun, 3 Aug 2008 22:18:51 +0800 Subject: arch/sh/boards/mach-se/7343/irq.c: removed duplicated #include Removed duplicated include in arch/sh/boards/mach-se/7343/irq.c. Signed-off-by: Huang Weiyi Signed-off-by: Paul Mundt --- arch/sh/boards/mach-se/7343/irq.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/sh/boards/mach-se') diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c index 5d96e2eef82..051c29d4eae 100644 --- a/arch/sh/boards/mach-se/7343/irq.c +++ b/arch/sh/boards/mach-se/7343/irq.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3-70-g09d2