From b67360db143448be1f6d68835c6d0cc43837667f Mon Sep 17 00:00:00 2001 From: Chris Zankel Date: Thu, 6 Sep 2007 01:38:18 -0700 Subject: [XTENSA] Flush the page-address in update-mmu instead of user-address The TLB entry for the user address doesn't exist at the time we want to flush the caches, so use the page address. Note that processor configurations with cache-aliasing issues are treated separately. Signed-off-by: Chris Zankel --- arch/xtensa/mm/cache.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/xtensa') diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c index 42bfb695a17..3ba990c6767 100644 --- a/arch/xtensa/mm/cache.c +++ b/arch/xtensa/mm/cache.c @@ -180,9 +180,9 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte) #else if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags) && (vma->vm_flags & VM_EXEC) != 0) { - unsigned long vaddr = addr & PAGE_MASK; - __flush_dcache_page(vaddr); - __invalidate_icache_page(vaddr); + unsigned long paddr = (unsigned long) page_address(page); + __flush_dcache_page(paddr); + __invalidate_icache_page(paddr); set_bit(PG_arch_1, &page->flags); } #endif -- cgit v1.2.3-70-g09d2