From a91549a8f27e63e0e537fe1c20d4845581de894f Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:54 -0700 Subject: iop: clocksource support This updates the IOP platform to expose the free-running timer 1 as a clocksource object. This timer is now also properly initialised, which requires a new write_tcr1() function from the mach-specific code. Apart from the explicit initialisation, there is no functional change in how timer 1 is programmed. Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/include/asm/hardware/iop3xx.h | 5 ++++ arch/arm/mach-iop13xx/include/mach/time.h | 5 ++++ arch/arm/plat-iop/time.c | 45 +++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 8d60ad267e3..643b7b95b25 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -260,6 +260,11 @@ static inline u32 read_tcr1(void) return val; } +static inline void write_tcr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); +} + static inline void write_trr0(u32 val) { asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h index d6d52527589..9fb2768c84b 100644 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ b/arch/arm/mach-iop13xx/include/mach/time.h @@ -90,6 +90,11 @@ static inline u32 read_tcr1(void) return val; } +static inline void write_tcr1(u32 val) +{ + asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); +} + static inline void write_trr0(u32 val) { asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 8da95d57c21..5506c9b4561 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,43 @@ #include #include +/* + * IOP clocksource (free-running timer 1). + */ +static cycle_t iop_clocksource_read(struct clocksource *unused) +{ + return 0xffffffffu - read_tcr1(); +} + +static struct clocksource iop_clocksource = { + .name = "iop_timer1", + .rating = 300, + .read = iop_clocksource_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz) +{ + u64 temp; + u32 shift; + + /* Find shift and mult values for hz. */ + shift = 32; + do { + temp = (u64) NSEC_PER_SEC << shift; + do_div(temp, hz); + if ((temp >> 32) == 0) + break; + } while (--shift != 0); + + cs->shift = shift; + cs->mult = (u32) temp; + + printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n", + cs->name, cs->shift, cs->mult); +} + static unsigned long ticks_per_jiffy; static unsigned long ticks_per_usec; static unsigned long next_jiffy_time; @@ -99,8 +137,15 @@ void __init iop_init_time(unsigned long tick_rate) */ write_trr0(ticks_per_jiffy - 1); write_tmr0(timer_ctl); + + /* + * Set up free-running clocksource timer 1. + */ write_trr1(0xffffffff); + write_tcr1(0xffffffff); write_tmr1(timer_ctl); + iop_clocksource_set_hz(&iop_clocksource, tick_rate); + clocksource_register(&iop_clocksource); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); } -- cgit v1.2.3-70-g09d2 From 469d30448dad13600cdd246024f9db8e80614c45 Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:54 -0700 Subject: iop: clockevent support This updates the IOP platform to expose the interrupting timer 0 as a clockevent object. The timer interrupt handler is changed to call the clockevent ->event_handler() instead of timer_tick(), and ->set_next_event() and ->set_mode() operations are added to allow the mode of the timer to be updated (required for ONESHOT/NOHZ mode). Timer 0 must now be properly initialised, which requires a new write_tcr0() function from the mach-specific code. The mode of timer 0 must be read at the start of ->set_mode(), which requires a new read_tmr0() function from the mach- specific code. Initial setup of timer 0 is also rewritten to be more robust. Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/Kconfig | 1 + arch/arm/include/asm/hardware/iop3xx.h | 12 ++++ arch/arm/mach-iop13xx/include/mach/time.h | 12 ++++ arch/arm/plat-iop/time.c | 101 ++++++++++++++++++++++++++---- 4 files changed, 115 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1c4119c6004..e732fcc3052 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -810,6 +810,7 @@ config ARCH_ACORN config PLAT_IOP bool + select GENERIC_CLOCKEVENTS config PLAT_ORION bool diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 643b7b95b25..34601b95204 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -236,6 +236,13 @@ void iop_init_cp6_handler(void); void iop_init_time(unsigned long tickrate); unsigned long iop_gettimeoffset(void); +static inline u32 read_tmr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); + return val; +} + static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); @@ -253,6 +260,11 @@ static inline u32 read_tcr0(void) return val; } +static inline void write_tcr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); +} + static inline u32 read_tcr1(void) { u32 val; diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h index 9fb2768c84b..b2fb17b3542 100644 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ b/arch/arm/mach-iop13xx/include/mach/time.h @@ -66,6 +66,13 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void) return 2; } +static inline u32 read_tmr0(void) +{ + u32 val; + asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); + return val; +} + static inline void write_tmr0(u32 val) { asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); @@ -83,6 +90,11 @@ static inline u32 read_tcr0(void) return val; } +static inline void write_tcr0(u32 val) +{ + asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); +} + static inline u32 read_tcr1(void) { u32 val; diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 5506c9b4561..a550e96394a 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -64,7 +65,81 @@ static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int h cs->name, cs->shift, cs->mult); } +/* + * IOP clockevents (interrupting timer 0). + */ +static int iop_set_next_event(unsigned long delta, + struct clock_event_device *unused) +{ + u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; + + BUG_ON(delta == 0); + write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); + write_tcr0(delta); + write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); + + return 0; +} + static unsigned long ticks_per_jiffy; + +static void iop_set_mode(enum clock_event_mode mode, + struct clock_event_device *unused) +{ + u32 tmr = read_tmr0(); + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + write_tmr0(tmr & ~IOP_TMR_EN); + write_tcr0(ticks_per_jiffy - 1); + tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); + break; + case CLOCK_EVT_MODE_ONESHOT: + /* ->set_next_event sets period and enables timer */ + tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); + break; + case CLOCK_EVT_MODE_RESUME: + tmr |= IOP_TMR_EN; + break; + case CLOCK_EVT_MODE_SHUTDOWN: + case CLOCK_EVT_MODE_UNUSED: + default: + tmr &= ~IOP_TMR_EN; + break; + } + + write_tmr0(tmr); +} + +static struct clock_event_device iop_clockevent = { + .name = "iop_timer0", + .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, + .rating = 300, + .set_next_event = iop_set_next_event, + .set_mode = iop_set_mode, +}; + +static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz) +{ + u64 temp; + u32 shift; + + /* Find shift and mult values for hz. */ + shift = 32; + do { + temp = (u64) hz << shift; + do_div(temp, NSEC_PER_SEC); + if ((temp >> 32) == 0) + break; + } while (--shift != 0); + + ce->shift = shift; + ce->mult = (u32) temp; + + printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n", + ce->name, ce->shift, ce->mult); +} + static unsigned long ticks_per_usec; static unsigned long next_jiffy_time; @@ -95,14 +170,10 @@ unsigned long iop_gettimeoffset(void) static irqreturn_t iop_timer_interrupt(int irq, void *dev_id) { - write_tisr(1); - - while ((signed long)(next_jiffy_time - read_tcr1()) - >= ticks_per_jiffy) { - timer_tick(); - next_jiffy_time -= ticks_per_jiffy; - } + struct clock_event_device *evt = dev_id; + write_tisr(1); + evt->event_handler(evt); return IRQ_HANDLED; } @@ -110,6 +181,7 @@ static struct irqaction iop_timer_irq = { .name = "IOP Timer Tick", .handler = iop_timer_interrupt, .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .dev_id = &iop_clockevent, }; static unsigned long iop_tick_rate; @@ -132,10 +204,19 @@ void __init iop_init_time(unsigned long tick_rate) IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; /* - * We use timer 0 for our timer interrupt, and timer 1 as - * monotonic counter for tracking missed jiffies. + * Set up interrupting clockevent timer 0. */ + write_tmr0(timer_ctl & ~IOP_TMR_EN); + setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); + iop_clockevent_set_hz(&iop_clockevent, tick_rate); + iop_clockevent.max_delta_ns = + clockevent_delta2ns(0xfffffffe, &iop_clockevent); + iop_clockevent.min_delta_ns = + clockevent_delta2ns(0xf, &iop_clockevent); + iop_clockevent.cpumask = cpumask_of(0); + clockevents_register_device(&iop_clockevent); write_trr0(ticks_per_jiffy - 1); + write_tcr0(ticks_per_jiffy - 1); write_tmr0(timer_ctl); /* @@ -146,6 +227,4 @@ void __init iop_init_time(unsigned long tick_rate) write_tmr1(timer_ctl); iop_clocksource_set_hz(&iop_clocksource, tick_rate); clocksource_register(&iop_clocksource); - - setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); } -- cgit v1.2.3-70-g09d2 From 980f2296b5a8dfe589f023fd34229dcfdcf280fa Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:55 -0700 Subject: iop: enable generic time This updates the IOP platform to use the kernel's generic time framework. With clockevent support in place, this reduces to selecting GENERIC_TIME and removing the platform's private timer ->offset() operation (iop_gettimeoffset). Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/Kconfig | 1 + arch/arm/include/asm/hardware/iop3xx.h | 1 - arch/arm/mach-iop13xx/include/mach/time.h | 1 - arch/arm/mach-iop13xx/iq81340mc.c | 1 - arch/arm/mach-iop13xx/iq81340sc.c | 1 - arch/arm/mach-iop32x/em7210.c | 1 - arch/arm/mach-iop32x/glantank.c | 1 - arch/arm/mach-iop32x/iq31244.c | 1 - arch/arm/mach-iop32x/iq80321.c | 1 - arch/arm/mach-iop32x/n2100.c | 1 - arch/arm/mach-iop33x/iq80331.c | 1 - arch/arm/mach-iop33x/iq80332.c | 1 - arch/arm/plat-iop/time.c | 29 ----------------------------- 13 files changed, 1 insertion(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e732fcc3052..455284edda2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -811,6 +811,7 @@ config ARCH_ACORN config PLAT_IOP bool select GENERIC_CLOCKEVENTS + select GENERIC_TIME config PLAT_ORION bool diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 34601b95204..5daea2961d4 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h @@ -234,7 +234,6 @@ extern int iop3xx_get_init_atu(void); void iop3xx_map_io(void); void iop_init_cp6_handler(void); void iop_init_time(unsigned long tickrate); -unsigned long iop_gettimeoffset(void); static inline u32 read_tmr0(void) { diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h index b2fb17b3542..f1c00d6d560 100644 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ b/arch/arm/mach-iop13xx/include/mach/time.h @@ -20,7 +20,6 @@ #define IOP13XX_CORE_FREQ_1200 (5 << 16) void iop_init_time(unsigned long tickrate); -unsigned long iop_gettimeoffset(void); static inline unsigned long iop13xx_core_freq(void) { diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 5051c03d437..f91f3154577 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c @@ -87,7 +87,6 @@ static void __init iq81340mc_timer_init(void) static struct sys_timer iq81340mc_timer = { .init = iq81340mc_timer_init, - .offset = iop_gettimeoffset, }; MACHINE_START(IQ81340MC, "Intel IQ81340MC") diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index bc443073a8e..ddb7a3435de 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c @@ -89,7 +89,6 @@ static void __init iq81340sc_timer_init(void) static struct sys_timer iq81340sc_timer = { .init = iq81340sc_timer_init, - .offset = iop_gettimeoffset, }; MACHINE_START(IQ81340SC, "Intel IQ81340SC") diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 3ad4696ade4..2bef9b6e1cc 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c @@ -42,7 +42,6 @@ static void __init em7210_timer_init(void) static struct sys_timer em7210_timer = { .init = em7210_timer_init, - .offset = iop_gettimeoffset, }; /* diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index a9c2dfdb250..93370a46b62 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c @@ -47,7 +47,6 @@ static void __init glantank_timer_init(void) static struct sys_timer glantank_timer = { .init = glantank_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index dd1cd990451..a7a08dda7f3 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c @@ -78,7 +78,6 @@ static void __init iq31244_timer_init(void) static struct sys_timer iq31244_timer = { .init = iq31244_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index fbe27798759..0200f80c1e1 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c @@ -46,7 +46,6 @@ static void __init iq80321_timer_init(void) static struct sys_timer iq80321_timer = { .init = iq80321_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index d2e42789972..2a5c637639b 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c @@ -53,7 +53,6 @@ static void __init n2100_timer_init(void) static struct sys_timer n2100_timer = { .init = n2100_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index d51e10cddf2..394e95a30b7 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c @@ -48,7 +48,6 @@ static void __init iq80331_timer_init(void) static struct sys_timer iq80331_timer = { .init = iq80331_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 92fb44cdbca..a40badf126c 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c @@ -48,7 +48,6 @@ static void __init iq80332_timer_init(void) static struct sys_timer iq80332_timer = { .init = iq80332_timer_init, - .offset = iop_gettimeoffset, }; diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index a550e96394a..aaaef3b4bc6 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -140,33 +140,6 @@ static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned ce->name, ce->shift, ce->mult); } -static unsigned long ticks_per_usec; -static unsigned long next_jiffy_time; - -unsigned long iop_gettimeoffset(void) -{ - unsigned long offset, temp; - - /* enable cp6, if necessary, to avoid taking the overhead of an - * undefined instruction trap - */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "tst %0, #(1 << 6)\n\t" - "orreq %0, %0, #(1 << 6)\n\t" - "mcreq p15, 0, %0, c15, c1, 0\n\t" -#ifdef CONFIG_CPU_XSCALE - "mrceq p15, 0, %0, c15, c1, 0\n\t" - "moveq %0, %0\n\t" - "subeq pc, pc, #4\n\t" -#endif - : "=r"(temp) : : "cc"); - - offset = next_jiffy_time - read_tcr1(); - - return offset / ticks_per_usec; -} - static irqreturn_t iop_timer_interrupt(int irq, void *dev_id) { @@ -196,8 +169,6 @@ void __init iop_init_time(unsigned long tick_rate) u32 timer_ctl; ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); - ticks_per_usec = tick_rate / 1000000; - next_jiffy_time = 0xffffffff; iop_tick_rate = tick_rate; timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | -- cgit v1.2.3-70-g09d2 From 345a32296b1f9f6121379e0240915e0e2be2dbf5 Mon Sep 17 00:00:00 2001 From: Mikael Pettersson Date: Thu, 29 Oct 2009 11:46:56 -0700 Subject: iop: implement sched_clock() This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-iop machines. [dan.j.williams@intel.com: allow early cp6 access] Signed-off-by: Mikael Pettersson Signed-off-by: Dan Williams --- arch/arm/mm/proc-xsc3.S | 2 +- arch/arm/plat-iop/time.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 2028f370288..fab134e2982 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -396,7 +396,7 @@ __xsc3_setup: orr r4, r4, #0x18 @ cache the page table in L2 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer - mov r0, #0 @ don't allow CP access + mov r0, #1 << 6 @ cp6 access for early sched_clock mcr p15, 0, r0, c15, c1, 0 @ write CP access register mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index aaaef3b4bc6..6c8a02ad98e 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c @@ -65,6 +65,17 @@ static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int h cs->name, cs->shift, cs->mult); } +/* + * IOP sched_clock() implementation via its clocksource. + */ +unsigned long long sched_clock(void) +{ + cycle_t cyc = iop_clocksource_read(NULL); + struct clocksource *cs = &iop_clocksource; + + return clocksource_cyc2ns(cyc, cs->mult, cs->shift); +} + /* * IOP clockevents (interrupting timer 0). */ -- cgit v1.2.3-70-g09d2 From f3a131b90b8f9bbcf46edc3bdd5246a744ba0017 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Thu, 5 Nov 2009 17:45:32 +0000 Subject: [ARM] Kirkwood: Add support for QNAP TS-41x Turbo NAS Add support for the QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS. Signed-off-by: Martin Michlmayr Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Kconfig | 7 + arch/arm/mach-kirkwood/Makefile | 1 + arch/arm/mach-kirkwood/ts41x-setup.c | 253 +++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 arch/arm/mach-kirkwood/ts41x-setup.c (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 0aca451b216..d58e8b0febe 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -38,6 +38,13 @@ config MACH_TS219 Say 'Y' here if you want your kernel to support the QNAP TS-119 and TS-219 Turbo NAS devices. +config MACH_TS41X + bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" + help + Say 'Y' here if you want your kernel to support the + QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS + devices. + config MACH_OPENRD_BASE bool "Marvell OpenRD Base Board" help diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 80ab0ec90ee..0c79cedfa64 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o +obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c new file mode 100644 index 00000000000..a1972c94850 --- /dev/null +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -0,0 +1,253 @@ +/* + * + * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup + * + * Copyright (C) 2009 Martin Michlmayr + * Copyright (C) 2008 Byron Bradley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "mpp.h" + +/**************************************************************************** + * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the + * partitions on the device because we want to keep compatability with + * the QNAP firmware. + * Layout as used by QNAP: + * 0x00000000-0x00080000 : "U-Boot" + * 0x00200000-0x00400000 : "Kernel" + * 0x00400000-0x00d00000 : "RootFS" + * 0x00d00000-0x01000000 : "RootFS2" + * 0x00080000-0x000c0000 : "U-Boot Config" + * 0x000c0000-0x00200000 : "NAS Config" + * + * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout + * used by the QNAP TS-109/TS-209. + * + ***************************************************************************/ + +static struct mtd_partition qnap_ts41x_partitions[] = { + { + .name = "U-Boot", + .size = 0x00080000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0x00200000, + }, { + .name = "RootFS1", + .size = 0x00900000, + .offset = 0x00400000, + }, { + .name = "RootFS2", + .size = 0x00300000, + .offset = 0x00d00000, + }, { + .name = "U-Boot Config", + .size = 0x00040000, + .offset = 0x00080000, + }, { + .name = "NAS Config", + .size = 0x00140000, + .offset = 0x000c0000, + }, +}; + +static const struct flash_platform_data qnap_ts41x_flash = { + .type = "m25p128", + .name = "spi_flash", + .parts = qnap_ts41x_partitions, + .nr_parts = ARRAY_SIZE(qnap_ts41x_partitions), +}; + +static struct spi_board_info __initdata qnap_ts41x_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &qnap_ts41x_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { + I2C_BOARD_INFO("s35390a", 0x30), +}; + +static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct mv_sata_platform_data qnap_ts41x_sata_data = { + .n_ports = 2, +}; + +static struct gpio_keys_button qnap_ts41x_buttons[] = { + { + .code = KEY_COPY, + .gpio = 43, + .desc = "USB Copy", + .active_low = 1, + }, + { + .code = KEY_RESTART, + .gpio = 37, + .desc = "Reset", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data qnap_ts41x_button_data = { + .buttons = qnap_ts41x_buttons, + .nbuttons = ARRAY_SIZE(qnap_ts41x_buttons), +}; + +static struct platform_device qnap_ts41x_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &qnap_ts41x_button_data, + } +}; + +static unsigned int qnap_ts41x_mpp_config[] __initdata = { + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, + MPP6_SYSRST_OUTn, + MPP7_PEX_RST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_UART1_TXD, /* PIC controller */ + MPP14_UART1_RXD, /* PIC controller */ + MPP15_SATA0_ACTn, + MPP16_SATA1_ACTn, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ + MPP37_GPIO, /* Reset button */ + MPP43_GPIO, /* USB Copy button */ + MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ + MPP45_GPIO, /* JP1: 0: console, 1: LCD */ + MPP46_GPIO, /* External SATA HDD1 error indicator */ + MPP47_GPIO, /* External SATA HDD2 error indicator */ + MPP48_GPIO, /* External SATA HDD3 error indicator */ + MPP49_GPIO, /* External SATA HDD4 error indicator */ + 0 +}; + + +/***************************************************************************** + * QNAP TS-x19 specific power off method via UART1-attached PIC + ****************************************************************************/ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +void qnap_ts41x_power_off(void) +{ + /* 19200 baud divisor */ + const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack UART1 and reset into sane state (19200,8n1) */ + writel(0x83, UART1_REG(LCR)); + writel(divisor & 0xff, UART1_REG(DLL)); + writel((divisor >> 8) & 0xff, UART1_REG(DLM)); + writel(0x03, UART1_REG(LCR)); + writel(0x00, UART1_REG(IER)); + writel(0x00, UART1_REG(FCR)); + writel(0x00, UART1_REG(MCR)); + + /* send the power-off command 'A' to PIC */ + writel('A', UART1_REG(TX)); +} + +static void __init qnap_ts41x_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(qnap_ts41x_mpp_config); + + kirkwood_uart0_init(); + kirkwood_uart1_init(); /* A PIC controller is connected here. */ + spi_register_board_info(qnap_ts41x_spi_slave_info, + ARRAY_SIZE(qnap_ts41x_spi_slave_info)); + kirkwood_spi_init(); + kirkwood_i2c_init(); + i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); + kirkwood_ge00_init(&qnap_ts41x_ge00_data); + kirkwood_ge01_init(&qnap_ts41x_ge01_data); + kirkwood_sata_init(&qnap_ts41x_sata_data); + kirkwood_ehci_init(); + platform_device_register(&qnap_ts41x_button_device); + + pm_power_off = qnap_ts41x_power_off; + +} + +static int __init ts41x_pci_init(void) +{ + if (machine_is_ts41x()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(ts41x_pci_init); + +MACHINE_START(TS41X, "QNAP TS-41x") + /* Maintainer: Martin Michlmayr */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = qnap_ts41x_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END -- cgit v1.2.3-70-g09d2 From b421950cdc7d0ac900414aa582c5e35aeab921c0 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Thu, 5 Nov 2009 18:09:01 +0000 Subject: [ARM] Kirkwood: Add MPP36 for QNAP TS-11x/TS-21x MPP36 is used on the QNAP TS-11x/TS-21x devices to indicate how much RAM there is: it's high for 512 MB RAM (TS-x19) and low for 256 MB (TS-x10). While this may not be very useful, let's add it for completeness. Signed-off-by: Martin Michlmayr Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/ts219-setup.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index ec1a64f263d..cb0f56dfd5b 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -152,6 +152,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { MPP14_UART1_RXD, /* PIC controller */ MPP15_GPIO, /* USB Copy button */ MPP16_GPIO, /* Reset button */ + MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ 0 }; -- cgit v1.2.3-70-g09d2 From 287989cac25ad71002153d55875584210adf78bd Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Thu, 5 Nov 2009 18:15:31 +0000 Subject: [ARM] Kirkwood: Add QNAP TS-110/TS-210 to Kconfig help text Add two new models from QNAP to the help text. They are compatible with the TS-119/TS-219 and therefore supported by the current code. The only difference is that they have less RAM (256 MB instead of 512 MB), a slower CPU (800 MHz vs 1.2 GHz) and a plastic case. Signed-off-by: Martin Michlmayr Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Kconfig | 5 +++-- arch/arm/mach-kirkwood/ts219-setup.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index d58e8b0febe..8bf09ae5b34 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -33,10 +33,11 @@ config MACH_SHEEVAPLUG Marvell SheevaPlug Reference Board. config MACH_TS219 - bool "QNAP TS-119 and TS-219 Turbo NAS" + bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" help Say 'Y' here if you want your kernel to support the - QNAP TS-119 and TS-219 Turbo NAS devices. + QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS + devices. config MACH_TS41X bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index cb0f56dfd5b..a7c209d599e 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -1,6 +1,6 @@ /* * - * QNAP TS-119/TS-219 Turbo NAS Board Setup + * QNAP TS-11x/TS-21x Turbo NAS Board Setup * * Copyright (C) 2009 Martin Michlmayr * Copyright (C) 2008 Byron Bradley -- cgit v1.2.3-70-g09d2 From 8d27b2f7988b652dbabf79291a3e2550c06e1af5 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Thu, 5 Nov 2009 20:27:46 +0000 Subject: [ARM] Kirkwood: Remove code duplication in QNAP setup files Remove the code duplication found in the setup files of TS-219 and TS-41x. Signed-off-by: Martin Michlmayr Signed-off-by: Nicolas Pitre --- arch/arm/mach-kirkwood/Makefile | 4 +- arch/arm/mach-kirkwood/ts219-setup.c | 105 +------------------------------ arch/arm/mach-kirkwood/ts41x-setup.c | 105 +------------------------------ arch/arm/mach-kirkwood/tsx1x-common.c | 113 ++++++++++++++++++++++++++++++++++ arch/arm/mach-kirkwood/tsx1x-common.h | 7 +++ 5 files changed, 128 insertions(+), 206 deletions(-) create mode 100644 arch/arm/mach-kirkwood/tsx1x-common.c create mode 100644 arch/arm/mach-kirkwood/tsx1x-common.h (limited to 'arch') diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 0c79cedfa64..9f2f67b2b63 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -5,8 +5,8 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o -obj-$(CONFIG_MACH_TS219) += ts219-setup.o -obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o +obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o +obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index a7c209d599e..2830f0fe80e 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c @@ -14,87 +14,17 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include #include -#include -#include -#include #include #include #include #include "common.h" #include "mpp.h" - -/**************************************************************************** - * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with - * the QNAP firmware. - * Layout as used by QNAP: - * 0x00000000-0x00080000 : "U-Boot" - * 0x00200000-0x00400000 : "Kernel" - * 0x00400000-0x00d00000 : "RootFS" - * 0x00d00000-0x01000000 : "RootFS2" - * 0x00080000-0x000c0000 : "U-Boot Config" - * 0x000c0000-0x00200000 : "NAS Config" - * - * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout - * used by the QNAP TS-109/TS-209. - * - ***************************************************************************/ - -static struct mtd_partition qnap_ts219_partitions[] = { - { - .name = "U-Boot", - .size = 0x00080000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0x00200000, - }, { - .name = "RootFS1", - .size = 0x00900000, - .offset = 0x00400000, - }, { - .name = "RootFS2", - .size = 0x00300000, - .offset = 0x00d00000, - }, { - .name = "U-Boot Config", - .size = 0x00040000, - .offset = 0x00080000, - }, { - .name = "NAS Config", - .size = 0x00140000, - .offset = 0x000c0000, - }, -}; - -static const struct flash_platform_data qnap_ts219_flash = { - .type = "m25p128", - .name = "spi_flash", - .parts = qnap_ts219_partitions, - .nr_parts = ARRAY_SIZE(qnap_ts219_partitions), -}; - -static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &qnap_ts219_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; +#include "tsx1x-common.h" static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), @@ -156,33 +86,6 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { 0 }; - -/***************************************************************************** - * QNAP TS-x19 specific power off method via UART1-attached PIC - ****************************************************************************/ - -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) - -void qnap_ts219_power_off(void) -{ - /* 19200 baud divisor */ - const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); - - pr_info("%s: triggering power-off...\n", __func__); - - /* hijack UART1 and reset into sane state (19200,8n1) */ - writel(0x83, UART1_REG(LCR)); - writel(divisor & 0xff, UART1_REG(DLL)); - writel((divisor >> 8) & 0xff, UART1_REG(DLM)); - writel(0x03, UART1_REG(LCR)); - writel(0x00, UART1_REG(IER)); - writel(0x00, UART1_REG(FCR)); - writel(0x00, UART1_REG(MCR)); - - /* send the power-off command 'A' to PIC */ - writel('A', UART1_REG(TX)); -} - static void __init qnap_ts219_init(void) { /* @@ -193,9 +96,7 @@ static void __init qnap_ts219_init(void) kirkwood_uart0_init(); kirkwood_uart1_init(); /* A PIC controller is connected here. */ - spi_register_board_info(qnap_ts219_spi_slave_info, - ARRAY_SIZE(qnap_ts219_spi_slave_info)); - kirkwood_spi_init(); + qnap_tsx1x_register_flash(); kirkwood_i2c_init(); i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); kirkwood_ge00_init(&qnap_ts219_ge00_data); @@ -203,7 +104,7 @@ static void __init qnap_ts219_init(void) kirkwood_ehci_init(); platform_device_register(&qnap_ts219_button_device); - pm_power_off = qnap_ts219_power_off; + pm_power_off = qnap_tsx1x_power_off; } diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c index a1972c94850..de49c2d9e74 100644 --- a/arch/arm/mach-kirkwood/ts41x-setup.c +++ b/arch/arm/mach-kirkwood/ts41x-setup.c @@ -14,87 +14,17 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include #include -#include -#include -#include #include #include #include #include "common.h" #include "mpp.h" - -/**************************************************************************** - * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the - * partitions on the device because we want to keep compatability with - * the QNAP firmware. - * Layout as used by QNAP: - * 0x00000000-0x00080000 : "U-Boot" - * 0x00200000-0x00400000 : "Kernel" - * 0x00400000-0x00d00000 : "RootFS" - * 0x00d00000-0x01000000 : "RootFS2" - * 0x00080000-0x000c0000 : "U-Boot Config" - * 0x000c0000-0x00200000 : "NAS Config" - * - * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout - * used by the QNAP TS-109/TS-209. - * - ***************************************************************************/ - -static struct mtd_partition qnap_ts41x_partitions[] = { - { - .name = "U-Boot", - .size = 0x00080000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0x00200000, - }, { - .name = "RootFS1", - .size = 0x00900000, - .offset = 0x00400000, - }, { - .name = "RootFS2", - .size = 0x00300000, - .offset = 0x00d00000, - }, { - .name = "U-Boot Config", - .size = 0x00040000, - .offset = 0x00080000, - }, { - .name = "NAS Config", - .size = 0x00140000, - .offset = 0x000c0000, - }, -}; - -static const struct flash_platform_data qnap_ts41x_flash = { - .type = "m25p128", - .name = "spi_flash", - .parts = qnap_ts41x_partitions, - .nr_parts = ARRAY_SIZE(qnap_ts41x_partitions), -}; - -static struct spi_board_info __initdata qnap_ts41x_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &qnap_ts41x_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; +#include "tsx1x-common.h" static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { I2C_BOARD_INFO("s35390a", 0x30), @@ -180,33 +110,6 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = { 0 }; - -/***************************************************************************** - * QNAP TS-x19 specific power off method via UART1-attached PIC - ****************************************************************************/ - -#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) - -void qnap_ts41x_power_off(void) -{ - /* 19200 baud divisor */ - const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); - - pr_info("%s: triggering power-off...\n", __func__); - - /* hijack UART1 and reset into sane state (19200,8n1) */ - writel(0x83, UART1_REG(LCR)); - writel(divisor & 0xff, UART1_REG(DLL)); - writel((divisor >> 8) & 0xff, UART1_REG(DLM)); - writel(0x03, UART1_REG(LCR)); - writel(0x00, UART1_REG(IER)); - writel(0x00, UART1_REG(FCR)); - writel(0x00, UART1_REG(MCR)); - - /* send the power-off command 'A' to PIC */ - writel('A', UART1_REG(TX)); -} - static void __init qnap_ts41x_init(void) { /* @@ -217,9 +120,7 @@ static void __init qnap_ts41x_init(void) kirkwood_uart0_init(); kirkwood_uart1_init(); /* A PIC controller is connected here. */ - spi_register_board_info(qnap_ts41x_spi_slave_info, - ARRAY_SIZE(qnap_ts41x_spi_slave_info)); - kirkwood_spi_init(); + qnap_tsx1x_register_flash(); kirkwood_i2c_init(); i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); kirkwood_ge00_init(&qnap_ts41x_ge00_data); @@ -228,7 +129,7 @@ static void __init qnap_ts41x_init(void) kirkwood_ehci_init(); platform_device_register(&qnap_ts41x_button_device); - pm_power_off = qnap_ts41x_power_off; + pm_power_off = qnap_tsx1x_power_off; } diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c new file mode 100644 index 00000000000..7221c20b2af --- /dev/null +++ b/arch/arm/mach-kirkwood/tsx1x-common.c @@ -0,0 +1,113 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * QNAP TS-x1x Boards flash + */ + +/**************************************************************************** + * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the + * partitions on the device because we want to keep compatability with + * the QNAP firmware. + * Layout as used by QNAP: + * 0x00000000-0x00080000 : "U-Boot" + * 0x00200000-0x00400000 : "Kernel" + * 0x00400000-0x00d00000 : "RootFS" + * 0x00d00000-0x01000000 : "RootFS2" + * 0x00080000-0x000c0000 : "U-Boot Config" + * 0x000c0000-0x00200000 : "NAS Config" + * + * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout + * used by the QNAP TS-109/TS-209. + * + ***************************************************************************/ + +struct mtd_partition qnap_tsx1x_partitions[] = { + { + .name = "U-Boot", + .size = 0x00080000, + .offset = 0, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "Kernel", + .size = 0x00200000, + .offset = 0x00200000, + }, { + .name = "RootFS1", + .size = 0x00900000, + .offset = 0x00400000, + }, { + .name = "RootFS2", + .size = 0x00300000, + .offset = 0x00d00000, + }, { + .name = "U-Boot Config", + .size = 0x00040000, + .offset = 0x00080000, + }, { + .name = "NAS Config", + .size = 0x00140000, + .offset = 0x000c0000, + }, +}; + +const struct flash_platform_data qnap_tsx1x_flash = { + .type = "m25p128", + .name = "spi_flash", + .parts = qnap_tsx1x_partitions, + .nr_parts = ARRAY_SIZE(qnap_tsx1x_partitions), +}; + +struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = { + { + .modalias = "m25p80", + .platform_data = &qnap_tsx1x_flash, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +void qnap_tsx1x_register_flash(void) +{ + spi_register_board_info(qnap_tsx1x_spi_slave_info, + ARRAY_SIZE(qnap_tsx1x_spi_slave_info)); + kirkwood_spi_init(); +} + + +/***************************************************************************** + * QNAP TS-x1x specific power off method via UART1-attached PIC + ****************************************************************************/ + +#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) + +void qnap_tsx1x_power_off(void) +{ + /* 19200 baud divisor */ + const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); + + pr_info("%s: triggering power-off...\n", __func__); + + /* hijack UART1 and reset into sane state (19200,8n1) */ + writel(0x83, UART1_REG(LCR)); + writel(divisor & 0xff, UART1_REG(DLL)); + writel((divisor >> 8) & 0xff, UART1_REG(DLM)); + writel(0x03, UART1_REG(LCR)); + writel(0x00, UART1_REG(IER)); + writel(0x00, UART1_REG(FCR)); + writel(0x00, UART1_REG(MCR)); + + /* send the power-off command 'A' to PIC */ + writel('A', UART1_REG(TX)); +} + diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h new file mode 100644 index 00000000000..9a592962a6e --- /dev/null +++ b/arch/arm/mach-kirkwood/tsx1x-common.h @@ -0,0 +1,7 @@ +#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H +#define __ARCH_KIRKWOOD_TSX1X_COMMON_H + +extern void qnap_tsx1x_register_flash(void); +extern void qnap_tsx1x_power_off(void); + +#endif -- cgit v1.2.3-70-g09d2 From 95b7d4a8ca61da8f7280e10cc4e06823f988c4c8 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 26 Oct 2009 11:55:55 +0100 Subject: ARM: MX3: remove I2C defintions from mx31lilly.c The module does not use these pins for I2C but for SPI. Signed-off-by: Daniel Mack Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lilly.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c index 423025150f6..de5cf01f173 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mx31lilly.c @@ -108,7 +108,6 @@ static struct platform_device physmap_flash_device = { static struct platform_device *devices[] __initdata = { &smsc91x_device, &physmap_flash_device, - &mxc_i2c_device1, }; static int mx31lilly_baseboard; @@ -128,8 +127,6 @@ static void __init mx31lilly_board_init(void) } mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA"); platform_add_devices(devices, ARRAY_SIZE(devices)); } -- cgit v1.2.3-70-g09d2 From 3ea2e1a4b74e39f3cc665cf84a25eedb3ae70647 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 26 Oct 2009 11:55:56 +0100 Subject: ARM: MX3: add SPI functions for lilly1131-db This adds support for the two SPI busses found on the lilly1131 module. Signed-off-by: Daniel Mack Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lilly.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c index de5cf01f173..f593a629d8b 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mx31lilly.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "devices.h" @@ -110,6 +111,22 @@ static struct platform_device *devices[] __initdata = { &physmap_flash_device, }; +static int spi_internal_chipselect[] = { + MXC_SPI_CS(0), + MXC_SPI_CS(1), + MXC_SPI_CS(2), +}; + +static struct spi_imx_master spi0_pdata = { + .chipselect = spi_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), +}; + +static struct spi_imx_master spi1_pdata = { + .chipselect = spi_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), +}; + static int mx31lilly_baseboard; core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); @@ -128,6 +145,26 @@ static void __init mx31lilly_board_init(void) mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); + /* SPI */ + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); + + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); + mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); + + mxc_register_device(&mxc_spi_device0, &spi0_pdata); + mxc_register_device(&mxc_spi_device1, &spi1_pdata); + platform_add_devices(devices, ARRAY_SIZE(devices)); } -- cgit v1.2.3-70-g09d2 From 50f349e9fcd069bfc76f238c0c6069aedbdbc385 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 26 Oct 2009 11:55:57 +0100 Subject: ARM: MX3: add support for mc13783 on lilly-db The chip is actually located on the module, not on the base board. But other base boards might add more SPI devices, so the spi_board_info struct must be separated from the module code. Signed-off-by: Daniel Mack Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lilly-db.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 3b3a78f49c2..60f2d15ff4d 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include @@ -202,6 +204,22 @@ static void __init mx31lilly_init_fb(void) gpio_direction_output(LCD_VCC_EN_GPIO, 1); } +/* SPI */ + +static struct mc13783_platform_data mc13783_pdata __initdata = { + .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, +}; + +static struct spi_board_info lilly_spi_devs[] __initdata = { + { + .modalias = "mc13783", + .max_speed_hz = 1000000, + .bus_num = 1, + .chip_select = 0, + .platform_data = &mc13783_pdata, + }, +}; + void __init mx31lilly_db_init(void) { mxc_iomux_setup_multiple_pins(lilly_db_board_pins, @@ -212,5 +230,6 @@ void __init mx31lilly_db_init(void) mxc_register_device(&mxc_uart_device2, &uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); mx31lilly_init_fb(); + spi_register_board_info(lilly_spi_devs, ARRAY_SIZE(lilly_spi_devs)); } -- cgit v1.2.3-70-g09d2 From 24fb84222e21f413d3541f4fad76495954b3c858 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 26 Oct 2009 11:55:58 +0100 Subject: ARM: MX3: Add pad config for MMC pins on lilly-db Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lilly-db.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 60f2d15ff4d..bb1e44f5d30 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -111,6 +111,9 @@ static int mxc_mmc1_get_ro(struct device *dev) static int gpio_det, gpio_wp; +#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + static int mxc_mmc1_init(struct device *dev, irq_handler_t detect_irq, void *data) { @@ -119,6 +122,13 @@ static int mxc_mmc1_init(struct device *dev, gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); + ret = gpio_request(gpio_det, "MMC detect"); if (ret) return ret; -- cgit v1.2.3-70-g09d2 From 115b40c3d7d18d0cb48b4ba306807cc04f259316 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Mon, 26 Oct 2009 11:55:59 +0100 Subject: ARM: MX3: add MX3X_UART1_BASE_ADDR for uncompression on lilly1131 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported-by: Jörg Knobloch Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/uncompress.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 082a3908256..0e128766172 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -94,6 +94,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX31ADS: case MACH_TYPE_MX35_3DS: case MACH_TYPE_PCM043: + case MACH_TYPE_LILLY1131: uart_base = MX3X_UART1_BASE_ADDR; break; case MACH_TYPE_MAGX_ZN5: -- cgit v1.2.3-70-g09d2 From e33c049cb540602a2554264652e2c717ab7f5ec3 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Thu, 15 Oct 2009 19:24:51 +0200 Subject: Armadillo500 Add support for onboard GPIO Buttons. There are two low active Buttons on boards. This patch connect those to the Input Subsystem over gpio-keys driver. Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/armadillo5x0.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index 776c0ee1b3c..309fa7abc09 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include @@ -98,6 +100,36 @@ static int armadillo5x0_pins[] = { MX31_PIN_DRDY0__DRDY0, IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ }; +/* GPIO BUTTONS */ +static struct gpio_keys_button armadillo5x0_buttons[] = { + { + .code = KEY_ENTER, /*28*/ + .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0), + .active_low = 1, + .desc = "menu", + .wakeup = 1, + }, { + .code = KEY_BACK, /*158*/ + .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0), + .active_low = 1, + .desc = "back", + .wakeup = 1, + } +}; + +static struct gpio_keys_platform_data armadillo5x0_button_data = { + .buttons = armadillo5x0_buttons, + .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), +}; + +static struct platform_device armadillo5x0_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &armadillo5x0_button_data, + } +}; /* * NAND Flash @@ -300,6 +332,7 @@ static struct imxuart_platform_data uart_pdata = { static struct platform_device *devices[] __initdata = { &armadillo5x0_smc911x_device, + &armadillo5x0_button_device, }; /* -- cgit v1.2.3-70-g09d2 From 07299ca323022be10ccd56055704de3717b8fe69 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Thu, 15 Oct 2009 19:29:05 +0200 Subject: Armadillo500 Correct bus length for SMSC9118 on board chip. Armadillo500 Correct bus length for SMSC9118 on board chip. The SMSC9118 network chip is connected to the data bus with a 16 bit interface, not 32 as early suggested. Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/armadillo5x0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index 309fa7abc09..bd4a0f90fb3 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c @@ -310,7 +310,7 @@ static struct resource armadillo5x0_smc911x_resources[] = { }; static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_32BIT, + .flags = SMSC911X_USE_16BIT, .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, }; -- cgit v1.2.3-70-g09d2 From e9a6c5d0c8c3f7f4d4ed5c5b1514327d58b76df3 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Thu, 15 Oct 2009 19:31:07 +0200 Subject: Armadillo500 Add i2c second bus support. This add pin allocation an device registration for the second bus i2c. Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/armadillo5x0.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index bd4a0f90fb3..fa973e40329 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c @@ -99,7 +99,11 @@ static int armadillo5x0_pins[] = { MX31_PIN_FPSHIFT__FPSHIFT, MX31_PIN_DRDY0__DRDY0, IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ + /* I2C2 */ + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, }; + /* GPIO BUTTONS */ static struct gpio_keys_button armadillo5x0_buttons[] = { { @@ -332,6 +336,7 @@ static struct imxuart_platform_data uart_pdata = { static struct platform_device *devices[] __initdata = { &armadillo5x0_smc911x_device, + &mxc_i2c_device1, &armadillo5x0_button_device, }; -- cgit v1.2.3-70-g09d2 From 2097abcb8c5a1ccd8c126f6680df28ff6b6b96d0 Mon Sep 17 00:00:00 2001 From: Alberto Panizzo Date: Thu, 15 Oct 2009 19:33:24 +0200 Subject: Armadillo500 Add support for Seiko Instruments S-35390A rtc over i2c. The RTC chip Seiko Instruments S-35390A is connected to the Application Processor over the second bus i2c with the hard coded address 0x30. Signed-off-by: Alberto Panizzo Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/armadillo5x0.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index fa973e40329..54aab401dbd 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -104,6 +105,13 @@ static int armadillo5x0_pins[] = { MX31_PIN_CSPI2_MISO__SDA, }; +/* RTC over I2C*/ +#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) + +static struct i2c_board_info armadillo5x0_i2c_rtc = { + I2C_BOARD_INFO("s35390a", 0x30), +}; + /* GPIO BUTTONS */ static struct gpio_keys_button armadillo5x0_buttons[] = { { @@ -373,6 +381,18 @@ static void __init armadillo5x0_init(void) /* set NAND page size to 2k if not configured via boot mode pins */ __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); + + /* RTC */ + /* Get RTC IRQ and register the chip */ + if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) { + if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0) + armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO); + else + gpio_free(ARMADILLO5X0_RTC_GPIO); + } + if (armadillo5x0_i2c_rtc.irq == 0) + pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); + i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); } static void __init armadillo5x0_timer_init(void) -- cgit v1.2.3-70-g09d2 From 8963c49fdba293fbc21aee1bbae9afa99a52755f Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:46 +0100 Subject: mx31: various pins used for mx31moboard Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 446f8676381..0dcfb777917 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -623,6 +623,8 @@ enum iomux_pins { #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) @@ -693,7 +695,11 @@ enum iomux_pins { #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) #define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) - +#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ -- cgit v1.2.3-70-g09d2 From 421bf82e996826452ebe2011419f846a61950784 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:47 +0100 Subject: mx31moboard: serial port fix We get rid of CTS/RTS lines on uart0 on our platform. This is the port we use as main kernel console. We do not want it to be blocking because of CTS/RTS signals, not allowing the system to boot or print messages. However we often use it with a bluetooth module needing CTS/RTS lines as backup login in case of trouble. To be able to use it, we assert CTS low so that the module can always send chars. Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index 9243de54041..ff74fab34c8 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -45,8 +45,8 @@ static unsigned int moboard_pins[] = { /* UART0 */ - MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, + MX31_PIN_CTS1__GPIO2_7, /* UART4 */ MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, @@ -101,7 +101,18 @@ static struct platform_device mx31moboard_flash = { .num_resources = 1, }; -static struct imxuart_platform_data uart_pdata = { +static int moboard_uart0_init(struct platform_device *pdev) +{ + gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); + return 0; +} + +static struct imxuart_platform_data uart0_pdata = { + .init = moboard_uart0_init, +}; + +static struct imxuart_platform_data uart4_pdata = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -284,8 +295,9 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); - mxc_register_device(&mxc_uart_device0, &uart_pdata); - mxc_register_device(&mxc_uart_device4, &uart_pdata); + mxc_register_device(&mxc_uart_device0, &uart0_pdata); + + mxc_register_device(&mxc_uart_device4, &uart4_pdata); mx31moboard_init_sel_gpios(); -- cgit v1.2.3-70-g09d2 From 10949fff622e1488f0c534a10bca8edf5df95682 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:48 +0100 Subject: mx31moboard: support for pin linked for battery presence check Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard-marxbot.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 2bfaffb344f..6b06faf0cf3 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -49,6 +49,8 @@ static unsigned int marxbot_pins[] = { MX31_PIN_TXD2__GPIO1_28, /* dsPIC resets */ MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, + /*battery detection */ + MX31_PIN_LCS0__GPIO3_23, }; #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) @@ -133,4 +135,9 @@ void __init mx31moboard_marxbot_init(void) dspics_resets_init(); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + + /* battery present pin */ + gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); + gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); } -- cgit v1.2.3-70-g09d2 From 65da9791cba6f873c996099e19b29035203a1318 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:49 +0100 Subject: mx31moboard: SPI and MC13783 voltage regulator support Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard.c | 126 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 125 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index ff74fab34c8..f3ab51bcad4 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -26,6 +26,9 @@ #include #include #include +#include +#include +#include #include #include @@ -39,7 +42,8 @@ #include #include #include -#include +#include +#include #include "devices.h" @@ -79,6 +83,16 @@ static unsigned int moboard_pins[] = { /* SEL */ MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, + /* SPI1 */ + MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, + MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2, + /* Atlas IRQ */ + MX31_PIN_GPIO1_3__GPIO1_3, + /* SPI2 */ + MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO, + MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI2_SS1__CSPI3_SS1, }; static struct physmap_flash_data mx31moboard_flash_data = { @@ -124,6 +138,108 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = { .bitrate = 100000, }; +static int moboard_spi1_cs[] = { + MXC_SPI_CS(0), + MXC_SPI_CS(2), +}; + +static struct spi_imx_master moboard_spi1_master = { + .chipselect = moboard_spi1_cs, + .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), +}; + +static struct regulator_consumer_supply sdhc_consumers[] = { + { + .dev = &mxcsdhc_device0.dev, + .supply = "sdhc0_vcc", + }, + { + .dev = &mxcsdhc_device1.dev, + .supply = "sdhc1_vcc", + }, +}; + +static struct regulator_init_data sdhc_vreg_data = { + .constraints = { + .min_uV = 2700000, + .max_uV = 3000000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_FAST, + .always_on = 0, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers), + .consumer_supplies = sdhc_consumers, +}; + +static struct regulator_consumer_supply cam_consumers[] = { + { + .dev = &mx3_camera.dev, + .supply = "cam_vcc", + }, +}; + +static struct regulator_init_data cam_vreg_data = { + .constraints = { + .min_uV = 2700000, + .max_uV = 3000000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, + .valid_modes_mask = REGULATOR_MODE_NORMAL | + REGULATOR_MODE_FAST, + .always_on = 0, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(cam_consumers), + .consumer_supplies = cam_consumers, +}; + +static struct mc13783_regulator_init_data moboard_regulators[] = { + { + .id = MC13783_REGU_VMMC1, + .init_data = &sdhc_vreg_data, + }, + { + .id = MC13783_REGU_VCAM, + .init_data = &cam_vreg_data, + }, +}; + +static struct mc13783_platform_data moboard_pmic = { + .regulators = moboard_regulators, + .num_regulators = ARRAY_SIZE(moboard_regulators), + .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC, +}; + +static struct spi_board_info moboard_spi_board_info[] __initdata = { + { + .modalias = "mc13783", + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), + .max_speed_hz = 300000, + .bus_num = 1, + .chip_select = 0, + .platform_data = &moboard_pmic, + .mode = SPI_CS_HIGH, + }, + { + .modalias = "spidev", + .max_speed_hz = 300000, + .bus_num = 1, + .chip_select = 1, /* according spi1_cs[] ! */ + }, +}; + +static int moboard_spi2_cs[] = { + MXC_SPI_CS(1), +}; + +static struct spi_imx_master moboard_spi2_master = { + .chipselect = moboard_spi2_cs, + .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), +}; + #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) @@ -304,6 +420,14 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); + mxc_register_device(&mxc_spi_device1, &moboard_spi1_master); + mxc_register_device(&mxc_spi_device2, &moboard_spi2_master); + + gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); + spi_register_board_info(moboard_spi_board_info, + ARRAY_SIZE(moboard_spi_board_info)); + mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); usb_xcvr_reset(); -- cgit v1.2.3-70-g09d2 From 4dd7129345be71cb20da99a75ded01ea50615f66 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:50 +0100 Subject: mx31moboard: initialize ipu device for all the boards Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index f3ab51bcad4..2f95dcd805c 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include @@ -393,6 +394,10 @@ static void mx31moboard_init_sel_gpios(void) } } +static struct ipu_platform_data mx3_ipu_data = { + .irq_base = MXC_IPU_IRQ_START, +}; + static struct platform_device *devices[] __initdata = { &mx31moboard_flash, &mx31moboard_leds_device, @@ -430,6 +435,8 @@ static void __init mxc_board_init(void) mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); + mxc_register_device(&mx3_ipu, &mx3_ipu_data); + usb_xcvr_reset(); moboard_usbotg_init(); -- cgit v1.2.3-70-g09d2 From 04ea3c801905a4562cc89af78eba40dec0f960a9 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:51 +0100 Subject: mx31moboard: camera support We have two mt9t031 cameras that have a muxed bus on the robot. Only one is currently initialized because of limitations in soc_camera that should be removed later. Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard-marxbot.c | 86 ++++++++++++++++++++++++++++++++- arch/arm/mach-mx3/mx31moboard.c | 36 ++++++++++++++ 2 files changed, 121 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 6b06faf0cf3..e4e344eceb7 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -16,9 +16,11 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ +#include #include #include #include +#include #include #include @@ -28,6 +30,8 @@ #include #include +#include + #include "devices.h" static unsigned int marxbot_pins[] = { @@ -37,7 +41,6 @@ static unsigned int marxbot_pins[] = { MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, /* CSI */ - MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, @@ -45,6 +48,7 @@ static unsigned int marxbot_pins[] = { MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, + MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5, MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, MX31_PIN_TXD2__GPIO1_28, /* dsPIC resets */ @@ -122,6 +126,83 @@ static void dspics_resets_init(void) } } +#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) +#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5) +#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) +#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4) +#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2) + +static int marxbot_basecam_power(struct device *dev, int on) +{ + gpio_set_value(BASECAM_POWER, !on); + return 0; +} + +static int marxbot_basecam_reset(struct device *dev) +{ + gpio_set_value(BASECAM_RST_B, 0); + udelay(100); + gpio_set_value(BASECAM_RST_B, 1); + return 0; +} + +static struct i2c_board_info marxbot_i2c_devices[] = { + { + I2C_BOARD_INFO("mt9t031", 0x5d), + }, +}; + +static struct soc_camera_link base_iclink = { + .bus_id = 0, /* Must match with the camera ID */ + .power = marxbot_basecam_power, + .reset = marxbot_basecam_reset, + .board_info = &marxbot_i2c_devices[0], + .i2c_adapter_id = 0, + .module_name = "mt9t031", +}; + +static struct platform_device marxbot_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &base_iclink, + }, + }, +}; + +static struct platform_device *marxbot_cameras[] __initdata = { + &marxbot_camera[0], +}; + +static int __init marxbot_cam_init(void) +{ + int ret = gpio_request(CAM_CHOICE, "cam-choice"); + if (ret) + return ret; + gpio_direction_output(CAM_CHOICE, 1); + + ret = gpio_request(BASECAM_RST_B, "basecam-reset"); + if (ret) + return ret; + gpio_direction_output(BASECAM_RST_B, 1); + ret = gpio_request(BASECAM_POWER, "basecam-standby"); + if (ret) + return ret; + gpio_direction_output(BASECAM_POWER, 0); + + ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset"); + if (ret) + return ret; + gpio_direction_output(TURRETCAM_RST_B, 1); + ret = gpio_request(TURRETCAM_POWER, "turretcam-standby"); + if (ret) + return ret; + gpio_direction_output(TURRETCAM_POWER, 0); + + return 0; +} + /* * system init for baseboard usage. Will be called by mx31moboard init. */ @@ -136,6 +217,9 @@ void __init mx31moboard_marxbot_init(void) mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + marxbot_cam_init(); + platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras)); + /* battery present pin */ gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index 2f95dcd805c..b167f131f7c 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -403,6 +404,39 @@ static struct platform_device *devices[] __initdata = { &mx31moboard_leds_device, }; +static struct mx3_camera_pdata camera_pdata = { + .dma_dev = &mx3_ipu.dev, + .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, + .mclk_10khz = 4800, +}; + +#define CAMERA_BUF_SIZE (4*1024*1024) + +static int __init mx31moboard_cam_alloc_dma(const size_t buf_size) +{ + dma_addr_t dma_handle; + void *buf; + int dma; + + if (buf_size < 2 * 1024 * 1024) + return -EINVAL; + + buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); + if (!buf) { + pr_err("%s: cannot allocate camera buffer-memory\n", __func__); + return -ENOMEM; + } + + memset(buf, 0, buf_size); + + dma = dma_declare_coherent_memory(&mx3_camera.dev, + dma_handle, dma_handle, buf_size, + DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); + + /* The way we call dma_declare_coherent_memory only a malloc can fail */ + return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; +} + static int mx31moboard_baseboard; core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); @@ -436,6 +470,8 @@ static void __init mxc_board_init(void) mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); + if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) + mxc_register_device(&mx3_camera, &camera_pdata); usb_xcvr_reset(); -- cgit v1.2.3-70-g09d2 From f4f8bda2321d5ecbfeef878a50c996e3a32a75e6 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 5 Nov 2009 09:44:09 +0100 Subject: MXC: Add support for ULPI Viewports The ARC USB OTG Core has support for accessing ULPI tranceivers through so called ULPI viewports. Export a set of function for use with the USB OTG framework. Signed-off-by: Daniel Mack Cc: Greg Kroah-Hartman Cc: David Brownell Cc: linux-usb@vger.kernel.org Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/Kconfig | 3 + arch/arm/plat-mxc/Makefile | 1 + arch/arm/plat-mxc/include/mach/ulpi.h | 7 +++ arch/arm/plat-mxc/ulpi.c | 113 ++++++++++++++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 arch/arm/plat-mxc/include/mach/ulpi.h create mode 100644 arch/arm/plat-mxc/ulpi.c (limited to 'arch') diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index ca5c7c22634..e8e92cbd108 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -69,6 +69,9 @@ config MXC_PWM help Enable support for the i.MX PWM controller(s). +config MXC_ULPI + bool + config ARCH_HAS_RNGA bool depends on ARCH_MXC diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index e3212c8ff42..545412f8183 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o +obj-$(CONFIG_MXC_ULPI) += ulpi.o diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h new file mode 100644 index 00000000000..96b6ab4c40c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ulpi.h @@ -0,0 +1,7 @@ +#ifndef __MACH_ULPI_H +#define __MACH_ULPI_H + +extern struct otg_io_access_ops mxc_ulpi_access_ops; + +#endif /* __MACH_ULPI_H */ + diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c new file mode 100644 index 00000000000..582c6dfaba4 --- /dev/null +++ b/arch/arm/plat-mxc/ulpi.c @@ -0,0 +1,113 @@ +/* + * Copyright 2008 Sascha Hauer, Pengutronix + * Copyright 2009 Daniel Mack + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include + +#include + +/* ULPIVIEW register bits */ +#define ULPIVW_WU (1 << 31) /* Wakeup */ +#define ULPIVW_RUN (1 << 30) /* read/write run */ +#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */ +#define ULPIVW_SS (1 << 27) /* SyncState */ +#define ULPIVW_PORT_MASK 0x07 /* Port field */ +#define ULPIVW_PORT_SHIFT 24 +#define ULPIVW_ADDR_MASK 0xff /* data address field */ +#define ULPIVW_ADDR_SHIFT 16 +#define ULPIVW_RDATA_MASK 0xff /* read data field */ +#define ULPIVW_RDATA_SHIFT 8 +#define ULPIVW_WDATA_MASK 0xff /* write data field */ +#define ULPIVW_WDATA_SHIFT 0 + +static int ulpi_poll(void __iomem *view, u32 bit) +{ + int timeout = 10000; + + while (timeout--) { + u32 data = __raw_readl(view); + + if (!(data & bit)) + return 0; + + cpu_relax(); + }; + + printk(KERN_WARNING "timeout polling for ULPI device\n"); + + return -ETIMEDOUT; +} + +static int ulpi_read(struct otg_transceiver *otg, u32 reg) +{ + int ret; + void __iomem *view = otg->io_priv; + + /* make sure interface is running */ + if (!(__raw_readl(view) & ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + + /* wait for wakeup */ + ret = ulpi_poll(view, ULPIVW_WU); + if (ret) + return ret; + } + + /* read the register */ + __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); + + /* wait for completion */ + ret = ulpi_poll(view, ULPIVW_RUN); + if (ret) + return ret; + + return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; +} + +static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) +{ + int ret; + void __iomem *view = otg->io_priv; + + /* make sure the interface is running */ + if (!(__raw_readl(view) & ULPIVW_SS)) { + __raw_writel(ULPIVW_WU, view); + /* wait for wakeup */ + ret = ulpi_poll(view, ULPIVW_WU); + if (ret) + return ret; + } + + __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | + (reg << ULPIVW_ADDR_SHIFT) | + ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view); + + /* wait for completion */ + return ulpi_poll(view, ULPIVW_RUN); +} + +struct otg_io_access_ops mxc_ulpi_access_ops = { + .read = ulpi_read, + .write = ulpi_write, +}; +EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); + -- cgit v1.2.3-70-g09d2 From 060d20d32ae7c6a20a8eac465795ed5bc9b37f7c Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 19 Oct 2009 22:19:28 +0200 Subject: imx/gpio: Use handle_level_irq MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Russell King handle_edge_irq is only useful for "edge-based inputs where the controller does not remember transitions with the input masked." So using handle_edge_irq unconditionally for both edge and level irqs is wrong. Testing showed that the controller does remember transitions while the interrupt is masked. So use handle_level_irq unconditionally. Signed-off-by: Uwe Kleine-König Cc: Russell King Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index cfc4a8b43e6..d65ebe303b9 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) for (j = port[i].virtual_irq_start; j < port[i].virtual_irq_start + 32; j++) { set_irq_chip(j, &gpio_irq_chip); - set_irq_handler(j, handle_edge_irq); + set_irq_handler(j, handle_level_irq); set_irq_flags(j, IRQF_VALID); } -- cgit v1.2.3-70-g09d2 From 9e0afdf8f32f34f7e67db4d4622cb13e39a0e5db Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Fri, 2 Oct 2009 11:24:49 +0200 Subject: MXC NFC: Add the clock resource to support NFC in i.MX35 Signed-off-by: Juergen Beisert Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock-imx35.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index c595260ec1f..33a23e7c7e9 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -387,6 +387,35 @@ DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); +static int clk_dummy_enable(struct clk *clk) +{ + return 0; +} + +static void clk_dummy_disable(struct clk *clk) +{ +} + +static unsigned long get_rate_nfc(struct clk *clk) +{ + unsigned long div1; + + div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1; + + return get_rate_ahb(NULL) / div1; +} + +/* NAND Controller: It seems it can't be disabled */ +static struct clk nfc_clk = { + .id = 0, + .enable_reg = 0, + .enable_shift = 0, + .get_rate = get_rate_nfc, + .set_rate = NULL, /* set_rate_nfc, */ + .enable = clk_dummy_enable, + .disable = clk_dummy_disable +}; + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -449,6 +478,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "csi", csi_clk) _REGISTER_CLOCK(NULL, "iim", iim_clk) _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) + _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) }; int __init mx35_clocks_init() -- cgit v1.2.3-70-g09d2 From fcebfc8d9062ec696c5cf84129fa6fb2550de4fd Mon Sep 17 00:00:00 2001 From: Juergen Beisert Date: Fri, 2 Oct 2009 11:25:45 +0200 Subject: MXC NFC: Fix NFCs address area on i.MX35 The address area of the NFC in the i.MX35 silicon is much larger than 4k. Signed-off-by: Juergen Beisert Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/devices.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index e6abe181b96..e04920ed21b 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -546,7 +546,7 @@ static int mx3_devices_init(void) } if (cpu_is_mx35()) { mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; - mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; + mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; otg_resources[0].start = MX35_OTG_BASE_ADDR; otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; otg_resources[1].start = MXC_INT_USBOTG; -- cgit v1.2.3-70-g09d2 From 34499a7cc59061d1bf6d1bb448ae48f935f57c92 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 12 Nov 2009 11:29:43 +0100 Subject: pca100: Add board to uncompress.h Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/uncompress.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 0e128766172..a41bf57fb3d 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -83,6 +83,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX27ADS: case MACH_TYPE_PCM038: case MACH_TYPE_MX21ADS: + case MACH_TYPE_PCA100: uart_base = MX2X_UART1_BASE_ADDR; break; case MACH_TYPE_MX31LITE: -- cgit v1.2.3-70-g09d2 From f6f1bc64f0408814a835c09424269aabe39b5d38 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 12 Nov 2009 11:30:08 +0100 Subject: pca100: use correct irq initialisation function Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/pca100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c index fe5b165b88c..aea3d340d2e 100644 --- a/arch/arm/mach-mx2/pca100.c +++ b/arch/arm/mach-mx2/pca100.c @@ -237,7 +237,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27") .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, .boot_params = PHYS_OFFSET + 0x100, .map_io = mx27_map_io, - .init_irq = mxc_init_irq, + .init_irq = mx27_init_irq, .init_machine = pca100_init, .timer = &pca100_timer, MACHINE_END -- cgit v1.2.3-70-g09d2 From 4f43c2ed21d5902f29c41aeb22728193a8617192 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 12 Nov 2009 11:30:26 +0100 Subject: pcm043: Add NAND support Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/pcm043.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c index e18a224671f..e3aa829be58 100644 --- a/arch/arm/mach-mx3/pcm043.c +++ b/arch/arm/mach-mx3/pcm043.c @@ -43,6 +43,7 @@ #include #include #include +#include #include "devices.h" @@ -206,6 +207,11 @@ static struct pad_desc pcm043_pads[] = { MX35_PAD_ATA_CS0__GPIO2_6, }; +static struct mxc_nand_platform_data pcm037_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + /* * Board specific initialization. */ @@ -216,6 +222,7 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); mxc_register_device(&mxc_uart_device1, &uart_pdata); -- cgit v1.2.3-70-g09d2 From 23291df423fd6d656ce9d1189c4a477216d17f7c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 22 Oct 2009 14:50:33 +0200 Subject: i.MX2: Add sound (ssi) resources Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/clock_imx27.c | 4 +-- arch/arm/mach-mx2/devices.c | 78 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mx2/devices.h | 3 +- 3 files changed, 82 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index ff5e3329891..aa640b4876c 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -651,8 +651,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) - _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) - _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) _REGISTER_CLOCK(NULL, "vpu", vpu_clk) _REGISTER_CLOCK(NULL, "dma", dma_clk) diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 50199aff014..3d398ce09b3 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -530,6 +530,84 @@ struct platform_device mxc_usbh2 = { }; #endif +static struct resource imx_ssi_resources0[] = { + { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + 0x6F, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_SSI1, + .end = MXC_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, { + .name = "tx0", + .start = DMA_REQ_SSI1_TX0, + .end = DMA_REQ_SSI1_TX0, + .flags = IORESOURCE_DMA, + }, { + .name = "rx0", + .start = DMA_REQ_SSI1_RX0, + .end = DMA_REQ_SSI1_RX0, + .flags = IORESOURCE_DMA, + }, { + .name = "tx1", + .start = DMA_REQ_SSI1_TX1, + .end = DMA_REQ_SSI1_TX1, + .flags = IORESOURCE_DMA, + }, { + .name = "rx1", + .start = DMA_REQ_SSI1_RX1, + .end = DMA_REQ_SSI1_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + 0x6F, + .flags = IORESOURCE_MEM, + }, { + .start = MXC_INT_SSI2, + .end = MXC_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, { + .name = "tx0", + .start = DMA_REQ_SSI2_TX0, + .end = DMA_REQ_SSI2_TX0, + .flags = IORESOURCE_DMA, + }, { + .name = "rx0", + .start = DMA_REQ_SSI2_RX0, + .end = DMA_REQ_SSI2_RX0, + .flags = IORESOURCE_DMA, + }, { + .name = "tx1", + .start = DMA_REQ_SSI2_TX1, + .end = DMA_REQ_SSI2_TX1, + .flags = IORESOURCE_DMA, + }, { + .name = "rx1", + .start = DMA_REQ_SSI2_RX1, + .end = DMA_REQ_SSI2_RX1, + .flags = IORESOURCE_DMA, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + /* GPIO port description */ static struct mxc_gpio_port imx_gpio_ports[] = { { diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index d315406d672..97306aa18f1 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -26,4 +26,5 @@ extern struct platform_device mxc_usbh2; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; extern struct platform_device mxc_spi_device2; - +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; -- cgit v1.2.3-70-g09d2 From d8d982b1b284370512d5650aadb300d30fd9d4b2 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 29 Oct 2009 17:17:42 +0100 Subject: i.MX3: Add sound (ssi) resources Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock-imx35.c | 4 ++-- arch/arm/mach-mx3/devices.c | 42 +++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mx3/devices.h | 2 ++ 3 files changed, 46 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 33a23e7c7e9..93a172da591 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -463,8 +463,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "sdma", sdma_clk) _REGISTER_CLOCK(NULL, "spba", spba_clk) _REGISTER_CLOCK(NULL, "spdif", spdif_clk) - _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) - _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index e04920ed21b..6adb586515e 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -537,6 +537,44 @@ struct platform_device mxc_fec_device = { }; #endif +static struct resource imx_ssi_resources0[] = { + { + .start = SSI1_BASE_ADDR, + .end = SSI1_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX31_INT_SSI1, + .end = MX31_INT_SSI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource imx_ssi_resources1[] = { + { + .start = SSI2_BASE_ADDR, + .end = SSI2_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM + }, { + .start = MX31_INT_SSI2, + .end = MX31_INT_SSI2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device imx_ssi_device0 = { + .name = "imx-ssi", + .id = 0, + .num_resources = ARRAY_SIZE(imx_ssi_resources0), + .resource = imx_ssi_resources0, +}; + +struct platform_device imx_ssi_device1 = { + .name = "imx-ssi", + .id = 1, + .num_resources = ARRAY_SIZE(imx_ssi_resources1), + .resource = imx_ssi_resources1, +}; + static int mx3_devices_init(void) { if (cpu_is_mx31()) { @@ -555,6 +593,10 @@ static int mx3_devices_init(void) mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; mxc_usbh1_resources[1].start = MXC_INT_USBHS; mxc_usbh1_resources[1].end = MXC_INT_USBHS; + imx_ssi_resources0[1].start = MX35_INT_SSI1; + imx_ssi_resources0[1].end = MX35_INT_SSI1; + imx_ssi_resources1[1].start = MX35_INT_SSI2; + imx_ssi_resources1[1].end = MX35_INT_SSI2; } return 0; diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index ab87419dc9a..42cf175eac6 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h @@ -23,4 +23,6 @@ extern struct platform_device mxc_rnga_device; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; extern struct platform_device mxc_spi_device2; +extern struct platform_device imx_ssi_device0; +extern struct platform_device imx_ssi_device1; -- cgit v1.2.3-70-g09d2 From 9eedbdf1b4216e286bd660322ae5a52f79eee243 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 29 Oct 2009 17:12:39 +0100 Subject: MXC: Add a digital audio multiplexer driver Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/Kconfig | 2 + arch/arm/mach-mx3/Kconfig | 2 + arch/arm/plat-mxc/Kconfig | 7 ++++ arch/arm/plat-mxc/Makefile | 2 + arch/arm/plat-mxc/audmux-v1.c | 53 +++++++++++++++++++++++ arch/arm/plat-mxc/audmux-v2.c | 74 +++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/audmux.h | 52 +++++++++++++++++++++++ 7 files changed, 192 insertions(+) create mode 100644 arch/arm/plat-mxc/audmux-v1.c create mode 100644 arch/arm/plat-mxc/audmux-v2.c create mode 100644 arch/arm/plat-mxc/include/mach/audmux.h (limited to 'arch') diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index c8a2eac4d13..3e14da3698b 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -6,11 +6,13 @@ choice config MACH_MX21 bool "i.MX21 support" + select ARCH_MXC_AUDMUX_V1 help This enables support for Freescale's MX2 based i.MX21 processor. config MACH_MX27 bool "i.MX27 support" + select ARCH_MXC_AUDMUX_V1 help This enables support for Freescale's MX2 based i.MX27 processor. diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 851f2458bf6..ffdd211e353 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -2,11 +2,13 @@ if ARCH_MX3 config ARCH_MX31 select ARCH_HAS_RNGA + select ARCH_MXC_AUDMUX_V2 bool config ARCH_MX35 bool select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 comment "MX3 platforms:" diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index e8e92cbd108..8b0a1ee039f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -78,4 +78,11 @@ config ARCH_HAS_RNGA config ARCH_MXC_IOMUX_V3 bool + +config ARCH_MXC_AUDMUX_V1 + bool + +config ARCH_MXC_AUDMUX_V2 + bool + endif diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 545412f8183..4cbca9da150 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -10,3 +10,5 @@ obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_MXC_ULPI) += ulpi.o +obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o +obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c new file mode 100644 index 00000000000..70ab5aff2b9 --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -0,0 +1,53 @@ +/* + * Copyright 2009 Pengutronix, Sascha Hauer + * + * Initial development of this code was funded by + * Phytec Messtechnik GmbH, http://www.phytec.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +static void __iomem *audmux_base; + +#define MXC_AUDMUX_V1_PCR(x) ((x) * 4) + +int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr) +{ + if (!audmux_base) { + printk("%s: not configured\n", __func__); + return -ENOSYS; + } + + writel(pcr, audmux_base + MXC_AUDMUX_V1_PCR(port)); + + return 0; +} +EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); + +static int mxc_audmux_v1_init(void) +{ + if (cpu_is_mx27() || cpu_is_mx21()) + audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); + return 0; +} + +postcore_initcall(mxc_audmux_v1_init); diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c new file mode 100644 index 00000000000..6f21096086f --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -0,0 +1,74 @@ +/* + * Copyright 2009 Pengutronix, Sascha Hauer + * + * Initial development of this code was funded by + * Phytec Messtechnik GmbH, http://www.phytec.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +static struct clk *audmux_clk; +static void __iomem *audmux_base; + +#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8) +#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4) + +int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, + unsigned int pdcr) +{ + if (!audmux_base) + return -ENOSYS; + + if (audmux_clk) + clk_enable(audmux_clk); + + writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port)); + writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port)); + + if (audmux_clk) + clk_disable(audmux_clk); + + return 0; +} +EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); + +static int mxc_audmux_v2_init(void) +{ + int ret; + + if (cpu_is_mx35()) { + audmux_clk = clk_get(NULL, "audmux"); + if (IS_ERR(audmux_clk)) { + ret = PTR_ERR(audmux_clk); + printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, + ret); + return ret; + } + } + + if (cpu_is_mx31() || cpu_is_mx35()) + audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); + + return 0; +} + +postcore_initcall(mxc_audmux_v2_init); diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h new file mode 100644 index 00000000000..5cd6466964a --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/audmux.h @@ -0,0 +1,52 @@ +#ifndef __MACH_AUDMUX_H +#define __MACH_AUDMUX_H + +#define MX27_AUDMUX_HPCR1_SSI0 0 +#define MX27_AUDMUX_HPCR2_SSI1 1 +#define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 +#define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 +#define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 +#define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 + +#define MX31_AUDMUX_PORT1_SSI0 0 +#define MX31_AUDMUX_PORT2_SSI1 1 +#define MX31_AUDMUX_PORT3_SSI_PINS_3 2 +#define MX31_AUDMUX_PORT4_SSI_PINS_4 3 +#define MX31_AUDMUX_PORT5_SSI_PINS_5 4 +#define MX31_AUDMUX_PORT6_SSI_PINS_6 5 + +/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ +#define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) +#define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) +#define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10) +#define MXC_AUDMUX_V1_PCR_SYN (1 << 12) +#define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) +#define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) +#define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24) +#define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25) +#define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) +#define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) +#define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) + +/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ +#define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) +#define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) +#define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) +#define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) +#define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21) +#define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) +#define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) +#define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) +#define MXC_AUDMUX_V2_PTCR_SYN (1 << 11) + +#define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) +#define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12) +#define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) +#define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) + +int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr); + +int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, + unsigned int pdcr); + +#endif /* __MACH_AUDMUX_H */ -- cgit v1.2.3-70-g09d2 From 4dc7be72b5c9d33669cb2b68d16c7588fb36d8df Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Mon, 2 Nov 2009 09:49:41 +0100 Subject: i.MX35: Fix audmux clock Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock-imx35.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 93a172da591..02a9a18e118 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk) DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); -DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); +/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); @@ -381,7 +381,7 @@ DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); -DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); +DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL); DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); @@ -426,7 +426,6 @@ static struct clk nfc_clk = { static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "asrc", asrc_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) - _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK(NULL, "can", can1_clk) _REGISTER_CLOCK(NULL, "can", can2_clk) _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) @@ -474,7 +473,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "max", max_clk) - _REGISTER_CLOCK(NULL, "admux", admux_clk) + _REGISTER_CLOCK(NULL, "audmux", audmux_clk) _REGISTER_CLOCK(NULL, "csi", csi_clk) _REGISTER_CLOCK(NULL, "iim", iim_clk) _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) -- cgit v1.2.3-70-g09d2 From fdcad71cef68529a1f54331f533763ca53814f96 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 20 Oct 2009 16:32:53 +0200 Subject: at91: at91sam9g20ek modify dual slot evaluation kit at91sam9g20ek rev. C and onwards embed two SD/MMC slots. This patch modify the previous dual slot board definition to match the official rev. C board. It also allows the use of at91_mci SD/MMC driver in addition to the atmel-mci one. Some pins have been re-affected from leds or Ethernet phy IRQ to the SD/MMC slot A. This lead to a modification of those definitions. Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor --- arch/arm/mach-at91/Kconfig | 20 +++++++++++--------- arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c | 23 +++++++++++++++-------- 2 files changed, 26 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index e35d54d43e7..2fd88437348 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -289,13 +289,6 @@ config MACH_NEOCORE926 help Select this if you are using the Adeneo Neocore 926 board. -config MACH_AT91SAM9G20EK_2MMC - bool "Atmel AT91SAM9G20-EK Evaluation Kit modified for 2 MMC Slots" - depends on ARCH_AT91SAM9G20 - help - Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit - Rev A or B modified for 2 MMC Slots. - endif # ---------------------------------------------------------- @@ -322,7 +315,16 @@ config MACH_AT91SAM9G20EK bool "Atmel AT91SAM9G20-EK Evaluation Kit" depends on ARCH_AT91SAM9G20 help - Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit. + Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit + that embeds only one SD/MMC slot. + +config MACH_AT91SAM9G20EK_2MMC + bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" + depends on ARCH_AT91SAM9G20 + help + Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit + with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and + onwards. config MACH_CPU9G20 bool "Eukrea CPU9G20 board" @@ -392,7 +394,7 @@ config MTD_AT91_DATAFLASH_CARD config MTD_NAND_ATMEL_BUSWIDTH_16 bool "Enable 16-bit data bus interface to NAND flash" - depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK) + depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G20EK_2MMC || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK) help On AT91SAM926x boards both types of NAND flash can be present (8 and 16 bit data bus width). diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c index a28e53faf71..a4102d72cc9 100644 --- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c +++ b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c @@ -90,7 +90,7 @@ static struct at91_udc_data __initdata ek_udc_data = { * SPI devices. */ static struct spi_board_info ek_spi_devices[] = { -#if !defined(CONFIG_MMC_ATMELMCI) +#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91)) { /* DataFlash chip */ .modalias = "mtd_dataflash", .chip_select = 1, @@ -113,7 +113,7 @@ static struct spi_board_info ek_spi_devices[] = { * MACB Ethernet device */ static struct at91_eth_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PC12, + .phy_irq_pin = AT91_PIN_PB0, .is_rmii = 1, }; @@ -194,24 +194,27 @@ static void __init ek_add_device_nand(void) /* * MCI (SD/MMC) - * det_pin and wp_pin are not connected + * wp_pin is not connected */ #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) static struct mci_platform_data __initdata ek_mmc_data = { .slot[0] = { .bus_width = 4, - .detect_pin = -ENODEV, + .detect_pin = AT91_PIN_PC2, .wp_pin = -ENODEV, }, .slot[1] = { .bus_width = 4, - .detect_pin = -ENODEV, + .detect_pin = AT91_PIN_PC9, .wp_pin = -ENODEV, }, }; #else -static struct amci_platform_data __initdata ek_mmc_data = { +static struct at91_mmc_data __initdata ek_mmc_data = { + .slot_b = 1, /* Only one slot so use slot B */ + .wire4 = 1, + .det_pin = AT91_PIN_PC9, }; #endif @@ -221,13 +224,13 @@ static struct amci_platform_data __initdata ek_mmc_data = { static struct gpio_led ek_leds[] = { { /* "bottom" led, green, userled1 to be defined */ .name = "ds5", - .gpio = AT91_PIN_PB12, + .gpio = AT91_PIN_PB8, .active_low = 1, .default_trigger = "none", }, { /* "power" led, yellow */ .name = "ds1", - .gpio = AT91_PIN_PB13, + .gpio = AT91_PIN_PB9, .default_trigger = "heartbeat", } }; @@ -254,7 +257,11 @@ static void __init ek_board_init(void) /* Ethernet */ at91_add_device_eth(&ek_macb_data); /* MMC */ +#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) at91_add_device_mci(0, &ek_mmc_data); +#else + at91_add_device_mmc(0, &ek_mmc_data); +#endif /* I2C */ at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LEDs */ -- cgit v1.2.3-70-g09d2 From c4e4ab9f23d26498a01316428d710833fb96f214 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 22 Oct 2009 18:41:41 +0200 Subject: at91: remove not needed depends on Those "depends on" are a double check as all machine entries are surrounded by "if " conditions. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor --- arch/arm/mach-at91/Kconfig | 32 -------------------------------- 1 file changed, 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 2fd88437348..4301c6bad80 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -76,89 +76,76 @@ comment "AT91RM9200 Board Type" config MACH_ONEARM bool "Ajeco 1ARM Single Board Computer" - depends on ARCH_AT91RM9200 help Select this if you are using Ajeco's 1ARM Single Board Computer. config ARCH_AT91RM9200DK bool "Atmel AT91RM9200-DK Development board" - depends on ARCH_AT91RM9200 help Select this if you are using Atmel's AT91RM9200-DK Development board. (Discontinued) config MACH_AT91RM9200EK bool "Atmel AT91RM9200-EK Evaluation Kit" - depends on ARCH_AT91RM9200 help Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. config MACH_CSB337 bool "Cogent CSB337" - depends on ARCH_AT91RM9200 help Select this if you are using Cogent's CSB337 board. config MACH_CSB637 bool "Cogent CSB637" - depends on ARCH_AT91RM9200 help Select this if you are using Cogent's CSB637 board. config MACH_CARMEVA bool "Conitec ARM&EVA" - depends on ARCH_AT91RM9200 help Select this if you are using Conitec's AT91RM9200-MCU-Module. config MACH_ATEB9200 bool "Embest ATEB9200" - depends on ARCH_AT91RM9200 help Select this if you are using Embest's ATEB9200 board. config MACH_KB9200 bool "KwikByte KB920x" - depends on ARCH_AT91RM9200 help Select this if you are using KwikByte's KB920x board. config MACH_PICOTUX2XX bool "picotux 200" - depends on ARCH_AT91RM9200 help Select this if you are using a picotux 200. config MACH_KAFA bool "Sperry-Sun KAFA board" - depends on ARCH_AT91RM9200 help Select this if you are using Sperry-Sun's KAFA board. config MACH_ECBAT91 bool "emQbit ECB_AT91 SBC" - depends on ARCH_AT91RM9200 help Select this if you are using emQbit's ECB_AT91 board. config MACH_YL9200 bool "ucDragon YL-9200" - depends on ARCH_AT91RM9200 help Select this if you are using the ucDragon YL-9200 board. config MACH_CPUAT91 bool "Eukrea CPUAT91" - depends on ARCH_AT91RM9200 help Select this if you are using the Eukrea Electromatique's CPUAT91 board . @@ -173,7 +160,6 @@ comment "AT91SAM9260 Variants" config ARCH_AT91SAM9260_SAM9XE bool "AT91SAM9XE" - depends on ARCH_AT91SAM9260 help Select this if you are using Atmel's AT91SAM9XE System-on-Chip. They are basically AT91SAM9260s with various sizes of embedded Flash. @@ -182,28 +168,24 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type" config MACH_AT91SAM9260EK bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" - depends on ARCH_AT91SAM9260 help Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit config MACH_CAM60 bool "KwikByte KB9260 (CAM60) board" - depends on ARCH_AT91SAM9260 help Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. config MACH_SAM9_L9260 bool "Olimex SAM9-L9260 board" - depends on ARCH_AT91SAM9260 help Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. config MACH_AFEB9260 bool "Custom afeb9260 board v1" - depends on ARCH_AT91SAM9260 help Select this if you are using custom afeb9260 board based on open hardware design. Select this for revision 1 of the board. @@ -212,21 +194,18 @@ config MACH_AFEB9260 config MACH_USB_A9260 bool "CALAO USB-A9260" - depends on ARCH_AT91SAM9260 help Select this if you are using a Calao Systems USB-A9260. config MACH_QIL_A9260 bool "CALAO QIL-A9260 board" - depends on ARCH_AT91SAM9260 help Select this if you are using a Calao Systems QIL-A9260 Board. config MACH_CPU9260 bool "Eukrea CPU9260 board" - depends on ARCH_AT91SAM9260 help Select this if you are using a Eukrea Electromatique's CPU9260 Board @@ -241,7 +220,6 @@ comment "AT91SAM9261 Board Type" config MACH_AT91SAM9261EK bool "Atmel AT91SAM9261-EK Evaluation Kit" - depends on ARCH_AT91SAM9261 help Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. @@ -256,7 +234,6 @@ comment "AT91SAM9G10 Board Type" config MACH_AT91SAM9G10EK bool "Atmel AT91SAM9G10-EK Evaluation Kit" - depends on ARCH_AT91SAM9G10 help Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. @@ -271,21 +248,18 @@ comment "AT91SAM9263 Board Type" config MACH_AT91SAM9263EK bool "Atmel AT91SAM9263-EK Evaluation Kit" - depends on ARCH_AT91SAM9263 help Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. config MACH_USB_A9263 bool "CALAO USB-A9263" - depends on ARCH_AT91SAM9263 help Select this if you are using a Calao Systems USB-A9263. config MACH_NEOCORE926 bool "Adeneo NEOCORE926" - depends on ARCH_AT91SAM9263 help Select this if you are using the Adeneo Neocore 926 board. @@ -299,7 +273,6 @@ comment "AT91SAM9RL Board Type" config MACH_AT91SAM9RLEK bool "Atmel AT91SAM9RL-EK Evaluation Kit" - depends on ARCH_AT91SAM9RL help Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. @@ -313,14 +286,12 @@ comment "AT91SAM9G20 Board Type" config MACH_AT91SAM9G20EK bool "Atmel AT91SAM9G20-EK Evaluation Kit" - depends on ARCH_AT91SAM9G20 help Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit that embeds only one SD/MMC slot. config MACH_AT91SAM9G20EK_2MMC bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" - depends on ARCH_AT91SAM9G20 help Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and @@ -328,7 +299,6 @@ config MACH_AT91SAM9G20EK_2MMC config MACH_CPU9G20 bool "Eukrea CPU9G20 board" - depends on ARCH_AT91SAM9G20 help Select this if you are using a Eukrea Electromatique's CPU9G20 Board @@ -343,7 +313,6 @@ comment "AT91SAM9G45 Board Type" config MACH_AT91SAM9G45EKES bool "Atmel AT91SAM9G45-EKES Evaluation Kit" - depends on ARCH_AT91SAM9G45 help Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. "ES" at the end of the name means that this board is an @@ -359,7 +328,6 @@ comment "AT91CAP9 Board Type" config MACH_AT91CAP9ADK bool "Atmel AT91CAP9A-DK Evaluation Kit" - depends on ARCH_AT91CAP9 help Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit. -- cgit v1.2.3-70-g09d2 From 2ef9f59a7a3a0894be63836542f0902a45ffdd22 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 22 Oct 2009 18:50:26 +0200 Subject: at91: Kconfig simplification Instead of adding "depends on" at config level, introduce HAVE_* config variables. Add them at machine or soc level to specify the ability of a particular support. It will ease new board introduction and readability. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Nicolas Ferre Acked-by: Andrew Victor --- arch/arm/mach-at91/Kconfig | 53 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 4301c6bad80..bb4cd27c322 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,5 +1,20 @@ if ARCH_AT91 +config HAVE_AT91_DATAFLASH_CARD + bool + +config HAVE_NAND_ATMEL_BUSWIDTH_16 + bool + +config HAVE_AT91_USART3 + bool + +config HAVE_AT91_USART4 + bool + +config HAVE_AT91_USART5 + bool + menu "Atmel AT91 System-on-Chip" choice @@ -10,12 +25,16 @@ config ARCH_AT91RM9200 select CPU_ARM920T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 + select HAVE_AT91_USART4 + select HAVE_AT91_USART5 config ARCH_AT91SAM9261 bool "AT91SAM9261" @@ -40,18 +59,23 @@ config ARCH_AT91SAM9RL select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 config ARCH_AT91SAM9G20 bool "AT91SAM9G20" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 + select HAVE_AT91_USART4 + select HAVE_AT91_USART5 config ARCH_AT91SAM9G45 bool "AT91SAM9G45" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_AT91_USART3 config ARCH_AT91CAP9 bool "AT91CAP9" @@ -82,12 +106,14 @@ config MACH_ONEARM config ARCH_AT91RM9200DK bool "Atmel AT91RM9200-DK Development board" + select HAVE_AT91_DATAFLASH_CARD help Select this if you are using Atmel's AT91RM9200-DK Development board. (Discontinued) config MACH_AT91RM9200EK bool "Atmel AT91RM9200-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD help Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. @@ -135,6 +161,7 @@ config MACH_KAFA config MACH_ECBAT91 bool "emQbit ECB_AT91 SBC" + select HAVE_AT91_DATAFLASH_CARD help Select this if you are using emQbit's ECB_AT91 board. @@ -168,6 +195,8 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type" config MACH_AT91SAM9260EK bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit @@ -180,6 +209,7 @@ config MACH_CAM60 config MACH_SAM9_L9260 bool "Olimex SAM9-L9260 board" + select HAVE_AT91_DATAFLASH_CARD help Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. @@ -220,6 +250,8 @@ comment "AT91SAM9261 Board Type" config MACH_AT91SAM9261EK bool "Atmel AT91SAM9261-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. @@ -234,6 +266,8 @@ comment "AT91SAM9G10 Board Type" config MACH_AT91SAM9G10EK bool "Atmel AT91SAM9G10-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. @@ -248,6 +282,8 @@ comment "AT91SAM9263 Board Type" config MACH_AT91SAM9263EK bool "Atmel AT91SAM9263-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. @@ -260,6 +296,7 @@ config MACH_USB_A9263 config MACH_NEOCORE926 bool "Adeneo NEOCORE926" + select HAVE_AT91_DATAFLASH_CARD help Select this if you are using the Adeneo Neocore 926 board. @@ -286,12 +323,15 @@ comment "AT91SAM9G20 Board Type" config MACH_AT91SAM9G20EK bool "Atmel AT91SAM9G20-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit that embeds only one SD/MMC slot. config MACH_AT91SAM9G20EK_2MMC bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and @@ -313,6 +353,7 @@ comment "AT91SAM9G45 Board Type" config MACH_AT91SAM9G45EKES bool "Atmel AT91SAM9G45-EKES Evaluation Kit" + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. "ES" at the end of the name means that this board is an @@ -328,6 +369,8 @@ comment "AT91CAP9 Board Type" config MACH_AT91CAP9ADK bool "Atmel AT91CAP9A-DK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + select HAVE_NAND_ATMEL_BUSWIDTH_16 help Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit. @@ -356,13 +399,13 @@ comment "AT91 Board Options" config MTD_AT91_DATAFLASH_CARD bool "Enable DataFlash Card support" - depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) + depends on HAVE_AT91_DATAFLASH_CARD help Enable support for the DataFlash card. config MTD_NAND_ATMEL_BUSWIDTH_16 bool "Enable 16-bit data bus interface to NAND flash" - depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G20EK_2MMC || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK) + depends on HAVE_NAND_ATMEL_BUSWIDTH_16 help On AT91SAM926x boards both types of NAND flash can be present (8 and 16 bit data bus width). @@ -424,15 +467,15 @@ config AT91_EARLY_USART2 config AT91_EARLY_USART3 bool "USART3" - depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45) + depends on HAVE_AT91_USART3 config AT91_EARLY_USART4 bool "USART4" - depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 + depends on HAVE_AT91_USART4 config AT91_EARLY_USART5 bool "USART5" - depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 + depends on HAVE_AT91_USART5 endchoice -- cgit v1.2.3-70-g09d2 From 0912e5359f89f303f53fd4874dadab77a4949a8a Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Tue, 23 Jun 2009 16:30:56 +0200 Subject: atmel_lcdfb Kconfig: remove long dependency line Many Atmel SOC are embedding a LCD controller. This patch removes the long dependency line for this Atmel LCD framebuffer driver configuration entry. The HAVE_FB_ATMEL configuration option is located in the video Kconfig file as it may be setup by ARM/AT91 and AVR32 chips. Signed-off-by: Nicolas Ferre Acked-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Andrew Victor --- arch/arm/mach-at91/Kconfig | 6 ++++++ arch/avr32/Kconfig | 1 + drivers/video/Kconfig | 5 ++++- 3 files changed, 11 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index bb4cd27c322..3df124e5426 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -41,18 +41,21 @@ config ARCH_AT91SAM9261 select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_FB_ATMEL config ARCH_AT91SAM9G10 bool "AT91SAM9G10" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_FB_ATMEL config ARCH_AT91SAM9263 bool "AT91SAM9263" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_FB_ATMEL config ARCH_AT91SAM9RL bool "AT91SAM9RL" @@ -60,6 +63,7 @@ config ARCH_AT91SAM9RL select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 + select HAVE_FB_ATMEL config ARCH_AT91SAM9G20 bool "AT91SAM9G20" @@ -76,12 +80,14 @@ config ARCH_AT91SAM9G45 select GENERIC_TIME select GENERIC_CLOCKEVENTS select HAVE_AT91_USART3 + select HAVE_FB_ATMEL config ARCH_AT91CAP9 bool "AT91CAP9" select CPU_ARM926T select GENERIC_TIME select GENERIC_CLOCKEVENTS + select HAVE_FB_ATMEL config ARCH_AT91X40 bool "AT91x40" diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 35e3bd9858d..d856354f427 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -92,6 +92,7 @@ config PLATFORM_AT32AP select PERFORMANCE_COUNTERS select ARCH_REQUIRE_GPIOLIB select GENERIC_ALLOCATOR + select HAVE_FB_ATMEL # # CPU types diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 188e1ba3b69..6b89eb55ed3 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -5,6 +5,9 @@ menu "Graphics support" depends on HAS_IOMEM +config HAVE_FB_ATMEL + bool + source "drivers/char/agp/Kconfig" source "drivers/gpu/vga/Kconfig" @@ -937,7 +940,7 @@ config FB_S1D13XXX config FB_ATMEL tristate "AT91/AT32 LCD Controller support" - depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9G10 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 || AVR32) + depends on FB && HAVE_FB_ATMEL select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- cgit v1.2.3-70-g09d2 From 104071b6dcc66cd66db83231fd3bd58cd63e680d Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 10:14:34 +0100 Subject: imx: reorder mx2x.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx2x.h | 138 +++++++++++++++++----------------- 1 file changed, 69 insertions(+), 69 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index db5d921e0fe..c0df87f6c90 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -105,78 +105,78 @@ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) /* fixed interrupt numbers */ -#define MXC_INT_LCDC 61 -#define MXC_INT_SLCDC 60 -#define MXC_INT_EMMAPP 52 -#define MXC_INT_EMMAPRP 51 -#define MXC_INT_DMACH15 47 -#define MXC_INT_DMACH14 46 -#define MXC_INT_DMACH13 45 -#define MXC_INT_DMACH12 44 -#define MXC_INT_DMACH11 43 -#define MXC_INT_DMACH10 42 -#define MXC_INT_DMACH9 41 -#define MXC_INT_DMACH8 40 -#define MXC_INT_DMACH7 39 -#define MXC_INT_DMACH6 38 -#define MXC_INT_DMACH5 37 -#define MXC_INT_DMACH4 36 -#define MXC_INT_DMACH3 35 -#define MXC_INT_DMACH2 34 -#define MXC_INT_DMACH1 33 -#define MXC_INT_DMACH0 32 -#define MXC_INT_CSI 31 -#define MXC_INT_NANDFC 29 -#define MXC_INT_PCMCIA 28 -#define MXC_INT_WDOG 27 -#define MXC_INT_GPT1 26 -#define MXC_INT_GPT2 25 -#define MXC_INT_GPT3 24 -#define MXC_INT_GPT INT_GPT1 -#define MXC_INT_PWM 23 -#define MXC_INT_RTC 22 -#define MXC_INT_KPP 21 -#define MXC_INT_UART1 20 -#define MXC_INT_UART2 19 -#define MXC_INT_UART3 18 -#define MXC_INT_UART4 17 -#define MXC_INT_CSPI1 16 -#define MXC_INT_CSPI2 15 -#define MXC_INT_SSI1 14 -#define MXC_INT_SSI2 13 -#define MXC_INT_I2C 12 -#define MXC_INT_SDHC1 11 -#define MXC_INT_SDHC2 10 -#define MXC_INT_GPIO 8 #define MXC_INT_CSPI3 6 +#define MXC_INT_GPIO 8 +#define MXC_INT_SDHC2 10 +#define MXC_INT_SDHC1 11 +#define MXC_INT_I2C 12 +#define MXC_INT_SSI2 13 +#define MXC_INT_SSI1 14 +#define MXC_INT_CSPI2 15 +#define MXC_INT_CSPI1 16 +#define MXC_INT_UART4 17 +#define MXC_INT_UART3 18 +#define MXC_INT_UART2 19 +#define MXC_INT_UART1 20 +#define MXC_INT_KPP 21 +#define MXC_INT_RTC 22 +#define MXC_INT_PWM 23 +#define MXC_INT_GPT INT_GPT1 +#define MXC_INT_GPT3 24 +#define MXC_INT_GPT2 25 +#define MXC_INT_GPT1 26 +#define MXC_INT_WDOG 27 +#define MXC_INT_PCMCIA 28 +#define MXC_INT_NANDFC 29 +#define MXC_INT_CSI 31 +#define MXC_INT_DMACH0 32 +#define MXC_INT_DMACH1 33 +#define MXC_INT_DMACH2 34 +#define MXC_INT_DMACH3 35 +#define MXC_INT_DMACH4 36 +#define MXC_INT_DMACH5 37 +#define MXC_INT_DMACH6 38 +#define MXC_INT_DMACH7 39 +#define MXC_INT_DMACH8 40 +#define MXC_INT_DMACH9 41 +#define MXC_INT_DMACH10 42 +#define MXC_INT_DMACH11 43 +#define MXC_INT_DMACH12 44 +#define MXC_INT_DMACH13 45 +#define MXC_INT_DMACH14 46 +#define MXC_INT_DMACH15 47 +#define MXC_INT_EMMAPRP 51 +#define MXC_INT_EMMAPP 52 +#define MXC_INT_SLCDC 60 +#define MXC_INT_LCDC 61 /* fixed DMA request numbers */ -#define DMA_REQ_CSI_RX 31 -#define DMA_REQ_CSI_STAT 30 -#define DMA_REQ_UART1_TX 27 -#define DMA_REQ_UART1_RX 26 -#define DMA_REQ_UART2_TX 25 -#define DMA_REQ_UART2_RX 24 -#define DMA_REQ_UART3_TX 23 -#define DMA_REQ_UART3_RX 22 -#define DMA_REQ_UART4_TX 21 -#define DMA_REQ_UART4_RX 20 -#define DMA_REQ_CSPI1_TX 19 -#define DMA_REQ_CSPI1_RX 18 -#define DMA_REQ_CSPI2_TX 17 -#define DMA_REQ_CSPI2_RX 16 -#define DMA_REQ_SSI1_TX1 15 -#define DMA_REQ_SSI1_RX1 14 -#define DMA_REQ_SSI1_TX0 13 -#define DMA_REQ_SSI1_RX0 12 -#define DMA_REQ_SSI2_TX1 11 -#define DMA_REQ_SSI2_RX1 10 -#define DMA_REQ_SSI2_TX0 9 -#define DMA_REQ_SSI2_RX0 8 -#define DMA_REQ_SDHC1 7 -#define DMA_REQ_SDHC2 6 -#define DMA_REQ_EXT 3 -#define DMA_REQ_CSPI3_TX 2 #define DMA_REQ_CSPI3_RX 1 +#define DMA_REQ_CSPI3_TX 2 +#define DMA_REQ_EXT 3 +#define DMA_REQ_SDHC2 6 +#define DMA_REQ_SDHC1 7 +#define DMA_REQ_SSI2_RX0 8 +#define DMA_REQ_SSI2_TX0 9 +#define DMA_REQ_SSI2_RX1 10 +#define DMA_REQ_SSI2_TX1 11 +#define DMA_REQ_SSI1_RX0 12 +#define DMA_REQ_SSI1_TX0 13 +#define DMA_REQ_SSI1_RX1 14 +#define DMA_REQ_SSI1_TX1 15 +#define DMA_REQ_CSPI2_RX 16 +#define DMA_REQ_CSPI2_TX 17 +#define DMA_REQ_CSPI1_RX 18 +#define DMA_REQ_CSPI1_TX 19 +#define DMA_REQ_UART4_RX 20 +#define DMA_REQ_UART4_TX 21 +#define DMA_REQ_UART3_RX 22 +#define DMA_REQ_UART3_TX 23 +#define DMA_REQ_UART2_RX 24 +#define DMA_REQ_UART2_TX 25 +#define DMA_REQ_UART1_RX 26 +#define DMA_REQ_UART1_TX 27 +#define DMA_REQ_CSI_STAT 30 +#define DMA_REQ_CSI_RX 31 #endif /* __ASM_ARCH_MXC_MX2x_H__ */ -- cgit v1.2.3-70-g09d2 From 27085f25184ee5a206706dd5f734ade1d15551fa Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 10:15:13 +0100 Subject: imx: reorder mx21.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx21.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 21112c695ec..2b1fccb748f 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -34,8 +34,8 @@ #define CS2_BASE_ADDR 0xD0000000 #define CS3_BASE_ADDR 0xD1000000 #define CS4_BASE_ADDR 0xD2000000 -#define CS5_BASE_ADDR 0xDD000000 #define PCMCIA_MEM_BASE_ADDR 0xD4000000 +#define CS5_BASE_ADDR 0xDD000000 /* NAND, SDRAM, WEIM etc controllers */ #define X_MEMC_BASE_ADDR 0xDF000000 @@ -50,21 +50,21 @@ #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ /* fixed interrupt numbers */ +#define MXC_INT_FIRI 9 +#define MXC_INT_BMI 30 +#define MXC_INT_EMMAENC 49 +#define MXC_INT_EMMADEC 50 +#define MXC_INT_USBWKUP 53 +#define MXC_INT_USBDMA 54 +#define MXC_INT_USBHOST 55 +#define MXC_INT_USBFUNC 56 +#define MXC_INT_USBMNP 57 #define MXC_INT_USBCTRL 58 #define MXC_INT_USBCTRL 58 -#define MXC_INT_USBMNP 57 -#define MXC_INT_USBFUNC 56 -#define MXC_INT_USBHOST 55 -#define MXC_INT_USBDMA 54 -#define MXC_INT_USBWKUP 53 -#define MXC_INT_EMMADEC 50 -#define MXC_INT_EMMAENC 49 -#define MXC_INT_BMI 30 -#define MXC_INT_FIRI 9 /* fixed DMA request numbers */ -#define DMA_REQ_BMI_RX 29 -#define DMA_REQ_BMI_TX 28 #define DMA_REQ_FIRI_RX 4 +#define DMA_REQ_BMI_TX 28 +#define DMA_REQ_BMI_RX 29 #endif /* __ASM_ARCH_MXC_MX21_H__ */ -- cgit v1.2.3-70-g09d2 From f73a42f7054b4ec7fab373789b7dae1e309f81a7 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 10:18:08 +0100 Subject: imx: reorder mx27.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx27.h | 63 ++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index dc3ad9aa952..0104c20bbda 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,9 +24,6 @@ #ifndef __ASM_ARCH_MXC_MX27_H__ #define __ASM_ARCH_MXC_MX27_H__ -/* IRAM */ -#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ - #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) @@ -60,7 +57,6 @@ #define CS3_BASE_ADDR 0xD2000000 #define CS4_BASE_ADDR 0xD4000000 #define CS5_BASE_ADDR 0xD6000000 -#define PCMCIA_MEM_BASE_ADDR 0xDC000000 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define X_MEMC_BASE_ADDR 0xD8000000 @@ -73,38 +69,43 @@ #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) +#define PCMCIA_MEM_BASE_ADDR 0xDC000000 + +/* IRAM */ +#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ + /* fixed interrupt numbers */ -#define MXC_INT_CCM 63 -#define MXC_INT_IIM 62 -#define MXC_INT_SAHARA 59 -#define MXC_INT_SCC_SCM 58 -#define MXC_INT_SCC_SMN 57 -#define MXC_INT_USB3 56 -#define MXC_INT_USB2 55 -#define MXC_INT_USB1 54 -#define MXC_INT_VPU 53 -#define MXC_INT_FEC 50 -#define MXC_INT_UART5 49 -#define MXC_INT_UART6 48 -#define MXC_INT_ATA 30 -#define MXC_INT_SDHC3 9 -#define MXC_INT_SDHC 7 -#define MXC_INT_RTIC 5 -#define MXC_INT_GPT4 4 -#define MXC_INT_GPT5 3 -#define MXC_INT_GPT6 2 #define MXC_INT_I2C2 1 +#define MXC_INT_GPT6 2 +#define MXC_INT_GPT5 3 +#define MXC_INT_GPT4 4 +#define MXC_INT_RTIC 5 +#define MXC_INT_SDHC 7 +#define MXC_INT_SDHC3 9 +#define MXC_INT_ATA 30 +#define MXC_INT_UART6 48 +#define MXC_INT_UART5 49 +#define MXC_INT_FEC 50 +#define MXC_INT_VPU 53 +#define MXC_INT_USB1 54 +#define MXC_INT_USB2 55 +#define MXC_INT_USB3 56 +#define MXC_INT_SCC_SMN 57 +#define MXC_INT_SCC_SCM 58 +#define MXC_INT_SAHARA 59 +#define MXC_INT_IIM 62 +#define MXC_INT_CCM 63 /* fixed DMA request numbers */ -#define DMA_REQ_NFC 37 -#define DMA_REQ_SDHC3 36 -#define DMA_REQ_UART6_RX 35 -#define DMA_REQ_UART6_TX 34 -#define DMA_REQ_UART5_RX 33 -#define DMA_REQ_UART5_TX 32 -#define DMA_REQ_ATA_RCV 29 -#define DMA_REQ_ATA_TX 28 #define DMA_REQ_MSHC 4 +#define DMA_REQ_ATA_TX 28 +#define DMA_REQ_ATA_RCV 29 +#define DMA_REQ_UART5_TX 32 +#define DMA_REQ_UART5_RX 33 +#define DMA_REQ_UART6_TX 34 +#define DMA_REQ_UART6_RX 35 +#define DMA_REQ_SDHC3 36 +#define DMA_REQ_NFC 37 /* silicon revisions specific to i.MX27 */ #define CHIP_REV_1_0 0x00 -- cgit v1.2.3-70-g09d2 From e676756fa43e04166111e4729c62bb4fdf477255 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 10:20:30 +0100 Subject: imx: reorder mx3x.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx3x.h | 45 ++++++++++++++++++----------------- 1 file changed, 23 insertions(+), 22 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 009f4440276..3e07d3da104 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -34,21 +34,6 @@ * C0000000 64M PCMCIA/CF */ -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 - -#define CS4_BASE_ADDR 0xB4000000 -#define CS4_BASE_ADDR_VIRT 0xF4000000 -#define CS4_SIZE SZ_32M - -#define CS5_BASE_ADDR 0xB6000000 -#define CS5_BASE_ADDR_VIRT 0xF6000000 -#define CS5_SIZE SZ_32M - -#define PCMCIA_MEM_BASE_ADDR 0xBC000000 - /* * L2CC */ @@ -101,6 +86,7 @@ #define AIPS2_BASE_ADDR 0x53F00000 #define AIPS2_BASE_ADDR_VIRT 0xFC200000 #define AIPS2_SIZE SZ_1M + #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) @@ -129,6 +115,27 @@ #define AVIC_BASE_ADDR_VIRT 0xFC400000 #define AVIC_SIZE SZ_1M +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE_ADDR 0x70000000 +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 + +#define CS0_BASE_ADDR 0xA0000000 +#define CS1_BASE_ADDR 0xA8000000 +#define CS2_BASE_ADDR 0xB0000000 +#define CS3_BASE_ADDR 0xB2000000 + +#define CS4_BASE_ADDR 0xB4000000 +#define CS4_BASE_ADDR_VIRT 0xF4000000 +#define CS4_SIZE SZ_32M + +#define CS5_BASE_ADDR 0xB6000000 +#define CS5_BASE_ADDR_VIRT 0xF6000000 +#define CS5_SIZE SZ_32M + + /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ @@ -142,12 +149,7 @@ #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR -/* - * Memory regions and CS - */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 +#define PCMCIA_MEM_BASE_ADDR 0xBC000000 /*! * This macro defines the physical to virtual address mapping for all the @@ -272,4 +274,3 @@ static inline int mx31_revision(void) #endif #endif /* __ASM_ARCH_MXC_MX31_H__ */ - -- cgit v1.2.3-70-g09d2 From b9fc90a48a3d1794443e095d8585dcaeafb2195f Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 11:34:22 +0100 Subject: imx: add namespace prefixes for symbols in mx2x.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx2x.h | 339 ++++++++++++++++++++++------------ 1 file changed, 224 insertions(+), 115 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index c0df87f6c90..1766c7c9184 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -26,50 +26,48 @@ /* The following addresses are common between i.MX21 and i.MX27 */ /* Register offests */ -#define AIPI_BASE_ADDR 0x10000000 -#define AIPI_BASE_ADDR_VIRT 0xF4000000 -#define AIPI_SIZE SZ_1M - -#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) -#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) -#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) -#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) -#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) -#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) -#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) -#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) -#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) -#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) -#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) -#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) -#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) -#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) -#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) -#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) -#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) -#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) -#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) -#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) -#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) -#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) -#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) -#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) -#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) -#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) -#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) -#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) -#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) -#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) -#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) -#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) - -#define AVIC_BASE_ADDR 0x10040000 - -#define SAHB1_BASE_ADDR 0x80000000 -#define SAHB1_BASE_ADDR_VIRT 0xF4100000 -#define SAHB1_SIZE SZ_1M - -#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) +#define MX2x_AIPI_BASE_ADDR 0x10000000 +#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 +#define MX2x_AIPI_SIZE SZ_1M +#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) +#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) +#define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) +#define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) +#define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) +#define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) +#define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) +#define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) +#define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) +#define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) +#define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) +#define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) +#define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) +#define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) +#define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) +#define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) +#define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) +#define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) +#define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) +#define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) +#define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) +#define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) +#define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) +#define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) +#define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) +#define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) +#define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) +#define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) +#define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) +#define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) +#define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) +#define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) + +#define MX2x_AVIC_BASE_ADDR 0x10040000 + +#define MX2x_SAHB1_BASE_ADDR 0x80000000 +#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 +#define MX2x_SAHB1_SIZE SZ_1M +#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) /* * This macro defines the physical to virtual address mapping for all the @@ -105,78 +103,189 @@ (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) /* fixed interrupt numbers */ -#define MXC_INT_CSPI3 6 -#define MXC_INT_GPIO 8 -#define MXC_INT_SDHC2 10 -#define MXC_INT_SDHC1 11 -#define MXC_INT_I2C 12 -#define MXC_INT_SSI2 13 -#define MXC_INT_SSI1 14 -#define MXC_INT_CSPI2 15 -#define MXC_INT_CSPI1 16 -#define MXC_INT_UART4 17 -#define MXC_INT_UART3 18 -#define MXC_INT_UART2 19 -#define MXC_INT_UART1 20 -#define MXC_INT_KPP 21 -#define MXC_INT_RTC 22 -#define MXC_INT_PWM 23 -#define MXC_INT_GPT INT_GPT1 -#define MXC_INT_GPT3 24 -#define MXC_INT_GPT2 25 -#define MXC_INT_GPT1 26 -#define MXC_INT_WDOG 27 -#define MXC_INT_PCMCIA 28 -#define MXC_INT_NANDFC 29 -#define MXC_INT_CSI 31 -#define MXC_INT_DMACH0 32 -#define MXC_INT_DMACH1 33 -#define MXC_INT_DMACH2 34 -#define MXC_INT_DMACH3 35 -#define MXC_INT_DMACH4 36 -#define MXC_INT_DMACH5 37 -#define MXC_INT_DMACH6 38 -#define MXC_INT_DMACH7 39 -#define MXC_INT_DMACH8 40 -#define MXC_INT_DMACH9 41 -#define MXC_INT_DMACH10 42 -#define MXC_INT_DMACH11 43 -#define MXC_INT_DMACH12 44 -#define MXC_INT_DMACH13 45 -#define MXC_INT_DMACH14 46 -#define MXC_INT_DMACH15 47 -#define MXC_INT_EMMAPRP 51 -#define MXC_INT_EMMAPP 52 -#define MXC_INT_SLCDC 60 -#define MXC_INT_LCDC 61 +#define MX2x_INT_CSPI3 6 +#define MX2x_INT_GPIO 8 +#define MX2x_INT_SDHC2 10 +#define MX2x_INT_SDHC1 11 +#define MX2x_INT_I2C 12 +#define MX2x_INT_SSI2 13 +#define MX2x_INT_SSI1 14 +#define MX2x_INT_CSPI2 15 +#define MX2x_INT_CSPI1 16 +#define MX2x_INT_UART4 17 +#define MX2x_INT_UART3 18 +#define MX2x_INT_UART2 19 +#define MX2x_INT_UART1 20 +#define MX2x_INT_KPP 21 +#define MX2x_INT_RTC 22 +#define MX2x_INT_PWM 23 +#define MX2x_INT_GPT3 24 +#define MX2x_INT_GPT2 25 +#define MX2x_INT_GPT1 26 +#define MX2x_INT_WDOG 27 +#define MX2x_INT_PCMCIA 28 +#define MX2x_INT_NANDFC 29 +#define MX2x_INT_CSI 31 +#define MX2x_INT_DMACH0 32 +#define MX2x_INT_DMACH1 33 +#define MX2x_INT_DMACH2 34 +#define MX2x_INT_DMACH3 35 +#define MX2x_INT_DMACH4 36 +#define MX2x_INT_DMACH5 37 +#define MX2x_INT_DMACH6 38 +#define MX2x_INT_DMACH7 39 +#define MX2x_INT_DMACH8 40 +#define MX2x_INT_DMACH9 41 +#define MX2x_INT_DMACH10 42 +#define MX2x_INT_DMACH11 43 +#define MX2x_INT_DMACH12 44 +#define MX2x_INT_DMACH13 45 +#define MX2x_INT_DMACH14 46 +#define MX2x_INT_DMACH15 47 +#define MX2x_INT_EMMAPRP 51 +#define MX2x_INT_EMMAPP 52 +#define MX2x_INT_SLCDC 60 +#define MX2x_INT_LCDC 61 /* fixed DMA request numbers */ -#define DMA_REQ_CSPI3_RX 1 -#define DMA_REQ_CSPI3_TX 2 -#define DMA_REQ_EXT 3 -#define DMA_REQ_SDHC2 6 -#define DMA_REQ_SDHC1 7 -#define DMA_REQ_SSI2_RX0 8 -#define DMA_REQ_SSI2_TX0 9 -#define DMA_REQ_SSI2_RX1 10 -#define DMA_REQ_SSI2_TX1 11 -#define DMA_REQ_SSI1_RX0 12 -#define DMA_REQ_SSI1_TX0 13 -#define DMA_REQ_SSI1_RX1 14 -#define DMA_REQ_SSI1_TX1 15 -#define DMA_REQ_CSPI2_RX 16 -#define DMA_REQ_CSPI2_TX 17 -#define DMA_REQ_CSPI1_RX 18 -#define DMA_REQ_CSPI1_TX 19 -#define DMA_REQ_UART4_RX 20 -#define DMA_REQ_UART4_TX 21 -#define DMA_REQ_UART3_RX 22 -#define DMA_REQ_UART3_TX 23 -#define DMA_REQ_UART2_RX 24 -#define DMA_REQ_UART2_TX 25 -#define DMA_REQ_UART1_RX 26 -#define DMA_REQ_UART1_TX 27 -#define DMA_REQ_CSI_STAT 30 -#define DMA_REQ_CSI_RX 31 +#define MX2x_DMA_REQ_CSPI3_RX 1 +#define MX2x_DMA_REQ_CSPI3_TX 2 +#define MX2x_DMA_REQ_EXT 3 +#define MX2x_DMA_REQ_SDHC2 6 +#define MX2x_DMA_REQ_SDHC1 7 +#define MX2x_DMA_REQ_SSI2_RX0 8 +#define MX2x_DMA_REQ_SSI2_TX0 9 +#define MX2x_DMA_REQ_SSI2_RX1 10 +#define MX2x_DMA_REQ_SSI2_TX1 11 +#define MX2x_DMA_REQ_SSI1_RX0 12 +#define MX2x_DMA_REQ_SSI1_TX0 13 +#define MX2x_DMA_REQ_SSI1_RX1 14 +#define MX2x_DMA_REQ_SSI1_TX1 15 +#define MX2x_DMA_REQ_CSPI2_RX 16 +#define MX2x_DMA_REQ_CSPI2_TX 17 +#define MX2x_DMA_REQ_CSPI1_RX 18 +#define MX2x_DMA_REQ_CSPI1_TX 19 +#define MX2x_DMA_REQ_UART4_RX 20 +#define MX2x_DMA_REQ_UART4_TX 21 +#define MX2x_DMA_REQ_UART3_RX 22 +#define MX2x_DMA_REQ_UART3_TX 23 +#define MX2x_DMA_REQ_UART2_RX 24 +#define MX2x_DMA_REQ_UART2_TX 25 +#define MX2x_DMA_REQ_UART1_RX 26 +#define MX2x_DMA_REQ_UART1_TX 27 +#define MX2x_DMA_REQ_CSI_STAT 30 +#define MX2x_DMA_REQ_CSI_RX 31 + +/* these should go away */ +#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR +#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT +#define AIPI_SIZE MX2x_AIPI_SIZE +#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR +#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR +#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR +#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR +#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR +#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR +#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR +#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR +#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR +#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR +#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR +#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR +#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR +#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR +#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR +#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR +#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR +#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR +#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR +#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR +#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR +#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR +#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR +#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR +#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR +#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR +#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR +#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR +#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR +#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR +#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR +#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR +#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR +#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT +#define SAHB1_SIZE MX2x_SAHB1_SIZE +#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR +#define MXC_INT_CSPI3 MX2x_INT_CSPI3 +#define MXC_INT_GPIO MX2x_INT_GPIO +#define MXC_INT_SDHC2 MX2x_INT_SDHC2 +#define MXC_INT_SDHC1 MX2x_INT_SDHC1 +#define MXC_INT_I2C MX2x_INT_I2C +#define MXC_INT_SSI2 MX2x_INT_SSI2 +#define MXC_INT_SSI1 MX2x_INT_SSI1 +#define MXC_INT_CSPI2 MX2x_INT_CSPI2 +#define MXC_INT_CSPI1 MX2x_INT_CSPI1 +#define MXC_INT_UART4 MX2x_INT_UART4 +#define MXC_INT_UART3 MX2x_INT_UART3 +#define MXC_INT_UART2 MX2x_INT_UART2 +#define MXC_INT_UART1 MX2x_INT_UART1 +#define MXC_INT_KPP MX2x_INT_KPP +#define MXC_INT_RTC MX2x_INT_RTC +#define MXC_INT_PWM MX2x_INT_PWM +#define MXC_INT_GPT3 MX2x_INT_GPT3 +#define MXC_INT_GPT2 MX2x_INT_GPT2 +#define MXC_INT_GPT1 MX2x_INT_GPT1 +#define MXC_INT_WDOG MX2x_INT_WDOG +#define MXC_INT_PCMCIA MX2x_INT_PCMCIA +#define MXC_INT_NANDFC MX2x_INT_NANDFC +#define MXC_INT_CSI MX2x_INT_CSI +#define MXC_INT_DMACH0 MX2x_INT_DMACH0 +#define MXC_INT_DMACH1 MX2x_INT_DMACH1 +#define MXC_INT_DMACH2 MX2x_INT_DMACH2 +#define MXC_INT_DMACH3 MX2x_INT_DMACH3 +#define MXC_INT_DMACH4 MX2x_INT_DMACH4 +#define MXC_INT_DMACH5 MX2x_INT_DMACH5 +#define MXC_INT_DMACH6 MX2x_INT_DMACH6 +#define MXC_INT_DMACH7 MX2x_INT_DMACH7 +#define MXC_INT_DMACH8 MX2x_INT_DMACH8 +#define MXC_INT_DMACH9 MX2x_INT_DMACH9 +#define MXC_INT_DMACH10 MX2x_INT_DMACH10 +#define MXC_INT_DMACH11 MX2x_INT_DMACH11 +#define MXC_INT_DMACH12 MX2x_INT_DMACH12 +#define MXC_INT_DMACH13 MX2x_INT_DMACH13 +#define MXC_INT_DMACH14 MX2x_INT_DMACH14 +#define MXC_INT_DMACH15 MX2x_INT_DMACH15 +#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP +#define MXC_INT_EMMAPP MX2x_INT_EMMAPP +#define MXC_INT_SLCDC MX2x_INT_SLCDC +#define MXC_INT_LCDC MX2x_INT_LCDC +#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX +#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX +#define DMA_REQ_EXT MX2x_DMA_REQ_EXT +#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 +#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 +#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 +#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 +#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 +#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 +#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 +#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 +#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 +#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 +#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX +#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX +#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX +#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX +#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX +#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX +#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX +#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX +#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX +#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX +#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX +#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX +#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT +#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX #endif /* __ASM_ARCH_MXC_MX2x_H__ */ -- cgit v1.2.3-70-g09d2 From c112931377589d751c012fa5c914c17b5d426be1 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 14:59:54 +0100 Subject: imx: add namespace prefixes for symbols in mx21.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx21.h | 95 +++++++++++++++++++++++------------ 1 file changed, 64 insertions(+), 31 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 2b1fccb748f..986f08bd9c0 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -26,45 +26,78 @@ #define __ASM_ARCH_MXC_MX21_H__ /* Memory regions and CS */ -#define SDRAM_BASE_ADDR 0xC0000000 -#define CSD1_BASE_ADDR 0xC4000000 +#define MX21_SDRAM_BASE_ADDR 0xc0000000 +#define MX21_CSD1_BASE_ADDR 0xc4000000 -#define CS0_BASE_ADDR 0xC8000000 -#define CS1_BASE_ADDR 0xCC000000 -#define CS2_BASE_ADDR 0xD0000000 -#define CS3_BASE_ADDR 0xD1000000 -#define CS4_BASE_ADDR 0xD2000000 -#define PCMCIA_MEM_BASE_ADDR 0xD4000000 -#define CS5_BASE_ADDR 0xDD000000 +#define MX21_CS0_BASE_ADDR 0xc8000000 +#define MX21_CS1_BASE_ADDR 0xcc000000 +#define MX21_CS2_BASE_ADDR 0xd0000000 +#define MX21_CS3_BASE_ADDR 0xd1000000 +#define MX21_CS4_BASE_ADDR 0xd2000000 +#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 +#define MX21_CS5_BASE_ADDR 0xdd000000 /* NAND, SDRAM, WEIM etc controllers */ -#define X_MEMC_BASE_ADDR 0xDF000000 -#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 -#define X_MEMC_SIZE SZ_256K +#define MX21_X_MEMC_BASE_ADDR 0xdf000000 +#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 +#define MX21_X_MEMC_SIZE SZ_256K -#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) -#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) -#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) -#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) +#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) +#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) +#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) +#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) -#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ +#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ /* fixed interrupt numbers */ -#define MXC_INT_FIRI 9 -#define MXC_INT_BMI 30 -#define MXC_INT_EMMAENC 49 -#define MXC_INT_EMMADEC 50 -#define MXC_INT_USBWKUP 53 -#define MXC_INT_USBDMA 54 -#define MXC_INT_USBHOST 55 -#define MXC_INT_USBFUNC 56 -#define MXC_INT_USBMNP 57 -#define MXC_INT_USBCTRL 58 -#define MXC_INT_USBCTRL 58 +#define MX21_INT_FIRI 9 +#define MX21_INT_BMI 30 +#define MX21_INT_EMMAENC 49 +#define MX21_INT_EMMADEC 50 +#define MX21_INT_USBWKUP 53 +#define MX21_INT_USBDMA 54 +#define MX21_INT_USBHOST 55 +#define MX21_INT_USBFUNC 56 +#define MX21_INT_USBMNP 57 +#define MX21_INT_USBCTRL 58 +#define MX21_INT_USBCTRL 58 /* fixed DMA request numbers */ -#define DMA_REQ_FIRI_RX 4 -#define DMA_REQ_BMI_TX 28 -#define DMA_REQ_BMI_RX 29 +#define MX21_DMA_REQ_FIRI_RX 4 +#define MX21_DMA_REQ_BMI_TX 28 +#define MX21_DMA_REQ_BMI_RX 29 + +/* these should go away */ +#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR +#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR +#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR +#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR +#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR +#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR +#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR +#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR +#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR +#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR +#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT +#define X_MEMC_SIZE MX21_X_MEMC_SIZE +#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR +#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR +#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR +#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR +#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR +#define MXC_INT_FIRI MX21_INT_FIRI +#define MXC_INT_BMI MX21_INT_BMI +#define MXC_INT_EMMAENC MX21_INT_EMMAENC +#define MXC_INT_EMMADEC MX21_INT_EMMADEC +#define MXC_INT_USBWKUP MX21_INT_USBWKUP +#define MXC_INT_USBDMA MX21_INT_USBDMA +#define MXC_INT_USBHOST MX21_INT_USBHOST +#define MXC_INT_USBFUNC MX21_INT_USBFUNC +#define MXC_INT_USBMNP MX21_INT_USBMNP +#define MXC_INT_USBCTRL MX21_INT_USBCTRL +#define MXC_INT_USBCTRL MX21_INT_USBCTRL +#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX +#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX +#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX #endif /* __ASM_ARCH_MXC_MX21_H__ */ -- cgit v1.2.3-70-g09d2 From 26b10e744322da31160a81edd4e6462ac581da91 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 15:26:21 +0100 Subject: imx: add namespace prefixes for symbols in mx27.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx27.h | 201 ++++++++++++++++++++++------------ 1 file changed, 133 insertions(+), 68 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 0104c20bbda..b619aa4f27b 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,88 +24,87 @@ #ifndef __ASM_ARCH_MXC_MX27_H__ #define __ASM_ARCH_MXC_MX27_H__ -#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) -#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) -#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) -#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000) -#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000) -#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) -#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) -#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) -#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) -#define OTG_BASE_ADDR USBOTG_BASE_ADDR -#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) -#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) -#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) -#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) -#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) -#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) -#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) +#define MX27_MSHC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x18000) +#define MX27_GPT5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1a000) +#define MX27_UART5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1b000) +#define MX27_UART6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1c000) +#define MX27_I2C2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1d000) +#define MX27_SDHC3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1e000) +#define MX27_GPT6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1f000) +#define MX27_VPU_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x23000) +#define MX27_OTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR +#define MX27_SAHARA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x25000) +#define MX27_IIM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x28000) +#define MX27_RTIC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2a000) +#define MX27_FEC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2b000) +#define MX27_SCC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2c000) +#define MX27_ETB_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3b000) +#define MX27_ETB_RAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3c000) /* ROM patch */ -#define ROMP_BASE_ADDR 0x10041000 +#define MX27_ROMP_BASE_ADDR 0x10041000 -#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) +#define MX27_ATA_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x1000) /* Memory regions and CS */ -#define SDRAM_BASE_ADDR 0xA0000000 -#define CSD1_BASE_ADDR 0xB0000000 +#define MX27_SDRAM_BASE_ADDR 0xa0000000 +#define MX27_CSD1_BASE_ADDR 0xb0000000 -#define CS0_BASE_ADDR 0xC0000000 -#define CS1_BASE_ADDR 0xC8000000 -#define CS2_BASE_ADDR 0xD0000000 -#define CS3_BASE_ADDR 0xD2000000 -#define CS4_BASE_ADDR 0xD4000000 -#define CS5_BASE_ADDR 0xD6000000 +#define MX27_CS0_BASE_ADDR 0xc0000000 +#define MX27_CS1_BASE_ADDR 0xc8000000 +#define MX27_CS2_BASE_ADDR 0xd0000000 +#define MX27_CS3_BASE_ADDR 0xd2000000 +#define MX27_CS4_BASE_ADDR 0xd4000000 +#define MX27_CS5_BASE_ADDR 0xd6000000 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ -#define X_MEMC_BASE_ADDR 0xD8000000 -#define X_MEMC_BASE_ADDR_VIRT 0xF4200000 -#define X_MEMC_SIZE SZ_1M +#define MX27_X_MEMC_BASE_ADDR 0xd8000000 +#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 +#define MX27_X_MEMC_SIZE SZ_1M +#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) +#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) +#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) +#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) +#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) -#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) -#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) -#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) -#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) -#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) - -#define PCMCIA_MEM_BASE_ADDR 0xDC000000 +#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 /* IRAM */ -#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ +#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ /* fixed interrupt numbers */ -#define MXC_INT_I2C2 1 -#define MXC_INT_GPT6 2 -#define MXC_INT_GPT5 3 -#define MXC_INT_GPT4 4 -#define MXC_INT_RTIC 5 -#define MXC_INT_SDHC 7 -#define MXC_INT_SDHC3 9 -#define MXC_INT_ATA 30 -#define MXC_INT_UART6 48 -#define MXC_INT_UART5 49 -#define MXC_INT_FEC 50 -#define MXC_INT_VPU 53 -#define MXC_INT_USB1 54 -#define MXC_INT_USB2 55 -#define MXC_INT_USB3 56 -#define MXC_INT_SCC_SMN 57 -#define MXC_INT_SCC_SCM 58 -#define MXC_INT_SAHARA 59 -#define MXC_INT_IIM 62 -#define MXC_INT_CCM 63 +#define MX27_INT_I2C2 1 +#define MX27_INT_GPT6 2 +#define MX27_INT_GPT5 3 +#define MX27_INT_GPT4 4 +#define MX27_INT_RTIC 5 +#define MX27_INT_SDHC 7 +#define MX27_INT_SDHC3 9 +#define MX27_INT_ATA 30 +#define MX27_INT_UART6 48 +#define MX27_INT_UART5 49 +#define MX27_INT_FEC 50 +#define MX27_INT_VPU 53 +#define MX27_INT_USB1 54 +#define MX27_INT_USB2 55 +#define MX27_INT_USB3 56 +#define MX27_INT_SCC_SMN 57 +#define MX27_INT_SCC_SCM 58 +#define MX27_INT_SAHARA 59 +#define MX27_INT_IIM 62 +#define MX27_INT_CCM 63 /* fixed DMA request numbers */ -#define DMA_REQ_MSHC 4 -#define DMA_REQ_ATA_TX 28 -#define DMA_REQ_ATA_RCV 29 -#define DMA_REQ_UART5_TX 32 -#define DMA_REQ_UART5_RX 33 -#define DMA_REQ_UART6_TX 34 -#define DMA_REQ_UART6_RX 35 -#define DMA_REQ_SDHC3 36 -#define DMA_REQ_NFC 37 +#define MX27_DMA_REQ_MSHC 4 +#define MX27_DMA_REQ_ATA_TX 28 +#define MX27_DMA_REQ_ATA_RCV 29 +#define MX27_DMA_REQ_UART5_TX 32 +#define MX27_DMA_REQ_UART5_RX 33 +#define MX27_DMA_REQ_UART6_TX 34 +#define MX27_DMA_REQ_UART6_RX 35 +#define MX27_DMA_REQ_SDHC3 36 +#define MX27_DMA_REQ_NFC 37 /* silicon revisions specific to i.MX27 */ #define CHIP_REV_1_0 0x00 @@ -115,6 +114,72 @@ extern int mx27_revision(void); #endif -/* Mandatory defines used globally */ +/* these should go away */ +#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR +#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR +#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR +#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR +#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR +#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR +#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR +#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR +#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR +#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR +#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR +#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR +#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR +#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR +#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR +#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR +#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR +#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR +#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR +#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR +#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR +#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR +#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR +#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR +#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR +#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR +#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR +#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR +#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT +#define X_MEMC_SIZE MX27_X_MEMC_SIZE +#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR +#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR +#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR +#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR +#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR +#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR +#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR +#define MXC_INT_I2C2 MX27_INT_I2C2 +#define MXC_INT_GPT6 MX27_INT_GPT6 +#define MXC_INT_GPT5 MX27_INT_GPT5 +#define MXC_INT_GPT4 MX27_INT_GPT4 +#define MXC_INT_RTIC MX27_INT_RTIC +#define MXC_INT_SDHC MX27_INT_SDHC +#define MXC_INT_SDHC3 MX27_INT_SDHC3 +#define MXC_INT_ATA MX27_INT_ATA +#define MXC_INT_UART6 MX27_INT_UART6 +#define MXC_INT_UART5 MX27_INT_UART5 +#define MXC_INT_FEC MX27_INT_FEC +#define MXC_INT_VPU MX27_INT_VPU +#define MXC_INT_USB1 MX27_INT_USB1 +#define MXC_INT_USB2 MX27_INT_USB2 +#define MXC_INT_USB3 MX27_INT_USB3 +#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN +#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM +#define MXC_INT_SAHARA MX27_INT_SAHARA +#define MXC_INT_IIM MX27_INT_IIM +#define MXC_INT_CCM MX27_INT_CCM +#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC +#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX +#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV +#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX +#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX +#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX +#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX +#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 +#define DMA_REQ_NFC MX27_DMA_REQ_NFC #endif /* __ASM_ARCH_MXC_MX27_H__ */ -- cgit v1.2.3-70-g09d2 From e4d0f7c71d60f7a783edd6dcc97423fcc9973aaf Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 10 Nov 2009 21:31:30 +0100 Subject: imx: add namespace prefixes for symbols in mx3x.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx3x.h | 404 ++++++++++++++++++++++------------ 1 file changed, 266 insertions(+), 138 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 3e07d3da104..8cedf29eee1 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -37,119 +37,114 @@ /* * L2CC */ -#define L2CC_BASE_ADDR 0x30000000 -#define L2CC_SIZE SZ_1M +#define MX3x_L2CC_BASE_ADDR 0x30000000 +#define MX3x_L2CC_SIZE SZ_1M /* * AIPS 1 */ -#define AIPS1_BASE_ADDR 0x43F00000 -#define AIPS1_BASE_ADDR_VIRT 0xFC000000 -#define AIPS1_SIZE SZ_1M - -#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) -#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) -#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) -#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) -#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) -#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) -#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) -#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) -#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) -#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) -#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) -#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) -#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) -#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) -#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define MX3x_AIPS1_BASE_ADDR 0x43f00000 +#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 +#define MX3x_AIPS1_SIZE SZ_1M +#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) +#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) +#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) +#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) +#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) +#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) +#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) +#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) +#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) +#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) +#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) +#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) +#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) +#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) +#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) +#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) +#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) +#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) /* * SPBA global module enabled #0 */ -#define SPBA0_BASE_ADDR 0x50000000 -#define SPBA0_BASE_ADDR_VIRT 0xFC100000 -#define SPBA0_SIZE SZ_1M - -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) -#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) -#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) -#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) -#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) +#define MX3x_SPBA0_BASE_ADDR 0x50000000 +#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 +#define MX3x_SPBA0_SIZE SZ_1M +#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) +#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) +#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) +#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) +#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) +#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) /* * AIPS 2 */ -#define AIPS2_BASE_ADDR 0x53F00000 -#define AIPS2_BASE_ADDR_VIRT 0xFC200000 -#define AIPS2_SIZE SZ_1M - -#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) -#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) -#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) -#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) -#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) -#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) -#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) -#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) -#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) -#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) -#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) -#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) -#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) -#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) -#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) -#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define MX3x_AIPS2_BASE_ADDR 0x53f00000 +#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 +#define MX3x_AIPS2_SIZE SZ_1M +#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) +#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) +#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) +#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) +#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) +#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) +#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) +#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) +#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) +#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) +#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) +#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) +#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) +#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) +#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) +#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) /* * ROMP and AVIC */ -#define ROMP_BASE_ADDR 0x60000000 -#define ROMP_BASE_ADDR_VIRT 0xFC500000 -#define ROMP_SIZE SZ_1M +#define MX3x_ROMP_BASE_ADDR 0x60000000 +#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 +#define MX3x_ROMP_SIZE SZ_1M -#define AVIC_BASE_ADDR 0x68000000 -#define AVIC_BASE_ADDR_VIRT 0xFC400000 -#define AVIC_SIZE SZ_1M +#define MX3x_AVIC_BASE_ADDR 0x68000000 +#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 +#define MX3x_AVIC_SIZE SZ_1M /* * Memory regions and CS */ -#define IPU_MEM_BASE_ADDR 0x70000000 -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 - -#define CS0_BASE_ADDR 0xA0000000 -#define CS1_BASE_ADDR 0xA8000000 -#define CS2_BASE_ADDR 0xB0000000 -#define CS3_BASE_ADDR 0xB2000000 +#define MX3x_IPU_MEM_BASE_ADDR 0x70000000 +#define MX3x_CSD0_BASE_ADDR 0x80000000 +#define MX3x_CSD1_BASE_ADDR 0x90000000 -#define CS4_BASE_ADDR 0xB4000000 -#define CS4_BASE_ADDR_VIRT 0xF4000000 -#define CS4_SIZE SZ_32M +#define MX3x_CS0_BASE_ADDR 0xa0000000 +#define MX3x_CS1_BASE_ADDR 0xa8000000 +#define MX3x_CS2_BASE_ADDR 0xb0000000 +#define MX3x_CS3_BASE_ADDR 0xb2000000 -#define CS5_BASE_ADDR 0xB6000000 -#define CS5_BASE_ADDR_VIRT 0xF6000000 -#define CS5_SIZE SZ_32M +#define MX3x_CS4_BASE_ADDR 0xb4000000 +#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX3x_CS4_SIZE SZ_32M +#define MX3x_CS5_BASE_ADDR 0xb6000000 +#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX3x_CS5_SIZE SZ_32M /* * NAND, SDRAM, WEIM, M3IF, EMI controllers */ -#define X_MEMC_BASE_ADDR 0xB8000000 -#define X_MEMC_BASE_ADDR_VIRT 0xFC320000 -#define X_MEMC_SIZE SZ_64K +#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 +#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 +#define MX3x_X_MEMC_SIZE SZ_64K +#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) +#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) +#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) +#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) +#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR -#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) -#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) -#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) -#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) -#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR - -#define PCMCIA_MEM_BASE_ADDR 0xBC000000 +#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 /*! * This macro defines the physical to virtual address mapping for all the @@ -204,62 +199,62 @@ /* * Interrupt numbers */ -#define MXC_INT_I2C3 3 -#define MXC_INT_I2C2 4 -#define MXC_INT_RTIC 6 -#define MXC_INT_I2C 10 -#define MXC_INT_CSPI2 13 -#define MXC_INT_CSPI1 14 -#define MXC_INT_ATA 15 -#define MXC_INT_UART3 18 -#define MXC_INT_IIM 19 -#define MXC_INT_RNGA 22 -#define MXC_INT_EVTMON 23 -#define MXC_INT_KPP 24 -#define MXC_INT_RTC 25 -#define MXC_INT_PWM 26 -#define MXC_INT_EPIT2 27 -#define MXC_INT_EPIT1 28 -#define MXC_INT_GPT 29 -#define MXC_INT_POWER_FAIL 30 -#define MXC_INT_UART2 32 -#define MXC_INT_NANDFC 33 -#define MXC_INT_SDMA 34 -#define MXC_INT_MSHC1 39 -#define MXC_INT_IPU_ERR 41 -#define MXC_INT_IPU_SYN 42 -#define MXC_INT_UART1 45 -#define MXC_INT_ECT 48 -#define MXC_INT_SCC_SCM 49 -#define MXC_INT_SCC_SMN 50 -#define MXC_INT_GPIO2 51 -#define MXC_INT_GPIO1 52 -#define MXC_INT_WDOG 55 -#define MXC_INT_GPIO3 56 -#define MXC_INT_EXT_POWER 58 -#define MXC_INT_EXT_TEMPER 59 -#define MXC_INT_EXT_SENSOR60 60 -#define MXC_INT_EXT_SENSOR61 61 -#define MXC_INT_EXT_WDOG 62 -#define MXC_INT_EXT_TV 63 - -#define PROD_SIGNATURE 0x1 /* For MX31 */ +#define MX3x_INT_I2C3 3 +#define MX3x_INT_I2C2 4 +#define MX3x_INT_RTIC 6 +#define MX3x_INT_I2C 10 +#define MX3x_INT_CSPI2 13 +#define MX3x_INT_CSPI1 14 +#define MX3x_INT_ATA 15 +#define MX3x_INT_UART3 18 +#define MX3x_INT_IIM 19 +#define MX3x_INT_RNGA 22 +#define MX3x_INT_EVTMON 23 +#define MX3x_INT_KPP 24 +#define MX3x_INT_RTC 25 +#define MX3x_INT_PWM 26 +#define MX3x_INT_EPIT2 27 +#define MX3x_INT_EPIT1 28 +#define MX3x_INT_GPT 29 +#define MX3x_INT_POWER_FAIL 30 +#define MX3x_INT_UART2 32 +#define MX3x_INT_NANDFC 33 +#define MX3x_INT_SDMA 34 +#define MX3x_INT_MSHC1 39 +#define MX3x_INT_IPU_ERR 41 +#define MX3x_INT_IPU_SYN 42 +#define MX3x_INT_UART1 45 +#define MX3x_INT_ECT 48 +#define MX3x_INT_SCC_SCM 49 +#define MX3x_INT_SCC_SMN 50 +#define MX3x_INT_GPIO2 51 +#define MX3x_INT_GPIO1 52 +#define MX3x_INT_WDOG 55 +#define MX3x_INT_GPIO3 56 +#define MX3x_INT_EXT_POWER 58 +#define MX3x_INT_EXT_TEMPER 59 +#define MX3x_INT_EXT_SENSOR60 60 +#define MX3x_INT_EXT_SENSOR61 61 +#define MX3x_INT_EXT_WDOG 62 +#define MX3x_INT_EXT_TV 63 + +#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ /* silicon revisions specific to i.MX31 */ -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_1_2 0x12 -#define CHIP_REV_1_3 0x13 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_1 0x21 -#define CHIP_REV_2_2 0x22 -#define CHIP_REV_2_3 0x23 -#define CHIP_REV_3_0 0x30 -#define CHIP_REV_3_1 0x31 -#define CHIP_REV_3_2 0x32 - -#define SYSTEM_REV_MIN CHIP_REV_1_0 -#define SYSTEM_REV_NUM 3 +#define MX3x_CHIP_REV_1_0 0x10 +#define MX3x_CHIP_REV_1_1 0x11 +#define MX3x_CHIP_REV_1_2 0x12 +#define MX3x_CHIP_REV_1_3 0x13 +#define MX3x_CHIP_REV_2_0 0x20 +#define MX3x_CHIP_REV_2_1 0x21 +#define MX3x_CHIP_REV_2_2 0x22 +#define MX3x_CHIP_REV_2_3 0x23 +#define MX3x_CHIP_REV_3_0 0x30 +#define MX3x_CHIP_REV_3_1 0x31 +#define MX3x_CHIP_REV_3_2 0x32 + +#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 +#define MX3x_SYSTEM_REV_NUM 3 /* Mandatory defines used globally */ @@ -273,4 +268,137 @@ static inline int mx31_revision(void) } #endif +/* these should go away */ +#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR +#define L2CC_SIZE MX3x_L2CC_SIZE +#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR +#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT +#define AIPS1_SIZE MX3x_AIPS1_SIZE +#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR +#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR +#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR +#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR +#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR +#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR +#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR +#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR +#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR +#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR +#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR +#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR +#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR +#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR +#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR +#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR +#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR +#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR +#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT +#define SPBA0_SIZE MX3x_SPBA0_SIZE +#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR +#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR +#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR +#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR +#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR +#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR +#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR +#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT +#define AIPS2_SIZE MX3x_AIPS2_SIZE +#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR +#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR +#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR +#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR +#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR +#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR +#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR +#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR +#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR +#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR +#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR +#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR +#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR +#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR +#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR +#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR +#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR +#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT +#define ROMP_SIZE MX3x_ROMP_SIZE +#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR +#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT +#define AVIC_SIZE MX3x_AVIC_SIZE +#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR +#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR +#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR +#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR +#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR +#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR +#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR +#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR +#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT +#define CS4_SIZE MX3x_CS4_SIZE +#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR +#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT +#define CS5_SIZE MX3x_CS5_SIZE +#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR +#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT +#define X_MEMC_SIZE MX3x_X_MEMC_SIZE +#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR +#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR +#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR +#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR +#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR +#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR +#define MXC_INT_I2C3 MX3x_INT_I2C3 +#define MXC_INT_I2C2 MX3x_INT_I2C2 +#define MXC_INT_RTIC MX3x_INT_RTIC +#define MXC_INT_I2C MX3x_INT_I2C +#define MXC_INT_CSPI2 MX3x_INT_CSPI2 +#define MXC_INT_CSPI1 MX3x_INT_CSPI1 +#define MXC_INT_ATA MX3x_INT_ATA +#define MXC_INT_UART3 MX3x_INT_UART3 +#define MXC_INT_IIM MX3x_INT_IIM +#define MXC_INT_RNGA MX3x_INT_RNGA +#define MXC_INT_EVTMON MX3x_INT_EVTMON +#define MXC_INT_KPP MX3x_INT_KPP +#define MXC_INT_RTC MX3x_INT_RTC +#define MXC_INT_PWM MX3x_INT_PWM +#define MXC_INT_EPIT2 MX3x_INT_EPIT2 +#define MXC_INT_EPIT1 MX3x_INT_EPIT1 +#define MXC_INT_GPT MX3x_INT_GPT +#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL +#define MXC_INT_UART2 MX3x_INT_UART2 +#define MXC_INT_NANDFC MX3x_INT_NANDFC +#define MXC_INT_SDMA MX3x_INT_SDMA +#define MXC_INT_MSHC1 MX3x_INT_MSHC1 +#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR +#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN +#define MXC_INT_UART1 MX3x_INT_UART1 +#define MXC_INT_ECT MX3x_INT_ECT +#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM +#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN +#define MXC_INT_GPIO2 MX3x_INT_GPIO2 +#define MXC_INT_GPIO1 MX3x_INT_GPIO1 +#define MXC_INT_WDOG MX3x_INT_WDOG +#define MXC_INT_GPIO3 MX3x_INT_GPIO3 +#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER +#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER +#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 +#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 +#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG +#define MXC_INT_EXT_TV MX3x_INT_EXT_TV +#define PROD_SIGNATURE MX3x_PROD_SIGNATURE +#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 +#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 +#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 +#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 +#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 +#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 +#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 +#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 +#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 +#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 +#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 +#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN +#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM + #endif /* __ASM_ARCH_MXC_MX31_H__ */ -- cgit v1.2.3-70-g09d2 From 4f683a046cb45f74610fb790e6affa7604636a9f Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 12 Nov 2009 21:43:39 +0100 Subject: imx: add namespace prefixes for symbols in mx31.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx31.h | 94 +++++++++++++++++++++++------------ 1 file changed, 62 insertions(+), 32 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 14ac0dcc82f..a4d6901755c 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -1,45 +1,75 @@ /* * IRAM */ -#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ +#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ #define MX31_IRAM_SIZE SZ_16K -#define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) -#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) -#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) -#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000) +#define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000) +#define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000) +#define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000) -#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) -#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) -#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) +#define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000) +#define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000) +#define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000) +#define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000) -#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) -#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) -#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) -#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) -#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000) +#define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000) +#define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000) +#define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000) +#define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000) -#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) +#define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000) -#define MXC_INT_MPEG4_ENCODER 5 -#define MXC_INT_FIRI 7 +#define MX31_INT_MPEG4_ENCODER 5 +#define MX31_INT_FIRI 7 #define MX31_INT_MMC_SDHC2 8 -#define MXC_INT_MMC_SDHC1 9 +#define MX31_INT_MMC_SDHC1 9 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 -#define MXC_INT_MBX 16 -#define MXC_INT_CSPI3 17 -#define MXC_INT_SIM2 20 -#define MXC_INT_SIM1 21 -#define MXC_INT_CCM_DVFS 31 -#define MXC_INT_USB1 35 -#define MXC_INT_USB2 36 -#define MXC_INT_USB3 37 -#define MXC_INT_USB4 38 -#define MXC_INT_MSHC2 40 -#define MXC_INT_UART4 46 -#define MXC_INT_UART5 47 -#define MXC_INT_CCM 53 -#define MXC_INT_PCMCIA 54 +#define MX31_INT_MBX 16 +#define MX31_INT_CSPI3 17 +#define MX31_INT_SIM2 20 +#define MX31_INT_SIM1 21 +#define MX31_INT_CCM_DVFS 31 +#define MX31_INT_USB1 35 +#define MX31_INT_USB2 36 +#define MX31_INT_USB3 37 +#define MX31_INT_USB4 38 +#define MX31_INT_MSHC2 40 +#define MX31_INT_UART4 46 +#define MX31_INT_UART5 47 +#define MX31_INT_CCM 53 +#define MX31_INT_PCMCIA 54 +/* these should go away */ +#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR +#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR +#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR +#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR +#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR +#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR +#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR +#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR +#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR +#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR +#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR +#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR +#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER +#define MXC_INT_FIRI MX31_INT_FIRI +#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1 +#define MXC_INT_MBX MX31_INT_MBX +#define MXC_INT_CSPI3 MX31_INT_CSPI3 +#define MXC_INT_SIM2 MX31_INT_SIM2 +#define MXC_INT_SIM1 MX31_INT_SIM1 +#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS +#define MXC_INT_USB1 MX31_INT_USB1 +#define MXC_INT_USB2 MX31_INT_USB2 +#define MXC_INT_USB3 MX31_INT_USB3 +#define MXC_INT_USB4 MX31_INT_USB4 +#define MXC_INT_MSHC2 MX31_INT_MSHC2 +#define MXC_INT_UART4 MX31_INT_UART4 +#define MXC_INT_UART5 MX31_INT_UART5 +#define MXC_INT_CCM MX31_INT_CCM +#define MXC_INT_PCMCIA MX31_INT_PCMCIA -- cgit v1.2.3-70-g09d2 From ae55326a00a6e3cf35e0469b5353aa171aee5407 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 12 Nov 2009 21:47:57 +0100 Subject: imx: add namespace prefixes for symbols in mx35.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The old names are still defined using the new names. Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx35.h | 49 +++++++++++++++++++++++------------ 1 file changed, 32 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index ab4cfec6c8a..42b2a99732f 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -2,29 +2,44 @@ * IRAM */ #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define MX35_IRAM_SIZE SZ_128K +#define MX35_IRAM_SIZE SZ_128K -#define MXC_FEC_BASE_ADDR 0x50038000 -#define MX35_OTG_BASE_ADDR 0x53ff4000 -#define MX35_NFC_BASE_ADDR 0xBB000000 +#define MX35_FEC_BASE_ADDR 0x50038000 +#define MX35_OTG_BASE_ADDR 0x53ff4000 +#define MX35_NFC_BASE_ADDR 0xbb000000 /* * Interrupt numbers */ -#define MXC_INT_OWIRE 2 +#define MX35_INT_OWIRE 2 #define MX35_INT_MMC_SDHC1 7 -#define MXC_INT_MMC_SDHC2 8 -#define MXC_INT_MMC_SDHC3 9 +#define MX35_INT_MMC_SDHC2 8 +#define MX35_INT_MMC_SDHC3 9 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 -#define MXC_INT_GPU2D 16 -#define MXC_INT_ASRC 17 -#define MXC_INT_USBHS 35 -#define MXC_INT_USBOTG 37 -#define MXC_INT_ESAI 40 -#define MXC_INT_CAN1 43 -#define MXC_INT_CAN2 44 -#define MXC_INT_MLB 46 -#define MXC_INT_SPDIF 47 -#define MXC_INT_FEC 57 +#define MX35_INT_GPU2D 16 +#define MX35_INT_ASRC 17 +#define MX35_INT_USBHS 35 +#define MX35_INT_USBOTG 37 +#define MX35_INT_ESAI 40 +#define MX35_INT_CAN1 43 +#define MX35_INT_CAN2 44 +#define MX35_INT_MLB 46 +#define MX35_INT_SPDIF 47 +#define MX35_INT_FEC 57 +/* these should go away */ +#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR +#define MXC_INT_OWIRE MX35_INT_OWIRE +#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2 +#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3 +#define MXC_INT_GPU2D MX35_INT_GPU2D +#define MXC_INT_ASRC MX35_INT_ASRC +#define MXC_INT_USBHS MX35_INT_USBHS +#define MXC_INT_USBOTG MX35_INT_USBOTG +#define MXC_INT_ESAI MX35_INT_ESAI +#define MXC_INT_CAN1 MX35_INT_CAN1 +#define MXC_INT_CAN2 MX35_INT_CAN2 +#define MXC_INT_MLB MX35_INT_MLB +#define MXC_INT_SPDIF MX35_INT_SPDIF +#define MXC_INT_FEC MX35_INT_FEC -- cgit v1.2.3-70-g09d2 From c8e5db0809e51b496f4a6ea11b411352011bda8c Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 12 Nov 2009 21:51:55 +0100 Subject: imx: reformat mx25.h to match the other platform includes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx25.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index ec64bd9a8ab..91e73814480 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -1,14 +1,14 @@ #ifndef __MACH_MX25_H__ #define __MACH_MX25_H__ -#define MX25_AIPS1_BASE_ADDR 0x43F00000 -#define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000 +#define MX25_AIPS1_BASE_ADDR 0x43f00000 +#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 #define MX25_AIPS1_SIZE SZ_1M -#define MX25_AIPS2_BASE_ADDR 0x53F00000 -#define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000 +#define MX25_AIPS2_BASE_ADDR 0x53f00000 +#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 #define MX25_AIPS2_SIZE SZ_1M #define MX25_AVIC_BASE_ADDR 0x68000000 -#define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000 +#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 #define MX25_AVIC_SIZE SZ_1M #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) -- cgit v1.2.3-70-g09d2 From 4c12b3c2e399a8838875e46cbb458ce6488be239 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Nov 2009 21:23:04 +0100 Subject: imx: copy constants from mx2x.h to mx21.h using the appropriate namespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx21.h | 114 +++++++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 986f08bd9c0..bb297d8765a 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -25,6 +25,49 @@ #ifndef __ASM_ARCH_MXC_MX21_H__ #define __ASM_ARCH_MXC_MX21_H__ +#define MX21_AIPI_BASE_ADDR 0x10000000 +#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 +#define MX21_AIPI_SIZE SZ_1M +#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) +#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) +#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) +#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) +#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) +#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) +#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) +#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) +#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) +#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) +#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) +#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) +#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) +#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) +#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) +#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) +#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) +#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) +#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) +#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) +#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) +#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) +#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) +#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) +#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) +#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) +#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) +#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) +#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) +#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) +#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) +#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) + +#define MX21_AVIC_BASE_ADDR 0x10040000 + +#define MX21_SAHB1_BASE_ADDR 0x80000000 +#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 +#define MX21_SAHB1_SIZE SZ_1M +#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) + /* Memory regions and CS */ #define MX21_SDRAM_BASE_ADDR 0xc0000000 #define MX21_CSD1_BASE_ADDR 0xc4000000 @@ -50,22 +93,91 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ /* fixed interrupt numbers */ +#define MX21_INT_CSPI3 6 +#define MX21_INT_GPIO 8 #define MX21_INT_FIRI 9 +#define MX21_INT_SDHC2 10 +#define MX21_INT_SDHC1 11 +#define MX21_INT_I2C 12 +#define MX21_INT_SSI2 13 +#define MX21_INT_SSI1 14 +#define MX21_INT_CSPI2 15 +#define MX21_INT_CSPI1 16 +#define MX21_INT_UART4 17 +#define MX21_INT_UART3 18 +#define MX21_INT_UART2 19 +#define MX21_INT_UART1 20 +#define MX21_INT_KPP 21 +#define MX21_INT_RTC 22 +#define MX21_INT_PWM 23 +#define MX21_INT_GPT3 24 +#define MX21_INT_GPT2 25 +#define MX21_INT_GPT1 26 +#define MX21_INT_WDOG 27 +#define MX21_INT_PCMCIA 28 +#define MX21_INT_NANDFC 29 #define MX21_INT_BMI 30 +#define MX21_INT_CSI 31 +#define MX21_INT_DMACH0 32 +#define MX21_INT_DMACH1 33 +#define MX21_INT_DMACH2 34 +#define MX21_INT_DMACH3 35 +#define MX21_INT_DMACH4 36 +#define MX21_INT_DMACH5 37 +#define MX21_INT_DMACH6 38 +#define MX21_INT_DMACH7 39 +#define MX21_INT_DMACH8 40 +#define MX21_INT_DMACH9 41 +#define MX21_INT_DMACH10 42 +#define MX21_INT_DMACH11 43 +#define MX21_INT_DMACH12 44 +#define MX21_INT_DMACH13 45 +#define MX21_INT_DMACH14 46 +#define MX21_INT_DMACH15 47 #define MX21_INT_EMMAENC 49 #define MX21_INT_EMMADEC 50 +#define MX21_INT_EMMAPRP 51 +#define MX21_INT_EMMAPP 52 #define MX21_INT_USBWKUP 53 #define MX21_INT_USBDMA 54 #define MX21_INT_USBHOST 55 #define MX21_INT_USBFUNC 56 #define MX21_INT_USBMNP 57 #define MX21_INT_USBCTRL 58 -#define MX21_INT_USBCTRL 58 +#define MX21_INT_SLCDC 60 +#define MX21_INT_LCDC 61 /* fixed DMA request numbers */ +#define MX21_DMA_REQ_CSPI3_RX 1 +#define MX21_DMA_REQ_CSPI3_TX 2 +#define MX21_DMA_REQ_EXT 3 #define MX21_DMA_REQ_FIRI_RX 4 +#define MX21_DMA_REQ_SDHC2 6 +#define MX21_DMA_REQ_SDHC1 7 +#define MX21_DMA_REQ_SSI2_RX0 8 +#define MX21_DMA_REQ_SSI2_TX0 9 +#define MX21_DMA_REQ_SSI2_RX1 10 +#define MX21_DMA_REQ_SSI2_TX1 11 +#define MX21_DMA_REQ_SSI1_RX0 12 +#define MX21_DMA_REQ_SSI1_TX0 13 +#define MX21_DMA_REQ_SSI1_RX1 14 +#define MX21_DMA_REQ_SSI1_TX1 15 +#define MX21_DMA_REQ_CSPI2_RX 16 +#define MX21_DMA_REQ_CSPI2_TX 17 +#define MX21_DMA_REQ_CSPI1_RX 18 +#define MX21_DMA_REQ_CSPI1_TX 19 +#define MX21_DMA_REQ_UART4_RX 20 +#define MX21_DMA_REQ_UART4_TX 21 +#define MX21_DMA_REQ_UART3_RX 22 +#define MX21_DMA_REQ_UART3_TX 23 +#define MX21_DMA_REQ_UART2_RX 24 +#define MX21_DMA_REQ_UART2_TX 25 +#define MX21_DMA_REQ_UART1_RX 26 +#define MX21_DMA_REQ_UART1_TX 27 #define MX21_DMA_REQ_BMI_TX 28 #define MX21_DMA_REQ_BMI_RX 29 +#define MX21_DMA_REQ_CSI_STAT 30 +#define MX21_DMA_REQ_CSI_RX 31 /* these should go away */ #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR -- cgit v1.2.3-70-g09d2 From 2ae959f420ac656d2c715e074f6494f1230af2ff Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Nov 2009 21:31:31 +0100 Subject: imx: copy constants from mx2x.h to mx27.h using the appropriate namespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx27.h | 147 +++++++++++++++++++++++++++++----- 1 file changed, 129 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index b619aa4f27b..e2ae19f5171 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -24,28 +24,69 @@ #ifndef __ASM_ARCH_MXC_MX27_H__ #define __ASM_ARCH_MXC_MX27_H__ -#define MX27_MSHC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1a000) -#define MX27_UART5_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1b000) -#define MX27_UART6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1c000) -#define MX27_I2C2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1d000) -#define MX27_SDHC3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1e000) -#define MX27_GPT6_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x1f000) -#define MX27_VPU_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x23000) -#define MX27_OTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR -#define MX27_SAHARA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x25000) -#define MX27_IIM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x28000) -#define MX27_RTIC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2a000) -#define MX27_FEC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2b000) -#define MX27_SCC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x2c000) -#define MX27_ETB_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3b000) -#define MX27_ETB_RAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3c000) +#define MX27_AIPI_BASE_ADDR 0x10000000 +#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 +#define MX27_AIPI_SIZE SZ_1M +#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) +#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) +#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) +#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) +#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) +#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) +#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) +#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) +#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) +#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) +#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) +#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) +#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) +#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) +#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) +#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) +#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) +#define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) +#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) +#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) +#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) +#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) +#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) +#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) +#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) +#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) +#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) +#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) +#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) +#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) +#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) +#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) +#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) +#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) +#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) +#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR +#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) +#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) +#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) +#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) +#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) +#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) +#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) +#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) +#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) +#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) +#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) +#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) +#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) + +#define MX27_AVIC_BASE_ADDR 0x10040000 /* ROM patch */ #define MX27_ROMP_BASE_ADDR 0x10041000 -#define MX27_ATA_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x1000) +#define MX27_SAHB1_BASE_ADDR 0x80000000 +#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 +#define MX27_SAHB1_SIZE SZ_1M +#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) +#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) /* Memory regions and CS */ #define MX27_SDRAM_BASE_ADDR 0xa0000000 @@ -79,12 +120,53 @@ #define MX27_INT_GPT5 3 #define MX27_INT_GPT4 4 #define MX27_INT_RTIC 5 +#define MX27_INT_CSPI3 6 #define MX27_INT_SDHC 7 +#define MX27_INT_GPIO 8 #define MX27_INT_SDHC3 9 +#define MX27_INT_SDHC2 10 +#define MX27_INT_SDHC1 11 +#define MX27_INT_I2C 12 +#define MX27_INT_SSI2 13 +#define MX27_INT_SSI1 14 +#define MX27_INT_CSPI2 15 +#define MX27_INT_CSPI1 16 +#define MX27_INT_UART4 17 +#define MX27_INT_UART3 18 +#define MX27_INT_UART2 19 +#define MX27_INT_UART1 20 +#define MX27_INT_KPP 21 +#define MX27_INT_RTC 22 +#define MX27_INT_PWM 23 +#define MX27_INT_GPT3 24 +#define MX27_INT_GPT2 25 +#define MX27_INT_GPT1 26 +#define MX27_INT_WDOG 27 +#define MX27_INT_PCMCIA 28 +#define MX27_INT_NANDFC 29 #define MX27_INT_ATA 30 +#define MX27_INT_CSI 31 +#define MX27_INT_DMACH0 32 +#define MX27_INT_DMACH1 33 +#define MX27_INT_DMACH2 34 +#define MX27_INT_DMACH3 35 +#define MX27_INT_DMACH4 36 +#define MX27_INT_DMACH5 37 +#define MX27_INT_DMACH6 38 +#define MX27_INT_DMACH7 39 +#define MX27_INT_DMACH8 40 +#define MX27_INT_DMACH9 41 +#define MX27_INT_DMACH10 42 +#define MX27_INT_DMACH11 43 +#define MX27_INT_DMACH12 44 +#define MX27_INT_DMACH13 45 +#define MX27_INT_DMACH14 46 +#define MX27_INT_DMACH15 47 #define MX27_INT_UART6 48 #define MX27_INT_UART5 49 #define MX27_INT_FEC 50 +#define MX27_INT_EMMAPRP 51 +#define MX27_INT_EMMAPP 52 #define MX27_INT_VPU 53 #define MX27_INT_USB1 54 #define MX27_INT_USB2 55 @@ -92,13 +174,42 @@ #define MX27_INT_SCC_SMN 57 #define MX27_INT_SCC_SCM 58 #define MX27_INT_SAHARA 59 +#define MX27_INT_SLCDC 60 +#define MX27_INT_LCDC 61 #define MX27_INT_IIM 62 #define MX27_INT_CCM 63 /* fixed DMA request numbers */ +#define MX27_DMA_REQ_CSPI3_RX 1 +#define MX27_DMA_REQ_CSPI3_TX 2 +#define MX27_DMA_REQ_EXT 3 #define MX27_DMA_REQ_MSHC 4 +#define MX27_DMA_REQ_SDHC2 6 +#define MX27_DMA_REQ_SDHC1 7 +#define MX27_DMA_REQ_SSI2_RX0 8 +#define MX27_DMA_REQ_SSI2_TX0 9 +#define MX27_DMA_REQ_SSI2_RX1 10 +#define MX27_DMA_REQ_SSI2_TX1 11 +#define MX27_DMA_REQ_SSI1_RX0 12 +#define MX27_DMA_REQ_SSI1_TX0 13 +#define MX27_DMA_REQ_SSI1_RX1 14 +#define MX27_DMA_REQ_SSI1_TX1 15 +#define MX27_DMA_REQ_CSPI2_RX 16 +#define MX27_DMA_REQ_CSPI2_TX 17 +#define MX27_DMA_REQ_CSPI1_RX 18 +#define MX27_DMA_REQ_CSPI1_TX 19 +#define MX27_DMA_REQ_UART4_RX 20 +#define MX27_DMA_REQ_UART4_TX 21 +#define MX27_DMA_REQ_UART3_RX 22 +#define MX27_DMA_REQ_UART3_TX 23 +#define MX27_DMA_REQ_UART2_RX 24 +#define MX27_DMA_REQ_UART2_TX 25 +#define MX27_DMA_REQ_UART1_RX 26 +#define MX27_DMA_REQ_UART1_TX 27 #define MX27_DMA_REQ_ATA_TX 28 #define MX27_DMA_REQ_ATA_RCV 29 +#define MX27_DMA_REQ_CSI_STAT 30 +#define MX27_DMA_REQ_CSI_RX 31 #define MX27_DMA_REQ_UART5_TX 32 #define MX27_DMA_REQ_UART5_RX 33 #define MX27_DMA_REQ_UART6_TX 34 -- cgit v1.2.3-70-g09d2 From ebca1a5543c70931eeab91751fe53f67b3d0e9c6 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Nov 2009 21:24:48 +0100 Subject: imx: copy constants from mx3x.h to mx31.h using the appropriate namespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx31.h | 171 +++++++++++++++++++++++++++++++--- 1 file changed, 157 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index a4d6901755c..b8b47d139eb 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -4,44 +4,187 @@ #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ #define MX31_IRAM_SIZE SZ_16K -#define MX31_OTG_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x88000) -#define MX31_ATA_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x8c000) -#define MX31_UART4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb0000) -#define MX31_UART5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb4000) +#define MX31_L2CC_BASE_ADDR 0x30000000 +#define MX31_L2CC_SIZE SZ_1M -#define MX31_MMC_SDHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x04000) -#define MX31_MMC_SDHC2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x08000) -#define MX31_SIM1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x18000) -#define MX31_IIM_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x1c000) +#define MX31_AIPS1_BASE_ADDR 0x43f00000 +#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 +#define MX31_AIPS1_SIZE SZ_1M +#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) +#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) +#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) +#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) +#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) +#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) +#define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) +#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) +#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) +#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) +#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) +#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) +#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) +#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) +#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) +#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) +#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) +#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) +#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) +#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) +#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) -#define MX31_CSPI3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x84000) -#define MX31_FIRI_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x8c000) -#define MX31_SCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xae000) -#define MX31_SMN_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xaf000) -#define MX31_MPEG4_ENC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc8000) +#define MX31_SPBA0_BASE_ADDR 0x50000000 +#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 +#define MX31_SPBA0_SIZE SZ_1M +#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) +#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) +#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) +#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) +#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) +#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) +#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) +#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) +#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) +#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) -#define MX31_NFC_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x0000) +#define MX31_AIPS2_BASE_ADDR 0x53f00000 +#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 +#define MX31_AIPS2_SIZE SZ_1M +#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) +#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) +#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) +#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) +#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) +#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) +#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) +#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) +#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) +#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) +#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) +#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) +#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) +#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) +#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) +#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) +#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) +#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) +#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) +#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) +#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) +#define MX31_ROMP_BASE_ADDR 0x60000000 +#define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000 +#define MX31_ROMP_SIZE SZ_1M + +#define MX31_AVIC_BASE_ADDR 0x68000000 +#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 +#define MX31_AVIC_SIZE SZ_1M + +#define MX31_IPU_MEM_BASE_ADDR 0x70000000 +#define MX31_CSD0_BASE_ADDR 0x80000000 +#define MX31_CSD1_BASE_ADDR 0x90000000 + +#define MX31_CS0_BASE_ADDR 0xa0000000 +#define MX31_CS1_BASE_ADDR 0xa8000000 +#define MX31_CS2_BASE_ADDR 0xb0000000 +#define MX31_CS3_BASE_ADDR 0xb2000000 + +#define MX31_CS4_BASE_ADDR 0xb4000000 +#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX31_CS4_SIZE SZ_32M + +#define MX31_CS5_BASE_ADDR 0xb6000000 +#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX31_CS5_SIZE SZ_32M + +#define MX31_X_MEMC_BASE_ADDR 0xb8000000 +#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 +#define MX31_X_MEMC_SIZE SZ_64K +#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) +#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) +#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) +#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) +#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) +#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR + +#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 + +#define MX31_INT_I2C3 3 +#define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 +#define MX31_INT_RTIC 6 #define MX31_INT_FIRI 7 #define MX31_INT_MMC_SDHC2 8 #define MX31_INT_MMC_SDHC1 9 +#define MX31_INT_I2C 10 #define MX31_INT_SSI2 11 #define MX31_INT_SSI1 12 +#define MX31_INT_CSPI2 13 +#define MX31_INT_CSPI1 14 +#define MX31_INT_ATA 15 #define MX31_INT_MBX 16 #define MX31_INT_CSPI3 17 +#define MX31_INT_UART3 18 +#define MX31_INT_IIM 19 #define MX31_INT_SIM2 20 #define MX31_INT_SIM1 21 +#define MX31_INT_RNGA 22 +#define MX31_INT_EVTMON 23 +#define MX31_INT_KPP 24 +#define MX31_INT_RTC 25 +#define MX31_INT_PWM 26 +#define MX31_INT_EPIT2 27 +#define MX31_INT_EPIT1 28 +#define MX31_INT_GPT 29 +#define MX31_INT_POWER_FAIL 30 #define MX31_INT_CCM_DVFS 31 +#define MX31_INT_UART2 32 +#define MX31_INT_NANDFC 33 +#define MX31_INT_SDMA 34 #define MX31_INT_USB1 35 #define MX31_INT_USB2 36 #define MX31_INT_USB3 37 #define MX31_INT_USB4 38 +#define MX31_INT_MSHC1 39 #define MX31_INT_MSHC2 40 +#define MX31_INT_IPU_ERR 41 +#define MX31_INT_IPU_SYN 42 +#define MX31_INT_UART1 45 #define MX31_INT_UART4 46 #define MX31_INT_UART5 47 +#define MX31_INT_ECT 48 +#define MX31_INT_SCC_SCM 49 +#define MX31_INT_SCC_SMN 50 +#define MX31_INT_GPIO2 51 +#define MX31_INT_GPIO1 52 #define MX31_INT_CCM 53 #define MX31_INT_PCMCIA 54 +#define MX31_INT_WDOG 55 +#define MX31_INT_GPIO3 56 +#define MX31_INT_EXT_POWER 58 +#define MX31_INT_EXT_TEMPER 59 +#define MX31_INT_EXT_SENSOR60 60 +#define MX31_INT_EXT_SENSOR61 61 +#define MX31_INT_EXT_WDOG 62 +#define MX31_INT_EXT_TV 63 + +#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ + +/* silicon revisions specific to i.MX31 */ +#define MX31_CHIP_REV_1_0 0x10 +#define MX31_CHIP_REV_1_1 0x11 +#define MX31_CHIP_REV_1_2 0x12 +#define MX31_CHIP_REV_1_3 0x13 +#define MX31_CHIP_REV_2_0 0x20 +#define MX31_CHIP_REV_2_1 0x21 +#define MX31_CHIP_REV_2_2 0x22 +#define MX31_CHIP_REV_2_3 0x23 +#define MX31_CHIP_REV_3_0 0x30 +#define MX31_CHIP_REV_3_1 0x31 +#define MX31_CHIP_REV_3_2 0x32 + +#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 +#define MX31_SYSTEM_REV_NUM 3 /* these should go away */ #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR -- cgit v1.2.3-70-g09d2 From 3f92a8bd5fb13e7e2505c65d1548910eaa843024 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 13 Nov 2009 21:25:01 +0100 Subject: imx: copy constants from mx3x.h to mx35.h using the appropriate namespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König --- arch/arm/plat-mxc/include/mach/mx35.h | 152 ++++++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index 42b2a99732f..af871bce35b 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -4,29 +4,181 @@ #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ #define MX35_IRAM_SIZE SZ_128K +#define MX35_L2CC_BASE_ADDR 0x30000000 +#define MX35_L2CC_SIZE SZ_1M + +#define MX35_AIPS1_BASE_ADDR 0x43f00000 +#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 +#define MX35_AIPS1_SIZE SZ_1M +#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) +#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) +#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) +#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) +#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) +#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) +#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) +#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) +#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) +#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) +#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) +#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) +#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) +#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) +#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) +#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) +#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) +#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) + +#define MX35_SPBA0_BASE_ADDR 0x50000000 +#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 +#define MX35_SPBA0_SIZE SZ_1M +#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) +#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) +#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) +#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) +#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) #define MX35_FEC_BASE_ADDR 0x50038000 +#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) + +#define MX35_AIPS2_BASE_ADDR 0x53f00000 +#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 +#define MX35_AIPS2_SIZE SZ_1M +#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) +#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) +#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) +#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) +#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) +#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) +#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) +#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) +#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) +#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) +#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) +#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) +#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) +#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) +#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) +#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) #define MX35_OTG_BASE_ADDR 0x53ff4000 + +#define MX35_ROMP_BASE_ADDR 0x60000000 +#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 +#define MX35_ROMP_SIZE SZ_1M + +#define MX35_AVIC_BASE_ADDR 0x68000000 +#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 +#define MX35_AVIC_SIZE SZ_1M + +/* + * Memory regions and CS + */ +#define MX35_IPU_MEM_BASE_ADDR 0x70000000 +#define MX35_CSD0_BASE_ADDR 0x80000000 +#define MX35_CSD1_BASE_ADDR 0x90000000 + +#define MX35_CS0_BASE_ADDR 0xa0000000 +#define MX35_CS1_BASE_ADDR 0xa8000000 +#define MX35_CS2_BASE_ADDR 0xb0000000 +#define MX35_CS3_BASE_ADDR 0xb2000000 + +#define MX35_CS4_BASE_ADDR 0xb4000000 +#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 +#define MX35_CS4_SIZE SZ_32M + +#define MX35_CS5_BASE_ADDR 0xb6000000 +#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 +#define MX35_CS5_SIZE SZ_32M + +/* + * NAND, SDRAM, WEIM, M3IF, EMI controllers + */ +#define MX35_X_MEMC_BASE_ADDR 0xb8000000 +#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 +#define MX35_X_MEMC_SIZE SZ_64K +#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) +#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) +#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) +#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) +#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR + #define MX35_NFC_BASE_ADDR 0xbb000000 +#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 /* * Interrupt numbers */ #define MX35_INT_OWIRE 2 +#define MX35_INT_I2C3 3 +#define MX35_INT_I2C2 4 +#define MX35_INT_RTIC 6 #define MX35_INT_MMC_SDHC1 7 #define MX35_INT_MMC_SDHC2 8 #define MX35_INT_MMC_SDHC3 9 +#define MX35_INT_I2C 10 #define MX35_INT_SSI1 11 #define MX35_INT_SSI2 12 +#define MX35_INT_CSPI2 13 +#define MX35_INT_CSPI1 14 +#define MX35_INT_ATA 15 #define MX35_INT_GPU2D 16 #define MX35_INT_ASRC 17 +#define MX35_INT_UART3 18 +#define MX35_INT_IIM 19 +#define MX35_INT_RNGA 22 +#define MX35_INT_EVTMON 23 +#define MX35_INT_KPP 24 +#define MX35_INT_RTC 25 +#define MX35_INT_PWM 26 +#define MX35_INT_EPIT2 27 +#define MX35_INT_EPIT1 28 +#define MX35_INT_GPT 29 +#define MX35_INT_POWER_FAIL 30 +#define MX35_INT_UART2 32 +#define MX35_INT_NANDFC 33 +#define MX35_INT_SDMA 34 #define MX35_INT_USBHS 35 #define MX35_INT_USBOTG 37 +#define MX35_INT_MSHC1 39 #define MX35_INT_ESAI 40 +#define MX35_INT_IPU_ERR 41 +#define MX35_INT_IPU_SYN 42 #define MX35_INT_CAN1 43 #define MX35_INT_CAN2 44 +#define MX35_INT_UART1 45 #define MX35_INT_MLB 46 #define MX35_INT_SPDIF 47 +#define MX35_INT_ECT 48 +#define MX35_INT_SCC_SCM 49 +#define MX35_INT_SCC_SMN 50 +#define MX35_INT_GPIO2 51 +#define MX35_INT_GPIO1 52 +#define MX35_INT_WDOG 55 +#define MX35_INT_GPIO3 56 #define MX35_INT_FEC 57 +#define MX35_INT_EXT_POWER 58 +#define MX35_INT_EXT_TEMPER 59 +#define MX35_INT_EXT_SENSOR60 60 +#define MX35_INT_EXT_SENSOR61 61 +#define MX35_INT_EXT_WDOG 62 +#define MX35_INT_EXT_TV 63 + +#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ + +/* silicon revisions specific to i.MX31 */ +#define MX35_CHIP_REV_1_0 0x10 +#define MX35_CHIP_REV_1_1 0x11 +#define MX35_CHIP_REV_1_2 0x12 +#define MX35_CHIP_REV_1_3 0x13 +#define MX35_CHIP_REV_2_0 0x20 +#define MX35_CHIP_REV_2_1 0x21 +#define MX35_CHIP_REV_2_2 0x22 +#define MX35_CHIP_REV_2_3 0x23 +#define MX35_CHIP_REV_3_0 0x30 +#define MX35_CHIP_REV_3_1 0x31 +#define MX35_CHIP_REV_3_2 0x32 + +#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 +#define MX35_SYSTEM_REV_NUM 3 /* these should go away */ #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR -- cgit v1.2.3-70-g09d2 From b7d91a62cb402a3d24a15dca9d2b0c309c4227b4 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:06 +0100 Subject: ARM: MX3: modularize 'mx31lite' code This commit splits the support code for LogicPD's mx31lite hardware into module and board specific parts. This introduces a new mandatory coreparam called 'mx31lite_baseboard' which specifies the base board support to use. For now, only the LiteKit development board is supported, and developers of own boards are encouraged to use that as reference. The UART support moved to the board code. Some comments were amended along the way. Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Makefile | 2 +- arch/arm/mach-mx3/mx31lite-db.c | 71 +++++++++++++++++++++++++ arch/arm/mach-mx3/mx31lite.c | 36 ++++++------- arch/arm/plat-mxc/include/mach/board-mx31lite.h | 39 +++++++++++--- 4 files changed, 121 insertions(+), 27 deletions(-) create mode 100644 arch/arm/mach-mx3/mx31lite-db.c (limited to 'arch') diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 6b9775471be..ed492d32b66 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o +obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o obj-$(CONFIG_MACH_PCM037) += pcm037.o obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c new file mode 100644 index 00000000000..751d15ec0b0 --- /dev/null +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -0,0 +1,71 @@ +/* + * LogicPD i.MX31 SOM-LV development board support + * + * Copyright (c) 2009 Daniel Mack + * + * based on code for other MX31 boards, + * + * Copyright 2005-2007 Freescale Semiconductor + * Copyright (c) 2009 Alberto Panizzo + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "devices.h" + +/* + * This file contains board-specific initialization routines for the + * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'. + * If you design an own baseboard for the module, use this file as base + * for support code. + */ + +static unsigned int litekit_db_board_pins[] __initdata = { + /* UART1 */ + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1, +}; + +/* UART */ +static struct imxuart_platform_data uart_pdata __initdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +void __init mx31lite_db_init(void) +{ + mxc_iomux_setup_multiple_pins(litekit_db_board_pins, + ARRAY_SIZE(litekit_db_board_pins), + "development board pins"); + mxc_register_device(&mxc_uart_device0, &uart_pdata); +} + diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index a8d57decdfd..dc993a87816 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -42,23 +42,14 @@ #include "devices.h" /* - * This file contains the board-specific initialization routines. + * This file contains the module-specific initialization routines. */ static unsigned int mx31lite_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, /* LAN9117 IRQ pin */ IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), }; -static struct imxuart_platform_data uart_pdata = { - .flags = IMXUART_HAVE_RTSCTS, -}; - static struct mxc_nand_platform_data mx31lite_nand_board_info = { .width = 1, .hw_ecc = 1, @@ -118,17 +109,27 @@ void __init mx31lite_map_io(void) iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); } -/* - * Board specific initialization. - */ +static int mx31lite_baseboard; +core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); + static void __init mxc_board_init(void) { int ret; + switch (mx31lite_baseboard) { + case MX31LITE_NOBOARD: + break; + case MX31LITE_DB: + mx31lite_db_init(); + break; + default: + printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n", + mx31lite_baseboard); + } + mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), "mx31lite"); - mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); /* SMSC9117 IRQ pin */ @@ -150,12 +151,7 @@ struct sys_timer mx31lite_timer = { .init = mx31lite_timer_init, }; -/* - * The following uses standard kernel macros defined in arch.h in order to - * initialize __mach_desc_MX31LITE data structure. - */ - -MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT") +MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 8e64325d690..0184b638c26 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h @@ -1,15 +1,42 @@ /* * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Daniel Mack + * + * Based on code for mobots boards, + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. */ +#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ +#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ + +#ifndef __ASSEMBLY__ + +enum mx31lilly_boards { + MX31LITE_NOBOARD = 0, + MX31LITE_DB = 1, +}; + /* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * This CPU module needs a baseboard to work. After basic initializing + * its own devices, it calls baseboard's init function. */ -#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ +extern void mx31lite_db_init(void); -#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ +#endif +#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ -- cgit v1.2.3-70-g09d2 From 364cd540f036f106d886a9c51ae05e9a9bacf051 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:07 +0100 Subject: ARM: MX3: add MMC/SDHC support to mx31lite-db.c Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite-db.c | 70 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 751d15ec0b0..45abae1da33 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -38,6 +38,7 @@ #include #include #include +#include #include "devices.h" @@ -61,11 +62,80 @@ static struct imxuart_platform_data uart_pdata __initdata = { .flags = IMXUART_HAVE_RTSCTS, }; +/* MMC */ + +static int gpio_det, gpio_wp; + +#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +static int mxc_mmc1_get_ro(struct device *dev) +{ + return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); +} + +static int mxc_mmc1_init(struct device *dev, + irq_handler_t detect_irq, void *data) +{ + int ret; + + gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); + gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); + + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); + + ret = gpio_request(gpio_det, "MMC detect"); + if (ret) + return ret; + + ret = gpio_request(gpio_wp, "MMC w/p"); + if (ret) + goto exit_free_det; + + gpio_direction_input(gpio_det); + gpio_direction_input(gpio_wp); + + ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, + IRQF_DISABLED | IRQF_TRIGGER_FALLING, + "MMC detect", data); + if (ret) + goto exit_free_wp; + + return 0; + +exit_free_wp: + gpio_free(gpio_wp); + +exit_free_det: + gpio_free(gpio_det); + + return ret; +} + +static void mxc_mmc1_exit(struct device *dev, void *data) +{ + gpio_free(gpio_det); + gpio_free(gpio_wp); + free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); +} + +static struct imxmmc_platform_data mmc_pdata = { + .get_ro = mxc_mmc1_get_ro, + .init = mxc_mmc1_init, + .exit = mxc_mmc1_exit, +}; + void __init mx31lite_db_init(void) { mxc_iomux_setup_multiple_pins(litekit_db_board_pins, ARRAY_SIZE(litekit_db_board_pins), "development board pins"); mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxcsdhc_device0, &mmc_pdata); } -- cgit v1.2.3-70-g09d2 From 84677d114a7bcba11981a76ee60498a1b41d9d94 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:08 +0100 Subject: ARM: MX3: add SPI devices for mx31lite Some header files were reordered while I was at it. The only device currently registered is the ATLAS PMIC (MC13783) chip. Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite-db.c | 24 ++++++++++++++++++++ arch/arm/mach-mx3/mx31lite.c | 49 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 71 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 45abae1da33..f60cf0813ce 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ #include #include #include +#include #include "devices.h" @@ -55,6 +57,14 @@ static unsigned int litekit_db_board_pins[] __initdata = { MX31_PIN_RTS1__RTS1, MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, + /* SPI 0 */ + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS0__SS0, + MX31_PIN_CSPI1_SS1__SS1, + MX31_PIN_CSPI1_SS2__SS2, }; /* UART */ @@ -130,6 +140,19 @@ static struct imxmmc_platform_data mmc_pdata = { .exit = mxc_mmc1_exit, }; +/* SPI */ + +static int spi_internal_chipselect[] = { + MXC_SPI_CS(0), + MXC_SPI_CS(1), + MXC_SPI_CS(2), +}; + +static struct spi_imx_master spi0_pdata = { + .chipselect = spi_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), +}; + void __init mx31lite_db_init(void) { mxc_iomux_setup_multiple_pins(litekit_db_board_pins, @@ -137,5 +160,6 @@ void __init mx31lite_db_init(void) "development board pins"); mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); + mxc_register_device(&mxc_spi_device0, &spi0_pdata); } diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index dc993a87816..03762a36d29 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -2,6 +2,7 @@ * Copyright (C) 2000 Deep Blue Solutions Ltd * Copyright (C) 2002 Shane Nay (shane@minirl.com) * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009 Daniel Mack * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,20 +26,25 @@ #include #include #include +#include +#include -#include #include #include #include #include -#include #include #include + +#include +#include #include #include #include #include #include +#include + #include "devices.h" /* @@ -48,6 +54,14 @@ static unsigned int mx31lite_pins[] = { /* LAN9117 IRQ pin */ IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), + /* SPI 1 */ + MX31_PIN_CSPI2_SCLK__SCLK, + MX31_PIN_CSPI2_MOSI__MOSI, + MX31_PIN_CSPI2_MISO__MISO, + MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI2_SS0__SS0, + MX31_PIN_CSPI2_SS1__SS1, + MX31_PIN_CSPI2_SS2__SS2, }; static struct mxc_nand_platform_data mx31lite_nand_board_info = { @@ -83,6 +97,35 @@ static struct platform_device smsc911x_device = { }, }; +/* + * SPI + * + * The MC13783 is the only hard-wired SPI device on the module. + */ + +static int spi_internal_chipselect[] = { + MXC_SPI_CS(0), +}; + +static struct spi_imx_master spi1_pdata = { + .chipselect = spi_internal_chipselect, + .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), +}; + +static struct mc13783_platform_data mc13783_pdata __initdata = { + .flags = MC13783_USE_RTC | + MC13783_USE_REGULATOR, +}; + +static struct spi_board_info mc13783_spi_dev __initdata = { + .modalias = "mc13783", + .max_speed_hz = 1000000, + .bus_num = 1, + .chip_select = 0, + .platform_data = &mc13783_pdata, + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), +}; + /* * This structure defines the MX31 memory map. */ @@ -131,6 +174,8 @@ static void __init mxc_board_init(void) "mx31lite"); mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); + mxc_register_device(&mxc_spi_device1, &spi1_pdata); + spi_register_board_info(&mc13783_spi_dev, 1); /* SMSC9117 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); -- cgit v1.2.3-70-g09d2 From a050c8e9b70b90a3e3b808a12d985a31e19c2f95 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:09 +0100 Subject: ARM: MX3: add USB functions for mx31litekit Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite.c | 60 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index 03762a36d29..4651e2376a7 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include #include #include @@ -44,6 +46,8 @@ #include #include #include +#include +#include #include "devices.h" @@ -126,6 +130,56 @@ static struct spi_board_info mc13783_spi_dev __initdata = { .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), }; +/* + * USB + */ + +#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +static int usbh2_init(struct platform_device *pdev) +{ + int pins[] = { + MX31_PIN_USBH2_DATA0__USBH2_DATA0, + MX31_PIN_USBH2_DATA1__USBH2_DATA1, + MX31_PIN_USBH2_CLK__USBH2_CLK, + MX31_PIN_USBH2_DIR__USBH2_DIR, + MX31_PIN_USBH2_NXT__USBH2_NXT, + MX31_PIN_USBH2_STP__USBH2_STP, + }; + + mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); + + mxc_iomux_set_gpr(MUX_PGP_UH2, true); + + /* chip select */ + mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), + "USBH2_CS"); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); + gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); + + return 0; +} + +static struct mxc_usbh_platform_data usbh2_pdata = { + .init = usbh2_init, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + /* * This structure defines the MX31 memory map. */ @@ -177,6 +231,12 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_spi_device1, &spi1_pdata); spi_register_board_info(&mc13783_spi_dev, 1); + /* USB */ + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); + /* SMSC9117 IRQ pin */ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); if (ret) -- cgit v1.2.3-70-g09d2 From 81057f328618181f87b25571dd9f623c86fe960e Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:10 +0100 Subject: ARM: MX3: add support for GPIO LEDs on litekit db The names are chosen to match the silkscreen. Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite-db.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index f60cf0813ce..694611d6b05 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include #include #include @@ -153,6 +155,36 @@ static struct spi_imx_master spi0_pdata = { .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; +/* GPIO LEDs */ + +static struct gpio_led litekit_leds[] = { + { + .name = "GPIO0", + .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + }, + { + .name = "GPIO1", + .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE), + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + } +}; + +static struct gpio_led_platform_data litekit_led_platform_data = { + .leds = litekit_leds, + .num_leds = ARRAY_SIZE(litekit_leds), +}; + +static struct platform_device litekit_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &litekit_led_platform_data, + }, +}; + void __init mx31lite_db_init(void) { mxc_iomux_setup_multiple_pins(litekit_db_board_pins, @@ -161,5 +193,6 @@ void __init mx31lite_db_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); mxc_register_device(&mxc_spi_device0, &spi0_pdata); + platform_device_register(&litekit_led_device); } -- cgit v1.2.3-70-g09d2 From 6d3e6601ba0ff6ca804d3c103164624618cab4a9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Thu, 19 Nov 2009 12:02:11 +0100 Subject: ARM: MX3: add NOR flash support via physmap mtd driver Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lite.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index 4651e2376a7..def6b673659 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -180,6 +181,32 @@ static struct mxc_usbh_platform_data usbh2_pdata = { .flags = MXC_EHCI_POWER_PINS_ENABLED, }; +/* + * NOR flash + */ + +static struct physmap_flash_data nor_flash_data = { + .width = 2, +}; + +static struct resource nor_flash_resource = { + .start = 0xa0000000, + .end = 0xa1ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device physmap_flash_device = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &nor_flash_data, + }, + .resource = &nor_flash_resource, + .num_resources = 1, +}; + + + /* * This structure defines the MX31 memory map. */ @@ -227,7 +254,10 @@ static void __init mxc_board_init(void) mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), "mx31lite"); + /* NOR and NAND flash */ + platform_device_register(&physmap_flash_device); mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); + mxc_register_device(&mxc_spi_device1, &spi1_pdata); spi_register_board_info(&mc13783_spi_dev, 1); -- cgit v1.2.3-70-g09d2 From 2cc326833f616ee49f73be94d4bf0ab1bc9a72d9 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sat, 21 Nov 2009 18:40:40 +0100 Subject: ARM: MX3: lilly1131: move MC13783 device registration Register the MC13783 device in the module code. Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31lilly-db.c | 19 ------------------- arch/arm/mach-mx3/mx31lilly.c | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index bb1e44f5d30..7aebd74a12e 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c @@ -29,8 +29,6 @@ #include #include #include -#include -#include #include #include @@ -214,22 +212,6 @@ static void __init mx31lilly_init_fb(void) gpio_direction_output(LCD_VCC_EN_GPIO, 1); } -/* SPI */ - -static struct mc13783_platform_data mc13783_pdata __initdata = { - .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, -}; - -static struct spi_board_info lilly_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - }, -}; - void __init mx31lilly_db_init(void) { mxc_iomux_setup_multiple_pins(lilly_db_board_pins, @@ -240,6 +222,5 @@ void __init mx31lilly_db_init(void) mxc_register_device(&mxc_uart_device2, &uart_pdata); mxc_register_device(&mxcsdhc_device0, &mmc_pdata); mx31lilly_init_fb(); - spi_register_board_info(lilly_spi_devs, ARRAY_SIZE(lilly_spi_devs)); } diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c index f593a629d8b..9ce029f554b 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mx31lilly.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include #include #include @@ -111,6 +113,8 @@ static struct platform_device *devices[] __initdata = { &physmap_flash_device, }; +/* SPI */ + static int spi_internal_chipselect[] = { MXC_SPI_CS(0), MXC_SPI_CS(1), @@ -127,6 +131,18 @@ static struct spi_imx_master spi1_pdata = { .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), }; +static struct mc13783_platform_data mc13783_pdata __initdata = { + .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, +}; + +static struct spi_board_info mc13783_dev __initdata = { + .modalias = "mc13783", + .max_speed_hz = 1000000, + .bus_num = 1, + .chip_select = 0, + .platform_data = &mc13783_pdata, +}; + static int mx31lilly_baseboard; core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); @@ -164,6 +180,7 @@ static void __init mx31lilly_board_init(void) mxc_register_device(&mxc_spi_device0, &spi0_pdata); mxc_register_device(&mxc_spi_device1, &spi1_pdata); + spi_register_board_info(&mc13783_dev, 1); platform_add_devices(devices, ARRAY_SIZE(devices)); } -- cgit v1.2.3-70-g09d2 From 52939c03e53b151848da9e83fd839bddfda29e78 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Sat, 21 Nov 2009 20:17:18 +0100 Subject: ARM: MX3: fix CPU revision number detection The macro mx31_revision() used to take the global variable system_rev to determine the CPU revision number. However, this number is expected to be set by the bootloader and is usually zero (at least on my MX31 based boards here). More than that, it is usually taken to identify the board's revision, not the CPU's. Fix that by reading the the CPU's SREV register instead. Right now, mx31_read_cpu_rev() is called from mx31_clocks_init() which is admittedly not a good place for it. However, we need to enable the IIM clock first, and the clock code also has conditional code that depends on mx31_revision() returning the right thing. Signed-off-by: Daniel Mack Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Makefile | 2 +- arch/arm/mach-mx3/clock.c | 2 ++ arch/arm/mach-mx3/cpu.c | 57 +++++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx3x.h | 5 +-- 4 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 arch/arm/mach-mx3/cpu.c (limited to 'arch') diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index ed492d32b66..940035cacae 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -4,7 +4,7 @@ # Object file lists. -obj-y := mm.o devices.o +obj-y := mm.o devices.o cpu.o obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index b2a3bcf8266..bec097d176e 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref) clk_enable(&serial_pll_clk); + mx31_read_cpu_rev(); + if (mx31_revision() >= CHIP_REV_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c new file mode 100644 index 00000000000..db828809c67 --- /dev/null +++ b/arch/arm/mach-mx3/cpu.c @@ -0,0 +1,57 @@ +/* + * MX3 CPU type detection + * + * Copyright (c) 2009 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +unsigned int mx31_cpu_rev; +EXPORT_SYMBOL(mx31_cpu_rev); + +struct mx3_cpu_type { + u8 srev; + const char *name; + const char *v; + unsigned int rev; +}; + +static struct mx3_cpu_type mx31_cpu_type[] __initdata = { + { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 }, + { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 }, + { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 }, + { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 }, + { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 }, + { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 }, + { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 }, + { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 }, + { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 }, +}; + +void __init mx31_read_cpu_rev(void) +{ + u32 i, srev; + + /* read SREV register from IIM module */ + srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); + + for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) + if (srev == mx31_cpu_type[i].srev) { + printk(KERN_INFO + "CPU identified as %s, silicon rev %s\n", + mx31_cpu_type[i].name, mx31_cpu_type[i].v); + + mx31_cpu_rev = mx31_cpu_type[i].rev; + return; + } + + printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); +} diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 8cedf29eee1..be69272407a 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -260,11 +260,12 @@ #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) -extern unsigned int system_rev; +extern unsigned int mx31_cpu_rev; +extern void mx31_read_cpu_rev(void); static inline int mx31_revision(void) { - return system_rev; + return mx31_cpu_rev; } #endif -- cgit v1.2.3-70-g09d2 From 2abc1c50b6be81233e0b79478dc04d8fec737ed5 Mon Sep 17 00:00:00 2001 From: Tim Abbott Date: Fri, 2 Oct 2009 16:32:46 -0400 Subject: ARM: convert to use __HEAD and HEAD_TEXT macros. This has the consequence of changing the section name used for head code from ".text.head" to ".head.text". Since this commit changes all users in the architecture, this change should be harmless. The .text.head output section is eliminated and the head text code is included at the start of the .init output section. Signed-off-by: Tim Abbott Cc: Linus Torvalds Acked-by: Sam Ravnborg Signed-off-by: Russell King --- arch/arm/kernel/head-nommu.S | 2 +- arch/arm/kernel/head.S | 2 +- arch/arm/kernel/vmlinux.lds.S | 8 +++----- 3 files changed, 5 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index e5dfc2895e2..573b803dc6b 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -32,7 +32,7 @@ * numbers for r1. * */ - .section ".text.head", "ax" + __HEAD ENTRY(stext) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 38ccbe1d3b2..eb62bf94721 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -74,7 +74,7 @@ * crap here - that's what the boot loader (or in extreme, well justified * circumstances, zImage) is for. */ - .section ".text.head", "ax" + __HEAD ENTRY(stext) setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index aecf87dfbae..0902f806cd3 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -24,13 +24,11 @@ SECTIONS #else . = PAGE_OFFSET + TEXT_OFFSET; #endif - .text.head : { - _stext = .; - _sinittext = .; - *(.text.head) - } .init : { /* Init code and data */ + _stext = .; + _sinittext = .; + HEAD_TEXT INIT_TEXT _einittext = .; __proc_info_begin = .; -- cgit v1.2.3-70-g09d2 From 78d7530ac338e458fa513527ee7bb4278d0d8017 Mon Sep 17 00:00:00 2001 From: Nelson Elhage Date: Fri, 2 Oct 2009 16:32:47 -0400 Subject: ARM: Clean up linker script using new linker script macros. This patch is mostly a straightforward translation. The primary side effect to the resulting vmlinux should be to increase the alignment on the initramfs to the standard PAGE_SIZE from 32 bytes. Signed-off-by: Nelson Elhage Signed-off-by: Tim Abbott Acked-by: Sam Ravnborg Signed-off-by: Russell King --- arch/arm/kernel/vmlinux.lds.S | 77 +++++++++++++------------------------------ 1 file changed, 23 insertions(+), 54 deletions(-) (limited to 'arch') diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 0902f806cd3..71151bd87a3 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -40,43 +40,31 @@ SECTIONS __tagtable_begin = .; *(.taglist.init) __tagtable_end = .; - . = ALIGN(16); - __setup_start = .; - *(.init.setup) - __setup_end = .; + + INIT_SETUP(16) + __early_begin = .; *(.early_param.init) __early_end = .; - __initcall_start = .; - INITCALLS - __initcall_end = .; - __con_initcall_start = .; - *(.con_initcall.init) - __con_initcall_end = .; - __security_initcall_start = .; - *(.security_initcall.init) - __security_initcall_end = .; -#ifdef CONFIG_BLK_DEV_INITRD - . = ALIGN(32); - __initramfs_start = .; - usr/built-in.o(.init.ramfs) - __initramfs_end = .; -#endif - . = ALIGN(PAGE_SIZE); - __per_cpu_load = .; - __per_cpu_start = .; - *(.data.percpu.page_aligned) - *(.data.percpu) - *(.data.percpu.shared_aligned) - __per_cpu_end = .; + + INIT_CALLS + CON_INITCALL + SECURITY_INITCALL + INIT_RAM_FS + #ifndef CONFIG_XIP_KERNEL __init_begin = _stext; INIT_DATA - . = ALIGN(PAGE_SIZE); - __init_end = .; #endif } + PERCPU(PAGE_SIZE) + +#ifndef CONFIG_XIP_KERNEL + . = ALIGN(PAGE_SIZE); + __init_end = .; +#endif + /DISCARD/ : { /* Exit code and data */ EXIT_TEXT EXIT_DATA @@ -155,7 +143,7 @@ SECTIONS * first, the init task union, aligned * to an 8192 byte boundary. */ - *(.data.init_task) + INIT_TASK_DATA(THREAD_SIZE) #ifdef CONFIG_XIP_KERNEL . = ALIGN(PAGE_SIZE); @@ -165,17 +153,8 @@ SECTIONS __init_end = .; #endif - . = ALIGN(PAGE_SIZE); - __nosave_begin = .; - *(.data.nosave) - . = ALIGN(PAGE_SIZE); - __nosave_end = .; - - /* - * then the cacheline aligned data - */ - . = ALIGN(32); - *(.data.cacheline_aligned) + NOSAVE_DATA + CACHELINE_ALIGNED_DATA(32) /* * The exception fixup table (might need resorting at runtime) @@ -254,20 +233,10 @@ SECTIONS } #endif - .bss : { - __bss_start = .; /* BSS */ - *(.bss) - *(COMMON) - __bss_stop = .; - _end = .; - } - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } + BSS_SECTION(0, 0, 0) + _end = .; + + STABS_DEBUG .comment 0 : { *(.comment) } } -- cgit v1.2.3-70-g09d2 From 9e554540f8686d546639d1594a8259896c39633d Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 23 Nov 2009 19:16:35 +0100 Subject: mx31: pins used for mx31moboard USB Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 0dcfb777917..50efa24dc57 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -644,12 +644,22 @@ enum iomux_pins { #define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) +#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) #define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) #define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -- cgit v1.2.3-70-g09d2 From 33c4d91928bea4444b067e620496befbeb87029c Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 23 Nov 2009 19:16:36 +0100 Subject: mx31moboard: SPI corrections Adds requirement for ADC on mc13783 and moves the spidev declaration to marxbot file. Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx31moboard-marxbot.c | 13 +++++++++++++ arch/arm/mach-mx3/mx31moboard.c | 7 +------ 2 files changed, 14 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index e4e344eceb7..7d98cb0164f 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -126,6 +127,15 @@ static void dspics_resets_init(void) } } +static struct spi_board_info marxbot_spi_board_info[] __initdata = { + { + .modalias = "spidev", + .max_speed_hz = 300000, + .bus_num = 1, + .chip_select = 1, /* according spi1_cs[] ! */ + }, +}; + #define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) #define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5) #define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) @@ -217,6 +227,9 @@ void __init mx31moboard_marxbot_init(void) mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + spi_register_board_info(marxbot_spi_board_info, + ARRAY_SIZE(marxbot_spi_board_info)); + marxbot_cam_init(); platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras)); diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index b167f131f7c..2c9ea5f6181 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -213,6 +213,7 @@ static struct mc13783_platform_data moboard_pmic = { .regulators = moboard_regulators, .num_regulators = ARRAY_SIZE(moboard_regulators), .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC, + MC13783_USE_ADC, }; static struct spi_board_info moboard_spi_board_info[] __initdata = { @@ -225,12 +226,6 @@ static struct spi_board_info moboard_spi_board_info[] __initdata = { .platform_data = &moboard_pmic, .mode = SPI_CS_HIGH, }, - { - .modalias = "spidev", - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 1, /* according spi1_cs[] ! */ - }, }; static int moboard_spi2_cs[] = { -- cgit v1.2.3-70-g09d2 From d67d107586fa2c6fe4237292d58fb3787c75c6d1 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Mon, 23 Nov 2009 19:16:37 +0100 Subject: mx31moboard: support for usbh1 and usbh2 Signed-off-by: Valentin Longchamp Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/Kconfig | 1 + arch/arm/mach-mx3/mx31moboard-devboard.c | 86 ++++++++++++++++++++++++++++++++ arch/arm/mach-mx3/mx31moboard-marxbot.c | 86 ++++++++++++++++++++++++++++++++ arch/arm/mach-mx3/mx31moboard.c | 65 ++++++++++++++++++++++++ 4 files changed, 238 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index ffdd211e353..0177b8a5fe3 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -63,6 +63,7 @@ config MACH_MX31_3DS config MACH_MX31MOBOARD bool "Support mx31moboard platforms (EPFL Mobots group)" select ARCH_MX31 + select MXC_ULPI help Include support for mx31moboard platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 5592cdb8d0a..8fc624f141c 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -22,11 +22,15 @@ #include #include +#include + #include #include #include #include #include +#include +#include #include "devices.h" @@ -39,6 +43,12 @@ static unsigned int devboard_pins[] = { MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, + /* USB H1 */ + MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, + MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, + MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, + MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, + MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, }; static struct imxuart_platform_data uart_pdata = { @@ -98,6 +108,80 @@ static struct imxmmc_platform_data sdhc2_pdata = { .exit = devboard_sdhc2_exit, }; +#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +static int devboard_usbh1_hw_init(struct platform_device *pdev) +{ + mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); + + return 0; +} + +#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) +#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) + +static int devboard_isp1105_init(struct otg_transceiver *otg) +{ + int ret = gpio_request(USBH1_MODE, "usbh1-mode"); + if (ret) + return ret; + /* single ended */ + gpio_direction_output(USBH1_MODE, 0); + + ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); + if (ret) { + gpio_free(USBH1_MODE); + return ret; + } + gpio_direction_output(USBH1_VBUSEN_B, 1); + + return 0; +} + + +static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) +{ + if (on) + gpio_set_value(USBH1_VBUSEN_B, 0); + else + gpio_set_value(USBH1_VBUSEN_B, 1); + + return 0; +} + +static struct mxc_usbh_platform_data usbh1_pdata = { + .init = devboard_usbh1_hw_init, + .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, + .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, +}; + +static int __init devboard_usbh1_init(void) +{ + struct otg_transceiver *otg; + + otg = kzalloc(sizeof(*otg), GFP_KERNEL); + if (!otg) + return -ENOMEM; + + otg->label = "ISP1105"; + otg->init = devboard_isp1105_init; + otg->set_vbus = devboard_isp1105_set_vbus; + + usbh1_pdata.otg = otg; + + return mxc_register_device(&mx31_usbh1, &usbh1_pdata); +} + /* * system init for baseboard usage. Will be called by mx31moboard init. */ @@ -111,4 +195,6 @@ void __init mx31moboard_devboard_init(void) mxc_register_device(&mxc_uart_device1, &uart_pdata); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + + devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 7d98cb0164f..85184a35e67 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -25,11 +25,15 @@ #include #include +#include + #include #include #include #include #include +#include +#include #include @@ -56,6 +60,12 @@ static unsigned int marxbot_pins[] = { MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, /*battery detection */ MX31_PIN_LCS0__GPIO3_23, + /* USB H1 */ + MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, + MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, + MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, + MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, + MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, }; #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) @@ -213,6 +223,80 @@ static int __init marxbot_cam_init(void) return 0; } +#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ + PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + +static int marxbot_usbh1_hw_init(struct platform_device *pdev) +{ + mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); + + mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); + + return 0; +} + +#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) +#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) + +static int marxbot_isp1105_init(struct otg_transceiver *otg) +{ + int ret = gpio_request(USBH1_MODE, "usbh1-mode"); + if (ret) + return ret; + /* single ended */ + gpio_direction_output(USBH1_MODE, 0); + + ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); + if (ret) { + gpio_free(USBH1_MODE); + return ret; + } + gpio_direction_output(USBH1_VBUSEN_B, 1); + + return 0; +} + + +static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) +{ + if (on) + gpio_set_value(USBH1_VBUSEN_B, 0); + else + gpio_set_value(USBH1_VBUSEN_B, 1); + + return 0; +} + +static struct mxc_usbh_platform_data usbh1_pdata = { + .init = marxbot_usbh1_hw_init, + .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, + .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, +}; + +static int __init marxbot_usbh1_init(void) +{ + struct otg_transceiver *otg; + + otg = kzalloc(sizeof(*otg), GFP_KERNEL); + if (!otg) + return -ENOMEM; + + otg->label = "ISP1105"; + otg->init = marxbot_isp1105_init; + otg->set_vbus = marxbot_isp1105_set_vbus; + + usbh1_pdata.otg = otg; + + return mxc_register_device(&mx31_usbh1, &usbh1_pdata); +} + /* * system init for baseboard usage. Will be called by mx31moboard init. */ @@ -237,4 +321,6 @@ void __init mx31moboard_marxbot_init(void) gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); + + marxbot_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index 2c9ea5f6181..1ec679a3c72 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c @@ -32,6 +32,9 @@ #include #include +#include +#include + #include #include #include @@ -44,8 +47,10 @@ #include #include #include +#include #include #include +#include #include "devices.h" @@ -79,6 +84,15 @@ static unsigned int moboard_pins[] = { MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, MX31_PIN_USB_OC__GPIO1_30, + /* USB H2 */ + MX31_PIN_USBH2_DATA0__USBH2_DATA0, + MX31_PIN_USBH2_DATA1__USBH2_DATA1, + MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3, + MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5, + MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7, + MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, + MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, + MX31_PIN_SCK6__GPIO1_25, /* LEDs */ MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, @@ -332,6 +346,56 @@ static struct fsl_usb2_platform_data usb_pdata = { .phy_mode = FSL_USB2_PHY_ULPI, }; +#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) + +static int moboard_usbh2_hw_init(struct platform_device *pdev) +{ + int ret = gpio_request(USBH2_EN_B, "usbh2-en"); + if (ret) + return ret; + + mxc_iomux_set_gpr(MUX_PGP_UH2, true); + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); + + gpio_direction_output(USBH2_EN_B, 0); + + return 0; +} + +static int moboard_usbh2_hw_exit(struct platform_device *pdev) +{ + gpio_free(USBH2_EN_B); + return 0; +} + +static struct mxc_usbh_platform_data usbh2_pdata = { + .init = moboard_usbh2_hw_init, + .exit = moboard_usbh2_hw_exit, + .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, + .flags = MXC_EHCI_POWER_PINS_ENABLED, +}; + +static int __init moboard_usbh2_init(void) +{ + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + return mxc_register_device(&mx31_usbh2, &usbh2_pdata); +} + + static struct gpio_led mx31moboard_leds[] = { { .name = "coreboard-led-0:red:running", @@ -472,6 +536,7 @@ static void __init mxc_board_init(void) moboard_usbotg_init(); mxc_register_device(&mxc_otg_udc_device, &usb_pdata); + moboard_usbh2_init(); switch (mx31moboard_baseboard) { case MX31NOBOARD: -- cgit v1.2.3-70-g09d2 From c6e7c0e20d0ece2825389f5e24684490a440c427 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 12 Nov 2009 14:02:22 +0100 Subject: mx3: Add SSI pins to iomux table Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-mx3.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 50efa24dc57..2f6583e185a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -710,6 +710,14 @@ enum iomux_pins { #define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) #define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) #define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/ -- cgit v1.2.3-70-g09d2 From 654166d6879ed1e4df9815d04e6a358adf1259a6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 29 Oct 2009 17:18:02 +0100 Subject: mxc: iomux v3: remove resource handling The current model does not allow to put a pad into different modes once a pins is allocated. Remove the resource handling. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/include/mach/iomux-v3.h | 17 +-------------- arch/arm/plat-mxc/iomux-v3.c | 36 ++----------------------------- 2 files changed, 3 insertions(+), 50 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index a0fa4026546..1deda018489 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -88,9 +88,7 @@ struct pad_desc { #define PAD_CTL_SRE_FAST (1 << 0) /* - * setups a single pad: - * - reserves the pad so that it is not claimed by another driver - * - setups the iomux according to the configuration + * setups a single pad in the iomuxer */ int mxc_iomux_v3_setup_pad(struct pad_desc *pad); @@ -100,19 +98,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad); */ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); -/* - * releases a single pad: - * - make it available for a future use by another driver - * - DOES NOT reconfigure the IOMUX in its reset state - */ -void mxc_iomux_v3_release_pad(struct pad_desc *pad); - -/* - * releases multiple pads - * convenvient way to call the above function with tables - */ -void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); - /* * Initialise the iomux controller */ diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 851ca99bf1b..b318c6a222d 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -31,19 +31,11 @@ static void __iomem *base; -static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; - /* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration + * setups a single pad in the iomuxer */ int mxc_iomux_v3_setup_pad(struct pad_desc *pad) { - unsigned int pad_ofs = pad->pad_ctrl_ofs; - - if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) - return -EBUSY; if (pad->mux_ctrl_ofs) __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); @@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) for (i = 0; i < count; i++) { ret = mxc_iomux_v3_setup_pad(p); if (ret) - goto setup_error; + return ret; p++; } return 0; - -setup_error: - mxc_iomux_v3_release_multiple_pads(pad_list, i); - return ret; } EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); -void mxc_iomux_v3_release_pad(struct pad_desc *pad) -{ - unsigned int pad_ofs = pad->pad_ctrl_ofs; - - clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map); -} -EXPORT_SYMBOL(mxc_iomux_v3_release_pad); - -void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) -{ - struct pad_desc *p = pad_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_v3_release_pad(p); - p++; - } -} -EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); - void mxc_iomux_v3_init(void __iomem *iomux_v3_base) { base = iomux_v3_base; -- cgit v1.2.3-70-g09d2 From 74b2a70e34c69687f82b1319a358b21afeea497c Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 12 Nov 2009 14:09:39 +0100 Subject: i.MX31 clock: rename SSI clocks to driver name Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index bec097d176e..27a318af0d2 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c @@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) - _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) - _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) _REGISTER_CLOCK(NULL, "firi", firi_clk) _REGISTER_CLOCK(NULL, "ata", ata_clk) _REGISTER_CLOCK(NULL, "rtic", rtic_clk) -- cgit v1.2.3-70-g09d2 From 4998f1a30cf8e21c5bc0766fde4fa58e1adabd72 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Wed, 18 Nov 2009 15:21:44 +0100 Subject: mxc: mx1/mx2 DMA: add a possibility to create an endless DMA transfer This is useful for audio where we do not want to setup a new scatterlist after playing 4GB of audio data. This would cause skips in the playback. Signed-off-by: Sascha Hauer --- arch/arm/plat-mxc/dma-mx1-mx2.c | 3 ++- arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 77646436c00..9c1b3f9c4f4 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c @@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) } now = min(imxdma->resbytes, sg->length); - imxdma->resbytes -= now; + if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP) + imxdma->resbytes -= now; if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index b3876cc238c..07be8ad7ec3 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h @@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address, unsigned int dma_length, unsigned int dev_addr, unsigned int dmamode); + +/* + * Use this flag as the dma_length argument to imx_dma_setup_sg() + * to create an endless running dma loop. The end of the scatterlist + * must be linked to the beginning for this to work. + */ +#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) + int imx_dma_setup_sg(int channel, struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, -- cgit v1.2.3-70-g09d2 From fb3704663058ebb8ec05236f9c984b702550bac5 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 26 Nov 2009 11:55:19 +0000 Subject: ARM: fix "offest" -> "offset" typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Jiri Kosina Signed-off-by: Russell King --- arch/arm/plat-mxc/include/mach/mx2x.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index 1766c7c9184..f2eaf140ed0 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -25,7 +25,7 @@ /* The following addresses are common between i.MX21 and i.MX27 */ -/* Register offests */ +/* Register offsets */ #define MX2x_AIPI_BASE_ADDR 0x10000000 #define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 #define MX2x_AIPI_SIZE SZ_1M -- cgit v1.2.3-70-g09d2 From 97adeda043d4c2e11dcaca64a7e5fd0c4574c3fe Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 12 Nov 2009 22:56:29 +0100 Subject: IMX: don't disable the uart clock if DEBUG_LL uses it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before the clock was left enabled only for DEBUG_LL_CONSOLE which requires an additional patch to exist at all. With this patch applied DEBUG_LL_CONSOLE depends on DEBUG_LL, so this doesn't break. Signed-off-by: Uwe Kleine-König Cc: Sascha Hauer Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/clock_imx21.c | 2 +- arch/arm/mach-mx2/clock_imx27.c | 2 +- arch/arm/mach-mx3/clock-imx35.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index eede79855f4..91901b5d56c 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -1000,7 +1000,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&per_clk[0]); clk_enable(&gpio_clk); -#ifdef CONFIG_DEBUG_LL_CONSOLE +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) clk_enable(&uart_clk[0]); #endif diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index aa640b4876c..b010bf9ceaa 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -751,7 +751,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&emi_clk); clk_enable(&iim_clk); -#ifdef CONFIG_DEBUG_LL_CONSOLE +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) clk_enable(&uart1_clk); #endif diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 02a9a18e118..18d4775ff5f 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -485,7 +485,7 @@ int __init mx35_clocks_init() int i; unsigned int ll = 0; -#ifdef CONFIG_DEBUG_LL_CONSOLE +#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) ll = (3 << 16); #endif -- cgit v1.2.3-70-g09d2 From 143a179d6cafe939c881ee918574e3943157ef01 Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Wed, 25 Nov 2009 15:24:50 -0200 Subject: mx27: Add basic support for Maxtrack i-MXT TD60 Signed-off-by: Alan Carvalho de Assis Signed-off-by: Sascha Hauer --- arch/arm/mach-mx2/Kconfig | 7 + arch/arm/mach-mx2/Makefile | 1 + arch/arm/mach-mx2/mxt_td60.c | 284 ++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/uncompress.h | 1 + 4 files changed, 293 insertions(+) create mode 100644 arch/arm/mach-mx2/mxt_td60.c (limited to 'arch') diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index 3e14da3698b..b96c6a38936 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -104,4 +104,11 @@ config MACH_PCA100 Include support for phyCARD-s (aka pca100) platform. This includes specific configurations for the module and its peripherals. +config MACH_MXT_TD60 + bool "Maxtrack i-MXT TD60" + depends on MACH_MX27 + help + Include support for i-MXT (aka td60) platform. This + includes specific configurations for the module and its peripherals. + endif diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 19560f04563..52aca0aaf9b 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -20,4 +20,5 @@ obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o obj-$(CONFIG_MACH_PCA100) += pca100.o +obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mxt_td60.c new file mode 100644 index 00000000000..dd251f578e2 --- /dev/null +++ b/arch/arm/mach-mx2/mxt_td60.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +static unsigned int mxt_td60_pins[] __initdata = { + /* UART0 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* UART1 */ + PE3_PF_UART2_CTS, + PE4_PF_UART2_RTS, + PE6_PF_UART2_TXD, + PE7_PF_UART2_RXD, + /* UART2 */ + PE8_PF_UART3_TXD, + PE9_PF_UART3_RXD, + PE10_PF_UART3_CTS, + PE11_PF_UART3_RTS, + /* UART3 */ + PB26_AF_UART4_RTS, + PB28_AF_UART4_TXD, + PB29_AF_UART4_CTS, + PB31_AF_UART4_RXD, + /* UART4 */ + PB18_AF_UART5_TXD, + PB19_AF_UART5_RXD, + PB20_AF_UART5_CTS, + PB21_AF_UART5_RTS, + /* UART5 */ + PB10_AF_UART6_TXD, + PB12_AF_UART6_CTS, + PB11_AF_UART6_RXD, + PB13_AF_UART6_RTS, + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* I2C1 */ + PD17_PF_I2C_DATA, + PD18_PF_I2C_CLK, + /* I2C2 */ + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* FB */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA25_PF_CLS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + /* OWIRE */ + PE16_AF_OWIRE, + /* SDHC1*/ + PE18_PF_SD1_D0, + PE19_PF_SD1_D1, + PE20_PF_SD1_D2, + PE21_PF_SD1_D3, + PE22_PF_SD1_CMD, + PE23_PF_SD1_CLK, + /* SDHC2*/ + PB4_PF_SD2_D0, + PB5_PF_SD2_D1, + PB6_PF_SD2_D2, + PB7_PF_SD2_D3, + PB8_PF_SD2_CMD, + PB9_PF_SD2_CLK, +}; + +static struct mxc_nand_platform_data mxt_td60_nand_board_info = { + .width = 1, + .hw_ecc = 1, +}; + +static struct imxi2c_platform_data mxt_td60_i2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxt_td60_i2c_devices[] = { +}; + +static struct imxi2c_platform_data mxt_td60_i2c2_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxt_td60_i2c2_devices[] = { +}; + +static struct imx_fb_videomode mxt_td60_modes[] = { + { + .mode = { + .name = "Chimei LW700AT9003", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 30303, + .hsync_len = 64, + .left_margin = 0x67, + .right_margin = 0x68, + .vsync_len = 16, + .upper_margin = 0x0f, + .lower_margin = 0x0f, + }, + .bpp = 16, + .pcr = 0xFA208B83, + }, +}; + +static struct imx_fb_platform_data mxt_td60_fb_data = { + .mode = mxt_td60_modes, + .num_modes = ARRAY_SIZE(mxt_td60_modes), + + /* + * - HSYNC active high + * - VSYNC active high + * - clk notenabled while idle + * - clock inverted + * - data not inverted + * - data enable low active + * - enable sharp mode + */ + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + +static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq, + void *data) +{ + return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING, + "sdhc1-card-detect", data); +} + +static void mxt_td60_sdhc1_exit(struct device *dev, void *data) +{ + free_irq(IRQ_GPIOE(21), data); +} + +static struct imxmmc_platform_data sdhc1_pdata = { + .init = mxt_td60_sdhc1_init, + .exit = mxt_td60_sdhc1_exit, +}; + +static struct platform_device *platform_devices[] __initdata = { + &mxc_fec_device, +}; + +static struct imxuart_platform_data uart_pdata[] = { + { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, { + .flags = IMXUART_HAVE_RTSCTS, + }, +}; + +static void __init mxt_td60_board_init(void) +{ + mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), + "MXT_TD60"); + + mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); + mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); + mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); + mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); + mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); + mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); + mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); + + i2c_register_board_info(0, mxt_td60_i2c_devices, + ARRAY_SIZE(mxt_td60_i2c_devices)); + + i2c_register_board_info(1, mxt_td60_i2c2_devices, + ARRAY_SIZE(mxt_td60_i2c2_devices)); + + mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data); + mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data); + mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); + mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); +} + +static void __init mxt_td60_timer_init(void) +{ + mx27_clocks_init(26000000); +} + +static struct sys_timer mxt_td60_timer = { + .init = mxt_td60_timer_init, +}; + +MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") + /* maintainer: Maxtrack Industrial */ + .phys_io = AIPI_BASE_ADDR, + .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx27_map_io, + .init_irq = mx27_init_irq, + .init_machine = mxt_td60_board_init, + .timer = &mxt_td60_timer, +MACHINE_END + diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index a41bf57fb3d..4d5d395ad63 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -84,6 +84,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_PCM038: case MACH_TYPE_MX21ADS: case MACH_TYPE_PCA100: + case MACH_TYPE_MXT_TD60: uart_base = MX2X_UART1_BASE_ADDR; break; case MACH_TYPE_MX31LITE: -- cgit v1.2.3-70-g09d2 From 415c7d26d28fa10edb46503a8dd5b6440d479c0b Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Mon, 2 Nov 2009 11:37:36 +0900 Subject: Add KZM-ARM11-01 support Signed-off-by: Yoichi Yuasa Signed-off-by: Sascha Hauer --- arch/arm/configs/mx3_defconfig | 101 ++++++--- arch/arm/mach-mx3/Kconfig | 8 + arch/arm/mach-mx3/Makefile | 1 + arch/arm/mach-mx3/kzmarm11.c | 268 ++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/board-kzmarm11.h | 39 ++++ arch/arm/plat-mxc/include/mach/iomux-mx3.h | 8 + 6 files changed, 392 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-mx3/kzmarm11.c create mode 100644 arch/arm/plat-mxc/include/mach/board-kzmarm11.h (limited to 'arch') diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index a4f9a2a8149..7734ccab211 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31-rc4 -# Tue Jul 28 14:11:34 2009 +# Linux kernel version: 2.6.32-rc5 +# Sun Nov 1 22:56:24 2009 # CONFIG_ARM=y CONFIG_HAVE_PWM=y @@ -9,7 +9,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -46,11 +45,12 @@ CONFIG_SYSVIPC_SYSCTL=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -87,16 +87,14 @@ CONFIG_SHMEM=y CONFIG_AIO=y # -# Performance Counters +# Kernel Performance Events And Counters # CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y @@ -139,6 +137,7 @@ CONFIG_FREEZER=y # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set @@ -153,6 +152,7 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -175,18 +175,22 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set # # Freescale MXC Implementations # # CONFIG_ARCH_MX1 is not set # CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set CONFIG_ARCH_MX3=y +# CONFIG_ARCH_MXC91231 is not set CONFIG_ARCH_MX31=y CONFIG_ARCH_MX35=y @@ -205,6 +209,7 @@ CONFIG_MACH_QONG=y CONFIG_MACH_PCM043=y CONFIG_MACH_ARMADILLO5X0=y CONFIG_MACH_MX35_3DS=y +CONFIG_MACH_KZM_ARM11_01=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y CONFIG_ARCH_HAS_RNGA=y @@ -218,7 +223,7 @@ CONFIG_CPU_V6=y # CONFIG_CPU_32v6K is not set CONFIG_CPU_32v6=y CONFIG_CPU_ABRT_EV6=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_V6=y CONFIG_CPU_CACHE_V6=y CONFIG_CPU_CACHE_VIPT=y CONFIG_CPU_COPY_V6=y @@ -236,6 +241,7 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_OUTER_CACHE=y CONFIG_CACHE_L2X0=y +CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_ERRATA_411920 is not set CONFIG_COMMON_CLKDEV=y @@ -257,6 +263,8 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y @@ -277,6 +285,7 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y # CONFIG_UACCESS_WITH_MEMCPY is not set @@ -326,6 +335,7 @@ CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -367,6 +377,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -407,6 +418,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m @@ -416,9 +428,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set @@ -587,14 +599,12 @@ CONFIG_DNET=y # CONFIG_B44 is not set # CONFIG_CS89x0 is not set # CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set CONFIG_FEC=y # CONFIG_FEC2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# +CONFIG_WLAN=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set @@ -608,6 +618,7 @@ CONFIG_FEC=y # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support @@ -630,7 +641,14 @@ CONFIG_DEVKMEM=y # # Serial drivers # -# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_8250=m +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set # # Non-8250 serial port support @@ -649,6 +667,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_HELPER_AUTO=y @@ -681,15 +700,17 @@ CONFIG_I2C_IMX=y # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_GPIO_SYSFS is not set @@ -712,6 +733,10 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # + +# +# AC97 GPIO expanders: +# CONFIG_W1=y # @@ -734,7 +759,6 @@ CONFIG_W1_SLAVE_THERM=y # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -759,12 +783,24 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set CONFIG_MFD_WM8350=y CONFIG_MFD_WM8350_CONFIG_MODE_0=y CONFIG_MFD_WM8352_CONFIG_MODE_0=y CONFIG_MFD_WM8350_I2C=y # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_WM8350=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set CONFIG_MEDIA_SUPPORT=y # @@ -874,10 +910,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set CONFIG_MMC_MXC=y # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set CONFIG_DMADEVICES=y @@ -896,16 +934,11 @@ CONFIG_DMA_ENGINE=y # CONFIG_ASYNC_TX_DMA is not set # CONFIG_DMATEST is not set # CONFIG_AUXDISPLAY is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_BQ24022 is not set -# CONFIG_REGULATOR_MAX1586 is not set -CONFIG_REGULATOR_WM8350=y -# CONFIG_REGULATOR_LP3971 is not set # CONFIG_UIO is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set # @@ -921,6 +954,7 @@ CONFIG_REGULATOR_WM8350=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set @@ -995,7 +1029,6 @@ CONFIG_UBIFS_FS_ZLIB=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y @@ -1033,6 +1066,7 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -1062,7 +1096,6 @@ CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD2=y @@ -1104,11 +1137,13 @@ CONFIG_CRYPTO_CBC=y # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 0177b8a5fe3..ea8ed109a7c 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -103,4 +103,12 @@ config MACH_MX35_3DS help Include support for MX35PDK platform. This includes specific configurations for the board and its peripherals. + +config MACH_KZM_ARM11_01 + bool "Support KZM-ARM11-01(Kyoto Microcomputer)" + select ARCH_MX31 + help + Include support for KZM-ARM11-01. This includes specific + configurations for the board and its peripherals. + endif diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 940035cacae..93c7b296be6 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_QONG) += qong.o obj-$(CONFIG_MACH_PCM043) += pcm043.o obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o +obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/kzmarm11.c new file mode 100644 index 00000000000..6fa99ce3008 --- /dev/null +++ b/arch/arm/mach-mx3/kzmarm11.c @@ -0,0 +1,268 @@ +/* + * KZM-ARM11-01 support + * Copyright (C) 2009 Yoichi Yuasa + * + * based on code for MX31ADS, + * Copyright (C) 2000 Deep Blue Solutions Ltd + * Copyright (C) 2002 Shane Nay (shane@minirl.com) + * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "devices.h" + +#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) +/* + * KZM-ARM11-01 has an external UART on FPGA + */ +static struct plat_serial8250_port serial_platform_data[] = { + { + .membase = IO_ADDRESS(KZM_ARM11_16550), + .mapbase = KZM_ARM11_16550, + .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), + .irqflags = IRQ_TYPE_EDGE_RISING, + .uartclk = 14745600, + .regshift = 0, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | + UPF_BUGGY_UART, + }, + {}, +}; + +static struct resource serial8250_resources[] = { + { + .start = KZM_ARM11_16550, + .end = KZM_ARM11_16550 + 0x10, + .flags = IORESOURCE_MEM, + }, + { + .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), + .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = serial_platform_data, + }, + .num_resources = ARRAY_SIZE(serial8250_resources), + .resource = serial8250_resources, +}; + +static int __init kzm_init_ext_uart(void) +{ + u8 tmp; + + /* + * GPIO 1-1: external UART interrupt line + */ + mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); + + /* + * Unmask UART interrupt + */ + tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); + tmp |= 0x2; + __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); + + return platform_device_register(&serial_device); +} +#else +static inline int kzm_init_ext_uart(void) +{ + return 0; +} +#endif + +/* + * SMSC LAN9118 + */ +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +static struct smsc911x_platform_config kzm_smsc9118_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +}; + +static struct resource kzm_smsc9118_resources[] = { + { + .start = CS5_BASE_ADDR, + .end = CS5_BASE_ADDR + SZ_128K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), + .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + }, +}; + +static struct platform_device kzm_smsc9118_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(kzm_smsc9118_resources), + .resource = kzm_smsc9118_resources, + .dev = { + .platform_data = &kzm_smsc9118_config, + }, +}; + +static int __init kzm_init_smsc9118(void) +{ + /* + * GPIO 1-2: SMSC9118 interrupt line + */ + mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); + gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); + gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); + + return platform_device_register(&kzm_smsc9118_device); +} +#else +static inline int kzm_init_smsc9118(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static void __init kzm_init_imx_uart(void) +{ + mxc_register_device(&mxc_uart_device0, &uart_pdata); + + mxc_register_device(&mxc_uart_device1, &uart_pdata); +} +#else +static inline void kzm_init_imx_uart(void) +{ +} +#endif + +static int kzm_pins[] __initdata = { + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_RXD1__RXD1, + MX31_PIN_DCD_DCE1__DCD_DCE1, + MX31_PIN_RI_DCE1__RI_DCE1, + MX31_PIN_DSR_DCE1__DSR_DCE1, + MX31_PIN_DTR_DCE1__DTR_DCE1, + MX31_PIN_CTS2__CTS2, + MX31_PIN_RTS2__RTS2, + MX31_PIN_TXD2__TXD2, + MX31_PIN_RXD2__RXD2, + MX31_PIN_DCD_DTE1__DCD_DTE2, + MX31_PIN_RI_DTE1__RI_DTE2, + MX31_PIN_DSR_DTE1__DSR_DTE2, + MX31_PIN_DTR_DTE1__DTR_DTE2, +}; + +/* + * Board specific initialization. + */ +static void __init kzm_board_init(void) +{ + mxc_iomux_setup_multiple_pins(kzm_pins, + ARRAY_SIZE(kzm_pins), "kzm"); + kzm_init_ext_uart(); + kzm_init_smsc9118(); + kzm_init_imx_uart(); + + pr_info("Clock input source is 26MHz\n"); +} + +/* + * This structure defines static mappings for the kzm-arm11-01 board. + */ +static struct map_desc kzm_io_desc[] __initdata = { + { + .virtual = CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .length = CS4_SIZE, + .type = MT_DEVICE + }, + { + .virtual = CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(CS5_BASE_ADDR), + .length = CS5_SIZE, + .type = MT_DEVICE + }, +}; + +/* + * Set up static virtual mappings. + */ +static void __init kzm_map_io(void) +{ + mx31_map_io(); + iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc)); +} + +static void __init kzm_timer_init(void) +{ + mx31_clocks_init(26000000); +} + +static struct sys_timer kzm_timer = { + .init = kzm_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_KZM_ARM11_01 data structure. + */ +MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = kzm_map_io, + .init_irq = mx31_init_irq, + .init_machine = kzm_board_init, + .timer = &kzm_timer, +MACHINE_END diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h new file mode 100644 index 00000000000..05ff2f31ef1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2009 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H +#define __ARM_ARCH_BOARD_KZM_ARM11_H + +/* + * KZM-ARM11-01 Board Control Registers on FPGA + */ +#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) +#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) +#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) +#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) +#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) +#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) +#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) +#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) + +/* + * External UART for touch panel on FPGA + */ +#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) + +#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ + diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 2f6583e185a..eaabd4e9692 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -524,10 +524,18 @@ enum iomux_pins { #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) -- cgit v1.2.3-70-g09d2 From edabd38e1a017e922e3e3b485ee3ddb4df433aa4 Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Thu, 6 Aug 2009 15:12:43 +0300 Subject: ARM: add base support for Marvell Dove SoC The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/Kconfig | 13 + arch/arm/Makefile | 1 + arch/arm/boot/compressed/head.S | 6 + arch/arm/configs/dove_defconfig | 1617 +++++++++++++++++++++++++ arch/arm/mach-dove/Kconfig | 14 + arch/arm/mach-dove/Makefile | 3 + arch/arm/mach-dove/Makefile.boot | 3 + arch/arm/mach-dove/addr-map.c | 149 +++ arch/arm/mach-dove/common.c | 777 ++++++++++++ arch/arm/mach-dove/common.h | 40 + arch/arm/mach-dove/dove-db-setup.c | 102 ++ arch/arm/mach-dove/include/mach/bridge-regs.h | 58 + arch/arm/mach-dove/include/mach/debug-macro.S | 20 + arch/arm/mach-dove/include/mach/dove.h | 180 +++ arch/arm/mach-dove/include/mach/entry-macro.S | 39 + arch/arm/mach-dove/include/mach/gpio.h | 49 + arch/arm/mach-dove/include/mach/hardware.h | 26 + arch/arm/mach-dove/include/mach/io.h | 20 + arch/arm/mach-dove/include/mach/irqs.h | 101 ++ arch/arm/mach-dove/include/mach/memory.h | 10 + arch/arm/mach-dove/include/mach/pm.h | 54 + arch/arm/mach-dove/include/mach/system.h | 36 + arch/arm/mach-dove/include/mach/timex.h | 9 + arch/arm/mach-dove/include/mach/uncompress.h | 37 + arch/arm/mach-dove/include/mach/vmalloc.h | 5 + arch/arm/mach-dove/irq.c | 133 ++ arch/arm/mach-dove/pcie.c | 238 ++++ arch/arm/mm/Kconfig | 2 +- arch/arm/mm/proc-v6.S | 33 +- 29 files changed, 3773 insertions(+), 2 deletions(-) create mode 100644 arch/arm/configs/dove_defconfig create mode 100644 arch/arm/mach-dove/Kconfig create mode 100644 arch/arm/mach-dove/Makefile create mode 100644 arch/arm/mach-dove/Makefile.boot create mode 100644 arch/arm/mach-dove/addr-map.c create mode 100644 arch/arm/mach-dove/common.c create mode 100644 arch/arm/mach-dove/common.h create mode 100644 arch/arm/mach-dove/dove-db-setup.c create mode 100644 arch/arm/mach-dove/include/mach/bridge-regs.h create mode 100644 arch/arm/mach-dove/include/mach/debug-macro.S create mode 100644 arch/arm/mach-dove/include/mach/dove.h create mode 100644 arch/arm/mach-dove/include/mach/entry-macro.S create mode 100644 arch/arm/mach-dove/include/mach/gpio.h create mode 100644 arch/arm/mach-dove/include/mach/hardware.h create mode 100644 arch/arm/mach-dove/include/mach/io.h create mode 100644 arch/arm/mach-dove/include/mach/irqs.h create mode 100644 arch/arm/mach-dove/include/mach/memory.h create mode 100644 arch/arm/mach-dove/include/mach/pm.h create mode 100644 arch/arm/mach-dove/include/mach/system.h create mode 100644 arch/arm/mach-dove/include/mach/timex.h create mode 100644 arch/arm/mach-dove/include/mach/uncompress.h create mode 100644 arch/arm/mach-dove/include/mach/vmalloc.h create mode 100644 arch/arm/mach-dove/irq.c create mode 100644 arch/arm/mach-dove/pcie.c (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1c4119c6004..7fae1ef9dde 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -433,6 +433,17 @@ config ARCH_L7200 If you have any questions or comments about the Linux kernel port to this board, send e-mail to . +config ARCH_DOVE + bool "Marvell Dove" + select PCI + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select GENERIC_TIME + select GENERIC_CLOCKEVENTS + select PLAT_ORION + help + Support for the Marvell Dove SoC 88AP510 + config ARCH_KIRKWOOD bool "Marvell Kirkwood" select CPU_FEROCEON @@ -747,6 +758,8 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/mach-dove/Kconfig" + source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a73caaf6676..2ddc323b1c6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91) := at91 machine-$(CONFIG_ARCH_BCMRING) := bcmring machine-$(CONFIG_ARCH_CLPS711X) := clps711x machine-$(CONFIG_ARCH_DAVINCI) := davinci +machine-$(CONFIG_ARCH_DOVE) := dove machine-$(CONFIG_ARCH_EBSA110) := ebsa110 machine-$(CONFIG_ARCH_EP93XX) := ep93xx machine-$(CONFIG_ARCH_GEMINI) := gemini diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fa6fbf45cf3..d356af7cef8 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -743,6 +743,12 @@ proc_types: W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush + .word 0x560f5810 @ Marvell PJ4 ARMv6 + .word 0xff0ffff0 + W(b) __armv4_mmu_cache_on + W(b) __armv4_mmu_cache_off + W(b) __armv6_mmu_cache_flush + .word 0x000f0000 @ new CPU Id .word 0x000f0000 W(b) __armv7_mmu_cache_on diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig new file mode 100644 index 00000000000..f2d1ea0abb8 --- /dev/null +++ b/arch/arm/configs/dove_defconfig @@ -0,0 +1,1617 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc6 +# Tue Nov 24 13:48:39 2009 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +CONFIG_ARCH_DOVE=y +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set + +# +# Marvell Dove Implementations +# +CONFIG_MACH_DOVE_DB=y +CONFIG_PLAT_ORION=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_SYSCALL=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +CONFIG_SATA_MV=y +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +CONFIG_MV643XX_ETH=y +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_ORION=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_LANGWELL is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_MV_XOR=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +# CONFIG_ZISOFS is not set +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_BLOWFISH=y +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_MV_CESA is not set +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig new file mode 100644 index 00000000000..3b9a32ace90 --- /dev/null +++ b/arch/arm/mach-dove/Kconfig @@ -0,0 +1,14 @@ +if ARCH_DOVE + +menu "Marvell Dove Implementations" + +config MACH_DOVE_DB + bool "Marvell DB-MV88AP510 Development Board" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell DB-MV88AP510 Development Board. + +endmenu + +endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile new file mode 100644 index 00000000000..7ab3be53f64 --- /dev/null +++ b/arch/arm/mach-dove/Makefile @@ -0,0 +1,3 @@ +obj-y += common.o addr-map.o irq.o pcie.o + +obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot new file mode 100644 index 00000000000..67039c3e0c4 --- /dev/null +++ b/arch/arm/mach-dove/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c new file mode 100644 index 00000000000..00be4fc26dd --- /dev/null +++ b/arch/arm/mach-dove/addr-map.c @@ -0,0 +1,149 @@ +/* + * arch/arm/mach-dove/addr-map.c + * + * Address map functions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0x0 +#define TARGET_BOOTROM 0x1 +#define TARGET_CESA 0x3 +#define TARGET_PCIE0 0x4 +#define TARGET_PCIE1 0x8 +#define TARGET_SCRATCHPAD 0xd + +#define ATTR_CESA 0x01 +#define ATTR_BOOTROM 0xfd +#define ATTR_DEV_SPI0_ROM 0xfe +#define ATTR_DEV_SPI1_ROM 0xfb +#define ATTR_PCIE_IO 0xe0 +#define ATTR_PCIE_MEM 0xe8 +#define ATTR_SCRATCHPAD 0x0 + +/* + * CPU Address Decode Windows registers + */ +#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) +#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) +#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) +#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) + +struct mbus_dram_target_info dove_mbus_dram_info; + +static inline void __iomem *ddr_map_sc(int i) +{ + return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); +} + +static int cpu_win_can_remap(int win) +{ + if (win < 4) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base, WIN_BASE(win)); + writel(ctrl, WIN_CTRL(win)); + if (cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + writel(remap & 0xffff0000, WIN_REMAP_LO(win)); + writel(0, WIN_REMAP_HI(win)); + } +} + +void __init dove_setup_cpu_mbus(void) +{ + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + writel(0, WIN_BASE(i)); + writel(0, WIN_CTRL(i)); + if (cpu_win_can_remap(i)) { + writel(0, WIN_REMAP_LO(i)); + writel(0, WIN_REMAP_HI(i)); + } + } + + /* + * Setup windows for PCIe IO+MEM space. + */ + setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, + TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); + setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, + TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); + setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1); + + /* + * Setup window for CESA engine. + */ + setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, + TARGET_CESA, ATTR_CESA, -1); + + /* + * Setup the Window to the BootROM for Standby and Sleep Resume + */ + setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, + TARGET_BOOTROM, ATTR_BOOTROM, -1); + + /* + * Setup the Window to the PMU Scratch Pad space + */ + setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, + TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); + + /* + * Setup MBUS dram target info. + */ + dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 2; i++) { + u32 map = readl(ddr_map_sc(i)); + + /* + * Chip select enabled? + */ + if (map & 1) { + struct mbus_dram_window *w; + + w = &dove_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0; /* CS address decoding done inside */ + /* the DDR controller, no need to */ + /* provide attributes */ + w->base = map & 0xff800000; + w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); + } + } + dove_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c new file mode 100644 index 00000000000..a20cf099cd9 --- /dev/null +++ b/arch/arm/mach-dove/common.c @@ -0,0 +1,777 @@ +/* + * arch/arm/mach-dove/common.c + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc dove_io_desc[] __initdata = { + { + .virtual = DOVE_SB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), + .length = DOVE_SB_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_NB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), + .length = DOVE_NB_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE0_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), + .length = DOVE_PCIE0_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), + .length = DOVE_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init dove_map_io(void) +{ + iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); +} + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data dove_ehci_data = { + .dram = &dove_mbus_dram_info, + .phy_version = EHCI_PHY_NA, +}; + +static u64 ehci_dmamask = DMA_BIT_MASK(32); + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource dove_ehci0_resources[] = { + { + .start = DOVE_USB0_PHYS_BASE, + .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_USB0, + .end = IRQ_DOVE_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ehci0 = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &dove_ehci_data, + }, + .resource = dove_ehci0_resources, + .num_resources = ARRAY_SIZE(dove_ehci0_resources), +}; + +void __init dove_ehci0_init(void) +{ + platform_device_register(&dove_ehci0); +} + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource dove_ehci1_resources[] = { + { + .start = DOVE_USB1_PHYS_BASE, + .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_USB1, + .end = IRQ_DOVE_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ehci1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &dove_ehci_data, + }, + .resource = dove_ehci1_resources, + .num_resources = ARRAY_SIZE(dove_ehci1_resources), +}; + +void __init dove_ehci1_init(void) +{ + platform_device_register(&dove_ehci1); +} + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { + .t_clk = 0, + .dram = &dove_mbus_dram_info, +}; + +static struct resource dove_ge00_shared_resources[] = { + { + .name = "ge00 base", + .start = DOVE_GE00_PHYS_BASE + 0x2000, + .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &dove_ge00_shared_data, + }, + .num_resources = 1, + .resource = dove_ge00_shared_resources, +}; + +static struct resource dove_ge00_resources[] = { + { + .name = "ge00 irq", + .start = IRQ_DOVE_GE00_SUM, + .end = IRQ_DOVE_GE00_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = dove_ge00_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &dove_ge00_shared; + dove_ge00.dev.platform_data = eth_data; + + platform_device_register(&dove_ge00_shared); + platform_device_register(&dove_ge00); +} + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource dove_rtc_resource[] = { + { + .start = DOVE_RTC_PHYS_BASE, + .end = DOVE_RTC_PHYS_BASE + 32 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_RTC, + .flags = IORESOURCE_IRQ, + } +}; + +void __init dove_rtc_init(void) +{ + platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); +} + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource dove_sata_resources[] = { + { + .name = "sata base", + .start = DOVE_SATA_PHYS_BASE, + .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_DOVE_SATA, + .end = IRQ_DOVE_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dove_sata_resources), + .resource = dove_sata_resources, +}; + +void __init dove_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &dove_mbus_dram_info; + dove_sata.dev.platform_data = sata_data; + platform_device_register(&dove_sata); +} + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart0_data[] = { + { + .mapbase = DOVE_UART0_PHYS_BASE, + .membase = (char *)DOVE_UART0_VIRT_BASE, + .irq = IRQ_DOVE_UART_0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart0_resources[] = { + { + .start = DOVE_UART0_PHYS_BASE, + .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_0, + .end = IRQ_DOVE_UART_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = dove_uart0_data, + }, + .resource = dove_uart0_resources, + .num_resources = ARRAY_SIZE(dove_uart0_resources), +}; + +void __init dove_uart0_init(void) +{ + platform_device_register(&dove_uart0); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart1_data[] = { + { + .mapbase = DOVE_UART1_PHYS_BASE, + .membase = (char *)DOVE_UART1_VIRT_BASE, + .irq = IRQ_DOVE_UART_1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart1_resources[] = { + { + .start = DOVE_UART1_PHYS_BASE, + .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_1, + .end = IRQ_DOVE_UART_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = dove_uart1_data, + }, + .resource = dove_uart1_resources, + .num_resources = ARRAY_SIZE(dove_uart1_resources), +}; + +void __init dove_uart1_init(void) +{ + platform_device_register(&dove_uart1); +} + +/***************************************************************************** + * UART2 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart2_data[] = { + { + .mapbase = DOVE_UART2_PHYS_BASE, + .membase = (char *)DOVE_UART2_VIRT_BASE, + .irq = IRQ_DOVE_UART_2, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart2_resources[] = { + { + .start = DOVE_UART2_PHYS_BASE, + .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_2, + .end = IRQ_DOVE_UART_2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart2 = { + .name = "serial8250", + .id = 2, + .dev = { + .platform_data = dove_uart2_data, + }, + .resource = dove_uart2_resources, + .num_resources = ARRAY_SIZE(dove_uart2_resources), +}; + +void __init dove_uart2_init(void) +{ + platform_device_register(&dove_uart2); +} + +/***************************************************************************** + * UART3 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart3_data[] = { + { + .mapbase = DOVE_UART3_PHYS_BASE, + .membase = (char *)DOVE_UART3_VIRT_BASE, + .irq = IRQ_DOVE_UART_3, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart3_resources[] = { + { + .start = DOVE_UART3_PHYS_BASE, + .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_3, + .end = IRQ_DOVE_UART_3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart3 = { + .name = "serial8250", + .id = 3, + .dev = { + .platform_data = dove_uart3_data, + }, + .resource = dove_uart3_resources, + .num_resources = ARRAY_SIZE(dove_uart3_resources), +}; + +void __init dove_uart3_init(void) +{ + platform_device_register(&dove_uart3); +} + +/***************************************************************************** + * SPI0 + ****************************************************************************/ +static struct orion_spi_info dove_spi0_data = { + .tclk = 0, +}; + +static struct resource dove_spi0_resources[] = { + { + .start = DOVE_SPI0_PHYS_BASE, + .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SPI0, + .end = IRQ_DOVE_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_spi0 = { + .name = "orion_spi", + .id = 0, + .resource = dove_spi0_resources, + .dev = { + .platform_data = &dove_spi0_data, + }, + .num_resources = ARRAY_SIZE(dove_spi0_resources), +}; + +void __init dove_spi0_init(void) +{ + platform_device_register(&dove_spi0); +} + +/***************************************************************************** + * SPI1 + ****************************************************************************/ +static struct orion_spi_info dove_spi1_data = { + .tclk = 0, +}; + +static struct resource dove_spi1_resources[] = { + { + .start = DOVE_SPI1_PHYS_BASE, + .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SPI1, + .end = IRQ_DOVE_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_spi1 = { + .name = "orion_spi", + .id = 1, + .resource = dove_spi1_resources, + .dev = { + .platform_data = &dove_spi1_data, + }, + .num_resources = ARRAY_SIZE(dove_spi1_resources), +}; + +void __init dove_spi1_init(void) +{ + platform_device_register(&dove_spi1); +} + +/***************************************************************************** + * I2C + ****************************************************************************/ +static struct mv64xxx_i2c_pdata dove_i2c_data = { + .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource dove_i2c_resources[] = { + { + .name = "i2c base", + .start = DOVE_I2C_PHYS_BASE, + .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "i2c irq", + .start = IRQ_DOVE_I2C, + .end = IRQ_DOVE_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(dove_i2c_resources), + .resource = dove_i2c_resources, + .dev = { + .platform_data = &dove_i2c_data, + }, +}; + +void __init dove_i2c_init(void) +{ + platform_device_register(&dove_i2c); +} + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static int get_tclk(void) +{ + /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ + return 166666667; +} + +static void dove_timer_init(void) +{ + orion_time_init(IRQ_DOVE_BRIDGE, get_tclk()); +} + +struct sys_timer dove_timer = { + .init = dove_timer_init, +}; + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data dove_xor_shared_data = { + .dram = &dove_mbus_dram_info, +}; + +/***************************************************************************** + * XOR 0 + ****************************************************************************/ +static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .start = DOVE_XOR0_PHYS_BASE, + .end = DOVE_XOR0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = DOVE_XOR0_HIGH_PHYS_BASE, + .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &dove_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), + .resource = dove_xor0_shared_resources, +}; + +static struct resource dove_xor00_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_00, + .end = IRQ_DOVE_XOR_00, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor00_data = { + .shared = &dove_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(dove_xor00_resources), + .resource = dove_xor00_resources, + .dev = { + .dma_mask = &dove_xor0_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor00_data, + }, +}; + +static struct resource dove_xor01_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_01, + .end = IRQ_DOVE_XOR_01, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor01_data = { + .shared = &dove_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(dove_xor01_resources), + .resource = dove_xor01_resources, + .dev = { + .dma_mask = &dove_xor0_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor01_data, + }, +}; + +void __init dove_xor0_init(void) +{ + platform_device_register(&dove_xor0_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); + platform_device_register(&dove_xor00_channel); + + dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); + dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); + platform_device_register(&dove_xor01_channel); +} + +/***************************************************************************** + * XOR 1 + ****************************************************************************/ +static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_xor1_shared_resources[] = { + { + .name = "xor 0 low", + .start = DOVE_XOR1_PHYS_BASE, + .end = DOVE_XOR1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = DOVE_XOR1_HIGH_PHYS_BASE, + .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &dove_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), + .resource = dove_xor1_shared_resources, +}; + +static struct resource dove_xor10_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_10, + .end = IRQ_DOVE_XOR_10, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor10_data = { + .shared = &dove_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor10_channel = { + .name = MV_XOR_NAME, + .id = 2, + .num_resources = ARRAY_SIZE(dove_xor10_resources), + .resource = dove_xor10_resources, + .dev = { + .dma_mask = &dove_xor1_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor10_data, + }, +}; + +static struct resource dove_xor11_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_11, + .end = IRQ_DOVE_XOR_11, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor11_data = { + .shared = &dove_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor11_channel = { + .name = MV_XOR_NAME, + .id = 3, + .num_resources = ARRAY_SIZE(dove_xor11_resources), + .resource = dove_xor11_resources, + .dev = { + .dma_mask = &dove_xor1_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor11_data, + }, +}; + +void __init dove_xor1_init(void) +{ + platform_device_register(&dove_xor1_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); + platform_device_register(&dove_xor10_channel); + + dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); + dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); + platform_device_register(&dove_xor11_channel); +} + +void __init dove_init(void) +{ + int tclk; + + tclk = get_tclk(); + + printk(KERN_INFO "Dove 88AP510 SoC, "); + printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); + + dove_setup_cpu_mbus(); + + dove_ge00_shared_data.t_clk = tclk; + dove_uart0_data[0].uartclk = tclk; + dove_uart1_data[0].uartclk = tclk; + dove_uart2_data[0].uartclk = tclk; + dove_uart3_data[0].uartclk = tclk; + dove_spi0_data.tclk = tclk; + dove_spi1_data.tclk = tclk; + + /* internal devices that every board has */ + dove_rtc_init(); + dove_xor0_init(); + dove_xor1_init(); +} diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h new file mode 100644 index 00000000000..b29e8937de4 --- /dev/null +++ b/arch/arm/mach-dove/common.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-dove/common.h + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_DOVE_COMMON_H +#define __ARCH_DOVE_COMMON_H + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +extern struct sys_timer dove_timer; +extern struct mbus_dram_target_info dove_mbus_dram_info; + +/* + * Basic Dove init functions used early by machine-setup. + */ +void dove_map_io(void); +void dove_init(void); +void dove_init_irq(void); +void dove_setup_cpu_mbus(void); +void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); +void dove_sata_init(struct mv_sata_platform_data *sata_data); +void dove_pcie_init(int init_port0, int init_port1); +void dove_ehci0_init(void); +void dove_ehci1_init(void); +void dove_uart0_init(void); +void dove_uart1_init(void); +void dove_uart2_init(void); +void dove_uart3_init(void); +void dove_spi0_init(void); +void dove_spi1_init(void); +void dove_i2c_init(void); + +#endif diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c new file mode 100644 index 00000000000..f2971b74522 --- /dev/null +++ b/arch/arm/mach-dove/dove-db-setup.c @@ -0,0 +1,102 @@ +/* + * arch/arm/mach-dove/dove-db-setup.c + * + * Marvell DB-MV88AP510-BP Development Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static struct mv643xx_eth_platform_data dove_db_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, +}; + +static struct mv_sata_platform_data dove_db_sata_data = { + .n_ports = 1, +}; + +/***************************************************************************** + * SPI Devices: + * SPI0: 4M Flash ST-M25P32-VMF6P + ****************************************************************************/ +static const struct flash_platform_data dove_db_spi_flash_data = { + .type = "m25p64", +}; + +static struct spi_board_info __initdata dove_db_spi_flash_info[] = { + { + .modalias = "m25p80", + .platform_data = &dove_db_spi_flash_data, + .irq = -1, + .max_speed_hz = 20000000, + .bus_num = 0, + .chip_select = 0, + }, +}; + +/***************************************************************************** + * PCI + ****************************************************************************/ +static int __init dove_db_pci_init(void) +{ + if (machine_is_dove_db()) + dove_pcie_init(1, 1); + + return 0; +} + +subsys_initcall(dove_db_pci_init); + +/***************************************************************************** + * Board Init + ****************************************************************************/ +static void __init dove_db_init(void) +{ + /* + * Basic Dove setup. Needs to be called early. + */ + dove_init(); + + dove_ge00_init(&dove_db_ge00_data); + dove_ehci0_init(); + dove_ehci1_init(); + dove_sata_init(&dove_db_sata_data); + dove_spi0_init(); + dove_spi1_init(); + dove_uart0_init(); + dove_uart1_init(); + dove_i2c_init(); + spi_register_board_info(dove_db_spi_flash_info, + ARRAY_SIZE(dove_db_spi_flash_info)); +} + +MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") + .phys_io = DOVE_SB_REGS_PHYS_BASE, + .io_pg_offst = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = dove_db_init, + .map_io = dove_map_io, + .init_irq = dove_init_irq, + .timer = &dove_timer, +MACHINE_END diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h new file mode 100644 index 00000000000..214a4c31f06 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h @@ -0,0 +1,58 @@ +/* + * arch/arm/mach-dove/include/mach/bridge-regs.h + * + * Mbus-L to Mbus Bridge Registers + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_BRIDGE_REGS_H +#define __ASM_ARCH_BRIDGE_REGS_H + +#include + +#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) + +#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) +#define CPU_CTRL_PCIE0_LINK 0x00000001 +#define CPU_RESET 0x00000002 +#define CPU_CTRL_PCIE1_LINK 0x00000008 + +#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) +#define SOFT_RESET_OUT_EN 0x00000004 + +#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) +#define SOFT_RESET 0x00000001 + +#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) +#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) +#define BRIDGE_INT_TIMER0 0x0002 +#define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) + +#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) +#define IRQ_CAUSE_LOW_OFF 0x0000 +#define IRQ_MASK_LOW_OFF 0x0004 +#define FIQ_MASK_LOW_OFF 0x0008 +#define ENDPOINT_MASK_LOW_OFF 0x000c +#define IRQ_CAUSE_HIGH_OFF 0x0010 +#define IRQ_MASK_HIGH_OFF 0x0014 +#define FIQ_MASK_HIGH_OFF 0x0018 +#define ENDPOINT_MASK_HIGH_OFF 0x001c +#define PCIE_INTERRUPT_MASK_OFF 0x0020 + +#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) +#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) +#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) +#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) +#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) +#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) +#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) + +#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) + +#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) + +#endif diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S new file mode 100644 index 00000000000..9b89ec7d304 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/debug-macro.S @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-dove/include/mach/debug-macro.S + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart,rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =DOVE_SB_REGS_PHYS_BASE + ldrne \rx, =DOVE_SB_REGS_VIRT_BASE + orr \rx, \rx, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h new file mode 100644 index 00000000000..f6a08397f04 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/dove.h @@ -0,0 +1,180 @@ +/* + * arch/arm/mach-dove/include/mach/dove.h + * + * Generic definitions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_DOVE_H +#define __ASM_ARCH_DOVE_H + +#include + +/* + * Marvell Dove address maps. + * + * phys virt size + * c8000000 fdb00000 1M Cryptographic SRAM + * e0000000 @runtime 128M PCIe-0 Memory space + * e8000000 @runtime 128M PCIe-1 Memory space + * f1000000 fde00000 8M on-chip south-bridge registers + * f1800000 fe600000 8M on-chip north-bridge registers + * f2000000 fee00000 1M PCIe-0 I/O space + * f2100000 fef00000 1M PCIe-1 I/O space + */ + +#define DOVE_CESA_PHYS_BASE 0xc8000000 +#define DOVE_CESA_VIRT_BASE 0xfdb00000 +#define DOVE_CESA_SIZE SZ_1M + +#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 +#define DOVE_PCIE0_MEM_SIZE SZ_128M + +#define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 +#define DOVE_PCIE1_MEM_SIZE SZ_128M + +#define DOVE_BOOTROM_PHYS_BASE 0xf8000000 +#define DOVE_BOOTROM_SIZE SZ_128M + +#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 +#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 +#define DOVE_SCRATCHPAD_SIZE SZ_1M + +#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 +#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 +#define DOVE_SB_REGS_SIZE SZ_8M + +#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 +#define DOVE_NB_REGS_VIRT_BASE 0xfe600000 +#define DOVE_NB_REGS_SIZE SZ_8M + +#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 +#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 +#define DOVE_PCIE0_IO_BUS_BASE 0x00000000 +#define DOVE_PCIE0_IO_SIZE SZ_1M + +#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 +#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 +#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 +#define DOVE_PCIE1_IO_SIZE SZ_1M + +/* + * Dove Core Registers Map + */ + +/* SPI, I2C, UART */ +#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) +#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) +#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) +#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) +#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) +#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) +#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) +#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) +#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) +#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) +#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) + +/* North-South Bridge */ +#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) + +/* Cryptographic Engine */ +#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) + +/* PCIe 0 */ +#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) + +/* USB */ +#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) +#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) + +/* XOR 0 Engine */ +#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) +#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) +#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) +#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) + +/* XOR 1 Engine */ +#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) +#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) +#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) +#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) + +/* Gigabit Ethernet */ +#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) + +/* PCIe 1 */ +#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) + +/* CAFE */ +#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) +#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) +#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) +#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) + +/* SATA */ +#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) + +/* I2S/SPDIF */ +#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) +#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) + +/* NAND Flash Controller */ +#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) + +/* MPP, GPIO, Reset Sampling */ +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) +#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) +#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) +#define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) +#define DOVE_NAND_GPIO_EN (1 << 0) +#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) + + +/* Power Management */ +#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) + +/* Real Time Clock */ +#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) + +/* AC97 */ +#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) +#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) + +/* Peripheral DMA */ +#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) +#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) + +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) +#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) +#define DOVE_TWSI_OPTION3_GPIO (1 << 22) +#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_ON_AU1 (1 << 0) +#define DOVE_SSP_CLOCK_ENABLE (1 << 1) +#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) +/* Memory Controller */ +#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) + +/* LCD Controller */ +#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) +#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) +#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) +#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) + +/* Graphic Engine */ +#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) + +/* Video Engine */ +#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) + +#endif diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S new file mode 100644 index 00000000000..e84c78c2a8b --- /dev/null +++ b/arch/arm/mach-dove/include/mach/entry-macro.S @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-dove/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Dove platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] + ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] + mov \irqnr, #31 + ands \irqstat, \irqstat, \tmp + + @ if no low interrupts set, check high interrupts + ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] + ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] + moveq \irqnr, #63 + andeqs \irqstat, \irqstat, \tmp + + @ find first active interrupt source + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h new file mode 100644 index 00000000000..0ee70ff39e1 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/gpio.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-dove/include/mach/gpio.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include +#include +#include +#include /* cansleep wrappers */ + +#define GPIO_MAX 64 + +#define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) +#define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) + +#define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) + +#define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) +#define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08) +#define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c) + +static inline int gpio_to_irq(int pin) +{ + if (pin < NR_GPIO_IRQS) + return pin + IRQ_DOVE_GPIO_START; + + return -EINVAL; +} + +static inline int irq_to_gpio(int irq) +{ + if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS) + return irq - IRQ_DOVE_GPIO_START; + + return -EINVAL; +} + +#endif diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h new file mode 100644 index 00000000000..32b0826e787 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/hardware.h @@ -0,0 +1,26 @@ +/* + * arch/arm/mach-dove/include/mach/hardware.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include "dove.h" + +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0x1000 +#define PCIBIOS_MIN_MEM 0x01000000 +#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE + + +/* Macros below are required for compatibility with PXA AC'97 driver. */ +#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ + DOVE_SB_REGS_VIRT_BASE))) +#define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \ + DOVE_SB_REGS_PHYS_BASE) +#endif diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h new file mode 100644 index 00000000000..3b3e4721ce2 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/io.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-dove/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "dove.h" + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\ + DOVE_PCIE0_IO_VIRT_BASE)) +#define __mem_pci(a) (a) + +#endif diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h new file mode 100644 index 00000000000..46681466f92 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/irqs.h @@ -0,0 +1,101 @@ +/* + * arch/arm/mach-dove/include/mach/irqs.h + * + * IRQ definitions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* + * Dove Low Interrupt Controller + */ +#define IRQ_DOVE_BRIDGE 0 +#define IRQ_DOVE_H2C 1 +#define IRQ_DOVE_C2H 2 +#define IRQ_DOVE_NAND 3 +#define IRQ_DOVE_PDMA 4 +#define IRQ_DOVE_SPI1 5 +#define IRQ_DOVE_SPI0 6 +#define IRQ_DOVE_UART_0 7 +#define IRQ_DOVE_UART_1 8 +#define IRQ_DOVE_UART_2 9 +#define IRQ_DOVE_UART_3 10 +#define IRQ_DOVE_I2C 11 +#define IRQ_DOVE_GPIO_0_7 12 +#define IRQ_DOVE_GPIO_8_15 13 +#define IRQ_DOVE_GPIO_16_23 14 +#define IRQ_DOVE_PCIE0_ERR 15 +#define IRQ_DOVE_PCIE0 16 +#define IRQ_DOVE_PCIE1_ERR 17 +#define IRQ_DOVE_PCIE1 18 +#define IRQ_DOVE_I2S0 19 +#define IRQ_DOVE_I2S0_ERR 20 +#define IRQ_DOVE_I2S1 21 +#define IRQ_DOVE_I2S1_ERR 22 +#define IRQ_DOVE_USB_ERR 23 +#define IRQ_DOVE_USB0 24 +#define IRQ_DOVE_USB1 25 +#define IRQ_DOVE_GE00_RX 26 +#define IRQ_DOVE_GE00_TX 27 +#define IRQ_DOVE_GE00_MISC 28 +#define IRQ_DOVE_GE00_SUM 29 +#define IRQ_DOVE_GE00_ERR 30 +#define IRQ_DOVE_CRYPTO 31 + +/* + * Dove High Interrupt Controller + */ +#define IRQ_DOVE_AC97 32 +#define IRQ_DOVE_PMU 33 +#define IRQ_DOVE_CAM 34 +#define IRQ_DOVE_SDIO0 35 +#define IRQ_DOVE_SDIO1 36 +#define IRQ_DOVE_SDIO0_WAKEUP 37 +#define IRQ_DOVE_SDIO1_WAKEUP 38 +#define IRQ_DOVE_XOR_00 39 +#define IRQ_DOVE_XOR_01 40 +#define IRQ_DOVE_XOR0_ERR 41 +#define IRQ_DOVE_XOR_10 42 +#define IRQ_DOVE_XOR_11 43 +#define IRQ_DOVE_XOR1_ERR 44 +#define IRQ_DOVE_LCD_DCON 45 +#define IRQ_DOVE_LCD1 46 +#define IRQ_DOVE_LCD0 47 +#define IRQ_DOVE_GPU 48 +#define IRQ_DOVE_PERFORM_MNTR 49 +#define IRQ_DOVE_VPRO_DMA1 51 +#define IRQ_DOVE_SSP_TIMER 54 +#define IRQ_DOVE_SSP 55 +#define IRQ_DOVE_MC_L2_ERR 56 +#define IRQ_DOVE_CRYPTO_ERR 59 +#define IRQ_DOVE_GPIO_24_31 60 +#define IRQ_DOVE_HIGH_GPIO 61 +#define IRQ_DOVE_SATA 62 + +/* + * DOVE General Purpose Pins + */ +#define IRQ_DOVE_GPIO_START 64 +#define NR_GPIO_IRQS 64 + +/* + * PMU interrupts + */ +#define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) +#define NR_PMU_IRQS 7 +#define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) + +#define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) + +/* Required for compatability with PXA AC97 driver. */ +#define IRQ_AC97 IRQ_DOVE_AC97 +/* Required for compatability with PXA DMA driver. */ +#define IRQ_DMA IRQ_DOVE_PDMA +/* Required for compatability with PXA NAND driver */ +#define IRQ_NAND IRQ_DOVE_NAND +#endif diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h new file mode 100644 index 00000000000..d6687207494 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/memory.h @@ -0,0 +1,10 @@ +/* + * arch/arm/mach-dove/include/mach/memory.h + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x00000000) + +#endif diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h new file mode 100644 index 00000000000..3ad9f946a9e --- /dev/null +++ b/arch/arm/mach-dove/include/mach/pm.h @@ -0,0 +1,54 @@ +/* + * arch/arm/mach-dove/include/mach/pm.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_PM_H +#define __ASM_ARCH_PM_H + +#include +#include + +#define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) +#define CLOCK_GATING_USB0_MASK (1 << 0) +#define CLOCK_GATING_USB1_MASK (1 << 1) +#define CLOCK_GATING_GBE_MASK (1 << 2) +#define CLOCK_GATING_SATA_MASK (1 << 3) +#define CLOCK_GATING_PCIE0_MASK (1 << 4) +#define CLOCK_GATING_PCIE1_MASK (1 << 5) +#define CLOCK_GATING_SDIO0_MASK (1 << 8) +#define CLOCK_GATING_SDIO1_MASK (1 << 9) +#define CLOCK_GATING_NAND_MASK (1 << 10) +#define CLOCK_GATING_CAMERA_MASK (1 << 11) +#define CLOCK_GATING_I2S0_MASK (1 << 12) +#define CLOCK_GATING_I2S1_MASK (1 << 13) +#define CLOCK_GATING_CRYPTO_MASK (1 << 15) +#define CLOCK_GATING_AC97_MASK (1 << 21) +#define CLOCK_GATING_PDMA_MASK (1 << 22) +#define CLOCK_GATING_XOR0_MASK (1 << 23) +#define CLOCK_GATING_XOR1_MASK (1 << 24) +#define CLOCK_GATING_GIGA_PHY_MASK (1 << 30) + +#define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) +#define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) + +static inline int pmu_to_irq(int pin) +{ + if (pin < NR_PMU_IRQS) + return pin + IRQ_DOVE_PMU_START; + + return -EINVAL; +} + +static inline int irq_to_pmu(int irq) +{ + if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS) + return irq - IRQ_DOVE_PMU_START; + + return -EINVAL; +} + +#endif diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h new file mode 100644 index 00000000000..356afda5685 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/system.h @@ -0,0 +1,36 @@ +/* + * arch/arm/mach-dove/include/mach/system.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); + + /* + * Assert soft reset. + */ + writel(SOFT_RESET, SYSTEM_SOFT_RESET); + + while (1) + ; +} + + +#endif diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h new file mode 100644 index 00000000000..251d538541d --- /dev/null +++ b/arch/arm/mach-dove/include/mach/timex.h @@ -0,0 +1,9 @@ +/* + * arch/arm/mach-dove/include/mach/timex.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h new file mode 100644 index 00000000000..2c5cdd7a3ee --- /dev/null +++ b/arch/arm/mach-dove/include/mach/uncompress.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-dove/include/mach/uncompress.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0)) +#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14)) + +#define LSR_THRE 0x20 + +static void putc(const char c) +{ + int i; + + for (i = 0; i < 0x1000; i++) { + /* Transmit fifo not full? */ + if (*UART_LSR & LSR_THRE) + break; + } + + *UART_THR = c; +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h new file mode 100644 index 00000000000..8b2c974755c --- /dev/null +++ b/arch/arm/mach-dove/include/mach/vmalloc.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-dove/include/mach/vmalloc.h + */ + +#define VMALLOC_END 0xfd800000 diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c new file mode 100644 index 00000000000..61bfcb3b08c --- /dev/null +++ b/arch/arm/mach-dove/irq.c @@ -0,0 +1,133 @@ +/* + * arch/arm/mach-dove/irq.c + * + * Dove IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int irqoff; + BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO); + + irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 : + 3 + irq - IRQ_DOVE_GPIO_24_31; + + orion_gpio_irq_handler(irqoff << 3); + if (irq == IRQ_DOVE_HIGH_GPIO) { + orion_gpio_irq_handler(40); + orion_gpio_irq_handler(48); + orion_gpio_irq_handler(56); + } +} + +static void pmu_irq_mask(unsigned int irq) +{ + int pin = irq_to_pmu(irq); + u32 u; + + u = readl(PMU_INTERRUPT_MASK); + u &= ~(1 << (pin & 31)); + writel(u, PMU_INTERRUPT_MASK); +} + +static void pmu_irq_unmask(unsigned int irq) +{ + int pin = irq_to_pmu(irq); + u32 u; + + u = readl(PMU_INTERRUPT_MASK); + u |= 1 << (pin & 31); + writel(u, PMU_INTERRUPT_MASK); +} + +static void pmu_irq_ack(unsigned int irq) +{ + int pin = irq_to_pmu(irq); + u32 u; + + u = ~(1 << (pin & 31)); + writel(u, PMU_INTERRUPT_CAUSE); +} + +static struct irq_chip pmu_irq_chip = { + .name = "pmu_irq", + .mask = pmu_irq_mask, + .unmask = pmu_irq_unmask, + .ack = pmu_irq_ack, +}; + +static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + unsigned long cause = readl(PMU_INTERRUPT_CAUSE); + + cause &= readl(PMU_INTERRUPT_MASK); + if (cause == 0) { + do_bad_IRQ(irq, desc); + return; + } + + for (irq = 0; irq < NR_PMU_IRQS; irq++) { + if (!(cause & (1 << irq))) + continue; + irq = pmu_to_irq(irq); + desc = irq_desc + irq; + desc_handle_irq(irq, desc); + } +} + +void __init dove_init_irq(void) +{ + int i; + + orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); + orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); + + /* + * Mask and clear GPIO IRQ interrupts. + */ + writel(0, GPIO_LEVEL_MASK(0)); + writel(0, GPIO_EDGE_MASK(0)); + writel(0, GPIO_EDGE_CAUSE(0)); + + /* + * Mask and clear PMU interrupts + */ + writel(0, PMU_INTERRUPT_MASK); + writel(0, PMU_INTERRUPT_CAUSE); + + for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) { + set_irq_chip(i, &orion_gpio_irq_chip); + set_irq_handler(i, handle_level_irq); + irq_desc[i].status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); + set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); + set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); + set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); + set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); + + for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { + set_irq_chip(i, &pmu_irq_chip); + set_irq_handler(i, handle_level_irq); + irq_desc[i].status |= IRQ_LEVEL; + set_irq_flags(i, IRQF_VALID); + } + set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); +} diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c new file mode 100644 index 00000000000..502d1ca2f4b --- /dev/null +++ b/arch/arm/mach-dove/pcie.c @@ -0,0 +1,238 @@ +/* + * arch/arm/mach-dove/pcie.c + * + * PCIe functions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +struct pcie_port { + u8 index; + u8 root_bus_nr; + void __iomem *base; + spinlock_t conf_lock; + char io_space_name[16]; + char mem_space_name[16]; + struct resource res[2]; +}; + +static struct pcie_port pcie_port[2]; +static int num_pcie_ports; + + +static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) +{ + struct pcie_port *pp; + + if (nr >= num_pcie_ports) + return 0; + + pp = &pcie_port[nr]; + pp->root_bus_nr = sys->busnr; + + /* + * Generic PCIe unit setup. + */ + orion_pcie_set_local_bus_nr(pp->base, sys->busnr); + + orion_pcie_setup(pp->base, &dove_mbus_dram_info); + + /* + * IORESOURCE_IO + */ + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d I/O", pp->index); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + if (pp->index == 0) { + pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; + } else { + pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; + } + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); + sys->resource[0] = &pp->res[0]; + + /* + * IORESOURCE_MEM + */ + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), + "PCIe %d MEM", pp->index); + pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; + pp->res[1].name = pp->mem_space_name; + if (pp->index == 0) { + pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; + } else { + pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; + } + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) + panic("Request PCIe Memory resource failed\n"); + sys->resource[1] = &pp->res[1]; + + sys->resource[2] = NULL; + + return 1; +} + +static struct pcie_port *bus_to_port(int bus) +{ + int i; + + for (i = num_pcie_ports - 1; i >= 0; i--) { + int rbus = pcie_port[i].root_bus_nr; + if (rbus != -1 && rbus <= bus) + break; + } + + return i >= 0 ? pcie_port + i : NULL; +} + +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) +{ + /* + * Don't go out when trying to access nonexisting devices + * on the local bus. + */ + if (bus == pp->root_bus_nr && dev > 1) + return 0; + + return 1; +} + +static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { + *val = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 val) +{ + struct pcie_port *pp = bus_to_port(bus->number); + unsigned long flags; + int ret; + + if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + spin_lock_irqsave(&pp->conf_lock, flags); + ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); + spin_unlock_irqrestore(&pp->conf_lock, flags); + + return ret; +} + +static struct pci_ops pcie_ops = { + .read = pcie_rd_conf, + .write = pcie_wr_conf, +}; + +static void __devinit rc_pci_fixup(struct pci_dev *dev) +{ + /* + * Prevent enumeration of root complex. + */ + if (dev->bus->parent == NULL && dev->devfn == 0) { + int i; + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + dev->resource[i].start = 0; + dev->resource[i].end = 0; + dev->resource[i].flags = 0; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); + +static struct pci_bus __init * +dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) +{ + struct pci_bus *bus; + + if (nr < num_pcie_ports) { + bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); + } else { + bus = NULL; + BUG(); + } + + return bus; +} + +static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + struct pcie_port *pp = bus_to_port(dev->bus->number); + + return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; +} + +static struct hw_pci dove_pci __initdata = { + .nr_controllers = 2, + .swizzle = pci_std_swizzle, + .setup = dove_pcie_setup, + .scan = dove_pcie_scan_bus, + .map_irq = dove_pcie_map_irq, +}; + +static void __init add_pcie_port(int index, unsigned long base) +{ + printk(KERN_INFO "Dove PCIe port %d: ", index); + + if (orion_pcie_link_up((void __iomem *)base)) { + struct pcie_port *pp = &pcie_port[num_pcie_ports++]; + + printk(KERN_INFO "link up\n"); + + pp->index = index; + pp->root_bus_nr = -1; + pp->base = (void __iomem *)base; + spin_lock_init(&pp->conf_lock); + memset(pp->res, 0, sizeof(pp->res)); + } else { + printk(KERN_INFO "link down, ignoring\n"); + } +} + +void __init dove_pcie_init(int init_port0, int init_port1) +{ + if (init_port0) + add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); + + if (init_port1) + add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); + + pci_common_init(&dove_pci); +} diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9264d814cd7..1549863d7b5 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID # ARMv6 config CPU_V6 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE select CPU_32v6 select CPU_ABRT_EV6 select CPU_PABRT_V6 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 70f75d2e3ea..5485c821101 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext) - + .type cpu_v6_name, #object cpu_v6_name: .asciz "ARMv6-compatible processor" + .size cpu_v6_name, . - cpu_v6_name + + .type cpu_pj4_name, #object +cpu_pj4_name: + .asciz "Marvell PJ4 processor" + .size cpu_pj4_name, . - cpu_pj4_name + .align __INIT @@ -241,3 +248,27 @@ __v6_proc_info: .long v6_user_fns .long v6_cache_fns .size __v6_proc_info, . - __v6_proc_info + + .type __pj4_v6_proc_info, #object +__pj4_v6_proc_info: + .long 0x560f5810 + .long 0xff0ffff0 + .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + .long PMD_TYPE_SECT | \ + PMD_SECT_XN | \ + PMD_SECT_AP_WRITE | \ + PMD_SECT_AP_READ + b __v6_setup + .long cpu_arch_name + .long cpu_elf_name + .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP + .long cpu_pj4_name + .long v6_processor_functions + .long v6wbi_tlb_fns + .long v6_user_fns + .long v6_cache_fns + .size __pj4_v6_proc_info, . - __pj4_v6_proc_info -- cgit v1.2.3-70-g09d2 From 573a652fb0da50a1ff3fca2c67afd81138fd06d2 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Tue, 24 Nov 2009 19:33:52 +0200 Subject: ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/configs/dove_defconfig | 4 +- arch/arm/include/asm/hardware/cache-tauros2.h | 11 ++ arch/arm/mach-dove/common.c | 4 + arch/arm/mm/Kconfig | 9 + arch/arm/mm/Makefile | 2 +- arch/arm/mm/cache-tauros2.c | 263 ++++++++++++++++++++++++++ 6 files changed, 291 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/hardware/cache-tauros2.h create mode 100644 arch/arm/mm/cache-tauros2.c (limited to 'arch') diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index f2d1ea0abb8..837bb522d46 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.32-rc6 -# Tue Nov 24 13:48:39 2009 +# Tue Nov 24 13:51:23 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -207,6 +207,8 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_TAUROS2=y CONFIG_ARM_L1_CACHE_SHIFT=5 # CONFIG_ARM_ERRATA_411920 is not set diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h new file mode 100644 index 00000000000..538f17ca905 --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-tauros2.h @@ -0,0 +1,11 @@ +/* + * arch/arm/include/asm/hardware/cache-tauros2.h + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +extern void __init tauros2_init(void); diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index a20cf099cd9..806972a68c8 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -760,6 +761,9 @@ void __init dove_init(void) printk(KERN_INFO "Dove 88AP510 SoC, "); printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); +#ifdef CONFIG_CACHE_TAUROS2 + tauros2_init(); +#endif dove_setup_cpu_mbus(); dove_ge00_shared_data.t_clk = tclk; diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1549863d7b5..4958ef2c625 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -764,6 +764,15 @@ config CACHE_L2X0 help This option enables the L2x0 PrimeCell. +config CACHE_TAUROS2 + bool "Enable the Tauros2 L2 cache controller" + depends on ARCH_DOVE + default y + select OUTER_CACHE + help + This option enables the Tauros2 L2 cache controller (as + found on PJ1/PJ4). + config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 055cb2aa813..06bcf2e7385 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o - +obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c new file mode 100644 index 00000000000..50868651890 --- /dev/null +++ b/arch/arm/mm/cache-tauros2.c @@ -0,0 +1,263 @@ +/* + * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support + * + * Copyright (C) 2008 Marvell Semiconductor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * References: + * - PJ1 CPU Core Datasheet, + * Document ID MV-S104837-01, Rev 0.7, January 24 2008. + * - PJ4 CPU Core Datasheet, + * Document ID MV-S105190-00, Rev 0.7, March 14 2008. + */ + +#include +#include +#include + + +/* + * When Tauros2 is used on a CPU that supports the v7 hierarchical + * cache operations, the cache handling code in proc-v7.S takes care + * of everything, including handling DMA coherency. + * + * So, we only need to register outer cache operations here if we're + * being used on a pre-v7 CPU, and we only need to build support for + * outer cache operations into the kernel image if the kernel has been + * configured to support a pre-v7 CPU. + */ +#if __LINUX_ARM_ARCH__ < 7 +/* + * Low-level cache maintenance operations. + */ +static inline void tauros2_clean_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); +} + +static inline void tauros2_clean_inv_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); +} + +static inline void tauros2_inv_pa(unsigned long addr) +{ + __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); +} + + +/* + * Linux primitives. + * + * Note that the end addresses passed to Linux primitives are + * noninclusive. + */ +#define CACHE_LINE_SIZE 32 + +static void tauros2_inv_range(unsigned long start, unsigned long end) +{ + /* + * Clean and invalidate partial first cache line. + */ + if (start & (CACHE_LINE_SIZE - 1)) { + tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); + start = (start | (CACHE_LINE_SIZE - 1)) + 1; + } + + /* + * Clean and invalidate partial last cache line. + */ + if (end & (CACHE_LINE_SIZE - 1)) { + tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); + end &= ~(CACHE_LINE_SIZE - 1); + } + + /* + * Invalidate all full cache lines between 'start' and 'end'. + */ + while (start < end) { + tauros2_inv_pa(start); + start += CACHE_LINE_SIZE; + } + + dsb(); +} + +static void tauros2_clean_range(unsigned long start, unsigned long end) +{ + start &= ~(CACHE_LINE_SIZE - 1); + while (start < end) { + tauros2_clean_pa(start); + start += CACHE_LINE_SIZE; + } + + dsb(); +} + +static void tauros2_flush_range(unsigned long start, unsigned long end) +{ + start &= ~(CACHE_LINE_SIZE - 1); + while (start < end) { + tauros2_clean_inv_pa(start); + start += CACHE_LINE_SIZE; + } + + dsb(); +} +#endif + +static inline u32 __init read_extra_features(void) +{ + u32 u; + + __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); + + return u; +} + +static inline void __init write_extra_features(u32 u) +{ + __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); +} + +static void __init disable_l2_prefetch(void) +{ + u32 u; + + /* + * Read the CPU Extra Features register and verify that the + * Disable L2 Prefetch bit is set. + */ + u = read_extra_features(); + if (!(u & 0x01000000)) { + printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); + write_extra_features(u | 0x01000000); + } +} + +static inline int __init cpuid_scheme(void) +{ + extern int processor_id; + + return !!((processor_id & 0x000f0000) == 0x000f0000); +} + +static inline u32 __init read_mmfr3(void) +{ + u32 mmfr3; + + __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3)); + + return mmfr3; +} + +static inline u32 __init read_actlr(void) +{ + u32 actlr; + + __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); + + return actlr; +} + +static inline void __init write_actlr(u32 actlr) +{ + __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); +} + +void __init tauros2_init(void) +{ + extern int processor_id; + char *mode; + + disable_l2_prefetch(); + +#ifdef CONFIG_CPU_32v5 + if ((processor_id & 0xff0f0000) == 0x56050000) { + u32 feat; + + /* + * v5 CPUs with Tauros2 have the L2 cache enable bit + * located in the CPU Extra Features register. + */ + feat = read_extra_features(); + if (!(feat & 0x00400000)) { + printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); + write_extra_features(feat | 0x00400000); + } + + mode = "ARMv5"; + outer_cache.inv_range = tauros2_inv_range; + outer_cache.clean_range = tauros2_clean_range; + outer_cache.flush_range = tauros2_flush_range; + } +#endif + +#ifdef CONFIG_CPU_32v6 + /* + * Check whether this CPU lacks support for the v7 hierarchical + * cache ops. (PJ4 is in its v6 personality mode if the MMFR3 + * register indicates no support for the v7 hierarchical cache + * ops.) + */ + if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) { + /* + * When Tauros2 is used in an ARMv6 system, the L2 + * enable bit is in the ARMv6 ARM-mandated position + * (bit [26] of the System Control Register). + */ + if (!(get_cr() & 0x04000000)) { + printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); + adjust_cr(0x04000000, 0x04000000); + } + + mode = "ARMv6"; + outer_cache.inv_range = tauros2_inv_range; + outer_cache.clean_range = tauros2_clean_range; + outer_cache.flush_range = tauros2_flush_range; + } +#endif + +#ifdef CONFIG_CPU_32v7 + /* + * Check whether this CPU has support for the v7 hierarchical + * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 + * register indicates support for the v7 hierarchical cache + * ops.) + * + * (Although strictly speaking there may exist CPUs that + * implement the v7 cache ops but are only ARMv6 CPUs (due to + * not complying with all of the other ARMv7 requirements), + * there are no real-life examples of Tauros2 being used on + * such CPUs as of yet.) + */ + if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) { + u32 actlr; + + /* + * When Tauros2 is used in an ARMv7 system, the L2 + * enable bit is located in the Auxiliary System Control + * Register (which is the only register allowed by the + * ARMv7 spec to contain fine-grained cache control bits). + */ + actlr = read_actlr(); + if (!(actlr & 0x00000002)) { + printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); + write_actlr(actlr | 0x00000002); + } + + mode = "ARMv7"; + } +#endif + + if (mode == NULL) { + printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n"); + return; + } + + printk(KERN_INFO "Tauros2: L2 cache support initialised " + "in %s mode.\n", mode); +} -- cgit v1.2.3-70-g09d2 From da43243e765908d2ce6d22b2be995edf3218457d Mon Sep 17 00:00:00 2001 From: Saeed Bishara Date: Tue, 24 Nov 2009 19:33:53 +0200 Subject: RTC: let Dove soc select the rtc-mv driver. Signed-off-by: Saeed Bishara Signed-off-by: Nicolas Pitre --- arch/arm/configs/dove_defconfig | 3 ++- drivers/rtc/Kconfig | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index 837bb522d46..b3a491675d5 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.32-rc6 -# Tue Nov 24 13:51:23 2009 +# Tue Nov 24 13:53:37 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -1209,6 +1209,7 @@ CONFIG_RTC_INTF_DEV=y # # on-CPU RTC drivers # +CONFIG_RTC_DRV_MV=y CONFIG_DMADEVICES=y # diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 3c20dae43ce..e11e1cda4ba 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -780,7 +780,7 @@ config RTC_DRV_TX4939 config RTC_DRV_MV tristate "Marvell SoC RTC" - depends on ARCH_KIRKWOOD + depends on ARCH_KIRKWOOD || ARCH_DOVE help If you say yes here you will get support for the in-chip RTC that can be found in some of Marvell's SoC devices, such as -- cgit v1.2.3-70-g09d2 From 3e9a23dbaf581978d6e3eb8c92329ea622fce8ba Mon Sep 17 00:00:00 2001 From: Harro Haan Date: Fri, 27 Nov 2009 11:44:35 +0100 Subject: mx35: register usb_ahb clock in clock-imx35.c Signed-off-by: Harro Haan Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/clock-imx35.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 18d4775ff5f..7584b4c6c55 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -387,6 +387,8 @@ DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); +DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL); + static int clk_dummy_enable(struct clk *clk) { return 0; @@ -471,6 +473,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) + _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) _REGISTER_CLOCK(NULL, "max", max_clk) _REGISTER_CLOCK(NULL, "audmux", audmux_clk) -- cgit v1.2.3-70-g09d2 From 9c2daf15ac5aba3c7897540c3b606e54550d9c8f Mon Sep 17 00:00:00 2001 From: Harro Haan Date: Fri, 27 Nov 2009 11:44:36 +0100 Subject: mx35: add usb gadget support in mx35pdk.c Signed-off-by: Harro Haan Signed-off-by: Sascha Hauer --- arch/arm/mach-mx3/mx35pdk.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c index 6ff186e46ce..0bbc65ea23c 100644 --- a/arch/arm/mach-mx3/mx35pdk.c +++ b/arch/arm/mach-mx3/mx35pdk.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -69,6 +70,15 @@ static struct pad_desc mx35pdk_pads[] = { MX35_PAD_FEC_TDATA2__FEC_TDATA_2, MX35_PAD_FEC_RDATA3__FEC_RDATA_3, MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + /* USBOTG */ + MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, + MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, +}; + +/* OTG config */ +static struct fsl_usb2_platform_data usb_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI_WIDE, }; /* @@ -81,6 +91,8 @@ static void __init mxc_board_init(void) platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_uart_device0, &uart_pdata); + + mxc_register_device(&mxc_otg_udc_device, &usb_pdata); } static void __init mx35pdk_timer_init(void) -- cgit v1.2.3-70-g09d2 From 049ad833b1e52f6edeb675c744547167bf76ab2c Mon Sep 17 00:00:00 2001 From: Pieter Grimmerink Date: Fri, 13 Nov 2009 10:28:54 +0100 Subject: pxafb: add transparency field to pxafb_mode_info struct This allows to select either RGB565 (transparency 0) or RGBT555 (transparency 1) from the mode info Signed-off-by: Pieter Grimmerink Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/pxafb.h | 3 ++- drivers/video/pxafb.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index f73061c90b5..160ec83f51a 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h @@ -76,7 +76,8 @@ struct pxafb_mode_info { u_char bpp; u_int cmap_greyscale:1, depth:8, - unused:23; + transparency:1, + unused:22; /* Parallel Mode Timing */ u_char hsync_len; diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 33a6aacfcbe..f58a3aae6ea 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -398,6 +398,7 @@ static void pxafb_setmode(struct fb_var_screeninfo *var, var->lower_margin = mode->lower_margin; var->sync = mode->sync; var->grayscale = mode->cmap_greyscale; + var->transp.length = mode->transparency; /* set the initial RGBA bitfields */ pxafb_set_pixfmt(var, mode->depth); -- cgit v1.2.3-70-g09d2 From 70c7d2dd276dfb6aa802186a2be4efe80d380d15 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 5 Nov 2009 10:31:01 -0500 Subject: [ARM] pxa/saar: set default WLED output current Set default WLED output current in saar. Otherwise, LCD backlight won't be effective. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-pxa/saar.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 8241a63ea58..de588636f72 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -451,10 +451,15 @@ static inline void saar_init_lcd(void) {} #endif #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) +static struct da9034_backlight_pdata saar_da9034_backlight = { + .output_current = 4, /* 4mA */ +}; + static struct da903x_subdev_info saar_da9034_subdevs[] = { [0] = { .name = "da903x-backlight", .id = DA9034_ID_WLED, + .platform_data = &saar_da9034_backlight, }, }; -- cgit v1.2.3-70-g09d2 From 82b95ecb96122896fd5b7b75001fdda3e047ef38 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 10 Sep 2009 13:55:23 +0800 Subject: pxa3xx_nand: move pxa3xx_nand.h common into plat directory Since the same nand controller is shared between ARCH_PXA and ARCH_MMP. Move the pxa3xx_nand.h from mach directory to plat directoy. Signed-off-by: Haojian Zhuang Cc: David Woodhouse Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 2 +- arch/arm/mach-pxa/colibri-pxa3xx.c | 2 +- arch/arm/mach-pxa/devices.c | 4 +- arch/arm/mach-pxa/include/mach/pxa3xx_nand.h | 63 ---------------------------- arch/arm/mach-pxa/littleton.c | 4 +- arch/arm/mach-pxa/zylonite.c | 2 +- arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | 63 ++++++++++++++++++++++++++++ drivers/mtd/nand/pxa3xx_nand.c | 2 +- 8 files changed, 71 insertions(+), 71 deletions(-) delete mode 100644 arch/arm/mach-pxa/include/mach/pxa3xx_nand.h create mode 100644 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 102916f1e46..06552ca9181 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index efebaf4d734..e6c0a2287eb 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include "generic.h" #include "devices.h" diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 46fabe1cca1..e2b427fa55e 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -8,13 +8,13 @@ #include #include #include -#include #include #include #include #include #include -#include +#include +#include #include "devices.h" #include "generic.h" diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h b/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h deleted file mode 100644 index 3478eae32d8..00000000000 --- a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __ASM_ARCH_PXA3XX_NAND_H -#define __ASM_ARCH_PXA3XX_NAND_H - -#include -#include - -struct pxa3xx_nand_timing { - unsigned int tCH; /* Enable signal hold time */ - unsigned int tCS; /* Enable signal setup time */ - unsigned int tWH; /* ND_nWE high duration */ - unsigned int tWP; /* ND_nWE pulse time */ - unsigned int tRH; /* ND_nRE high duration */ - unsigned int tRP; /* ND_nRE pulse width */ - unsigned int tR; /* ND_nWE high to ND_nRE low for read */ - unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ - unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ -}; - -struct pxa3xx_nand_cmdset { - uint16_t read1; - uint16_t read2; - uint16_t program; - uint16_t read_status; - uint16_t read_id; - uint16_t erase; - uint16_t reset; - uint16_t lock; - uint16_t unlock; - uint16_t lock_status; -}; - -struct pxa3xx_nand_flash { - const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ - const struct pxa3xx_nand_cmdset *cmdset; - - uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ - uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ - uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ - uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ - uint32_t num_blocks; /* Number of physical blocks in Flash */ - uint32_t chip_id; -}; - -struct pxa3xx_nand_platform_data { - - /* the data flash bus is shared between the Static Memory - * Controller and the Data Flash Controller, the arbiter - * controls the ownership of the bus - */ - int enable_arbiter; - - /* allow platform code to keep OBM/bootloader defined NFC config */ - int keep_config; - - const struct mtd_partition *parts; - unsigned int nr_parts; - - const struct pxa3xx_nand_flash * flash; - size_t num_flash; -}; - -extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); -#endif /* __ASM_ARCH_PXA3XX_NAND_H */ diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 13848955d13..ce5e6175a05 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -44,10 +44,10 @@ #include #include #include -#include #include -#include #include +#include +#include #include "generic.h" diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 09784d3954e..8fcb69411cf 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include "devices.h" #include "generic.h" diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h new file mode 100644 index 00000000000..3478eae32d8 --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h @@ -0,0 +1,63 @@ +#ifndef __ASM_ARCH_PXA3XX_NAND_H +#define __ASM_ARCH_PXA3XX_NAND_H + +#include +#include + +struct pxa3xx_nand_timing { + unsigned int tCH; /* Enable signal hold time */ + unsigned int tCS; /* Enable signal setup time */ + unsigned int tWH; /* ND_nWE high duration */ + unsigned int tWP; /* ND_nWE pulse time */ + unsigned int tRH; /* ND_nRE high duration */ + unsigned int tRP; /* ND_nRE pulse width */ + unsigned int tR; /* ND_nWE high to ND_nRE low for read */ + unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ + unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ +}; + +struct pxa3xx_nand_cmdset { + uint16_t read1; + uint16_t read2; + uint16_t program; + uint16_t read_status; + uint16_t read_id; + uint16_t erase; + uint16_t reset; + uint16_t lock; + uint16_t unlock; + uint16_t lock_status; +}; + +struct pxa3xx_nand_flash { + const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ + const struct pxa3xx_nand_cmdset *cmdset; + + uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ + uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ + uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ + uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ + uint32_t num_blocks; /* Number of physical blocks in Flash */ + uint32_t chip_id; +}; + +struct pxa3xx_nand_platform_data { + + /* the data flash bus is shared between the Static Memory + * Controller and the Data Flash Controller, the arbiter + * controls the ownership of the bus + */ + int enable_arbiter; + + /* allow platform code to keep OBM/bootloader defined NFC config */ + int keep_config; + + const struct mtd_partition *parts; + unsigned int nr_parts; + + const struct pxa3xx_nand_flash * flash; + size_t num_flash; +}; + +extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); +#endif /* __ASM_ARCH_PXA3XX_NAND_H */ diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 7f97d57e8a5..1a5a0365c98 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -23,7 +23,7 @@ #include #include -#include +#include #define CHIP_DELAY_TIMEOUT (2 * HZ/10) -- cgit v1.2.3-70-g09d2 From a0f266c1fa040e1fe61b51e3de75b6a11e32ceb1 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 13 Oct 2009 15:24:55 +0800 Subject: [ARM] pxa: add nand device and clock for pxa168/pxa910 Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/include/mach/pxa168.h | 7 +++++++ arch/arm/mach-mmp/include/mach/pxa910.h | 7 +++++++ arch/arm/mach-mmp/pxa168.c | 5 +++++ arch/arm/mach-mmp/pxa910.c | 4 ++++ 4 files changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 6bf1f0eefcd..3ad612cbdf0 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h @@ -4,6 +4,7 @@ #include #include #include +#include extern struct pxa_device_desc pxa168_device_uart1; extern struct pxa_device_desc pxa168_device_uart2; @@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa168_device_pwm1; extern struct pxa_device_desc pxa168_device_pwm2; extern struct pxa_device_desc pxa168_device_pwm3; extern struct pxa_device_desc pxa168_device_pwm4; +extern struct pxa_device_desc pxa168_device_nand; static inline int pxa168_add_uart(int id) { @@ -64,4 +66,9 @@ static inline int pxa168_add_pwm(int id) return pxa_register_device(d, NULL, 0); } + +static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) +{ + return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); +} #endif /* __ASM_MACH_PXA168_H */ diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index 6ae1ed7a0a9..4f0b4ec6f5d 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h @@ -4,6 +4,7 @@ #include #include #include +#include extern struct pxa_device_desc pxa910_device_uart1; extern struct pxa_device_desc pxa910_device_uart2; @@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa910_device_pwm1; extern struct pxa_device_desc pxa910_device_pwm2; extern struct pxa_device_desc pxa910_device_pwm3; extern struct pxa_device_desc pxa910_device_pwm4; +extern struct pxa_device_desc pxa910_device_nand; static inline int pxa910_add_uart(int id) { @@ -64,4 +66,9 @@ static inline int pxa910_add_pwm(int id) return pxa_register_device(d, NULL, 0); } + +static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info) +{ + return pxa_register_device(&pxa910_device_nand, info, sizeof(*info)); +} #endif /* __ASM_MACH_PXA910_H */ diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 71b1ae33875..37dbdde17fa 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -72,6 +73,8 @@ static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); +static APMU_CLK(nand, NAND, 0x01db, 208000000); + /* device and clock bindings */ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), @@ -82,6 +85,7 @@ static struct clk_lookup pxa168_clkregs[] = { INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), }; static int __init pxa168_init(void) @@ -127,3 +131,4 @@ PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); +PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 5882ca6b49f..d4049508a4d 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c @@ -110,6 +110,8 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); +static APMU_CLK(nand, NAND, 0x01db, 208000000); + /* device and clock bindings */ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), @@ -120,6 +122,7 @@ static struct clk_lookup pxa910_clkregs[] = { INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), }; static int __init pxa910_init(void) @@ -174,3 +177,4 @@ PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); +PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); -- cgit v1.2.3-70-g09d2 From ef559def40cd5861ba2da747747c42c2f7331057 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 10 Sep 2009 14:37:48 +0800 Subject: [ARM] pxa: add nand support in aspensite board Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/aspenite.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index 4562452d407..a2d307ec042 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include @@ -85,12 +88,48 @@ static struct platform_device smc91x_device = { .resource = smc91x_resources, }; +static struct mtd_partition aspenite_nand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (SZ_2M + SZ_1M), + .mask_flags = 0, + }, { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = SZ_48M, + .mask_flags = 0, + } +}; + +static struct pxa3xx_nand_platform_data aspenite_nand_info = { + .enable_arbiter = 1, + .parts = aspenite_nand_partitions, + .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), +}; + static void __init common_init(void) { mfp_config(ARRAY_AND_SIZE(common_pin_config)); /* on-chip devices */ pxa168_add_uart(1); + pxa168_add_nand(&aspenite_nand_info); /* off-chip devices */ platform_device_register(&smc91x_device); -- cgit v1.2.3-70-g09d2 From d6587c34a6de8e2e577dfc149f2d4352752dafdf Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 23 Sep 2009 01:57:35 +0800 Subject: [ARM] pxa: add onenand support for TTC-DKB Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/ttc_dkb.c | 87 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 08cfef6c92a..bb26cb5351d 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -11,9 +11,13 @@ #include #include #include +#include +#include +#include #include #include +#include #include #include #include @@ -26,6 +30,86 @@ static unsigned long ttc_dkb_pin_config[] __initdata = { /* UART2 */ GPIO47_UART2_RXD, GPIO48_UART2_TXD, + + /* DFI */ + DF_IO0_ND_IO0, + DF_IO1_ND_IO1, + DF_IO2_ND_IO2, + DF_IO3_ND_IO3, + DF_IO4_ND_IO4, + DF_IO5_ND_IO5, + DF_IO6_ND_IO6, + DF_IO7_ND_IO7, + DF_IO8_ND_IO8, + DF_IO9_ND_IO9, + DF_IO10_ND_IO10, + DF_IO11_ND_IO11, + DF_IO12_ND_IO12, + DF_IO13_ND_IO13, + DF_IO14_ND_IO14, + DF_IO15_ND_IO15, + DF_nCS0_SM_nCS2_nCS0, + DF_ALE_SM_WEn_ND_ALE, + DF_CLE_SM_OEn_ND_CLE, + DF_WEn_DF_WEn, + DF_REn_DF_REn, + DF_RDY0_DF_RDY0, +}; + +static struct mtd_partition ttc_dkb_onenand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (SZ_2M + SZ_1M), + .mask_flags = 0, + }, { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = SZ_48M, + .mask_flags = 0, + } +}; + +static struct flash_platform_data ttc_dkb_onenand_info = { + .parts = ttc_dkb_onenand_partitions, + .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions), +}; + +static struct resource ttc_dkb_resource_onenand[] = { + [0] = { + .start = SMC_CS0_PHYS_BASE, + .end = SMC_CS0_PHYS_BASE + SZ_1M, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device ttc_dkb_device_onenand = { + .name = "onenand-flash", + .id = -1, + .resource = ttc_dkb_resource_onenand, + .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand), + .dev = { + .platform_data = &ttc_dkb_onenand_info, + }, +}; + +static struct platform_device *ttc_dkb_devices[] = { + &ttc_dkb_device_onenand, }; static void __init ttc_dkb_init(void) @@ -34,6 +118,9 @@ static void __init ttc_dkb_init(void) /* on-chip devices */ pxa910_add_uart(1); + + /* off-chip devices */ + platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); } MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") -- cgit v1.2.3-70-g09d2 From b1e3719e655a74065bdc5ddc58d6f1566dfe8138 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 25 Sep 2009 13:15:28 -0400 Subject: [ARM] pxa: add onenand support for SAAR Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-pxa/saar.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index de588636f72..926258703de 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -22,9 +22,13 @@ #include #include #include +#include +#include +#include #include #include +#include #include #include @@ -33,7 +37,7 @@ #include "devices.h" #include "generic.h" -#define GPIO_LCD_RESET (16) +#define GPIO_LCD_RESET (16) /* SAAR MFP configurations */ static mfp_cfg_t saar_mfp_cfg[] __initdata = { @@ -56,6 +60,31 @@ static mfp_cfg_t saar_mfp_cfg[] __initdata = { /* Ethernet */ DF_nCS1_nCS3, GPIO97_GPIO, + + /* DFI */ + DF_INT_RnB_ND_INT_RnB, + DF_nRE_nOE_ND_nRE, + DF_nWE_ND_nWE, + DF_CLE_nOE_ND_CLE, + DF_nADV1_ALE_ND_ALE, + DF_nADV2_ALE_nCS3, + DF_nCS0_ND_nCS0, + DF_IO0_ND_IO0, + DF_IO1_ND_IO1, + DF_IO2_ND_IO2, + DF_IO3_ND_IO3, + DF_IO4_ND_IO4, + DF_IO5_ND_IO5, + DF_IO6_ND_IO6, + DF_IO7_ND_IO7, + DF_IO8_ND_IO8, + DF_IO9_ND_IO9, + DF_IO10_ND_IO10, + DF_IO11_ND_IO11, + DF_IO12_ND_IO12, + DF_IO13_ND_IO13, + DF_IO14_ND_IO14, + DF_IO15_ND_IO15, }; #define SAAR_ETH_PHYS (0x14000000) @@ -485,12 +514,77 @@ static void __init saar_init_i2c(void) #else static inline void saar_init_i2c(void) {} #endif + +#if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE) +static struct mtd_partition saar_onenand_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_128K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "reserved", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = (SZ_2M + SZ_1M), + .mask_flags = 0, + }, { + .name = "filesystem", + .offset = MTDPART_OFS_APPEND, + .size = SZ_48M, + .mask_flags = 0, + } +}; + +static struct flash_platform_data saar_onenand_info = { + .parts = saar_onenand_partitions, + .nr_parts = ARRAY_SIZE(saar_onenand_partitions), +}; + +#define SMC_CS0_PHYS_BASE (0x10000000) + +static struct resource saar_resource_onenand[] = { + [0] = { + .start = SMC_CS0_PHYS_BASE, + .end = SMC_CS0_PHYS_BASE + SZ_1M, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device saar_device_onenand = { + .name = "onenand-flash", + .id = -1, + .dev = { + .platform_data = &saar_onenand_info, + }, + .resource = saar_resource_onenand, + .num_resources = ARRAY_SIZE(saar_resource_onenand), +}; + +static void __init saar_init_onenand(void) +{ + platform_device_register(&saar_device_onenand); +} +#else +static void __init saar_init_onenand(void) {} +#endif + static void __init saar_init(void) { /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); platform_device_register(&smc91x_device); + saar_init_onenand(); saar_init_i2c(); saar_init_lcd(); -- cgit v1.2.3-70-g09d2 From d62238711a0a917ddc6bb47390c7502806c963b1 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 20 Nov 2009 10:57:16 -0500 Subject: [ARM] pxa: update flash structure in onenand info Since flash structure is changed from flash_platform_data to onenand_platform_data in generic driver. Update the struct in saar and ttc platform driver. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/ttc_dkb.c | 2 +- arch/arm/mach-pxa/saar.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index bb26cb5351d..8f49b2b1260 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c @@ -85,7 +85,7 @@ static struct mtd_partition ttc_dkb_onenand_partitions[] = { } }; -static struct flash_platform_data ttc_dkb_onenand_info = { +static struct onenand_platform_data ttc_dkb_onenand_info = { .parts = ttc_dkb_onenand_partitions, .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions), }; diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 926258703de..3cccb085b97 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -545,7 +545,7 @@ static struct mtd_partition saar_onenand_partitions[] = { } }; -static struct flash_platform_data saar_onenand_info = { +static struct onenand_platform_data saar_onenand_info = { .parts = saar_onenand_partitions, .nr_parts = ARRAY_SIZE(saar_onenand_partitions), }; -- cgit v1.2.3-70-g09d2 From bb2ae8f0325221a2dfd9eb31554f42e9c24abdf2 Mon Sep 17 00:00:00 2001 From: Tomáš Čech Date: Fri, 11 Sep 2009 13:57:01 +0200 Subject: [ARM] pxa/treo: generalisation of Treo680 code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Tomáš Čech Acked-by: Marek Vasut Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 5 + arch/arm/mach-pxa/Makefile | 2 +- arch/arm/mach-pxa/include/mach/palmtreo.h | 60 ++++ arch/arm/mach-pxa/include/mach/treo680.h | 49 --- arch/arm/mach-pxa/palmtreo.c | 551 ++++++++++++++++++++++++++++++ arch/arm/mach-pxa/treo680.c | 519 ---------------------------- 6 files changed, 617 insertions(+), 569 deletions(-) create mode 100644 arch/arm/mach-pxa/include/mach/palmtreo.h delete mode 100644 arch/arm/mach-pxa/include/mach/treo680.h create mode 100644 arch/arm/mach-pxa/palmtreo.c delete mode 100644 arch/arm/mach-pxa/treo680.c (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index a6f8eab14ba..ce6519c000a 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -421,12 +421,17 @@ config MACH_PALMZ72 Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. +config PALM_TREO + bool + depends on ARCH_PXA_PALM + config MACH_TREO680 bool "Palm Treo 680" default y depends on ARCH_PXA_PALM select PXA27x select IWMMXT + select PALM_TREO help Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f10e152bfc2..e5d450c5434 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -64,7 +64,7 @@ obj-$(CONFIG_MACH_PALMT5) += palmt5.o obj-$(CONFIG_MACH_PALMTX) += palmtx.o obj-$(CONFIG_MACH_PALMLD) += palmld.o obj-$(CONFIG_MACH_PALMZ72) += palmz72.o -obj-$(CONFIG_MACH_TREO680) += treo680.o +obj-$(CONFIG_PALM_TREO) += palmtreo.o obj-$(CONFIG_ARCH_VIPER) += viper.o ifeq ($(CONFIG_MACH_ZYLONITE),y) diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h new file mode 100644 index 00000000000..8cb0bca7f70 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmtreo.h @@ -0,0 +1,60 @@ +/* + * GPIOs and interrupts for Palm Treo smartphones + * + * currently supported: + * Palm Treo 680 (GSM) + * + * Author: Tomas Cech + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * find more info at www.hackndev.com + * + */ + +#ifndef _INCLUDE_TREO_H_ +#define _INCLUDE_TREO_H_ + +/* GPIOs */ +#define GPIO_NR_TREO_POWER_DETECT 0 +#define GPIO_NR_TREO_AMP_EN 27 +#define GPIO_NR_TREO_GREEN_LED 20 +#define GPIO_NR_TREO_RED_LED 79 +#define GPIO_NR_TREO_SD_DETECT_N 113 +#define GPIO_NR_TREO_EP_DETECT_N 116 +#define GPIO_NR_TREO_USB_DETECT 1 +#define GPIO_NR_TREO_USB_PULLUP 114 +#define GPIO_NR_TREO_GSM_POWER 40 +#define GPIO_NR_TREO_GSM_RESET 87 +#define GPIO_NR_TREO_GSM_WAKE 57 +#define GPIO_NR_TREO_GSM_HOST_WAKE 14 +#define GPIO_NR_TREO_GSM_TRIGGER 10 +#define GPIO_NR_TREO_IR_EN 115 +#define GPIO_NR_TREO_IR_TXD 47 +#define GPIO_NR_TREO_BL_POWER 38 +#define GPIO_NR_TREO_LCD_POWER 25 + +/* Treo680 specific GPIOs */ +#ifdef CONFIG_MACH_TREO680 +#define GPIO_NR_TREO680_SD_READONLY 33 +#define GPIO_NR_TREO680_SD_POWER 42 +#define GPIO_NR_TREO680_VIBRATE_EN 44 +#define GPIO_NR_TREO680_KEYB_BL 24 +#define GPIO_NR_TREO680_BT_EN 43 +#endif /* CONFIG_MACH_TREO680 */ + +/* Various addresses */ +#define TREO_PHYS_RAM_START 0xa0000000 +#define TREO_PHYS_IO_START 0x40000000 +#define TREO_STR_BASE 0xa2000000 + +/* BACKLIGHT */ +#define TREO_MAX_INTENSITY 254 +#define TREO_DEFAULT_INTENSITY 160 +#define TREO_LIMIT_MASK 0x7F +#define TREO_PRESCALER 63 +#define TREO_PERIOD_NS 3500 + +#endif diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h deleted file mode 100644 index af443b24d99..00000000000 --- a/arch/arm/mach-pxa/include/mach/treo680.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * GPIOs and interrupts for Palm Treo 680 smartphone - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _INCLUDE_TREO680_H_ -#define _INCLUDE_TREO680_H_ - -/* GPIOs */ -#define GPIO_NR_TREO680_POWER_DETECT 0 -#define GPIO_NR_TREO680_AMP_EN 27 -#define GPIO_NR_TREO680_KEYB_BL 24 -#define GPIO_NR_TREO680_VIBRATE_EN 44 -#define GPIO_NR_TREO680_GREEN_LED 20 -#define GPIO_NR_TREO680_RED_LED 79 -#define GPIO_NR_TREO680_SD_DETECT_N 113 -#define GPIO_NR_TREO680_SD_READONLY 33 -#define GPIO_NR_TREO680_EP_DETECT_N 116 -#define GPIO_NR_TREO680_SD_POWER 42 -#define GPIO_NR_TREO680_USB_DETECT 1 -#define GPIO_NR_TREO680_USB_PULLUP 114 -#define GPIO_NR_TREO680_GSM_POWER 40 -#define GPIO_NR_TREO680_GSM_RESET 87 -#define GPIO_NR_TREO680_GSM_WAKE 57 -#define GPIO_NR_TREO680_GSM_HOST_WAKE 14 -#define GPIO_NR_TREO680_GSM_TRIGGER 10 -#define GPIO_NR_TREO680_BT_EN 43 -#define GPIO_NR_TREO680_IR_EN 115 -#define GPIO_NR_TREO680_IR_TXD 47 -#define GPIO_NR_TREO680_BL_POWER 38 -#define GPIO_NR_TREO680_LCD_POWER 25 - -/* Various addresses */ -#define TREO680_PHYS_RAM_START 0xa0000000 -#define TREO680_PHYS_IO_START 0x40000000 -#define TREO680_STR_BASE 0xa2000000 - -/* BACKLIGHT */ -#define TREO680_MAX_INTENSITY 254 -#define TREO680_DEFAULT_INTENSITY 160 -#define TREO680_LIMIT_MASK 0x7F -#define TREO680_PRESCALER 63 -#define TREO680_PERIOD_NS 3500 - -#endif diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c new file mode 100644 index 00000000000..5e66028d291 --- /dev/null +++ b/arch/arm/mach-pxa/palmtreo.c @@ -0,0 +1,551 @@ +/* + * Hardware definitions for Palm Treo smartphones + * + * currently supported: + * Palm Treo 680 (GSM) + * + * Author: Tomas Cech + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (find more info at www.hackndev.com) + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "generic.h" +#include "devices.h" + +/****************************************************************************** + * Pin configuration + ******************************************************************************/ +static unsigned long treo_pin_config[] __initdata = { + /* MMC */ + GPIO32_MMC_CLK, + GPIO92_MMC_DAT_0, + GPIO109_MMC_DAT_1, + GPIO110_MMC_DAT_2, + GPIO111_MMC_DAT_3, + GPIO112_MMC_CMD, + GPIO113_GPIO, /* SD detect */ + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO89_AC97_SYSCLK, + GPIO95_AC97_nRESET, + + /* IrDA */ + GPIO46_FICP_RXD, + GPIO47_FICP_TXD, + + /* PWM */ + GPIO16_PWM0_OUT, + + /* USB */ + GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ + + /* MATRIX KEYPAD */ + GPIO101_KP_MKIN_1, + GPIO102_KP_MKIN_2, + GPIO97_KP_MKIN_3, + GPIO98_KP_MKIN_4, + GPIO91_KP_MKIN_6, + GPIO13_KP_MKIN_7, + GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, + GPIO104_KP_MKOUT_1, + GPIO105_KP_MKOUT_2, + GPIO106_KP_MKOUT_3, + GPIO107_KP_MKOUT_4, + GPIO108_KP_MKOUT_5, + GPIO96_KP_MKOUT_6, + GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + + /* Quick Capture Interface */ + GPIO84_CIF_FV, + GPIO85_CIF_LV, + GPIO53_CIF_MCLK, + GPIO54_CIF_PCLK, + GPIO81_CIF_DD_0, + GPIO55_CIF_DD_1, + GPIO51_CIF_DD_2, + GPIO50_CIF_DD_3, + GPIO52_CIF_DD_4, + GPIO48_CIF_DD_5, + GPIO17_CIF_DD_6, + GPIO12_CIF_DD_7, + + /* I2C */ + GPIO117_I2C_SCL, + GPIO118_I2C_SDA, + + /* GSM */ + GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO39_FFUART_TXD, + GPIO41_FFUART_RTS, + + /* MISC. */ + GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */ + GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */ + GPIO116_GPIO, /* headphone detect */ + GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ +}; + +#ifdef CONFIG_MACH_TREO680 +static unsigned long treo680_pin_config[] __initdata = { + GPIO33_GPIO, /* SD read only */ + + /* MATRIX KEYPAD - different wake up source */ + GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, + GPIO99_KP_MKIN_5, +}; +#endif /* CONFIG_MACH_TREO680 */ + +/****************************************************************************** + * SD/MMC card controller + ******************************************************************************/ +#ifdef CONFIG_MACH_TREO680 +static struct pxamci_platform_data treo680_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, + .gpio_card_ro = GPIO_NR_TREO680_SD_READONLY, + .gpio_power = GPIO_NR_TREO680_SD_POWER, +}; +#endif /* CONFIG_MACH_TREO680 */ + +/****************************************************************************** + * GPIO keyboard + ******************************************************************************/ +#ifdef CONFIG_MACH_TREO680 +static unsigned int treo680_matrix_keys[] = { + KEY(0, 0, KEY_F8), /* Red/Off/Power */ + KEY(0, 1, KEY_LEFT), + KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ + KEY(0, 3, KEY_L), + KEY(0, 4, KEY_A), + KEY(0, 5, KEY_Q), + KEY(0, 6, KEY_P), + + KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ + KEY(1, 1, KEY_RIGHT), + KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ + KEY(1, 3, KEY_Z), + KEY(1, 4, KEY_S), + KEY(1, 5, KEY_W), + + KEY(2, 0, KEY_F1), /* Phone */ + KEY(2, 1, KEY_UP), + KEY(2, 2, KEY_0), + KEY(2, 3, KEY_X), + KEY(2, 4, KEY_D), + KEY(2, 5, KEY_E), + + KEY(3, 0, KEY_F10), /* Calendar */ + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_SPACE), + KEY(3, 3, KEY_C), + KEY(3, 4, KEY_F), + KEY(3, 5, KEY_R), + + KEY(4, 0, KEY_F12), /* Mail */ + KEY(4, 1, KEY_KPENTER), + KEY(4, 2, KEY_RIGHTALT), /* Alt */ + KEY(4, 3, KEY_V), + KEY(4, 4, KEY_G), + KEY(4, 5, KEY_T), + + KEY(5, 0, KEY_F9), /* Home */ + KEY(5, 1, KEY_PAGEUP), /* Side up */ + KEY(5, 2, KEY_DOT), + KEY(5, 3, KEY_B), + KEY(5, 4, KEY_H), + KEY(5, 5, KEY_Y), + + KEY(6, 0, KEY_TAB), /* Side Activate */ + KEY(6, 1, KEY_PAGEDOWN), /* Side down */ + KEY(6, 2, KEY_ENTER), + KEY(6, 3, KEY_N), + KEY(6, 4, KEY_J), + KEY(6, 5, KEY_U), + + KEY(7, 0, KEY_F6), /* Green/Call */ + KEY(7, 1, KEY_O), + KEY(7, 2, KEY_BACKSPACE), + KEY(7, 3, KEY_M), + KEY(7, 4, KEY_K), + KEY(7, 5, KEY_I), +}; + +static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { + .matrix_key_rows = 8, + .matrix_key_cols = 7, + .matrix_key_map = treo680_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), + .direct_key_map = { KEY_CONNECT }, + .direct_key_num = 1, + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_TREO680 */ + +/****************************************************************************** + * aSoC audio + ******************************************************************************/ + +static pxa2xx_audio_ops_t treo_ac97_pdata = { + .reset_gpio = 95, +}; + +/****************************************************************************** + * Backlight + ******************************************************************************/ +static int treo_backlight_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO_BL_POWER, "BL POWER"); + if (ret) + goto err; + ret = gpio_direction_output(GPIO_NR_TREO_BL_POWER, 0); + if (ret) + goto err2; + + return 0; + +err2: + gpio_free(GPIO_NR_TREO_BL_POWER); +err: + return ret; +} + +static int treo_backlight_notify(int brightness) +{ + gpio_set_value(GPIO_NR_TREO_BL_POWER, brightness); + return TREO_MAX_INTENSITY - brightness; +}; + +static void treo_backlight_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO_BL_POWER); +} + +static struct platform_pwm_backlight_data treo_backlight_data = { + .pwm_id = 0, + .max_brightness = TREO_MAX_INTENSITY, + .dft_brightness = TREO_DEFAULT_INTENSITY, + .pwm_period_ns = TREO_PERIOD_NS, + .init = treo_backlight_init, + .notify = treo_backlight_notify, + .exit = treo_backlight_exit, +}; + +static struct platform_device treo_backlight = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &treo_backlight_data, + }, +}; + +/****************************************************************************** + * IrDA + ******************************************************************************/ +static struct pxaficp_platform_data treo_ficp_info = { + .gpio_pwdown = GPIO_NR_TREO_IR_EN, + .transceiver_cap = IR_SIRMODE | IR_OFF, +}; + +/****************************************************************************** + * UDC + ******************************************************************************/ +static struct pxa2xx_udc_mach_info treo_udc_info __initdata = { + .gpio_vbus = GPIO_NR_TREO_USB_DETECT, + .gpio_vbus_inverted = 1, + .gpio_pullup = GPIO_NR_TREO_USB_PULLUP, +}; + + +/****************************************************************************** + * USB host + ******************************************************************************/ +#ifdef CONFIG_MACH_TREO680 +static struct pxaohci_platform_data treo680_ohci_info = { + .port_mode = PMM_PERPORT_MODE, + .flags = ENABLE_PORT1 | ENABLE_PORT3, + .power_budget = 0, +}; +#endif /* CONFIG_MACH_TREO680 */ + +/****************************************************************************** + * Power supply + ******************************************************************************/ +static int power_supply_init(struct device *dev) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO_POWER_DETECT, "CABLE_STATE_AC"); + if (ret) + goto err1; + ret = gpio_direction_input(GPIO_NR_TREO_POWER_DETECT); + if (ret) + goto err2; + + return 0; + +err2: + gpio_free(GPIO_NR_TREO_POWER_DETECT); +err1: + return ret; +} + +static int treo_is_ac_online(void) +{ + return gpio_get_value(GPIO_NR_TREO_POWER_DETECT); +} + +static void power_supply_exit(struct device *dev) +{ + gpio_free(GPIO_NR_TREO_POWER_DETECT); +} + +static char *treo_supplicants[] = { + "main-battery", +}; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = treo_is_ac_online, + .exit = power_supply_exit, + .supplied_to = treo_supplicants, + .num_supplicants = ARRAY_SIZE(treo_supplicants), +}; + +static struct platform_device power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &power_supply_info, + }, +}; + +/****************************************************************************** + * Vibra and LEDs + ******************************************************************************/ +#ifdef CONFIG_MACH_TREO680 +static struct gpio_led treo680_gpio_leds[] = { + { + .name = "treo680:vibra:vibra", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_VIBRATE_EN, + }, + { + .name = "treo680:green:led", + .default_trigger = "mmc0", + .gpio = GPIO_NR_TREO_GREEN_LED, + }, + { + .name = "treo680:white:keybbl", + .default_trigger = "none", + .gpio = GPIO_NR_TREO680_KEYB_BL, + }, +}; + +static struct gpio_led_platform_data treo680_gpio_led_info = { + .leds = treo680_gpio_leds, + .num_leds = ARRAY_SIZE(treo680_gpio_leds), +}; + +static struct platform_device treo680_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &treo680_gpio_led_info, + } +}; +#endif /* CONFIG_MACH_TREO680 */ + +/****************************************************************************** + * Framebuffer + ******************************************************************************/ +/* TODO: add support for 324x324 */ +static struct pxafb_mode_info treo_lcd_modes[] = { +{ + .pixclock = 86538, + .xres = 320, + .yres = 320, + .bpp = 16, + + .left_margin = 20, + .right_margin = 8, + .upper_margin = 8, + .lower_margin = 5, + + .hsync_len = 4, + .vsync_len = 1, +}, +}; + +static void treo_lcd_power(int on, struct fb_var_screeninfo *info) +{ + gpio_set_value(GPIO_NR_TREO_BL_POWER, on); +} + +static struct pxafb_mach_info treo_lcd_screen = { + .modes = treo_lcd_modes, + .num_modes = ARRAY_SIZE(treo_lcd_modes), + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +/****************************************************************************** + * Power management - standby + ******************************************************************************/ +static void __init treo_pm_init(void) +{ + static u32 resume[] = { + 0xe3a00101, /* mov r0, #0x40000000 */ + 0xe380060f, /* orr r0, r0, #0x00f00000 */ + 0xe590f008, /* ldr pc, [r0, #0x08] */ + }; + + /* this is where the bootloader jumps */ + memcpy(phys_to_virt(TREO_STR_BASE), resume, sizeof(resume)); +} + +/****************************************************************************** + * Machine init + ******************************************************************************/ +static struct platform_device *treo_devices[] __initdata = { + &treo_backlight, + &power_supply, +}; + +#ifdef CONFIG_MACH_TREO680 +static struct platform_device *treo680_devices[] __initdata = { + &treo680_leds, +}; +#endif /* CONFIG_MACH_TREO680 */ + +/* setup udc GPIOs initial state */ +static void __init treo_udc_init(void) +{ + if (!gpio_request(GPIO_NR_TREO_USB_PULLUP, "UDC Vbus")) { + gpio_direction_output(GPIO_NR_TREO_USB_PULLUP, 1); + gpio_free(GPIO_NR_TREO_USB_PULLUP); + } +} + +static void __init treo_lcd_power_init(void) +{ + int ret; + + ret = gpio_request(GPIO_NR_TREO_LCD_POWER, "LCD POWER"); + if (ret) { + pr_err("Treo680: LCD power GPIO request failed!\n"); + return; + } + + ret = gpio_direction_output(GPIO_NR_TREO_LCD_POWER, 0); + if (ret) { + pr_err("Treo680: setting LCD power GPIO direction failed!\n"); + gpio_free(GPIO_NR_TREO_LCD_POWER); + return; + } + + treo_lcd_screen.pxafb_lcd_power = treo_lcd_power; +} + +static void __init treo_init(void) +{ + treo_pm_init(); + pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config)); + treo_lcd_power_init(); + set_pxa_fb_info(&treo_lcd_screen); + treo_udc_init(); + pxa_set_udc_info(&treo_udc_info); + pxa_set_ac97_info(&treo_ac97_pdata); + pxa_set_ficp_info(&treo_ficp_info); + + platform_add_devices(ARRAY_AND_SIZE(treo_devices)); +} + +#ifdef CONFIG_MACH_TREO680 +static void __init treo680_init(void) +{ + treo_init(); + pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); + pxa_set_mci_info(&treo680_mci_platform_data); + pxa_set_keypad_info(&treo680_keypad_platform_data); + pxa_set_ohci_info(&treo680_ohci_info); + + platform_add_devices(ARRAY_AND_SIZE(treo680_devices)); +} + +MACHINE_START(TREO680, "Palm Treo 680") + .phys_io = TREO_PHYS_IO_START, + .io_pg_offst = io_p2v(0x40000000), + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = treo680_init, +MACHINE_END +#endif /* CONFIG_MACH_TREO680 */ diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/treo680.c deleted file mode 100644 index fe085076fbf..00000000000 --- a/arch/arm/mach-pxa/treo680.c +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Hardware definitions for Palm Treo 680 - * - * Author: Tomas Cech - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * (find more info at www.hackndev.com) - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "generic.h" -#include "devices.h" - -/****************************************************************************** - * Pin configuration - ******************************************************************************/ -static unsigned long treo680_pin_config[] __initdata = { - /* MMC */ - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, - GPIO33_GPIO, /* SD read only */ - GPIO113_GPIO, /* SD detect */ - - /* AC97 */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - GPIO89_AC97_SYSCLK, - GPIO95_AC97_nRESET, - - /* IrDA */ - GPIO46_FICP_RXD, - GPIO47_FICP_TXD, - - /* PWM */ - GPIO16_PWM0_OUT, - - /* USB */ - GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ - - /* MATRIX KEYPAD */ - GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, - GPIO101_KP_MKIN_1, - GPIO102_KP_MKIN_2, - GPIO97_KP_MKIN_3, - GPIO98_KP_MKIN_4, - GPIO99_KP_MKIN_5, - GPIO91_KP_MKIN_6, - GPIO13_KP_MKIN_7, - GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, - GPIO104_KP_MKOUT_1, - GPIO105_KP_MKOUT_2, - GPIO106_KP_MKOUT_3, - GPIO107_KP_MKOUT_4, - GPIO108_KP_MKOUT_5, - GPIO96_KP_MKOUT_6, - GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ - - /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - - /* Quick Capture Interface */ - GPIO84_CIF_FV, - GPIO85_CIF_LV, - GPIO53_CIF_MCLK, - GPIO54_CIF_PCLK, - GPIO81_CIF_DD_0, - GPIO55_CIF_DD_1, - GPIO51_CIF_DD_2, - GPIO50_CIF_DD_3, - GPIO52_CIF_DD_4, - GPIO48_CIF_DD_5, - GPIO17_CIF_DD_6, - GPIO12_CIF_DD_7, - - /* I2C */ - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, - - /* GSM */ - GPIO14_GPIO | WAKEUP_ON_EDGE_BOTH, /* GSM host wake up */ - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO39_FFUART_TXD, - GPIO41_FFUART_RTS, - - /* MISC. */ - GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* external power detect */ - GPIO15_GPIO | WAKEUP_ON_EDGE_BOTH, /* silent switch */ - GPIO116_GPIO, /* headphone detect */ - GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ -}; - -/****************************************************************************** - * SD/MMC card controller - ******************************************************************************/ -static struct pxamci_platform_data treo680_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .gpio_card_detect = GPIO_NR_TREO680_SD_DETECT_N, - .gpio_card_ro = GPIO_NR_TREO680_SD_READONLY, - .gpio_power = GPIO_NR_TREO680_SD_POWER, -}; - -/****************************************************************************** - * GPIO keyboard - ******************************************************************************/ -static unsigned int treo680_matrix_keys[] = { - KEY(0, 0, KEY_F8), /* Red/Off/Power */ - KEY(0, 1, KEY_LEFT), - KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ - KEY(0, 3, KEY_L), - KEY(0, 4, KEY_A), - KEY(0, 5, KEY_Q), - KEY(0, 6, KEY_P), - - KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ - KEY(1, 1, KEY_RIGHT), - KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ - KEY(1, 3, KEY_Z), - KEY(1, 4, KEY_S), - KEY(1, 5, KEY_W), - - KEY(2, 0, KEY_F1), /* Phone */ - KEY(2, 1, KEY_UP), - KEY(2, 2, KEY_0), - KEY(2, 3, KEY_X), - KEY(2, 4, KEY_D), - KEY(2, 5, KEY_E), - - KEY(3, 0, KEY_F10), /* Calendar */ - KEY(3, 1, KEY_DOWN), - KEY(3, 2, KEY_SPACE), - KEY(3, 3, KEY_C), - KEY(3, 4, KEY_F), - KEY(3, 5, KEY_R), - - KEY(4, 0, KEY_F12), /* Mail */ - KEY(4, 1, KEY_KPENTER), - KEY(4, 2, KEY_RIGHTALT), /* Alt */ - KEY(4, 3, KEY_V), - KEY(4, 4, KEY_G), - KEY(4, 5, KEY_T), - - KEY(5, 0, KEY_F9), /* Home */ - KEY(5, 1, KEY_PAGEUP), /* Side up */ - KEY(5, 2, KEY_DOT), - KEY(5, 3, KEY_B), - KEY(5, 4, KEY_H), - KEY(5, 5, KEY_Y), - - KEY(6, 0, KEY_TAB), /* Side Activate */ - KEY(6, 1, KEY_PAGEDOWN), /* Side down */ - KEY(6, 2, KEY_ENTER), - KEY(6, 3, KEY_N), - KEY(6, 4, KEY_J), - KEY(6, 5, KEY_U), - - KEY(7, 0, KEY_F6), /* Green/Call */ - KEY(7, 1, KEY_O), - KEY(7, 2, KEY_BACKSPACE), - KEY(7, 3, KEY_M), - KEY(7, 4, KEY_K), - KEY(7, 5, KEY_I), -}; - -static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { - .matrix_key_rows = 8, - .matrix_key_cols = 7, - .matrix_key_map = treo680_matrix_keys, - .matrix_key_map_size = ARRAY_SIZE(treo680_matrix_keys), - .direct_key_map = { KEY_CONNECT }, - .direct_key_num = 1, - - .debounce_interval = 30, -}; - -/****************************************************************************** - * aSoC audio - ******************************************************************************/ - -static pxa2xx_audio_ops_t treo680_ac97_pdata = { - .reset_gpio = 95, -}; - -/****************************************************************************** - * Backlight - ******************************************************************************/ -static int treo680_backlight_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER"); - if (ret) - goto err; - ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0); - if (ret) - goto err2; - - return 0; - -err2: - gpio_free(GPIO_NR_TREO680_BL_POWER); -err: - return ret; -} - -static int treo680_backlight_notify(int brightness) -{ - gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness); - return TREO680_MAX_INTENSITY - brightness; -}; - -static void treo680_backlight_exit(struct device *dev) -{ - gpio_free(GPIO_NR_TREO680_BL_POWER); -} - -static struct platform_pwm_backlight_data treo680_backlight_data = { - .pwm_id = 0, - .max_brightness = TREO680_MAX_INTENSITY, - .dft_brightness = TREO680_DEFAULT_INTENSITY, - .pwm_period_ns = TREO680_PERIOD_NS, - .init = treo680_backlight_init, - .notify = treo680_backlight_notify, - .exit = treo680_backlight_exit, -}; - -static struct platform_device treo680_backlight = { - .name = "pwm-backlight", - .dev = { - .parent = &pxa27x_device_pwm0.dev, - .platform_data = &treo680_backlight_data, - }, -}; - -/****************************************************************************** - * IrDA - ******************************************************************************/ -static struct pxaficp_platform_data treo680_ficp_info = { - .gpio_pwdown = GPIO_NR_TREO680_IR_EN, - .transceiver_cap = IR_SIRMODE | IR_OFF, -}; - -/****************************************************************************** - * UDC - ******************************************************************************/ -static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = { - .gpio_vbus = GPIO_NR_TREO680_USB_DETECT, - .gpio_vbus_inverted = 1, - .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP, -}; - - -/****************************************************************************** - * USB host - ******************************************************************************/ -static struct pxaohci_platform_data treo680_ohci_info = { - .port_mode = PMM_PERPORT_MODE, - .flags = ENABLE_PORT1 | ENABLE_PORT3, - .power_budget = 0, -}; - -/****************************************************************************** - * Power supply - ******************************************************************************/ -static int power_supply_init(struct device *dev) -{ - int ret; - - ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC"); - if (ret) - goto err1; - ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT); - if (ret) - goto err2; - - return 0; - -err2: - gpio_free(GPIO_NR_TREO680_POWER_DETECT); -err1: - return ret; -} - -static int treo680_is_ac_online(void) -{ - return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT); -} - -static void power_supply_exit(struct device *dev) -{ - gpio_free(GPIO_NR_TREO680_POWER_DETECT); -} - -static char *treo680_supplicants[] = { - "main-battery", -}; - -static struct pda_power_pdata power_supply_info = { - .init = power_supply_init, - .is_ac_online = treo680_is_ac_online, - .exit = power_supply_exit, - .supplied_to = treo680_supplicants, - .num_supplicants = ARRAY_SIZE(treo680_supplicants), -}; - -static struct platform_device power_supply = { - .name = "pda-power", - .id = -1, - .dev = { - .platform_data = &power_supply_info, - }, -}; - -/****************************************************************************** - * Vibra and LEDs - ******************************************************************************/ -static struct gpio_led gpio_leds[] = { - { - .name = "treo680:vibra:vibra", - .default_trigger = "none", - .gpio = GPIO_NR_TREO680_VIBRATE_EN, - }, - { - .name = "treo680:green:led", - .default_trigger = "mmc0", - .gpio = GPIO_NR_TREO680_GREEN_LED, - }, - { - .name = "treo680:keybbl:keybbl", - .default_trigger = "none", - .gpio = GPIO_NR_TREO680_KEYB_BL, - }, -}; - -static struct gpio_led_platform_data gpio_led_info = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device treo680_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &gpio_led_info, - } -}; - - -/****************************************************************************** - * Framebuffer - ******************************************************************************/ -/* TODO: add support for 324x324 */ -static struct pxafb_mode_info treo680_lcd_modes[] = { -{ - .pixclock = 86538, - .xres = 320, - .yres = 320, - .bpp = 16, - - .left_margin = 20, - .right_margin = 8, - .upper_margin = 8, - .lower_margin = 5, - - .hsync_len = 4, - .vsync_len = 1, -}, -}; - -static void treo680_lcd_power(int on, struct fb_var_screeninfo *info) -{ - gpio_set_value(GPIO_NR_TREO680_BL_POWER, on); -} - -static struct pxafb_mach_info treo680_lcd_screen = { - .modes = treo680_lcd_modes, - .num_modes = ARRAY_SIZE(treo680_lcd_modes), - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, -}; - -/****************************************************************************** - * Power management - standby - ******************************************************************************/ -static void __init treo680_pm_init(void) -{ - static u32 resume[] = { - 0xe3a00101, /* mov r0, #0x40000000 */ - 0xe380060f, /* orr r0, r0, #0x00f00000 */ - 0xe590f008, /* ldr pc, [r0, #0x08] */ - }; - - /* this is where the bootloader jumps */ - memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume)); -} - -/****************************************************************************** - * Machine init - ******************************************************************************/ -static struct platform_device *devices[] __initdata = { - &treo680_backlight, - &treo680_leds, - &power_supply, -}; - -/* setup udc GPIOs initial state */ -static void __init treo680_udc_init(void) -{ - if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) { - gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1); - gpio_free(GPIO_NR_TREO680_USB_PULLUP); - } -} - -static void __init treo680_lcd_power_init(void) -{ - int ret; - - ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER"); - if (ret) { - pr_err("Treo680: LCD power GPIO request failed!\n"); - return; - } - - ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0); - if (ret) { - pr_err("Treo680: setting LCD power GPIO direction failed!\n"); - gpio_free(GPIO_NR_TREO680_LCD_POWER); - return; - } - - treo680_lcd_screen.pxafb_lcd_power = treo680_lcd_power; -} - -static void __init treo680_init(void) -{ - treo680_pm_init(); - pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); - pxa_set_keypad_info(&treo680_keypad_platform_data); - treo680_lcd_power_init(); - set_pxa_fb_info(&treo680_lcd_screen); - pxa_set_mci_info(&treo680_mci_platform_data); - treo680_udc_init(); - pxa_set_udc_info(&treo680_udc_info); - pxa_set_ac97_info(&treo680_ac97_pdata); - pxa_set_ficp_info(&treo680_ficp_info); - pxa_set_ohci_info(&treo680_ohci_info); - - platform_add_devices(devices, ARRAY_SIZE(devices)); -} - -MACHINE_START(TREO680, "Palm Treo 680") - .phys_io = TREO680_PHYS_IO_START, - .io_pg_offst = io_p2v(0x40000000), - .boot_params = 0xa0000100, - .map_io = pxa_map_io, - .init_irq = pxa27x_init_irq, - .timer = &pxa_timer, - .init_machine = treo680_init, -MACHINE_END -- cgit v1.2.3-70-g09d2 From d0a92fd3b84bf707f6b32f31d0f09d2b7bb1ad67 Mon Sep 17 00:00:00 2001 From: Tomáš Čech Date: Fri, 11 Sep 2009 13:57:02 +0200 Subject: [ARM] pxa/treo: add Palm Centro 685 support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Tomáš Čech Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 11 ++ arch/arm/mach-pxa/include/mach/palmtreo.h | 7 ++ arch/arm/mach-pxa/palmtreo.c | 161 ++++++++++++++++++++++++++++++ arch/arm/mm/mmu.c | 2 +- 4 files changed, 180 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index ce6519c000a..28f0260777a 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -425,6 +425,17 @@ config PALM_TREO bool depends on ARCH_PXA_PALM +config MACH_CENTRO + bool "Palm Centro 685 (GSM)" + default y + depends on ARCH_PXA_PALM + select PXA27x + select IWMMXT + select PALM_TREO + help + Say Y here if you intend to run this kernel on Palm Centro 685 (GSM) + smartphone. + config MACH_TREO680 bool "Palm Treo 680" default y diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h index 8cb0bca7f70..2d3f14e3be2 100644 --- a/arch/arm/mach-pxa/include/mach/palmtreo.h +++ b/arch/arm/mach-pxa/include/mach/palmtreo.h @@ -3,6 +3,7 @@ * * currently supported: * Palm Treo 680 (GSM) + * Palm Centro 685 (GSM) * * Author: Tomas Cech * @@ -45,6 +46,12 @@ #define GPIO_NR_TREO680_BT_EN 43 #endif /* CONFIG_MACH_TREO680 */ +/* Centro685 specific GPIOs */ +#define GPIO_NR_CENTRO_SD_POWER 21 +#define GPIO_NR_CENTRO_VIBRATE_EN 22 +#define GPIO_NR_CENTRO_KEYB_BL 33 +#define GPIO_NR_CENTRO_BT_EN 80 + /* Various addresses */ #define TREO_PHYS_RAM_START 0xa0000000 #define TREO_PHYS_IO_START 0x40000000 diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index 5e66028d291..c071b60ebed 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -3,6 +3,7 @@ * * currently supported: * Palm Treo 680 (GSM) + * Palm Centro 685 (GSM) * * Author: Tomas Cech * @@ -160,6 +161,21 @@ static unsigned long treo680_pin_config[] __initdata = { }; #endif /* CONFIG_MACH_TREO680 */ +#ifdef CONFIG_MACH_CENTRO +static unsigned long centro685_pin_config[] __initdata = { + /* Bluetooth attached to BT UART*/ + MFP_CFG_OUT(GPIO80, AF0, DRIVE_LOW), /* power: LOW = off */ + GPIO42_BTUART_RXD, + GPIO43_BTUART_TXD, + GPIO44_BTUART_CTS, + GPIO45_BTUART_RTS, + + /* MATRIX KEYPAD - different wake up source */ + GPIO100_KP_MKIN_0, + GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, +}; +#endif /* CONFIG_MACH_CENTRO */ + /****************************************************************************** * SD/MMC card controller ******************************************************************************/ @@ -172,6 +188,16 @@ static struct pxamci_platform_data treo680_mci_platform_data = { }; #endif /* CONFIG_MACH_TREO680 */ +#ifdef CONFIG_MACH_CENTRO +static struct pxamci_platform_data centro_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, + .gpio_card_ro = -1, + .gpio_power = GPIO_NR_CENTRO_SD_POWER, + .gpio_power_invert = 1, +}; +#endif /* CONFIG_MACH_CENTRO */ + /****************************************************************************** * GPIO keyboard ******************************************************************************/ @@ -247,6 +273,78 @@ static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { }; #endif /* CONFIG_MACH_TREO680 */ +#ifdef CONFIG_MACH_CENTRO +static unsigned int centro_matrix_keys[] = { + KEY(0, 0, KEY_F9), /* Home */ + KEY(0, 1, KEY_LEFT), + KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ + KEY(0, 3, KEY_L), + KEY(0, 4, KEY_A), + KEY(0, 5, KEY_Q), + KEY(0, 6, KEY_P), + + KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ + KEY(1, 1, KEY_RIGHT), + KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ + KEY(1, 3, KEY_Z), + KEY(1, 4, KEY_S), + KEY(1, 5, KEY_W), + + KEY(2, 0, KEY_F1), /* Phone */ + KEY(2, 1, KEY_UP), + KEY(2, 2, KEY_0), + KEY(2, 3, KEY_X), + KEY(2, 4, KEY_D), + KEY(2, 5, KEY_E), + + KEY(3, 0, KEY_F10), /* Calendar */ + KEY(3, 1, KEY_DOWN), + KEY(3, 2, KEY_SPACE), + KEY(3, 3, KEY_C), + KEY(3, 4, KEY_F), + KEY(3, 5, KEY_R), + + KEY(4, 0, KEY_F12), /* Mail */ + KEY(4, 1, KEY_KPENTER), + KEY(4, 2, KEY_RIGHTALT), /* Alt */ + KEY(4, 3, KEY_V), + KEY(4, 4, KEY_G), + KEY(4, 5, KEY_T), + + KEY(5, 0, KEY_F8), /* Red/Off/Power */ + KEY(5, 1, KEY_PAGEUP), /* Side up */ + KEY(5, 2, KEY_DOT), + KEY(5, 3, KEY_B), + KEY(5, 4, KEY_H), + KEY(5, 5, KEY_Y), + + KEY(6, 0, KEY_TAB), /* Side Activate */ + KEY(6, 1, KEY_PAGEDOWN), /* Side down */ + KEY(6, 2, KEY_ENTER), + KEY(6, 3, KEY_N), + KEY(6, 4, KEY_J), + KEY(6, 5, KEY_U), + + KEY(7, 0, KEY_F6), /* Green/Call */ + KEY(7, 1, KEY_O), + KEY(7, 2, KEY_BACKSPACE), + KEY(7, 3, KEY_M), + KEY(7, 4, KEY_K), + KEY(7, 5, KEY_I), +}; + +static struct pxa27x_keypad_platform_data centro_keypad_platform_data = { + .matrix_key_rows = 8, + .matrix_key_cols = 7, + .matrix_key_map = centro_matrix_keys, + .matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys), + .direct_key_map = { KEY_CONNECT }, + .direct_key_num = 1, + + .debounce_interval = 30, +}; +#endif /* CONFIG_MACH_CENTRO */ + /****************************************************************************** * aSoC audio ******************************************************************************/ @@ -423,6 +521,40 @@ static struct platform_device treo680_leds = { }; #endif /* CONFIG_MACH_TREO680 */ +#ifdef CONFIG_MACH_CENTRO +static struct gpio_led centro_gpio_leds[] = { + { + .name = "centro:vibra:vibra", + .default_trigger = "none", + .gpio = GPIO_NR_CENTRO_VIBRATE_EN, + }, + { + .name = "centro:green:led", + .default_trigger = "mmc0", + .gpio = GPIO_NR_TREO_GREEN_LED, + }, + { + .name = "centro:white:keybbl", + .default_trigger = "none", + .active_low = 1, + .gpio = GPIO_NR_CENTRO_KEYB_BL, + }, +}; + +static struct gpio_led_platform_data centro_gpio_led_info = { + .leds = centro_gpio_leds, + .num_leds = ARRAY_SIZE(centro_gpio_leds), +}; + +static struct platform_device centro_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = ¢ro_gpio_led_info, + } +}; +#endif /* CONFIG_MACH_CENTRO */ + /****************************************************************************** * Framebuffer ******************************************************************************/ @@ -484,6 +616,12 @@ static struct platform_device *treo680_devices[] __initdata = { }; #endif /* CONFIG_MACH_TREO680 */ +#ifdef CONFIG_MACH_CENTRO +static struct platform_device *centro_devices[] __initdata = { + ¢ro_leds, +}; +#endif /* CONFIG_MACH_CENTRO */ + /* setup udc GPIOs initial state */ static void __init treo_udc_init(void) { @@ -549,3 +687,26 @@ MACHINE_START(TREO680, "Palm Treo 680") .init_machine = treo680_init, MACHINE_END #endif /* CONFIG_MACH_TREO680 */ + +#ifdef CONFIG_MACH_CENTRO +static void __init centro_init(void) +{ + treo_init(); + pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); + pxa_set_mci_info(¢ro_mci_platform_data); + + pxa_set_keypad_info(¢ro_keypad_platform_data); + + platform_add_devices(ARRAY_AND_SIZE(centro_devices)); +} + +MACHINE_START(CENTRO, "Palm Centro 685") + .phys_io = TREO_PHYS_IO_START, + .io_pg_offst = io_p2v(0x40000000), + .boot_params = 0xa0000100, + .map_io = pxa_map_io, + .init_irq = pxa27x_init_irq, + .timer = &pxa_timer, + .init_machine = centro_init, +MACHINE_END +#endif /* CONFIG_MACH_CENTRO */ diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index ea67be0223a..3e8556b16a9 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -881,7 +881,7 @@ void __init reserve_node_zero(pg_data_t *pgdat) BOOTMEM_EXCLUSIVE); } - if (machine_is_treo680()) { + if (machine_is_treo680() || machine_is_centro()) { reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, BOOTMEM_EXCLUSIVE); reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, -- cgit v1.2.3-70-g09d2 From de0710aa81a4663feb4a039973f96cb7a7661496 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 12 Oct 2009 09:32:07 +0800 Subject: [ARM] pxa: re-order platforms in Kconfig and Makefile Due to the naming mess in Kconfig and Makefile, I'd like to get them sorted in the following order: 1. By category: Intel/Marvell Dev Platforms, followed by 3rd party platforms, followed by end-user products (this is to ensure the commonly referenced platforms will appear first) 2. By vendor name in alphabetic within each category (this is to ensure code reuse and similar platforms can be grouped as much as possible) VENDOR BOARD Intel/Marvell Lubbock Intel/Marvell Mainstone Intel/Marvell Zylonite Intel/Marvell Littleton Intel/Marvell TavorEVB Intel/Marvell SAAR Accelent IDP Arcom/Eurotech VIPER Community Balloon3 Cogent CSB726 CompuLab EM_X270 CompuLab EXEDA CompuLab ARMCORE CompuLab CM_X300 Gumstix Gumstix Intel Research MOTE2 Intel research Stargate2 Iskratel XCEP Keith and Koep Trizeps4 LogicPD LPD270 Phytec PCM027 Toradex Colibri HP HX4700 HP H5000 HTC Himalaya HTC Magician Mitac MioA701 Motorola EZX NEC MP900C Palm Palm PDA Palm Palm GSM Sharp Zaurus Toshiba E-Series Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 566 +++++++++++++++++++++++---------------------- arch/arm/mach-pxa/Makefile | 93 ++++---- 2 files changed, 333 insertions(+), 326 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 28f0260777a..e62572dc2d7 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -31,216 +31,144 @@ endmenu endif -config ARCH_GUMSTIX - bool "Gumstix XScale 255 boards" - select PXA25x - help - Say Y here if you intend to run this kernel on - Basix, Connex, ws-200ax, ws-400ax systems - -choice - prompt "Gumstix Carrier/Expansion Board" - depends on ARCH_GUMSTIX - -config GUMSTIX_AM200EPD - bool "Enable AM200EPD board support" - -config GUMSTIX_AM300EPD - bool "Enable AM300EPD board support" - -endchoice - -config MACH_INTELMOTE2 - bool "Intel Mote 2 Platform" - select PXA27x - select IWMMXT - select PXA_HAVE_BOARD_IRQS - -config MACH_STARGATE2 - bool "Intel Stargate 2 Platform" - select PXA27x - select IWMMXT - select PXA_HAVE_BOARD_IRQS +comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config ARCH_LUBBOCK - bool "Intel DBPXA250 Development Platform" + bool "Intel DBPXA250 Development Platform (aka Lubbock)" select PXA25x select SA1111 select PXA_HAVE_BOARD_IRQS -config MACH_LOGICPD_PXA270 - bool "LogicPD PXA270 Card Engine Development Platform" +config MACH_MAINSTONE + bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" select PXA27x select HAVE_PWM select PXA_HAVE_BOARD_IRQS -config MACH_MAINSTONE - bool "Intel HCDDBBVA0 Development Platform" - select PXA27x +config MACH_ZYLONITE + bool "PXA3xx Development Platform (aka Zylonite)" + select PXA3xx + select PXA_SSP select HAVE_PWM select PXA_HAVE_BOARD_IRQS -config MACH_MP900C - bool "Nec Mobilepro 900/c" +config MACH_LITTLETON + bool "PXA3xx Form Factor Platform (aka Littleton)" + select PXA3xx + select PXA_SSP + +config MACH_TAVOREVB + bool "PXA930 Evaluation Board (aka TavorEVB)" + select PXA3xx + select CPU_PXA930 + +config MACH_SAAR + bool "PXA930 Handheld Platform (aka SAAR)" + select PXA3xx + select CPU_PXA930 + +comment "Third Party Dev Platforms (sorted by vendor name)" + +config ARCH_PXA_IDP + bool "Accelent Xscale IDP" select PXA25x +config ARCH_VIPER + bool "Arcom/Eurotech VIPER SBC" + select PXA25x + select ISA + select I2C_GPIO + select HAVE_PWM + select PXA_HAVE_BOARD_IRQS + select PXA_HAVE_ISA_IRQS + config MACH_BALLOON3 bool "Balloon 3 board" select PXA27x select IWMMXT select PXA_HAVE_BOARD_IRQS -config ARCH_PXA_IDP - bool "Accelent Xscale IDP" - select PXA25x - -config PXA_SHARPSL - bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" - select SHARP_SCOOP - select SHARP_PARAM +config MACH_CSB726 + bool "Enable Cogent CSB726 System On a Module" + select PXA27x + select IWMMXT help - Say Y here if you intend to run this kernel on a - Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), - SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), - SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) - handheld computer. - -config SHARPSL_PM - bool - select APM_EMULATION + Say Y here if you intend to run this kernel on a Cogent + CSB726 System On Module. -config CORGI_SSP_DEPRECATED - bool - select PXA_SSP - help - This option will include corgi_ssp.c and corgi_lcd.c - that corgi_ts.c and other legacy drivers (corgi_bl.c - and sharpsl_pm.c) may depend on. +config CSB726_CSB701 + bool "Enable support for CSB701 baseboard" + depends on MACH_CSB726 -config MACH_POODLE - bool "Enable Sharp SL-5600 (Poodle) Support" - depends on PXA_SHARPSL +config MACH_ARMCORE + bool "CompuLab CM-X255/CM-X270 modules" + select PXA27x + select IWMMXT select PXA25x - select SHARP_LOCOMO select PXA_SSP -config MACH_CORGI - bool "Enable Sharp SL-C700 (Corgi) Support" - depends on PXA_SHARPSL - select PXA25x - select PXA_SHARP_C7xx - -config MACH_SHEPHERD - bool "Enable Sharp SL-C750 (Shepherd) Support" - depends on PXA_SHARPSL - select PXA25x - select PXA_SHARP_C7xx - -config MACH_HUSKY - bool "Enable Sharp SL-C760 (Husky) Support" - depends on PXA_SHARPSL - select PXA25x - select PXA_SHARP_C7xx - -config MACH_AKITA - bool "Enable Sharp SL-1000 (Akita) Support" - depends on PXA_SHARPSL - select PXA27x - select PXA_SHARP_Cxx00 - select MACH_SPITZ - select I2C - select I2C_PXA - -config MACH_SPITZ - bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" - depends on PXA_SHARPSL +config MACH_EM_X270 + bool "CompuLab EM-x270 platform" select PXA27x - select PXA_SHARP_Cxx00 -config MACH_BORZOI - bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" - depends on PXA_SHARPSL +config MACH_EXEDA + bool "CompuLab eXeda platform" select PXA27x - select PXA_SHARP_Cxx00 -config MACH_TOSA - bool "Enable Sharp SL-6000x (Tosa) Support" - depends on PXA_SHARPSL - select PXA25x - select PXA_HAVE_BOARD_IRQS +config MACH_CM_X300 + bool "CompuLab CM-X300 modules" + select PXA3xx + select CPU_PXA300 -config ARCH_VIPER - bool "Arcom/Eurotech VIPER SBC" +config ARCH_GUMSTIX + bool "Gumstix XScale 255 boards" select PXA25x - select ISA - select I2C_GPIO - select HAVE_PWM - select PXA_HAVE_BOARD_IRQS - select PXA_HAVE_ISA_IRQS + help + Say Y here if you intend to run this kernel on + Basix, Connex, ws-200ax, ws-400ax systems -config ARCH_PXA_ESERIES - bool "PXA based Toshiba e-series PDAs" - select PXA25x - select PXA_HAVE_BOARD_IRQS +choice + prompt "Gumstix Carrier/Expansion Board" + depends on ARCH_GUMSTIX -config MACH_E330 - bool "Toshiba e330" - default y - depends on ARCH_PXA_ESERIES - help - Say Y here if you intend to run this kernel on a Toshiba - e330 family PDA. +config GUMSTIX_AM200EPD + bool "Enable AM200EPD board support" -config MACH_E350 - bool "Toshiba e350" - default y - depends on ARCH_PXA_ESERIES - help - Say Y here if you intend to run this kernel on a Toshiba - e350 family PDA. +config GUMSTIX_AM300EPD + bool "Enable AM300EPD board support" -config MACH_E740 - bool "Toshiba e740" - default y - depends on ARCH_PXA_ESERIES - select FB_W100 - help - Say Y here if you intend to run this kernel on a Toshiba - e740 family PDA. +endchoice -config MACH_E750 - bool "Toshiba e750" - default y - depends on ARCH_PXA_ESERIES - select FB_W100 - help - Say Y here if you intend to run this kernel on a Toshiba - e750 family PDA. +config MACH_INTELMOTE2 + bool "Intel Mote 2 Platform" + select PXA27x + select IWMMXT + select PXA_HAVE_BOARD_IRQS -config MACH_E400 - bool "Toshiba e400" - default y - depends on ARCH_PXA_ESERIES - help - Say Y here if you intend to run this kernel on a Toshiba - e400 family PDA. +config MACH_STARGATE2 + bool "Intel Stargate 2 Platform" + select PXA27x + select IWMMXT + select PXA_HAVE_BOARD_IRQS -config MACH_E800 - bool "Toshiba e800" - default y - depends on ARCH_PXA_ESERIES - select FB_W100 +config MACH_XCEP + bool "Iskratel Electronics XCEP" + select PXA25x + select MTD + select MTD_PARTITIONS + select MTD_PHYSMAP + select MTD_CFI_INTELEXT + select MTD_CFI + select MTD_CHAR + select SMC91X + select PXA_SSP help - Say Y here if you intend to run this kernel on a Toshiba - e800 family PDA. + PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. + Tuned for usage in Libera instruments for particle accelerators. config TRIZEPS_PXA bool "PXA based Keith und Koep Trizeps DIMM-Modules" -config MACH_H5000 - bool "HP iPAQ h5000" - select PXA25x - config MACH_TRIZEPS4 bool "Keith und Koep Trizeps4 DIMM-Module" depends on TRIZEPS_PXA @@ -274,62 +202,55 @@ config TRIZEPS_PCMCIA help Enable PCMCIA support for Trizeps modules -config MACH_EM_X270 - bool "CompuLab EM-x270 platform" - select PXA27x - -config MACH_EXEDA - bool "CompuLab eXeda platform" +config MACH_LOGICPD_PXA270 + bool "LogicPD PXA270 Card Engine Development Platform" select PXA27x + select HAVE_PWM + select PXA_HAVE_BOARD_IRQS -config MACH_COLIBRI - bool "Toradex Colibri PXA270" +config MACH_PCM027 + bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" select PXA27x + select IWMMXT + select PXA_SSP + select PXA_HAVE_BOARD_IRQS -config MACH_COLIBRI300 - bool "Toradex Colibri PXA300/310" - select PXA3xx - select CPU_PXA300 +config MACH_PCM990_BASEBOARD + bool "PHYTEC PCM-990 development board" + select HAVE_PWM + depends on MACH_PCM027 -config MACH_COLIBRI320 - bool "Toradex Colibri PXA320" - select PXA3xx - select CPU_PXA320 +choice + prompt "display on pcm990" + depends on MACH_PCM990_BASEBOARD -config MACH_ZYLONITE - bool "PXA3xx Development Platform (aka Zylonite)" - select PXA3xx - select PXA_SSP - select HAVE_PWM - select PXA_HAVE_BOARD_IRQS +config PCM990_DISPLAY_SHARP + bool "sharp lq084v1dg21 stn display" -config MACH_LITTLETON - bool "PXA3xx Form Factor Platform (aka Littleton)" - select PXA3xx - select PXA_SSP +config PCM990_DISPLAY_NEC + bool "nec nl6448bc20_18d tft display" -config MACH_TAVOREVB - bool "PXA930 Evaluation Board (aka TavorEVB)" - select PXA3xx - select CPU_PXA930 +config PCM990_DISPLAY_NONE + bool "no display" -config MACH_SAAR - bool "PXA930 Handheld Platform (aka SAAR)" - select PXA3xx - select CPU_PXA930 +endchoice -config MACH_ARMCORE - bool "CompuLab CM-X255/CM-X270 modules" +config MACH_COLIBRI + bool "Toradex Colibri PXA270" select PXA27x - select IWMMXT - select PXA25x - select PXA_SSP -config MACH_CM_X300 - bool "CompuLab CM-X300 modules" +config MACH_COLIBRI300 + bool "Toradex Colibri PXA300/310" select PXA3xx select CPU_PXA300 +config MACH_COLIBRI320 + bool "Toradex Colibri PXA320" + select PXA3xx + select CPU_PXA320 + +comment "End-user Products (sorted by vendor name)" + config MACH_H4700 bool "HP iPAQ hx4700" select PXA27x @@ -338,6 +259,15 @@ config MACH_H4700 select HAVE_PWM select PXA_HAVE_BOARD_IRQS +config MACH_H5000 + bool "HP iPAQ h5000" + select PXA25x + +config MACH_HIMALAYA + bool "HTC Himalaya Support" + select CPU_PXA26x + select FB_W100 + config MACH_MAGICIAN bool "Enable HTC Magician Support" select PXA27x @@ -346,11 +276,6 @@ config MACH_MAGICIAN select HAVE_PWM select PXA_HAVE_BOARD_IRQS -config MACH_HIMALAYA - bool "HTC Himalaya Support" - select CPU_PXA26x - select FB_W100 - config MACH_MIOA701 bool "Mitac Mio A701 Support" select PXA27x @@ -362,13 +287,47 @@ config MACH_MIOA701 MIO A701. Currently there is only basic support for this PDA. -config MACH_PCM027 - bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" +config PXA_EZX + bool "Motorola EZX Platform" select PXA27x select IWMMXT - select PXA_SSP + select HAVE_PWM select PXA_HAVE_BOARD_IRQS +config MACH_EZX_A780 + bool "Motorola EZX A780" + default y + depends on PXA_EZX + +config MACH_EZX_E680 + bool "Motorola EZX E680" + default y + depends on PXA_EZX + +config MACH_EZX_A1200 + bool "Motorola EZX A1200" + default y + depends on PXA_EZX + +config MACH_EZX_A910 + bool "Motorola EZX A910" + default y + depends on PXA_EZX + +config MACH_EZX_E6 + bool "Motorola EZX E6" + default y + depends on PXA_EZX + +config MACH_EZX_E2 + bool "Motorola EZX E2" + default y + depends on PXA_EZX + +config MACH_MP900C + bool "Nec Mobilepro 900/c" + select PXA25x + config ARCH_PXA_PALM bool "PXA based Palm PDAs" select HAVE_PWM @@ -421,6 +380,16 @@ config MACH_PALMZ72 Say Y here if you intend to run this kernel on Palm Zire 72 handheld computer. +config MACH_PALMLD + bool "Palm LifeDrive" + default y + depends on ARCH_PXA_PALM + select PXA27x + select IWMMXT + help + Say Y here if you intend to run this kernel on a Palm LifeDrive + handheld computer. + config PALM_TREO bool depends on ARCH_PXA_PALM @@ -447,99 +416,136 @@ config MACH_TREO680 Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. -config MACH_PALMLD - bool "Palm LifeDrive" - default y - depends on ARCH_PXA_PALM - select PXA27x - select IWMMXT +config PXA_SHARPSL + bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" + select SHARP_SCOOP + select SHARP_PARAM help - Say Y here if you intend to run this kernel on a Palm LifeDrive + Say Y here if you intend to run this kernel on a + Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), + SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), + SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) handheld computer. -config MACH_PCM990_BASEBOARD - bool "PHYTEC PCM-990 development board" - select HAVE_PWM - depends on MACH_PCM027 +config SHARPSL_PM + bool + select APM_EMULATION -choice - prompt "display on pcm990" - depends on MACH_PCM990_BASEBOARD +config CORGI_SSP_DEPRECATED + bool + select PXA_SSP + help + This option will include corgi_ssp.c and corgi_lcd.c + that corgi_ts.c and other legacy drivers (corgi_bl.c + and sharpsl_pm.c) may depend on. -config PCM990_DISPLAY_SHARP - bool "sharp lq084v1dg21 stn display" +config MACH_POODLE + bool "Enable Sharp SL-5600 (Poodle) Support" + depends on PXA_SHARPSL + select PXA25x + select SHARP_LOCOMO + select PXA_SSP -config PCM990_DISPLAY_NEC - bool "nec nl6448bc20_18d tft display" +config MACH_CORGI + bool "Enable Sharp SL-C700 (Corgi) Support" + depends on PXA_SHARPSL + select PXA25x + select PXA_SHARP_C7xx -config PCM990_DISPLAY_NONE - bool "no display" +config MACH_SHEPHERD + bool "Enable Sharp SL-C750 (Shepherd) Support" + depends on PXA_SHARPSL + select PXA25x + select PXA_SHARP_C7xx -endchoice +config MACH_HUSKY + bool "Enable Sharp SL-C760 (Husky) Support" + depends on PXA_SHARPSL + select PXA25x + select PXA_SHARP_C7xx -config MACH_CSB726 - bool "Enable Cogent CSB726 System On a Module" +config MACH_AKITA + bool "Enable Sharp SL-1000 (Akita) Support" + depends on PXA_SHARPSL select PXA27x - select IWMMXT - help - Say Y here if you intend to run this kernel on a Cogent - CSB726 System On Module. + select PXA_SHARP_Cxx00 + select MACH_SPITZ + select I2C + select I2C_PXA -config CSB726_CSB701 - bool "Enable supprot for CSB701 baseboard" - depends on MACH_CSB726 +config MACH_SPITZ + bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" + depends on PXA_SHARPSL + select PXA27x + select PXA_SHARP_Cxx00 -config PXA_EZX - bool "Motorola EZX Platform" +config MACH_BORZOI + bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" + depends on PXA_SHARPSL select PXA27x - select IWMMXT - select HAVE_PWM + select PXA_SHARP_Cxx00 + +config MACH_TOSA + bool "Enable Sharp SL-6000x (Tosa) Support" + depends on PXA_SHARPSL + select PXA25x select PXA_HAVE_BOARD_IRQS -config MACH_EZX_A780 - bool "Motorola EZX A780" - default y - depends on PXA_EZX +config ARCH_PXA_ESERIES + bool "PXA based Toshiba e-series PDAs" + select PXA25x + select PXA_HAVE_BOARD_IRQS -config MACH_EZX_E680 - bool "Motorola EZX E680" +config MACH_E330 + bool "Toshiba e330" default y - depends on PXA_EZX + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e330 family PDA. -config MACH_EZX_A1200 - bool "Motorola EZX A1200" +config MACH_E350 + bool "Toshiba e350" default y - depends on PXA_EZX + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e350 family PDA. -config MACH_EZX_A910 - bool "Motorola EZX A910" +config MACH_E740 + bool "Toshiba e740" default y - depends on PXA_EZX + depends on ARCH_PXA_ESERIES + select FB_W100 + help + Say Y here if you intend to run this kernel on a Toshiba + e740 family PDA. -config MACH_EZX_E6 - bool "Motorola EZX E6" +config MACH_E750 + bool "Toshiba e750" default y - depends on PXA_EZX + depends on ARCH_PXA_ESERIES + select FB_W100 + help + Say Y here if you intend to run this kernel on a Toshiba + e750 family PDA. -config MACH_EZX_E2 - bool "Motorola EZX E2" +config MACH_E400 + bool "Toshiba e400" default y - depends on PXA_EZX + depends on ARCH_PXA_ESERIES + help + Say Y here if you intend to run this kernel on a Toshiba + e400 family PDA. -config MACH_XCEP - bool "Iskratel Electronics XCEP" - select PXA25x - select MTD - select MTD_PARTITIONS - select MTD_PHYSMAP - select MTD_CFI_INTELEXT - select MTD_CFI - select MTD_CHAR - select SMC91X - select PXA_SSP +config MACH_E800 + bool "Toshiba e800" + default y + depends on ARCH_PXA_ESERIES + select FB_W100 help - PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. - Tuned for usage in Libera instruments for particle accelerators. + Say Y here if you intend to run this kernel on a Toshiba + e800 family PDA. endmenu diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index e5d450c5434..cdaf88831c2 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -24,33 +24,66 @@ obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o -# Specific board support -obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o -obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o -obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o +# NOTE: keep the order of boards in accordance to their order in Kconfig + +# Intel/Marvell Dev Platforms obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o -obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o -obj-$(CONFIG_MACH_BALLOON3) += balloon3.o -obj-$(CONFIG_MACH_MP900C) += mp900.o +ifeq ($(CONFIG_MACH_ZYLONITE),y) + obj-y += zylonite.o + obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o + obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o +endif +obj-$(CONFIG_MACH_LITTLETON) += littleton.o +obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o +obj-$(CONFIG_MACH_SAAR) += saar.o + +# 3rd Party Dev Platforms obj-$(CONFIG_ARCH_PXA_IDP) += idp.o +obj-$(CONFIG_ARCH_VIPER) += viper.o +obj-$(CONFIG_MACH_BALLOON3) += balloon3.o +obj-$(CONFIG_MACH_CSB726) += csb726.o +obj-$(CONFIG_CSB726_CSB701) += csb701.o +obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o +ifeq ($(CONFIG_PCI),y) +obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o +endif +obj-$(CONFIG_MACH_EM_X270) += em-x270.o +obj-$(CONFIG_MACH_CM_X300) += cm-x300.o +obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o +obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o +obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o +obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o +obj-$(CONFIG_MACH_STARGATE2) += stargate2.o +obj-$(CONFIG_MACH_XCEP) += xcep.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o +obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o +obj-$(CONFIG_MACH_PCM027) += pcm027.o +obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o + +# End-user Products +obj-$(CONFIG_MACH_H4700) += hx4700.o obj-$(CONFIG_MACH_H5000) += h5000.o +obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o +obj-$(CONFIG_MACH_MAGICIAN) += magician.o +obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o +obj-$(CONFIG_PXA_EZX) += ezx.o +obj-$(CONFIG_MACH_MP900C) += mp900.o +obj-$(CONFIG_MACH_PALMTE2) += palmte2.o +obj-$(CONFIG_MACH_PALMTC) += palmtc.o +obj-$(CONFIG_MACH_PALMT5) += palmt5.o +obj-$(CONFIG_MACH_PALMTX) += palmtx.o +obj-$(CONFIG_MACH_PALMZ72) += palmz72.o +obj-$(CONFIG_MACH_PALMLD) += palmld.o +obj-$(CONFIG_PALM_TREO) += palmtreo.o obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o obj-$(CONFIG_MACH_POODLE) += poodle.o -obj-$(CONFIG_MACH_PCM027) += pcm027.o -obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o obj-$(CONFIG_MACH_TOSA) += tosa.o -obj-$(CONFIG_MACH_EM_X270) += em-x270.o -obj-$(CONFIG_MACH_H4700) += hx4700.o -obj-$(CONFIG_MACH_MAGICIAN) += magician.o -obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o -obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o obj-$(CONFIG_MACH_E330) += e330.o obj-$(CONFIG_MACH_E350) += e350.o @@ -58,34 +91,6 @@ obj-$(CONFIG_MACH_E740) += e740.o obj-$(CONFIG_MACH_E750) += e750.o obj-$(CONFIG_MACH_E400) += e400.o obj-$(CONFIG_MACH_E800) += e800.o -obj-$(CONFIG_MACH_PALMTE2) += palmte2.o -obj-$(CONFIG_MACH_PALMTC) += palmtc.o -obj-$(CONFIG_MACH_PALMT5) += palmt5.o -obj-$(CONFIG_MACH_PALMTX) += palmtx.o -obj-$(CONFIG_MACH_PALMLD) += palmld.o -obj-$(CONFIG_MACH_PALMZ72) += palmz72.o -obj-$(CONFIG_PALM_TREO) += palmtreo.o -obj-$(CONFIG_ARCH_VIPER) += viper.o - -ifeq ($(CONFIG_MACH_ZYLONITE),y) - obj-y += zylonite.o - obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o - obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o -endif -obj-$(CONFIG_MACH_LITTLETON) += littleton.o -obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o -obj-$(CONFIG_MACH_SAAR) += saar.o - -obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o -obj-$(CONFIG_MACH_CM_X300) += cm-x300.o -obj-$(CONFIG_PXA_EZX) += ezx.o - -obj-$(CONFIG_MACH_XCEP) += xcep.o - -obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o -obj-$(CONFIG_MACH_STARGATE2) += stargate2.o -obj-$(CONFIG_MACH_CSB726) += csb726.o -obj-$(CONFIG_CSB726_CSB701) += csb701.o # Support for blinky lights led-y := leds.o @@ -95,8 +100,4 @@ led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o obj-$(CONFIG_LEDS) += $(led-y) -ifeq ($(CONFIG_PCI),y) -obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o -endif - obj-$(CONFIG_TOSA_BT) += tosa-bt.o -- cgit v1.2.3-70-g09d2 From 68bef3a7859ebee8bf79a8e6e36369cbbe5903ca Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Fri, 4 Sep 2009 17:33:23 +0800 Subject: [ARM] pxa: add missing irq events for pxa168 Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/include/mach/irqs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index 16295cfd5e2..d68871b0f28 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -31,7 +31,9 @@ #define IRQ_PXA168_DDR_INT 26 #define IRQ_PXA168_UART1 27 #define IRQ_PXA168_UART2 28 +#define IRQ_PXA168_UART3 29 #define IRQ_PXA168_WDT 35 +#define IRQ_PXA168_MAIN_PMU 36 #define IRQ_PXA168_FRQ_CHANGE 38 #define IRQ_PXA168_SDH1 39 #define IRQ_PXA168_SDH2 40 @@ -46,7 +48,7 @@ #define IRQ_PXA168_USB2 51 #define IRQ_PXA168_AC97 57 #define IRQ_PXA168_TWSI1 58 -#define IRQ_PXA168_PMU 60 +#define IRQ_PXA168_AP_PMU 60 #define IRQ_PXA168_SM_INT 63 /* -- cgit v1.2.3-70-g09d2 From 4092855d9634fd0cce879b0f47a7e128f86d869e Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Thu, 10 Sep 2009 14:01:22 +0800 Subject: [ARM] pxa: add apmu clock support in mmp Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-mmp/clock.c | 15 +++++++++++++++ arch/arm/mach-mmp/clock.h | 1 + 2 files changed, 16 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c index 2d9cc5a7122..2a46ed5cc2a 100644 --- a/arch/arm/mach-mmp/clock.c +++ b/arch/arm/mach-mmp/clock.c @@ -34,6 +34,21 @@ struct clkops apbc_clk_ops = { .disable = apbc_clk_disable, }; +static void apmu_clk_enable(struct clk *clk) +{ + __raw_writel(clk->enable_val, clk->clk_rst); +} + +static void apmu_clk_disable(struct clk *clk) +{ + __raw_writel(0, clk->clk_rst); +} + +struct clkops apmu_clk_ops = { + .enable = apmu_clk_enable, + .disable = apmu_clk_disable, +}; + static DEFINE_SPINLOCK(clocks_lock); int clk_enable(struct clk *clk) diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index ed967e78e6a..eefffbe683b 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h @@ -25,6 +25,7 @@ struct clk { }; extern struct clkops apbc_clk_ops; +extern struct clkops apmu_clk_ops; #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ struct clk clk_##_name = { \ -- cgit v1.2.3-70-g09d2 From 6427d45068dd4357c44a5a623e5efb6990eb43c9 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 23 Oct 2009 00:09:47 +0800 Subject: [ARM] pxa: use platform_device_id table for SSP driver Signed-off-by: Eric Miao --- arch/arm/mach-pxa/ssp.c | 73 ++++++++++--------------------------------------- 1 file changed, 15 insertions(+), 58 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 965e38c6baf..9ebe658590f 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c @@ -342,8 +342,9 @@ void ssp_free(struct ssp_device *ssp) } EXPORT_SYMBOL(ssp_free); -static int __devinit ssp_probe(struct platform_device *pdev, int type) +static int __devinit ssp_probe(struct platform_device *pdev) { + const struct platform_device_id *id = platform_get_device_id(pdev); struct resource *res; struct ssp_device *ssp; int ret = 0; @@ -413,7 +414,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type) */ ssp->port_id = pdev->id + 1; ssp->use_count = 0; - ssp->type = type; + ssp->type = (int)id->driver_data; mutex_lock(&ssp_lock); list_add(&ssp->node, &ssp_list); @@ -457,75 +458,31 @@ static int __devexit ssp_remove(struct platform_device *pdev) return 0; } -static int __devinit pxa25x_ssp_probe(struct platform_device *pdev) -{ - return ssp_probe(pdev, PXA25x_SSP); -} - -static int __devinit pxa25x_nssp_probe(struct platform_device *pdev) -{ - return ssp_probe(pdev, PXA25x_NSSP); -} - -static int __devinit pxa27x_ssp_probe(struct platform_device *pdev) -{ - return ssp_probe(pdev, PXA27x_SSP); -} - -static struct platform_driver pxa25x_ssp_driver = { - .driver = { - .name = "pxa25x-ssp", - }, - .probe = pxa25x_ssp_probe, - .remove = __devexit_p(ssp_remove), +static const struct platform_device_id ssp_id_table[] = { + { "pxa25x-ssp", PXA25x_SSP }, + { "pxa25x-nssp", PXA25x_NSSP }, + { "pxa27x-ssp", PXA27x_SSP }, + { }, }; -static struct platform_driver pxa25x_nssp_driver = { - .driver = { - .name = "pxa25x-nssp", - }, - .probe = pxa25x_nssp_probe, +static struct platform_driver ssp_driver = { + .probe = ssp_probe, .remove = __devexit_p(ssp_remove), -}; - -static struct platform_driver pxa27x_ssp_driver = { .driver = { - .name = "pxa27x-ssp", + .owner = THIS_MODULE, + .name = "pxa2xx-ssp", }, - .probe = pxa27x_ssp_probe, - .remove = __devexit_p(ssp_remove), + .id_table = ssp_id_table, }; static int __init pxa_ssp_init(void) { - int ret = 0; - - ret = platform_driver_register(&pxa25x_ssp_driver); - if (ret) { - printk(KERN_ERR "failed to register pxa25x_ssp_driver"); - return ret; - } - - ret = platform_driver_register(&pxa25x_nssp_driver); - if (ret) { - printk(KERN_ERR "failed to register pxa25x_nssp_driver"); - return ret; - } - - ret = platform_driver_register(&pxa27x_ssp_driver); - if (ret) { - printk(KERN_ERR "failed to register pxa27x_ssp_driver"); - return ret; - } - - return ret; + return platform_driver_register(&ssp_driver); } static void __exit pxa_ssp_exit(void) { - platform_driver_unregister(&pxa25x_ssp_driver); - platform_driver_unregister(&pxa25x_nssp_driver); - platform_driver_unregister(&pxa27x_ssp_driver); + platform_driver_unregister(&ssp_driver); } arch_initcall(pxa_ssp_init); -- cgit v1.2.3-70-g09d2 From e68750aea06756bb7dd8d00ef85d3d51c7fd6bc4 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 4 Nov 2009 14:14:39 +0200 Subject: [ARM] pxa: register U2D clock for pxa3xx Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/pxa3xx.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 09b7b1a10ca..ca536f2b2bf 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -237,6 +237,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); +static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); @@ -261,6 +262,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), + INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), -- cgit v1.2.3-70-g09d2 From 7c6ccbf0ddce6d5a1e13e7f50befd864f289e108 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 4 Nov 2009 14:14:40 +0200 Subject: [ARM] pxa: add U2D registers and bits definitions This should be eventually moved to somewhere closer to the U2D driver, but is kept here atm so it's easier for USB configuration code to work. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/regs-u2d.h | 199 ++++++++++++++++++++++++++++++ 1 file changed, 199 insertions(+) create mode 100644 arch/arm/mach-pxa/include/mach/regs-u2d.h (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h new file mode 100644 index 00000000000..44b0b20b69a --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h @@ -0,0 +1,199 @@ +#ifndef __ASM_ARCH_PXA3xx_U2D_H +#define __ASM_ARCH_PXA3xx_U2D_H + +#include + +/* + * USB2 device controller registers and bits definitions + */ +#define U2DCR (0x0000) /* U2D Control Register */ +#define U2DCR_NDC (1 << 31) /* NAK During Config */ +#define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ +#define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ + +#define U2DICR (0x0004) /* U2D Interrupt Control Register */ +#define U2DISR (0x000C) /* U2D Interrupt Status Register */ +#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ + +#define U2DFNR (0x0014) /* U2D Frame Number Register */ + +#define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) +#define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ +#define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ + +#define U2DOTGCR (0x0020) /* U2D OTG Control Register */ +#define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ +#define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ +#define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ +#define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ + +#ifdef CONFIG_CPU_PXA930 +#define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ +#define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ +#define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ +#endif + +#define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ +#define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ +#define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ +#define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ +#define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ +#define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ + +#define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ +#define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ + +#define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ +#define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ +#define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ +#define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ +#define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ +#define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ +#define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ +#define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ +#define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ +#define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ +#define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ +#define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ +#define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ +#define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ +#define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ +#define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ + +#define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ +#define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ +#define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ +#define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ +#define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ +#define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ +#define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ +#define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ +#define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ +#define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ +#define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ +#define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ + +#define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ +#define U2DOTGUCR_RUN (1 << 25) /* RUN */ +#define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ +#define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ +#define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ +#define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ + +#define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ +#define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ +#define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ +#define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ +#define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ + +#define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ +#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ +#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ +#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ +#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ +#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ +#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ +#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ +#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ +#define U2DCSR_DME (1 << 3) /* DMA Enable */ +#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ +#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ +#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ + +#define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ +#define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ + +#define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ + +#define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ +#define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ +#define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ + +#define U2DSCA (0x0500) /* U2D Setup Command Address */ +#define U2DSCA_VALUE (0x0120) + +#define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ +#define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ + +/* U2DMA registers */ +#define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ +#define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ +#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ +#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ +#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ +#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ +#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ +#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ +#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ +#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ +#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ +#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ +#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ + +#define U2DMACR (0x1080) /* U2DMA Control Register */ +#define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ + +#define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ +#define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ + +#define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ +#define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ + +#define U2DMADADR_STOP (1U << 0) + +#define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ +#define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ +#define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ +#define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ + +#define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ +#define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ + +#define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ +#define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ +#define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ + +#endif /* __ASM_ARCH_PXA3xx_U2D_H */ -- cgit v1.2.3-70-g09d2 From cc155c6f2cc705cb082ed676044368424e4b9121 Mon Sep 17 00:00:00 2001 From: Russell King Date: Mon, 9 Nov 2009 13:34:08 +0800 Subject: [ARM] pxa: allow platforms to control which uarts are registered For some platforms, it is inappropriate to register all PXA UARTs. In some cases, the UARTs may not be used, and in others we may want to avoid registering the UARTs to allow other drivers (eg, FICP) to make use of the UART. In addition, a while back there was a request to be able to pass platform data to the UART driver. This patch enables all of this by providing functions platforms can call to register each individual UART. Signed-off-by: Russell King Acked-by: Mike Rapoport Acked-by: Robert Jarzmik Signed-off-by: Eric Miao --- arch/arm/mach-pxa/balloon3.c | 4 ++++ arch/arm/mach-pxa/cm-x2xx.c | 4 ++++ arch/arm/mach-pxa/cm-x300.c | 4 ++++ arch/arm/mach-pxa/colibri-pxa270.c | 3 +++ arch/arm/mach-pxa/colibri-pxa300.c | 4 ++++ arch/arm/mach-pxa/colibri-pxa320.c | 4 ++++ arch/arm/mach-pxa/corgi.c | 4 ++++ arch/arm/mach-pxa/csb726.c | 3 +++ arch/arm/mach-pxa/devices.c | 25 ++++++++++++++++++++++++- arch/arm/mach-pxa/e330.c | 3 +++ arch/arm/mach-pxa/e350.c | 3 +++ arch/arm/mach-pxa/e400.c | 3 +++ arch/arm/mach-pxa/e740.c | 3 +++ arch/arm/mach-pxa/e750.c | 3 +++ arch/arm/mach-pxa/e800.c | 3 +++ arch/arm/mach-pxa/em-x270.c | 4 ++++ arch/arm/mach-pxa/ezx.c | 24 ++++++++++++++++++++++++ arch/arm/mach-pxa/generic.h | 5 +++++ arch/arm/mach-pxa/gumstix.c | 5 +++++ arch/arm/mach-pxa/h5000.c | 3 +++ arch/arm/mach-pxa/himalaya.c | 3 +++ arch/arm/mach-pxa/hx4700.c | 4 ++++ arch/arm/mach-pxa/idp.c | 3 +++ arch/arm/mach-pxa/imote2.c | 6 +++++- arch/arm/mach-pxa/littleton.c | 4 ++++ arch/arm/mach-pxa/lpd270.c | 4 ++++ arch/arm/mach-pxa/lubbock.c | 4 ++++ arch/arm/mach-pxa/magician.c | 4 ++++ arch/arm/mach-pxa/mainstone.c | 4 ++++ arch/arm/mach-pxa/mioa701.c | 3 +++ arch/arm/mach-pxa/mp900.c | 3 +++ arch/arm/mach-pxa/palmld.c | 4 ++++ arch/arm/mach-pxa/palmt5.c | 4 ++++ arch/arm/mach-pxa/palmtc.c | 5 +++++ arch/arm/mach-pxa/palmte2.c | 4 ++++ arch/arm/mach-pxa/palmtreo.c | 4 ++++ arch/arm/mach-pxa/palmtx.c | 4 ++++ arch/arm/mach-pxa/palmz72.c | 4 ++++ arch/arm/mach-pxa/pcm027.c | 4 ++++ arch/arm/mach-pxa/poodle.c | 4 ++++ arch/arm/mach-pxa/pxa25x.c | 7 +------ arch/arm/mach-pxa/pxa27x.c | 3 --- arch/arm/mach-pxa/pxa3xx.c | 3 --- arch/arm/mach-pxa/saar.c | 4 ++++ arch/arm/mach-pxa/spitz.c | 4 ++++ arch/arm/mach-pxa/stargate2.c | 4 ++++ arch/arm/mach-pxa/tavorevb.c | 4 ++++ arch/arm/mach-pxa/tosa.c | 5 +++++ arch/arm/mach-pxa/trizeps4.c | 4 ++++ arch/arm/mach-pxa/viper.c | 4 ++++ arch/arm/mach-pxa/xcep.c | 5 +++++ arch/arm/mach-pxa/zylonite.c | 4 ++++ 52 files changed, 230 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index f23138b8fca..b8cd07ca938 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -306,6 +306,10 @@ static void __init balloon3_init(void) */ ARB_CNTRL = ARB_CORE_PARK | 0x234; + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); if (balloon3_has(BALLOON3_FEATURE_AUDIO)) pxa_set_ac97_info(NULL); diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index b50ef39eabf..bff6e78f033 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c @@ -453,6 +453,10 @@ static inline void cmx2xx_init_ac97(void) {} static void __init cmx2xx_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + cmx2xx_pm_init(); if (cpu_is_pxa25x()) diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 06552ca9181..7f2e87839a8 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -438,6 +438,10 @@ static void __init cm_x300_init(void) /* board-processor specific GPIO initialization */ pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + cm_x300_init_dm9000(); cm_x300_init_lcd(); cm_x300_init_ohci(); diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 01bcfaae75b..061c45316de 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c @@ -130,6 +130,9 @@ static struct platform_device *colibri_pxa270_devices[] __initdata = { static void __init colibri_pxa270_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); } diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 37c239c5656..45c23fd6df3 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c @@ -170,6 +170,10 @@ static inline void colibri_pxa310_init_ac97(void) {} void __init colibri_pxa300_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + colibri_pxa300_init_eth(); colibri_pxa300_init_ohci(); colibri_pxa3xx_init_nand(); diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ec0e14b9668..ae835fad7d1 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c @@ -199,6 +199,10 @@ static void __init colibri_pxa320_init_uart(void) void __init colibri_pxa320_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + colibri_pxa320_init_eth(); colibri_pxa320_init_ohci(); colibri_pxa3xx_init_nand(); diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index b536b5a5a10..74446cf8ae6 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -671,6 +671,10 @@ static void __init corgi_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + corgi_init_spi(); pxa_set_udc_info(&udc_info); diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 965480eb4fe..88575b87bd3 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c @@ -268,6 +268,9 @@ static void __init csb726_init(void) /* MSC2 = 0x06697ff4; *//* none/SM501 */ MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); pxa_set_i2c_info(NULL); pxa27x_set_i2c_power_info(NULL); pxa_set_mci_info(&csb726_mci); diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index e2b427fa55e..d4cc41d04b2 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -167,13 +167,18 @@ static struct resource pxa_resource_ffuart[] = { } }; -struct platform_device pxa_device_ffuart= { +struct platform_device pxa_device_ffuart = { .name = "pxa2xx-uart", .id = 0, .resource = pxa_resource_ffuart, .num_resources = ARRAY_SIZE(pxa_resource_ffuart), }; +void __init pxa_set_ffuart_info(void *info) +{ + pxa_register_device(&pxa_device_ffuart, info); +} + static struct resource pxa_resource_btuart[] = { { .start = 0x40200000, @@ -193,6 +198,11 @@ struct platform_device pxa_device_btuart = { .num_resources = ARRAY_SIZE(pxa_resource_btuart), }; +void __init pxa_set_btuart_info(void *info) +{ + pxa_register_device(&pxa_device_btuart, info); +} + static struct resource pxa_resource_stuart[] = { { .start = 0x40700000, @@ -212,6 +222,11 @@ struct platform_device pxa_device_stuart = { .num_resources = ARRAY_SIZE(pxa_resource_stuart), }; +void __init pxa_set_stuart_info(void *info) +{ + pxa_register_device(&pxa_device_stuart, info); +} + static struct resource pxa_resource_hwuart[] = { { .start = 0x41600000, @@ -231,6 +246,14 @@ struct platform_device pxa_device_hwuart = { .num_resources = ARRAY_SIZE(pxa_resource_hwuart), }; +void __init pxa_set_hwuart_info(void *info) +{ + if (cpu_is_pxa255()) + pxa_register_device(&pxa_device_hwuart, info); + else + pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware"); +} + static struct resource pxai2c_resources[] = { { .start = 0x40301680, diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index 74d3f8987c5..8fde3387279 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c @@ -55,6 +55,9 @@ static struct platform_device *devices[] __initdata = { static void __init e330_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index 08003627213..f50f055f572 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c @@ -56,6 +56,9 @@ static struct platform_device *devices[] __initdata = { static void __init e350_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); eseries_register_clks(); eseries_get_tmio_gpios(); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index ed9c0c3f64a..55b950f1284 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c @@ -130,6 +130,9 @@ static struct platform_device *devices[] __initdata = { static void __init e400_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); /* Fixme - e400 may have a switched clock */ eseries_register_clks(); eseries_get_tmio_gpios(); diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index 49acdfa6650..94b23a9e387 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c @@ -192,6 +192,9 @@ static struct platform_device *devices[] __initdata = { static void __init e740_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); eseries_register_clks(); clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, "UDCCLK", &pxa25x_device_udc.dev), diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 4052ece3ef4..5eccbce73a3 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c @@ -194,6 +194,9 @@ static struct platform_device *devices[] __initdata = { static void __init e750_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index 9866c7b9e78..aad129bed19 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c @@ -195,6 +195,9 @@ static struct platform_device *devices[] __initdata = { static void __init e800_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, "GPIO11_CLK", NULL), eseries_get_tmio_gpios(); diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index aec7f4214b1..e0b0fda9e67 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -1286,6 +1286,10 @@ static void __init em_x270_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + #ifdef CONFIG_PM pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP); #endif diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 588b265e575..48c17372bc1 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -693,6 +693,10 @@ static void __init a780_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); set_pxa_fb_info(&ezx_fb_info_1); @@ -754,6 +758,10 @@ static void __init e680_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); @@ -816,6 +824,10 @@ static void __init a1200_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); @@ -874,6 +886,10 @@ static void __init a910_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); set_pxa_fb_info(&ezx_fb_info_2); @@ -935,6 +951,10 @@ static void __init e6_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); @@ -971,6 +991,10 @@ static void __init e2_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 485fede83d9..890fb90a672 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h @@ -67,3 +67,8 @@ extern struct sysdev_class pxa_irq_sysclass; extern struct sysdev_class pxa_gpio_sysclass; extern struct sysdev_class pxa2xx_mfp_sysclass; extern struct sysdev_class pxa3xx_mfp_sysclass; + +void __init pxa_set_ffuart_info(void *info); +void __init pxa_set_btuart_info(void *info); +void __init pxa_set_stuart_info(void *info); +void __init pxa_set_hwuart_info(void *info); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 1708c010984..96c34512913 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -211,6 +211,11 @@ static void __init gumstix_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_hwuart_info(NULL); + gumstix_bluetooth_init(); gumstix_udc_init(); gumstix_mmc_init(); diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index f3d220c32e0..c1cab0871c9 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c @@ -193,6 +193,9 @@ static void __init h5000_init(void) fix_msc(); pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); pxa_set_udc_info(&h5000_udc_mach_info); platform_add_devices(ARRAY_AND_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index cea99fe65b9..f9a2e4b0f09 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c @@ -150,6 +150,9 @@ static void __init himalaya_lcd_init(void) static void __init himalaya_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); himalaya_lcd_init(); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 83bd3c6e388..6b3c90ed5f2 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -849,6 +849,10 @@ static void __init hx4700_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config)); hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_add_devices(devices, ARRAY_SIZE(devices)); pxa_set_ficp_info(&ficp_info); diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index b6486ef20b1..5c9e11d74f4 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -179,6 +179,9 @@ static void __init idp_init(void) printk("idp_init()\n"); pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); platform_device_register(&smc91x_device); //platform_device_register(&mst_audio_device); diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 2a4945db31c..5b0862df61a 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c @@ -554,8 +554,12 @@ static struct i2c_pxa_platform_data i2c_pdata = { static void __init imote2_init(void) { - pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); + + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* SPI chip select directions - all other directions should * be handled by drivers.*/ gpio_direction_output(37, 0); diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index ce5e6175a05..f28c1715b91 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c @@ -413,6 +413,10 @@ static void __init littleton_init(void) /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* * Note: we depend bootloader set the correct * value to MSC register for SMC91x. diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index d64395f26a3..1373c22dbb8 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -455,6 +455,10 @@ static void __init lpd270_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; lpd270_flash_data[1].width = 4; diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index c6a94d3fdd6..98ee7e59029 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -518,6 +518,10 @@ static void __init lubbock_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); pxa_set_udc_info(&udc_info); set_pxa_fb_info(&sharp_lm8v31); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 5360c07f513..8a38d604dc7 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -742,6 +742,10 @@ static void __init magician_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_add_devices(ARRAY_AND_SIZE(devices)); err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN"); diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a4eeae345e6..851ee0fc32e 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -576,6 +576,10 @@ static void __init mainstone_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; mst_flash_data[1].width = 4; diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 3cab452e556..2466a44d8fd 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -798,6 +798,9 @@ static void __init mioa701_machine_init(void) UP2OCR = UP2OCR_HXOE; pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); bootstrap_init(); set_pxa_fb_info(&mioa701_pxafb_info); diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index a65713ce019..6d4503927a7 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c @@ -84,6 +84,9 @@ static struct platform_device *devices[] __initdata = { static void __init mp900c_init(void) { printk(KERN_INFO "MobilePro 900/C machine init\n"); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 1ad029dd443..59140217890 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -530,6 +530,10 @@ static void __init palmld_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + palmld_pm_init(); set_pxa_fb_info(&palmld_lcd_screen); pxa_set_mci_info(&palmld_mci_platform_data); diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 2dd7ce28556..7f89ca20f13 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -419,6 +419,10 @@ static void __init palmt5_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + palmt5_pm_init(); set_pxa_fb_info(&palmt5_lcd_screen); pxa_set_mci_info(&palmt5_mci_platform_data); diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 0b92291a58f..30841759200 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -416,6 +416,11 @@ static void __init palmtc_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_hwuart_info(NULL); + set_pxa_fb_info(&palmtc_lcd_screen); pxa_set_mci_info(&palmtc_mci_platform_data); pxa_set_udc_info(&palmtc_udc_info); diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 277c4062e3c..265d62bae7d 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -373,6 +373,10 @@ static void __init palmte2_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmte2_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + set_pxa_fb_info(&palmte2_lcd_screen); pxa_set_mci_info(&palmte2_mci_platform_data); palmte2_udc_init(); diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index c071b60ebed..606eb7e8a17 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -653,6 +653,10 @@ static void __init treo_lcd_power_init(void) static void __init treo_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + treo_pm_init(); pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config)); treo_lcd_power_init(); diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 76a2b37eaf3..7bf18c2f002 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -570,6 +570,10 @@ static void __init palmtx_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + palmtx_pm_init(); set_pxa_fb_info(&palmtx_lcd_screen); pxa_set_mci_info(&palmtx_mci_platform_data); diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index c2bf493c5f5..d787ac7cfdd 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -491,6 +491,10 @@ static void __init palmz72_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + set_pxa_fb_info(&palmz72_lcd_screen); pxa_set_mci_info(&palmz72_mci_platform_data); palmz72_udc_init(); diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 6abfa2979c6..2190af06647 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c @@ -227,6 +227,10 @@ static void __init pcm027_init(void) pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_add_devices(devices, ARRAY_SIZE(devices)); /* at last call the baseboard to initialize itself */ diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index a186994f77f..e5eeb3a62d0 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -449,6 +449,10 @@ static void __init poodle_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_scoop_config = &poodle_pcmcia_config; ret = platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 77c2693cfee..2c1b0b70d01 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -322,9 +322,6 @@ void __init pxa26x_init_irq(void) static struct platform_device *pxa25x_devices[] __initdata = { &pxa25x_device_udc, - &pxa_device_ffuart, - &pxa_device_btuart, - &pxa_device_stuart, &pxa_device_i2s, &sa1100_device_rtc, &pxa25x_device_ssp, @@ -372,10 +369,8 @@ static int __init pxa25x_init(void) } /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ - if (cpu_is_pxa255()) { + if (cpu_is_pxa255()) clks_register(&pxa25x_hwuart_clkreg, 1); - ret = platform_device_register(&pxa_device_hwuart); - } return ret; } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index ec68cc16b4e..6a0b73167e0 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -364,9 +364,6 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, - &pxa_device_ffuart, - &pxa_device_btuart, - &pxa_device_stuart, &pxa_device_i2s, &sa1100_device_rtc, &pxa_device_rtc, diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index ca536f2b2bf..3198680626e 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -555,9 +555,6 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) static struct platform_device *devices[] __initdata = { &pxa27x_device_udc, - &pxa_device_ffuart, - &pxa_device_btuart, - &pxa_device_stuart, &pxa_device_i2s, &sa1100_device_rtc, &pxa_device_rtc, diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 3cccb085b97..115b6f234bd 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c @@ -583,6 +583,10 @@ static void __init saar_init(void) /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_device_register(&smc91x_device); saar_init_onenand(); diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 3da45d05174..bbd7a855ae2 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -768,6 +768,10 @@ static void __init common_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + spitz_init_spi(); platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 3b205b69f3f..a98a434f011 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c @@ -760,6 +760,10 @@ static void __init stargate2_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* spi chip selects */ gpio_direction_output(37, 0); gpio_direction_output(24, 0); diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index b75353a2ec7..f02dcb5b4e9 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c @@ -477,6 +477,10 @@ static void __init tavorevb_init(void) /* initialize MFP configurations */ pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + platform_device_register(&smc91x_device); tavorevb_init_lcd(); diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index e81a52673d4..c854c168a45 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -825,6 +825,11 @@ static void __init tosa_init(void) int dummy; pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config)); + + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + gpio_set_wake(MFP_PIN_GPIO1, 1); /* We can't pass to gpio-keys since it will drop the Reset altfunc */ diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 3981e0356d1..0aa858ebc57 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -524,6 +524,10 @@ static void __init trizeps4_init(void) ARRAY_SIZE(trizeps4_devices)); } + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + if (0) /* dont know how to determine LCD */ set_pxa_fb_info(&sharp_lcd); else diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index d33c232b686..6c36bd9f3b5 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -908,6 +908,10 @@ static void __init viper_init(void) pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* Wake-up serial console */ viper_init_serial_gpio(); diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 3fd79cbb36c..d3b4e3f2e03 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c @@ -165,6 +165,11 @@ static void __init xcep_init(void) { pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config)); + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + pxa_set_hwuart_info(NULL); + /* See Intel XScale Developer's Guide for details */ /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ MSC1 = (MSC1 & 0xffff) | 0xD5540000; diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 8fcb69411cf..b66e9e2d06e 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c @@ -444,6 +444,10 @@ static inline void zylonite_init_ohci(void) {} static void __init zylonite_init(void) { + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); + /* board-processor specific initialization */ zylonite_pxa300_init(); zylonite_pxa320_init(); -- cgit v1.2.3-70-g09d2 From 1493df7319e06fb6ae6daa7e0d28355e6e8be1c9 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 9 Nov 2009 14:25:52 +0800 Subject: [ARM] pxa: introduce CONFIG_MACH_ZYLONITE{300,320} for CPU_PXA* removing Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 13 ++++++++++++- arch/arm/mach-pxa/Makefile | 7 ++----- 2 files changed, 14 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index e62572dc2d7..ca2bd593ca3 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -46,12 +46,23 @@ config MACH_MAINSTONE select PXA_HAVE_BOARD_IRQS config MACH_ZYLONITE - bool "PXA3xx Development Platform (aka Zylonite)" + bool select PXA3xx select PXA_SSP select HAVE_PWM select PXA_HAVE_BOARD_IRQS +config MACH_ZYLONITE300 + bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" + select CPU_PXA300 + select CPU_PXA310 + select MACH_ZYLONITE + +config MACH_ZYLONITE320 + bool "PXA3xx Development Platform (aka Zylonite) PXA320" + select CPU_PXA320 + select MACH_ZYLONITE + config MACH_LITTLETON bool "PXA3xx Form Factor Platform (aka Littleton)" select PXA3xx diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index cdaf88831c2..b5d29e60a34 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -29,11 +29,8 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o # Intel/Marvell Dev Platforms obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o -ifeq ($(CONFIG_MACH_ZYLONITE),y) - obj-y += zylonite.o - obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o - obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o -endif +obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o +obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o obj-$(CONFIG_MACH_LITTLETON) += littleton.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_SAAR) += saar.o -- cgit v1.2.3-70-g09d2 From 9035a9ece9819155ed6a12654ab5d5293d3f2545 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 9 Nov 2009 14:40:47 +0800 Subject: [ARM] pxa: select CPU_PXA310 for MACH_COLIBRI300 MACH_COLIBRI300 is supposed to support both PXA300 and PXA310, select the missing CPU_PXA310. Signed-off-by: Eric Miao Acked-by: Daniel Mack --- arch/arm/mach-pxa/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index ca2bd593ca3..4bd0f8740b2 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -254,6 +254,7 @@ config MACH_COLIBRI300 bool "Toradex Colibri PXA300/310" select PXA3xx select CPU_PXA300 + select CPU_PXA310 config MACH_COLIBRI320 bool "Toradex Colibri PXA320" -- cgit v1.2.3-70-g09d2 From 15cc7112abb66e7e1c956135ba2390638acf3416 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 9 Nov 2009 14:37:59 +0800 Subject: [ARM] pxa: make CPU_PXA* to be selectable hidden options CONFIG_CPU_PXA{300,310,320,930,935,950} are really platform dependent and should be made into selectable hidden options. Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 65 ++++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 4bd0f8740b2..20e645a6943 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -2,35 +2,6 @@ if ARCH_PXA menu "Intel PXA2xx/PXA3xx Implementations" -if PXA3xx - -menu "Supported PXA3xx Processor Variants" - -config CPU_PXA300 - bool "PXA300 (codename Monahans-L)" - -config CPU_PXA310 - bool "PXA310 (codename Monahans-LV)" - select CPU_PXA300 - -config CPU_PXA320 - bool "PXA320 (codename Monahans-P)" - -config CPU_PXA930 - bool "PXA930 (codename Tavor-P)" - -config CPU_PXA935 - bool "PXA935 (codename Tavor-P65)" - select CPU_PXA930 - -config CPU_PXA950 - bool "PXA950 (codename Tavor-PV2)" - select CPU_PXA930 - -endmenu - -endif - comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" config ARCH_LUBBOCK @@ -585,6 +556,42 @@ config PXA3xx help Select code specific to PXA3xx variants +config CPU_PXA300 + bool + select PXA3xx + help + PXA300 (codename Monahans-L) + +config CPU_PXA310 + bool + select CPU_PXA300 + help + PXA310 (codename Monahans-LV) + +config CPU_PXA320 + bool + select PXA3xx + help + PXA320 (codename Monahans-P) + +config CPU_PXA930 + bool + select PXA3xx + help + PXA930 (codename Tavor-P) + +config CPU_PXA935 + bool + select CPU_PXA930 + help + PXA935 (codename Tavor-P65) + +config CPU_PXA950 + bool + select CPU_PXA930 + help + PXA950 (codename Tavor-PV2) + config PXA_SHARP_C7xx bool select PXA_SSP -- cgit v1.2.3-70-g09d2 From bf293aec15fb223fd81c0cdfd1829edff95a325b Mon Sep 17 00:00:00 2001 From: Mike Rapoport Date: Wed, 11 Nov 2009 11:36:59 +0200 Subject: [ARM] pxa: add EXT_WAKEUP interrupts handling for pxa3xx Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/pxa3xx.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 3198680626e..fcb0721f466 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "generic.h" @@ -45,6 +46,9 @@ #define ACCR_D0CS (1 << 26) #define ACCR_PCCE (1 << 11) +#define PECR_IE(n) ((1 << ((n) * 2)) << 28) +#define PECR_IS(n) ((1 << ((n) * 2)) << 29) + /* crystal frequency to static memory controller multiplier (SMCFS) */ static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; @@ -532,6 +536,43 @@ static inline void pxa3xx_init_pm(void) {} #define pxa3xx_set_wake NULL #endif +static void pxa_ack_ext_wakeup(unsigned int irq) +{ + PECR |= PECR_IS(irq - IRQ_WAKEUP0); +} + +static void pxa_mask_ext_wakeup(unsigned int irq) +{ + ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); + PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); +} + +static void pxa_unmask_ext_wakeup(unsigned int irq) +{ + ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); + PECR |= PECR_IE(irq - IRQ_WAKEUP0); +} + +static struct irq_chip pxa_ext_wakeup_chip = { + .name = "WAKEUP", + .ack = pxa_ack_ext_wakeup, + .mask = pxa_mask_ext_wakeup, + .unmask = pxa_unmask_ext_wakeup, +}; + +static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) +{ + int irq; + + for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { + set_irq_chip(irq, &pxa_ext_wakeup_chip); + set_irq_handler(irq, handle_edge_irq); + set_irq_flags(irq, IRQF_VALID); + } + + pxa_ext_wakeup_chip.set_wake = fn; +} + void __init pxa3xx_init_irq(void) { /* enable CP6 access */ @@ -541,6 +582,7 @@ void __init pxa3xx_init_irq(void) __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); pxa_init_irq(56, pxa3xx_set_wake); + pxa_init_ext_wakeup_irq(pxa3xx_set_wake); pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); } -- cgit v1.2.3-70-g09d2 From 61333c63005e5708977e309da32c952057ee445b Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Wed, 4 Nov 2009 21:58:16 -0500 Subject: [ARM] pxa: rename macro from pxa9xx to pxa93x Because original macro can only judge whether current CPU is pxa93x, rename the macro to correct name. Signed-off-by: Haojian Zhuang Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/hardware.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index aa3d9f70a08..50f1297bf5a 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h @@ -105,6 +105,7 @@ * * PXA935 A0 0x56056931 0x1E653013 * PXA935 B0 0x56056936 0x6E653013 + * PXA935 B1 0x56056938 0x8E653013 */ #ifdef CONFIG_PXA25x #define __cpu_is_pxa210(id) \ @@ -283,7 +284,7 @@ _id == 0x3; \ }) -#define __cpu_is_pxa9xx(id) \ +#define __cpu_is_pxa93x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x683 || _id == 0x693; \ @@ -299,9 +300,9 @@ __cpu_is_pxa3xx(read_cpuid_id()); \ }) -#define cpu_is_pxa9xx() \ +#define cpu_is_pxa93x() \ ({ \ - __cpu_is_pxa9xx(read_cpuid_id()); \ + __cpu_is_pxa93x(read_cpuid_id()); \ }) /* * return current memory and LCD clock frequency in units of 10kHz -- cgit v1.2.3-70-g09d2 From b64b0b76cd90406f5411dc29308b9bb83180bfd6 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Thu, 22 Oct 2009 21:35:33 +0200 Subject: [ARM] pxa/zaurus: cleanup sharpsl_pm.c This fixes checkpatch/style problems in sharpsl_pm.c, allowing me to submit real fixes next. Signed-off-by: Pavel Machek Signed-off-by: Eric Miao --- arch/arm/mach-pxa/sharpsl_pm.c | 108 ++++++++++++++++++++--------------------- arch/arm/mach-pxa/spitz_pm.c | 10 ++-- 2 files changed, 59 insertions(+), 59 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 629e05d1196..dc3907f7986 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -165,19 +165,20 @@ struct battery_thresh spitz_battery_levels_noac[] = { }; /* MAX1111 Commands */ -#define MAXCTRL_PD0 1u << 0 -#define MAXCTRL_PD1 1u << 1 -#define MAXCTRL_SGL 1u << 2 -#define MAXCTRL_UNI 1u << 3 +#define MAXCTRL_PD0 (1u << 0) +#define MAXCTRL_PD1 (1u << 1) +#define MAXCTRL_SGL (1u << 2) +#define MAXCTRL_UNI (1u << 3) #define MAXCTRL_SEL_SH 4 -#define MAXCTRL_STR 1u << 7 +#define MAXCTRL_STR (1u << 7) /* * Read MAX1111 ADC */ int sharpsl_pm_pxa_read_max1111(int channel) { - if (machine_is_tosa()) // Ugly, better move this function into another module + /* Ugly, better move this function into another module */ + if (machine_is_tosa()) return 0; #ifdef CONFIG_CORGI_SSP_DEPRECATED @@ -238,7 +239,7 @@ EXPORT_SYMBOL(sharpsl_battery_kick); static void sharpsl_battery_thread(struct work_struct *private_) { - int voltage, percent, apm_status, i = 0; + int voltage, percent, apm_status, i; if (!sharpsl_pm.machinfo) return; @@ -250,15 +251,14 @@ static void sharpsl_battery_thread(struct work_struct *private_) && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL)) schedule_delayed_work(&toggle_charger, 0); - while(1) { + for (i = 0; i < 5; i++) { voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); - - if (voltage > 0) break; - if (i++ > 5) { - voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage; - dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n"); + if (voltage > 0) break; - } + } + if (voltage <= 0) { + voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage; + dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n"); } voltage = sharpsl_average_value(voltage); @@ -266,8 +266,10 @@ static void sharpsl_battery_thread(struct work_struct *private_) percent = get_percentage(voltage); /* At low battery voltages, the voltage has a tendency to start - creeping back up so we try to avoid this here */ - if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) || (apm_status == APM_BATTERY_STATUS_HIGH) || percent <= sharpsl_pm.battstat.mainbat_percent) { + creeping back up so we try to avoid this here */ + if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) + || (apm_status == APM_BATTERY_STATUS_HIGH) + || percent <= sharpsl_pm.battstat.mainbat_percent) { sharpsl_pm.battstat.mainbat_voltage = voltage; sharpsl_pm.battstat.mainbat_status = apm_status; sharpsl_pm.battstat.mainbat_percent = percent; @@ -279,8 +281,8 @@ static void sharpsl_battery_thread(struct work_struct *private_) #ifdef CONFIG_BACKLIGHT_CORGI /* If battery is low. limit backlight intensity to save power. */ if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) - && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) || - (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) { + && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) + || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) { if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) { sharpsl_pm.machinfo->backlight_limit(1); sharpsl_pm.flags |= SHARPSL_BL_LIMIT; @@ -293,8 +295,8 @@ static void sharpsl_battery_thread(struct work_struct *private_) /* Suspend if critical battery level */ if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) - && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL) - && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) { + && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL) + && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) { sharpsl_pm.flags |= SHARPSL_APM_QUEUED; dev_err(sharpsl_pm.dev, "Fatal Off\n"); apm_queue_event(APM_CRITICAL_SUSPEND); @@ -346,7 +348,7 @@ static void sharpsl_charge_error(void) static void sharpsl_charge_toggle(struct work_struct *private_) { - dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies); + dev_dbg(sharpsl_pm.dev, "Toggling Charger at time: %lx\n", jiffies); if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) { sharpsl_charge_off(); @@ -368,7 +370,7 @@ static void sharpsl_ac_timer(unsigned long data) { int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN); - dev_dbg(sharpsl_pm.dev, "AC Status: %d\n",acin); + dev_dbg(sharpsl_pm.dev, "AC Status: %d\n", acin); sharpsl_average_clear(); if (acin && (sharpsl_pm.charge_mode != CHRG_ON)) @@ -472,14 +474,14 @@ static int sharpsl_average_value(int ad) sharpsl_ad[sharpsl_ad_index] = ad; sharpsl_ad_index++; if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) { - for (i=0; i < (SHARPSL_CNV_VALUE_NUM-1); i++) + for (i = 0; i < (SHARPSL_CNV_VALUE_NUM-1); i++) sharpsl_ad[i] = sharpsl_ad[i+1]; sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1; } - for (i=0; i < sharpsl_ad_index; i++) + for (i = 0; i < sharpsl_ad_index; i++) ad_val += sharpsl_ad[i]; - return (ad_val / sharpsl_ad_index); + return ad_val / sharpsl_ad_index; } /* @@ -492,8 +494,8 @@ static int get_select_val(int *val) /* Find MAX val */ temp = val[0]; - j=0; - for (i=1; i<5; i++) { + j = 0; + for (i = 1; i < 5; i++) { if (temp < val[i]) { temp = val[i]; j = i; @@ -502,21 +504,21 @@ static int get_select_val(int *val) /* Find MIN val */ temp = val[4]; - k=4; - for (i=3; i>=0; i--) { + k = 4; + for (i = 3; i >= 0; i--) { if (temp > val[i]) { temp = val[i]; k = i; } } - for (i=0; i<5; i++) - if (i != j && i != k ) + for (i = 0; i < 5; i++) + if (i != j && i != k) sum += val[i]; dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]); - return (sum/3); + return sum/3; } static int sharpsl_check_battery_temp(void) @@ -524,7 +526,7 @@ static int sharpsl_check_battery_temp(void) int val, i, buff[5]; /* Check battery temperature */ - for (i=0; i<5; i++) { + for (i = 0; i < 5; i++) { mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); sharpsl_pm.machinfo->measure_temp(1); mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); @@ -557,7 +559,7 @@ static int sharpsl_check_battery_voltage(void) sharpsl_pm.machinfo->discharge1(1); /* Check battery voltage */ - for (i=0; i<5; i++) { + for (i = 0; i < 5; i++) { buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); } @@ -581,16 +583,16 @@ static int sharpsl_ac_check(void) { int temp, i, buff[5]; - for (i=0; i<5; i++) { + for (i = 0; i < 5; i++) { buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT); mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN); } temp = get_select_val(buff); - dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n",temp); + dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n", temp); if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) { - dev_err(sharpsl_pm.dev, "Error: AC check failed.\n"); + dev_err(sharpsl_pm.dev, "Error: AC check failed: voltage %d.\n", temp); return -1; } @@ -624,9 +626,9 @@ static int sharpsl_pm_resume(struct platform_device *pdev) static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) { - dev_dbg(sharpsl_pm.dev, "Time is: %08x\n",RCNR); + dev_dbg(sharpsl_pm.dev, "Time is: %08x\n", RCNR); - dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n",sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG); + dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n", sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG); /* not charging and AC-IN! */ if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) { @@ -644,12 +646,12 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) { RTSR &= RTSR_ALE; RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND; - dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n",RTAR); + dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n", RTAR); sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE; } else if (alarm_enable) { RTSR &= RTSR_ALE; RTAR = alarm_time; - dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n",RTAR); + dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n", RTAR); } else { dev_dbg(sharpsl_pm.dev, "No alarms set.\n"); } @@ -658,19 +660,18 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable sharpsl_pm.machinfo->postsuspend(); - dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n",PEDR); + dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n", PEDR); } static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) { - if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable) ) - { + if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable)) { if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) { dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n"); corgi_goto_sleep(alarm_time, alarm_enable, state); return 1; } - if(sharpsl_off_charge_battery()) { + if (sharpsl_off_charge_battery()) { dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n"); corgi_goto_sleep(alarm_time, alarm_enable, state); return 1; @@ -697,7 +698,7 @@ static int corgi_pxa_pm_enter(suspend_state_t state) corgi_goto_sleep(alarm_time, alarm_status, state); - while (corgi_enter_suspend(alarm_time,alarm_status,state)) + while (corgi_enter_suspend(alarm_time, alarm_status, state)) {} if (sharpsl_pm.machinfo->earlyresume) @@ -732,7 +733,7 @@ static int sharpsl_fatal_check(void) sharpsl_pm.machinfo->discharge1(1); /* Check battery : check inserting battery ? */ - for (i=0; i<5; i++) { + for (i = 0; i < 5; i++) { buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); } @@ -812,7 +813,7 @@ static int sharpsl_off_charge_battery(void) mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); time = RCNR; - while(1) { + while (1) { /* Check if any wakeup event had occurred */ if (sharpsl_pm.machinfo->charger_wakeup() != 0) return 0; @@ -835,9 +836,9 @@ static int sharpsl_off_charge_battery(void) mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); time = RCNR; - while(1) { + while (1) { /* Check if any wakeup event had occurred */ - if (sharpsl_pm.machinfo->charger_wakeup() != 0) + if (sharpsl_pm.machinfo->charger_wakeup()) return 0; /* Check for timeout */ if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) { @@ -864,12 +865,12 @@ static int sharpsl_off_charge_battery(void) static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_percent); + return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_percent); } static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_voltage); + return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_voltage); } static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL); @@ -943,8 +944,7 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) } } - if (sharpsl_pm.machinfo->batfull_irq) - { + if (sharpsl_pm.machinfo->batfull_irq) { /* Register interrupt handler. */ if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 724ffb03031..60bfaff172c 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -103,7 +103,7 @@ static void spitz_presuspend(void) PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC; PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); - PKSR = 0xffffffff; // clear + PKSR = 0xffffffff; /* clear */ /* nRESET_OUT Disable */ PSLR |= PSLR_SL_ROD; @@ -149,7 +149,7 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm) if (resume_on_alarm && (PEDR & PWER_RTC)) is_resume |= PWER_RTC; - dev_dbg(sharpsl_pm.dev, "is_resume: %x\n",is_resume); + dev_dbg(sharpsl_pm.dev, "is_resume: %x\n", is_resume); return is_resume; } @@ -160,7 +160,7 @@ static unsigned long spitz_charger_wakeup(void) unsigned long spitzpm_read_devdata(int type) { - switch(type) { + switch (type) { case SHARPSL_STATUS_ACIN: return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0); case SHARPSL_STATUS_LOCK: @@ -199,7 +199,7 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { #if defined(CONFIG_LCD_CORGI) .backlight_limit = corgi_lcd_limit_intensity, #elif defined(CONFIG_BACKLIGHT_CORGI) - .backlight_limit = corgibl_limit_intensity, + .backlight_limit = corgibl_limit_intensity, #endif .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, @@ -241,7 +241,7 @@ static int __devinit spitzpm_init(void) static void spitzpm_exit(void) { - platform_device_unregister(spitzpm_device); + platform_device_unregister(spitzpm_device); } module_init(spitzpm_init); -- cgit v1.2.3-70-g09d2 From 0ba01ebcb39aeb27c5a861c80e0b38634d0cb457 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Thu, 22 Oct 2009 22:16:34 +0200 Subject: [ARM] pxa/zaurus: rename spitz_battery_levels_* to sharpsl_* Battery power levels are shared between spitz and corgi, rename variable to reflect it. Signed-off-by: Pavel Machek Signed-off-by: Eric Miao --- arch/arm/mach-pxa/corgi_pm.c | 4 ++-- arch/arm/mach-pxa/sharpsl.h | 4 ++-- arch/arm/mach-pxa/sharpsl_pm.c | 4 ++-- arch/arm/mach-pxa/spitz_pm.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index a093282fe4d..d4a0733e905 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c @@ -214,8 +214,8 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, .bat_levels = 40, - .bat_levels_noac = spitz_battery_levels_noac, - .bat_levels_acin = spitz_battery_levels_acin, + .bat_levels_noac = sharpsl_battery_levels_noac, + .bat_levels_acin = sharpsl_battery_levels_acin, .status_high_acin = 188, .status_low_acin = 178, .status_high_noac = 185, diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h index 55259f4756c..1439785d397 100644 --- a/arch/arm/mach-pxa/sharpsl.h +++ b/arch/arm/mach-pxa/sharpsl.h @@ -42,8 +42,8 @@ void corgi_lcdtg_hw_init(int mode); #define MAX1111_BATT_TEMP 2u #define MAX1111_ACIN_VOLT 6u -extern struct battery_thresh spitz_battery_levels_acin[]; -extern struct battery_thresh spitz_battery_levels_noac[]; +extern struct battery_thresh sharpsl_battery_levels_acin[]; +extern struct battery_thresh sharpsl_battery_levels_noac[]; int sharpsl_pm_pxa_read_max1111(int channel); diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index dc3907f7986..67229a1ef55 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -78,7 +78,7 @@ DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger); -struct battery_thresh spitz_battery_levels_acin[] = { +struct battery_thresh sharpsl_battery_levels_acin[] = { { 213, 100}, { 212, 98}, { 211, 95}, @@ -121,7 +121,7 @@ struct battery_thresh spitz_battery_levels_acin[] = { { 0, 0}, }; -struct battery_thresh spitz_battery_levels_noac[] = { +struct battery_thresh sharpsl_battery_levels_noac[] = { { 213, 100}, { 212, 98}, { 211, 95}, diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 60bfaff172c..fc5a70c4035 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c @@ -208,8 +208,8 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, .bat_levels = 40, - .bat_levels_noac = spitz_battery_levels_noac, - .bat_levels_acin = spitz_battery_levels_acin, + .bat_levels_noac = sharpsl_battery_levels_noac, + .bat_levels_acin = sharpsl_battery_levels_acin, .status_high_acin = 188, .status_low_acin = 178, .status_high_noac = 185, -- cgit v1.2.3-70-g09d2 From 405ac4015a92904b6366db7c6ef21491bdb7e771 Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Thu, 12 Nov 2009 15:47:04 +0100 Subject: [ARM] pxa/ezx: add camera support for A780 and A910 EZX phones Signed-off-by: Bart Visscher Signed-off-by: Antonio Ospite Acked-by: Guennadi Liakhovetski Signed-off-by: Eric Miao --- arch/arm/mach-pxa/ezx.c | 174 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 170 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 48c17372bc1..320e2f8c599 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -17,8 +17,11 @@ #include #include #include +#include #include +#include + #include #include #include @@ -29,6 +32,7 @@ #include #include #include +#include #include "devices.h" #include "generic.h" @@ -38,6 +42,9 @@ #define GPIO15_A910_FLIP_LID 15 #define GPIO12_E680_LOCK_SWITCH 12 #define GPIO15_E6_LOCK_SWITCH 15 +#define GPIO50_nCAM_EN 50 +#define GPIO19_GEN1_CAM_RST 19 +#define GPIO28_GEN2_CAM_RST 28 static struct platform_pwm_backlight_data ezx_backlight_data = { .pwm_id = 0, @@ -191,8 +198,8 @@ static unsigned long gen1_pin_config[] __initdata = { GPIO94_CIF_DD_5, GPIO17_CIF_DD_6, GPIO108_CIF_DD_7, - GPIO50_GPIO, /* CAM_EN */ - GPIO19_GPIO, /* CAM_RST */ + GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */ + GPIO19_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */ /* EMU */ GPIO120_GPIO, /* EMU_MUX1 */ @@ -248,8 +255,8 @@ static unsigned long gen2_pin_config[] __initdata = { GPIO48_CIF_DD_5, GPIO93_CIF_DD_6, GPIO12_CIF_DD_7, - GPIO50_GPIO, /* CAM_EN */ - GPIO28_GPIO, /* CAM_RST */ + GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */ + GPIO28_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */ GPIO17_GPIO, /* CAM_FLASH */ }; #endif @@ -683,6 +690,81 @@ static struct platform_device a780_gpio_keys = { }, }; +/* camera */ +static int a780_camera_init(void) +{ + int err; + + /* + * GPIO50_nCAM_EN is active low + * GPIO19_GEN1_CAM_RST is active on rising edge + */ + err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN"); + if (err) { + pr_err("%s: Failed to request nCAM_EN\n", __func__); + goto fail; + } + + err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST"); + if (err) { + pr_err("%s: Failed to request CAM_RST\n", __func__); + goto fail_gpio_cam_rst; + } + + gpio_direction_output(GPIO50_nCAM_EN, 1); + gpio_direction_output(GPIO19_GEN1_CAM_RST, 0); + + return 0; + +fail_gpio_cam_rst: + gpio_free(GPIO50_nCAM_EN); +fail: + return err; +} + +static int a780_camera_power(struct device *dev, int on) +{ + gpio_set_value(GPIO50_nCAM_EN, !on); + return 0; +} + +static int a780_camera_reset(struct device *dev) +{ + gpio_set_value(GPIO19_GEN1_CAM_RST, 0); + msleep(10); + gpio_set_value(GPIO19_GEN1_CAM_RST, 1); + + return 0; +} + +struct pxacamera_platform_data a780_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 5000, +}; + +static struct i2c_board_info a780_camera_i2c_board_info = { + I2C_BOARD_INFO("mt9m111", 0x5d), +}; + +static struct soc_camera_link a780_iclink = { + .bus_id = 0, + .flags = SOCAM_SENSOR_INVERT_PCLK, + .i2c_adapter_id = 0, + .board_info = &a780_camera_i2c_board_info, + .module_name = "mt9m111", + .power = a780_camera_power, + .reset = a780_camera_reset, +}; + +static struct platform_device a780_camera = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &a780_iclink, + }, +}; + static struct platform_device *a780_devices[] __initdata = { &a780_gpio_keys, }; @@ -703,6 +785,11 @@ static void __init a780_init(void) pxa_set_keypad_info(&a780_keypad_platform_data); + if (a780_camera_init() == 0) { + pxa_set_camera_info(&a780_pxacamera_platform_data); + platform_device_register(&a780_camera); + } + platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); platform_add_devices(ARRAY_AND_SIZE(a780_devices)); } @@ -876,6 +963,80 @@ static struct platform_device a910_gpio_keys = { }, }; +/* camera */ +static int a910_camera_init(void) +{ + int err; + + /* + * GPIO50_nCAM_EN is active low + * GPIO28_GEN2_CAM_RST is active on rising edge + */ + err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN"); + if (err) { + pr_err("%s: Failed to request nCAM_EN\n", __func__); + goto fail; + } + + err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST"); + if (err) { + pr_err("%s: Failed to request CAM_RST\n", __func__); + goto fail_gpio_cam_rst; + } + + gpio_direction_output(GPIO50_nCAM_EN, 1); + gpio_direction_output(GPIO28_GEN2_CAM_RST, 0); + + return 0; + +fail_gpio_cam_rst: + gpio_free(GPIO50_nCAM_EN); +fail: + return err; +} + +static int a910_camera_power(struct device *dev, int on) +{ + gpio_set_value(GPIO50_nCAM_EN, !on); + return 0; +} + +static int a910_camera_reset(struct device *dev) +{ + gpio_set_value(GPIO28_GEN2_CAM_RST, 0); + msleep(10); + gpio_set_value(GPIO28_GEN2_CAM_RST, 1); + + return 0; +} + +struct pxacamera_platform_data a910_pxacamera_platform_data = { + .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | + PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, + .mclk_10khz = 5000, +}; + +static struct i2c_board_info a910_camera_i2c_board_info = { + I2C_BOARD_INFO("mt9m111", 0x5d), +}; + +static struct soc_camera_link a910_iclink = { + .bus_id = 0, + .i2c_adapter_id = 0, + .board_info = &a910_camera_i2c_board_info, + .module_name = "mt9m111", + .power = a910_camera_power, + .reset = a910_camera_reset, +}; + +static struct platform_device a910_camera = { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &a910_iclink, + }, +}; + static struct platform_device *a910_devices[] __initdata = { &a910_gpio_keys, }; @@ -896,6 +1057,11 @@ static void __init a910_init(void) pxa_set_keypad_info(&a910_keypad_platform_data); + if (a910_camera_init() == 0) { + pxa_set_camera_info(&a910_pxacamera_platform_data); + platform_device_register(&a910_camera); + } + platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); platform_add_devices(ARRAY_AND_SIZE(a910_devices)); } -- cgit v1.2.3-70-g09d2 From 87303b8a9e162e6c9746e3b9dacb40cf3e3e5e62 Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Tue, 3 Nov 2009 17:45:33 +0100 Subject: [ARM] pxa/ezx: add leds-lp3944 support for A910 EZX phone Signed-off-by: Antonio Ospite Signed-off-by: Eric Miao --- arch/arm/mach-pxa/ezx.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 320e2f8c599..626c82b1397 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -1037,6 +1038,57 @@ static struct platform_device a910_camera = { }, }; +/* leds-lp3944 */ +static struct lp3944_platform_data a910_lp3944_leds = { + .leds_size = LP3944_LEDS_MAX, + .leds = { + [0] = { + .name = "a910:red:", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED, + }, + [1] = { + .name = "a910:green:", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED, + }, + [2] { + .name = "a910:blue:", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED, + }, + /* Leds 3 and 4 are used as display power switches */ + [3] = { + .name = "a910::cli_display", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED_INVERTED + }, + [4] = { + .name = "a910::main_display", + .status = LP3944_LED_STATUS_ON, + .type = LP3944_LED_TYPE_LED_INVERTED + }, + [5] = { .type = LP3944_LED_TYPE_NONE }, + [6] = { + .name = "a910::torch", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED, + }, + [7] = { + .name = "a910::flash", + .status = LP3944_LED_STATUS_OFF, + .type = LP3944_LED_TYPE_LED_INVERTED, + }, + }, +}; + +static struct i2c_board_info __initdata a910_i2c_board_info[] = { + { + I2C_BOARD_INFO("lp3944", 0x60), + .platform_data = &a910_lp3944_leds, + }, +}; + static struct platform_device *a910_devices[] __initdata = { &a910_gpio_keys, }; @@ -1052,6 +1104,7 @@ static void __init a910_init(void) pxa_set_stuart_info(NULL); pxa_set_i2c_info(NULL); + i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); set_pxa_fb_info(&ezx_fb_info_2); -- cgit v1.2.3-70-g09d2 From 2fd8e55e13daecc729e893636a06b5133d872852 Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Wed, 4 Nov 2009 22:35:01 +0100 Subject: [ARM] pxa/ezx: update ezx_defconfig now that ezx-pcap is in Signed-off-by: Antonio Ospite Signed-off-by: Eric Miao --- arch/arm/configs/ezx_defconfig | 947 +++++++++++++++++++++++++++++------------ 1 file changed, 667 insertions(+), 280 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index d5ee16e6abf..492f29aba33 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc3 -# Mon Jul 7 17:52:21 2008 +# Linux kernel version: 2.6.32-rc5 +# Mon Nov 2 13:18:50 2009 # CONFIG_ARM=y CONFIG_HAVE_PWM=y @@ -9,24 +9,22 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_AOUT=y -CONFIG_ZONE_DMA=y CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -35,7 +33,7 @@ CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="-ezxdev" +CONFIG_LOCALVERSION="-ezx200910312315" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y @@ -44,56 +42,78 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -# CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -101,12 +121,10 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_LBDAF is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -120,25 +138,27 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" -CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -146,39 +166,64 @@ CONFIG_CLASSIC_RCU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set CONFIG_ARCH_PXA=y +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM7X00A is not set +# CONFIG_ARCH_BCMRING is not set # # Intel PXA2xx/PXA3xx Implementations # # CONFIG_ARCH_GUMSTIX is not set +# CONFIG_MACH_INTELMOTE2 is not set +# CONFIG_MACH_STARGATE2 is not set # CONFIG_ARCH_LUBBOCK is not set # CONFIG_MACH_LOGICPD_PXA270 is not set # CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_MP900C is not set +# CONFIG_MACH_BALLOON3 is not set # CONFIG_ARCH_PXA_IDP is not set # CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_VIPER is not set # CONFIG_ARCH_PXA_ESERIES is not set -# CONFIG_MACH_TRIZEPS4 is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_H5000 is not set # CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_EXEDA is not set # CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_COLIBRI300 is not set +# CONFIG_MACH_COLIBRI320 is not set # CONFIG_MACH_ZYLONITE is not set # CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_TAVOREVB is not set +# CONFIG_MACH_SAAR is not set # CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_CM_X300 is not set +# CONFIG_MACH_H4700 is not set # CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_MIOA701 is not set # CONFIG_MACH_PCM027 is not set +# CONFIG_ARCH_PXA_PALM is not set +# CONFIG_MACH_CSB726 is not set CONFIG_PXA_EZX=y CONFIG_MACH_EZX_A780=y CONFIG_MACH_EZX_E680=y @@ -186,17 +231,11 @@ CONFIG_MACH_EZX_A1200=y CONFIG_MACH_EZX_A910=y CONFIG_MACH_EZX_E6=y CONFIG_MACH_EZX_E2=y +# CONFIG_MACH_XCEP is not set CONFIG_PXA27x=y CONFIG_PXA_SSP=y -CONFIG_PXA_PWM=y - -# -# Boot options -# - -# -# Power management -# +CONFIG_PXA_HAVE_BOARD_IRQS=y +CONFIG_PLAT_PXA=y # # Processor Type @@ -205,7 +244,7 @@ CONFIG_CPU_32=y CONFIG_CPU_XSCALE=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y @@ -216,9 +255,10 @@ CONFIG_CPU_CP15_MMU=y # CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_IWMMXT=y CONFIG_XSCALE_PMU=y +CONFIG_COMMON_CLKDEV=y # # Bus support @@ -231,44 +271,71 @@ CONFIG_XSCALE_PMU=y # Kernel Features # CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set +CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=1 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" +CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" # CONFIG_XIP_KERNEL is not set CONFIG_KEXEC=y CONFIG_ATAGS_PROC=y # -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_DEBUG=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y # # Floating point emulation @@ -285,6 +352,8 @@ CONFIG_FPE_NWFPE=y # Userspace binary formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y CONFIG_BINFMT_AOUT=m CONFIG_BINFMT_MISC=m @@ -297,11 +366,8 @@ CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME=y CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# Networking -# CONFIG_NET=y # @@ -315,6 +381,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -342,7 +409,6 @@ CONFIG_INET_TUNNEL=m CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set -# CONFIG_IP_VS is not set CONFIG_IPV6=m # CONFIG_IPV6_PRIVACY is not set # CONFIG_IPV6_ROUTER_PREF is not set @@ -393,18 +459,22 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +# CONFIG_NETFILTER_TPROXY is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set # CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set # CONFIG_NETFILTER_XT_TARGET_TRACE is not set CONFIG_NETFILTER_XT_TARGET_TCPMSS=m # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m @@ -413,20 +483,23 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m # CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m @@ -434,20 +507,21 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_IP_VS is not set # # IP: Netfilter Configuration # +CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m CONFIG_NF_CONNTRACK_PROC_COMPAT=y CONFIG_IP_NF_QUEUE=m CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_RECENT=m -CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_LOG=m @@ -455,8 +529,8 @@ CONFIG_IP_NF_TARGET_ULOG=m CONFIG_NF_NAT=m CONFIG_NF_NAT_NEEDED=y CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m CONFIG_NF_NAT_SNMP_BASIC=m CONFIG_NF_NAT_PROTO_GRE=m CONFIG_NF_NAT_PROTO_UDPLITE=m @@ -469,9 +543,9 @@ CONFIG_NF_NAT_PPTP=m CONFIG_NF_NAT_H323=m CONFIG_NF_NAT_SIP=m CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m @@ -483,30 +557,29 @@ CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NF_CONNTRACK_IPV6=m CONFIG_IP6_NF_QUEUE=m CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_RAW=m - -# -# Bridge: Netfilter Configuration -# # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set +CONFIG_STP=m CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=m @@ -517,9 +590,11 @@ CONFIG_LLC=m # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y -CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing @@ -529,64 +604,34 @@ CONFIG_NET_SCH_FIFO=y # CONFIG_CAN is not set # CONFIG_IRDA is not set CONFIG_BT=y -CONFIG_BT_L2CAP=m +CONFIG_BT_L2CAP=y CONFIG_BT_SCO=y -CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m +CONFIG_BT_BNEP=y CONFIG_BT_BNEP_MC_FILTER=y CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m +CONFIG_BT_HIDP=y # # Bluetooth device drivers # -# CONFIG_BT_HCIUSB is not set -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y # CONFIG_BT_HCIUART_BCSP is not set # CONFIG_BT_HCIUART_LL is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBPA10X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIVHCI is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y - -# -# Wireless -# -CONFIG_CFG80211=m -CONFIG_NL80211=y -CONFIG_WIRELESS_EXT=y -CONFIG_MAC80211=m - -# -# Rate control algorithm selection -# -CONFIG_MAC80211_RC_DEFAULT_PID=y -# CONFIG_MAC80211_RC_DEFAULT_NONE is not set - -# -# Selecting 'y' for an algorithm will -# - -# -# build the algorithm into mac80211. -# -CONFIG_MAC80211_RC_DEFAULT="pid" -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_MESH is not set -CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set -# CONFIG_MAC80211_DEBUG is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -598,13 +643,19 @@ CONFIG_IEEE80211_CRYPT_TKIP=m # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -616,9 +667,9 @@ CONFIG_MTD_PARTITIONS=y # User Modules And Translation Layers # CONFIG_MTD_CHAR=y -# CONFIG_MTD_BLKDEVS is not set -# CONFIG_MTD_BLOCK is not set -# CONFIG_MTD_BLOCK_RO is not set +CONFIG_HAVE_MTD_OTP=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set @@ -647,7 +698,7 @@ CONFIG_MTD_CFI_I1=y # CONFIG_MTD_CFI_I2 is not set # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set +CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set @@ -655,19 +706,15 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -CONFIG_MTD_XIP=y +# CONFIG_MTD_XIP is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PHYSMAP_START=0x0 -CONFIG_MTD_PHYSMAP_LEN=0x0 -CONFIG_MTD_PHYSMAP_BANKWIDTH=2 -# CONFIG_MTD_PXA2XX is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PXA2XX=y # CONFIG_MTD_ARM_INTEGRATOR is not set -# CONFIG_MTD_SHARP_SL is not set # CONFIG_MTD_PLATRAM is not set # @@ -675,6 +722,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # # CONFIG_MTD_DATAFLASH is not set # CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -689,6 +737,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + # # UBI - Unsorted block images # @@ -700,15 +753,14 @@ CONFIG_BLK_DEV_LOOP=m CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_NBD=m # CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -CONFIG_MISC_DEVICES=y -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -722,7 +774,6 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set CONFIG_DUMMY=y # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -732,13 +783,11 @@ CONFIG_DUMMY=y # CONFIG_NET_ETHERNET is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set # -# Wireless LAN +# Enable WiMAX (Networking options) to see the WiMAX drivers # -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -765,6 +814,7 @@ CONFIG_SLHC=m # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support @@ -786,29 +836,45 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_OPENCORES is not set CONFIG_KEYBOARD_PXA27x=y -CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_UCB1400 is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set CONFIG_TOUCHSCREEN_PCAP=y CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATI_REMOTE is not set @@ -816,7 +882,10 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +CONFIG_INPUT_PCAP=y # # Hardware I/O ports @@ -828,6 +897,7 @@ CONFIG_INPUT_UINPUT=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set @@ -842,92 +912,130 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_PXA=y CONFIG_SERIAL_PXA_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=8 # CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_NVRAM is not set +# CONFIG_HW_RANDOM is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set CONFIG_I2C_PXA=y # CONFIG_I2C_PXA_SLAVE is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_STUB is not set # CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# # CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_TPS65010 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y # # SPI Master Controller Drivers # # CONFIG_SPI_BITBANG is not set -CONFIG_SPI_PXA2XX=m +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_PXA2XX=y # # SPI Protocol Masters # -# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set -CONFIG_HAVE_GPIO_LIB=y # -# GPIO Support +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: # # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# +# PCI GPIO expanders: +# + # # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set # CONFIG_HWMON is not set +# CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # @@ -938,54 +1046,170 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set CONFIG_EZX_PCAP=y - -# -# Multimedia devices -# +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_LP3971 is not set +CONFIG_REGULATOR_PCAP=y +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y CONFIG_VIDEO_ALLOW_V4L1=y CONFIG_VIDEO_V4L1_COMPAT=y # CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=m +CONFIG_VIDEO_MEDIA=y # # Multimedia drivers # # CONFIG_MEDIA_ATTACH is not set -CONFIG_MEDIA_TUNER=m -# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_SG=y CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_ADV_DEBUG is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set # CONFIG_VIDEO_VIVI is not set # CONFIG_VIDEO_CPIA is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_SAA5246A is not set # CONFIG_VIDEO_SAA5249 is not set -# CONFIG_TUNER_3036 is not set +CONFIG_SOC_CAMERA=y +# CONFIG_SOC_CAMERA_MT9M001 is not set +CONFIG_SOC_CAMERA_MT9M111=y +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_SOC_CAMERA_OV772X is not set +CONFIG_VIDEO_PXA27x=y +# CONFIG_VIDEO_SH_MOBILE_CEU is not set # CONFIG_V4L_USB_DRIVERS is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_VIDEO_PXA27x is not set CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set # CONFIG_USB_DSBR is not set -# CONFIG_USB_SI470X is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +CONFIG_RADIO_TEA5764=y +CONFIG_RADIO_TEA5764_XTAL=y # CONFIG_DAB is not set # @@ -996,6 +1220,7 @@ CONFIG_RADIO_ADAPTERS=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y @@ -1017,15 +1242,19 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set CONFIG_FB_PXA=y +CONFIG_FB_PXA_OVERLAY=y # CONFIG_FB_PXA_SMARTPANEL is not set CONFIG_FB_PXA_PARAMETERS=y # CONFIG_FB_MBX is not set -# CONFIG_FB_AM200EPD is not set +# CONFIG_FB_W100 is not set # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set +CONFIG_BACKLIGHT_GENERIC=y CONFIG_BACKLIGHT_PWM=y # @@ -1053,85 +1282,60 @@ CONFIG_FONT_MINI_4x6=y # CONFIG_FONT_SUN12x22 is not set # CONFIG_FONT_10x18 is not set # CONFIG_LOGO is not set - -# -# Sound -# CONFIG_SOUND=y - -# -# Advanced Linux Sound Architecture -# +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y +CONFIG_SND_JACK=y # CONFIG_SND_SEQUENCER is not set CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y CONFIG_SND_PCM_OSS=y CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set - -# -# ALSA ARM devices -# -# CONFIG_SND_PXA2XX_AC97 is not set - -# -# SPI devices -# - -# -# USB devices -# -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set - -# -# System on Chip audio support -# +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_PXA2XX_LIB=y +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set CONFIG_SND_SOC=y CONFIG_SND_PXA2XX_SOC=y - -# -# ALSA SoC audio for Freescale SOCs -# - -# -# SoC Audio for the Texas Instruments OMAP -# - -# -# Open Sound System -# +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y -# CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # # USB Input Devices # # CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_APPLE=m +# CONFIG_HID_WACOM is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y @@ -1150,32 +1354,42 @@ CONFIG_USB=y # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # -# may also be needed; see USB_STORAGE Help for more information +# also be needed; see USB_STORAGE Help for more info # # CONFIG_USB_LIBUSUAL is not set @@ -1183,7 +1397,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # USB Imaging devices # # CONFIG_USB_MDC800 is not set -# CONFIG_USB_MON is not set # # USB port drivers @@ -1196,7 +1409,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1204,62 +1417,94 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set # CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_R8A66597 is not set CONFIG_USB_GADGET_PXA27X=y CONFIG_USB_PXA27X=y -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set # CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set # CONFIG_USB_GADGET_DUALSPEED is not set # CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set CONFIG_USB_ETH=y # CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_ETH_EEM is not set # CONFIG_USB_GADGETFS is not set # CONFIG_USB_FILE_STORAGE is not set # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set # CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y # -# MMC/SD Card Drivers +# MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y -CONFIG_SDIO_UART=y +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set # -# MMC/SD Host Controller Drivers +# MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_PXA=y -# CONFIG_MMC_SPI is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +CONFIG_MMC_SPI=y +# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # # LED drivers # +# CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_LP3944=y +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set # # LED Triggers @@ -1267,7 +1512,14 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -1297,32 +1549,52 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # -CONFIG_RTC_DRV_SA1100=m +# CONFIG_RTC_DRV_SA1100 is not set +# CONFIG_RTC_DRV_PXA is not set +CONFIG_RTC_DRV_PCAP=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + # # File systems # @@ -1330,12 +1602,14 @@ CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set -# CONFIG_EXT4DEV_FS is not set +# CONFIG_EXT4_FS is not set CONFIG_JBD=m -CONFIG_FS_MBCACHE=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=m CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set @@ -1350,6 +1624,10 @@ CONFIG_XFS_FS=m # CONFIG_XFS_RT is not set # CONFIG_XFS_DEBUG is not set # CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1357,6 +1635,12 @@ CONFIG_INOTIFY_USER=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m +CONFIG_CUSE=m + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems @@ -1381,15 +1665,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1397,13 +1679,35 @@ CONFIG_TMPFS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -# CONFIG_JFFS2_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y @@ -1411,19 +1715,18 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set +# CONFIG_ROOT_NFS is not set CONFIG_NFSD=m CONFIG_NFSD_V2_ACL=y CONFIG_NFSD_V3=y CONFIG_NFSD_V3_ACL=y # CONFIG_NFSD_V4 is not set -# CONFIG_ROOT_NFS is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1490,25 +1793,83 @@ CONFIG_NLS_UTF8=m # # Kernel hacking # -# CONFIG_PRINTK_TIME is not set +CONFIG_PRINTK_TIME=y CONFIG_ENABLE_WARN_DEPRECATED=y -# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set +CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_PROVE_LOCKING=y +CONFIG_LOCKDEP=y +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_TRACE_IRQFLAGS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set -# CONFIG_DEBUG_USER is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y @@ -1516,12 +1877,20 @@ CONFIG_CRYPTO=y # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_ALGAPI2=m CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=m CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=m CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH2=m +CONFIG_CRYPTO_RNG2=m +CONFIG_CRYPTO_PCOMP=m CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=m CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=m CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m @@ -1549,14 +1918,20 @@ CONFIG_CRYPTO_XTS=m # CONFIG_CRYPTO_HMAC=m CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m # # Digest # CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=m CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m @@ -1587,28 +1962,40 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m # Compression # CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set -# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m -CONFIG_CRC16=m -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y CONFIG_CRC32=y -# CONFIG_CRC7 is not set +CONFIG_CRC7=y CONFIG_LIBCRC32C=m -CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m CONFIG_TEXTSEARCH_BM=m CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- cgit v1.2.3-70-g09d2 From 3fe6ccffcbc6c79512fe9bea5c10de75ae0c497e Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 14 Nov 2009 15:53:14 +0100 Subject: [ARM] pxa/viper: convert to use plat_serial8250_port irqflags field Use .irqflags in the plat_serial8250_port structure to set IRQ polarity, and get rid of the corresponding set_irq_type(). Signed-off-by: Marc Zyngier Signed-off-by: Eric Miao --- arch/arm/mach-pxa/viper.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 6c36bd9f3b5..cf0d71b7797 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -301,15 +301,6 @@ static void __init viper_init_irq(void) set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), viper_irq_handler); set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); - -#ifndef CONFIG_SERIAL_PXA - /* - * 8250 doesn't support IRQ_TYPE being passed as part - * of the plat_serial8250_port structure... - */ - set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING); - set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING); -#endif } /* Flat Panel */ @@ -539,6 +530,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .mapbase = VIPER_UARTA_PHYS, .irq = gpio_to_irq(VIPER_UARTA_GPIO), + .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1, .iotype = UPIO_MEM, @@ -548,6 +540,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .mapbase = VIPER_UARTB_PHYS, .irq = gpio_to_irq(VIPER_UARTB_GPIO), + .irqflags = IRQF_TRIGGER_RISING, .uartclk = 1843200, .regshift = 1, .iotype = UPIO_MEM, -- cgit v1.2.3-70-g09d2 From 55052ea23d09ebe71ebeadc054e828b37d4e0356 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:18 +0200 Subject: [ARM] pxa/cm-x300: add revision difference handling Different revisions of CM-X300 use different pins for several functions. Make the kernel aware of it. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 33 ++++++++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 7f2e87839a8..07d7473344b 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -137,7 +137,6 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { GPIO36_UART1_DTR, /* GPIOs */ - GPIO79_GPIO, /* LED */ GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ GPIO85_GPIO, /* MMC WP */ GPIO99_GPIO, /* Ethernet IRQ */ @@ -153,6 +152,20 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { GPIO22_I2C_SDA, }; +static mfp_cfg_t cm_x300_rev_lt130_mfp_cfg[] __initdata = { + /* GPIOs */ + GPIO79_GPIO, /* LED */ + GPIO77_GPIO, /* WiFi reset */ + GPIO78_GPIO, /* BT reset */ +}; + +static mfp_cfg_t cm_x300_rev_ge130_mfp_cfg[] __initdata = { + /* GPIOs */ + GPIO76_GPIO, /* LED */ + GPIO71_GPIO, /* WiFi reset */ + GPIO70_GPIO, /* BT reset */ +}; + #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) static struct resource dm9000_resources[] = { [0] = { @@ -351,7 +364,6 @@ static struct gpio_led cm_x300_leds[] = { [0] = { .name = "cm-x300:green", .default_trigger = "heartbeat", - .gpio = 79, .active_low = 1, }, }; @@ -371,6 +383,11 @@ static struct platform_device cm_x300_led_device = { static void __init cm_x300_init_leds(void) { + if (system_rev < 130) + cm_x300_leds[0].gpio = 79; + else + cm_x300_leds[0].gpio = 76; + platform_device_register(&cm_x300_led_device); } #else @@ -433,11 +450,21 @@ static void __init cm_x300_init_rtc(void) static inline void cm_x300_init_rtc(void) {} #endif -static void __init cm_x300_init(void) +static void __init cm_x300_init_mfp(void) { /* board-processor specific GPIO initialization */ pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg)); + if (system_rev < 130) + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_rev_lt130_mfp_cfg)); + else + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_rev_ge130_mfp_cfg)); +} + +static void __init cm_x300_init(void) +{ + cm_x300_init_mfp(); + pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); -- cgit v1.2.3-70-g09d2 From 83e560eee12b3215c193338496090838e5f6d1cb Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:19 +0200 Subject: [ARM] pxa/cm-x300: add TDO35S lcd support Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 60 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 07d7473344b..ecee7e82911 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -26,6 +26,10 @@ #include #include +#include +#include +#include + #include #include #include @@ -208,17 +212,18 @@ static void __init cm_x300_init_dm9000(void) static inline void cm_x300_init_dm9000(void) {} #endif +/* LCD */ #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) static struct pxafb_mode_info cm_x300_lcd_modes[] = { [0] = { - .pixclock = 38000, + .pixclock = 38250, .bpp = 16, .xres = 480, .yres = 640, .hsync_len = 8, .vsync_len = 2, .left_margin = 8, - .upper_margin = 0, + .upper_margin = 2, .right_margin = 24, .lower_margin = 4, .cmap_greyscale = 0, @@ -240,7 +245,7 @@ static struct pxafb_mode_info cm_x300_lcd_modes[] = { static struct pxafb_mach_info cm_x300_lcd = { .modes = cm_x300_lcd_modes, - .num_modes = 2, + .num_modes = ARRAY_SIZE(cm_x300_lcd_modes), .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, }; @@ -252,6 +257,54 @@ static void __init cm_x300_init_lcd(void) static inline void cm_x300_init_lcd(void) {} #endif +#if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE) +#define GPIO_LCD_BASE (144) +#define GPIO_LCD_DIN (GPIO_LCD_BASE + 8) /* aux_gpio3_0 */ +#define GPIO_LCD_DOUT (GPIO_LCD_BASE + 9) /* aux_gpio3_1 */ +#define GPIO_LCD_SCL (GPIO_LCD_BASE + 10) /* aux_gpio3_2 */ +#define GPIO_LCD_CS (GPIO_LCD_BASE + 11) /* aux_gpio3_3 */ +#define LCD_SPI_BUS_NUM (1) + +static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = { + .sck = GPIO_LCD_SCL, + .mosi = GPIO_LCD_DIN, + .miso = GPIO_LCD_DOUT, + .num_chipselect = 1, +}; + +static struct platform_device cm_x300_spi_gpio = { + .name = "spi_gpio", + .id = LCD_SPI_BUS_NUM, + .dev = { + .platform_data = &cm_x300_spi_gpio_pdata, + }, +}; + +static struct tdo24m_platform_data cm_x300_tdo24m_pdata = { + .model = TDO35S, +}; + +static struct spi_board_info cm_x300_spi_devices[] __initdata = { + { + .modalias = "tdo24m", + .max_speed_hz = 1000000, + .bus_num = LCD_SPI_BUS_NUM, + .chip_select = 0, + .controller_data = (void *) GPIO_LCD_CS, + .platform_data = &cm_x300_tdo24m_pdata, + }, +}; + +static void __init cm_x300_init_spi(void) +{ + spi_register_board_info(cm_x300_spi_devices, + ARRAY_SIZE(cm_x300_spi_devices)); + platform_device_register(&cm_x300_spi_gpio); +} +#else +static inline void cm_x300_init_spi(void) {} +#endif + #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) static struct mtd_partition cm_x300_nand_partitions[] = { [0] = { @@ -476,6 +529,7 @@ static void __init cm_x300_init(void) cm_x300_init_nand(); cm_x300_init_leds(); cm_x300_init_i2c(); + cm_x300_init_spi(); cm_x300_init_rtc(); } -- cgit v1.2.3-70-g09d2 From 74e74defd6c471fc7ec108e64cb953164940a122 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:20 +0200 Subject: [ARM] pxa/cm-x300: add ac97 controller registration Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index ecee7e82911..8726dc7c73a 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -40,6 +40,7 @@ #include #include #include +#include #include @@ -305,6 +306,15 @@ static void __init cm_x300_init_spi(void) static inline void cm_x300_init_spi(void) {} #endif +#if defined(CONFIG_SND_PXA2XX_LIB_AC97) +static void __init cm_x300_init_ac97(void) +{ + pxa_set_ac97_info(NULL); +} +#else +static inline void cm_x300_init_ac97(void) {} +#endif + #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) static struct mtd_partition cm_x300_nand_partitions[] = { [0] = { @@ -531,6 +541,7 @@ static void __init cm_x300_init(void) cm_x300_init_i2c(); cm_x300_init_spi(); cm_x300_init_rtc(); + cm_x300_init_ac97(); } static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, -- cgit v1.2.3-70-g09d2 From b3d01da66d45504f8bdc6fbc9c0c1f1705ebc251 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:21 +0200 Subject: [ARM] pxa/cm-x300: add Wi2Wi chip (Bluetooth and WiFi) initialization Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 8726dc7c73a..9a21bc567ca 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -513,6 +514,42 @@ static void __init cm_x300_init_rtc(void) static inline void cm_x300_init_rtc(void) {} #endif +static void __init cm_x300_init_wi2wi(void) +{ + int bt_reset, wlan_en; + int err; + + if (system_rev < 130) { + wlan_en = 77; + bt_reset = 78; + } else { + wlan_en = 71; + bt_reset = 70; + } + + /* Libertas and CSR reset */ + err = gpio_request(wlan_en, "wlan en"); + if (err) { + pr_err("CM-X300: failed to request wlan en gpio: %d\n", err); + } else { + gpio_direction_output(wlan_en, 1); + gpio_free(wlan_en); + } + + err = gpio_request(bt_reset, "bt reset"); + if (err) { + pr_err("CM-X300: failed to request bt reset gpio: %d\n", err); + } else { + gpio_direction_output(bt_reset, 1); + udelay(10); + gpio_set_value(bt_reset, 0); + udelay(10); + gpio_set_value(bt_reset, 1); + gpio_free(bt_reset); + } +} + +/* MFP */ static void __init cm_x300_init_mfp(void) { /* board-processor specific GPIO initialization */ @@ -542,6 +579,7 @@ static void __init cm_x300_init(void) cm_x300_init_spi(); cm_x300_init_rtc(); cm_x300_init_ac97(); + cm_x300_init_wi2wi(); } static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, -- cgit v1.2.3-70-g09d2 From def8252ddb9bc52434b2ac1d560a609c61849638 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:22 +0200 Subject: [ARM] pxa/cm-x300: add support for PXA310 cpu CM-X300 can be assembled with PXA300 and PXA310 CPU. Provide support for both CPU variants. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 42 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 9a21bc567ca..d9006c271e8 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -59,7 +59,7 @@ #define GPIO97_RTC_RD (97) #define GPIO98_RTC_IO (98) -static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { +static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = { /* LCD */ GPIO54_LCD_LDD_0, GPIO55_LCD_LDD_1, @@ -158,20 +158,47 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { GPIO22_I2C_SDA, }; -static mfp_cfg_t cm_x300_rev_lt130_mfp_cfg[] __initdata = { +static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = { /* GPIOs */ GPIO79_GPIO, /* LED */ GPIO77_GPIO, /* WiFi reset */ GPIO78_GPIO, /* BT reset */ }; -static mfp_cfg_t cm_x300_rev_ge130_mfp_cfg[] __initdata = { +static mfp_cfg_t cm_x3xx_rev_ge130_mfp_cfg[] __initdata = { /* GPIOs */ GPIO76_GPIO, /* LED */ GPIO71_GPIO, /* WiFi reset */ GPIO70_GPIO, /* BT reset */ }; +static mfp_cfg_t cm_x310_mfp_cfg[] __initdata = { + /* USB PORT 2 */ + ULPI_STP, + ULPI_NXT, + ULPI_DIR, + GPIO30_ULPI_DATA_OUT_0, + GPIO31_ULPI_DATA_OUT_1, + GPIO32_ULPI_DATA_OUT_2, + GPIO33_ULPI_DATA_OUT_3, + GPIO34_ULPI_DATA_OUT_4, + GPIO35_ULPI_DATA_OUT_5, + GPIO36_ULPI_DATA_OUT_6, + GPIO37_ULPI_DATA_OUT_7, + GPIO38_ULPI_CLK, + /* external PHY reset pin */ + GPIO127_GPIO, + + /* USB PORT 3 */ + GPIO77_USB_P3_1, + GPIO78_USB_P3_2, + GPIO79_USB_P3_3, + GPIO80_USB_P3_4, + GPIO81_USB_P3_5, + GPIO82_USB_P3_6, + GPIO0_2_USBH_PEN, +}; + #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) static struct resource dm9000_resources[] = { [0] = { @@ -553,12 +580,15 @@ static void __init cm_x300_init_wi2wi(void) static void __init cm_x300_init_mfp(void) { /* board-processor specific GPIO initialization */ - pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg)); + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_mfp_cfg)); if (system_rev < 130) - pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_rev_lt130_mfp_cfg)); + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_lt130_mfp_cfg)); else - pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_rev_ge130_mfp_cfg)); + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_ge130_mfp_cfg)); + + if (cpu_is_pxa310()) + pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x310_mfp_cfg)); } static void __init cm_x300_init(void) -- cgit v1.2.3-70-g09d2 From edaa64c906f1e977396d0bd868079ee632583149 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:23 +0200 Subject: [ARM] pxa/cm-x300: enable USB port 2 for PXA300 Port 2 requires setting of UP2OCR register to function as USB host. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index d9006c271e8..2142fe74666 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include @@ -437,9 +438,19 @@ static inline void cm_x300_init_mmc(void) {} #endif #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) +static int cm_x300_ohci_init(struct device *dev) +{ + if (cpu_is_pxa300()) + UP2OCR = UP2OCR_HXS + | UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE; + + return 0; +} + static struct pxaohci_platform_data cm_x300_ohci_platform_data = { .port_mode = PMM_PERPORT_MODE, - .flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW, + .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW, + .init = cm_x300_ohci_init, }; static void __init cm_x300_init_ohci(void) -- cgit v1.2.3-70-g09d2 From 9c017ca1a0782ccfe26bfb36f03a9ba09370d7f7 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:24 +0200 Subject: [ARM] pxa/cm-x300: add da9030 support Register DA9030 PMIC. Use only backlight sub-device for now. Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 2142fe74666..8aedc60aaa6 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -27,6 +27,8 @@ #include #include +#include + #include #include #include @@ -552,6 +554,35 @@ static void __init cm_x300_init_rtc(void) static inline void cm_x300_init_rtc(void) {} #endif +/* DA9030 */ +struct da903x_subdev_info cm_x300_da9030_subdevs[] = { + { + .name = "da903x-backlight", + .id = DA9030_ID_WLED, + } +}; + +static struct da903x_platform_data cm_x300_da9030_info = { + .num_subdevs = ARRAY_SIZE(cm_x300_da9030_subdevs), + .subdevs = cm_x300_da9030_subdevs, +}; + +static struct i2c_board_info cm_x300_pmic_info = { + I2C_BOARD_INFO("da9030", 0x49), + .irq = IRQ_GPIO(0), + .platform_data = &cm_x300_da9030_info, +}; + +static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = { + .use_pio = 1, +}; + +static void __init cm_x300_init_da9030(void) +{ + pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); + i2c_register_board_info(1, &cm_x300_pmic_info, 1); +} + static void __init cm_x300_init_wi2wi(void) { int bt_reset, wlan_en; @@ -610,6 +641,7 @@ static void __init cm_x300_init(void) pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); + cm_x300_init_da9030(); cm_x300_init_dm9000(); cm_x300_init_lcd(); cm_x300_init_ohci(); -- cgit v1.2.3-70-g09d2 From 14fd9e00538fa0271602bb529f094285c6e596d6 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:25 +0200 Subject: [ARM] pxa/cm-x300: update authors and copyright Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/cm-x300.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 8aedc60aaa6..d564d8ea5a3 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -3,9 +3,10 @@ * * Support for the CompuLab CM-X300 modules * - * Copyright (C) 2008 CompuLab Ltd. + * Copyright (C) 2008,2009 CompuLab Ltd. * * Mike Rapoport + * Igor Grinberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as -- cgit v1.2.3-70-g09d2 From 5fa46fca1c209b9fd1dbfd5bc680a236d9f78d54 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Wed, 14 Oct 2009 09:20:27 +0200 Subject: [ARM] pxa/cm-x300: update defconfig Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/configs/cm_x300_defconfig | 351 +++++++++++++++++++++++++------------ 1 file changed, 240 insertions(+), 111 deletions(-) (limited to 'arch') diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index d18d21bb41e..a0170867130 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig @@ -1,15 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30-rc8 -# Thu Jun 4 09:53:21 2009 +# Linux kernel version: 2.6.32-rc4 +# Tue Oct 13 19:03:13 2009 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -18,14 +16,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_HAS_CPUFREQ=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_MTD_XIP=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -46,11 +44,12 @@ CONFIG_SYSVIPC_SYSCTL=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 @@ -83,7 +82,6 @@ CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y @@ -96,6 +94,10 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y @@ -103,13 +105,17 @@ CONFIG_COMPAT_BRK=y CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_CLK=y -# CONFIG_SLOW_WORK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -117,11 +123,11 @@ CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -142,19 +148,22 @@ CONFIG_FREEZER=y # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -163,25 +172,27 @@ CONFIG_FREEZER=y # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set CONFIG_ARCH_PXA=y -# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_BCMRING is not set # # Intel PXA2xx/PXA3xx Implementations @@ -191,16 +202,19 @@ CONFIG_ARCH_PXA=y # Supported PXA3xx Processor Variants # CONFIG_CPU_PXA300=y -# CONFIG_CPU_PXA310 is not set +CONFIG_CPU_PXA310=y # CONFIG_CPU_PXA320 is not set # CONFIG_CPU_PXA930 is not set # CONFIG_CPU_PXA935 is not set +# CONFIG_CPU_PXA950 is not set # CONFIG_ARCH_GUMSTIX is not set # CONFIG_MACH_INTELMOTE2 is not set +# CONFIG_MACH_STARGATE2 is not set # CONFIG_ARCH_LUBBOCK is not set # CONFIG_MACH_LOGICPD_PXA270 is not set # CONFIG_MACH_MAINSTONE is not set # CONFIG_MACH_MP900C is not set +# CONFIG_MACH_BALLOON3 is not set # CONFIG_ARCH_PXA_IDP is not set # CONFIG_PXA_SHARPSL is not set # CONFIG_ARCH_VIPER is not set @@ -218,6 +232,7 @@ CONFIG_CPU_PXA300=y # CONFIG_MACH_SAAR is not set # CONFIG_MACH_ARMCORE is not set CONFIG_MACH_CM_X300=y +# CONFIG_MACH_H4700 is not set # CONFIG_MACH_MAGICIAN is not set # CONFIG_MACH_HIMALAYA is not set # CONFIG_MACH_MIOA701 is not set @@ -225,8 +240,8 @@ CONFIG_MACH_CM_X300=y # CONFIG_ARCH_PXA_PALM is not set # CONFIG_MACH_CSB726 is not set # CONFIG_PXA_EZX is not set +# CONFIG_MACH_XCEP is not set CONFIG_PXA3xx=y -# CONFIG_PXA_PWM is not set CONFIG_PLAT_PXA=y # @@ -236,7 +251,7 @@ CONFIG_CPU_32=y CONFIG_CPU_XSC3=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y @@ -246,11 +261,12 @@ CONFIG_IO_36=y # # Processor Features # -# CONFIG_ARM_THUMB is not set +CONFIG_ARM_THUMB=y # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_OUTER_CACHE=y CONFIG_CACHE_XSC3L2=y +CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_IWMMXT=y CONFIG_COMMON_CLKDEV=y @@ -272,11 +288,12 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -# CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_HIGHMEM=y @@ -292,17 +309,19 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096 CONFIG_ZONE_DMA_FLAG=0 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=jffs2 console=ttyS2,38400" +CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set @@ -355,6 +374,7 @@ CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y CONFIG_APM_EMULATION=y +# CONFIG_PM_RUNTIME is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_NET=y @@ -396,6 +416,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -410,6 +431,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set @@ -433,22 +455,27 @@ CONFIG_BT_HIDP=m # # Bluetooth device drivers # -# CONFIG_BT_HCIBTUSB is not set +CONFIG_BT_HCIBTUSB=m # CONFIG_BT_HCIBTSDIO is not set # CONFIG_BT_HCIUART is not set # CONFIG_BT_HCIBCM203X is not set # CONFIG_BT_HCIBPA10X is not set # CONFIG_BT_HCIBFUSB is not set # CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set +CONFIG_CFG80211_DEFAULT_PS_VALUE=0 # CONFIG_WIRELESS_OLD_REGULATORY is not set CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=m # CONFIG_LIB80211_DEBUG is not set -# CONFIG_MAC80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -461,6 +488,7 @@ CONFIG_LIB80211=m # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y @@ -472,9 +500,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set @@ -521,6 +549,9 @@ CONFIG_MTD_CFI_I2=y # # Self-contained MTD device drivers # +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -556,7 +587,15 @@ CONFIG_MTD_NAND_PXA3xx=y # # UBI - Unsorted block images # -# CONFIG_MTD_UBI is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set @@ -570,6 +609,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -593,10 +633,6 @@ CONFIG_BLK_DEV_SD=y # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -621,7 +657,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -636,6 +671,7 @@ CONFIG_MII=y CONFIG_DM9000=y CONFIG_DM9000_DEBUGLEVEL=0 CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y +# CONFIG_ENC28J60 is not set # CONFIG_ETHOC is not set # CONFIG_SMC911X is not set # CONFIG_SMSC911X is not set @@ -648,20 +684,20 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# +CONFIG_WLAN=y # CONFIG_WLAN_PRE80211 is not set CONFIG_WLAN_80211=y CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_USB is not set CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set # CONFIG_LIBERTAS_DEBUG is not set # CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set # CONFIG_HOSTAP is not set # @@ -683,6 +719,7 @@ CONFIG_LIBERTAS_SDIO=m # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support @@ -706,33 +743,51 @@ CONFIG_INPUT_EVDEV=y # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_OPENCORES is not set CONFIG_KEYBOARD_PXA27x=m -# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DA9034 is not set +# CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_WM97XX=m +# CONFIG_TOUCHSCREEN_WM9705 is not set +CONFIG_TOUCHSCREEN_WM9712=y +# CONFIG_TOUCHSCREEN_WM9713 is not set +# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set # CONFIG_INPUT_MISC is not set # @@ -760,6 +815,7 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_PXA=y CONFIG_SERIAL_PXA_CONSOLE=y CONFIG_SERIAL_CORE=y @@ -774,6 +830,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y # CONFIG_I2C_CHARDEV is not set CONFIG_I2C_HELPER_AUTO=y @@ -784,6 +841,7 @@ CONFIG_I2C_HELPER_AUTO=y # # I2C system bus drivers (mostly embedded / system-on-chip) # +# CONFIG_I2C_DESIGNWARE is not set # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set CONFIG_I2C_PXA=y @@ -807,19 +865,36 @@ CONFIG_I2C_PXA=y # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +# CONFIG_SPI_PXA2XX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set -# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_SYSFS=y # # Memory mapped GPIO expanders: @@ -839,11 +914,17 @@ CONFIG_GPIO_PCA953X=y # # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -860,32 +941,33 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set # CONFIG_TPS65010 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set -# CONFIG_PMIC_DA903X is not set +CONFIG_PMIC_DA903X=y # CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_DA903X=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -925,7 +1007,17 @@ CONFIG_FB_PXA=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI9320 is not set +CONFIG_LCD_TDO24M=y +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=m +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_DA903X=m # # Display device support @@ -956,38 +1048,48 @@ CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=m -# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m CONFIG_SND_JACK=y # CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DRIVERS is not set CONFIG_SND_ARM=y CONFIG_SND_PXA2XX_LIB=m +CONFIG_SND_PXA2XX_LIB_AC97=y # CONFIG_SND_PXA2XX_AC97 is not set -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_PXA2XX_SOC=m +CONFIG_SND_PXA2XX_SOC_AC97=m +CONFIG_SND_PXA2XX_SOC_EM_X270=m CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM9712=m # CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y -CONFIG_HID_DEBUG=y # CONFIG_HIDRAW is not set # @@ -1006,10 +1108,12 @@ CONFIG_HID_BELKIN=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y # CONFIG_DRAGONRISE_FF is not set CONFIG_HID_EZKEY=y CONFIG_HID_KYE=y CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LOGITECH=y # CONFIG_LOGITECH_FF is not set @@ -1023,9 +1127,15 @@ CONFIG_HID_PETALYNX=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y # CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y # CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_WACOM=m +CONFIG_HID_ZEROPLUS=y # CONFIG_ZEROPLUS_FF is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y @@ -1054,6 +1164,7 @@ CONFIG_USB_MON=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -1151,8 +1262,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_MMC_PXA=m # CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y @@ -1162,8 +1274,10 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_PCA9532 is not set CONFIG_LEDS_GPIO=y CONFIG_LEDS_GPIO_PLATFORM=y -# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DA903X is not set +# CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_BD2802 is not set # @@ -1179,6 +1293,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y # # iptables trigger is under Netfilter config (LED target) # +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y @@ -1210,10 +1325,19 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set # # Platform RTC drivers @@ -1233,12 +1357,15 @@ CONFIG_RTC_DRV_V3020=y # # on-CPU RTC drivers # -CONFIG_RTC_DRV_SA1100=y -# CONFIG_RTC_DRV_PXA is not set +# CONFIG_RTC_DRV_SA1100 is not set +CONFIG_RTC_DRV_PXA=y # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set -# CONFIG_REGULATOR is not set # CONFIG_UIO is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set # @@ -1256,10 +1383,13 @@ CONFIG_JBD=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1319,6 +1449,12 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1329,12 +1465,12 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y @@ -1378,7 +1514,7 @@ CONFIG_MSDOS_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=m +CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m # CONFIG_NLS_CODEPAGE_737 is not set @@ -1428,6 +1564,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set @@ -1441,6 +1578,7 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -1460,32 +1598,20 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y @@ -1509,7 +1635,6 @@ CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD2=y @@ -1551,11 +1676,13 @@ CONFIG_CRYPTO_ECB=m # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_MICHAEL_MIC=m @@ -1591,9 +1718,9 @@ CONFIG_CRYPTO_DES=y # # Compression # -# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_DEFLATE=y # CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_LZO=y # # Random Number Generation @@ -1608,7 +1735,7 @@ CONFIG_CRYPTO_DES=y CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set +CONFIG_CRC16=y CONFIG_CRC_T10DIF=y # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y @@ -1616,6 +1743,8 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_BZIP2=y CONFIG_DECOMPRESS_LZMA=y -- cgit v1.2.3-70-g09d2 From db205463fd24c0972ad2c4e4fafb1c76e51b4380 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Tue, 10 Nov 2009 14:18:41 +0200 Subject: [ARM] pxa/cm-x300: add PWM backlight support Signed-off-by: Igor Grinberg Signed-off-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/Kconfig | 1 + arch/arm/mach-pxa/cm-x300.c | 30 ++++++++++++++++++++++++++++++ arch/arm/mach-pxa/devices.c | 1 + 3 files changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 20e645a6943..d89c6adbe8b 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -226,6 +226,7 @@ config MACH_COLIBRI300 select PXA3xx select CPU_PXA300 select CPU_PXA310 + select HAVE_PWM config MACH_COLIBRI320 bool "Toradex Colibri PXA320" diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index d564d8ea5a3..d37cfa132a6 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -50,6 +51,7 @@ #include #include "generic.h" +#include "devices.h" #define CM_X300_ETH_PHYS 0x08000010 @@ -160,6 +162,9 @@ static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = { /* Standard I2C */ GPIO21_I2C_SCL, GPIO22_I2C_SDA, + + /* PWM Backlight */ + GPIO19_PWM2_OUT, }; static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = { @@ -290,6 +295,30 @@ static void __init cm_x300_init_lcd(void) static inline void cm_x300_init_lcd(void) {} #endif +#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) +static struct platform_pwm_backlight_data cm_x300_backlight_data = { + .pwm_id = 2, + .max_brightness = 100, + .dft_brightness = 100, + .pwm_period_ns = 10000, +}; + +static struct platform_device cm_x300_backlight_device = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &cm_x300_backlight_data, + }, +}; + +static void cm_x300_init_bl(void) +{ + platform_device_register(&cm_x300_backlight_device); +} +#else +static inline void cm_x300_init_bl(void) {} +#endif + #if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE) #define GPIO_LCD_BASE (144) #define GPIO_LCD_DIN (GPIO_LCD_BASE + 8) /* aux_gpio3_0 */ @@ -654,6 +683,7 @@ static void __init cm_x300_init(void) cm_x300_init_rtc(); cm_x300_init_ac97(); cm_x300_init_wi2wi(); + cm_x300_init_bl(); } static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index d4cc41d04b2..3395463bb5a 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include -- cgit v1.2.3-70-g09d2 From a7f2bdb39ed67c039ebef49e216e0fa543d6642e Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Fri, 27 Nov 2009 21:30:23 +0100 Subject: [ARM] pxa/em-x270: don't use pxa_camera init() callback pxa_camera init() is ambiguous, it's better to statically configure the sensor. Signed-off-by: Antonio Ospite Acked-by: Mike Rapoport Signed-off-by: Eric Miao --- arch/arm/mach-pxa/em-x270.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index e0b0fda9e67..1c0de808b54 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -967,7 +967,7 @@ static inline void em_x270_init_gpio_keys(void) {} #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) static struct regulator *em_x270_camera_ldo; -static int em_x270_sensor_init(struct device *dev) +static int em_x270_sensor_init(void) { int ret; @@ -996,7 +996,6 @@ static int em_x270_sensor_init(struct device *dev) } struct pxacamera_platform_data em_x270_camera_platform_data = { - .init = em_x270_sensor_init, .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, .mclk_10khz = 2600, @@ -1049,8 +1048,10 @@ static struct platform_device em_x270_camera = { static void __init em_x270_init_camera(void) { - pxa_set_camera_info(&em_x270_camera_platform_data); - platform_device_register(&em_x270_camera); + if (em_x270_sensor_init() == 0) { + pxa_set_camera_info(&em_x270_camera_platform_data); + platform_device_register(&em_x270_camera); + } } #else static inline void em_x270_init_camera(void) {} -- cgit v1.2.3-70-g09d2 From 0e85190755f5f336fbd5af01bbffe1f4aacf765a Mon Sep 17 00:00:00 2001 From: Antonio Ospite Date: Fri, 27 Nov 2009 21:31:36 +0100 Subject: [ARM] pxa/pcm990: don't use pxa_camera init() callback pxa_camera init() is ambiguous, it's better to configure PXA CIF pins statically in machine init function. Signed-off-by: Antonio Ospite Signed-off-by: Eric Miao --- arch/arm/mach-pxa/pcm990-baseboard.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index bbda57078e0..d5255ae74fe 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -359,19 +359,12 @@ static unsigned long pcm990_camera_pin_config[] = { GPIO44_CIF_LV, }; -static int pcm990_pxacamera_init(struct device *dev) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config)); - return 0; -} - /* * CICR4: PCLK_EN: Pixel clock is supplied by the sensor * MCLK_EN: Master clock is generated by PXA * PCP: Data sampled on the falling edge of pixel clock */ struct pxacamera_platform_data pcm990_pxacamera_platform_data = { - .init = pcm990_pxacamera_init, .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/, .mclk_10khz = 1000, @@ -532,6 +525,7 @@ void __init pcm990_baseboard_init(void) pxa_set_ac97_info(NULL); #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) + pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config)); pxa_set_camera_info(&pcm990_pxacamera_platform_data); i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices)); -- cgit v1.2.3-70-g09d2 From 19d6c13b56a78b3757e747f469285c2a546d634a Mon Sep 17 00:00:00 2001 From: Dmitry Artamonow Date: Wed, 25 Nov 2009 14:33:15 +0300 Subject: [ARM] pxa/hx4700: actually use platform_lcd driver Commit e2c509c7e6 ([ARM] pxa/hx4700: use platform_lcd driver) missed to actually register platform device for LCD. It causes following GCC warning: arch/arm/mach-pxa/hx4700.c:553: warning: 'hx4700_lcd' defined but not used Signed-off-by: Dmitry Artamonow Acked-by: Philipp Zabel Signed-off-by: Eric Miao --- arch/arm/mach-pxa/hx4700.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 6b3c90ed5f2..848c861dd23 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c @@ -820,6 +820,7 @@ static struct platform_device *devices[] __initdata = { &gpio_keys, &backlight, &w3220, + &hx4700_lcd, &egpio, &bq24022, &gpio_vbus, -- cgit v1.2.3-70-g09d2 From cf383678242eacd6f92a48314922598ed3408355 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 10 Nov 2009 00:14:58 +0000 Subject: ARM: SAMSUNG: Add plat-samsung as starting point for plat-s3c* moves We inted to re-organise the plat-s3c/plat-s3c24xx/plat-s3c64xx into a more generic plat-samsung with less code in the other plat- directories to make it easier to port new devices and try and clear up some of the naming issues with newer devices. Start by creating a small arch/arm/plat-samsung with no actuall code in so we can move items in as we process them. Add this to arch/arm to allow it to build things once support is added. Signed-off-by: Ben Dooks --- arch/arm/Kconfig | 1 + arch/arm/Makefile | 6 +++--- arch/arm/plat-samsung/Kconfig | 17 +++++++++++++++++ arch/arm/plat-samsung/Makefile | 11 +++++++++++ 4 files changed, 32 insertions(+), 3 deletions(-) create mode 100644 arch/arm/plat-samsung/Kconfig create mode 100644 arch/arm/plat-samsung/Makefile (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1c4119c6004..51a454bb40f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -747,6 +747,7 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-kirkwood/Kconfig" +source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a73caaf6676..df0d3a687f0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -178,9 +178,9 @@ plat-$(CONFIG_ARCH_OMAP) := omap plat-$(CONFIG_PLAT_IOP) := iop plat-$(CONFIG_PLAT_ORION) := orion plat-$(CONFIG_PLAT_PXA) := pxa -plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c -plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c -plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c +plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung +plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung +plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig new file mode 100644 index 00000000000..486a0d6301e --- /dev/null +++ b/arch/arm/plat-samsung/Kconfig @@ -0,0 +1,17 @@ +# arch/arm/plat-samsung/Kconfig +# +# Copyright 2009 Simtec Electronics +# +# Licensed under GPLv2 + +config PLAT_SAMSUNG + bool + depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX + default y + help + Base platform code for all Samsung SoC based systems + +if PLAT_SAMSUNG + + +endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile new file mode 100644 index 00000000000..4478b9f7dc3 --- /dev/null +++ b/arch/arm/plat-samsung/Makefile @@ -0,0 +1,11 @@ +# arch/arm/plat-s3c64xx/Makefile +# +# Copyright 2009 Simtec Electronics +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := dummy.o +obj- := + -- cgit v1.2.3-70-g09d2 From b0cc3031ffe1800aa6fe8ab0f55a75939bb265b7 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:11 +0100 Subject: ARM: S5PC1XX: registers rename S5PC110 and S5PC100 register maps differs in many places, rename all defined registers to be S5PC100 specific. PA_SYS register known from S3C64XX series has been renamed to more adequate PA_CLK. Also system map has been also updated to cover more integrated peripherals. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/include/mach/map.h | 87 +++++++++++++++++++++++++++++--- arch/arm/mach-s5pc100/mach-smdkc100.c | 2 +- 2 files changed, 82 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 9e9f39130b2..4681ebe8bef 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -17,6 +17,19 @@ #include +/* + * map-base.h has already defined virtual memory address + * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) + * S3C_VA_SYS S3C_ADDR(0x00100000) system control + * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) + * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block + * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog + * S3C_VA_UART S3C_ADDR(0x01000000) UART + * + * S5PC100 specific virtual memory address can be defined here + * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO + * + */ /* Chip ID */ #define S5PC100_PA_CHIPID (0xE0000000) @@ -24,13 +37,20 @@ #define S5PC1XX_VA_CHIPID S3C_VA_SYS /* System */ -#define S5PC100_PA_SYS (0xE0100000) -#define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0) -#define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000) +#define S5PC100_PA_CLK (0xE0100000) +#define S5PC100_PA_CLK_OTHER (0xE0200000) +#define S5PC100_PA_PWR (0xE0108000) #define S5PC1XX_PA_CLK S5PC100_PA_CLK #define S5PC1XX_PA_PWR S5PC100_PA_PWR +#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER #define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) #define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) +#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000) + +/* GPIO */ +#define S5PC100_PA_GPIO (0xE0300000) +#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO +#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) /* Interrupt */ #define S5PC100_PA_VIC (0xE4000000) @@ -40,23 +60,64 @@ #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) +/* DMA */ +#define S5PC100_PA_MDMA (0xE8100000) +#define S5PC100_PA_PDMA0 (0xE9000000) +#define S5PC100_PA_PDMA1 (0xE9200000) + /* Timer */ #define S5PC100_PA_TIMER (0xEA000000) #define S5PC1XX_PA_TIMER S5PC100_PA_TIMER #define S5PC1XX_VA_TIMER S3C_VA_TIMER +/* RTC */ +#define S5PC100_PA_RTC (0xEA300000) + /* UART */ #define S5PC100_PA_UART (0xEC000000) #define S5PC1XX_PA_UART S5PC100_PA_UART #define S5PC1XX_VA_UART S3C_VA_UART -/* IIC */ -#define S5PC100_PA_IIC (0xEC100000) +/* I2C */ +#define S5PC100_PA_I2C (0xEC100000) +#define S5PC100_PA_I2C1 (0xEC200000) + +/* USB HS OTG */ +#define S5PC100_PA_USB_HSOTG (0xED200000) +#define S5PC100_PA_USB_HSPHY (0xED300000) + +/* SD/MMC */ +#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) +#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0) +#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1) +#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2) + +/* LCD */ +#define S5PC100_PA_FB (0xEE000000) + +/* Multimedia */ +#define S5PC100_PA_G2D (0xEE800000) +#define S5PC100_PA_JPEG (0xEE500000) +#define S5PC100_PA_ROTATOR (0xEE100000) +#define S5PC100_PA_G3D (0xEF000000) + +/* I2S */ +#define S5PC100_PA_I2S0 (0xF2000000) +#define S5PC100_PA_I2S1 (0xF2100000) +#define S5PC100_PA_I2S2 (0xF2200000) + +/* KEYPAD */ +#define S5PC100_PA_KEYPAD (0xF3100000) + +/* ADC & TouchScreen */ +#define S5PC100_PA_TSADC (0xF3000000) /* ETC */ #define S5PC100_PA_SDRAM (0x20000000) +#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM /* compatibility defines. */ +#define S3C_PA_RTC S5PC100_PA_RTC #define S3C_PA_UART S5PC100_PA_UART #define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) #define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) @@ -67,9 +128,23 @@ #define S3C_VA_UART2 (S3C_VA_UART + 0x800) #define S3C_VA_UART3 (S3C_VA_UART + 0xC00) #define S3C_UART_OFFSET 0x400 +#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) +#define S3C_PA_FB S5PC100_PA_FB +#define S3C_PA_G2D S5PC100_PA_G2D +#define S3C_PA_G3D S5PC100_PA_G3D +#define S3C_PA_JPEG S5PC100_PA_JPEG +#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) #define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) -#define S3C_PA_IIC S5PC100_PA_IIC +#define S3C_PA_IIC S5PC100_PA_I2C +#define S3C_PA_IIC1 S5PC100_PA_I2C1 +#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG +#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY +#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 +#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 +#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 +#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD +#define S3C_PA_TSADC S5PC100_PA_TSADC #endif /* __ASM_ARCH_C100_MAP_H */ diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 214093cd763..daf6a2bc6b6 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -92,7 +92,7 @@ static void __init smdkc100_machine_init(void) MACHINE_START(SMDKC100, "SMDKC100") /* Maintainer: Byungho Min */ - .phys_io = S5PC1XX_PA_UART & 0xfff00000, + .phys_io = S5PC100_PA_UART & 0xfff00000, .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, .boot_params = S5PC100_PA_SDRAM + 0x100, -- cgit v1.2.3-70-g09d2 From 9ebaf2f4e7090a8c3b0c99419924b1e8f99a07a3 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:12 +0100 Subject: ARM: S5PC1XX: clock registers rename S5PC100 and S5PC110 clock registers differs in many places, rename all previously defined registers to be S5PC100 specific. Remove all power management registers. They will be added later to a separate file. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | 212 +++++++++--------------- arch/arm/plat-s5pc1xx/s5pc100-clock.c | 44 ++--- 2 files changed, 97 insertions(+), 159 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index 75c8390cb82..c5cc86e92d6 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h @@ -13,68 +13,69 @@ #ifndef __PLAT_REGS_CLOCK_H #define __PLAT_REGS_CLOCK_H __FILE__ -#define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x)) - -#define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00) -#define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04) -#define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08) -#define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C) - -#define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100) -#define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104) -#define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108) -#define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C) - -#define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200) -#define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204) -#define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208) -#define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C) - -#define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300) -#define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304) -#define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308) -#define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C) -#define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310) - -#define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400) - -#define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500) -#define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504) -#define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508) - -#define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520) -#define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524) -#define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528) -#define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C) -#define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530) -#define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534) - -#define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540) - -#define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560) -#define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564) - -#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) - -#define S5PC1XX_EPLL_EN (1<<31) -#define S5PC1XX_EPLL_MASK 0xffffffff -#define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) +#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x)) +#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x)) + +/* s5pc100 register for clock */ +#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00) +#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04) +#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08) +#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C) + +#define S5PC100_APLL_CON S5PC100_CLKREG(0x100) +#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104) +#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108) +#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C) + +#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200) +#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204) +#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208) +#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C) + +#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300) +#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304) +#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308) +#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C) +#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310) + +#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400) + +#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500) +#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504) +#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508) + +#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520) +#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524) +#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528) +#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C) +#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530) +#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534) + +#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540) + +#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560) +#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564) + +/* EPLL_CON */ +#define S5PC100_EPLL_EN (1<<31) +#define S5PC100_EPLL_MASK 0xffffffff +#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) /* CLKSRC0 */ -#define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0) -#define S5PC1XX_CLKSRC0_APLL_SHIFT (0) -#define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4) -#define S5PC1XX_CLKSRC0_MPLL_SHIFT (4) -#define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8) -#define S5PC1XX_CLKSRC0_EPLL_SHIFT (8) +#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) +#define S5PC100_CLKSRC0_APLL_SHIFT (0) +#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) +#define S5PC100_CLKSRC0_MPLL_SHIFT (4) +#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) +#define S5PC100_CLKSRC0_EPLL_SHIFT (8) #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) #define S5PC100_CLKSRC0_HPLL_SHIFT (12) #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) #define S5PC100_CLKSRC0_HREF_SHIFT (20) -#define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24) -#define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24) +#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) +#define S5PC100_CLKSRC0_ONENAND_SHIFT (24) /* CLKSRC1 */ @@ -127,10 +128,9 @@ #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) - /* CLKDIV0 */ -#define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0) -#define S5PC1XX_CLKDIV0_APLL_SHIFT (0) +#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) +#define S5PC100_CLKDIV0_APLL_SHIFT (0) #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) #define S5PC100_CLKDIV0_ARM_SHIFT (4) #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) @@ -141,8 +141,8 @@ #define S5PC100_CLKDIV0_SECSS_SHIFT (16) /* CLKDIV1 */ -#define S5PC100_CLKDIV1_AM_MASK (0x7<<0) -#define S5PC100_CLKDIV1_AM_SHIFT (0) +#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) +#define S5PC100_CLKDIV1_APLL2_SHIFT (0) #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) #define S5PC100_CLKDIV1_MPLL_SHIFT (4) #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) @@ -202,7 +202,6 @@ #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) - /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ #define S5PC100_CLKGATE_D00_INTC (1<<0) #define S5PC100_CLKGATE_D00_TZIC (1<<1) @@ -295,8 +294,8 @@ #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) /* Special Clock Gate 0 Registers */ -#define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0) -#define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1) +#define S5PC100_CLKGATE_SCLK0_HPM (1<<0) +#define S5PC100_CLKGATE_SCLK0_PWI (1<<1) #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) #define S5PC100_CLKGATE_SCLK0_UART (1<<3) #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) @@ -329,89 +328,28 @@ #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) -/* register for power management */ -#define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000) -#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004) -#define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010) -#define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014) -#define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018) -#define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C) -#define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100) -#define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104) -#define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108) -#define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110) -#define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114) -#define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) -#define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300) -#define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304) -#define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308) -#define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400) -#define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404) -#define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408) -#define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C) -#define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410) -#define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414) -#define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418) -#define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C) -#define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500) -#define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504) -#define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508) -#define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C) -#define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510) -#define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514) -#define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518) -#define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C) -#define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520) -#define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600) -#define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604) -#define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608) -#define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C) -#define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610) -#define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614) -#define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618) -#define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C) -#define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620) -#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700) -#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704) -#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708) -#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C) -#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710) -#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714) -#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718) -#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C) -#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724) - -#define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000) -#define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008) -#define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100) -#define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104) -#define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200) -#define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300) -#define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304) -#define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308) -#define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400) -#define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414) -#define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420) - -#define S5PC100_CFG_WFI_CLEAN (~(3<<5)) -#define S5PC100_CFG_WFI_IDLE (1<<5) -#define S5PC100_CFG_WFI_STOP (2<<5) -#define S5PC100_CFG_WFI_SLEEP (3<<5) - +#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000) +#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008) +#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100) +#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104) +#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200) +#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300) +#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304) +#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308) +#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400) +#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414) +#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420) + +#define S5PC100_SWRESET_RESETVAL 0xc100 #define S5PC100_OTHER_SYS_INT 24 #define S5PC100_OTHER_STA_TYPE 23 #define STA_TYPE_EXPON 0 #define STA_TYPE_SFR 1 -#define S5PC100_PWR_STA_EXP_SCALE 0 -#define S5PC100_PWR_STA_CNT 4 - -#define S5PC100_PWR_STABLE_COUNT 85500 - #define S5PC100_SLEEP_CFG_OSC_EN 0 /* OTHERS Resgister */ -#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) +#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) /* MIPI D-PHY Control Register 0 */ diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index 6b24035172f..efc868b4c2a 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -87,13 +87,13 @@ static int clk_48m_ctrl(struct clk *clk, int enable) /* can't rely on clock lock, this register has other usages */ local_irq_save(flags); - val = __raw_readl(S5PC1XX_CLK_SRC1); + val = __raw_readl(S5PC100_CLKSRC1); if (enable) val |= S5PC100_CLKSRC1_CLK48M_MASK; else val &= ~S5PC100_CLKSRC1_CLK48M_MASK; - __raw_writel(val, S5PC1XX_CLK_SRC1); + __raw_writel(val, S5PC100_CLKSRC1); local_irq_restore(flags); return 0; @@ -685,7 +685,7 @@ static struct clk init_clocks[] = { .id = -1, .parent = NULL, .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM, + .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, }, { .name = "sclk_onenand", .id = -1, @@ -801,10 +801,10 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .shift = S5PC1XX_CLKSRC0_APLL_SHIFT, - .mask = S5PC1XX_CLKSRC0_APLL_MASK, + .shift = S5PC100_CLKSRC0_APLL_SHIFT, + .mask = S5PC100_CLKSRC0_APLL_MASK, .sources = &clk_src_apll, - .reg_source = S5PC1XX_CLK_SRC0, + .reg_source = S5PC100_CLKSRC0, }; static struct clk clk_fout_epll = { @@ -827,10 +827,10 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .shift = S5PC1XX_CLKSRC0_EPLL_SHIFT, - .mask = S5PC1XX_CLKSRC0_EPLL_MASK, + .shift = S5PC100_CLKSRC0_EPLL_SHIFT, + .mask = S5PC100_CLKSRC0_EPLL_MASK, .sources = &clk_src_epll, - .reg_source = S5PC1XX_CLK_SRC0, + .reg_source = S5PC100_CLKSRC0, }; static struct clk *clk_src_mpll_list[] = { @@ -848,10 +848,10 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .shift = S5PC1XX_CLKSRC0_MPLL_SHIFT, - .mask = S5PC1XX_CLKSRC0_MPLL_MASK, + .shift = S5PC100_CLKSRC0_MPLL_SHIFT, + .mask = S5PC100_CLKSRC0_MPLL_MASK, .sources = &clk_src_mpll, - .reg_source = S5PC1XX_CLK_SRC0, + .reg_source = S5PC100_CLKSRC0, }; static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) @@ -861,7 +861,7 @@ static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK; + clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1; return rate; @@ -881,7 +881,7 @@ static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK; + clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1; return rate; @@ -1007,8 +1007,8 @@ static struct clksrc_clk clk_uart_uclk1 = { .mask = S5PC100_CLKSRC1_UART_MASK, .sources = &clkset_uart, .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, - .reg_divider = S5PC1XX_CLK_DIV2, - .reg_source = S5PC1XX_CLK_SRC1, + .reg_divider = S5PC100_CLKDIV2, + .reg_source = S5PC100_CLKSRC1, }; /* Clock initialisation code */ @@ -1061,8 +1061,8 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) printk(KERN_DEBUG "%s: registering clocks\n", __func__); - clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0); - clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1); + clkdiv0 = __raw_readl(S5PC100_CLKDIV0); + clkdiv1 = __raw_readl(S5PC100_CLKDIV1); printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); @@ -1075,15 +1075,15 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON)); - mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON)); - epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON)); + apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON)); + mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON)); + epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", apll, mpll, epll, hpll); - armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL); + armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); -- cgit v1.2.3-70-g09d2 From ff916f25b2890403a9e6c02c98391daeb71ae92a Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:13 +0100 Subject: ARM: S5PC1XX: clocks reimplementation Clocks hierarchy has been completely reimplemented to match the S5PC100 specification. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/plat-s5pc1xx/Makefile | 1 + arch/arm/plat-s5pc1xx/clock.c | 728 ++++++++++++ arch/arm/plat-s5pc1xx/cpu.c | 5 + arch/arm/plat-s5pc1xx/include/plat/s5pc100.h | 5 +- arch/arm/plat-s5pc1xx/s5pc100-clock.c | 1531 +++++++++++++------------- 5 files changed, 1504 insertions(+), 766 deletions(-) create mode 100644 arch/arm/plat-s5pc1xx/clock.c (limited to 'arch') diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index f1ecb2c37ee..ebbf36490f4 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile @@ -14,6 +14,7 @@ obj- := obj-y += dev-uart.o obj-y += cpu.o obj-y += irq.o +obj-y += clock.o # CPU support diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c new file mode 100644 index 00000000000..26c21d84979 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -0,0 +1,728 @@ +/* linux/arch/arm/plat-s5pc1xx/clock.c + * + * Copyright 2009 Samsung Electronics Co. + * + * S5PC1XX Base clock support + * + * Based on plat-s3c64xx/clock.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +struct clk clk_27m = { + .name = "clk_27m", + .id = -1, + .rate = 27000000, +}; + +static int clk_48m_ctrl(struct clk *clk, int enable) +{ + unsigned long flags; + u32 val; + + /* can't rely on clock lock, this register has other usages */ + local_irq_save(flags); + + val = __raw_readl(S5PC100_CLKSRC1); + if (enable) + val |= S5PC100_CLKSRC1_CLK48M_MASK; + else + val &= ~S5PC100_CLKSRC1_CLK48M_MASK; + + __raw_writel(val, S5PC100_CLKSRC1); + local_irq_restore(flags); + + return 0; +} + +struct clk clk_48m = { + .name = "clk_48m", + .id = -1, + .rate = 48000000, + .enable = clk_48m_ctrl, +}; + +struct clk clk_54m = { + .name = "clk_54m", + .id = -1, + .rate = 54000000, +}; + +static int clk_default_setrate(struct clk *clk, unsigned long rate) +{ + clk->rate = rate; + return 0; +} + +static int clk_dummy_enable(struct clk *clk, int enable) +{ + return 0; +} + +struct clk clk_hd0 = { + .name = "hclkd0", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .set_rate = clk_default_setrate, + .enable = clk_dummy_enable, +}; + +struct clk clk_pd0 = { + .name = "pclkd0", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .set_rate = clk_default_setrate, + .enable = clk_dummy_enable, +}; + +static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + if (enable) + con |= ctrlbit; + else + con &= ~ctrlbit; + __raw_writel(con, reg); + + return 0; +} + +static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); +} + +static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); +} + +static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); +} + +static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); +} + +static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); +} + +static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); +} + +static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); +} + +static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); +} + +static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); +} + +static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); +} + +int s5pc100_sclk0_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); +} + +int s5pc100_sclk1_ctrl(struct clk *clk, int enable) +{ + return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); +} + +static struct clk s5pc100_init_clocks_disable[] = { + { + .name = "dsi", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_DSI, + }, { + .name = "csi", + .id = -1, + .parent = &clk_h, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_CSI, + }, { + .name = "ccan", + .id = 0, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, + }, { + .name = "ccan", + .id = 1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, + }, { + .name = "keypad", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, + }, { + .name = "hclkd2", + .id = -1, + .parent = NULL, + .enable = s5pc100_clk_d20_ctrl, + .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, + }, { + .name = "iis-d2", + .id = -1, + .parent = NULL, + .enable = s5pc100_clk_d20_ctrl, + .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, + }, +}; + +static struct clk s5pc100_init_clocks[] = { + /* System1 (D0_0) devices */ + { + .name = "intc", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_INTC, + }, { + .name = "tzic", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_TZIC, + }, { + .name = "cf-ata", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_CFCON, + }, { + .name = "mdma", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_MDMA, + }, { + .name = "g2d", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_G2D, + }, { + .name = "secss", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_SECSS, + }, { + .name = "cssys", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d00_ctrl, + .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, + }, + + /* Memory (D0_1) devices */ + { + .name = "dmc", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_DMC, + }, { + .name = "sromc", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_SROMC, + }, { + .name = "onenand", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, + }, { + .name = "nand", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_NFCON, + }, { + .name = "intmem", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, + }, { + .name = "ebi", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d01_ctrl, + .ctrlbit = S5PC100_CLKGATE_D01_EBI, + }, + + /* System2 (D0_2) devices */ + { + .name = "seckey", + .id = -1, + .parent = &clk_pd0, + .enable = s5pc100_clk_d02_ctrl, + .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, + }, { + .name = "sdm", + .id = -1, + .parent = &clk_hd0, + .enable = s5pc100_clk_d02_ctrl, + .ctrlbit = S5PC100_CLKGATE_D02_SDM, + }, + + /* File (D1_0) devices */ + { + .name = "pdma", + .id = 0, + .parent = &clk_h, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, + }, { + .name = "pdma", + .id = 1, + .parent = &clk_h, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, + }, { + .name = "usb-host", + .id = -1, + .parent = &clk_h, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, + }, { + .name = "otg", + .id = -1, + .parent = &clk_h, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, + }, { + .name = "modem", + .id = -1, + .parent = &clk_h, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_48m, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_48m, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_48m, + .enable = s5pc100_clk_d10_ctrl, + .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, + }, + + /* Multimedia1 (D1_1) devices */ + { + .name = "lcd", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_LCD, + }, { + .name = "rotator", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, + }, { + .name = "fimc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, + }, { + .name = "fimc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, + }, { + .name = "fimc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, + }, { + .name = "jpeg", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_JPEG, + }, { + .name = "g3d", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d11_ctrl, + .ctrlbit = S5PC100_CLKGATE_D11_G3D, + }, + + /* Multimedia2 (D1_2) devices */ + { + .name = "tv", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d12_ctrl, + .ctrlbit = S5PC100_CLKGATE_D12_TV, + }, { + .name = "vp", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d12_ctrl, + .ctrlbit = S5PC100_CLKGATE_D12_VP, + }, { + .name = "mixer", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d12_ctrl, + .ctrlbit = S5PC100_CLKGATE_D12_MIXER, + }, { + .name = "hdmi", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d12_ctrl, + .ctrlbit = S5PC100_CLKGATE_D12_HDMI, + }, { + .name = "mfc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d12_ctrl, + .ctrlbit = S5PC100_CLKGATE_D12_MFC, + }, + + /* System (D1_3) devices */ + { + .name = "chipid", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, + }, { + .name = "gpio", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_GPIO, + }, { + .name = "apc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_APC, + }, { + .name = "iec", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_IEC, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_PWM, + }, { + .name = "systimer", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_WDT, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d13_ctrl, + .ctrlbit = S5PC100_CLKGATE_D13_RTC, + }, + + /* Connectivity (D1_4) devices */ + { + .name = "uart", + .id = 0, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_UART3, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_IIC, + }, { + .name = "hdmi-i2c", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, + }, { + .name = "spi", + .id = 0, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_SPI0, + }, { + .name = "spi", + .id = 1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_SPI1, + }, { + .name = "spi", + .id = 2, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_SPI2, + }, { + .name = "irda", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_IRDA, + }, { + .name = "hsitx", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_HSITX, + }, { + .name = "hsirx", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d14_ctrl, + .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, + }, + + /* Audio (D1_5) devices */ + { + .name = "iis", + .id = 0, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_IIS0, + }, { + .name = "iis", + .id = 1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_IIS1, + }, { + .name = "iis", + .id = 2, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_IIS2, + }, { + .name = "ac97", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_AC97, + }, { + .name = "pcm", + .id = 0, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_PCM0, + }, { + .name = "pcm", + .id = 1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_PCM1, + }, { + .name = "spdif", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_TSADC, + }, { + .name = "cg", + .id = -1, + .parent = &clk_p, + .enable = s5pc100_clk_d15_ctrl, + .ctrlbit = S5PC100_CLKGATE_D15_CG, + }, + + /* Audio (D2_0) devices: all disabled */ + + /* Special Clocks 0 */ + { + .name = "sclk_hpm", + .id = -1, + .parent = NULL, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, + }, { + .name = "sclk_onenand", + .id = -1, + .parent = NULL, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, + }, { + .name = "spi_48", + .id = 0, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, + }, { + .name = "spi_48", + .id = 1, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, + }, { + .name = "spi_48", + .id = 2, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, + }, { + .name = "mmc_48", + .id = 0, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, + }, { + .name = "mmc_48", + .id = 1, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, + }, { + .name = "mmc_48", + .id = 2, + .parent = &clk_48m, + .enable = s5pc100_sclk0_ctrl, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, + }, + /* Special Clocks 1 */ +}; + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_epll, + &clk_27m, + &clk_48m, + &clk_54m, +}; + +void __init s5pc1xx_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + int size; + + s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + + clkp = s5pc100_init_clocks; + size = ARRAY_SIZE(s5pc100_init_clocks); + + for (ptr = 0; ptr < size; ptr++, clkp++) { + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } + + clkp = s5pc100_init_clocks_disable; + size = ARRAY_SIZE(s5pc100_init_clocks_disable); + + for (ptr = 0; ptr < size; ptr++, clkp++) { + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c index 715a7330794..e8f347218ec 100644 --- a/arch/arm/plat-s5pc1xx/cpu.c +++ b/arch/arm/plat-s5pc1xx/cpu.c @@ -55,6 +55,11 @@ static struct cpu_table cpu_ids[] __initdata = { static struct map_desc s5pc1xx_iodesc[] __initdata = { { + .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER, + .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER), + .length = SZ_4K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)S5PC1XX_VA_CHIPID, .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), .length = SZ_16, diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h index 45e27513166..2531f34a56f 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h +++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h @@ -35,10 +35,9 @@ extern struct clk clk_hpll; extern struct clk clk_hd0; extern struct clk clk_pd0; extern struct clk clk_54m; -extern struct clk clk_dout_mpll2; extern void s5pc1xx_register_clocks(void); -extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); -extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); +extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable); +extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable); /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index efc868b4c2a..b436d44510c 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = { #define clk_fin_hpll clk_ext_xtal_mux #define clk_fout_mpll clk_mpll +#define clk_vclk_54m clk_54m struct clk_sources { unsigned int nr_sources; @@ -67,746 +68,327 @@ struct clksrc_clk { void __iomem *reg_source; }; -static int clk_default_setrate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 1; -} - -struct clk clk_27m = { - .name = "clk_27m", +/* APLL */ +static struct clk clk_fout_apll = { + .name = "fout_apll", .id = -1, .rate = 27000000, }; -static int clk_48m_ctrl(struct clk *clk, int enable) -{ - unsigned long flags; - u32 val; +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; - /* can't rely on clock lock, this register has other usages */ - local_irq_save(flags); +static struct clk_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; - val = __raw_readl(S5PC100_CLKSRC1); - if (enable) - val |= S5PC100_CLKSRC1_CLK48M_MASK; - else - val &= ~S5PC100_CLKSRC1_CLK48M_MASK; +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .shift = S5PC100_CLKSRC0_APLL_SHIFT, + .mask = S5PC100_CLKSRC0_APLL_MASK, + .sources = &clk_src_apll, + .reg_source = S5PC100_CLKSRC0, +}; - __raw_writel(val, S5PC100_CLKSRC1); - local_irq_restore(flags); +static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; - return 0; -} + ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK; + ratio >>= S5PC100_CLKDIV0_APLL_SHIFT; -struct clk clk_48m = { - .name = "clk_48m", - .id = -1, - .rate = 48000000, - .enable = clk_48m_ctrl, -}; + return rate / (ratio + 1); +} -struct clk clk_54m = { - .name = "clk_54m", +static struct clk clk_dout_apll = { + .name = "dout_apll", .id = -1, - .rate = 54000000, + .parent = &clk_mout_apll.clk, + .get_rate = s5pc100_clk_dout_apll_get_rate, }; -struct clk clk_hpll = { - .name = "hpll", - .id = -1, -}; +static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; -struct clk clk_hd0 = { - .name = "hclkd0", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; + ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK; + ratio >>= S5PC100_CLKDIV0_ARM_SHIFT; -struct clk clk_pd0 = { - .name = "pclkd0", - .id = -1, - .rate = 0, - .parent = NULL, - .ctrlbit = 0, - .set_rate = clk_default_setrate, -}; + return rate / (ratio + 1); +} -static int s5pc1xx_clk_gate(void __iomem *reg, - struct clk *clk, - int enable) +static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk, + unsigned long rate) { - unsigned int ctrlbit = clk->ctrlbit; - u32 con; + unsigned long parent = clk_get_rate(clk->parent); + u32 div; - con = __raw_readl(reg); + if (parent < rate) + return rate; - if (enable) - con |= ctrlbit; - else - con &= ~ctrlbit; + div = (parent / rate) - 1; + if (div > S5PC100_CLKDIV0_ARM_MASK) + div = S5PC100_CLKDIV0_ARM_MASK; - __raw_writel(con, reg); - return 0; + return parent / (div + 1); } -static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) +static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate) { - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); -} + unsigned long parent = clk_get_rate(clk->parent); + u32 div; + u32 val; -static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); -} + if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1)) + return -EINVAL; -static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); -} + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; -static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); -} + val = __raw_readl(S5PC100_CLKDIV0); + val &= S5PC100_CLKDIV0_ARM_MASK; + val |= (div - 1); + __raw_writel(val, S5PC100_CLKDIV0); -static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); + return 0; } -static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); -} +static struct clk clk_arm = { + .name = "armclk", + .id = -1, + .parent = &clk_dout_apll, + .get_rate = s5pc100_clk_arm_get_rate, + .set_rate = s5pc100_clk_arm_set_rate, + .round_rate = s5pc100_clk_arm_round_rate, +}; -static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) +static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) { - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); -} + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; -static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); -} + ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK; + ratio >>= S5PC100_CLKDIV0_D0_SHIFT; -static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); + return rate / (ratio + 1); } -static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) -{ - return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); -} +static struct clk clk_dout_d0_bus = { + .name = "dout_d0_bus", + .id = -1, + .parent = &clk_arm, + .get_rate = s5pc100_clk_dout_d0_bus_get_rate, +}; -int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) +static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) { - return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; + + ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK; + ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT; + + return rate / (ratio + 1); } -int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) +static struct clk clk_dout_pclkd0 = { + .name = "dout_pclkd0", + .id = -1, + .parent = &clk_dout_d0_bus, + .get_rate = s5pc100_clk_dout_pclkd0_get_rate, +}; + +static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) { - return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; + + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK; + ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT; + + return rate / (ratio + 1); } -static struct clk init_clocks_disable[] = { - { - .name = "dsi", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_DSI, - }, { - .name = "csi", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_CSI, - }, { - .name = "ccan0", - .id = 0, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, - }, { - .name = "ccan1", - .id = 1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, - }, { - .name = "keypad", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, - }, { - .name = "hclkd2", - .id = -1, - .parent = NULL, - .enable = s5pc1xx_clk_d20_ctrl, - .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, - }, { - .name = "iis-d2", - .id = -1, - .parent = NULL, - .enable = s5pc1xx_clk_d20_ctrl, - .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, - }, { - .name = "otg", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, - }, +static struct clk clk_dout_apll2 = { + .name = "dout_apll2", + .id = -1, + .parent = &clk_mout_apll.clk, + .get_rate = s5pc100_clk_dout_apll2_get_rate, }; -static struct clk init_clocks[] = { - /* System1 (D0_0) devices */ - { - .name = "intc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_INTC, - }, { - .name = "tzic", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_TZIC, - }, { - .name = "cf-ata", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_CFCON, - }, { - .name = "mdma", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_MDMA, - }, { - .name = "g2d", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_G2D, - }, { - .name = "secss", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_SECSS, - }, { - .name = "cssys", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d00_ctrl, - .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, - }, +/* MPLL */ +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; - /* Memory (D0_1) devices */ - { - .name = "dmc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_DMC, - }, { - .name = "sromc", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_SROMC, - }, { - .name = "onenand", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, - }, { - .name = "nand", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_NFCON, - }, { - .name = "intmem", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, - }, { - .name = "ebi", - .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d01_ctrl, - .ctrlbit = S5PC100_CLKGATE_D01_EBI, - }, +static struct clk_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; - /* System2 (D0_2) devices */ - { - .name = "seckey", - .id = -1, - .parent = &clk_pd0, - .enable = s5pc1xx_clk_d02_ctrl, - .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, - }, { - .name = "sdm", +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", .id = -1, - .parent = &clk_hd0, - .enable = s5pc1xx_clk_d02_ctrl, - .ctrlbit = S5PC100_CLKGATE_D02_SDM, }, + .shift = S5PC100_CLKSRC0_MPLL_SHIFT, + .mask = S5PC100_CLKSRC0_MPLL_MASK, + .sources = &clk_src_mpll, + .reg_source = S5PC100_CLKSRC0, +}; - /* File (D1_0) devices */ - { - .name = "pdma0", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, - }, { - .name = "pdma1", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, - }, { - .name = "usb-host", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, - }, { - .name = "modem", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, - }, { - .name = "hsmmc", - .id = 0, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, - }, { - .name = "hsmmc", - .id = 1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, - }, { - .name = "hsmmc", - .id = 2, - .parent = &clk_h, - .enable = s5pc1xx_clk_d10_ctrl, - .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, - }, +static struct clk *clkset_am_list[] = { + [0] = &clk_mout_mpll.clk, + [1] = &clk_dout_apll2, +}; - /* Multimedia1 (D1_1) devices */ - { - .name = "lcd", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_LCD, - }, { - .name = "rotator", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, - }, { - .name = "fimc", - .id = 0, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, - }, { - .name = "fimc", - .id = 1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, - }, { - .name = "fimc", - .id = 2, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, - }, { - .name = "jpeg", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_JPEG, - }, { - .name = "g3d", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d11_ctrl, - .ctrlbit = S5PC100_CLKGATE_D11_G3D, - }, +static struct clk_sources clk_src_am = { + .sources = clkset_am_list, + .nr_sources = ARRAY_SIZE(clkset_am_list), +}; - /* Multimedia2 (D1_2) devices */ - { - .name = "tv", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_TV, - }, { - .name = "vp", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_VP, - }, { - .name = "mixer", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_MIXER, - }, { - .name = "hdmi", - .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_HDMI, - }, { - .name = "mfc", +static struct clksrc_clk clk_mout_am = { + .clk = { + .name = "mout_am", .id = -1, - .parent = &clk_h, - .enable = s5pc1xx_clk_d12_ctrl, - .ctrlbit = S5PC100_CLKGATE_D12_MFC, }, + .shift = S5PC100_CLKSRC0_AMMUX_SHIFT, + .mask = S5PC100_CLKSRC0_AMMUX_MASK, + .sources = &clk_src_am, + .reg_source = S5PC100_CLKSRC0, +}; - /* System (D1_3) devices */ - { - .name = "chipid", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, - }, { - .name = "gpio", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_GPIO, - }, { - .name = "apc", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_APC, - }, { - .name = "iec", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_IEC, - }, { - .name = "timers", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_PWM, - }, { - .name = "systimer", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, - }, { - .name = "watchdog", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_WDT, - }, { - .name = "rtc", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d13_ctrl, - .ctrlbit = S5PC100_CLKGATE_D13_RTC, - }, +static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; - /* Connectivity (D1_4) devices */ - { - .name = "uart", - .id = 0, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART0, - }, { - .name = "uart", - .id = 1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART1, - }, { - .name = "uart", - .id = 2, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART2, - }, { - .name = "uart", - .id = 3, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_UART3, - }, { - .name = "i2c", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_IIC, - }, { - .name = "hdmi-i2c", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, - }, { - .name = "spi", - .id = 0, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI0, - }, { - .name = "spi", - .id = 1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI1, - }, { - .name = "spi", - .id = 2, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_SPI2, - }, { - .name = "irda", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_IRDA, - }, { - .name = "hsitx", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HSITX, - }, { - .name = "hsirx", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d14_ctrl, - .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, - }, + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - /* Audio (D1_5) devices */ - { - .name = "iis", - .id = 0, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS0, - }, { - .name = "iis", - .id = 1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS1, - }, { - .name = "iis", - .id = 2, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_IIS2, - }, { - .name = "ac97", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_AC97, - }, { - .name = "pcm", - .id = 0, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_PCM0, - }, { - .name = "pcm", - .id = 1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_PCM1, - }, { - .name = "spdif", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, - }, { - .name = "adc", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_TSADC, - }, { - .name = "keyif", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, - }, { - .name = "cg", - .id = -1, - .parent = &clk_p, - .enable = s5pc1xx_clk_d15_ctrl, - .ctrlbit = S5PC100_CLKGATE_D15_CG, - }, + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK; + ratio >>= S5PC100_CLKDIV1_D1_SHIFT; - /* Audio (D2_0) devices: all disabled */ + return rate / (ratio + 1); +} - /* Special Clocks 1 */ - { - .name = "sclk_hpm", - .id = -1, - .parent = NULL, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, - }, { - .name = "sclk_onenand", - .id = -1, - .parent = NULL, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, - }, { - .name = "sclk_spi_48", - .id = 0, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, - }, { - .name = "sclk_spi_48", - .id = 1, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, - }, { - .name = "sclk_spi_48", - .id = 2, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, - }, { - .name = "sclk_mmc_48", - .id = 0, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, - }, { - .name = "sclk_mmc_48", - .id = 1, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, - }, { - .name = "sclk_mmc_48", - .id = 2, - .parent = &clk_48m, - .enable = s5pc1xx_sclk0_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, - }, +static struct clk clk_dout_d1_bus = { + .name = "dout_d1_bus", + .id = -1, + .parent = &clk_mout_am.clk, + .get_rate = s5pc100_clk_dout_d1_bus_get_rate, +}; - /* Special Clocks 2 */ - { - .name = "sclk_tv_54", - .id = -1, - .parent = &clk_54m, - .enable = s5pc1xx_sclk1_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK1_TV54, - }, { - .name = "sclk_vdac_54", - .id = -1, - .parent = &clk_54m, - .enable = s5pc1xx_sclk1_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54, - }, { - .name = "sclk_spdif", +static struct clk *clkset_onenand_list[] = { + [0] = &clk_dout_d0_bus, + [1] = &clk_dout_d1_bus, +}; + +static struct clk_sources clk_src_onenand = { + .sources = clkset_onenand_list, + .nr_sources = ARRAY_SIZE(clkset_onenand_list), +}; + +static struct clksrc_clk clk_mout_onenand = { + .clk = { + .name = "mout_onenand", .id = -1, - .parent = NULL, - .enable = s5pc1xx_sclk1_ctrl, - .ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF, }, + .shift = S5PC100_CLKSRC0_ONENAND_SHIFT, + .mask = S5PC100_CLKSRC0_ONENAND_MASK, + .sources = &clk_src_onenand, + .reg_source = S5PC100_CLKSRC0, }; -void __init s5pc1xx_register_clocks(void) +static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) { - struct clk *clkp; - int ret; - int ptr; + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - clkp = init_clocks_disable; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK; + ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT; - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } + return rate / (ratio + 1); +} - (clkp->enable)(clkp, 0); - } +static struct clk clk_dout_pclkd1 = { + .name = "dout_pclkd1", + .id = -1, + .parent = &clk_dout_d1_bus, + .get_rate = s5pc100_clk_dout_pclkd1_get_rate, +}; - s3c_pwmclk_init(); +static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; + + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; + ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT; + + return rate / (ratio + 1); } -static struct clk clk_fout_apll = { - .name = "fout_apll", + +static struct clk clk_dout_mpll2 = { + .name = "dout_mpll2", .id = -1, + .parent = &clk_mout_am.clk, + .get_rate = s5pc100_clk_dout_mpll2_get_rate, }; -static struct clk *clk_src_apll_list[] = { - [0] = &clk_fin_apll, - [1] = &clk_fout_apll, -}; +static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; -static struct clk_sources clk_src_apll = { - .sources = clk_src_apll_list, - .nr_sources = ARRAY_SIZE(clk_src_apll_list), + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK; + ratio >>= S5PC100_CLKDIV1_CAM_SHIFT; + + return rate / (ratio + 1); +} + +static struct clk clk_dout_cam = { + .name = "dout_cam", + .id = -1, + .parent = &clk_dout_mpll2, + .get_rate = s5pc100_clk_dout_cam_get_rate, }; -static struct clksrc_clk clk_mout_apll = { - .clk = { - .name = "mout_apll", - .id = -1, - }, - .shift = S5PC100_CLKSRC0_APLL_SHIFT, - .mask = S5PC100_CLKSRC0_APLL_MASK, - .sources = &clk_src_apll, - .reg_source = S5PC100_CLKSRC0, +static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned int ratio; + + printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); + + ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; + ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT; + + return rate / (ratio + 1); +} + +static struct clk clk_dout_mpll = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_am.clk, + .get_rate = s5pc100_clk_dout_mpll_get_rate, }; +/* EPLL */ static struct clk clk_fout_epll = { .name = "fout_epll", .id = -1, @@ -833,85 +415,51 @@ static struct clksrc_clk clk_mout_epll = { .reg_source = S5PC100_CLKSRC0, }; -static struct clk *clk_src_mpll_list[] = { - [0] = &clk_fin_mpll, - [1] = &clk_fout_mpll, +/* HPLL */ +static struct clk clk_fout_hpll = { + .name = "fout_hpll", + .id = -1, }; -static struct clk_sources clk_src_mpll = { - .sources = clk_src_mpll_list, - .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +static struct clk *clk_src_hpll_list[] = { + [0] = &clk_27m, + [1] = &clk_fout_hpll, }; -static struct clksrc_clk clk_mout_mpll = { - .clk = { - .name = "mout_mpll", +static struct clk_sources clk_src_hpll = { + .sources = clk_src_hpll_list, + .nr_sources = ARRAY_SIZE(clk_src_hpll_list), +}; + +static struct clksrc_clk clk_mout_hpll = { + .clk = { + .name = "mout_hpll", .id = -1, }, - .shift = S5PC100_CLKSRC0_MPLL_SHIFT, - .mask = S5PC100_CLKSRC0_MPLL_MASK, - .sources = &clk_src_mpll, + .shift = S5PC100_CLKSRC0_HPLL_SHIFT, + .mask = S5PC100_CLKSRC0_HPLL_MASK, + .sources = &clk_src_hpll, .reg_source = S5PC100_CLKSRC0, }; -static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; - rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1; - - return rate; -} - -static struct clk clk_dout_mpll = { - .name = "dout_mpll", - .id = -1, - .parent = &clk_mout_mpll.clk, - .get_rate = s5pc1xx_clk_doutmpll_get_rate, -}; - -static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) -{ - unsigned long rate = clk_get_rate(clk->parent); - unsigned long clkdiv; - - printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); - - clkdiv = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; - rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1; - - return rate; -} - -struct clk clk_dout_mpll2 = { - .name = "dout_mpll2", - .id = -1, - .parent = &clk_mout_mpll.clk, - .get_rate = s5pc1xx_clk_doutmpll2_get_rate, -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, - NULL, - NULL -}; - -static struct clk_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; +/* Peripherals */ +/* + * The peripheral clocks are all controlled via clocksource followed + * by an optional divider and gate stage. We currently roll this into + * one clock which hides the intermediate clock from the mux. + * + * Note, the JPEG clock can only be an even divider... + * + * The scaler and LCD clocks depend on the S5PC100 version, and also + * have a common parent divisor so are not included here. + */ static inline struct clksrc_clk *to_clksrc(struct clk *clk) { return container_of(clk, struct clksrc_clk, clk); } -static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) +static unsigned long s5pc100_getrate_clksrc(struct clk *clk) { struct clksrc_clk *sclk = to_clksrc(clk); unsigned long rate = clk_get_rate(clk->parent); @@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) return rate; } -static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) +static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate) { struct clksrc_clk *sclk = to_clksrc(clk); void __iomem *reg = sclk->reg_divider; @@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) return -EINVAL; val = __raw_readl(reg); - val &= ~(0xf << sclk->shift); - val |= (div - 1) << sclk->shift; + val &= ~(0xf << sclk->divider_shift); + val |= (div - 1) << sclk->divider_shift; __raw_writel(val, reg); return 0; } -static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) +static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent) { struct clksrc_clk *sclk = to_clksrc(clk); struct clk_sources *srcs = sclk->sources; @@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) return -EINVAL; } -static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, +static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, unsigned long rate) { unsigned long parent_rate = clk_get_rate(clk->parent); @@ -992,16 +540,95 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, return rate; } +static struct clk *clkset_spi_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll2, + &clk_fin_epll, + &clk_mout_hpll.clk, +}; + +static struct clk_sources clkset_spi = { + .sources = clkset_spi_list, + .nr_sources = ARRAY_SIZE(clkset_spi_list), +}; + +static struct clksrc_clk clk_spi0 = { + .clk = { + .name = "spi_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC1_SPI0_SHIFT, + .mask = S5PC100_CLKSRC1_SPI0_MASK, + .sources = &clkset_spi, + .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT, + .reg_divider = S5PC100_CLKDIV2, + .reg_source = S5PC100_CLKSRC1, +}; + +static struct clksrc_clk clk_spi1 = { + .clk = { + .name = "spi_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC1_SPI1_SHIFT, + .mask = S5PC100_CLKSRC1_SPI1_MASK, + .sources = &clkset_spi, + .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT, + .reg_divider = S5PC100_CLKDIV2, + .reg_source = S5PC100_CLKSRC1, +}; + +static struct clksrc_clk clk_spi2 = { + .clk = { + .name = "spi_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC1_SPI2_SHIFT, + .mask = S5PC100_CLKSRC1_SPI2_MASK, + .sources = &clkset_spi, + .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT, + .reg_divider = S5PC100_CLKDIV2, + .reg_source = S5PC100_CLKSRC1, +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, +}; + +static struct clk_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + static struct clksrc_clk clk_uart_uclk1 = { .clk = { .name = "uclk1", .id = -1, .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, - .enable = s5pc1xx_sclk0_ctrl, - .set_parent = s5pc1xx_setparent_clksrc, - .get_rate = s5pc1xx_getrate_clksrc, - .set_rate = s5pc1xx_setrate_clksrc, - .round_rate = s5pc1xx_roundrate_clksrc, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, }, .shift = S5PC100_CLKSRC1_UART_SHIFT, .mask = S5PC100_CLKSRC1_UART_MASK, @@ -1011,16 +638,368 @@ static struct clksrc_clk clk_uart_uclk1 = { .reg_source = S5PC100_CLKSRC1, }; +static struct clk clk_iis_cd0 = { + .name = "iis_cdclk0", + .id = -1, +}; + +static struct clk clk_iis_cd1 = { + .name = "iis_cdclk1", + .id = -1, +}; + +static struct clk clk_iis_cd2 = { + .name = "iis_cdclk2", + .id = -1, +}; + +static struct clk clk_pcm_cd0 = { + .name = "pcm_cdclk0", + .id = -1, +}; + +static struct clk clk_pcm_cd1 = { + .name = "pcm_cdclk1", + .id = -1, +}; + +static struct clk *clkset_audio0_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd0, + &clk_pcm_cd0, + &clk_mout_hpll.clk, +}; + +static struct clk_sources clkset_audio0 = { + .sources = clkset_audio0_list, + .nr_sources = ARRAY_SIZE(clkset_audio0_list), +}; + +static struct clksrc_clk clk_audio0 = { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, + .mask = S5PC100_CLKSRC3_AUDIO0_MASK, + .sources = &clkset_audio0, + .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, + .reg_divider = S5PC100_CLKDIV4, + .reg_source = S5PC100_CLKSRC3, +}; + +static struct clk *clkset_audio1_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd1, + &clk_pcm_cd1, + &clk_mout_hpll.clk, +}; + +static struct clk_sources clkset_audio1 = { + .sources = clkset_audio1_list, + .nr_sources = ARRAY_SIZE(clkset_audio1_list), +}; + +static struct clksrc_clk clk_audio1 = { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, + .mask = S5PC100_CLKSRC3_AUDIO1_MASK, + .sources = &clkset_audio1, + .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT, + .reg_divider = S5PC100_CLKDIV4, + .reg_source = S5PC100_CLKSRC3, +}; + +static struct clk *clkset_audio2_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_iis_cd2, + &clk_mout_hpll.clk, +}; + +static struct clk_sources clkset_audio2 = { + .sources = clkset_audio2_list, + .nr_sources = ARRAY_SIZE(clkset_audio2_list), +}; + +static struct clksrc_clk clk_audio2 = { + .clk = { + .name = "audio-bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, + .mask = S5PC100_CLKSRC3_AUDIO2_MASK, + .sources = &clkset_audio2, + .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT, + .reg_divider = S5PC100_CLKDIV4, + .reg_source = S5PC100_CLKSRC3, +}; + +static struct clk *clkset_spdif_list[] = { + &clk_audio0.clk, + &clk_audio1.clk, + &clk_audio2.clk, +}; + +static struct clk_sources clkset_spdif = { + .sources = clkset_spdif_list, + .nr_sources = ARRAY_SIZE(clkset_spdif_list), +}; + +static struct clksrc_clk clk_spdif = { + .clk = { + .name = "spdif", + .id = -1, + }, + .shift = S5PC100_CLKSRC3_SPDIF_SHIFT, + .mask = S5PC100_CLKSRC3_SPDIF_MASK, + .sources = &clkset_spdif, + .reg_source = S5PC100_CLKSRC3, +}; + +static struct clk *clkset_lcd_fimc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_mout_hpll.clk, + &clk_vclk_54m, +}; + +static struct clk_sources clkset_lcd_fimc = { + .sources = clkset_lcd_fimc_list, + .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), +}; + +static struct clksrc_clk clk_lcd = { + .clk = { + .name = "lcd", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_LCD_SHIFT, + .mask = S5PC100_CLKSRC2_LCD_MASK, + .sources = &clkset_lcd_fimc, + .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clksrc_clk clk_fimc0 = { + .clk = { + .name = "fimc", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, + .mask = S5PC100_CLKSRC2_FIMC0_MASK, + .sources = &clkset_lcd_fimc, + .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clksrc_clk clk_fimc1 = { + .clk = { + .name = "fimc", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, + .mask = S5PC100_CLKSRC2_FIMC1_MASK, + .sources = &clkset_lcd_fimc, + .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clksrc_clk clk_fimc2 = { + .clk = { + .name = "fimc", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, + .enable = s5pc100_sclk1_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, + .mask = S5PC100_CLKSRC2_FIMC2_MASK, + .sources = &clkset_lcd_fimc, + .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clk *clkset_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, + &clk_mout_hpll.clk , +}; + +static struct clk_sources clkset_mmc = { + .sources = clkset_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_mmc_list), +}; + +static struct clksrc_clk clk_mmc0 = { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_MMC0_SHIFT, + .mask = S5PC100_CLKSRC2_MMC0_MASK, + .sources = &clkset_mmc, + .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clksrc_clk clk_mmc1 = { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_MMC1_SHIFT, + .mask = S5PC100_CLKSRC2_MMC1_MASK, + .sources = &clkset_mmc, + .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + +static struct clksrc_clk clk_mmc2 = { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC2_MMC2_SHIFT, + .mask = S5PC100_CLKSRC2_MMC2_MASK, + .sources = &clkset_mmc, + .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, + .reg_divider = S5PC100_CLKDIV3, + .reg_source = S5PC100_CLKSRC2, +}; + + +static struct clk *clkset_usbhost_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_mout_hpll.clk, + &clk_48m, +}; + +static struct clk_sources clkset_usbhost = { + .sources = clkset_usbhost_list, + .nr_sources = ARRAY_SIZE(clkset_usbhost_list), +}; + +static struct clksrc_clk clk_usbhost = { + .clk = { + .name = "usbhost", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, + .enable = s5pc100_sclk0_ctrl, + .set_parent = s5pc100_setparent_clksrc, + .get_rate = s5pc100_getrate_clksrc, + .set_rate = s5pc100_setrate_clksrc, + .round_rate = s5pc100_roundrate_clksrc, + }, + .shift = S5PC100_CLKSRC1_UHOST_SHIFT, + .mask = S5PC100_CLKSRC1_UHOST_MASK, + .sources = &clkset_usbhost, + .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, + .reg_divider = S5PC100_CLKDIV2, + .reg_source = S5PC100_CLKSRC1, +}; + /* Clock initialisation code */ static struct clksrc_clk *init_parents[] = { &clk_mout_apll, - &clk_mout_epll, &clk_mout_mpll, + &clk_mout_am, + &clk_mout_onenand, + &clk_mout_epll, + &clk_mout_hpll, + &clk_spi0, + &clk_spi1, + &clk_spi2, &clk_uart_uclk1, + &clk_audio0, + &clk_audio1, + &clk_audio2, + &clk_spdif, + &clk_lcd, + &clk_fimc0, + &clk_fimc1, + &clk_fimc2, + &clk_mmc0, + &clk_mmc1, + &clk_mmc2, + &clk_usbhost, }; -static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) +static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk) { struct clk_sources *srcs = clk->sources; u32 clksrc = __raw_readl(clk->reg_source); @@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) clk->clk.parent = srcs->sources[clksrc]; - printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", - clk->clk.name, clk->clk.parent->name, clksrc, - clk_get_rate(&clk->clk)); + printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n", + clk->clk.name, clk->clk.parent->name, clksrc, + print_mhz(clk_get_rate(&clk->clk))); } #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) @@ -1052,10 +1031,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) unsigned long hclk; unsigned long pclkd0; unsigned long pclk; - unsigned long apll; - unsigned long mpll; - unsigned long hpll; - unsigned long epll; + unsigned long apll, mpll, epll, hpll; unsigned int ptr; u32 clkdiv0, clkdiv1; @@ -1064,8 +1040,7 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) clkdiv0 = __raw_readl(S5PC100_CLKDIV0); clkdiv1 = __raw_readl(S5PC100_CLKDIV1); - printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", - __func__, clkdiv0, clkdiv1); + printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); @@ -1080,8 +1055,10 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); - printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", - apll, mpll, epll, hpll); + printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz" + ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n", + print_mhz(apll), print_mhz(mpll), + print_mhz(epll), print_mhz(hpll)); armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); @@ -1090,33 +1067,64 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); - printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", - armclk, hclkd0, pclkd0, hclk, pclk); + printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz," + " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz," + " PCLK=%ld.%03ld MHz\n", + print_mhz(armclk), print_mhz(hclkd0), + print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk)); clk_fout_apll.rate = apll; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; - clk_fout_apll.rate = apll; + clk_fout_hpll.rate = hpll; clk_h.rate = hclk; clk_p.rate = pclk; + clk_f.rate = armclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s5pc1xx_set_clksrc(init_parents[ptr]); + s5pc100_set_clksrc(init_parents[ptr]); } static struct clk *clks[] __initdata = { &clk_ext_xtal_mux, - &clk_mout_epll.clk, - &clk_fout_epll, + &clk_mout_apll.clk, + &clk_dout_apll, + &clk_dout_d0_bus, + &clk_dout_pclkd0, + &clk_dout_apll2, &clk_mout_mpll.clk, + &clk_mout_am.clk, + &clk_dout_d1_bus, + &clk_mout_onenand.clk, + &clk_dout_pclkd1, + &clk_dout_mpll2, + &clk_dout_cam, &clk_dout_mpll, + &clk_mout_epll.clk, + &clk_fout_epll, + &clk_iis_cd0, + &clk_iis_cd1, + &clk_iis_cd2, + &clk_pcm_cd0, + &clk_pcm_cd1, + &clk_spi0.clk, + &clk_spi1.clk, + &clk_spi2.clk, &clk_uart_uclk1.clk, - &clk_ext, - &clk_epll, - &clk_27m, - &clk_48m, - &clk_54m, + &clk_audio0.clk, + &clk_audio1.clk, + &clk_audio2.clk, + &clk_spdif.clk, + &clk_lcd.clk, + &clk_fimc0.clk, + &clk_fimc1.clk, + &clk_fimc2.clk, + &clk_mmc0.clk, + &clk_mmc1.clk, + &clk_mmc2.clk, + &clk_usbhost.clk, + &clk_arm, }; void __init s5pc100_register_clocks(void) @@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void) clkp->name, ret); } } - - clk_mpll.parent = &clk_mout_mpll.clk; - clk_epll.parent = &clk_mout_epll.clk; } -- cgit v1.2.3-70-g09d2 From 91e7d96e1f1781165a7df97e0dee1d007d3918f8 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:14 +0100 Subject: ARM: S5PC1XX: add GPIO L banks to register definition Add GPIO L0-L4 banks to register definition. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/include/mach/gpio.h | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index c74fc93d7d1..5d22961a481 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -47,6 +47,11 @@ #define S5PC1XX_GPIO_K1_NR (6) #define S5PC1XX_GPIO_K2_NR (8) #define S5PC1XX_GPIO_K3_NR (8) +#define S5PC1XX_GPIO_L0_NR (8) +#define S5PC1XX_GPIO_L1_NR (8) +#define S5PC1XX_GPIO_L2_NR (8) +#define S5PC1XX_GPIO_L3_NR (8) +#define S5PC1XX_GPIO_L4_NR (8) #define S5PC1XX_GPIO_MP00_NR (8) #define S5PC1XX_GPIO_MP01_NR (8) #define S5PC1XX_GPIO_MP02_NR (8) @@ -64,9 +69,9 @@ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) enum s3c_gpio_number { - S5PC1XX_GPIO_A0_START = 0, - S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), - S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), + S5PC1XX_GPIO_A0_START = 0, + S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), + S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), @@ -93,11 +98,17 @@ enum s3c_gpio_number { S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), - S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), + S5PC1XX_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), + S5PC1XX_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L0), + S5PC1XX_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L1), + S5PC1XX_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L2), + S5PC1XX_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L3), + S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L4), S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), + S5PC1XX_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP04), }; /* S5PC1XX GPIO number definitions. */ @@ -130,17 +141,22 @@ enum s3c_gpio_number { #define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) #define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) #define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) +#define S5PC1XX_GPL0(_nr) (S5PC1XX_GPIO_L0_START + (_nr)) +#define S5PC1XX_GPL1(_nr) (S5PC1XX_GPIO_L1_START + (_nr)) +#define S5PC1XX_GPL2(_nr) (S5PC1XX_GPIO_L2_START + (_nr)) +#define S5PC1XX_GPL3(_nr) (S5PC1XX_GPIO_L3_START + (_nr)) +#define S5PC1XX_GPL4(_nr) (S5PC1XX_GPIO_L4_START + (_nr)) #define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) #define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) #define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) #define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) #define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) +#define S5PC1XX_MP05(_nr) (S5PC1XX_GPIO_MP05_START + (_nr)) -/* the end of the S5PC1XX specific gpios */ -#define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) +/* It used the end of the S5PC1XX gpios */ #define S3C_GPIO_END S5PC1XX_GPIO_END /* define the number of gpios we need to the one after the MP04() range */ -#define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) +#define ARCH_NR_GPIOS (S5PC1XX_GPIO_END + 1) #include -- cgit v1.2.3-70-g09d2 From d7b9ace51d949e1bfec7f32d21d094cf2c683ca0 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:15 +0100 Subject: ARM: S5PC1XX: GPIO registers rename S5PC100 and S5PC110 GPIO registers differs in many places, rename all previously defined registers to be S5PC100 specific. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/include/mach/gpio.h | 244 +++++++++++++++--------------- 1 file changed, 122 insertions(+), 122 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 5d22961a481..2c4cbe8ee6b 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h @@ -18,45 +18,45 @@ #define gpio_to_irq __gpio_to_irq /* GPIO bank sizes */ -#define S5PC1XX_GPIO_A0_NR (8) -#define S5PC1XX_GPIO_A1_NR (5) -#define S5PC1XX_GPIO_B_NR (8) -#define S5PC1XX_GPIO_C_NR (5) -#define S5PC1XX_GPIO_D_NR (7) -#define S5PC1XX_GPIO_E0_NR (8) -#define S5PC1XX_GPIO_E1_NR (6) -#define S5PC1XX_GPIO_F0_NR (8) -#define S5PC1XX_GPIO_F1_NR (8) -#define S5PC1XX_GPIO_F2_NR (8) -#define S5PC1XX_GPIO_F3_NR (4) -#define S5PC1XX_GPIO_G0_NR (8) -#define S5PC1XX_GPIO_G1_NR (3) -#define S5PC1XX_GPIO_G2_NR (7) -#define S5PC1XX_GPIO_G3_NR (7) -#define S5PC1XX_GPIO_H0_NR (8) -#define S5PC1XX_GPIO_H1_NR (8) -#define S5PC1XX_GPIO_H2_NR (8) -#define S5PC1XX_GPIO_H3_NR (8) -#define S5PC1XX_GPIO_I_NR (8) -#define S5PC1XX_GPIO_J0_NR (8) -#define S5PC1XX_GPIO_J1_NR (5) -#define S5PC1XX_GPIO_J2_NR (8) -#define S5PC1XX_GPIO_J3_NR (8) -#define S5PC1XX_GPIO_J4_NR (4) -#define S5PC1XX_GPIO_K0_NR (8) -#define S5PC1XX_GPIO_K1_NR (6) -#define S5PC1XX_GPIO_K2_NR (8) -#define S5PC1XX_GPIO_K3_NR (8) -#define S5PC1XX_GPIO_L0_NR (8) -#define S5PC1XX_GPIO_L1_NR (8) -#define S5PC1XX_GPIO_L2_NR (8) -#define S5PC1XX_GPIO_L3_NR (8) -#define S5PC1XX_GPIO_L4_NR (8) -#define S5PC1XX_GPIO_MP00_NR (8) -#define S5PC1XX_GPIO_MP01_NR (8) -#define S5PC1XX_GPIO_MP02_NR (8) -#define S5PC1XX_GPIO_MP03_NR (8) -#define S5PC1XX_GPIO_MP04_NR (5) +#define S5PC100_GPIO_A0_NR (8) +#define S5PC100_GPIO_A1_NR (5) +#define S5PC100_GPIO_B_NR (8) +#define S5PC100_GPIO_C_NR (5) +#define S5PC100_GPIO_D_NR (7) +#define S5PC100_GPIO_E0_NR (8) +#define S5PC100_GPIO_E1_NR (6) +#define S5PC100_GPIO_F0_NR (8) +#define S5PC100_GPIO_F1_NR (8) +#define S5PC100_GPIO_F2_NR (8) +#define S5PC100_GPIO_F3_NR (4) +#define S5PC100_GPIO_G0_NR (8) +#define S5PC100_GPIO_G1_NR (3) +#define S5PC100_GPIO_G2_NR (7) +#define S5PC100_GPIO_G3_NR (7) +#define S5PC100_GPIO_H0_NR (8) +#define S5PC100_GPIO_H1_NR (8) +#define S5PC100_GPIO_H2_NR (8) +#define S5PC100_GPIO_H3_NR (8) +#define S5PC100_GPIO_I_NR (8) +#define S5PC100_GPIO_J0_NR (8) +#define S5PC100_GPIO_J1_NR (5) +#define S5PC100_GPIO_J2_NR (8) +#define S5PC100_GPIO_J3_NR (8) +#define S5PC100_GPIO_J4_NR (4) +#define S5PC100_GPIO_K0_NR (8) +#define S5PC100_GPIO_K1_NR (6) +#define S5PC100_GPIO_K2_NR (8) +#define S5PC100_GPIO_K3_NR (8) +#define S5PC100_GPIO_L0_NR (8) +#define S5PC100_GPIO_L1_NR (8) +#define S5PC100_GPIO_L2_NR (8) +#define S5PC100_GPIO_L3_NR (8) +#define S5PC100_GPIO_L4_NR (8) +#define S5PC100_GPIO_MP00_NR (8) +#define S5PC100_GPIO_MP01_NR (8) +#define S5PC100_GPIO_MP02_NR (8) +#define S5PC100_GPIO_MP03_NR (8) +#define S5PC100_GPIO_MP04_NR (5) /* GPIO bank numbes */ @@ -69,94 +69,94 @@ ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) enum s3c_gpio_number { - S5PC1XX_GPIO_A0_START = 0, - S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), - S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), - S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), - S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), - S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), - S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), - S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), - S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), - S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), - S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), - S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), - S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), - S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), - S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), - S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), - S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), - S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), - S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), - S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), - S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), - S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), - S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), - S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), - S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), - S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), - S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), - S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), - S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), - S5PC1XX_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), - S5PC1XX_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L0), - S5PC1XX_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L1), - S5PC1XX_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L2), - S5PC1XX_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L3), - S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_L4), - S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), - S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), - S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), - S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), - S5PC1XX_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP04), + S5PC100_GPIO_A0_START = 0, + S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0), + S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1), + S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B), + S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C), + S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D), + S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0), + S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1), + S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0), + S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1), + S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2), + S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3), + S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0), + S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1), + S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2), + S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3), + S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0), + S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1), + S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2), + S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3), + S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I), + S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0), + S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1), + S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2), + S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3), + S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4), + S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0), + S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1), + S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2), + S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3), + S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0), + S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1), + S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2), + S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3), + S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4), + S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00), + S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01), + S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02), + S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03), + S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04), }; -/* S5PC1XX GPIO number definitions. */ -#define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) -#define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) -#define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) -#define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) -#define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) -#define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) -#define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) -#define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) -#define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) -#define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) -#define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) -#define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) -#define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) -#define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) -#define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) -#define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) -#define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) -#define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) -#define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) -#define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) -#define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) -#define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) -#define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) -#define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) -#define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) -#define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) -#define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) -#define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) -#define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) -#define S5PC1XX_GPL0(_nr) (S5PC1XX_GPIO_L0_START + (_nr)) -#define S5PC1XX_GPL1(_nr) (S5PC1XX_GPIO_L1_START + (_nr)) -#define S5PC1XX_GPL2(_nr) (S5PC1XX_GPIO_L2_START + (_nr)) -#define S5PC1XX_GPL3(_nr) (S5PC1XX_GPIO_L3_START + (_nr)) -#define S5PC1XX_GPL4(_nr) (S5PC1XX_GPIO_L4_START + (_nr)) -#define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) -#define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) -#define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) -#define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) -#define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) -#define S5PC1XX_MP05(_nr) (S5PC1XX_GPIO_MP05_START + (_nr)) +/* S5PC100 GPIO number definitions. */ +#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr)) +#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr)) +#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr)) +#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr)) +#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr)) +#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr)) +#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr)) +#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr)) +#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr)) +#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr)) +#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr)) +#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr)) +#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr)) +#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr)) +#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr)) +#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr)) +#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr)) +#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr)) +#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr)) +#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr)) +#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr)) +#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr)) +#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr)) +#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr)) +#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr)) +#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr)) +#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr)) +#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr)) +#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr)) +#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr)) +#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr)) +#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) +#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) +#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) +#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr)) +#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr)) +#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr)) +#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr)) +#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr)) +#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr)) /* It used the end of the S5PC1XX gpios */ -#define S3C_GPIO_END S5PC1XX_GPIO_END +#define S3C_GPIO_END S5PC100_GPIO_END /* define the number of gpios we need to the one after the MP04() range */ -#define ARCH_NR_GPIOS (S5PC1XX_GPIO_END + 1) +#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) #include -- cgit v1.2.3-70-g09d2 From b0d5217cfb0a2357ac076977400c648cccff6154 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:16 +0100 Subject: ARM: S5PC1xx: add gpiolib and external/gpio interrupt support Add support for gpiolib calls. This is based on the gpiolib implementation from plat-s3c64xx tree. Add support for external interrupts for GPIO H banks. Add support for GPIO interrupts for all banks. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/plat-s3c/Kconfig | 6 + arch/arm/plat-s5pc1xx/Kconfig | 3 + arch/arm/plat-s5pc1xx/Makefile | 4 +- arch/arm/plat-s5pc1xx/cpu.c | 5 + arch/arm/plat-s5pc1xx/gpio-config.c | 62 +++ arch/arm/plat-s5pc1xx/gpiolib.c | 503 +++++++++++++++++++++ .../plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h | 32 ++ arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h | 44 ++ arch/arm/plat-s5pc1xx/include/plat/irqs.h | 15 +- arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | 70 +++ arch/arm/plat-s5pc1xx/irq-eint.c | 281 ++++++++++++ arch/arm/plat-s5pc1xx/irq-gpio.c | 266 +++++++++++ arch/arm/plat-s5pc1xx/irq.c | 2 +- 13 files changed, 1288 insertions(+), 5 deletions(-) create mode 100644 arch/arm/plat-s5pc1xx/gpio-config.c create mode 100644 arch/arm/plat-s5pc1xx/gpiolib.c create mode 100644 arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h create mode 100644 arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h create mode 100644 arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h create mode 100644 arch/arm/plat-s5pc1xx/irq-eint.c create mode 100644 arch/arm/plat-s5pc1xx/irq-gpio.c (limited to 'arch') diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 8931c5f0e46..f155a849e70 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -159,6 +159,12 @@ config S3C_GPIO_CFG_S3C64XX Internal configuration to enable S3C64XX style GPIO configuration functions. +config S5P_GPIO_CFG_S5PC1XX + bool + help + Internal configuration to enable S5PC1XX style GPIO configuration + functions. + # DMA config S3C_DMA diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index a8a711c3c06..86edd27c7f2 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -15,6 +15,9 @@ config PLAT_S5PC1XX select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX + select S3C_GPIO_CFG_S3C64XX + select S5P_GPIO_CFG_S5PC1XX help Base platform code for any Samsung S5PC1XX device diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index ebbf36490f4..e860813cb8d 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile @@ -13,8 +13,9 @@ obj- := obj-y += dev-uart.o obj-y += cpu.o -obj-y += irq.o +obj-y += irq.o irq-gpio.o irq-eint.o obj-y += clock.o +obj-y += gpiolib.o # CPU support @@ -23,5 +24,6 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o # Device setup +obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c index e8f347218ec..02baeaa2a12 100644 --- a/arch/arm/plat-s5pc1xx/cpu.c +++ b/arch/arm/plat-s5pc1xx/cpu.c @@ -59,6 +59,11 @@ static struct map_desc s5pc1xx_iodesc[] __initdata = { .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5PC1XX_VA_GPIO, + .pfn = __phys_to_pfn(S5PC100_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5PC1XX_VA_CHIPID, .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c new file mode 100644 index 00000000000..bba675df9c7 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/gpio-config.c @@ -0,0 +1,62 @@ +/* linux/arch/arm/plat-s5pc1xx/gpio-config.c + * + * Copyright 2009 Samsung Electronics + * + * S5PC1XX GPIO Configuration. + * + * Based on plat-s3c64xx/gpio-config.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include + +#include +#include + +s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + void __iomem *reg; + int shift = off * 2; + u32 drvstr; + + if (!chip) + return -EINVAL; + + reg = chip->base + 0x0C; + + drvstr = __raw_readl(reg); + drvstr = 0xffff & (0x3 << shift); + drvstr = drvstr >> shift; + + return (__force s5p_gpio_drvstr_t)drvstr; +} +EXPORT_SYMBOL(s5p_gpio_get_drvstr); + +int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, + s5p_gpio_drvstr_t drvstr) +{ + struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); + void __iomem *reg; + int shift = off * 2; + u32 tmp; + + if (!chip) + return -EINVAL; + + reg = chip->base + 0x0C; + + tmp = __raw_readl(reg); + tmp |= drvstr << shift; + + __raw_writel(tmp, reg); + + return 0; +} +EXPORT_SYMBOL(s5p_gpio_set_drvstr); diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c new file mode 100644 index 00000000000..facb410e7a7 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/gpiolib.c @@ -0,0 +1,503 @@ +/* + * arch/arm/plat-s5pc1xx/gpiolib.c + * + * Copyright 2009 Samsung Electronics Co + * Kyungmin Park + * + * S5PC1XX - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +/* S5PC100 GPIO bank summary: + * + * Bank GPIOs Style INT Type + * A0 8 4Bit GPIO_INT0 + * A1 5 4Bit GPIO_INT1 + * B 8 4Bit GPIO_INT2 + * C 5 4Bit GPIO_INT3 + * D 7 4Bit GPIO_INT4 + * E0 8 4Bit GPIO_INT5 + * E1 6 4Bit GPIO_INT6 + * F0 8 4Bit GPIO_INT7 + * F1 8 4Bit GPIO_INT8 + * F2 8 4Bit GPIO_INT9 + * F3 4 4Bit GPIO_INT10 + * G0 8 4Bit GPIO_INT11 + * G1 3 4Bit GPIO_INT12 + * G2 7 4Bit GPIO_INT13 + * G3 7 4Bit GPIO_INT14 + * H0 8 4Bit WKUP_INT + * H1 8 4Bit WKUP_INT + * H2 8 4Bit WKUP_INT + * H3 8 4Bit WKUP_INT + * I 8 4Bit GPIO_INT15 + * J0 8 4Bit GPIO_INT16 + * J1 5 4Bit GPIO_INT17 + * J2 8 4Bit GPIO_INT18 + * J3 8 4Bit GPIO_INT19 + * J4 4 4Bit GPIO_INT20 + * K0 8 4Bit None + * K1 6 4Bit None + * K2 8 4Bit None + * K3 8 4Bit None + * L0 8 4Bit None + * L1 8 4Bit None + * L2 8 4Bit None + * L3 8 4Bit None + */ + +#define OFF_GPCON (0x00) +#define OFF_GPDAT (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + +#if 1 +#define gpio_dbg(x...) do { } while (0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG x) +#endif + +/* The s5pc1xx_gpiolib routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of + * the output. + */ + +static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + OFF_GPCON); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +static int s5pc1xx_gpiolib_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + OFF_GPDAT); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + OFF_GPDAT); + __raw_writel(con, base + OFF_GPCON); + __raw_writel(dat, base + OFF_GPDAT); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + return S3C_IRQ_GPIO(chip->base + offset); +} + +static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) +{ + int base; + + base = chip->base - S5PC100_GPH0(0); + if (base == 0) + return IRQ_EINT(offset); + base = chip->base - S5PC100_GPH1(0); + if (base == 0) + return IRQ_EINT(8 + offset); + base = chip->base - S5PC100_GPH2(0); + if (base == 0) + return IRQ_EINT(16 + offset); + base = chip->base - S5PC100_GPH3(0); + if (base == 0) + return IRQ_EINT(24 + offset); + return -EINVAL; +} + +static struct s3c_gpio_cfg gpio_cfg = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_cfg_eint = { + .cfg_eint = 0xf, + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_chip s5pc100_gpio_chips[] = { + { + .base = S5PC100_GPA0_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPA0(0), + .ngpio = S5PC100_GPIO_A0_NR, + .label = "GPA0", + }, + }, { + .base = S5PC100_GPA1_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPA1(0), + .ngpio = S5PC100_GPIO_A1_NR, + .label = "GPA1", + }, + }, { + .base = S5PC100_GPB_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPB(0), + .ngpio = S5PC100_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S5PC100_GPC_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPC(0), + .ngpio = S5PC100_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5PC100_GPD_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPD(0), + .ngpio = S5PC100_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S5PC100_GPE0_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPE0(0), + .ngpio = S5PC100_GPIO_E0_NR, + .label = "GPE0", + }, + }, { + .base = S5PC100_GPE1_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPE1(0), + .ngpio = S5PC100_GPIO_E1_NR, + .label = "GPE1", + }, + }, { + .base = S5PC100_GPF0_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPF0(0), + .ngpio = S5PC100_GPIO_F0_NR, + .label = "GPF0", + }, + }, { + .base = S5PC100_GPF1_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPF1(0), + .ngpio = S5PC100_GPIO_F1_NR, + .label = "GPF1", + }, + }, { + .base = S5PC100_GPF2_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPF2(0), + .ngpio = S5PC100_GPIO_F2_NR, + .label = "GPF2", + }, + }, { + .base = S5PC100_GPF3_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPF3(0), + .ngpio = S5PC100_GPIO_F3_NR, + .label = "GPF3", + }, + }, { + .base = S5PC100_GPG0_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPG0(0), + .ngpio = S5PC100_GPIO_G0_NR, + .label = "GPG0", + }, + }, { + .base = S5PC100_GPG1_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPG1(0), + .ngpio = S5PC100_GPIO_G1_NR, + .label = "GPG1", + }, + }, { + .base = S5PC100_GPG2_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPG2(0), + .ngpio = S5PC100_GPIO_G2_NR, + .label = "GPG2", + }, + }, { + .base = S5PC100_GPG3_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPG3(0), + .ngpio = S5PC100_GPIO_G3_NR, + .label = "GPG3", + }, + }, { + .base = S5PC100_GPH0_BASE, + .config = &gpio_cfg_eint, + .chip = { + .base = S5PC100_GPH0(0), + .ngpio = S5PC100_GPIO_H0_NR, + .label = "GPH0", + }, + }, { + .base = S5PC100_GPH1_BASE, + .config = &gpio_cfg_eint, + .chip = { + .base = S5PC100_GPH1(0), + .ngpio = S5PC100_GPIO_H1_NR, + .label = "GPH1", + }, + }, { + .base = S5PC100_GPH2_BASE, + .config = &gpio_cfg_eint, + .chip = { + .base = S5PC100_GPH2(0), + .ngpio = S5PC100_GPIO_H2_NR, + .label = "GPH2", + }, + }, { + .base = S5PC100_GPH3_BASE, + .config = &gpio_cfg_eint, + .chip = { + .base = S5PC100_GPH3(0), + .ngpio = S5PC100_GPIO_H3_NR, + .label = "GPH3", + }, + }, { + .base = S5PC100_GPI_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPI(0), + .ngpio = S5PC100_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5PC100_GPJ0_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPJ0(0), + .ngpio = S5PC100_GPIO_J0_NR, + .label = "GPJ0", + }, + }, { + .base = S5PC100_GPJ1_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPJ1(0), + .ngpio = S5PC100_GPIO_J1_NR, + .label = "GPJ1", + }, + }, { + .base = S5PC100_GPJ2_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPJ2(0), + .ngpio = S5PC100_GPIO_J2_NR, + .label = "GPJ2", + }, + }, { + .base = S5PC100_GPJ3_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPJ3(0), + .ngpio = S5PC100_GPIO_J3_NR, + .label = "GPJ3", + }, + }, { + .base = S5PC100_GPJ4_BASE, + .config = &gpio_cfg, + .chip = { + .base = S5PC100_GPJ4(0), + .ngpio = S5PC100_GPIO_J4_NR, + .label = "GPJ4", + }, + }, { + .base = S5PC100_GPK0_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPK0(0), + .ngpio = S5PC100_GPIO_K0_NR, + .label = "GPK0", + }, + }, { + .base = S5PC100_GPK1_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPK1(0), + .ngpio = S5PC100_GPIO_K1_NR, + .label = "GPK1", + }, + }, { + .base = S5PC100_GPK2_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPK2(0), + .ngpio = S5PC100_GPIO_K2_NR, + .label = "GPK2", + }, + }, { + .base = S5PC100_GPK3_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPK3(0), + .ngpio = S5PC100_GPIO_K3_NR, + .label = "GPK3", + }, + }, { + .base = S5PC100_GPL0_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPL0(0), + .ngpio = S5PC100_GPIO_L0_NR, + .label = "GPL0", + }, + }, { + .base = S5PC100_GPL1_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPL1(0), + .ngpio = S5PC100_GPIO_L1_NR, + .label = "GPL1", + }, + }, { + .base = S5PC100_GPL2_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPL2(0), + .ngpio = S5PC100_GPIO_L2_NR, + .label = "GPL2", + }, + }, { + .base = S5PC100_GPL3_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPL3(0), + .ngpio = S5PC100_GPIO_L3_NR, + .label = "GPL3", + }, + }, { + .base = S5PC100_GPL4_BASE, + .config = &gpio_cfg_noint, + .chip = { + .base = S5PC100_GPL4(0), + .ngpio = S5PC100_GPIO_L4_NR, + .label = "GPL4", + }, + }, +}; + +/* FIXME move from irq-gpio.c */ +extern struct irq_chip s5pc1xx_gpioint; +extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); + +static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = s5pc1xx_gpiolib_input; + chip->chip.direction_output = s5pc1xx_gpiolib_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); + + /* Interrupt */ + if (chip->config == &gpio_cfg) { + int i, irq; + + chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; + + for (i = 0; i < chip->chip.ngpio; i++) { + irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; + set_irq_chip(irq, &s5pc1xx_gpioint); + set_irq_data(irq, &chip->chip); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + } else if (chip->config == &gpio_cfg_eint) + chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; +} + +static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips, + int nr_chips, + void (*fn)(struct s3c_gpio_chip *)) +{ + for (; nr_chips > 0; nr_chips--, chips++) { + if (fn) + (fn)(chips); + s3c_gpiolib_add(chips); + } +} + +static __init int s5pc1xx_gpiolib_init(void) +{ + struct s3c_gpio_chip *chips; + int nr_chips; + + chips = s5pc100_gpio_chips; + nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); + + s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link); + /* Interrupt */ + set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); + + return 0; +} +core_initcall(s5pc1xx_gpiolib_init); diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h new file mode 100644 index 00000000000..72ad59f61ef --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h @@ -0,0 +1,32 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h + * + * Copyright 2009 Samsung Electronic + * + * S5PC1XX Platform - GPIO pin configuration + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* This file contains the necessary definitions to get the basic gpio + * pin configuration done such as setting a pin to input or output or + * changing the pull-{up,down} configurations. + */ + +#ifndef __GPIO_CFG_S5PC1XX_H +#define __GPIO_CFG_S5PC1XX_H __FILE__ + +typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; + +#define S5P_GPIO_DRVSTR_LV1 0x00 +#define S5P_GPIO_DRVSTR_LV2 0x01 +#define S5P_GPIO_DRVSTR_LV3 0x10 +#define S5P_GPIO_DRVSTR_LV4 0x11 + +extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off); + +extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, + s5p_gpio_drvstr_t drvstr); + +#endif /* __GPIO_CFG_S5PC1XX_H */ diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h new file mode 100644 index 00000000000..33ad267e847 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h + * + * Copyright 2009 Samsung Electronics Co. + * + * External Interrupt (GPH0 ~ GPH3) control register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0) +#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4) +#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8) +#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC) +#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4)) + +#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80) +#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84) +#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88) +#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C) +#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90) +#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94) +#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98) +#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C) +#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4)) + +#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100) +#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104) +#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108) +#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C) +#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4)) + +#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140) +#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144) +#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148) +#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C) +#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4)) + +#define S5PC1XX_WKUP_INT_LOWLEV (0x00) +#define S5PC1XX_WKUP_INT_HILEV (0x01) +#define S5PC1XX_WKUP_INT_FALLEDGE (0x02) +#define S5PC1XX_WKUP_INT_RISEEDGE (0x03) +#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04) diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index f07d8c3b25d..ef8736366f0 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h @@ -171,12 +171,21 @@ #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) +/* External interrupt */ #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) -#define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) -#define IRQ_EINT(x) S3C_EINT(x) +#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) +#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) +#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0)) -#define NR_IRQS (IRQ_EINT(31)+1) +/* GPIO interrupt */ +#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) +#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) + +/* + * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs + */ +#define NR_IRQS (S3C_IRQ_GPIO(320) + 1) #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h new file mode 100644 index 00000000000..43c7bc8bf78 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h @@ -0,0 +1,70 @@ +/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min + * + * S5PC1XX - GPIO register definitions + */ + +#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H +#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ + +#include + +/* S5PC100 */ +#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO +#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) +#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) +#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) +#define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060) +#define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080) +#define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0) +#define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0) +#define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0) +#define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100) +#define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120) +#define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140) +#define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160) +#define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180) +#define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0) +#define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0) +#define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00) +#define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20) +#define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40) +#define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60) +#define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0) +#define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200) +#define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220) +#define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240) +#define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260) +#define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280) +#define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0) +#define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0) +#define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0) +#define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300) +#define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320) +#define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340) +#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) +#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) +#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) +#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00) + +#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) +#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) + +/* PDNEN */ +#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) +#define S5PC100_PDNEN_CFG_AUTO (0 << 1) +#define S5PC100_PDNEN_POWERDOWN (1 << 0) +#define S5PC100_PDNEN_NORMAL (0 << 0) + +/* Common part */ +/* External interrupt base is same at both s5pc100 and s5pc110 */ +#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE) + +#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) +#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) + +#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ + diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c new file mode 100644 index 00000000000..373122f57d5 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/irq-eint.c @@ -0,0 +1,281 @@ +/* + * linux/arch/arm/plat-s5pc1xx/irq-eint.c + * + * Copyright 2009 Samsung Electronics Co. + * Byungho Min + * Kyungin Park + * + * Based on plat-s3c64xx/irq-eint.c + * + * S5PC1XX - Interrupt handling for IRQ_EINT(x) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include +#include +#include + +/* + * bank is a group of external interrupt + * bank0 means EINT0 ... EINT7 + * bank1 means EINT8 ... EINT15 + * bank2 means EINT16 ... EINT23 + * bank3 means EINT24 ... EINT31 + */ + +static inline int s3c_get_eint(unsigned int irq) +{ + int real; + + if (irq < IRQ_EINT16_31) + real = (irq - IRQ_EINT0); + else + real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0; + + return real; +} + +static inline int s3c_get_bank(unsigned int irq) +{ + return s3c_get_eint(irq) >> 3; +} + +static inline int s3c_eint_to_bit(unsigned int irq) +{ + int real, bit; + + real = s3c_get_eint(irq); + bit = 1 << (real & (8 - 1)); + + return bit; +} + +static inline void s3c_irq_eint_mask(unsigned int irq) +{ + u32 mask; + u32 bank = s3c_get_bank(irq); + + mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); + mask |= s3c_eint_to_bit(irq); + __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); +} + +static void s3c_irq_eint_unmask(unsigned int irq) +{ + u32 mask; + u32 bank = s3c_get_bank(irq); + + mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); + mask &= ~(s3c_eint_to_bit(irq)); + __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); +} + +static inline void s3c_irq_eint_ack(unsigned int irq) +{ + u32 bank = s3c_get_bank(irq); + + __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank)); +} + +static void s3c_irq_eint_maskack(unsigned int irq) +{ + /* compiler should in-line these */ + s3c_irq_eint_mask(irq); + s3c_irq_eint_ack(irq); +} + +static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) +{ + u32 bank = s3c_get_bank(irq); + int real = s3c_get_eint(irq); + int gpio, shift, sfn; + u32 ctrl, con = 0; + + switch (type) { + case IRQ_TYPE_NONE: + printk(KERN_WARNING "No edge setting!\n"); + break; + + case IRQ_TYPE_EDGE_RISING: + con = S5PC1XX_WKUP_INT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_FALLING: + con = S5PC1XX_WKUP_INT_FALLEDGE; + break; + + case IRQ_TYPE_EDGE_BOTH: + con = S5PC1XX_WKUP_INT_BOTHEDGE; + break; + + case IRQ_TYPE_LEVEL_LOW: + con = S5PC1XX_WKUP_INT_LOWLEV; + break; + + case IRQ_TYPE_LEVEL_HIGH: + con = S5PC1XX_WKUP_INT_HILEV; + break; + + default: + printk(KERN_ERR "No such irq type %d", type); + return -EINVAL; + } + + gpio = real & (8 - 1); + shift = gpio << 2; + + ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank)); + ctrl &= ~(0x7 << shift); + ctrl |= con << shift; + __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank)); + + switch (real) { + case 0 ... 7: + gpio = S5PC100_GPH0(gpio); + break; + case 8 ... 15: + gpio = S5PC100_GPH1(gpio); + break; + case 16 ... 23: + gpio = S5PC100_GPH2(gpio); + break; + case 24 ... 31: + gpio = S5PC100_GPH3(gpio); + break; + default: + return -EINVAL; + } + + sfn = S3C_GPIO_SFN(0x2); + s3c_gpio_cfgpin(gpio, sfn); + + return 0; +} + +static struct irq_chip s3c_irq_eint = { + .name = "EINT", + .mask = s3c_irq_eint_mask, + .unmask = s3c_irq_eint_unmask, + .mask_ack = s3c_irq_eint_maskack, + .ack = s3c_irq_eint_ack, + .set_type = s3c_irq_eint_set_type, + .set_wake = s3c_irqext_wake, +}; + +/* s3c_irq_demux_eint + * + * This function demuxes the IRQ from external interrupts, + * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into + * the specific handlers s3c_irq_demux_eintX_Y. + */ +static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) +{ + u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3))); + u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3))); + unsigned int irq; + + status &= ~mask; + status &= (1 << (end - start + 1)) - 1; + + for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { + if (status & 1) + generic_handle_irq(irq); + + status >>= 1; + } +} + +static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) +{ + s3c_irq_demux_eint(16, 23); + s3c_irq_demux_eint(24, 31); +} + +/* + * Handle EINT0 ... EINT15 at VIC directly + */ +static void s3c_irq_vic_eint_mask(unsigned int irq) +{ + void __iomem *base = get_irq_chip_data(irq); + unsigned int real; + + s3c_irq_eint_mask(irq); + real = s3c_get_eint(irq); + writel(1 << real, base + VIC_INT_ENABLE_CLEAR); +} + +static void s3c_irq_vic_eint_unmask(unsigned int irq) +{ + void __iomem *base = get_irq_chip_data(irq); + unsigned int real; + + s3c_irq_eint_unmask(irq); + real = s3c_get_eint(irq); + writel(1 << real, base + VIC_INT_ENABLE); +} + +static inline void s3c_irq_vic_eint_ack(unsigned int irq) +{ + u32 bit; + u32 bank = s3c_get_bank(irq); + + bit = s3c_eint_to_bit(irq); + __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank)); +} + +static void s3c_irq_vic_eint_maskack(unsigned int irq) +{ + /* compiler should in-line these */ + s3c_irq_vic_eint_mask(irq); + s3c_irq_vic_eint_ack(irq); +} + +static struct irq_chip s3c_irq_vic_eint = { + .name = "EINT", + .mask = s3c_irq_vic_eint_mask, + .unmask = s3c_irq_vic_eint_unmask, + .mask_ack = s3c_irq_vic_eint_maskack, + .ack = s3c_irq_vic_eint_ack, + .set_type = s3c_irq_eint_set_type, + .set_wake = s3c_irqext_wake, +}; + +static int __init s5pc1xx_init_irq_eint(void) +{ + int irq; + + for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) { + set_irq_chip(irq, &s3c_irq_vic_eint); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { + set_irq_chip(irq, &s3c_irq_eint); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31); + + return 0; +} + +arch_initcall(s5pc1xx_init_irq_eint); diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c new file mode 100644 index 00000000000..fecca7a679b --- /dev/null +++ b/arch/arm/plat-s5pc1xx/irq-gpio.c @@ -0,0 +1,266 @@ +/* + * arch/arm/plat-s5pc1xx/irq-gpio.c + * + * Copyright (C) 2009 Samsung Electronics + * + * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) + +#define CON_OFFSET 0x700 +#define MASK_OFFSET 0x900 +#define PEND_OFFSET 0xA00 +#define CON_OFFSET_2 0xE00 +#define MASK_OFFSET_2 0xF00 +#define PEND_OFFSET_2 0xF40 + +#define GPIOINT_LEVEL_LOW 0x0 +#define GPIOINT_LEVEL_HIGH 0x1 +#define GPIOINT_EDGE_FALLING 0x2 +#define GPIOINT_EDGE_RISING 0x3 +#define GPIOINT_EDGE_BOTH 0x4 + +static int group_to_con_offset(int group) +{ + return group << 2; +} + +static int group_to_mask_offset(int group) +{ + return group << 2; +} + +static int group_to_pend_offset(int group) +{ + return group << 2; +} + +static int s5pc1xx_get_start(unsigned int group) +{ + switch (group) { + case 0: return S5PC100_GPIO_A0_START; + case 1: return S5PC100_GPIO_A1_START; + case 2: return S5PC100_GPIO_B_START; + case 3: return S5PC100_GPIO_C_START; + case 4: return S5PC100_GPIO_D_START; + case 5: return S5PC100_GPIO_E0_START; + case 6: return S5PC100_GPIO_E1_START; + case 7: return S5PC100_GPIO_F0_START; + case 8: return S5PC100_GPIO_F1_START; + case 9: return S5PC100_GPIO_F2_START; + case 10: return S5PC100_GPIO_F3_START; + case 11: return S5PC100_GPIO_G0_START; + case 12: return S5PC100_GPIO_G1_START; + case 13: return S5PC100_GPIO_G2_START; + case 14: return S5PC100_GPIO_G3_START; + case 15: return S5PC100_GPIO_I_START; + case 16: return S5PC100_GPIO_J0_START; + case 17: return S5PC100_GPIO_J1_START; + case 18: return S5PC100_GPIO_J2_START; + case 19: return S5PC100_GPIO_J3_START; + case 20: return S5PC100_GPIO_J4_START; + default: + BUG(); + } + + return -EINVAL; +} + +static int s5pc1xx_get_group(unsigned int irq) +{ + irq -= S3C_IRQ_GPIO(0); + + switch (irq) { + case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1: + return 0; + case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1: + return 1; + case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1: + return 2; + case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1: + return 3; + case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1: + return 4; + case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1: + return 5; + case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1: + return 6; + case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1: + return 7; + case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1: + return 8; + case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1: + return 9; + case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1: + return 10; + case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1: + return 11; + case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1: + return 12; + case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1: + return 13; + case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1: + return 14; + case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1: + return 15; + case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1: + return 16; + case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1: + return 17; + case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1: + return 18; + case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1: + return 19; + case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1: + return 20; + default: + BUG(); + } + + return -EINVAL; +} + +static int s5pc1xx_get_offset(unsigned int irq) +{ + struct gpio_chip *chip = get_irq_data(irq); + return irq - S3C_IRQ_GPIO(chip->base); +} + +static void s5pc1xx_gpioint_ack(unsigned int irq) +{ + int group, offset, pend_offset; + unsigned int value; + + group = s5pc1xx_get_group(irq); + offset = s5pc1xx_get_offset(irq); + pend_offset = group_to_pend_offset(group); + + value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); + value |= 1 << offset; + __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); +} + +static void s5pc1xx_gpioint_mask(unsigned int irq) +{ + int group, offset, mask_offset; + unsigned int value; + + group = s5pc1xx_get_group(irq); + offset = s5pc1xx_get_offset(irq); + mask_offset = group_to_mask_offset(group); + + value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + value |= 1 << offset; + __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); +} + +static void s5pc1xx_gpioint_unmask(unsigned int irq) +{ + int group, offset, mask_offset; + unsigned int value; + + group = s5pc1xx_get_group(irq); + offset = s5pc1xx_get_offset(irq); + mask_offset = group_to_mask_offset(group); + + value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + value &= ~(1 << offset); + __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); +} + +static void s5pc1xx_gpioint_mask_ack(unsigned int irq) +{ + s5pc1xx_gpioint_mask(irq); + s5pc1xx_gpioint_ack(irq); +} + +static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) +{ + int group, offset, con_offset; + unsigned int value; + + group = s5pc1xx_get_group(irq); + offset = s5pc1xx_get_offset(irq); + con_offset = group_to_con_offset(group); + + switch (type) { + case IRQ_TYPE_NONE: + printk(KERN_WARNING "No irq type\n"); + return -EINVAL; + case IRQ_TYPE_EDGE_RISING: + type = GPIOINT_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + type = GPIOINT_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + type = GPIOINT_EDGE_BOTH; + break; + case IRQ_TYPE_LEVEL_HIGH: + type = GPIOINT_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + type = GPIOINT_LEVEL_LOW; + break; + default: + BUG(); + } + + + value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); + value &= ~(0xf << (offset * 0x4)); + value |= (type << (offset * 0x4)); + __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); + + return 0; +} + +struct irq_chip s5pc1xx_gpioint = { + .name = "GPIO", + .ack = s5pc1xx_gpioint_ack, + .mask = s5pc1xx_gpioint_mask, + .mask_ack = s5pc1xx_gpioint_mask_ack, + .unmask = s5pc1xx_gpioint_unmask, + .set_type = s5pc1xx_gpioint_set_type, +}; + +void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) +{ + int group, offset, pend_offset, mask_offset; + int real_irq, group_end; + unsigned int pend, mask; + + group_end = 21; + + for (group = 0; group < group_end; group++) { + pend_offset = group_to_pend_offset(group); + pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); + if (!pend) + continue; + + mask_offset = group_to_mask_offset(group); + mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); + pend &= ~mask; + + for (offset = 0; offset < 8; offset++) { + if (pend & (1 << offset)) { + real_irq = s5pc1xx_get_start(group) + offset; + generic_handle_irq(S3C_IRQ_GPIO(real_irq)); + } + } + } +} diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index 80d6dd942cb..e44fd04ef33 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c @@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq) { u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - reg &= 0x1f; + reg &= 0x1f; /* mask out pending interrupts */ reg |= (1 << 5) << (irq - IRQ_TIMER0); __raw_writel(reg, S3C64XX_TINT_CSTAT); } -- cgit v1.2.3-70-g09d2 From c3fcf5d1a43cc27393f77d07b1323232095173de Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:17 +0100 Subject: ARM: S5PC1XX: add cpu idle and system reset support Add CPU idle support by a call to SoC build-in power management core. Add system reset support by a simple write to system controll register. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/cpu.c | 22 +++++++ arch/arm/mach-s5pc100/include/mach/system.h | 13 +++- arch/arm/plat-s3c/include/plat/cpu.h | 6 ++ arch/arm/plat-s5pc1xx/include/plat/regs-power.h | 84 +++++++++++++++++++++++++ 4 files changed, 122 insertions(+), 3 deletions(-) create mode 100644 arch/arm/plat-s5pc1xx/include/plat/regs-power.h (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index 0e718890da3..a23ca5795bc 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -22,6 +22,8 @@ #include #include +#include + #include #include #include @@ -32,6 +34,7 @@ #include #include +#include #include #include @@ -45,6 +48,23 @@ static struct map_desc s5pc100_iodesc[] __initdata = { }; +static void s5pc100_idle(void) +{ + unsigned long tmp; + + tmp = __raw_readl(S5PC100_PWR_CFG); + tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE; + tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK; + tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE; + __raw_writel(tmp, S5PC100_PWR_CFG); + + tmp = __raw_readl(S5PC100_OTHERS); + tmp |= S5PC100_PMU_INT_DISABLE; + __raw_writel(tmp, S5PC100_OTHERS); + + cpu_do_idle(); +} + /* s5pc100_map_io * * register the standard cpu IO areas @@ -93,5 +113,7 @@ int __init s5pc100_init(void) { printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); + s5pc1xx_idle = s5pc100_idle; + return sysdev_register(&s5pc100_sysdev); } diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index e3901437547..f0d31a2a598 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h @@ -11,14 +11,21 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ +#include +#include +#include + +void (*s5pc1xx_idle)(void); + static void arch_idle(void) { - /* nothing here yet */ + if (s5pc1xx_idle) + s5pc1xx_idle(); } static void arch_reset(char mode, const char *cmd) { - /* nothing here yet */ + __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET); + return; } - #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index fbc3d498e02..d1131ca11e9 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -12,6 +12,9 @@ /* todo - fix when rmk changes iodescs to use `void __iomem *` */ +#ifndef __SAMSUNG_PLAT_CPU_H +#define __SAMSUNG_PLAT_CPU_H + #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } #ifndef MHZ @@ -73,3 +76,6 @@ extern struct sysdev_class s3c2443_sysclass; extern struct sysdev_class s3c6410_sysclass; extern struct sysdev_class s3c64xx_sysclass; +extern void (*s5pc1xx_idle)(void); + +#endif diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h new file mode 100644 index 00000000000..02ffa491b53 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h @@ -0,0 +1,84 @@ +/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h + * + * Copyright 2009 Samsung Electronics Co. + * Jongse Won + * + * S5PC1XX clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARM_REGS_PWR +#define __ASM_ARM_REGS_PWR __FILE__ + +#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x)) + +/* s5pc100 (0xE0108000) register for power management */ +#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0) +#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4) +#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10) +#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14) +#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18) +#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C) +#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100) +#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104) +#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108) +#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110) +#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114) +#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200) +#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300) +#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304) +#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308) +#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400) +#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404) +#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408) +#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C) +#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410) +#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414) +#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418) +#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C) +#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500) +#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504) +#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508) +#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C) +#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510) +#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514) +#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518) +#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C) +#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520) +#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600) +#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604) +#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608) +#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C) +#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610) +#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614) +#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618) +#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C) +#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620) +#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700) +#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704) +#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708) +#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C) +#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710) +#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714) +#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718) +#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C) +#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724) + +/* PWR_CFG */ +#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31) +#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5) +#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5) +#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5) +#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5) +#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5) + +/* SLEEP_CFG */ +#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0) + +/* OTHERS */ +#define S5PC100_PMU_INT_DISABLE (1 << 24) + +#endif /* __ASM_ARM_REGS_PWR */ -- cgit v1.2.3-70-g09d2 From d7ab33a0b3511e3d738a7b52f20ee83daede4465 Mon Sep 17 00:00:00 2001 From: Pawel Osciak Date: Tue, 17 Nov 2009 08:41:18 +0100 Subject: ARM: S3C: Prepare s3c64xx-specific s3c-fb register definition for reuse S5PC1xx Samsung SOC series has very similar frame buffer hardware, so a lot of the code can be shared. Moved s3c64xx-specific s3c-fb register definitions from mach-s3c6400 to common platform directory as regs-fb-v4.h. The new v4 file will be common for S3C6400, S3C6410, S5PC100 and possibly others. Some s3c64xx series specific defines (palette handling) were left in s3c-6400/mach/regs-fb.h, because it is handled differently in S5PC1xx series. Signed-off-by: Pawel Osciak Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s3c6400/include/mach/regs-fb.h | 236 +-------------------------- arch/arm/plat-s3c/include/plat/regs-fb-v4.h | 235 ++++++++++++++++++++++++++ 2 files changed, 244 insertions(+), 227 deletions(-) create mode 100644 arch/arm/plat-s3c/include/plat/regs-fb-v4.h (limited to 'arch') diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h index 47019795ce0..f56611526c6 100644 --- a/arch/arm/mach-s3c6400/include/mach/regs-fb.h +++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h @@ -1,195 +1,30 @@ -/* arch/arm/mach-s3c6400/include/mach/regs-fb.h - * +/* * Copyright 2008 Openmoko, Inc. * Copyright 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C64XX - new-style framebuffer register definitions + * Copyright 2009 Samsung Electronics Co. * - * This is the register set for the new style framebuffer interface - * found from the S3C2443 onwards and specifically the S3C64XX series - * S3C6400 and S3C6410. + * Pawel Osciak + * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks * - * The file contains the cpu specific items which change between whichever - * architecture is selected. See for the core definitions - * that are the same. + * Framebuffer register definitions for Samsung S3C64xx. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/* include the core definitions here, in case we really do need to - * override them at a later date. -*/ - -#include - -#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ -#define VIDCON1_FSTATUS_EVEN (1 << 15) - -/* Video timing controls */ -#define VIDTCON0 (0x10) -#define VIDTCON1 (0x14) -#define VIDTCON2 (0x18) - -/* Window position controls */ - -#define WINCON(_win) (0x20 + ((_win) * 4)) - -/* OSD1 and OSD4 do not have register D */ - -#define VIDOSD_A(_win) (0x40 + ((_win) * 16)) -#define VIDOSD_B(_win) (0x44 + ((_win) * 16)) -#define VIDOSD_C(_win) (0x48 + ((_win) * 16)) -#define VIDOSD_D(_win) (0x4C + ((_win) * 16)) - -/* Video buffer addresses */ - -#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) -#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) -#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) -#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) -#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) - -#define VIDINTCON0 (0x130) - -#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) - -/* WINCONx */ - -#define WINCONx_CSCWIDTH_MASK (0x3 << 26) -#define WINCONx_CSCWIDTH_SHIFT (26) -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) - -#define WINCONx_ENLOCAL (1 << 22) -#define WINCONx_BUFSTATUS (1 << 21) -#define WINCONx_BUFSEL (1 << 20) -#define WINCONx_BUFAUTOEN (1 << 19) -#define WINCONx_YCbCr (1 << 13) - -#define WINCON1_LOCALSEL_CAMIF (1 << 23) - -#define WINCON2_LOCALSEL_CAMIF (1 << 23) -#define WINCON2_BLD_PIX (1 << 6) - -#define WINCON2_ALPHA_SEL (1 << 1) -#define WINCON2_BPPMODE_MASK (0xf << 2) -#define WINCON2_BPPMODE_SHIFT (2) -#define WINCON2_BPPMODE_1BPP (0x0 << 2) -#define WINCON2_BPPMODE_2BPP (0x1 << 2) -#define WINCON2_BPPMODE_4BPP (0x2 << 2) -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) - -#define WINCON3_BLD_PIX (1 << 6) - -#define WINCON3_ALPHA_SEL (1 << 1) -#define WINCON3_BPPMODE_MASK (0xf << 2) -#define WINCON3_BPPMODE_SHIFT (2) -#define WINCON3_BPPMODE_1BPP (0x0 << 2) -#define WINCON3_BPPMODE_2BPP (0x1 << 2) -#define WINCON3_BPPMODE_4BPP (0x2 << 2) -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) - -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) - -#define DITHMODE (0x170) -#define WINxMAP(_win) (0x180 + ((_win) * 4)) - - -#define DITHMODE_R_POS_MASK (0x3 << 5) -#define DITHMODE_R_POS_SHIFT (5) -#define DITHMODE_R_POS_8BIT (0x0 << 5) -#define DITHMODE_R_POS_6BIT (0x1 << 5) -#define DITHMODE_R_POS_5BIT (0x2 << 5) - -#define DITHMODE_G_POS_MASK (0x3 << 3) -#define DITHMODE_G_POS_SHIFT (3) -#define DITHMODE_G_POS_8BIT (0x0 << 3) -#define DITHMODE_G_POS_6BIT (0x1 << 3) -#define DITHMODE_G_POS_5BIT (0x2 << 3) - -#define DITHMODE_B_POS_MASK (0x3 << 1) -#define DITHMODE_B_POS_SHIFT (1) -#define DITHMODE_B_POS_8BIT (0x0 << 1) -#define DITHMODE_B_POS_6BIT (0x1 << 1) -#define DITHMODE_B_POS_5BIT (0x2 << 1) +#ifndef __ASM_ARCH_MACH_REGS_FB_H +#define __ASM_ARCH_MACH_REGS_FB_H __FILE__ -#define DITHMODE_DITH_EN (1 << 0) - -#define WPALCON (0x1A0) - -#define WPALCON_W4PAL_16BPP_A555 (1 << 8) -#define WPALCON_W3PAL_16BPP_A555 (1 << 7) -#define WPALCON_W2PAL_16BPP_A555 (1 << 6) +#include /* Palette registers */ - #define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) #define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) #define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) #define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) #define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) -/* system specific implementation code for palette sizes, and other - * information that changes depending on which architecture is being - * compiled. -*/ - -/* return true if window _win has OSD register D */ -#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) - -static inline unsigned int s3c_fb_win_pal_size(unsigned int win) -{ - if (win < 2) - return 256; - if (win < 4) - return 16; - if (win == 4) - return 4; - - BUG(); /* shouldn't get here */ -} - -static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) -{ - /* all windows can do 1/2 bpp */ - - if ((bpp == 25 || bpp == 19) && win == 0) - return 0; /* win 0 does not have 19 or 25bpp modes */ - - if (bpp == 4 && win == 4) - return 0; - - if (bpp == 8 && (win >= 3)) - return 0; /* win 3/4 cannot do 8bpp in any mode */ - - return 1; -} - static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) { switch (window) { @@ -203,57 +38,4 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) BUG(); } -static inline int s3c_fb_pal_is16(unsigned int window) -{ - return window > 1; -} - -struct s3c_fb_palette { - struct fb_bitfield r; - struct fb_bitfield g; - struct fb_bitfield b; - struct fb_bitfield a; -}; - -static inline void s3c_fb_init_palette(unsigned int window, - struct s3c_fb_palette *palette) -{ - if (window < 2) { - /* Windows 0/1 are 8/8/8 or A/8/8/8 */ - palette->r.offset = 16; - palette->r.length = 8; - palette->g.offset = 8; - palette->g.length = 8; - palette->b.offset = 0; - palette->b.length = 8; - } else { - /* currently we assume RGB 5/6/5 */ - palette->r.offset = 11; - palette->r.length = 5; - palette->g.offset = 5; - palette->g.length = 6; - palette->b.offset = 0; - palette->b.length = 5; - } -} - -/* Notes on per-window bpp settings - * - * Value Win0 Win1 Win2 Win3 Win 4 - * 0000 1(P) 1(P) 1(P) 1(P) 1(P) - * 0001 2(P) 2(P) 2(P) 2(P) 2(P) - * 0010 4(P) 4(P) 4(P) 4(P) -none- - * 0011 8(P) 8(P) -none- -none- -none- - * 0100 -none- 8(A232) 8(A232) -none- -none- - * 0101 16(565) 16(565) 16(565) 16(565) 16(565) - * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) - * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) - * 1000 18(666) 18(666) 18(666) 18(666) 18(666) - * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) - * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) - * 1011 24(888) 24(888) 24(888) 24(888) 24(888) - * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) - * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) - * 1110 -none- -none- -none- -none- -none- - * 1111 -none- -none- -none- -none- -none- -*/ +#endif /* __ASM_ARCH_MACH_REGS_FB_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h new file mode 100644 index 00000000000..a60ed0d06c9 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h @@ -0,0 +1,235 @@ +/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C64XX - new-style framebuffer register definitions + * + * This is the register set for the new style framebuffer interface + * found from the S3C2443 onwards and specifically the S3C64XX series + * S3C6400 and S3C6410. + * + * The file contains the cpu specific items which change between whichever + * architecture is selected. See for the core definitions + * that are the same. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* include the core definitions here, in case we really do need to + * override them at a later date. +*/ + +#include + +#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ +#define VIDCON1_FSTATUS_EVEN (1 << 15) + +/* Video timing controls */ +#define VIDTCON0 (0x10) +#define VIDTCON1 (0x14) +#define VIDTCON2 (0x18) + +/* Window position controls */ + +#define WINCON(_win) (0x20 + ((_win) * 4)) + +/* OSD1 and OSD4 do not have register D */ + +#define VIDOSD_A(_win) (0x40 + ((_win) * 16)) +#define VIDOSD_B(_win) (0x44 + ((_win) * 16)) +#define VIDOSD_C(_win) (0x48 + ((_win) * 16)) +#define VIDOSD_D(_win) (0x4C + ((_win) * 16)) + + +#define VIDINTCON0 (0x130) + +#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) + +/* WINCONx */ + +#define WINCONx_CSCWIDTH_MASK (0x3 << 26) +#define WINCONx_CSCWIDTH_SHIFT (26) +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) + +#define WINCONx_ENLOCAL (1 << 22) +#define WINCONx_BUFSTATUS (1 << 21) +#define WINCONx_BUFSEL (1 << 20) +#define WINCONx_BUFAUTOEN (1 << 19) +#define WINCONx_YCbCr (1 << 13) + +#define WINCON1_LOCALSEL_CAMIF (1 << 23) + +#define WINCON2_LOCALSEL_CAMIF (1 << 23) +#define WINCON2_BLD_PIX (1 << 6) + +#define WINCON2_ALPHA_SEL (1 << 1) +#define WINCON2_BPPMODE_MASK (0xf << 2) +#define WINCON2_BPPMODE_SHIFT (2) +#define WINCON2_BPPMODE_1BPP (0x0 << 2) +#define WINCON2_BPPMODE_2BPP (0x1 << 2) +#define WINCON2_BPPMODE_4BPP (0x2 << 2) +#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) +#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) +#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) +#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) +#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) +#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) +#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) +#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) + +#define WINCON3_BLD_PIX (1 << 6) + +#define WINCON3_ALPHA_SEL (1 << 1) +#define WINCON3_BPPMODE_MASK (0xf << 2) +#define WINCON3_BPPMODE_SHIFT (2) +#define WINCON3_BPPMODE_1BPP (0x0 << 2) +#define WINCON3_BPPMODE_2BPP (0x1 << 2) +#define WINCON3_BPPMODE_4BPP (0x2 << 2) +#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) +#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) +#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) +#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) +#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) +#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) +#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) +#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) +#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) + +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) + +#define DITHMODE (0x170) +#define WINxMAP(_win) (0x180 + ((_win) * 4)) + + +#define DITHMODE_R_POS_MASK (0x3 << 5) +#define DITHMODE_R_POS_SHIFT (5) +#define DITHMODE_R_POS_8BIT (0x0 << 5) +#define DITHMODE_R_POS_6BIT (0x1 << 5) +#define DITHMODE_R_POS_5BIT (0x2 << 5) + +#define DITHMODE_G_POS_MASK (0x3 << 3) +#define DITHMODE_G_POS_SHIFT (3) +#define DITHMODE_G_POS_8BIT (0x0 << 3) +#define DITHMODE_G_POS_6BIT (0x1 << 3) +#define DITHMODE_G_POS_5BIT (0x2 << 3) + +#define DITHMODE_B_POS_MASK (0x3 << 1) +#define DITHMODE_B_POS_SHIFT (1) +#define DITHMODE_B_POS_8BIT (0x0 << 1) +#define DITHMODE_B_POS_6BIT (0x1 << 1) +#define DITHMODE_B_POS_5BIT (0x2 << 1) + +#define DITHMODE_DITH_EN (1 << 0) + +#define WPALCON (0x1A0) + +/* Palette control */ +/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), + * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ +#define WPALCON_W4PAL_16BPP_A555 (1 << 8) +#define WPALCON_W3PAL_16BPP_A555 (1 << 7) +#define WPALCON_W2PAL_16BPP_A555 (1 << 6) + + +/* system specific implementation code for palette sizes, and other + * information that changes depending on which architecture is being + * compiled. +*/ + +/* return true if window _win has OSD register D */ +#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) + +static inline unsigned int s3c_fb_win_pal_size(unsigned int win) +{ + if (win < 2) + return 256; + if (win < 4) + return 16; + if (win == 4) + return 4; + + BUG(); /* shouldn't get here */ +} + +static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) +{ + /* all windows can do 1/2 bpp */ + + if ((bpp == 25 || bpp == 19) && win == 0) + return 0; /* win 0 does not have 19 or 25bpp modes */ + + if (bpp == 4 && win == 4) + return 0; + + if (bpp == 8 && (win >= 3)) + return 0; /* win 3/4 cannot do 8bpp in any mode */ + + return 1; +} + +static inline int s3c_fb_pal_is16(unsigned int window) +{ + return window > 1; +} + +struct s3c_fb_palette { + struct fb_bitfield r; + struct fb_bitfield g; + struct fb_bitfield b; + struct fb_bitfield a; +}; + +static inline void s3c_fb_init_palette(unsigned int window, + struct s3c_fb_palette *palette) +{ + if (window < 2) { + /* Windows 0/1 are 8/8/8 or A/8/8/8 */ + palette->r.offset = 16; + palette->r.length = 8; + palette->g.offset = 8; + palette->g.length = 8; + palette->b.offset = 0; + palette->b.length = 8; + } else { + /* currently we assume RGB 5/6/5 */ + palette->r.offset = 11; + palette->r.length = 5; + palette->g.offset = 5; + palette->g.length = 6; + palette->b.offset = 0; + palette->b.length = 5; + } +} + +/* Notes on per-window bpp settings + * + * Value Win0 Win1 Win2 Win3 Win 4 + * 0000 1(P) 1(P) 1(P) 1(P) 1(P) + * 0001 2(P) 2(P) 2(P) 2(P) 2(P) + * 0010 4(P) 4(P) 4(P) 4(P) -none- + * 0011 8(P) 8(P) -none- -none- -none- + * 0100 -none- 8(A232) 8(A232) -none- -none- + * 0101 16(565) 16(565) 16(565) 16(565) 16(565) + * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) + * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) + * 1000 18(666) 18(666) 18(666) 18(666) 18(666) + * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) + * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) + * 1011 24(888) 24(888) 24(888) 24(888) 24(888) + * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) + * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) + * 1110 -none- -none- -none- -none- -none- + * 1111 -none- -none- -none- -none- -none- +*/ -- cgit v1.2.3-70-g09d2 From edd6e3f89d7fe245149669400bd213140c16d6e4 Mon Sep 17 00:00:00 2001 From: Pawel Osciak Date: Tue, 17 Nov 2009 08:41:19 +0100 Subject: ARM: S5PC1xx: add platform helpers for s3c-fb device Samsung S5PC100 has LCD-controller compatible with the one known from previous SoCs series. Add required platform setup and support code that it can be used with s3c-fb driver. Signed-off-by: Pawel Osciak Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/include/mach/irqs.h | 5 + arch/arm/mach-s5pc100/include/mach/regs-fb.h | 139 +++++++++++++++++++++++++++ arch/arm/plat-s3c/include/plat/fb.h | 7 ++ arch/arm/plat-s5pc1xx/Kconfig | 5 + arch/arm/plat-s5pc1xx/Makefile | 1 + arch/arm/plat-s5pc1xx/setup-fb-24bpp.c | 49 ++++++++++ 6 files changed, 206 insertions(+) create mode 100644 arch/arm/mach-s5pc100/include/mach/regs-fb.h create mode 100644 arch/arm/plat-s5pc1xx/setup-fb-24bpp.c (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 622720dba28..b53fa48a52c 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h @@ -11,4 +11,9 @@ #include +/* LCD */ +#define IRQ_LCD_FIFO IRQ_LCD0 +#define IRQ_LCD_VSYNC IRQ_LCD1 +#define IRQ_LCD_SYSTEM IRQ_LCD2 + #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h new file mode 100644 index 00000000000..1732cd28c76 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h @@ -0,0 +1,139 @@ +/* arch/arm/mach-s5pc100/include/mach/regs-fb.h + * + * Copyright 2009 Samsung Electronics Co. + * Pawel Osciak + * + * Framebuffer register definitions for Samsung S5PC100. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_FB_H +#define __ASM_ARCH_REGS_FB_H __FILE__ + +#include + +/* VP1 interface timing control */ +#define VP1CON0 (0x118) +#define VP1_RATECON_EN (1 << 31) +#define VP1_CLKRATE_MASK (0xff) + +#define VP1CON1 (0x11c) +#define VP1_VTREGCON_EN (1 << 31) +#define VP1_VBPD_MASK (0xfff) +#define VP1_VBPD_SHIFT (16) + + +#define WPALCON_H (0x19c) +#define WPALCON_L (0x1a0) + +/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but + * different for WPAL2-4 + */ +/* In WPALCON_L (aka WPALCON) */ +#define WPALCON_W1PAL_32BPP_A888 (0x7 << 3) +#define WPALCON_W0PAL_32BPP_A888 (0x7 << 0) + +/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H, + * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]). + */ +#define WPALCON_L_WxPAL_L_MASK (0x1) +#define WPALCON_L_W2PAL_L_SHIFT (6) +#define WPALCON_L_W3PAL_L_SHIFT (7) +#define WPALCON_L_W4PAL_L_SHIFT (8) + +#define WPALCON_L_WxPAL_H_MASK (0x3) +#define WPALCON_H_W2PAL_H_SHIFT (9) +#define WPALCON_H_W3PAL_H_SHIFT (13) +#define WPALCON_H_W4PAL_H_SHIFT (17) + +/* Per-window alpha value registers */ +/* For window 0 8-bit alpha values are in VIDW0ALPHAx, + * for windows 1-4 alpha values consist of two parts, the 4 low bits are + * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC, + * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0]) + */ +#define VIDWxALPHA0(_win) (0x200 + (_win * 8)) +#define VIDWxALPHA1(_win) (0x204 + (_win * 8)) + +/* Only for window 0 in VIDW0ALPHAx. */ +#define VIDW0ALPHAx_R(_x) ((_x) << 16) +#define VIDW0ALPHAx_R_MASK (0xff << 16) +#define VIDW0ALPHAx_R_SHIFT (16) +#define VIDW0ALPHAx_G(_x) ((_x) << 8) +#define VIDW0ALPHAx_G_MASK (0xff << 8) +#define VIDW0ALPHAx_G_SHIFT (8) +#define VIDW0ALPHAx_B(_x) ((_x) << 0) +#define VIDW0ALPHAx_B_MASK (0xff << 0) +#define VIDW0ALPHAx_B_SHIFT (0) + +/* Low 4 bits of alpha0-1 for windows 1-4 */ +#define VIDW14ALPHAx_R_L(_x) ((_x) << 16) +#define VIDW14ALPHAx_R_L_MASK (0xf << 16) +#define VIDW14ALPHAx_R_L_SHIFT (16) +#define VIDW14ALPHAx_G_L(_x) ((_x) << 8) +#define VIDW14ALPHAx_G_L_MASK (0xf << 8) +#define VIDW14ALPHAx_G_L_SHIFT (8) +#define VIDW14ALPHAx_B_L(_x) ((_x) << 0) +#define VIDW14ALPHAx_B_L_MASK (0xf << 0) +#define VIDW14ALPHAx_B_L_SHIFT (0) + + +/* Per-window blending equation control registers */ +#define BLENDEQx(_win) (0x244 + ((_win) * 4)) +#define BLENDEQ1 (0x244) +#define BLENDEQ2 (0x248) +#define BLENDEQ3 (0x24c) +#define BLENDEQ4 (0x250) + +#define BLENDEQx_Q_FUNC(_x) ((_x) << 18) +#define BLENDEQx_Q_FUNC_MASK (0xf << 18) +#define BLENDEQx_P_FUNC(_x) ((_x) << 12) +#define BLENDEQx_P_FUNC_MASK (0xf << 12) +#define BLENDEQx_B_FUNC(_x) ((_x) << 6) +#define BLENDEQx_B_FUNC_MASK (0xf << 6) +#define BLENDEQx_A_FUNC(_x) ((_x) << 0) +#define BLENDEQx_A_FUNC_MASK (0xf << 0) + +#define BLENDCON (0x260) +#define BLENDCON_8BIT_ALPHA (1 << 0) + +/* Per-window palette base addresses (start of palette memory). + * Each window palette area consists of 256 32-bit entries. + * START is the first address (entry 0th), END is the address of 255th entry. + */ +#define WIN0_PAL_BASE (0x2400) +#define WIN0_PAL_END (0x27fc) +#define WIN1_PAL_BASE (0x2800) +#define WIN1_PAL_END (0x2bfc) +#define WIN2_PAL_BASE (0x2c00) +#define WIN2_PAL_END (0x2ffc) +#define WIN3_PAL_BASE (0x3000) +#define WIN3_PAL_END (0x33fc) +#define WIN4_PAL_BASE (0x3400) +#define WIN4_PAL_END (0x37fc) + +#define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4)) +#define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4)) +#define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4)) +#define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4)) +#define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4)) + +static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) +{ + switch (window) { + case 0: return WIN0_PAL(reg); + case 1: return WIN1_PAL(reg); + case 2: return WIN2_PAL(reg); + case 3: return WIN3_PAL(reg); + case 4: return WIN4_PAL(reg); + } + + BUG(); +} + + +#endif /* __ASM_ARCH_REGS_FB_H */ + diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h index 214ff561b0d..f8db87930f8 100644 --- a/arch/arm/plat-s3c/include/plat/fb.h +++ b/arch/arm/plat-s3c/include/plat/fb.h @@ -70,4 +70,11 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); */ extern void s3c64xx_fb_gpio_setup_24bpp(void); +/** + * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD + * + * Initialise the GPIO for an 24bpp LCD display on the RGB interface. + */ +extern void s5pc100_fb_gpio_setup_24bpp(void); + #endif /* __PLAT_S3C_FB_H */ diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index 86edd27c7f2..6ac48a6fba7 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -37,6 +37,11 @@ config CPU_S5PC100_CLOCK # platform specific device setup +config S5PC1XX_SETUP_FB_24BPP + bool + help + Common setup code for S5PC1XX with an 24bpp RGB display helper. + config S5PC100_SETUP_I2C0 bool default y diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index e860813cb8d..3d2ac7150b1 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile @@ -25,5 +25,6 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o # Device setup obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o +obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c new file mode 100644 index 00000000000..1a63768a9a2 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c @@ -0,0 +1,49 @@ +/* + * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c + * + * Copyright 2009 Samsung Electronics + * + * Base S5PC1XX setup information for 24bpp LCD framebuffer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DISR_OFFSET 0x7008 + +void s5pc100_fb_gpio_setup_24bpp(void) +{ + unsigned int gpio = 0; + + for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } + + for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) { + s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); + s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); + } +} -- cgit v1.2.3-70-g09d2 From 079b03241765f0a31c4bfdefd277452399dbafc9 Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Tue, 17 Nov 2009 08:41:20 +0100 Subject: SMDKC100: enable S3C FrameBuffer Add required machine definitions for s3c-fb device. A 800x480 lcd device (simmilar to the one known from SMDK6410 boards) has been defined. The lcd controller is attached to GPIO lines and can be enabled/disabled with platform-lcd driver. Signed-off-by: Kyungmin Park Signed-off-by: Marek Szyprowski Signed-off-by: Ben Dooks --- arch/arm/mach-s5pc100/Kconfig | 2 ++ arch/arm/mach-s5pc100/mach-smdkc100.c | 67 +++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index b1a4ba50441..5e6b9a32bd9 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig @@ -17,6 +17,8 @@ config CPU_S5PC100 config MACH_SMDKC100 bool "SMDKC100" select CPU_S5PC100 + select S3C_DEV_FB select S5PC1XX_SETUP_I2C1 + select S5PC1XX_SETUP_FB_24BPP help Machine support for the Samsung SMDKC100 diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index daf6a2bc6b6..e8f45535f03 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c @@ -27,16 +27,21 @@ #include #include +#include +#include