From 5816898b9592b877209e91c493db946ab275d825 Mon Sep 17 00:00:00 2001 From: Marc Dietrich Date: Sat, 21 Dec 2013 21:38:13 +0100 Subject: ARM: tegra: paz00: Add LVDS support to device tree Add backlight and panel nodes for the PAZ00 TFT LCD panel. Signed-off-by: Marc Dietrich Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-paz00.dts | 46 ++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index c7cd8e6802d..9a39a8001f7 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -257,7 +265,11 @@ status = "okay"; }; - i2c@7000c000 { + pwm: pwm@7000a000 { + status = "okay"; + }; + + lvds_ddc: i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -475,6 +487,18 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <10>; + + backlight-boot-off; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -509,6 +533,16 @@ }; }; + panel: panel { + compatible = "samsung,ltn101nt05", "simple-panel"; + + ddc-i2c-bus = <&lvds_ddc>; + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(M, 6) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -522,6 +556,16 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + vdd_pnl_reg: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+3VS,vdd_pnl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; sound { -- cgit v1.2.3-70-g09d2 From da45d738c5c2bb9f3aa58e39818af9104dd7b848 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 6 Jan 2014 16:20:42 +0100 Subject: ARM: tegra: Properly sort clocks property Other files and nodes list the resets property after the clocks property so do the same here for consistency. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index ed8e7700b46..18d52a7704c 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -144,9 +144,9 @@ compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; - clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; gr3d@54180000 { -- cgit v1.2.3-70-g09d2 From 76af3467a7189d84a6ce2bb2ee6d565f543b5dbc Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 6 Jan 2014 12:15:49 -0700 Subject: ARM: tegra: document which Dalmore revisions are supported There are a number of revisions of the Dalmore board, each with a variety of incompatible SW-visible HW changes. The Dalmore DT file in the kernel only supports HW revision A04. Document this in the DT file. Reported-by: Paul Walmsley Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 73aecfb57cc..8de54377788 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -1,3 +1,8 @@ +/* + * This dts file supports Dalmore A04. + * Other board revisions are not supported + */ + /dts-v1/; #include -- cgit v1.2.3-70-g09d2 From 7be75df218eb012e4f5f4385cb49df3f89662bc7 Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Thu, 9 Jan 2014 16:31:48 +0530 Subject: ARM: tegra: add system-power-controller property for PMIC node Add system-power-controller property to system PMIC, ams AS3722, node to enable power off functionality through PMIC. Signed-off-by: Laxman Dewangan Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c6dcef513e5..1ad3f334fb1 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -616,6 +616,8 @@ reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + ams,system-power-controller; + #interrupt-cells = <2>; interrupt-controller; -- cgit v1.2.3-70-g09d2 From 9615d65631bfed84dcbdf8b1ef3b6410f512e974 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 7 Jan 2014 16:16:32 -0700 Subject: ARM: tegra: enable LCD panel on Seaboard Seaboard uses a CLAA101WA01A LCD panel. Enable the relevant display controller, backlight, and regulators. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra20-seaboard.dts | 55 +++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index a11b6e7b475..a1d4bf9895d 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -312,6 +320,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -369,7 +381,7 @@ #size-cells = <0>; }; - i2c@1 { + lvds_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -762,6 +774,17 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -795,6 +818,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -839,6 +872,26 @@ regulator-always-on; regulator-boot-on; }; + + vdd_pnl_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_bl_reg: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; sound { -- cgit v1.2.3-70-g09d2 From 1771a2542043109f9382b870db9a35f578c42096 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 7 Jan 2014 16:33:31 -0700 Subject: ARM: tegra: enable LCD panel on Ventana Ventana uses a CLAA101WA01A LCD panel. Enable the relevant display controller, backlight, and regulators. Signed-off-by: Stephen Warren Reviewed-by: Thierry Reding --- arch/arm/boot/dts/tegra20-ventana.dts | 39 ++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 571d12e6ac2..ca8484cccdd 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -17,6 +17,14 @@ }; host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + nvidia,panel = <&panel>; + }; + }; + hdmi@54280000 { status = "okay"; @@ -309,6 +317,10 @@ status = "okay"; }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { status = "okay"; clock-frequency = <400000>; @@ -359,7 +371,7 @@ #size-cells = <0>; }; - i2c@1 { + lvds_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -557,6 +569,17 @@ non-removable; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_bl_reg>; + pwms = <&pwm 2 5000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -581,6 +604,16 @@ }; }; + panel: panel { + compatible = "chunghwa,claa101wa01a", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + ddc-i2c-bus = <&lvds_ddc>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -614,7 +647,7 @@ enable-active-high; }; - regulator@3 { + vdd_pnl_reg: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "vdd_pnl"; @@ -624,7 +657,7 @@ enable-active-high; }; - regulator@4 { + vdd_bl_reg: regulator@4 { compatible = "regulator-fixed"; reg = <4>; regulator-name = "vdd_bl"; -- cgit v1.2.3-70-g09d2 From 40431d16ff1143844023c9f7d8d4b4c70200e597 Mon Sep 17 00:00:00 2001 From: Bryan Wu Date: Fri, 7 Feb 2014 15:54:58 -0800 Subject: ARM: tegra: enable PCA9546 on Cardhu Cardhu has a PCA9546 for I2C bus extension, which connects to 3 cameras. It's required for Tegra V4L2 soc camera driver and camera sensor drivers. Signed-off-by: Bryan Wu Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra30-cardhu.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 9104224124e..004002c8c8a 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -187,6 +187,13 @@ interrupt-parent = <&gpio>; interrupts = ; }; + + i2cmux@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; }; i2c@7000c700 { -- cgit v1.2.3-70-g09d2 From 11e5b4f9e33b0da8a5bf44c370688e37f5a4a72e Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 18 Feb 2014 15:03:21 -0700 Subject: ARM: tegra: add SPI flash to Venice2 DT Venice2 contains an SPI Flash chip, which contains the bootloader. Add this to the DT, so the kernel can access it. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 1ad3f334fb1..e71aeb9929b 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -914,6 +914,16 @@ }; }; + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + spi-flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + spi-max-frequency = <20000000>; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; -- cgit v1.2.3-70-g09d2 From e2b6d77ef8e6066e479fc4fcf9549f21b031f389 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 25 Feb 2014 16:31:40 +0100 Subject: ARM: tegra: Use "disabled" for status property To disable a device tree node, the status property should be set to "disabled", not "disable". Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++---- arch/arm/boot/dts/tegra124.dtsi | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 389e987ec28..275cb184696 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -600,7 +600,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; resets = <&tegra_car 14>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000200 { @@ -610,7 +610,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; resets = <&tegra_car 9>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000400 { @@ -620,7 +620,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; resets = <&tegra_car 69>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@78000600 { @@ -630,7 +630,7 @@ clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; resets = <&tegra_car 15>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; usb@7d000000 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index ec0698a8354..30a7377d560 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -388,7 +388,7 @@ clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; resets = <&tegra_car 14>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@700b0200 { @@ -398,7 +398,7 @@ clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; resets = <&tegra_car 9>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@700b0400 { @@ -408,7 +408,7 @@ clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; resets = <&tegra_car 69>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; sdhci@700b0600 { @@ -418,7 +418,7 @@ clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; resets = <&tegra_car 15>; reset-names = "sdhci"; - status = "disable"; + status = "disabled"; }; ahub@70300000 { -- cgit v1.2.3-70-g09d2 From fa15ffaaea4abe1115d075946d87cd75360e59a2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 25 Feb 2014 16:45:04 +0100 Subject: ARM: tegra: Combine VBUS enable pins into one node Both USB_VBUS_EN0 and USB_VBUS_EN1 are configured the same way, so they can be combined into a single node. While at it, don't configure them as pull-up since they already have external pull-ups. Also U-Boot doesn't configure them as pull-up either. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index e71aeb9929b..c950c76185d 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -402,19 +402,11 @@ nvidia,enable-input = ; }; usb_vbus_en0_pn4 { - nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; nvidia,function = "usb"; nvidia,enable-input = ; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,lock = ; - nvidia,open-drain = ; - }; - usb_vbus_en1_pn5 { - nvidia,pins = "usb_vbus_en1_pn5"; - nvidia,function = "usb"; - nvidia,enable-input = ; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,lock = ; nvidia,open-drain = ; -- cgit v1.2.3-70-g09d2 From af144b8d5dc260b5394cd43297bdb2bd9156a932 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:20 +0100 Subject: ARM: tegra: Overhaul Venice2 regulators Some of the regulators and the relationships to other regulators are wrong. This commit attempts to rectify this by making them more similar to what the schematics contain. This starts by adding a +VDD_MUX supply that represents the 12V input and derives the main +3.3V_SYS and +5V_SYS supplies from that. The majority of the other regulators derive from one of those three. While at it, rename the regulators to match the names in the schematics to make them easier to match up. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 171 +++++++++++++++++++-------------- 1 file changed, 98 insertions(+), 73 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index c950c76185d..cedf0641626 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -644,19 +644,19 @@ }; regulators { - vsup-sd2-supply = <&vdd_ac_bat_reg>; - vsup-sd3-supply = <&vdd_ac_bat_reg>; - vsup-sd4-supply = <&vdd_ac_bat_reg>; - vsup-sd5-supply = <&vdd_ac_bat_reg>; - vin-ldo0-supply = <&as3722_sd2>; - vin-ldo1-6-supply = <&vdd_ac_bat_reg>; - vin-ldo2-5-7-supply = <&as3722_sd5>; - vin-ldo3-4-supply = <&vdd_ac_bat_reg>; - vin-ldo9-10-supply = <&vdd_ac_bat_reg>; - vin-ldo11-supply = <&vdd_ac_bat_reg>; + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; sd0 { - regulator-name = "vdd-cpu"; + regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>; regulator-min-microamp = <3500000>; @@ -667,7 +667,7 @@ }; sd1 { - regulator-name = "vdd-core"; + regulator-name = "+VDD_CORE"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-min-microamp = <2500000>; @@ -677,8 +677,8 @@ ams,external-control = <1>; }; - as3722_sd2: sd2 { - regulator-name = "vddio-ddr"; + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -686,7 +686,7 @@ }; sd3 { - regulator-name = "vddio-ddr-2phase"; + regulator-name = "+1.35V_LP0(sd3)"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -694,15 +694,13 @@ }; sd4 { - regulator-name = "avdd-pex-sata"; + regulator-name = "+1.05V_RUN"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; - regulator-boot-on; - regulator-always-on; }; - as3722_sd5: sd5 { - regulator-name = "vddio-sys"; + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -710,7 +708,7 @@ }; sd6 { - regulator-name = "vdd-gpu"; + regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>; regulator-min-microamp = <3500000>; @@ -720,7 +718,7 @@ }; ldo0 { - regulator-name = "avdd_pll"; + regulator-name = "+1.05V_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; regulator-boot-on; @@ -729,13 +727,13 @@ }; ldo1 { - regulator-name = "run-cam-1.8"; + regulator-name = "+1.8V_RUN_CAM"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo2 { - regulator-name = "gen-avdd,vddio-hsic"; + regulator-name = "+1.2V_GEN_AVDD"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-boot-on; @@ -743,7 +741,7 @@ }; ldo3 { - regulator-name = "vdd-rtc"; + regulator-name = "+1.00V_LP0_VDD_RTC"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; @@ -752,21 +750,19 @@ }; ldo4 { - regulator-name = "vdd-cam"; + regulator-name = "+3.3V_RUN_CAM"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-boot-on; - regulator-always-on; }; ldo5 { - regulator-name = "vdd-cam-front"; + regulator-name = "+1.2V_RUN_CAM_FRONT"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; ldo6 { - regulator-name = "vddio-sdmmc3"; + regulator-name = "+VDDIO_SDMMC3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -774,25 +770,25 @@ }; ldo7 { - regulator-name = "vdd-cam-rear"; + regulator-name = "+1.05V_RUN_CAM_REAR"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; ldo9 { - regulator-name = "vdd-touch"; + regulator-name = "+2.8V_RUN_TOUCH"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; ldo10 { - regulator-name = "vdd-cam-af"; + regulator-name = "+2.8V_RUN_CAM_AF"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; ldo11 { - regulator-name = "vpp-fuse"; + regulator-name = "+1.8V_RUN_VPP_FUSE"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; @@ -975,99 +971,128 @@ #address-cells = <1>; #size-cells = <0>; - vdd_ac_bat_reg: regulator@0 { + vdd_mux: regulator@0 { compatible = "regulator-fixed"; reg = <0>; - regulator-name = "vdd_ac_bat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; regulator-always-on; + regulator-boot-on; }; - vdd_3v3_reg: regulator@1 { + vdd_5v0_sys: regulator@1 { compatible = "regulator-fixed"; reg = <1>; - regulator-name = "vdd_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; regulator-always-on; regulator-boot-on; - enable-active-high; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_mux>; }; - vdd_3v3_modem_reg: regulator@2 { + vdd_3v3_sys: regulator@2 { compatible = "regulator-fixed"; reg = <2>; - regulator-name = "vdd-modem-3v3"; + regulator-name = "+3.3V_SYS"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; }; - vdd_hdmi_5v0_reg: regulator@3 { + vdd_3v3_run: regulator@3 { compatible = "regulator-fixed"; reg = <3>; - regulator-name = "vdd-hdmi-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_3v3_sys>; }; - vdd_bl_reg: regulator@4 { + vdd_3v3_hdmi: regulator@4 { compatible = "regulator-fixed"; reg = <4>; - regulator-name = "vdd-bl"; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_3v3_run>; }; - vdd_ts_sw_5v0: regulator@5 { + vdd_led: regulator@5 { compatible = "regulator-fixed"; reg = <5>; - regulator-name = "vdd_ts_sw"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-boot-on; - gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_mux>; }; - usb1_vbus_reg: regulator@6 { + vdd_5v0_ts: regulator@6 { compatible = "regulator-fixed"; reg = <6>; - regulator-name = "usb1_vbus"; + regulator-name = "+5V_VDD_TS_SW"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; - gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; }; - usb3_vbus_reg: regulator@7 { + vdd_usb1_vbus: regulator@7 { compatible = "regulator-fixed"; reg = <7>; - regulator-name = "usb3_vbus"; + regulator-name = "+5V_USB_HS"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; enable-active-high; - gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; }; - panel_3v3_reg: regulator@8 { + vdd_usb3_vbus: regulator@8 { compatible = "regulator-fixed"; reg = <8>; - regulator-name = "panel_3v3"; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - enable-active-high; gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; }; }; -- cgit v1.2.3-70-g09d2 From 4989b439237dabe80e842b2e2c3743b847b87c2d Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:21 +0100 Subject: ARM: tegra: Hook up SDMMC3 power-supply on Venice2 The SDMMC3 interface is supplied with 1.8V by the PMICs LDO6. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index cedf0641626..b0db6348827 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -761,12 +761,10 @@ regulator-max-microvolt = <1200000>; }; - ldo6 { + vddio_sdmmc3: ldo6 { regulator-name = "+VDDIO_SDMMC3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; }; ldo7 { @@ -928,6 +926,7 @@ power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; status = "okay"; bus-width = <4>; + vmmc-supply = <&vddio_sdmmc3>; }; sdhci@700b0600 { -- cgit v1.2.3-70-g09d2 From ad6be7d1146daa90be90e924fd5fb07a22d8ffda Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:22 +0100 Subject: ARM: tegra: Add Tegra124 host1x support The version of host1x on Tegra124 is largely compatible with that on earlier Tegra generations. Some of the registers have moved around or expanded to allow for more capability, so a separate compatible string is still required. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 30a7377d560..26dfe09e841 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -9,6 +9,47 @@ compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + host1x@50000000 { + compatible = "nvidia,tegra124-host1x", "simple-bus"; + reg = <0x50000000 0x00034000>; + interrupts = , /* syncpt */ + ; /* general */ + clocks = <&tegra_car TEGRA124_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x54000000 0x54000000 0x01000000>; + + dc@54200000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54200000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP1>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; + + nvidia,head = <0>; + }; + + dc@54240000 { + compatible = "nvidia,tegra124-dc"; + reg = <0x54240000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DISP2>, + <&tegra_car TEGRA124_CLK_PLL_P>; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; + + nvidia,head = <1>; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; -- cgit v1.2.3-70-g09d2 From d72be031b3ceeae5a4761e400af1ac60ca313449 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:23 +0100 Subject: ARM: tegra: Add Tegra124 eDP support The SOR block on Tegra124 can be used standalone to drive LVDS panels or used in conjunction with the DPAUX block to support eDP. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 26dfe09e841..dd5330f01e1 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -48,6 +48,32 @@ nvidia,head = <1>; }; + + sor@54540000 { + compatible = "nvidia,tegra124-sor"; + reg = <0x54540000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, + <&tegra_car TEGRA124_CLK_PLL_DP>, + <&tegra_car TEGRA124_CLK_CLK_M>; + clock-names = "sor", "parent", "dp", "safe"; + resets = <&tegra_car 182>; + reset-names = "sor"; + status = "disabled"; + }; + + dpaux@545c0000 { + compatible = "nvidia,tegra124-dpaux"; + reg = <0x545c0000 0x00040000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DPAUX>, + <&tegra_car TEGRA124_CLK_PLL_DP>; + clock-names = "dpaux", "parent"; + resets = <&tegra_car 181>; + reset-names = "dpaux"; + status = "disabled"; + }; }; gic: interrupt-controller@50041000 { -- cgit v1.2.3-70-g09d2 From 40e231c770a4201febdf64f677862c9910e81946 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:24 +0100 Subject: ARM: tegra: Enable eDP for Venice2 Venice2 has a 12.9" (2560x1700) panel connected to the eDP output of the Tegra124. The panel has an EDID to describe the video timings but needs a few extra nodes to get the backlight to come up. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index b0db6348827..7ffef561d66 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -16,6 +16,20 @@ reg = <0x80000000 0x80000000>; }; + host1x@50000000 { + sor@54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux: dpaux@545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + pinmux: pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -940,6 +954,17 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -965,6 +990,13 @@ }; }; + panel: panel { + compatible = "lg,lp129qe", "simple-panel"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; -- cgit v1.2.3-70-g09d2 From f2d50158ebe61d72e06017e8762a0b853860e7b7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:25 +0100 Subject: ARM: tegra: Add Tegra124 USB support The USB controllers on Tegra124 are backwards-compatible with those found on Tegra30. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124.dtsi | 99 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index dd5330f01e1..b1459844ef0 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -591,6 +591,105 @@ }; }; + usb@7d000000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; + nvidia,phy = <&phy1>; + status = "disabled"; + }; + + phy1: usb-phy@7d000000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USBD>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + usb@7d004000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; + nvidia,phy = <&phy2>; + status = "disabled"; + }; + + phy2: usb-phy@7d004000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB2>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + + usb@7d008000 { + compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = ; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; + nvidia,phy = <&phy3>; + status = "disabled"; + }; + + phy3: usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3-70-g09d2 From 431b7be0a33e5505b3706c6970c3c4753bebf708 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:26 +0100 Subject: ARM: tegra: Enable USB on Venice2 USB1 and USB3 are routed to two external connectors, while USB2 is used for the integrated webcam. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 7ffef561d66..ee92d912ed2 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -763,7 +763,7 @@ ams,enable-tracking; }; - ldo4 { + vdd_run_cam: ldo4 { regulator-name = "+3.3V_RUN_CAM"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -954,6 +954,33 @@ }; }; + usb@7d000000 { + status = "okay"; + }; + + usb-phy@7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@7d004000 { + status = "okay"; + }; + + usb-phy@7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@7d008000 { + status = "okay"; + }; + + usb-phy@7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + backlight: backlight { compatible = "pwm-backlight"; -- cgit v1.2.3-70-g09d2 From 4b3566080e09dad665b3208c31136a356493fe62 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:27 +0100 Subject: ARM: tegra: Fix whitespace around '=' Equal signs should always be preceded and followed by a single space in device tree files. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index ee92d912ed2..8c36e4c4787 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -999,7 +999,7 @@ clk32k_in: clock@0 { compatible = "fixed-clock"; - reg=<0>; + reg = <0>; #clock-cells = <0>; clock-frequency = <32768>; }; -- cgit v1.2.3-70-g09d2 From fdc44f9491cda0607b9c4b2ddb95bd742418635e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 28 Feb 2014 17:40:28 +0100 Subject: ARM: tegra: Rename as3722 node to pmic Device tree node name should reflect the kind of device rather than the specific name of the device. Signed-off-by: Thierry Reding Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 8c36e4c4787..1ad68615428 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -8,7 +8,7 @@ compatible = "nvidia,venice2", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@7000d000/as3722@40"; + rtc0 = "/i2c@7000d000/pmic@40"; rtc1 = "/rtc@7000e000"; }; @@ -617,7 +617,7 @@ status = "okay"; clock-frequency = <400000>; - as3722: as3722@40 { + pmic: pmic@40 { compatible = "ams,as3722"; reg = <0x40>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; @@ -1067,7 +1067,7 @@ regulator-name = "+3.3V_RUN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_sys>; }; @@ -1132,7 +1132,7 @@ regulator-name = "+3.3V_PANEL"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_run>; }; @@ -1148,7 +1148,7 @@ * controllers so that it can be enabled on demand. */ regulator-always-on; - gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_3v3_sys>; }; -- cgit v1.2.3-70-g09d2 From e30cb2388ab68de68142120ab9fca5ae6e377682 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 3 Mar 2014 14:51:15 -0700 Subject: ARM: tegra: use 2 address cells for Tegra124 DT Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-venice2.dts | 54 ++++----- arch/arm/boot/dts/tegra124.dtsi | 215 +++++++++++++++++---------------- 2 files changed, 137 insertions(+), 132 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 1ad68615428..86536d919ed 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -8,29 +8,29 @@ compatible = "nvidia,venice2", "nvidia,tegra124"; aliases { - rtc0 = "/i2c@7000d000/pmic@40"; - rtc1 = "/rtc@7000e000"; + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; }; memory { - reg = <0x80000000 0x80000000>; + reg = <0x0 0x80000000 0x0 0x80000000>; }; - host1x@50000000 { - sor@54540000 { + host1x@0,50000000 { + sor@0,54540000 { status = "okay"; nvidia,dpaux = <&dpaux>; nvidia,panel = <&panel>; }; - dpaux: dpaux@545c0000 { + dpaux: dpaux@0,545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; }; - pinmux: pinmux@70000868 { + pinmux: pinmux@0,70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -578,15 +578,15 @@ }; }; - serial@70006000 { + serial@0,70006000 { status = "okay"; }; - pwm: pwm@7000a000 { + pwm: pwm@0,7000a000 { status = "okay"; }; - i2c@7000c000 { + i2c@0,7000c000 { status = "okay"; clock-frequency = <100000>; @@ -598,22 +598,22 @@ }; }; - i2c@7000c400 { + i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000c500 { + i2c@0,7000c500 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000c700 { + i2c@0,7000c700 { status = "okay"; clock-frequency = <100000>; }; - i2c@7000d000 { + i2c@0,7000d000 { status = "okay"; clock-frequency = <400000>; @@ -808,7 +808,7 @@ }; }; - spi@7000d400 { + spi@0,7000d400 { status = "okay"; cros-ec@0 { @@ -914,7 +914,7 @@ }; }; - spi@7000da00 { + spi@0,7000da00 { status = "okay"; spi-max-frequency = <25000000>; spi-flash@0 { @@ -924,7 +924,7 @@ }; }; - pmc@7000e400 { + pmc@0,7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <1>; nvidia,cpu-pwr-good-time = <500>; @@ -935,7 +935,7 @@ nvidia,sys-clock-req-active-high; }; - sdhci@700b0400 { + sdhci@0,700b0400 { cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; status = "okay"; @@ -943,40 +943,40 @@ vmmc-supply = <&vddio_sdmmc3>; }; - sdhci@700b0600 { + sdhci@0,700b0600 { status = "okay"; bus-width = <8>; }; - ahub@70300000 { - i2s@70301100 { + ahub@0,70300000 { + i2s@0,70301100 { status = "okay"; }; }; - usb@7d000000 { + usb@0,7d000000 { status = "okay"; }; - usb-phy@7d000000 { + usb-phy@0,7d000000 { status = "okay"; vbus-supply = <&vdd_usb1_vbus>; }; - usb@7d004000 { + usb@0,7d004000 { status = "okay"; }; - usb-phy@7d004000 { + usb-phy@0,7d004000 { status = "okay"; vbus-supply = <&vdd_run_cam>; }; - usb@7d008000 { + usb@0,7d008000 { status = "okay"; }; - usb-phy@7d008000 { + usb-phy@0,7d008000 { status = "okay"; vbus-supply = <&vdd_usb3_vbus>; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b1459844ef0..cf45a1a3948 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -8,24 +8,26 @@ / { compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; - host1x@50000000 { + host1x@0,50000000 { compatible = "nvidia,tegra124-host1x", "simple-bus"; - reg = <0x50000000 0x00034000>; + reg = <0x0 0x50000000 0x0 0x00034000>; interrupts = , /* syncpt */ ; /* general */ clocks = <&tegra_car TEGRA124_CLK_HOST1X>; resets = <&tegra_car 28>; reset-names = "host1x"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; - ranges = <0x54000000 0x54000000 0x01000000>; + ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; - dc@54200000 { + dc@0,54200000 { compatible = "nvidia,tegra124-dc"; - reg = <0x54200000 0x00040000>; + reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_DISP1>, <&tegra_car TEGRA124_CLK_PLL_P>; @@ -36,9 +38,9 @@ nvidia,head = <0>; }; - dc@54240000 { + dc@0,54240000 { compatible = "nvidia,tegra124-dc"; - reg = <0x54240000 0x00040000>; + reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_DISP2>, <&tegra_car TEGRA124_CLK_PLL_P>; @@ -49,9 +51,9 @@ nvidia,head = <1>; }; - sor@54540000 { + sor@0,54540000 { compatible = "nvidia,tegra124-sor"; - reg = <0x54540000 0x00040000>; + reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SOR0>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, @@ -63,9 +65,9 @@ status = "disabled"; }; - dpaux@545c0000 { + dpaux@0,545c0000 { compatible = "nvidia,tegra124-dpaux"; - reg = <0x545c0000 0x00040000>; + reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_DPAUX>, <&tegra_car TEGRA124_CLK_PLL_DP>; @@ -76,21 +78,21 @@ }; }; - gic: interrupt-controller@50041000 { + gic: interrupt-controller@0,50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x50041000 0x1000>, - <0x50042000 0x1000>, - <0x50044000 0x2000>, - <0x50046000 0x2000>; + reg = <0x0 0x50041000 0x0 0x1000>, + <0x0 0x50042000 0x0 0x1000>, + <0x0 0x50044000 0x0 0x2000>, + <0x0 0x50046000 0x0 0x2000>; interrupts = ; }; - timer@60005000 { + timer@0,60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; - reg = <0x60005000 0x400>; + reg = <0x0 0x60005000 0x0 0x400>; interrupts = , , , @@ -100,16 +102,16 @@ clocks = <&tegra_car TEGRA124_CLK_TIMER>; }; - tegra_car: clock@60006000 { + tegra_car: clock@0,60006000 { compatible = "nvidia,tegra124-car"; - reg = <0x60006000 0x1000>; + reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - gpio: gpio@6000d000 { + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; - reg = <0x6000d000 0x1000>; + reg = <0x0 0x6000d000 0x0 0x1000>; interrupts = , , , @@ -124,9 +126,9 @@ interrupt-controller; }; - apbdma: dma@60020000 { + apbdma: dma@0,60020000 { compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; - reg = <0x60020000 0x1400>; + reg = <0x0 0x60020000 0x0 0x1400>; interrupts = , , , @@ -165,10 +167,10 @@ #dma-cells = <1>; }; - pinmux: pinmux@70000868 { + pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; - reg = <0x70000868 0x164>, /* Pad control registers */ - <0x70003000 0x434>; /* Mux registers */ + reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ + <0x0 0x70003000 0x0 0x434>; /* Mux registers */ }; /* @@ -179,9 +181,9 @@ * the APB DMA based serial driver, the comptible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ - serial@70006000 { + serial@0,70006000 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006000 0x40>; + reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTA>; @@ -192,9 +194,9 @@ status = "disabled"; }; - serial@70006040 { + serial@0,70006040 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006040 0x40>; + reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTB>; @@ -205,9 +207,9 @@ status = "disabled"; }; - serial@70006200 { + serial@0,70006200 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006200 0x40>; + reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTC>; @@ -218,9 +220,9 @@ status = "disabled"; }; - serial@70006300 { + serial@0,70006300 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006300 0x40>; + reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTD>; @@ -231,9 +233,9 @@ status = "disabled"; }; - serial@70006400 { + serial@0,70006400 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; - reg = <0x70006400 0x40>; + reg = <0x0 0x70006400 0x0 0x40>; reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTE>; @@ -244,9 +246,9 @@ status = "disabled"; }; - pwm@7000a000 { + pwm@0,7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; - reg = <0x7000a000 0x100>; + reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA124_CLK_PWM>; resets = <&tegra_car 17>; @@ -254,9 +256,9 @@ status = "disabled"; }; - i2c@7000c000 { + i2c@0,7000c000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c000 0x100>; + reg = <0x0 0x7000c000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -269,9 +271,9 @@ status = "disabled"; }; - i2c@7000c400 { + i2c@0,7000c400 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c400 0x100>; + reg = <0x0 0x7000c400 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -284,9 +286,9 @@ status = "disabled"; }; - i2c@7000c500 { + i2c@0,7000c500 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c500 0x100>; + reg = <0x0 0x7000c500 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -299,9 +301,9 @@ status = "disabled"; }; - i2c@7000c700 { + i2c@0,7000c700 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000c700 0x100>; + reg = <0x0 0x7000c700 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -314,9 +316,9 @@ status = "disabled"; }; - i2c@7000d000 { + i2c@0,7000d000 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d000 0x100>; + reg = <0x0 0x7000d000 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -329,9 +331,9 @@ status = "disabled"; }; - i2c@7000d100 { + i2c@0,7000d100 { compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; - reg = <0x7000d100 0x100>; + reg = <0x0 0x7000d100 0x0 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -344,9 +346,9 @@ status = "disabled"; }; - spi@7000d400 { + spi@0,7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d400 0x200>; + reg = <0x0 0x7000d400 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -359,9 +361,9 @@ status = "disabled"; }; - spi@7000d600 { + spi@0,7000d600 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d600 0x200>; + reg = <0x0 0x7000d600 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -374,9 +376,9 @@ status = "disabled"; }; - spi@7000d800 { + spi@0,7000d800 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000d800 0x200>; + reg = <0x0 0x7000d800 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -389,9 +391,9 @@ status = "disabled"; }; - spi@7000da00 { + spi@0,7000da00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000da00 0x200>; + reg = <0x0 0x7000da00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -404,9 +406,9 @@ status = "disabled"; }; - spi@7000dc00 { + spi@0,7000dc00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000dc00 0x200>; + reg = <0x0 0x7000dc00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -419,9 +421,9 @@ status = "disabled"; }; - spi@7000de00 { + spi@0,7000de00 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; - reg = <0x7000de00 0x200>; + reg = <0x0 0x7000de00 0x0 0x200>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -434,23 +436,23 @@ status = "disabled"; }; - rtc@7000e000 { + rtc@0,7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; + reg = <0x0 0x7000e000 0x0 0x100>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@7000e400 { + pmc@0,7000e400 { compatible = "nvidia,tegra124-pmc"; - reg = <0x7000e400 0x400>; + reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; }; - sdhci@700b0000 { + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0000 0x200>; + reg = <0x0 0x700b0000 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; resets = <&tegra_car 14>; @@ -458,9 +460,9 @@ status = "disabled"; }; - sdhci@700b0200 { + sdhci@0,700b0200 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0200 0x200>; + reg = <0x0 0x700b0200 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; resets = <&tegra_car 9>; @@ -468,9 +470,9 @@ status = "disabled"; }; - sdhci@700b0400 { + sdhci@0,700b0400 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0400 0x200>; + reg = <0x0 0x700b0400 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; resets = <&tegra_car 69>; @@ -478,9 +480,9 @@ status = "disabled"; }; - sdhci@700b0600 { + sdhci@0,700b0600 { compatible = "nvidia,tegra124-sdhci"; - reg = <0x700b0600 0x200>; + reg = <0x0 0x700b0600 0x0 0x200>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; resets = <&tegra_car 15>; @@ -488,11 +490,11 @@ status = "disabled"; }; - ahub@70300000 { + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; - reg = <0x70300000 0x200>, - <0x70300800 0x800>, - <0x70300200 0x600>; + reg = <0x0 0x70300000 0x0 0x200>, + <0x0 0x70300800 0x0 0x800>, + <0x0 0x70300200 0x0 0x600>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, <&tegra_car TEGRA124_CLK_APBIF>; @@ -537,12 +539,12 @@ "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; ranges; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; - tegra_i2s0: i2s@70301000 { + tegra_i2s0: i2s@0,70301000 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301000 0x100>; + reg = <0x0 0x70301000 0x0 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA124_CLK_I2S0>; resets = <&tegra_car 30>; @@ -550,9 +552,9 @@ status = "disabled"; }; - tegra_i2s1: i2s@70301100 { + tegra_i2s1: i2s@0,70301100 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301100 0x100>; + reg = <0x0 0x70301100 0x0 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA124_CLK_I2S1>; resets = <&tegra_car 11>; @@ -560,9 +562,9 @@ status = "disabled"; }; - tegra_i2s2: i2s@70301200 { + tegra_i2s2: i2s@0,70301200 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301200 0x100>; + reg = <0x0 0x70301200 0x0 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA124_CLK_I2S2>; resets = <&tegra_car 18>; @@ -570,9 +572,9 @@ status = "disabled"; }; - tegra_i2s3: i2s@70301300 { + tegra_i2s3: i2s@0,70301300 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301300 0x100>; + reg = <0x0 0x70301300 0x0 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA124_CLK_I2S3>; resets = <&tegra_car 101>; @@ -580,9 +582,9 @@ status = "disabled"; }; - tegra_i2s4: i2s@70301400 { + tegra_i2s4: i2s@0,70301400 { compatible = "nvidia,tegra124-i2s"; - reg = <0x70301400 0x100>; + reg = <0x0 0x70301400 0x0 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA124_CLK_I2S4>; resets = <&tegra_car 102>; @@ -591,9 +593,9 @@ }; }; - usb@7d000000 { + usb@0,7d000000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d000000 0x4000>; + reg = <0x0 0x7d000000 0x0 0x4000>; interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>; @@ -603,9 +605,10 @@ status = "disabled"; }; - phy1: usb-phy@7d000000 { + phy1: usb-phy@0,7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d000000 0x4000 0x7d000000 0x4000>; + reg = <0x0 0x7d000000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -624,9 +627,9 @@ status = "disabled"; }; - usb@7d004000 { + usb@0,7d004000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d004000 0x4000>; + reg = <0x0 0x7d004000 0x0 0x4000>; interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>; @@ -636,9 +639,10 @@ status = "disabled"; }; - phy2: usb-phy@7d004000 { + phy2: usb-phy@0,7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000 0x7d000000 0x4000>; + reg = <0x0 0x7d004000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -657,9 +661,9 @@ status = "disabled"; }; - usb@7d008000 { + usb@0,7d008000 { compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; - reg = <0x7d008000 0x4000>; + reg = <0x0 0x7d008000 0x0 0x4000>; interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>; @@ -669,9 +673,10 @@ status = "disabled"; }; - phy3: usb-phy@7d008000 { + phy3: usb-phy@0,7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; - reg = <0x7d008000 0x4000 0x7d000000 0x4000>; + reg = <0x0 0x7d008000 0x0 0x4000>, + <0x0 0x7d000000 0x0 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, -- cgit v1.2.3-70-g09d2 From 97070bd44bab603fc47063952250f479e9e7321e Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 5 Mar 2014 14:25:46 +0100 Subject: ARM: dts: tegra: add PCIe interrupt mapping properties Those are defined by the common PCI binding. Signed-off-by: Lucas Stach Acked-by: Arnd Bergmann Signed-off-by: Stephen Warren --- Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 8 ++++++++ arch/arm/boot/dts/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 3 files changed, 16 insertions(+) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 24cee06915c..c300391e8d3 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt @@ -42,6 +42,10 @@ Required properties: - 0xc2000000: prefetchable memory region Please refer to the standard PCI bus binding document for a more detailed explanation. +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. - clocks: Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names: Must include the following entries: @@ -86,6 +90,10 @@ SoC DTSI: 0 99 0x04>; /* MSI interrupt */ interrupt-names = "intr", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 480ecda3416..52ef2cf0b14 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -552,6 +552,10 @@ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 18d52a7704c..6c9ee9697e6 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -28,6 +28,10 @@ GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ interrupt-names = "intr", "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; -- cgit v1.2.3-70-g09d2