From 74ddcdb868a84f4a9f65e33c1ca0d24e1134e53a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 21 Dec 2012 22:42:39 +0100 Subject: ARM: 7608/1: l2x0: Only set .set_debug on PL310 r3p0 and earlier PL310 errata work-arounds using .set_debug function are only needed on r3p0 and earlier, so check the rev and only set .set_debug on older revs. Avoiding debug register accesses fixes aborts on non-secure platforms like highbank. It is assumed that non-secure platforms needing these work-arounds have already implemented .set_debug with secure monitor calls. Signed-off-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 6911b8b2745..05d577613b1 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -352,7 +352,8 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) /* Unmapped register. */ sync_reg_offset = L2X0_DUMMY_REG; #endif - outer_cache.set_debug = pl310_set_debug; + if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0) + outer_cache.set_debug = pl310_set_debug; break; case L2X0_CACHE_ID_PART_L210: ways = (aux >> 13) & 0xf; -- cgit v1.2.3-70-g09d2 From 62e4d357aae0c7438c537bdb1c86909d7cac2663 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 21 Dec 2012 22:42:40 +0100 Subject: ARM: 7609/1: disable errata work-arounds which access secure registers In order to support secure and non-secure platforms in multi-platform kernels, errata work-arounds that access secure only registers need to be disabled. Make all the errata options that fit in this category depend on !CONFIG_ARCH_MULTIPLATFORM. This will effectively remove the errata options as platforms are converted over to multi-platform. Signed-off-by: Rob Herring Acked-by: Tony Lindgren Signed-off-by: Russell King --- arch/arm/Kconfig | 6 ++++++ arch/arm/mach-vexpress/Kconfig | 1 - arch/arm/mm/proc-v7.S | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f95ba14ae3d..432921ecfec 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1230,6 +1230,7 @@ config ARM_ERRATA_430973 config ARM_ERRATA_458693 bool "ARM errata: Processor deadlock when a false hazard is created" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 458693 Cortex-A8 (r2p0) erratum. For very specific sequences of memory operations, it is @@ -1243,6 +1244,7 @@ config ARM_ERRATA_458693 config ARM_ERRATA_460075 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 460075 Cortex-A8 (r2p0) erratum. Any asynchronous access to the L2 cache may encounter a @@ -1255,6 +1257,7 @@ config ARM_ERRATA_460075 config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" depends on CPU_V7 && SMP + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 742230 Cortex-A9 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction @@ -1267,6 +1270,7 @@ config ARM_ERRATA_742230 config ARM_ERRATA_742231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" depends on CPU_V7 && SMP + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 742231 Cortex-A9 (r2p0..r2p2) erratum. Under certain conditions, specific to the @@ -1317,6 +1321,7 @@ config PL310_ERRATA_727915 config ARM_ERRATA_743622 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 743622 Cortex-A9 (r2p*) erratum. Under very rare conditions, a faulty @@ -1330,6 +1335,7 @@ config ARM_ERRATA_743622 config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" depends on CPU_V7 + depends on !ARCH_MULTIPLATFORM help This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 99e63f5f99d..52d315b792c 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig @@ -42,7 +42,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA bool "Enable A5 and A9 only errata work-arounds" default y select ARM_ERRATA_720789 - select ARM_ERRATA_751472 select PL310_ERRATA_753970 if CACHE_PL310 help Provides common dependencies for Versatile Express platforms diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 350f6a74992..26a62054f0c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -245,7 +245,8 @@ __v7_setup: ldr r10, =0x00000c08 @ Cortex-A8 primary part number teq r0, r10 bne 2f -#ifdef CONFIG_ARM_ERRATA_430973 +#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM) + teq r5, #0x00100000 @ only present in r1p* mrceq p15, 0, r10, c1, c0, 1 @ read aux control register orreq r10, r10, #(1 << 6) @ set IBE to 1 -- cgit v1.2.3-70-g09d2 From f5565295892eb93c3191aa241405fe8b685542d6 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 26 Dec 2012 01:38:28 +0100 Subject: ARM: 7610/1: versatile: bump IRQ numbers The Versatile starts to register Linux IRQ numbers from offset 0 which is illegal, since this is NO_IRQ. Bump all hard-coded IRQs by 32 to get rid of the problem. Cc: Grant Likely Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/mach-versatile/include/mach/irqs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index bf44c61bd1f..0fd771ca617 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h @@ -25,7 +25,7 @@ * IRQ interrupts definitions are the same as the INT definitions * held within platform.h */ -#define IRQ_VIC_START 0 +#define IRQ_VIC_START 32 #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) @@ -100,7 +100,7 @@ /* * Secondary interrupt controller */ -#define IRQ_SIC_START 32 +#define IRQ_SIC_START 64 #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) @@ -120,7 +120,7 @@ #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) -#define IRQ_SIC_END 63 +#define IRQ_SIC_END 95 #define IRQ_GPIO0_START (IRQ_SIC_END + 1) #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31) -- cgit v1.2.3-70-g09d2 From 5ced33bc06e7e76cb8a236f15bff49eb6155b618 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 26 Dec 2012 01:39:16 +0100 Subject: ARM: 7611/1: VIC: fix bug in VIC irqdomain code The VIC irqdomain code added in commit 07c9249f1fa90cc8189bed44c0bcece664596a72 "ARM: 7554/1: VIC: use irq_domain_add_simple()" Had two bugs: 1) It didn't call irq_create_mapping() once on each valid irq source in the slowpath when registering the controller. 2) It passed a -1 as IRQ offset for the DT case, whereas 0 should be passed as invalid IRQ instead. Cc: Grant Likely Signed-off-by: Linus Walleij Signed-off-by: Russell King --- arch/arm/common/vic.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index e4df17ca90c..8f324b99416 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -206,6 +206,7 @@ static void __init vic_register(void __iomem *base, unsigned int irq, struct device_node *node) { struct vic_device *v; + int i; if (vic_id >= ARRAY_SIZE(vic_devices)) { printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); @@ -220,6 +221,10 @@ static void __init vic_register(void __iomem *base, unsigned int irq, vic_id++; v->domain = irq_domain_add_simple(node, fls(valid_sources), irq, &vic_irqdomain_ops, v); + /* create an IRQ mapping for each valid IRQ */ + for (i = 0; i < fls(valid_sources); i++) + if (valid_sources & (1 << i)) + irq_create_mapping(v->domain, i); } static void vic_ack_irq(struct irq_data *d) @@ -416,9 +421,9 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent) return -EIO; /* - * Passing -1 as first IRQ makes the simple domain allocate descriptors + * Passing 0 as first IRQ makes the simple domain allocate descriptors */ - __vic_init(regs, -1, ~0, ~0, node); + __vic_init(regs, 0, ~0, ~0, node); return 0; } -- cgit v1.2.3-70-g09d2 From a47e3bc10d0e34a67e10a9f8150a144af654be2a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 5 Jan 2013 03:51:59 +0100 Subject: ARM: 7612/1: imx: Do not select some errata that depends on !ARCH_MULTIPLATFORM Since commit 62e4d357a (ARM: 7609/1: disable errata work-arounds which access secure registers) ARM_ERRATA_743622/751472 depends on !ARCH_MULTIPLATFORM. Since imx has been converted to multiplatform, the following warning happens: $ make imx_v6_v7_defconfig warning: (SOC_IMX6Q && ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_751472 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM) warning: (SOC_IMX6Q && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_743622 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM) warning: (SOC_IMX6Q && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_743622 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM) warning: (SOC_IMX6Q && ARCH_TEGRA_2x_SOC && ARCH_TEGRA_3x_SOC) selects ARM_ERRATA_751472 which has unmet direct dependencies (CPU_V7 && !ARCH_MULTIPLATFORM) Recommended approach is to remove ARM_ERRATA_743622/751472 from being selected by SOC_IMX6Q and apply such workarounds into the bootloader. Signed-off-by: Fabio Estevam Acked-by: Rob Herring Signed-off-by: Russell King --- arch/arm/mach-imx/Kconfig | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 1ad0d76de8c..3e628fd7a67 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -841,8 +841,6 @@ config SOC_IMX6Q select ARCH_HAS_CPUFREQ select ARCH_HAS_OPP select ARM_CPU_SUSPEND if PM - select ARM_ERRATA_743622 - select ARM_ERRATA_751472 select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP select ARM_ERRATA_775420 -- cgit v1.2.3-70-g09d2 From d106de38ca927f2a53cd56ef94c506e8f6bd37e1 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Sat, 5 Jan 2013 13:57:38 +0100 Subject: ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b If CONFIG_ARCH_MULTIPLATFORM & CONFIG_ARCH_MVEBU are both enabled, __v7_pj4b_setup is added between __v7_ca9mp_setup and __v7_setup. But there's no jump instruction added. If the chip is Cortex A5/A9, it goes through __v7_pj4b_setup also. It results in system hang. Signed-off-by: Haojian Zhuang Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 26a62054f0c..3a3c015f8d5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -169,6 +169,7 @@ __v7_ca15mp_setup: orreq r0, r0, r10 @ Enable CPU-specific SMP bits mcreq p15, 0, r0, c1, c0, 1 #endif + b __v7_setup __v7_pj4b_setup: #ifdef CONFIG_CPU_PJ4B -- cgit v1.2.3-70-g09d2 From 8b827c60a1d984ef8c3ed175c99a33dd451348ff Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Jan 2013 11:27:14 +0100 Subject: ARM: 7615/1: cache-l2x0: aurora: Invalidate during clean operation with WT enable This patch fixes a bug for Aurora L2 cache controller when the write-through mode is enable. For the clean operation even if we don't have to flush the lines we still need to invalidate them. Signed-off-by: Gregory CLEMENT Tested-by: Thomas Petazzoni Acked-by: Jason Cooper Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 05d577613b1..55ca637a493 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -506,15 +506,21 @@ static void aurora_clean_range(unsigned long start, unsigned long end) static void aurora_flush_range(unsigned long start, unsigned long end) { - if (!l2_wt_override) { - start &= ~(CACHE_LINE_SIZE - 1); - end = ALIGN(end, CACHE_LINE_SIZE); - while (start != end) { - unsigned long range_end = calc_range_end(start, end); + start &= ~(CACHE_LINE_SIZE - 1); + end = ALIGN(end, CACHE_LINE_SIZE); + while (start != end) { + unsigned long range_end = calc_range_end(start, end); + /* + * If L2 is forced to WT, the L2 will always be clean and we + * just need to invalidate. + */ + if (l2_wt_override) aurora_pa_range(start, range_end - CACHE_LINE_SIZE, - AURORA_FLUSH_RANGE_REG); - start = range_end; - } + AURORA_INVAL_RANGE_REG); + else + aurora_pa_range(start, range_end - CACHE_LINE_SIZE, + AURORA_FLUSH_RANGE_REG); + start = range_end; } } -- cgit v1.2.3-70-g09d2 From 8a3a180d21793f2e4386b3cb61c48322564fc80a Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 7 Jan 2013 11:28:42 +0100 Subject: ARM: 7616/1: cache-l2x0: aurora: Use writel_relaxed instead of writel The use of writel instead of writel_relaxed lead to deadlock in some situation (SMP on Armada 370 for instance). The use of writel_relaxed as it was done in the rest of this driver fixes this bug. Signed-off-by: Gregory CLEMENT Tested-by: Thomas Petazzoni Acked-by: Jason Cooper Signed-off-by: Russell King --- arch/arm/mm/cache-l2x0.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 55ca637a493..c2f37390308 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -460,8 +460,8 @@ static void aurora_pa_range(unsigned long start, unsigned long end, unsigned long flags; raw_spin_lock_irqsave(&l2x0_lock, flags); - writel(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); - writel(end, l2x0_base + offset); + writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG); + writel_relaxed(end, l2x0_base + offset); raw_spin_unlock_irqrestore(&l2x0_lock, flags); cache_sync(); @@ -675,8 +675,9 @@ static void pl310_resume(void) static void aurora_resume(void) { if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { - writel(l2x0_saved_regs.aux_ctrl, l2x0_base + L2X0_AUX_CTRL); - writel(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); + writel_relaxed(l2x0_saved_regs.aux_ctrl, + l2x0_base + L2X0_AUX_CTRL); + writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL); } } -- cgit v1.2.3-70-g09d2