From 925ddb04c5eee5668e7229c71580d458ed61eb9b Mon Sep 17 00:00:00 2001
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Thu, 3 Feb 2005 23:06:29 +0000
Subject: Mask and ack CPU interrupts upon initialization. Keep the state of
software interrupts when unmasking.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
arch/mips/kernel/irq_cpu.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
(limited to 'arch')
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 2b936cf1ef7..8f8c15fa748 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -3,6 +3,8 @@
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2001 Ralf Baechle
+ * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
+ * Author: Maciej W. Rozycki <macro@mips.com>
*
* This file define the irq handler for MIPS CPU interrupts.
*
@@ -37,7 +39,6 @@ static int mips_cpu_irq_base;
static inline void unmask_mips_irq(unsigned int irq)
{
- clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
set_c0_status(0x100 << (irq - mips_cpu_irq_base));
}
@@ -107,6 +108,10 @@ void __init mips_cpu_irq_init(int irq_base)
{
int i;
+ /* Mask interrupts. */
+ clear_c0_status(ST0_IM);
+ clear_c0_cause(CAUSEF_IP);
+
for (i = irq_base; i < irq_base + 8; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
--
cgit v1.2.3-70-g09d2