From 852e372532bed457eaeb3edd198b939caeb863c5 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 9 Oct 2012 09:46:41 +0100 Subject: UAPI: (Scripted) Disintegrate arch/cris/include/arch-v10/arch Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones --- arch/cris/include/arch-v10/arch/Kbuild | 4 - arch/cris/include/arch-v10/arch/sv_addr.agh | 7306 --------------------- arch/cris/include/arch-v10/arch/sv_addr_ag.h | 139 - arch/cris/include/arch-v10/arch/svinto.h | 64 - arch/cris/include/arch-v10/arch/user.h | 46 - arch/cris/include/uapi/arch-v10/arch/Kbuild | 4 + arch/cris/include/uapi/arch-v10/arch/sv_addr.agh | 7306 +++++++++++++++++++++ arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h | 139 + arch/cris/include/uapi/arch-v10/arch/svinto.h | 64 + arch/cris/include/uapi/arch-v10/arch/user.h | 46 + 10 files changed, 7559 insertions(+), 7559 deletions(-) delete mode 100644 arch/cris/include/arch-v10/arch/sv_addr.agh delete mode 100644 arch/cris/include/arch-v10/arch/sv_addr_ag.h delete mode 100644 arch/cris/include/arch-v10/arch/svinto.h delete mode 100644 arch/cris/include/arch-v10/arch/user.h create mode 100644 arch/cris/include/uapi/arch-v10/arch/sv_addr.agh create mode 100644 arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h create mode 100644 arch/cris/include/uapi/arch-v10/arch/svinto.h create mode 100644 arch/cris/include/uapi/arch-v10/arch/user.h (limited to 'arch') diff --git a/arch/cris/include/arch-v10/arch/Kbuild b/arch/cris/include/arch-v10/arch/Kbuild index 7a192e1290b..e69de29bb2d 100644 --- a/arch/cris/include/arch-v10/arch/Kbuild +++ b/arch/cris/include/arch-v10/arch/Kbuild @@ -1,4 +0,0 @@ -header-y += user.h -header-y += svinto.h -header-y += sv_addr_ag.h -header-y += sv_addr.agh diff --git a/arch/cris/include/arch-v10/arch/sv_addr.agh b/arch/cris/include/arch-v10/arch/sv_addr.agh deleted file mode 100644 index 6ac3a7bc976..00000000000 --- a/arch/cris/include/arch-v10/arch/sv_addr.agh +++ /dev/null @@ -1,7306 +0,0 @@ -/* -!* This file was automatically generated by /n/asic/bin/reg_macro_gen -!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. -!* Editing within this file is thus not recommended, -!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. -!*/ - - -/* -!* Bus interface configuration registers -!*/ - -#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) -#define R_WAITSTATES__pcs4_7_zw__BITNR 30 -#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 -#define R_WAITSTATES__pcs4_7_ew__BITNR 28 -#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 -#define R_WAITSTATES__pcs4_7_lw__BITNR 24 -#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 -#define R_WAITSTATES__pcs0_3_zw__BITNR 22 -#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 -#define R_WAITSTATES__pcs0_3_ew__BITNR 20 -#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 -#define R_WAITSTATES__pcs0_3_lw__BITNR 16 -#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 -#define R_WAITSTATES__sram_zw__BITNR 14 -#define R_WAITSTATES__sram_zw__WIDTH 2 -#define R_WAITSTATES__sram_ew__BITNR 12 -#define R_WAITSTATES__sram_ew__WIDTH 2 -#define R_WAITSTATES__sram_lw__BITNR 8 -#define R_WAITSTATES__sram_lw__WIDTH 4 -#define R_WAITSTATES__flash_zw__BITNR 6 -#define R_WAITSTATES__flash_zw__WIDTH 2 -#define R_WAITSTATES__flash_ew__BITNR 4 -#define R_WAITSTATES__flash_ew__WIDTH 2 -#define R_WAITSTATES__flash_lw__BITNR 0 -#define R_WAITSTATES__flash_lw__WIDTH 4 - -#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) -#define R_BUS_CONFIG__sram_type__BITNR 9 -#define R_BUS_CONFIG__sram_type__WIDTH 1 -#define R_BUS_CONFIG__sram_type__cwe 1 -#define R_BUS_CONFIG__sram_type__bwe 0 -#define R_BUS_CONFIG__dma_burst__BITNR 8 -#define R_BUS_CONFIG__dma_burst__WIDTH 1 -#define R_BUS_CONFIG__dma_burst__burst16 1 -#define R_BUS_CONFIG__dma_burst__burst32 0 -#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 -#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_wr__ext 1 -#define R_BUS_CONFIG__pcs4_7_wr__norm 0 -#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 -#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_wr__ext 1 -#define R_BUS_CONFIG__pcs0_3_wr__norm 0 -#define R_BUS_CONFIG__sram_wr__BITNR 5 -#define R_BUS_CONFIG__sram_wr__WIDTH 1 -#define R_BUS_CONFIG__sram_wr__ext 1 -#define R_BUS_CONFIG__sram_wr__norm 0 -#define R_BUS_CONFIG__flash_wr__BITNR 4 -#define R_BUS_CONFIG__flash_wr__WIDTH 1 -#define R_BUS_CONFIG__flash_wr__ext 1 -#define R_BUS_CONFIG__flash_wr__norm 0 -#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 -#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 -#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 -#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 -#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 -#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 -#define R_BUS_CONFIG__sram_bw__BITNR 1 -#define R_BUS_CONFIG__sram_bw__WIDTH 1 -#define R_BUS_CONFIG__sram_bw__bw32 1 -#define R_BUS_CONFIG__sram_bw__bw16 0 -#define R_BUS_CONFIG__flash_bw__BITNR 0 -#define R_BUS_CONFIG__flash_bw__WIDTH 1 -#define R_BUS_CONFIG__flash_bw__bw32 1 -#define R_BUS_CONFIG__flash_bw__bw16 0 - -#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) -#define R_BUS_STATUS__pll_lock_tm__BITNR 5 -#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 -#define R_BUS_STATUS__pll_lock_tm__expired 0 -#define R_BUS_STATUS__pll_lock_tm__counting 1 -#define R_BUS_STATUS__both_faults__BITNR 4 -#define R_BUS_STATUS__both_faults__WIDTH 1 -#define R_BUS_STATUS__both_faults__no 0 -#define R_BUS_STATUS__both_faults__yes 1 -#define R_BUS_STATUS__bsen___BITNR 3 -#define R_BUS_STATUS__bsen___WIDTH 1 -#define R_BUS_STATUS__bsen___enable 0 -#define R_BUS_STATUS__bsen___disable 1 -#define R_BUS_STATUS__boot__BITNR 1 -#define R_BUS_STATUS__boot__WIDTH 2 -#define R_BUS_STATUS__boot__uncached 0 -#define R_BUS_STATUS__boot__serial 1 -#define R_BUS_STATUS__boot__network 2 -#define R_BUS_STATUS__boot__parallel 3 -#define R_BUS_STATUS__flashw__BITNR 0 -#define R_BUS_STATUS__flashw__WIDTH 1 -#define R_BUS_STATUS__flashw__bw32 1 -#define R_BUS_STATUS__flashw__bw16 0 - -#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_DRAM_TIMING__sdram__BITNR 31 -#define R_DRAM_TIMING__sdram__WIDTH 1 -#define R_DRAM_TIMING__sdram__enable 1 -#define R_DRAM_TIMING__sdram__disable 0 -#define R_DRAM_TIMING__ref__BITNR 14 -#define R_DRAM_TIMING__ref__WIDTH 2 -#define R_DRAM_TIMING__ref__e52us 0 -#define R_DRAM_TIMING__ref__e13us 1 -#define R_DRAM_TIMING__ref__e8700ns 2 -#define R_DRAM_TIMING__ref__disable 3 -#define R_DRAM_TIMING__rp__BITNR 12 -#define R_DRAM_TIMING__rp__WIDTH 2 -#define R_DRAM_TIMING__rs__BITNR 10 -#define R_DRAM_TIMING__rs__WIDTH 2 -#define R_DRAM_TIMING__rh__BITNR 8 -#define R_DRAM_TIMING__rh__WIDTH 2 -#define R_DRAM_TIMING__w__BITNR 7 -#define R_DRAM_TIMING__w__WIDTH 1 -#define R_DRAM_TIMING__w__norm 0 -#define R_DRAM_TIMING__w__ext 1 -#define R_DRAM_TIMING__c__BITNR 6 -#define R_DRAM_TIMING__c__WIDTH 1 -#define R_DRAM_TIMING__c__norm 0 -#define R_DRAM_TIMING__c__ext 1 -#define R_DRAM_TIMING__cz__BITNR 4 -#define R_DRAM_TIMING__cz__WIDTH 2 -#define R_DRAM_TIMING__cp__BITNR 2 -#define R_DRAM_TIMING__cp__WIDTH 2 -#define R_DRAM_TIMING__cw__BITNR 0 -#define R_DRAM_TIMING__cw__WIDTH 2 - -#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) -#define R_SDRAM_TIMING__sdram__BITNR 31 -#define R_SDRAM_TIMING__sdram__WIDTH 1 -#define R_SDRAM_TIMING__sdram__enable 1 -#define R_SDRAM_TIMING__sdram__disable 0 -#define R_SDRAM_TIMING__mrs_data__BITNR 16 -#define R_SDRAM_TIMING__mrs_data__WIDTH 15 -#define R_SDRAM_TIMING__ref__BITNR 14 -#define R_SDRAM_TIMING__ref__WIDTH 2 -#define R_SDRAM_TIMING__ref__e52us 0 -#define R_SDRAM_TIMING__ref__e13us 1 -#define R_SDRAM_TIMING__ref__e6500ns 2 -#define R_SDRAM_TIMING__ref__disable 3 -#define R_SDRAM_TIMING__ddr__BITNR 13 -#define R_SDRAM_TIMING__ddr__WIDTH 1 -#define R_SDRAM_TIMING__ddr__on 1 -#define R_SDRAM_TIMING__ddr__off 0 -#define R_SDRAM_TIMING__clk100__BITNR 12 -#define R_SDRAM_TIMING__clk100__WIDTH 1 -#define R_SDRAM_TIMING__clk100__on 1 -#define R_SDRAM_TIMING__clk100__off 0 -#define R_SDRAM_TIMING__ps__BITNR 11 -#define R_SDRAM_TIMING__ps__WIDTH 1 -#define R_SDRAM_TIMING__ps__on 1 -#define R_SDRAM_TIMING__ps__off 0 -#define R_SDRAM_TIMING__cmd__BITNR 9 -#define R_SDRAM_TIMING__cmd__WIDTH 2 -#define R_SDRAM_TIMING__cmd__pre 3 -#define R_SDRAM_TIMING__cmd__ref 2 -#define R_SDRAM_TIMING__cmd__mrs 1 -#define R_SDRAM_TIMING__cmd__nop 0 -#define R_SDRAM_TIMING__pde__BITNR 8 -#define R_SDRAM_TIMING__pde__WIDTH 1 -#define R_SDRAM_TIMING__rc__BITNR 6 -#define R_SDRAM_TIMING__rc__WIDTH 2 -#define R_SDRAM_TIMING__rp__BITNR 4 -#define R_SDRAM_TIMING__rp__WIDTH 2 -#define R_SDRAM_TIMING__rcd__BITNR 2 -#define R_SDRAM_TIMING__rcd__WIDTH 2 -#define R_SDRAM_TIMING__cl__BITNR 0 -#define R_SDRAM_TIMING__cl__WIDTH 2 - -#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_DRAM_CONFIG__wmm1__BITNR 31 -#define R_DRAM_CONFIG__wmm1__WIDTH 1 -#define R_DRAM_CONFIG__wmm1__wmm 1 -#define R_DRAM_CONFIG__wmm1__norm 0 -#define R_DRAM_CONFIG__wmm0__BITNR 30 -#define R_DRAM_CONFIG__wmm0__WIDTH 1 -#define R_DRAM_CONFIG__wmm0__wmm 1 -#define R_DRAM_CONFIG__wmm0__norm 0 -#define R_DRAM_CONFIG__sh1__BITNR 27 -#define R_DRAM_CONFIG__sh1__WIDTH 3 -#define R_DRAM_CONFIG__sh0__BITNR 24 -#define R_DRAM_CONFIG__sh0__WIDTH 3 -#define R_DRAM_CONFIG__w__BITNR 23 -#define R_DRAM_CONFIG__w__WIDTH 1 -#define R_DRAM_CONFIG__w__bw16 0 -#define R_DRAM_CONFIG__w__bw32 1 -#define R_DRAM_CONFIG__c__BITNR 22 -#define R_DRAM_CONFIG__c__WIDTH 1 -#define R_DRAM_CONFIG__c__byte 0 -#define R_DRAM_CONFIG__c__bank 1 -#define R_DRAM_CONFIG__e__BITNR 21 -#define R_DRAM_CONFIG__e__WIDTH 1 -#define R_DRAM_CONFIG__e__fast 0 -#define R_DRAM_CONFIG__e__edo 1 -#define R_DRAM_CONFIG__group_sel__BITNR 16 -#define R_DRAM_CONFIG__group_sel__WIDTH 5 -#define R_DRAM_CONFIG__group_sel__grp0 0 -#define R_DRAM_CONFIG__group_sel__grp1 1 -#define R_DRAM_CONFIG__group_sel__bit9 9 -#define R_DRAM_CONFIG__group_sel__bit10 10 -#define R_DRAM_CONFIG__group_sel__bit11 11 -#define R_DRAM_CONFIG__group_sel__bit12 12 -#define R_DRAM_CONFIG__group_sel__bit13 13 -#define R_DRAM_CONFIG__group_sel__bit14 14 -#define R_DRAM_CONFIG__group_sel__bit15 15 -#define R_DRAM_CONFIG__group_sel__bit16 16 -#define R_DRAM_CONFIG__group_sel__bit17 17 -#define R_DRAM_CONFIG__group_sel__bit18 18 -#define R_DRAM_CONFIG__group_sel__bit19 19 -#define R_DRAM_CONFIG__group_sel__bit20 20 -#define R_DRAM_CONFIG__group_sel__bit21 21 -#define R_DRAM_CONFIG__group_sel__bit22 22 -#define R_DRAM_CONFIG__group_sel__bit23 23 -#define R_DRAM_CONFIG__group_sel__bit24 24 -#define R_DRAM_CONFIG__group_sel__bit25 25 -#define R_DRAM_CONFIG__group_sel__bit26 26 -#define R_DRAM_CONFIG__group_sel__bit27 27 -#define R_DRAM_CONFIG__group_sel__bit28 28 -#define R_DRAM_CONFIG__group_sel__bit29 29 -#define R_DRAM_CONFIG__ca1__BITNR 13 -#define R_DRAM_CONFIG__ca1__WIDTH 3 -#define R_DRAM_CONFIG__bank23sel__BITNR 8 -#define R_DRAM_CONFIG__bank23sel__WIDTH 5 -#define R_DRAM_CONFIG__bank23sel__bank0 0 -#define R_DRAM_CONFIG__bank23sel__bank1 1 -#define R_DRAM_CONFIG__bank23sel__bit9 9 -#define R_DRAM_CONFIG__bank23sel__bit10 10 -#define R_DRAM_CONFIG__bank23sel__bit11 11 -#define R_DRAM_CONFIG__bank23sel__bit12 12 -#define R_DRAM_CONFIG__bank23sel__bit13 13 -#define R_DRAM_CONFIG__bank23sel__bit14 14 -#define R_DRAM_CONFIG__bank23sel__bit15 15 -#define R_DRAM_CONFIG__bank23sel__bit16 16 -#define R_DRAM_CONFIG__bank23sel__bit17 17 -#define R_DRAM_CONFIG__bank23sel__bit18 18 -#define R_DRAM_CONFIG__bank23sel__bit19 19 -#define R_DRAM_CONFIG__bank23sel__bit20 20 -#define R_DRAM_CONFIG__bank23sel__bit21 21 -#define R_DRAM_CONFIG__bank23sel__bit22 22 -#define R_DRAM_CONFIG__bank23sel__bit23 23 -#define R_DRAM_CONFIG__bank23sel__bit24 24 -#define R_DRAM_CONFIG__bank23sel__bit25 25 -#define R_DRAM_CONFIG__bank23sel__bit26 26 -#define R_DRAM_CONFIG__bank23sel__bit27 27 -#define R_DRAM_CONFIG__bank23sel__bit28 28 -#define R_DRAM_CONFIG__bank23sel__bit29 29 -#define R_DRAM_CONFIG__ca0__BITNR 5 -#define R_DRAM_CONFIG__ca0__WIDTH 3 -#define R_DRAM_CONFIG__bank01sel__BITNR 0 -#define R_DRAM_CONFIG__bank01sel__WIDTH 5 -#define R_DRAM_CONFIG__bank01sel__bank0 0 -#define R_DRAM_CONFIG__bank01sel__bank1 1 -#define R_DRAM_CONFIG__bank01sel__bit9 9 -#define R_DRAM_CONFIG__bank01sel__bit10 10 -#define R_DRAM_CONFIG__bank01sel__bit11 11 -#define R_DRAM_CONFIG__bank01sel__bit12 12 -#define R_DRAM_CONFIG__bank01sel__bit13 13 -#define R_DRAM_CONFIG__bank01sel__bit14 14 -#define R_DRAM_CONFIG__bank01sel__bit15 15 -#define R_DRAM_CONFIG__bank01sel__bit16 16 -#define R_DRAM_CONFIG__bank01sel__bit17 17 -#define R_DRAM_CONFIG__bank01sel__bit18 18 -#define R_DRAM_CONFIG__bank01sel__bit19 19 -#define R_DRAM_CONFIG__bank01sel__bit20 20 -#define R_DRAM_CONFIG__bank01sel__bit21 21 -#define R_DRAM_CONFIG__bank01sel__bit22 22 -#define R_DRAM_CONFIG__bank01sel__bit23 23 -#define R_DRAM_CONFIG__bank01sel__bit24 24 -#define R_DRAM_CONFIG__bank01sel__bit25 25 -#define R_DRAM_CONFIG__bank01sel__bit26 26 -#define R_DRAM_CONFIG__bank01sel__bit27 27 -#define R_DRAM_CONFIG__bank01sel__bit28 28 -#define R_DRAM_CONFIG__bank01sel__bit29 29 - -#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) -#define R_SDRAM_CONFIG__wmm1__BITNR 31 -#define R_SDRAM_CONFIG__wmm1__WIDTH 1 -#define R_SDRAM_CONFIG__wmm1__wmm 1 -#define R_SDRAM_CONFIG__wmm1__norm 0 -#define R_SDRAM_CONFIG__wmm0__BITNR 30 -#define R_SDRAM_CONFIG__wmm0__WIDTH 1 -#define R_SDRAM_CONFIG__wmm0__wmm 1 -#define R_SDRAM_CONFIG__wmm0__norm 0 -#define R_SDRAM_CONFIG__sh1__BITNR 27 -#define R_SDRAM_CONFIG__sh1__WIDTH 3 -#define R_SDRAM_CONFIG__sh0__BITNR 24 -#define R_SDRAM_CONFIG__sh0__WIDTH 3 -#define R_SDRAM_CONFIG__w__BITNR 23 -#define R_SDRAM_CONFIG__w__WIDTH 1 -#define R_SDRAM_CONFIG__w__bw16 0 -#define R_SDRAM_CONFIG__w__bw32 1 -#define R_SDRAM_CONFIG__type1__BITNR 22 -#define R_SDRAM_CONFIG__type1__WIDTH 1 -#define R_SDRAM_CONFIG__type1__bank2 0 -#define R_SDRAM_CONFIG__type1__bank4 1 -#define R_SDRAM_CONFIG__type0__BITNR 21 -#define R_SDRAM_CONFIG__type0__WIDTH 1 -#define R_SDRAM_CONFIG__type0__bank2 0 -#define R_SDRAM_CONFIG__type0__bank4 1 -#define R_SDRAM_CONFIG__group_sel__BITNR 16 -#define R_SDRAM_CONFIG__group_sel__WIDTH 5 -#define R_SDRAM_CONFIG__group_sel__grp0 0 -#define R_SDRAM_CONFIG__group_sel__grp1 1 -#define R_SDRAM_CONFIG__group_sel__bit9 9 -#define R_SDRAM_CONFIG__group_sel__bit10 10 -#define R_SDRAM_CONFIG__group_sel__bit11 11 -#define R_SDRAM_CONFIG__group_sel__bit12 12 -#define R_SDRAM_CONFIG__group_sel__bit13 13 -#define R_SDRAM_CONFIG__group_sel__bit14 14 -#define R_SDRAM_CONFIG__group_sel__bit15 15 -#define R_SDRAM_CONFIG__group_sel__bit16 16 -#define R_SDRAM_CONFIG__group_sel__bit17 17 -#define R_SDRAM_CONFIG__group_sel__bit18 18 -#define R_SDRAM_CONFIG__group_sel__bit19 19 -#define R_SDRAM_CONFIG__group_sel__bit20 20 -#define R_SDRAM_CONFIG__group_sel__bit21 21 -#define R_SDRAM_CONFIG__group_sel__bit22 22 -#define R_SDRAM_CONFIG__group_sel__bit23 23 -#define R_SDRAM_CONFIG__group_sel__bit24 24 -#define R_SDRAM_CONFIG__group_sel__bit25 25 -#define R_SDRAM_CONFIG__group_sel__bit26 26 -#define R_SDRAM_CONFIG__group_sel__bit27 27 -#define R_SDRAM_CONFIG__group_sel__bit28 28 -#define R_SDRAM_CONFIG__group_sel__bit29 29 -#define R_SDRAM_CONFIG__ca1__BITNR 13 -#define R_SDRAM_CONFIG__ca1__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 -#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel1__bit9 9 -#define R_SDRAM_CONFIG__bank_sel1__bit10 10 -#define R_SDRAM_CONFIG__bank_sel1__bit11 11 -#define R_SDRAM_CONFIG__bank_sel1__bit12 12 -#define R_SDRAM_CONFIG__bank_sel1__bit13 13 -#define R_SDRAM_CONFIG__bank_sel1__bit14 14 -#define R_SDRAM_CONFIG__bank_sel1__bit15 15 -#define R_SDRAM_CONFIG__bank_sel1__bit16 16 -#define R_SDRAM_CONFIG__bank_sel1__bit17 17 -#define R_SDRAM_CONFIG__bank_sel1__bit18 18 -#define R_SDRAM_CONFIG__bank_sel1__bit19 19 -#define R_SDRAM_CONFIG__bank_sel1__bit20 20 -#define R_SDRAM_CONFIG__bank_sel1__bit21 21 -#define R_SDRAM_CONFIG__bank_sel1__bit22 22 -#define R_SDRAM_CONFIG__bank_sel1__bit23 23 -#define R_SDRAM_CONFIG__bank_sel1__bit24 24 -#define R_SDRAM_CONFIG__bank_sel1__bit25 25 -#define R_SDRAM_CONFIG__bank_sel1__bit26 26 -#define R_SDRAM_CONFIG__bank_sel1__bit27 27 -#define R_SDRAM_CONFIG__bank_sel1__bit28 28 -#define R_SDRAM_CONFIG__bank_sel1__bit29 29 -#define R_SDRAM_CONFIG__ca0__BITNR 5 -#define R_SDRAM_CONFIG__ca0__WIDTH 3 -#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 -#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 -#define R_SDRAM_CONFIG__bank_sel0__bit9 9 -#define R_SDRAM_CONFIG__bank_sel0__bit10 10 -#define R_SDRAM_CONFIG__bank_sel0__bit11 11 -#define R_SDRAM_CONFIG__bank_sel0__bit12 12 -#define R_SDRAM_CONFIG__bank_sel0__bit13 13 -#define R_SDRAM_CONFIG__bank_sel0__bit14 14 -#define R_SDRAM_CONFIG__bank_sel0__bit15 15 -#define R_SDRAM_CONFIG__bank_sel0__bit16 16 -#define R_SDRAM_CONFIG__bank_sel0__bit17 17 -#define R_SDRAM_CONFIG__bank_sel0__bit18 18 -#define R_SDRAM_CONFIG__bank_sel0__bit19 19 -#define R_SDRAM_CONFIG__bank_sel0__bit20 20 -#define R_SDRAM_CONFIG__bank_sel0__bit21 21 -#define R_SDRAM_CONFIG__bank_sel0__bit22 22 -#define R_SDRAM_CONFIG__bank_sel0__bit23 23 -#define R_SDRAM_CONFIG__bank_sel0__bit24 24 -#define R_SDRAM_CONFIG__bank_sel0__bit25 25 -#define R_SDRAM_CONFIG__bank_sel0__bit26 26 -#define R_SDRAM_CONFIG__bank_sel0__bit27 27 -#define R_SDRAM_CONFIG__bank_sel0__bit28 28 -#define R_SDRAM_CONFIG__bank_sel0__bit29 29 - -/* -!* External DMA registers -!*/ - -#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) -#define R_EXT_DMA_0_CMD__cnt__BITNR 23 -#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_0_CMD__cnt__enable 1 -#define R_EXT_DMA_0_CMD__cnt__disable 0 -#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_0_CMD__rqpol__alow 1 -#define R_EXT_DMA_0_CMD__apol__BITNR 21 -#define R_EXT_DMA_0_CMD__apol__WIDTH 1 -#define R_EXT_DMA_0_CMD__apol__ahigh 0 -#define R_EXT_DMA_0_CMD__apol__alow 1 -#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_0_CMD__rq_ack__burst 0 -#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_0_CMD__wid__BITNR 18 -#define R_EXT_DMA_0_CMD__wid__WIDTH 2 -#define R_EXT_DMA_0_CMD__wid__byte 0 -#define R_EXT_DMA_0_CMD__wid__word 1 -#define R_EXT_DMA_0_CMD__wid__dword 2 -#define R_EXT_DMA_0_CMD__dir__BITNR 17 -#define R_EXT_DMA_0_CMD__dir__WIDTH 1 -#define R_EXT_DMA_0_CMD__dir__input 0 -#define R_EXT_DMA_0_CMD__dir__output 1 -#define R_EXT_DMA_0_CMD__run__BITNR 16 -#define R_EXT_DMA_0_CMD__run__WIDTH 1 -#define R_EXT_DMA_0_CMD__run__start 1 -#define R_EXT_DMA_0_CMD__run__stop 0 -#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) -#define R_EXT_DMA_0_STAT__run__BITNR 16 -#define R_EXT_DMA_0_STAT__run__WIDTH 1 -#define R_EXT_DMA_0_STAT__run__start 1 -#define R_EXT_DMA_0_STAT__run__stop 0 -#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) -#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 - -#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) -#define R_EXT_DMA_1_CMD__cnt__BITNR 23 -#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 -#define R_EXT_DMA_1_CMD__cnt__enable 1 -#define R_EXT_DMA_1_CMD__cnt__disable 0 -#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 -#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 -#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 -#define R_EXT_DMA_1_CMD__rqpol__alow 1 -#define R_EXT_DMA_1_CMD__apol__BITNR 21 -#define R_EXT_DMA_1_CMD__apol__WIDTH 1 -#define R_EXT_DMA_1_CMD__apol__ahigh 0 -#define R_EXT_DMA_1_CMD__apol__alow 1 -#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 -#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 -#define R_EXT_DMA_1_CMD__rq_ack__burst 0 -#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 -#define R_EXT_DMA_1_CMD__wid__BITNR 18 -#define R_EXT_DMA_1_CMD__wid__WIDTH 2 -#define R_EXT_DMA_1_CMD__wid__byte 0 -#define R_EXT_DMA_1_CMD__wid__word 1 -#define R_EXT_DMA_1_CMD__wid__dword 2 -#define R_EXT_DMA_1_CMD__dir__BITNR 17 -#define R_EXT_DMA_1_CMD__dir__WIDTH 1 -#define R_EXT_DMA_1_CMD__dir__input 0 -#define R_EXT_DMA_1_CMD__dir__output 1 -#define R_EXT_DMA_1_CMD__run__BITNR 16 -#define R_EXT_DMA_1_CMD__run__WIDTH 1 -#define R_EXT_DMA_1_CMD__run__start 1 -#define R_EXT_DMA_1_CMD__run__stop 0 -#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 -#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) -#define R_EXT_DMA_1_STAT__run__BITNR 16 -#define R_EXT_DMA_1_STAT__run__WIDTH 1 -#define R_EXT_DMA_1_STAT__run__start 1 -#define R_EXT_DMA_1_STAT__run__stop 0 -#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 -#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 - -#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) -#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 -#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 - -/* -!* Timer registers -!*/ - -#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) -#define R_TIMER_CTRL__timerdiv1__BITNR 24 -#define R_TIMER_CTRL__timerdiv1__WIDTH 8 -#define R_TIMER_CTRL__timerdiv0__BITNR 16 -#define R_TIMER_CTRL__timerdiv0__WIDTH 8 -#define R_TIMER_CTRL__presc_timer1__BITNR 15 -#define R_TIMER_CTRL__presc_timer1__WIDTH 1 -#define R_TIMER_CTRL__presc_timer1__normal 0 -#define R_TIMER_CTRL__presc_timer1__prescale 1 -#define R_TIMER_CTRL__i1__BITNR 14 -#define R_TIMER_CTRL__i1__WIDTH 1 -#define R_TIMER_CTRL__i1__clr 1 -#define R_TIMER_CTRL__i1__nop 0 -#define R_TIMER_CTRL__tm1__BITNR 12 -#define R_TIMER_CTRL__tm1__WIDTH 2 -#define R_TIMER_CTRL__tm1__stop_ld 0 -#define R_TIMER_CTRL__tm1__freeze 1 -#define R_TIMER_CTRL__tm1__run 2 -#define R_TIMER_CTRL__tm1__reserved 3 -#define R_TIMER_CTRL__clksel1__BITNR 8 -#define R_TIMER_CTRL__clksel1__WIDTH 4 -#define R_TIMER_CTRL__clksel1__c300Hz 0 -#define R_TIMER_CTRL__clksel1__c600Hz 1 -#define R_TIMER_CTRL__clksel1__c1200Hz 2 -#define R_TIMER_CTRL__clksel1__c2400Hz 3 -#define R_TIMER_CTRL__clksel1__c4800Hz 4 -#define R_TIMER_CTRL__clksel1__c9600Hz 5 -#define R_TIMER_CTRL__clksel1__c19k2Hz 6 -#define R_TIMER_CTRL__clksel1__c38k4Hz 7 -#define R_TIMER_CTRL__clksel1__c57k6Hz 8 -#define R_TIMER_CTRL__clksel1__c115k2Hz 9 -#define R_TIMER_CTRL__clksel1__c230k4Hz 10 -#define R_TIMER_CTRL__clksel1__c460k8Hz 11 -#define R_TIMER_CTRL__clksel1__c921k6Hz 12 -#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel1__c6250kHz 14 -#define R_TIMER_CTRL__clksel1__cascade0 15 -#define R_TIMER_CTRL__presc_ext__BITNR 7 -#define R_TIMER_CTRL__presc_ext__WIDTH 1 -#define R_TIMER_CTRL__presc_ext__prescale 0 -#define R_TIMER_CTRL__presc_ext__external 1 -#define R_TIMER_CTRL__i0__BITNR 6 -#define R_TIMER_CTRL__i0__WIDTH 1 -#define R_TIMER_CTRL__i0__clr 1 -#define R_TIMER_CTRL__i0__nop 0 -#define R_TIMER_CTRL__tm0__BITNR 4 -#define R_TIMER_CTRL__tm0__WIDTH 2 -#define R_TIMER_CTRL__tm0__stop_ld 0 -#define R_TIMER_CTRL__tm0__freeze 1 -#define R_TIMER_CTRL__tm0__run 2 -#define R_TIMER_CTRL__tm0__reserved 3 -#define R_TIMER_CTRL__clksel0__BITNR 0 -#define R_TIMER_CTRL__clksel0__WIDTH 4 -#define R_TIMER_CTRL__clksel0__c300Hz 0 -#define R_TIMER_CTRL__clksel0__c600Hz 1 -#define R_TIMER_CTRL__clksel0__c1200Hz 2 -#define R_TIMER_CTRL__clksel0__c2400Hz 3 -#define R_TIMER_CTRL__clksel0__c4800Hz 4 -#define R_TIMER_CTRL__clksel0__c9600Hz 5 -#define R_TIMER_CTRL__clksel0__c19k2Hz 6 -#define R_TIMER_CTRL__clksel0__c38k4Hz 7 -#define R_TIMER_CTRL__clksel0__c57k6Hz 8 -#define R_TIMER_CTRL__clksel0__c115k2Hz 9 -#define R_TIMER_CTRL__clksel0__c230k4Hz 10 -#define R_TIMER_CTRL__clksel0__c460k8Hz 11 -#define R_TIMER_CTRL__clksel0__c921k6Hz 12 -#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 -#define R_TIMER_CTRL__clksel0__c6250kHz 14 -#define R_TIMER_CTRL__clksel0__flexible 15 - -#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) -#define R_TIMER_DATA__timer1__BITNR 24 -#define R_TIMER_DATA__timer1__WIDTH 8 -#define R_TIMER_DATA__timer0__BITNR 16 -#define R_TIMER_DATA__timer0__WIDTH 8 -#define R_TIMER_DATA__clkdiv_high__BITNR 8 -#define R_TIMER_DATA__clkdiv_high__WIDTH 8 -#define R_TIMER_DATA__clkdiv_low__BITNR 0 -#define R_TIMER_DATA__clkdiv_low__WIDTH 8 - -#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) -#define R_TIMER01_DATA__count__BITNR 0 -#define R_TIMER01_DATA__count__WIDTH 16 - -#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) -#define R_TIMER0_DATA__count__BITNR 0 -#define R_TIMER0_DATA__count__WIDTH 8 - -#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) -#define R_TIMER1_DATA__count__BITNR 0 -#define R_TIMER1_DATA__count__WIDTH 8 - -#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) -#define R_WATCHDOG__key__BITNR 1 -#define R_WATCHDOG__key__WIDTH 3 -#define R_WATCHDOG__enable__BITNR 0 -#define R_WATCHDOG__enable__WIDTH 1 -#define R_WATCHDOG__enable__stop 0 -#define R_WATCHDOG__enable__start 1 - -#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) -#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 -#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 -#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 -#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 - -#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) -#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 -#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 - -#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) -#define R_TIMER_PRESCALE__tim_presc__BITNR 0 -#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 - -#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) -#define R_PRESCALE_STATUS__ser_status__BITNR 16 -#define R_PRESCALE_STATUS__ser_status__WIDTH 16 -#define R_PRESCALE_STATUS__tim_status__BITNR 0 -#define R_PRESCALE_STATUS__tim_status__WIDTH 16 - -#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) -#define R_SER_PRESC_STATUS__ser_status__BITNR 0 -#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 - -#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) -#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 -#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 - -#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 -#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 -#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 -#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 -#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 -#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 -#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 -#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 -#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 - -/* -!* Shared RAM interface registers -!*/ - -#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SHARED_RAM_CONFIG__width__BITNR 3 -#define R_SHARED_RAM_CONFIG__width__WIDTH 1 -#define R_SHARED_RAM_CONFIG__width__byte 0 -#define R_SHARED_RAM_CONFIG__width__word 1 -#define R_SHARED_RAM_CONFIG__enable__BITNR 2 -#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 -#define R_SHARED_RAM_CONFIG__enable__yes 1 -#define R_SHARED_RAM_CONFIG__enable__no 0 -#define R_SHARED_RAM_CONFIG__pint__BITNR 1 -#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 -#define R_SHARED_RAM_CONFIG__pint__int 1 -#define R_SHARED_RAM_CONFIG__pint__nop 0 -#define R_SHARED_RAM_CONFIG__clri__BITNR 0 -#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 -#define R_SHARED_RAM_CONFIG__clri__clr 1 -#define R_SHARED_RAM_CONFIG__clri__nop 0 - -#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 -#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 - -/* -!* General config registers -!*/ - -#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) -#define R_GEN_CONFIG__par_w__BITNR 31 -#define R_GEN_CONFIG__par_w__WIDTH 1 -#define R_GEN_CONFIG__par_w__select 1 -#define R_GEN_CONFIG__par_w__disable 0 -#define R_GEN_CONFIG__usb2__BITNR 30 -#define R_GEN_CONFIG__usb2__WIDTH 1 -#define R_GEN_CONFIG__usb2__select 1 -#define R_GEN_CONFIG__usb2__disable 0 -#define R_GEN_CONFIG__usb1__BITNR 29 -#define R_GEN_CONFIG__usb1__WIDTH 1 -#define R_GEN_CONFIG__usb1__select 1 -#define R_GEN_CONFIG__usb1__disable 0 -#define R_GEN_CONFIG__g24dir__BITNR 27 -#define R_GEN_CONFIG__g24dir__WIDTH 1 -#define R_GEN_CONFIG__g24dir__in 0 -#define R_GEN_CONFIG__g24dir__out 1 -#define R_GEN_CONFIG__g16_23dir__BITNR 26 -#define R_GEN_CONFIG__g16_23dir__WIDTH 1 -#define R_GEN_CONFIG__g16_23dir__in 0 -#define R_GEN_CONFIG__g16_23dir__out 1 -#define R_GEN_CONFIG__g8_15dir__BITNR 25 -#define R_GEN_CONFIG__g8_15dir__WIDTH 1 -#define R_GEN_CONFIG__g8_15dir__in 0 -#define R_GEN_CONFIG__g8_15dir__out 1 -#define R_GEN_CONFIG__g0dir__BITNR 24 -#define R_GEN_CONFIG__g0dir__WIDTH 1 -#define R_GEN_CONFIG__g0dir__in 0 -#define R_GEN_CONFIG__g0dir__out 1 -#define R_GEN_CONFIG__dma9__BITNR 23 -#define R_GEN_CONFIG__dma9__WIDTH 1 -#define R_GEN_CONFIG__dma9__usb 0 -#define R_GEN_CONFIG__dma9__serial1 1 -#define R_GEN_CONFIG__dma8__BITNR 22 -#define R_GEN_CONFIG__dma8__WIDTH 1 -#define R_GEN_CONFIG__dma8__usb 0 -#define R_GEN_CONFIG__dma8__serial1 1 -#define R_GEN_CONFIG__dma7__BITNR 20 -#define R_GEN_CONFIG__dma7__WIDTH 2 -#define R_GEN_CONFIG__dma7__unused 0 -#define R_GEN_CONFIG__dma7__serial0 1 -#define R_GEN_CONFIG__dma7__extdma1 2 -#define R_GEN_CONFIG__dma7__intdma6 3 -#define R_GEN_CONFIG__dma6__BITNR 18 -#define R_GEN_CONFIG__dma6__WIDTH 2 -#define R_GEN_CONFIG__dma6__unused 0 -#define R_GEN_CONFIG__dma6__serial0 1 -#define R_GEN_CONFIG__dma6__extdma1 2 -#define R_GEN_CONFIG__dma6__intdma7 3 -#define R_GEN_CONFIG__dma5__BITNR 16 -#define R_GEN_CONFIG__dma5__WIDTH 2 -#define R_GEN_CONFIG__dma5__par1 0 -#define R_GEN_CONFIG__dma5__scsi1 1 -#define R_GEN_CONFIG__dma5__serial3 2 -#define R_GEN_CONFIG__dma5__extdma0 3 -#define R_GEN_CONFIG__dma4__BITNR 14 -#define R_GEN_CONFIG__dma4__WIDTH 2 -#define R_GEN_CONFIG__dma4__par1 0 -#define R_GEN_CONFIG__dma4__scsi1 1 -#define R_GEN_CONFIG__dma4__serial3 2 -#define R_GEN_CONFIG__dma4__extdma0 3 -#define R_GEN_CONFIG__dma3__BITNR 12 -#define R_GEN_CONFIG__dma3__WIDTH 2 -#define R_GEN_CONFIG__dma3__par0 0 -#define R_GEN_CONFIG__dma3__scsi0 1 -#define R_GEN_CONFIG__dma3__serial2 2 -#define R_GEN_CONFIG__dma3__ata 3 -#define R_GEN_CONFIG__dma2__BITNR 10 -#define R_GEN_CONFIG__dma2__WIDTH 2 -#define R_GEN_CONFIG__dma2__par0 0 -#define R_GEN_CONFIG__dma2__scsi0 1 -#define R_GEN_CONFIG__dma2__serial2 2 -#define R_GEN_CONFIG__dma2__ata 3 -#define R_GEN_CONFIG__mio_w__BITNR 9 -#define R_GEN_CONFIG__mio_w__WIDTH 1 -#define R_GEN_CONFIG__mio_w__select 1 -#define R_GEN_CONFIG__mio_w__disable 0 -#define R_GEN_CONFIG__ser3__BITNR 8 -#define R_GEN_CONFIG__ser3__WIDTH 1 -#define R_GEN_CONFIG__ser3__select 1 -#define R_GEN_CONFIG__ser3__disable 0 -#define R_GEN_CONFIG__par1__BITNR 7 -#define R_GEN_CONFIG__par1__WIDTH 1 -#define R_GEN_CONFIG__par1__select 1 -#define R_GEN_CONFIG__par1__disable 0 -#define R_GEN_CONFIG__scsi0w__BITNR 6 -#define R_GEN_CONFIG__scsi0w__WIDTH 1 -#define R_GEN_CONFIG__scsi0w__select 1 -#define R_GEN_CONFIG__scsi0w__disable 0 -#define R_GEN_CONFIG__scsi1__BITNR 5 -#define R_GEN_CONFIG__scsi1__WIDTH 1 -#define R_GEN_CONFIG__scsi1__select 1 -#define R_GEN_CONFIG__scsi1__disable 0 -#define R_GEN_CONFIG__mio__BITNR 4 -#define R_GEN_CONFIG__mio__WIDTH 1 -#define R_GEN_CONFIG__mio__select 1 -#define R_GEN_CONFIG__mio__disable 0 -#define R_GEN_CONFIG__ser2__BITNR 3 -#define R_GEN_CONFIG__ser2__WIDTH 1 -#define R_GEN_CONFIG__ser2__select 1 -#define R_GEN_CONFIG__ser2__disable 0 -#define R_GEN_CONFIG__par0__BITNR 2 -#define R_GEN_CONFIG__par0__WIDTH 1 -#define R_GEN_CONFIG__par0__select 1 -#define R_GEN_CONFIG__par0__disable 0 -#define R_GEN_CONFIG__ata__BITNR 1 -#define R_GEN_CONFIG__ata__WIDTH 1 -#define R_GEN_CONFIG__ata__select 1 -#define R_GEN_CONFIG__ata__disable 0 -#define R_GEN_CONFIG__scsi0__BITNR 0 -#define R_GEN_CONFIG__scsi0__WIDTH 1 -#define R_GEN_CONFIG__scsi0__select 1 -#define R_GEN_CONFIG__scsi0__disable 0 - -#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) -#define R_GEN_CONFIG_II__sermode3__BITNR 6 -#define R_GEN_CONFIG_II__sermode3__WIDTH 1 -#define R_GEN_CONFIG_II__sermode3__async 0 -#define R_GEN_CONFIG_II__sermode3__sync 1 -#define R_GEN_CONFIG_II__sermode1__BITNR 4 -#define R_GEN_CONFIG_II__sermode1__WIDTH 1 -#define R_GEN_CONFIG_II__sermode1__async 0 -#define R_GEN_CONFIG_II__sermode1__sync 1 -#define R_GEN_CONFIG_II__ext_clk__BITNR 2 -#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 -#define R_GEN_CONFIG_II__ext_clk__select 1 -#define R_GEN_CONFIG_II__ext_clk__disable 0 -#define R_GEN_CONFIG_II__ser2__BITNR 1 -#define R_GEN_CONFIG_II__ser2__WIDTH 1 -#define R_GEN_CONFIG_II__ser2__select 1 -#define R_GEN_CONFIG_II__ser2__disable 0 -#define R_GEN_CONFIG_II__ser3__BITNR 0 -#define R_GEN_CONFIG_II__ser3__WIDTH 1 -#define R_GEN_CONFIG_II__ser3__select 1 -#define R_GEN_CONFIG_II__ser3__disable 0 - -#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) -#define R_PORT_G_DATA__data__BITNR 0 -#define R_PORT_G_DATA__data__WIDTH 32 - -/* -!* General port configuration registers -!*/ - -#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) -#define R_PORT_PA_SET__dir7__BITNR 15 -#define R_PORT_PA_SET__dir7__WIDTH 1 -#define R_PORT_PA_SET__dir7__input 0 -#define R_PORT_PA_SET__dir7__output 1 -#define R_PORT_PA_SET__dir6__BITNR 14 -#define R_PORT_PA_SET__dir6__WIDTH 1 -#define R_PORT_PA_SET__dir6__input 0 -#define R_PORT_PA_SET__dir6__output 1 -#define R_PORT_PA_SET__dir5__BITNR 13 -#define R_PORT_PA_SET__dir5__WIDTH 1 -#define R_PORT_PA_SET__dir5__input 0 -#define R_PORT_PA_SET__dir5__output 1 -#define R_PORT_PA_SET__dir4__BITNR 12 -#define R_PORT_PA_SET__dir4__WIDTH 1 -#define R_PORT_PA_SET__dir4__input 0 -#define R_PORT_PA_SET__dir4__output 1 -#define R_PORT_PA_SET__dir3__BITNR 11 -#define R_PORT_PA_SET__dir3__WIDTH 1 -#define R_PORT_PA_SET__dir3__input 0 -#define R_PORT_PA_SET__dir3__output 1 -#define R_PORT_PA_SET__dir2__BITNR 10 -#define R_PORT_PA_SET__dir2__WIDTH 1 -#define R_PORT_PA_SET__dir2__input 0 -#define R_PORT_PA_SET__dir2__output 1 -#define R_PORT_PA_SET__dir1__BITNR 9 -#define R_PORT_PA_SET__dir1__WIDTH 1 -#define R_PORT_PA_SET__dir1__input 0 -#define R_PORT_PA_SET__dir1__output 1 -#define R_PORT_PA_SET__dir0__BITNR 8 -#define R_PORT_PA_SET__dir0__WIDTH 1 -#define R_PORT_PA_SET__dir0__input 0 -#define R_PORT_PA_SET__dir0__output 1 -#define R_PORT_PA_SET__data_out__BITNR 0 -#define R_PORT_PA_SET__data_out__WIDTH 8 - -#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) -#define R_PORT_PA_DATA__data_out__BITNR 0 -#define R_PORT_PA_DATA__data_out__WIDTH 8 - -#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) -#define R_PORT_PA_DIR__dir7__BITNR 7 -#define R_PORT_PA_DIR__dir7__WIDTH 1 -#define R_PORT_PA_DIR__dir7__input 0 -#define R_PORT_PA_DIR__dir7__output 1 -#define R_PORT_PA_DIR__dir6__BITNR 6 -#define R_PORT_PA_DIR__dir6__WIDTH 1 -#define R_PORT_PA_DIR__dir6__input 0 -#define R_PORT_PA_DIR__dir6__output 1 -#define R_PORT_PA_DIR__dir5__BITNR 5 -#define R_PORT_PA_DIR__dir5__WIDTH 1 -#define R_PORT_PA_DIR__dir5__input 0 -#define R_PORT_PA_DIR__dir5__output 1 -#define R_PORT_PA_DIR__dir4__BITNR 4 -#define R_PORT_PA_DIR__dir4__WIDTH 1 -#define R_PORT_PA_DIR__dir4__input 0 -#define R_PORT_PA_DIR__dir4__output 1 -#define R_PORT_PA_DIR__dir3__BITNR 3 -#define R_PORT_PA_DIR__dir3__WIDTH 1 -#define R_PORT_PA_DIR__dir3__input 0 -#define R_PORT_PA_DIR__dir3__output 1 -#define R_PORT_PA_DIR__dir2__BITNR 2 -#define R_PORT_PA_DIR__dir2__WIDTH 1 -#define R_PORT_PA_DIR__dir2__input 0 -#define R_PORT_PA_DIR__dir2__output 1 -#define R_PORT_PA_DIR__dir1__BITNR 1 -#define R_PORT_PA_DIR__dir1__WIDTH 1 -#define R_PORT_PA_DIR__dir1__input 0 -#define R_PORT_PA_DIR__dir1__output 1 -#define R_PORT_PA_DIR__dir0__BITNR 0 -#define R_PORT_PA_DIR__dir0__WIDTH 1 -#define R_PORT_PA_DIR__dir0__input 0 -#define R_PORT_PA_DIR__dir0__output 1 - -#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) -#define R_PORT_PA_READ__data_in__BITNR 0 -#define R_PORT_PA_READ__data_in__WIDTH 8 - -#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) -#define R_PORT_PB_SET__syncser3__BITNR 29 -#define R_PORT_PB_SET__syncser3__WIDTH 1 -#define R_PORT_PB_SET__syncser3__port_cs 0 -#define R_PORT_PB_SET__syncser3__ss3extra 1 -#define R_PORT_PB_SET__syncser1__BITNR 28 -#define R_PORT_PB_SET__syncser1__WIDTH 1 -#define R_PORT_PB_SET__syncser1__port_cs 0 -#define R_PORT_PB_SET__syncser1__ss1extra 1 -#define R_PORT_PB_SET__i2c_en__BITNR 27 -#define R_PORT_PB_SET__i2c_en__WIDTH 1 -#define R_PORT_PB_SET__i2c_en__off 0 -#define R_PORT_PB_SET__i2c_en__on 1 -#define R_PORT_PB_SET__i2c_d__BITNR 26 -#define R_PORT_PB_SET__i2c_d__WIDTH 1 -#define R_PORT_PB_SET__i2c_clk__BITNR 25 -#define R_PORT_PB_SET__i2c_clk__WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___BITNR 24 -#define R_PORT_PB_SET__i2c_oe___WIDTH 1 -#define R_PORT_PB_SET__i2c_oe___enable 0 -#define R_PORT_PB_SET__i2c_oe___disable 1 -#define R_PORT_PB_SET__cs7__BITNR 23 -#define R_PORT_PB_SET__cs7__WIDTH 1 -#define R_PORT_PB_SET__cs7__port 0 -#define R_PORT_PB_SET__cs7__cs 1 -#define R_PORT_PB_SET__cs6__BITNR 22 -#define R_PORT_PB_SET__cs6__WIDTH 1 -#define R_PORT_PB_SET__cs6__port 0 -#define R_PORT_PB_SET__cs6__cs 1 -#define R_PORT_PB_SET__cs5__BITNR 21 -#define R_PORT_PB_SET__cs5__WIDTH 1 -#define R_PORT_PB_SET__cs5__port 0 -#define R_PORT_PB_SET__cs5__cs 1 -#define R_PORT_PB_SET__cs4__BITNR 20 -#define R_PORT_PB_SET__cs4__WIDTH 1 -#define R_PORT_PB_SET__cs4__port 0 -#define R_PORT_PB_SET__cs4__cs 1 -#define R_PORT_PB_SET__cs3__BITNR 19 -#define R_PORT_PB_SET__cs3__WIDTH 1 -#define R_PORT_PB_SET__cs3__port 0 -#define R_PORT_PB_SET__cs3__cs 1 -#define R_PORT_PB_SET__cs2__BITNR 18 -#define R_PORT_PB_SET__cs2__WIDTH 1 -#define R_PORT_PB_SET__cs2__port 0 -#define R_PORT_PB_SET__cs2__cs 1 -#define R_PORT_PB_SET__scsi1__BITNR 17 -#define R_PORT_PB_SET__scsi1__WIDTH 1 -#define R_PORT_PB_SET__scsi1__port_cs 0 -#define R_PORT_PB_SET__scsi1__enph 1 -#define R_PORT_PB_SET__scsi0__BITNR 16 -#define R_PORT_PB_SET__scsi0__WIDTH 1 -#define R_PORT_PB_SET__scsi0__port_cs 0 -#define R_PORT_PB_SET__scsi0__enph 1 -#define R_PORT_PB_SET__dir7__BITNR 15 -#define R_PORT_PB_SET__dir7__WIDTH 1 -#define R_PORT_PB_SET__dir7__input 0 -#define R_PORT_PB_SET__dir7__output 1 -#define R_PORT_PB_SET__dir6__BITNR 14 -#define R_PORT_PB_SET__dir6__WIDTH 1 -#define R_PORT_PB_SET__dir6__input 0 -#define R_PORT_PB_SET__dir6__output 1 -#define R_PORT_PB_SET__dir5__BITNR 13 -#define R_PORT_PB_SET__dir5__WIDTH 1 -#define R_PORT_PB_SET__dir5__input 0 -#define R_PORT_PB_SET__dir5__output 1 -#define R_PORT_PB_SET__dir4__BITNR 12 -#define R_PORT_PB_SET__dir4__WIDTH 1 -#define R_PORT_PB_SET__dir4__input 0 -#define R_PORT_PB_SET__dir4__output 1 -#define R_PORT_PB_SET__dir3__BITNR 11 -#define R_PORT_PB_SET__dir3__WIDTH 1 -#define R_PORT_PB_SET__dir3__input 0 -#define R_PORT_PB_SET__dir3__output 1 -#define R_PORT_PB_SET__dir2__BITNR 10 -#define R_PORT_PB_SET__dir2__WIDTH 1 -#define R_PORT_PB_SET__dir2__input 0 -#define R_PORT_PB_SET__dir2__output 1 -#define R_PORT_PB_SET__dir1__BITNR 9 -#define R_PORT_PB_SET__dir1__WIDTH 1 -#define R_PORT_PB_SET__dir1__input 0 -#define R_PORT_PB_SET__dir1__output 1 -#define R_PORT_PB_SET__dir0__BITNR 8 -#define R_PORT_PB_SET__dir0__WIDTH 1 -#define R_PORT_PB_SET__dir0__input 0 -#define R_PORT_PB_SET__dir0__output 1 -#define R_PORT_PB_SET__data_out__BITNR 0 -#define R_PORT_PB_SET__data_out__WIDTH 8 - -#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) -#define R_PORT_PB_DATA__data_out__BITNR 0 -#define R_PORT_PB_DATA__data_out__WIDTH 8 - -#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) -#define R_PORT_PB_DIR__dir7__BITNR 7 -#define R_PORT_PB_DIR__dir7__WIDTH 1 -#define R_PORT_PB_DIR__dir7__input 0 -#define R_PORT_PB_DIR__dir7__output 1 -#define R_PORT_PB_DIR__dir6__BITNR 6 -#define R_PORT_PB_DIR__dir6__WIDTH 1 -#define R_PORT_PB_DIR__dir6__input 0 -#define R_PORT_PB_DIR__dir6__output 1 -#define R_PORT_PB_DIR__dir5__BITNR 5 -#define R_PORT_PB_DIR__dir5__WIDTH 1 -#define R_PORT_PB_DIR__dir5__input 0 -#define R_PORT_PB_DIR__dir5__output 1 -#define R_PORT_PB_DIR__dir4__BITNR 4 -#define R_PORT_PB_DIR__dir4__WIDTH 1 -#define R_PORT_PB_DIR__dir4__input 0 -#define R_PORT_PB_DIR__dir4__output 1 -#define R_PORT_PB_DIR__dir3__BITNR 3 -#define R_PORT_PB_DIR__dir3__WIDTH 1 -#define R_PORT_PB_DIR__dir3__input 0 -#define R_PORT_PB_DIR__dir3__output 1 -#define R_PORT_PB_DIR__dir2__BITNR 2 -#define R_PORT_PB_DIR__dir2__WIDTH 1 -#define R_PORT_PB_DIR__dir2__input 0 -#define R_PORT_PB_DIR__dir2__output 1 -#define R_PORT_PB_DIR__dir1__BITNR 1 -#define R_PORT_PB_DIR__dir1__WIDTH 1 -#define R_PORT_PB_DIR__dir1__input 0 -#define R_PORT_PB_DIR__dir1__output 1 -#define R_PORT_PB_DIR__dir0__BITNR 0 -#define R_PORT_PB_DIR__dir0__WIDTH 1 -#define R_PORT_PB_DIR__dir0__input 0 -#define R_PORT_PB_DIR__dir0__output 1 - -#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) -#define R_PORT_PB_CONFIG__cs7__BITNR 7 -#define R_PORT_PB_CONFIG__cs7__WIDTH 1 -#define R_PORT_PB_CONFIG__cs7__port 0 -#define R_PORT_PB_CONFIG__cs7__cs 1 -#define R_PORT_PB_CONFIG__cs6__BITNR 6 -#define R_PORT_PB_CONFIG__cs6__WIDTH 1 -#define R_PORT_PB_CONFIG__cs6__port 0 -#define R_PORT_PB_CONFIG__cs6__cs 1 -#define R_PORT_PB_CONFIG__cs5__BITNR 5 -#define R_PORT_PB_CONFIG__cs5__WIDTH 1 -#define R_PORT_PB_CONFIG__cs5__port 0 -#define R_PORT_PB_CONFIG__cs5__cs 1 -#define R_PORT_PB_CONFIG__cs4__BITNR 4 -#define R_PORT_PB_CONFIG__cs4__WIDTH 1 -#define R_PORT_PB_CONFIG__cs4__port 0 -#define R_PORT_PB_CONFIG__cs4__cs 1 -#define R_PORT_PB_CONFIG__cs3__BITNR 3 -#define R_PORT_PB_CONFIG__cs3__WIDTH 1 -#define R_PORT_PB_CONFIG__cs3__port 0 -#define R_PORT_PB_CONFIG__cs3__cs 1 -#define R_PORT_PB_CONFIG__cs2__BITNR 2 -#define R_PORT_PB_CONFIG__cs2__WIDTH 1 -#define R_PORT_PB_CONFIG__cs2__port 0 -#define R_PORT_PB_CONFIG__cs2__cs 1 -#define R_PORT_PB_CONFIG__scsi1__BITNR 1 -#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi1__port_cs 0 -#define R_PORT_PB_CONFIG__scsi1__enph 1 -#define R_PORT_PB_CONFIG__scsi0__BITNR 0 -#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 -#define R_PORT_PB_CONFIG__scsi0__port_cs 0 -#define R_PORT_PB_CONFIG__scsi0__enph 1 - -#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) -#define R_PORT_PB_I2C__syncser3__BITNR 5 -#define R_PORT_PB_I2C__syncser3__WIDTH 1 -#define R_PORT_PB_I2C__syncser3__port_cs 0 -#define R_PORT_PB_I2C__syncser3__ss3extra 1 -#define R_PORT_PB_I2C__syncser1__BITNR 4 -#define R_PORT_PB_I2C__syncser1__WIDTH 1 -#define R_PORT_PB_I2C__syncser1__port_cs 0 -#define R_PORT_PB_I2C__syncser1__ss1extra 1 -#define R_PORT_PB_I2C__i2c_en__BITNR 3 -#define R_PORT_PB_I2C__i2c_en__WIDTH 1 -#define R_PORT_PB_I2C__i2c_en__off 0 -#define R_PORT_PB_I2C__i2c_en__on 1 -#define R_PORT_PB_I2C__i2c_d__BITNR 2 -#define R_PORT_PB_I2C__i2c_d__WIDTH 1 -#define R_PORT_PB_I2C__i2c_clk__BITNR 1 -#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___BITNR 0 -#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 -#define R_PORT_PB_I2C__i2c_oe___enable 0 -#define R_PORT_PB_I2C__i2c_oe___disable 1 - -#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) -#define R_PORT_PB_READ__data_in__BITNR 0 -#define R_PORT_PB_READ__data_in__WIDTH 8 - -/* -!* Serial port registers -!*/ - -#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) -#define R_SERIAL0_CTRL__tr_baud__BITNR 28 -#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__tr_baud__reserved 15 -#define R_SERIAL0_CTRL__rec_baud__BITNR 24 -#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL0_CTRL__rec_baud__reserved 15 -#define R_SERIAL0_CTRL__dma_err__BITNR 23 -#define R_SERIAL0_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_CTRL__dma_err__stop 0 -#define R_SERIAL0_CTRL__dma_err__ignore 1 -#define R_SERIAL0_CTRL__rec_enable__BITNR 22 -#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_CTRL__rec_enable__disable 0 -#define R_SERIAL0_CTRL__rec_enable__enable 1 -#define R_SERIAL0_CTRL__rts___BITNR 21 -#define R_SERIAL0_CTRL__rts___WIDTH 1 -#define R_SERIAL0_CTRL__rts___active 0 -#define R_SERIAL0_CTRL__rts___inactive 1 -#define R_SERIAL0_CTRL__sampling__BITNR 20 -#define R_SERIAL0_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_CTRL__sampling__middle 0 -#define R_SERIAL0_CTRL__sampling__majority 1 -#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_CTRL__rec_par__BITNR 18 -#define R_SERIAL0_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par__even 0 -#define R_SERIAL0_CTRL__rec_par__odd 1 -#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL0_CTRL__txd__BITNR 15 -#define R_SERIAL0_CTRL__txd__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__BITNR 14 -#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_CTRL__tr_enable__disable 0 -#define R_SERIAL0_CTRL__tr_enable__enable 1 -#define R_SERIAL0_CTRL__auto_cts__BITNR 13 -#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_CTRL__auto_cts__active 1 -#define R_SERIAL0_CTRL__stop_bits__BITNR 12 -#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_CTRL__tr_par__BITNR 10 -#define R_SERIAL0_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par__even 0 -#define R_SERIAL0_CTRL__tr_par__odd 1 -#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL0_CTRL__data_out__BITNR 0 -#define R_SERIAL0_CTRL__data_out__WIDTH 8 - -#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) -#define R_SERIAL0_BAUD__tr_baud__BITNR 4 -#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__tr_baud__reserved 15 -#define R_SERIAL0_BAUD__rec_baud__BITNR 0 -#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL0_BAUD__rec_baud__reserved 15 - -#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) -#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL0_REC_CTRL__dma_err__stop 0 -#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL0_REC_CTRL__rts___BITNR 5 -#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL0_REC_CTRL__rts___active 0 -#define R_SERIAL0_REC_CTRL__rts___inactive 1 -#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL0_REC_CTRL__sampling__middle 0 -#define R_SERIAL0_REC_CTRL__sampling__majority 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par__even 0 -#define R_SERIAL0_REC_CTRL__rec_par__odd 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) -#define R_SERIAL0_TR_CTRL__txd__BITNR 7 -#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL0_TR_CTRL__auto_cts__active 1 -#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par__even 0 -#define R_SERIAL0_TR_CTRL__tr_par__odd 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) -#define R_SERIAL0_TR_DATA__data_out__BITNR 0 -#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) -#define R_SERIAL0_READ__xoff_detect__BITNR 15 -#define R_SERIAL0_READ__xoff_detect__WIDTH 1 -#define R_SERIAL0_READ__xoff_detect__no_xoff 0 -#define R_SERIAL0_READ__xoff_detect__xoff 1 -#define R_SERIAL0_READ__cts___BITNR 14 -#define R_SERIAL0_READ__cts___WIDTH 1 -#define R_SERIAL0_READ__cts___active 0 -#define R_SERIAL0_READ__cts___inactive 1 -#define R_SERIAL0_READ__tr_ready__BITNR 13 -#define R_SERIAL0_READ__tr_ready__WIDTH 1 -#define R_SERIAL0_READ__tr_ready__full 0 -#define R_SERIAL0_READ__tr_ready__ready 1 -#define R_SERIAL0_READ__rxd__BITNR 12 -#define R_SERIAL0_READ__rxd__WIDTH 1 -#define R_SERIAL0_READ__overrun__BITNR 11 -#define R_SERIAL0_READ__overrun__WIDTH 1 -#define R_SERIAL0_READ__overrun__no 0 -#define R_SERIAL0_READ__overrun__yes 1 -#define R_SERIAL0_READ__par_err__BITNR 10 -#define R_SERIAL0_READ__par_err__WIDTH 1 -#define R_SERIAL0_READ__par_err__no 0 -#define R_SERIAL0_READ__par_err__yes 1 -#define R_SERIAL0_READ__framing_err__BITNR 9 -#define R_SERIAL0_READ__framing_err__WIDTH 1 -#define R_SERIAL0_READ__framing_err__no 0 -#define R_SERIAL0_READ__framing_err__yes 1 -#define R_SERIAL0_READ__data_avail__BITNR 8 -#define R_SERIAL0_READ__data_avail__WIDTH 1 -#define R_SERIAL0_READ__data_avail__no 0 -#define R_SERIAL0_READ__data_avail__yes 1 -#define R_SERIAL0_READ__data_in__BITNR 0 -#define R_SERIAL0_READ__data_in__WIDTH 8 - -#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) -#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL0_STATUS__xoff_detect__xoff 1 -#define R_SERIAL0_STATUS__cts___BITNR 6 -#define R_SERIAL0_STATUS__cts___WIDTH 1 -#define R_SERIAL0_STATUS__cts___active 0 -#define R_SERIAL0_STATUS__cts___inactive 1 -#define R_SERIAL0_STATUS__tr_ready__BITNR 5 -#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL0_STATUS__tr_ready__full 0 -#define R_SERIAL0_STATUS__tr_ready__ready 1 -#define R_SERIAL0_STATUS__rxd__BITNR 4 -#define R_SERIAL0_STATUS__rxd__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__BITNR 3 -#define R_SERIAL0_STATUS__overrun__WIDTH 1 -#define R_SERIAL0_STATUS__overrun__no 0 -#define R_SERIAL0_STATUS__overrun__yes 1 -#define R_SERIAL0_STATUS__par_err__BITNR 2 -#define R_SERIAL0_STATUS__par_err__WIDTH 1 -#define R_SERIAL0_STATUS__par_err__no 0 -#define R_SERIAL0_STATUS__par_err__yes 1 -#define R_SERIAL0_STATUS__framing_err__BITNR 1 -#define R_SERIAL0_STATUS__framing_err__WIDTH 1 -#define R_SERIAL0_STATUS__framing_err__no 0 -#define R_SERIAL0_STATUS__framing_err__yes 1 -#define R_SERIAL0_STATUS__data_avail__BITNR 0 -#define R_SERIAL0_STATUS__data_avail__WIDTH 1 -#define R_SERIAL0_STATUS__data_avail__no 0 -#define R_SERIAL0_STATUS__data_avail__yes 1 - -#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) -#define R_SERIAL0_REC_DATA__data_in__BITNR 0 -#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) -#define R_SERIAL0_XOFF__tx_stop__BITNR 9 -#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL0_XOFF__tx_stop__enable 0 -#define R_SERIAL0_XOFF__tx_stop__stop 1 -#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL0_XOFF__auto_xoff__disable 0 -#define R_SERIAL0_XOFF__auto_xoff__enable 1 -#define R_SERIAL0_XOFF__xoff_char__BITNR 0 -#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SERIAL1_CTRL__rec_baud__BITNR 24 -#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL1_CTRL__rec_baud__reserved 15 -#define R_SERIAL1_CTRL__dma_err__BITNR 23 -#define R_SERIAL1_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_CTRL__dma_err__stop 0 -#define R_SERIAL1_CTRL__dma_err__ignore 1 -#define R_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SERIAL1_CTRL__rts___BITNR 21 -#define R_SERIAL1_CTRL__rts___WIDTH 1 -#define R_SERIAL1_CTRL__rts___active 0 -#define R_SERIAL1_CTRL__rts___inactive 1 -#define R_SERIAL1_CTRL__sampling__BITNR 20 -#define R_SERIAL1_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_CTRL__sampling__middle 0 -#define R_SERIAL1_CTRL__sampling__majority 1 -#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_CTRL__rec_par__BITNR 18 -#define R_SERIAL1_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par__even 0 -#define R_SERIAL1_CTRL__rec_par__odd 1 -#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL1_CTRL__txd__BITNR 15 -#define R_SERIAL1_CTRL__txd__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SERIAL1_CTRL__auto_cts__BITNR 13 -#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_CTRL__auto_cts__active 1 -#define R_SERIAL1_CTRL__stop_bits__BITNR 12 -#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_CTRL__tr_par__BITNR 10 -#define R_SERIAL1_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par__even 0 -#define R_SERIAL1_CTRL__tr_par__odd 1 -#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL1_CTRL__data_out__BITNR 0 -#define R_SERIAL1_CTRL__data_out__WIDTH 8 - -#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) -#define R_SERIAL1_BAUD__tr_baud__BITNR 4 -#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__tr_baud__reserved 15 -#define R_SERIAL1_BAUD__rec_baud__BITNR 0 -#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL1_BAUD__rec_baud__reserved 15 - -#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) -#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL1_REC_CTRL__dma_err__stop 0 -#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL1_REC_CTRL__rts___BITNR 5 -#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL1_REC_CTRL__rts___active 0 -#define R_SERIAL1_REC_CTRL__rts___inactive 1 -#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL1_REC_CTRL__sampling__middle 0 -#define R_SERIAL1_REC_CTRL__sampling__majority 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par__even 0 -#define R_SERIAL1_REC_CTRL__rec_par__odd 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) -#define R_SERIAL1_TR_CTRL__txd__BITNR 7 -#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL1_TR_CTRL__auto_cts__active 1 -#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par__even 0 -#define R_SERIAL1_TR_CTRL__tr_par__odd 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) -#define R_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SERIAL1_READ__xoff_detect__BITNR 15 -#define R_SERIAL1_READ__xoff_detect__WIDTH 1 -#define R_SERIAL1_READ__xoff_detect__no_xoff 0 -#define R_SERIAL1_READ__xoff_detect__xoff 1 -#define R_SERIAL1_READ__cts___BITNR 14 -#define R_SERIAL1_READ__cts___WIDTH 1 -#define R_SERIAL1_READ__cts___active 0 -#define R_SERIAL1_READ__cts___inactive 1 -#define R_SERIAL1_READ__tr_ready__BITNR 13 -#define R_SERIAL1_READ__tr_ready__WIDTH 1 -#define R_SERIAL1_READ__tr_ready__full 0 -#define R_SERIAL1_READ__tr_ready__ready 1 -#define R_SERIAL1_READ__rxd__BITNR 12 -#define R_SERIAL1_READ__rxd__WIDTH 1 -#define R_SERIAL1_READ__overrun__BITNR 11 -#define R_SERIAL1_READ__overrun__WIDTH 1 -#define R_SERIAL1_READ__overrun__no 0 -#define R_SERIAL1_READ__overrun__yes 1 -#define R_SERIAL1_READ__par_err__BITNR 10 -#define R_SERIAL1_READ__par_err__WIDTH 1 -#define R_SERIAL1_READ__par_err__no 0 -#define R_SERIAL1_READ__par_err__yes 1 -#define R_SERIAL1_READ__framing_err__BITNR 9 -#define R_SERIAL1_READ__framing_err__WIDTH 1 -#define R_SERIAL1_READ__framing_err__no 0 -#define R_SERIAL1_READ__framing_err__yes 1 -#define R_SERIAL1_READ__data_avail__BITNR 8 -#define R_SERIAL1_READ__data_avail__WIDTH 1 -#define R_SERIAL1_READ__data_avail__no 0 -#define R_SERIAL1_READ__data_avail__yes 1 -#define R_SERIAL1_READ__data_in__BITNR 0 -#define R_SERIAL1_READ__data_in__WIDTH 8 - -#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) -#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL1_STATUS__xoff_detect__xoff 1 -#define R_SERIAL1_STATUS__cts___BITNR 6 -#define R_SERIAL1_STATUS__cts___WIDTH 1 -#define R_SERIAL1_STATUS__cts___active 0 -#define R_SERIAL1_STATUS__cts___inactive 1 -#define R_SERIAL1_STATUS__tr_ready__BITNR 5 -#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL1_STATUS__tr_ready__full 0 -#define R_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SERIAL1_STATUS__rxd__BITNR 4 -#define R_SERIAL1_STATUS__rxd__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__BITNR 3 -#define R_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SERIAL1_STATUS__overrun__no 0 -#define R_SERIAL1_STATUS__overrun__yes 1 -#define R_SERIAL1_STATUS__par_err__BITNR 2 -#define R_SERIAL1_STATUS__par_err__WIDTH 1 -#define R_SERIAL1_STATUS__par_err__no 0 -#define R_SERIAL1_STATUS__par_err__yes 1 -#define R_SERIAL1_STATUS__framing_err__BITNR 1 -#define R_SERIAL1_STATUS__framing_err__WIDTH 1 -#define R_SERIAL1_STATUS__framing_err__no 0 -#define R_SERIAL1_STATUS__framing_err__yes 1 -#define R_SERIAL1_STATUS__data_avail__BITNR 0 -#define R_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SERIAL1_STATUS__data_avail__no 0 -#define R_SERIAL1_STATUS__data_avail__yes 1 - -#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) -#define R_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SERIAL1_XOFF__tx_stop__BITNR 9 -#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL1_XOFF__tx_stop__enable 0 -#define R_SERIAL1_XOFF__tx_stop__stop 1 -#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL1_XOFF__auto_xoff__disable 0 -#define R_SERIAL1_XOFF__auto_xoff__enable 1 -#define R_SERIAL1_XOFF__xoff_char__BITNR 0 -#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) -#define R_SERIAL2_CTRL__tr_baud__BITNR 28 -#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__tr_baud__reserved 15 -#define R_SERIAL2_CTRL__rec_baud__BITNR 24 -#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL2_CTRL__rec_baud__reserved 15 -#define R_SERIAL2_CTRL__dma_err__BITNR 23 -#define R_SERIAL2_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_CTRL__dma_err__stop 0 -#define R_SERIAL2_CTRL__dma_err__ignore 1 -#define R_SERIAL2_CTRL__rec_enable__BITNR 22 -#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_CTRL__rec_enable__disable 0 -#define R_SERIAL2_CTRL__rec_enable__enable 1 -#define R_SERIAL2_CTRL__rts___BITNR 21 -#define R_SERIAL2_CTRL__rts___WIDTH 1 -#define R_SERIAL2_CTRL__rts___active 0 -#define R_SERIAL2_CTRL__rts___inactive 1 -#define R_SERIAL2_CTRL__sampling__BITNR 20 -#define R_SERIAL2_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_CTRL__sampling__middle 0 -#define R_SERIAL2_CTRL__sampling__majority 1 -#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_CTRL__rec_par__BITNR 18 -#define R_SERIAL2_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par__even 0 -#define R_SERIAL2_CTRL__rec_par__odd 1 -#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL2_CTRL__txd__BITNR 15 -#define R_SERIAL2_CTRL__txd__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__BITNR 14 -#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_CTRL__tr_enable__disable 0 -#define R_SERIAL2_CTRL__tr_enable__enable 1 -#define R_SERIAL2_CTRL__auto_cts__BITNR 13 -#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_CTRL__auto_cts__active 1 -#define R_SERIAL2_CTRL__stop_bits__BITNR 12 -#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_CTRL__tr_par__BITNR 10 -#define R_SERIAL2_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par__even 0 -#define R_SERIAL2_CTRL__tr_par__odd 1 -#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL2_CTRL__data_out__BITNR 0 -#define R_SERIAL2_CTRL__data_out__WIDTH 8 - -#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) -#define R_SERIAL2_BAUD__tr_baud__BITNR 4 -#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__tr_baud__reserved 15 -#define R_SERIAL2_BAUD__rec_baud__BITNR 0 -#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL2_BAUD__rec_baud__reserved 15 - -#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) -#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL2_REC_CTRL__dma_err__stop 0 -#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL2_REC_CTRL__rts___BITNR 5 -#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL2_REC_CTRL__rts___active 0 -#define R_SERIAL2_REC_CTRL__rts___inactive 1 -#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL2_REC_CTRL__sampling__middle 0 -#define R_SERIAL2_REC_CTRL__sampling__majority 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par__even 0 -#define R_SERIAL2_REC_CTRL__rec_par__odd 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) -#define R_SERIAL2_TR_CTRL__txd__BITNR 7 -#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL2_TR_CTRL__auto_cts__active 1 -#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par__even 0 -#define R_SERIAL2_TR_CTRL__tr_par__odd 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) -#define R_SERIAL2_TR_DATA__data_out__BITNR 0 -#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) -#define R_SERIAL2_READ__xoff_detect__BITNR 15 -#define R_SERIAL2_READ__xoff_detect__WIDTH 1 -#define R_SERIAL2_READ__xoff_detect__no_xoff 0 -#define R_SERIAL2_READ__xoff_detect__xoff 1 -#define R_SERIAL2_READ__cts___BITNR 14 -#define R_SERIAL2_READ__cts___WIDTH 1 -#define R_SERIAL2_READ__cts___active 0 -#define R_SERIAL2_READ__cts___inactive 1 -#define R_SERIAL2_READ__tr_ready__BITNR 13 -#define R_SERIAL2_READ__tr_ready__WIDTH 1 -#define R_SERIAL2_READ__tr_ready__full 0 -#define R_SERIAL2_READ__tr_ready__ready 1 -#define R_SERIAL2_READ__rxd__BITNR 12 -#define R_SERIAL2_READ__rxd__WIDTH 1 -#define R_SERIAL2_READ__overrun__BITNR 11 -#define R_SERIAL2_READ__overrun__WIDTH 1 -#define R_SERIAL2_READ__overrun__no 0 -#define R_SERIAL2_READ__overrun__yes 1 -#define R_SERIAL2_READ__par_err__BITNR 10 -#define R_SERIAL2_READ__par_err__WIDTH 1 -#define R_SERIAL2_READ__par_err__no 0 -#define R_SERIAL2_READ__par_err__yes 1 -#define R_SERIAL2_READ__framing_err__BITNR 9 -#define R_SERIAL2_READ__framing_err__WIDTH 1 -#define R_SERIAL2_READ__framing_err__no 0 -#define R_SERIAL2_READ__framing_err__yes 1 -#define R_SERIAL2_READ__data_avail__BITNR 8 -#define R_SERIAL2_READ__data_avail__WIDTH 1 -#define R_SERIAL2_READ__data_avail__no 0 -#define R_SERIAL2_READ__data_avail__yes 1 -#define R_SERIAL2_READ__data_in__BITNR 0 -#define R_SERIAL2_READ__data_in__WIDTH 8 - -#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) -#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL2_STATUS__xoff_detect__xoff 1 -#define R_SERIAL2_STATUS__cts___BITNR 6 -#define R_SERIAL2_STATUS__cts___WIDTH 1 -#define R_SERIAL2_STATUS__cts___active 0 -#define R_SERIAL2_STATUS__cts___inactive 1 -#define R_SERIAL2_STATUS__tr_ready__BITNR 5 -#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL2_STATUS__tr_ready__full 0 -#define R_SERIAL2_STATUS__tr_ready__ready 1 -#define R_SERIAL2_STATUS__rxd__BITNR 4 -#define R_SERIAL2_STATUS__rxd__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__BITNR 3 -#define R_SERIAL2_STATUS__overrun__WIDTH 1 -#define R_SERIAL2_STATUS__overrun__no 0 -#define R_SERIAL2_STATUS__overrun__yes 1 -#define R_SERIAL2_STATUS__par_err__BITNR 2 -#define R_SERIAL2_STATUS__par_err__WIDTH 1 -#define R_SERIAL2_STATUS__par_err__no 0 -#define R_SERIAL2_STATUS__par_err__yes 1 -#define R_SERIAL2_STATUS__framing_err__BITNR 1 -#define R_SERIAL2_STATUS__framing_err__WIDTH 1 -#define R_SERIAL2_STATUS__framing_err__no 0 -#define R_SERIAL2_STATUS__framing_err__yes 1 -#define R_SERIAL2_STATUS__data_avail__BITNR 0 -#define R_SERIAL2_STATUS__data_avail__WIDTH 1 -#define R_SERIAL2_STATUS__data_avail__no 0 -#define R_SERIAL2_STATUS__data_avail__yes 1 - -#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) -#define R_SERIAL2_REC_DATA__data_in__BITNR 0 -#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) -#define R_SERIAL2_XOFF__tx_stop__BITNR 9 -#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL2_XOFF__tx_stop__enable 0 -#define R_SERIAL2_XOFF__tx_stop__stop 1 -#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL2_XOFF__auto_xoff__disable 0 -#define R_SERIAL2_XOFF__auto_xoff__enable 1 -#define R_SERIAL2_XOFF__xoff_char__BITNR 0 -#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 - -#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 -#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 -#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SERIAL3_CTRL__rec_baud__BITNR 24 -#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 -#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 -#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 -#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 -#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 -#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 -#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 -#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 -#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 -#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 -#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 -#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 -#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 -#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 -#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 -#define R_SERIAL3_CTRL__rec_baud__reserved 15 -#define R_SERIAL3_CTRL__dma_err__BITNR 23 -#define R_SERIAL3_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_CTRL__dma_err__stop 0 -#define R_SERIAL3_CTRL__dma_err__ignore 1 -#define R_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SERIAL3_CTRL__rts___BITNR 21 -#define R_SERIAL3_CTRL__rts___WIDTH 1 -#define R_SERIAL3_CTRL__rts___active 0 -#define R_SERIAL3_CTRL__rts___inactive 1 -#define R_SERIAL3_CTRL__sampling__BITNR 20 -#define R_SERIAL3_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_CTRL__sampling__middle 0 -#define R_SERIAL3_CTRL__sampling__majority 1 -#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 -#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_CTRL__rec_par__BITNR 18 -#define R_SERIAL3_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par__even 0 -#define R_SERIAL3_CTRL__rec_par__odd 1 -#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 -#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 -#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 -#define R_SERIAL3_CTRL__txd__BITNR 15 -#define R_SERIAL3_CTRL__txd__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SERIAL3_CTRL__auto_cts__BITNR 13 -#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_CTRL__auto_cts__active 1 -#define R_SERIAL3_CTRL__stop_bits__BITNR 12 -#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 -#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_CTRL__tr_par__BITNR 10 -#define R_SERIAL3_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par__even 0 -#define R_SERIAL3_CTRL__tr_par__odd 1 -#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 -#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 -#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 -#define R_SERIAL3_CTRL__data_out__BITNR 0 -#define R_SERIAL3_CTRL__data_out__WIDTH 8 - -#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) -#define R_SERIAL3_BAUD__tr_baud__BITNR 4 -#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 -#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 -#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 -#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__tr_baud__reserved 15 -#define R_SERIAL3_BAUD__rec_baud__BITNR 0 -#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 -#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 -#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 -#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 -#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 -#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 -#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 -#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 -#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 -#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 -#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 -#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 -#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 -#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 -#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 -#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 -#define R_SERIAL3_BAUD__rec_baud__reserved 15 - -#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) -#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 -#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 -#define R_SERIAL3_REC_CTRL__dma_err__stop 0 -#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 -#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 -#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 -#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 -#define R_SERIAL3_REC_CTRL__rts___BITNR 5 -#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 -#define R_SERIAL3_REC_CTRL__rts___active 0 -#define R_SERIAL3_REC_CTRL__rts___inactive 1 -#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 -#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 -#define R_SERIAL3_REC_CTRL__sampling__middle 0 -#define R_SERIAL3_REC_CTRL__sampling__majority 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 -#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 -#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 -#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 -#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par__even 0 -#define R_SERIAL3_REC_CTRL__rec_par__odd 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 -#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 -#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 - -#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) -#define R_SERIAL3_TR_CTRL__txd__BITNR 7 -#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 -#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 -#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 -#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 -#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 -#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 -#define R_SERIAL3_TR_CTRL__auto_cts__active 1 -#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 -#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 -#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 -#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 -#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 -#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 -#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 -#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par__even 0 -#define R_SERIAL3_TR_CTRL__tr_par__odd 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 -#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 -#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 - -#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) -#define R_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 - -#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SERIAL3_READ__xoff_detect__BITNR 15 -#define R_SERIAL3_READ__xoff_detect__WIDTH 1 -#define R_SERIAL3_READ__xoff_detect__no_xoff 0 -#define R_SERIAL3_READ__xoff_detect__xoff 1 -#define R_SERIAL3_READ__cts___BITNR 14 -#define R_SERIAL3_READ__cts___WIDTH 1 -#define R_SERIAL3_READ__cts___active 0 -#define R_SERIAL3_READ__cts___inactive 1 -#define R_SERIAL3_READ__tr_ready__BITNR 13 -#define R_SERIAL3_READ__tr_ready__WIDTH 1 -#define R_SERIAL3_READ__tr_ready__full 0 -#define R_SERIAL3_READ__tr_ready__ready 1 -#define R_SERIAL3_READ__rxd__BITNR 12 -#define R_SERIAL3_READ__rxd__WIDTH 1 -#define R_SERIAL3_READ__overrun__BITNR 11 -#define R_SERIAL3_READ__overrun__WIDTH 1 -#define R_SERIAL3_READ__overrun__no 0 -#define R_SERIAL3_READ__overrun__yes 1 -#define R_SERIAL3_READ__par_err__BITNR 10 -#define R_SERIAL3_READ__par_err__WIDTH 1 -#define R_SERIAL3_READ__par_err__no 0 -#define R_SERIAL3_READ__par_err__yes 1 -#define R_SERIAL3_READ__framing_err__BITNR 9 -#define R_SERIAL3_READ__framing_err__WIDTH 1 -#define R_SERIAL3_READ__framing_err__no 0 -#define R_SERIAL3_READ__framing_err__yes 1 -#define R_SERIAL3_READ__data_avail__BITNR 8 -#define R_SERIAL3_READ__data_avail__WIDTH 1 -#define R_SERIAL3_READ__data_avail__no 0 -#define R_SERIAL3_READ__data_avail__yes 1 -#define R_SERIAL3_READ__data_in__BITNR 0 -#define R_SERIAL3_READ__data_in__WIDTH 8 - -#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) -#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 -#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 -#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 -#define R_SERIAL3_STATUS__xoff_detect__xoff 1 -#define R_SERIAL3_STATUS__cts___BITNR 6 -#define R_SERIAL3_STATUS__cts___WIDTH 1 -#define R_SERIAL3_STATUS__cts___active 0 -#define R_SERIAL3_STATUS__cts___inactive 1 -#define R_SERIAL3_STATUS__tr_ready__BITNR 5 -#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SERIAL3_STATUS__tr_ready__full 0 -#define R_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SERIAL3_STATUS__rxd__BITNR 4 -#define R_SERIAL3_STATUS__rxd__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__BITNR 3 -#define R_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SERIAL3_STATUS__overrun__no 0 -#define R_SERIAL3_STATUS__overrun__yes 1 -#define R_SERIAL3_STATUS__par_err__BITNR 2 -#define R_SERIAL3_STATUS__par_err__WIDTH 1 -#define R_SERIAL3_STATUS__par_err__no 0 -#define R_SERIAL3_STATUS__par_err__yes 1 -#define R_SERIAL3_STATUS__framing_err__BITNR 1 -#define R_SERIAL3_STATUS__framing_err__WIDTH 1 -#define R_SERIAL3_STATUS__framing_err__no 0 -#define R_SERIAL3_STATUS__framing_err__yes 1 -#define R_SERIAL3_STATUS__data_avail__BITNR 0 -#define R_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SERIAL3_STATUS__data_avail__no 0 -#define R_SERIAL3_STATUS__data_avail__yes 1 - -#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) -#define R_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 - -#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SERIAL3_XOFF__tx_stop__BITNR 9 -#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 -#define R_SERIAL3_XOFF__tx_stop__enable 0 -#define R_SERIAL3_XOFF__tx_stop__stop 1 -#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 -#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 -#define R_SERIAL3_XOFF__auto_xoff__disable 0 -#define R_SERIAL3_XOFF__auto_xoff__enable 1 -#define R_SERIAL3_XOFF__xoff_char__BITNR 0 -#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 - -#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) -#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 -#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 -#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 -#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 -#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 -#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 -#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 -#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 -#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 -#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 -#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 -#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 - -/* -!* Network interface registers -!*/ - -#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) -#define R_NETWORK_SA_0__ma0_low__BITNR 0 -#define R_NETWORK_SA_0__ma0_low__WIDTH 32 - -#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) -#define R_NETWORK_SA_1__ma1_low__BITNR 16 -#define R_NETWORK_SA_1__ma1_low__WIDTH 16 -#define R_NETWORK_SA_1__ma0_high__BITNR 0 -#define R_NETWORK_SA_1__ma0_high__WIDTH 16 - -#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) -#define R_NETWORK_SA_2__ma1_high__BITNR 0 -#define R_NETWORK_SA_2__ma1_high__WIDTH 32 - -#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) -#define R_NETWORK_GA_0__ga_low__BITNR 0 -#define R_NETWORK_GA_0__ga_low__WIDTH 32 - -#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) -#define R_NETWORK_GA_1__ga_high__BITNR 0 -#define R_NETWORK_GA_1__ga_high__WIDTH 32 - -#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) -#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 -#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 -#define R_NETWORK_REC_CONFIG__max_size__size1518 0 -#define R_NETWORK_REC_CONFIG__max_size__size1522 1 -#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 -#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 -#define R_NETWORK_REC_CONFIG__duplex__full 1 -#define R_NETWORK_REC_CONFIG__duplex__half 0 -#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 -#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 -#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 -#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 -#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 -#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__oversize__receive 1 -#define R_NETWORK_REC_CONFIG__oversize__discard 0 -#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 -#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 -#define R_NETWORK_REC_CONFIG__undersize__receive 1 -#define R_NETWORK_REC_CONFIG__undersize__discard 0 -#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 -#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 -#define R_NETWORK_REC_CONFIG__all_roots__receive 1 -#define R_NETWORK_REC_CONFIG__all_roots__discard 0 -#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 -#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 -#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 -#define R_NETWORK_REC_CONFIG__broadcast__receive 1 -#define R_NETWORK_REC_CONFIG__broadcast__discard 0 -#define R_NETWORK_REC_CONFIG__individual__BITNR 2 -#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 -#define R_NETWORK_REC_CONFIG__individual__receive 1 -#define R_NETWORK_REC_CONFIG__individual__discard 0 -#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 -#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma1__enable 1 -#define R_NETWORK_REC_CONFIG__ma1__disable 0 -#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 -#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 -#define R_NETWORK_REC_CONFIG__ma0__enable 1 -#define R_NETWORK_REC_CONFIG__ma0__disable 0 - -#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) -#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 -#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__loopback__on 1 -#define R_NETWORK_GEN_CONFIG__loopback__off 0 -#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 -#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 -#define R_NETWORK_GEN_CONFIG__frame__ether 0 -#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 -#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__vg__on 1 -#define R_NETWORK_GEN_CONFIG__vg__off 0 -#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 -#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 -#define R_NETWORK_GEN_CONFIG__phy__sni 0 -#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 -#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 -#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 -#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 -#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 -#define R_NETWORK_GEN_CONFIG__enable__on 1 -#define R_NETWORK_GEN_CONFIG__enable__off 0 - -#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) -#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 -#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 -#define R_NETWORK_TR_CTRL__clr_error__clr 1 -#define R_NETWORK_TR_CTRL__clr_error__nop 0 -#define R_NETWORK_TR_CTRL__delay__BITNR 5 -#define R_NETWORK_TR_CTRL__delay__WIDTH 1 -#define R_NETWORK_TR_CTRL__delay__d2us 1 -#define R_NETWORK_TR_CTRL__delay__none 0 -#define R_NETWORK_TR_CTRL__cancel__BITNR 4 -#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 -#define R_NETWORK_TR_CTRL__cancel__do 1 -#define R_NETWORK_TR_CTRL__cancel__dont 0 -#define R_NETWORK_TR_CTRL__cd__BITNR 3 -#define R_NETWORK_TR_CTRL__cd__WIDTH 1 -#define R_NETWORK_TR_CTRL__cd__enable 0 -#define R_NETWORK_TR_CTRL__cd__disable 1 -#define R_NETWORK_TR_CTRL__cd__ack_col 0 -#define R_NETWORK_TR_CTRL__cd__ack_crs 1 -#define R_NETWORK_TR_CTRL__retry__BITNR 2 -#define R_NETWORK_TR_CTRL__retry__WIDTH 1 -#define R_NETWORK_TR_CTRL__retry__enable 0 -#define R_NETWORK_TR_CTRL__retry__disable 1 -#define R_NETWORK_TR_CTRL__pad__BITNR 1 -#define R_NETWORK_TR_CTRL__pad__WIDTH 1 -#define R_NETWORK_TR_CTRL__pad__enable 1 -#define R_NETWORK_TR_CTRL__pad__disable 0 -#define R_NETWORK_TR_CTRL__crc__BITNR 0 -#define R_NETWORK_TR_CTRL__crc__WIDTH 1 -#define R_NETWORK_TR_CTRL__crc__enable 0 -#define R_NETWORK_TR_CTRL__crc__disable 1 - -#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) -#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 -#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 -#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 -#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 -#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 -#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 -#define R_NETWORK_MGM_CTRL__mdoe__enable 1 -#define R_NETWORK_MGM_CTRL__mdoe__disable 0 -#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 -#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 - -#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) -#define R_NETWORK_STAT__rxd_pins__BITNR 4 -#define R_NETWORK_STAT__rxd_pins__WIDTH 4 -#define R_NETWORK_STAT__rxer__BITNR 3 -#define R_NETWORK_STAT__rxer__WIDTH 1 -#define R_NETWORK_STAT__underrun__BITNR 2 -#define R_NETWORK_STAT__underrun__WIDTH 1 -#define R_NETWORK_STAT__underrun__yes 1 -#define R_NETWORK_STAT__underrun__no 0 -#define R_NETWORK_STAT__exc_col__BITNR 1 -#define R_NETWORK_STAT__exc_col__WIDTH 1 -#define R_NETWORK_STAT__exc_col__yes 1 -#define R_NETWORK_STAT__exc_col__no 0 -#define R_NETWORK_STAT__mdio__BITNR 0 -#define R_NETWORK_STAT__mdio__WIDTH 1 - -#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) -#define R_REC_COUNTERS__congestion__BITNR 24 -#define R_REC_COUNTERS__congestion__WIDTH 8 -#define R_REC_COUNTERS__oversize__BITNR 16 -#define R_REC_COUNTERS__oversize__WIDTH 8 -#define R_REC_COUNTERS__alignment_error__BITNR 8 -#define R_REC_COUNTERS__alignment_error__WIDTH 8 -#define R_REC_COUNTERS__crc_error__BITNR 0 -#define R_REC_COUNTERS__crc_error__WIDTH 8 - -#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) -#define R_TR_COUNTERS__deferred__BITNR 24 -#define R_TR_COUNTERS__deferred__WIDTH 8 -#define R_TR_COUNTERS__late_col__BITNR 16 -#define R_TR_COUNTERS__late_col__WIDTH 8 -#define R_TR_COUNTERS__multiple_col__BITNR 8 -#define R_TR_COUNTERS__multiple_col__WIDTH 8 -#define R_TR_COUNTERS__single_col__BITNR 0 -#define R_TR_COUNTERS__single_col__WIDTH 8 - -#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) -#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 -#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 -#define R_PHY_COUNTERS__carrier_loss__BITNR 0 -#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 - -/* -!* Parallel printer port registers -!*/ - -#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR0_CTRL_DATA__peri_int__ack 1 -#define R_PAR0_CTRL_DATA__peri_int__nop 0 -#define R_PAR0_CTRL_DATA__oe__BITNR 20 -#define R_PAR0_CTRL_DATA__oe__WIDTH 1 -#define R_PAR0_CTRL_DATA__oe__enable 1 -#define R_PAR0_CTRL_DATA__oe__disable 0 -#define R_PAR0_CTRL_DATA__seli__BITNR 19 -#define R_PAR0_CTRL_DATA__seli__WIDTH 1 -#define R_PAR0_CTRL_DATA__seli__active 1 -#define R_PAR0_CTRL_DATA__seli__inactive 0 -#define R_PAR0_CTRL_DATA__autofd__BITNR 18 -#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR0_CTRL_DATA__autofd__active 1 -#define R_PAR0_CTRL_DATA__autofd__inactive 0 -#define R_PAR0_CTRL_DATA__strb__BITNR 17 -#define R_PAR0_CTRL_DATA__strb__WIDTH 1 -#define R_PAR0_CTRL_DATA__strb__active 1 -#define R_PAR0_CTRL_DATA__strb__inactive 0 -#define R_PAR0_CTRL_DATA__init__BITNR 16 -#define R_PAR0_CTRL_DATA__init__WIDTH 1 -#define R_PAR0_CTRL_DATA__init__active 1 -#define R_PAR0_CTRL_DATA__init__inactive 0 -#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR0_CTRL_DATA__data__BITNR 0 -#define R_PAR0_CTRL_DATA__data__WIDTH 8 - -#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) -#define R_PAR0_CTRL__ctrl__BITNR 0 -#define R_PAR0_CTRL__ctrl__WIDTH 5 - -#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_PAR0_STATUS_DATA__mode__BITNR 29 -#define R_PAR0_STATUS_DATA__mode__WIDTH 3 -#define R_PAR0_STATUS_DATA__mode__manual 0 -#define R_PAR0_STATUS_DATA__mode__centronics 1 -#define R_PAR0_STATUS_DATA__mode__fastbyte 2 -#define R_PAR0_STATUS_DATA__mode__nibble 3 -#define R_PAR0_STATUS_DATA__mode__byte 4 -#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR0_STATUS_DATA__mode__off 7 -#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR0_STATUS_DATA__mode__epp_rd 0 -#define R_PAR0_STATUS_DATA__perr__BITNR 28 -#define R_PAR0_STATUS_DATA__perr__WIDTH 1 -#define R_PAR0_STATUS_DATA__perr__active 1 -#define R_PAR0_STATUS_DATA__perr__inactive 0 -#define R_PAR0_STATUS_DATA__ack__BITNR 27 -#define R_PAR0_STATUS_DATA__ack__WIDTH 1 -#define R_PAR0_STATUS_DATA__ack__active 0 -#define R_PAR0_STATUS_DATA__ack__inactive 1 -#define R_PAR0_STATUS_DATA__busy__BITNR 26 -#define R_PAR0_STATUS_DATA__busy__WIDTH 1 -#define R_PAR0_STATUS_DATA__busy__active 1 -#define R_PAR0_STATUS_DATA__busy__inactive 0 -#define R_PAR0_STATUS_DATA__fault__BITNR 25 -#define R_PAR0_STATUS_DATA__fault__WIDTH 1 -#define R_PAR0_STATUS_DATA__fault__active 0 -#define R_PAR0_STATUS_DATA__fault__inactive 1 -#define R_PAR0_STATUS_DATA__sel__BITNR 24 -#define R_PAR0_STATUS_DATA__sel__WIDTH 1 -#define R_PAR0_STATUS_DATA__sel__active 1 -#define R_PAR0_STATUS_DATA__sel__inactive 0 -#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR0_STATUS_DATA__ext_mode__enable 1 -#define R_PAR0_STATUS_DATA__ext_mode__disable 0 -#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 -#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_16__active 1 -#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 -#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR0_STATUS_DATA__dav__BITNR 16 -#define R_PAR0_STATUS_DATA__dav__WIDTH 1 -#define R_PAR0_STATUS_DATA__dav__data 1 -#define R_PAR0_STATUS_DATA__dav__nodata 0 -#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR0_STATUS_DATA__data__BITNR 0 -#define R_PAR0_STATUS_DATA__data__WIDTH 8 - -#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) -#define R_PAR0_STATUS__mode__BITNR 13 -#define R_PAR0_STATUS__mode__WIDTH 3 -#define R_PAR0_STATUS__mode__manual 0 -#define R_PAR0_STATUS__mode__centronics 1 -#define R_PAR0_STATUS__mode__fastbyte 2 -#define R_PAR0_STATUS__mode__nibble 3 -#define R_PAR0_STATUS__mode__byte 4 -#define R_PAR0_STATUS__mode__ecp_fwd 5 -#define R_PAR0_STATUS__mode__ecp_rev 6 -#define R_PAR0_STATUS__mode__off 7 -#define R_PAR0_STATUS__mode__epp_wr1 5 -#define R_PAR0_STATUS__mode__epp_wr2 6 -#define R_PAR0_STATUS__mode__epp_wr3 7 -#define R_PAR0_STATUS__mode__epp_rd 0 -#define R_PAR0_STATUS__perr__BITNR 12 -#define R_PAR0_STATUS__perr__WIDTH 1 -#define R_PAR0_STATUS__perr__active 1 -#define R_PAR0_STATUS__perr__inactive 0 -#define R_PAR0_STATUS__ack__BITNR 11 -#define R_PAR0_STATUS__ack__WIDTH 1 -#define R_PAR0_STATUS__ack__active 0 -#define R_PAR0_STATUS__ack__inactive 1 -#define R_PAR0_STATUS__busy__BITNR 10 -#define R_PAR0_STATUS__busy__WIDTH 1 -#define R_PAR0_STATUS__busy__active 1 -#define R_PAR0_STATUS__busy__inactive 0 -#define R_PAR0_STATUS__fault__BITNR 9 -#define R_PAR0_STATUS__fault__WIDTH 1 -#define R_PAR0_STATUS__fault__active 0 -#define R_PAR0_STATUS__fault__inactive 1 -#define R_PAR0_STATUS__sel__BITNR 8 -#define R_PAR0_STATUS__sel__WIDTH 1 -#define R_PAR0_STATUS__sel__active 1 -#define R_PAR0_STATUS__sel__inactive 0 -#define R_PAR0_STATUS__ext_mode__BITNR 7 -#define R_PAR0_STATUS__ext_mode__WIDTH 1 -#define R_PAR0_STATUS__ext_mode__enable 1 -#define R_PAR0_STATUS__ext_mode__disable 0 -#define R_PAR0_STATUS__ecp_16__BITNR 6 -#define R_PAR0_STATUS__ecp_16__WIDTH 1 -#define R_PAR0_STATUS__ecp_16__active 1 -#define R_PAR0_STATUS__ecp_16__inactive 0 -#define R_PAR0_STATUS__tr_rdy__BITNR 1 -#define R_PAR0_STATUS__tr_rdy__WIDTH 1 -#define R_PAR0_STATUS__tr_rdy__ready 1 -#define R_PAR0_STATUS__tr_rdy__busy 0 -#define R_PAR0_STATUS__dav__BITNR 0 -#define R_PAR0_STATUS__dav__WIDTH 1 -#define R_PAR0_STATUS__dav__data 1 -#define R_PAR0_STATUS__dav__nodata 0 - -#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_PAR_ECP16_DATA__data__BITNR 0 -#define R_PAR_ECP16_DATA__data__WIDTH 16 - -#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_PAR0_CONFIG__ioe__BITNR 25 -#define R_PAR0_CONFIG__ioe__WIDTH 1 -#define R_PAR0_CONFIG__ioe__inv 1 -#define R_PAR0_CONFIG__ioe__noninv 0 -#define R_PAR0_CONFIG__iseli__BITNR 24 -#define R_PAR0_CONFIG__iseli__WIDTH 1 -#define R_PAR0_CONFIG__iseli__inv 1 -#define R_PAR0_CONFIG__iseli__noninv 0 -#define R_PAR0_CONFIG__iautofd__BITNR 23 -#define R_PAR0_CONFIG__iautofd__WIDTH 1 -#define R_PAR0_CONFIG__iautofd__inv 1 -#define R_PAR0_CONFIG__iautofd__noninv 0 -#define R_PAR0_CONFIG__istrb__BITNR 22 -#define R_PAR0_CONFIG__istrb__WIDTH 1 -#define R_PAR0_CONFIG__istrb__inv 1 -#define R_PAR0_CONFIG__istrb__noninv 0 -#define R_PAR0_CONFIG__iinit__BITNR 21 -#define R_PAR0_CONFIG__iinit__WIDTH 1 -#define R_PAR0_CONFIG__iinit__inv 1 -#define R_PAR0_CONFIG__iinit__noninv 0 -#define R_PAR0_CONFIG__iperr__BITNR 20 -#define R_PAR0_CONFIG__iperr__WIDTH 1 -#define R_PAR0_CONFIG__iperr__inv 1 -#define R_PAR0_CONFIG__iperr__noninv 0 -#define R_PAR0_CONFIG__iack__BITNR 19 -#define R_PAR0_CONFIG__iack__WIDTH 1 -#define R_PAR0_CONFIG__iack__inv 1 -#define R_PAR0_CONFIG__iack__noninv 0 -#define R_PAR0_CONFIG__ibusy__BITNR 18 -#define R_PAR0_CONFIG__ibusy__WIDTH 1 -#define R_PAR0_CONFIG__ibusy__inv 1 -#define R_PAR0_CONFIG__ibusy__noninv 0 -#define R_PAR0_CONFIG__ifault__BITNR 17 -#define R_PAR0_CONFIG__ifault__WIDTH 1 -#define R_PAR0_CONFIG__ifault__inv 1 -#define R_PAR0_CONFIG__ifault__noninv 0 -#define R_PAR0_CONFIG__isel__BITNR 16 -#define R_PAR0_CONFIG__isel__WIDTH 1 -#define R_PAR0_CONFIG__isel__inv 1 -#define R_PAR0_CONFIG__isel__noninv 0 -#define R_PAR0_CONFIG__ext_mode__BITNR 11 -#define R_PAR0_CONFIG__ext_mode__WIDTH 1 -#define R_PAR0_CONFIG__ext_mode__enable 1 -#define R_PAR0_CONFIG__ext_mode__disable 0 -#define R_PAR0_CONFIG__wide__BITNR 10 -#define R_PAR0_CONFIG__wide__WIDTH 1 -#define R_PAR0_CONFIG__wide__enable 1 -#define R_PAR0_CONFIG__wide__disable 0 -#define R_PAR0_CONFIG__dma__BITNR 9 -#define R_PAR0_CONFIG__dma__WIDTH 1 -#define R_PAR0_CONFIG__dma__enable 1 -#define R_PAR0_CONFIG__dma__disable 0 -#define R_PAR0_CONFIG__rle_in__BITNR 8 -#define R_PAR0_CONFIG__rle_in__WIDTH 1 -#define R_PAR0_CONFIG__rle_in__enable 1 -#define R_PAR0_CONFIG__rle_in__disable 0 -#define R_PAR0_CONFIG__rle_out__BITNR 7 -#define R_PAR0_CONFIG__rle_out__WIDTH 1 -#define R_PAR0_CONFIG__rle_out__enable 1 -#define R_PAR0_CONFIG__rle_out__disable 0 -#define R_PAR0_CONFIG__enable__BITNR 6 -#define R_PAR0_CONFIG__enable__WIDTH 1 -#define R_PAR0_CONFIG__enable__on 1 -#define R_PAR0_CONFIG__enable__reset 0 -#define R_PAR0_CONFIG__force__BITNR 5 -#define R_PAR0_CONFIG__force__WIDTH 1 -#define R_PAR0_CONFIG__force__on 1 -#define R_PAR0_CONFIG__force__off 0 -#define R_PAR0_CONFIG__ign_ack__BITNR 4 -#define R_PAR0_CONFIG__ign_ack__WIDTH 1 -#define R_PAR0_CONFIG__ign_ack__ignore 1 -#define R_PAR0_CONFIG__ign_ack__wait 0 -#define R_PAR0_CONFIG__oe_ack__BITNR 3 -#define R_PAR0_CONFIG__oe_ack__WIDTH 1 -#define R_PAR0_CONFIG__oe_ack__wait_oe 1 -#define R_PAR0_CONFIG__oe_ack__dont_wait 0 -#define R_PAR0_CONFIG__oe_ack__epp_addr 1 -#define R_PAR0_CONFIG__oe_ack__epp_data 0 -#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR0_CONFIG__mode__BITNR 0 -#define R_PAR0_CONFIG__mode__WIDTH 3 -#define R_PAR0_CONFIG__mode__manual 0 -#define R_PAR0_CONFIG__mode__centronics 1 -#define R_PAR0_CONFIG__mode__fastbyte 2 -#define R_PAR0_CONFIG__mode__nibble 3 -#define R_PAR0_CONFIG__mode__byte 4 -#define R_PAR0_CONFIG__mode__ecp_fwd 5 -#define R_PAR0_CONFIG__mode__ecp_rev 6 -#define R_PAR0_CONFIG__mode__off 7 -#define R_PAR0_CONFIG__mode__epp_wr1 5 -#define R_PAR0_CONFIG__mode__epp_wr2 6 -#define R_PAR0_CONFIG__mode__epp_wr3 7 -#define R_PAR0_CONFIG__mode__epp_rd 0 - -#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) -#define R_PAR0_DELAY__fine_hold__BITNR 21 -#define R_PAR0_DELAY__fine_hold__WIDTH 3 -#define R_PAR0_DELAY__hold__BITNR 16 -#define R_PAR0_DELAY__hold__WIDTH 5 -#define R_PAR0_DELAY__fine_strb__BITNR 13 -#define R_PAR0_DELAY__fine_strb__WIDTH 3 -#define R_PAR0_DELAY__strobe__BITNR 8 -#define R_PAR0_DELAY__strobe__WIDTH 5 -#define R_PAR0_DELAY__fine_setup__BITNR 5 -#define R_PAR0_DELAY__fine_setup__WIDTH 3 -#define R_PAR0_DELAY__setup__BITNR 0 -#define R_PAR0_DELAY__setup__WIDTH 5 - -#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 -#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 -#define R_PAR1_CTRL_DATA__peri_int__ack 1 -#define R_PAR1_CTRL_DATA__peri_int__nop 0 -#define R_PAR1_CTRL_DATA__oe__BITNR 20 -#define R_PAR1_CTRL_DATA__oe__WIDTH 1 -#define R_PAR1_CTRL_DATA__oe__enable 1 -#define R_PAR1_CTRL_DATA__oe__disable 0 -#define R_PAR1_CTRL_DATA__seli__BITNR 19 -#define R_PAR1_CTRL_DATA__seli__WIDTH 1 -#define R_PAR1_CTRL_DATA__seli__active 1 -#define R_PAR1_CTRL_DATA__seli__inactive 0 -#define R_PAR1_CTRL_DATA__autofd__BITNR 18 -#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 -#define R_PAR1_CTRL_DATA__autofd__active 1 -#define R_PAR1_CTRL_DATA__autofd__inactive 0 -#define R_PAR1_CTRL_DATA__strb__BITNR 17 -#define R_PAR1_CTRL_DATA__strb__WIDTH 1 -#define R_PAR1_CTRL_DATA__strb__active 1 -#define R_PAR1_CTRL_DATA__strb__inactive 0 -#define R_PAR1_CTRL_DATA__init__BITNR 16 -#define R_PAR1_CTRL_DATA__init__WIDTH 1 -#define R_PAR1_CTRL_DATA__init__active 1 -#define R_PAR1_CTRL_DATA__init__inactive 0 -#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 -#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 -#define R_PAR1_CTRL_DATA__data__BITNR 0 -#define R_PAR1_CTRL_DATA__data__WIDTH 8 - -#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) -#define R_PAR1_CTRL__ctrl__BITNR 0 -#define R_PAR1_CTRL__ctrl__WIDTH 5 - -#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) -#define R_PAR1_STATUS_DATA__mode__BITNR 29 -#define R_PAR1_STATUS_DATA__mode__WIDTH 3 -#define R_PAR1_STATUS_DATA__mode__manual 0 -#define R_PAR1_STATUS_DATA__mode__centronics 1 -#define R_PAR1_STATUS_DATA__mode__fastbyte 2 -#define R_PAR1_STATUS_DATA__mode__nibble 3 -#define R_PAR1_STATUS_DATA__mode__byte 4 -#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 -#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 -#define R_PAR1_STATUS_DATA__mode__off 7 -#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 -#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 -#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 -#define R_PAR1_STATUS_DATA__mode__epp_rd 0 -#define R_PAR1_STATUS_DATA__perr__BITNR 28 -#define R_PAR1_STATUS_DATA__perr__WIDTH 1 -#define R_PAR1_STATUS_DATA__perr__active 1 -#define R_PAR1_STATUS_DATA__perr__inactive 0 -#define R_PAR1_STATUS_DATA__ack__BITNR 27 -#define R_PAR1_STATUS_DATA__ack__WIDTH 1 -#define R_PAR1_STATUS_DATA__ack__active 0 -#define R_PAR1_STATUS_DATA__ack__inactive 1 -#define R_PAR1_STATUS_DATA__busy__BITNR 26 -#define R_PAR1_STATUS_DATA__busy__WIDTH 1 -#define R_PAR1_STATUS_DATA__busy__active 1 -#define R_PAR1_STATUS_DATA__busy__inactive 0 -#define R_PAR1_STATUS_DATA__fault__BITNR 25 -#define R_PAR1_STATUS_DATA__fault__WIDTH 1 -#define R_PAR1_STATUS_DATA__fault__active 0 -#define R_PAR1_STATUS_DATA__fault__inactive 1 -#define R_PAR1_STATUS_DATA__sel__BITNR 24 -#define R_PAR1_STATUS_DATA__sel__WIDTH 1 -#define R_PAR1_STATUS_DATA__sel__active 1 -#define R_PAR1_STATUS_DATA__sel__inactive 0 -#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 -#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 -#define R_PAR1_STATUS_DATA__ext_mode__enable 1 -#define R_PAR1_STATUS_DATA__ext_mode__disable 0 -#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 -#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 -#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 -#define R_PAR1_STATUS_DATA__dav__BITNR 16 -#define R_PAR1_STATUS_DATA__dav__WIDTH 1 -#define R_PAR1_STATUS_DATA__dav__data 1 -#define R_PAR1_STATUS_DATA__dav__nodata 0 -#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 -#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 -#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 -#define R_PAR1_STATUS_DATA__data__BITNR 0 -#define R_PAR1_STATUS_DATA__data__WIDTH 8 - -#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) -#define R_PAR1_STATUS__mode__BITNR 13 -#define R_PAR1_STATUS__mode__WIDTH 3 -#define R_PAR1_STATUS__mode__manual 0 -#define R_PAR1_STATUS__mode__centronics 1 -#define R_PAR1_STATUS__mode__fastbyte 2 -#define R_PAR1_STATUS__mode__nibble 3 -#define R_PAR1_STATUS__mode__byte 4 -#define R_PAR1_STATUS__mode__ecp_fwd 5 -#define R_PAR1_STATUS__mode__ecp_rev 6 -#define R_PAR1_STATUS__mode__off 7 -#define R_PAR1_STATUS__mode__epp_wr1 5 -#define R_PAR1_STATUS__mode__epp_wr2 6 -#define R_PAR1_STATUS__mode__epp_wr3 7 -#define R_PAR1_STATUS__mode__epp_rd 0 -#define R_PAR1_STATUS__perr__BITNR 12 -#define R_PAR1_STATUS__perr__WIDTH 1 -#define R_PAR1_STATUS__perr__active 1 -#define R_PAR1_STATUS__perr__inactive 0 -#define R_PAR1_STATUS__ack__BITNR 11 -#define R_PAR1_STATUS__ack__WIDTH 1 -#define R_PAR1_STATUS__ack__active 0 -#define R_PAR1_STATUS__ack__inactive 1 -#define R_PAR1_STATUS__busy__BITNR 10 -#define R_PAR1_STATUS__busy__WIDTH 1 -#define R_PAR1_STATUS__busy__active 1 -#define R_PAR1_STATUS__busy__inactive 0 -#define R_PAR1_STATUS__fault__BITNR 9 -#define R_PAR1_STATUS__fault__WIDTH 1 -#define R_PAR1_STATUS__fault__active 0 -#define R_PAR1_STATUS__fault__inactive 1 -#define R_PAR1_STATUS__sel__BITNR 8 -#define R_PAR1_STATUS__sel__WIDTH 1 -#define R_PAR1_STATUS__sel__active 1 -#define R_PAR1_STATUS__sel__inactive 0 -#define R_PAR1_STATUS__ext_mode__BITNR 7 -#define R_PAR1_STATUS__ext_mode__WIDTH 1 -#define R_PAR1_STATUS__ext_mode__enable 1 -#define R_PAR1_STATUS__ext_mode__disable 0 -#define R_PAR1_STATUS__tr_rdy__BITNR 1 -#define R_PAR1_STATUS__tr_rdy__WIDTH 1 -#define R_PAR1_STATUS__tr_rdy__ready 1 -#define R_PAR1_STATUS__tr_rdy__busy 0 -#define R_PAR1_STATUS__dav__BITNR 0 -#define R_PAR1_STATUS__dav__WIDTH 1 -#define R_PAR1_STATUS__dav__data 1 -#define R_PAR1_STATUS__dav__nodata 0 - -#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) -#define R_PAR1_CONFIG__ioe__BITNR 25 -#define R_PAR1_CONFIG__ioe__WIDTH 1 -#define R_PAR1_CONFIG__ioe__inv 1 -#define R_PAR1_CONFIG__ioe__noninv 0 -#define R_PAR1_CONFIG__iseli__BITNR 24 -#define R_PAR1_CONFIG__iseli__WIDTH 1 -#define R_PAR1_CONFIG__iseli__inv 1 -#define R_PAR1_CONFIG__iseli__noninv 0 -#define R_PAR1_CONFIG__iautofd__BITNR 23 -#define R_PAR1_CONFIG__iautofd__WIDTH 1 -#define R_PAR1_CONFIG__iautofd__inv 1 -#define R_PAR1_CONFIG__iautofd__noninv 0 -#define R_PAR1_CONFIG__istrb__BITNR 22 -#define R_PAR1_CONFIG__istrb__WIDTH 1 -#define R_PAR1_CONFIG__istrb__inv 1 -#define R_PAR1_CONFIG__istrb__noninv 0 -#define R_PAR1_CONFIG__iinit__BITNR 21 -#define R_PAR1_CONFIG__iinit__WIDTH 1 -#define R_PAR1_CONFIG__iinit__inv 1 -#define R_PAR1_CONFIG__iinit__noninv 0 -#define R_PAR1_CONFIG__iperr__BITNR 20 -#define R_PAR1_CONFIG__iperr__WIDTH 1 -#define R_PAR1_CONFIG__iperr__inv 1 -#define R_PAR1_CONFIG__iperr__noninv 0 -#define R_PAR1_CONFIG__iack__BITNR 19 -#define R_PAR1_CONFIG__iack__WIDTH 1 -#define R_PAR1_CONFIG__iack__inv 1 -#define R_PAR1_CONFIG__iack__noninv 0 -#define R_PAR1_CONFIG__ibusy__BITNR 18 -#define R_PAR1_CONFIG__ibusy__WIDTH 1 -#define R_PAR1_CONFIG__ibusy__inv 1 -#define R_PAR1_CONFIG__ibusy__noninv 0 -#define R_PAR1_CONFIG__ifault__BITNR 17 -#define R_PAR1_CONFIG__ifault__WIDTH 1 -#define R_PAR1_CONFIG__ifault__inv 1 -#define R_PAR1_CONFIG__ifault__noninv 0 -#define R_PAR1_CONFIG__isel__BITNR 16 -#define R_PAR1_CONFIG__isel__WIDTH 1 -#define R_PAR1_CONFIG__isel__inv 1 -#define R_PAR1_CONFIG__isel__noninv 0 -#define R_PAR1_CONFIG__ext_mode__BITNR 11 -#define R_PAR1_CONFIG__ext_mode__WIDTH 1 -#define R_PAR1_CONFIG__ext_mode__enable 1 -#define R_PAR1_CONFIG__ext_mode__disable 0 -#define R_PAR1_CONFIG__dma__BITNR 9 -#define R_PAR1_CONFIG__dma__WIDTH 1 -#define R_PAR1_CONFIG__dma__enable 1 -#define R_PAR1_CONFIG__dma__disable 0 -#define R_PAR1_CONFIG__rle_in__BITNR 8 -#define R_PAR1_CONFIG__rle_in__WIDTH 1 -#define R_PAR1_CONFIG__rle_in__enable 1 -#define R_PAR1_CONFIG__rle_in__disable 0 -#define R_PAR1_CONFIG__rle_out__BITNR 7 -#define R_PAR1_CONFIG__rle_out__WIDTH 1 -#define R_PAR1_CONFIG__rle_out__enable 1 -#define R_PAR1_CONFIG__rle_out__disable 0 -#define R_PAR1_CONFIG__enable__BITNR 6 -#define R_PAR1_CONFIG__enable__WIDTH 1 -#define R_PAR1_CONFIG__enable__on 1 -#define R_PAR1_CONFIG__enable__reset 0 -#define R_PAR1_CONFIG__force__BITNR 5 -#define R_PAR1_CONFIG__force__WIDTH 1 -#define R_PAR1_CONFIG__force__on 1 -#define R_PAR1_CONFIG__force__off 0 -#define R_PAR1_CONFIG__ign_ack__BITNR 4 -#define R_PAR1_CONFIG__ign_ack__WIDTH 1 -#define R_PAR1_CONFIG__ign_ack__ignore 1 -#define R_PAR1_CONFIG__ign_ack__wait 0 -#define R_PAR1_CONFIG__oe_ack__BITNR 3 -#define R_PAR1_CONFIG__oe_ack__WIDTH 1 -#define R_PAR1_CONFIG__oe_ack__wait_oe 1 -#define R_PAR1_CONFIG__oe_ack__dont_wait 0 -#define R_PAR1_CONFIG__oe_ack__epp_addr 1 -#define R_PAR1_CONFIG__oe_ack__epp_data 0 -#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 -#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 -#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 -#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 -#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 -#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 -#define R_PAR1_CONFIG__mode__BITNR 0 -#define R_PAR1_CONFIG__mode__WIDTH 3 -#define R_PAR1_CONFIG__mode__manual 0 -#define R_PAR1_CONFIG__mode__centronics 1 -#define R_PAR1_CONFIG__mode__fastbyte 2 -#define R_PAR1_CONFIG__mode__nibble 3 -#define R_PAR1_CONFIG__mode__byte 4 -#define R_PAR1_CONFIG__mode__ecp_fwd 5 -#define R_PAR1_CONFIG__mode__ecp_rev 6 -#define R_PAR1_CONFIG__mode__off 7 -#define R_PAR1_CONFIG__mode__epp_wr1 5 -#define R_PAR1_CONFIG__mode__epp_wr2 6 -#define R_PAR1_CONFIG__mode__epp_wr3 7 -#define R_PAR1_CONFIG__mode__epp_rd 0 - -#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) -#define R_PAR1_DELAY__fine_hold__BITNR 21 -#define R_PAR1_DELAY__fine_hold__WIDTH 3 -#define R_PAR1_DELAY__hold__BITNR 16 -#define R_PAR1_DELAY__hold__WIDTH 5 -#define R_PAR1_DELAY__fine_strb__BITNR 13 -#define R_PAR1_DELAY__fine_strb__WIDTH 3 -#define R_PAR1_DELAY__strobe__BITNR 8 -#define R_PAR1_DELAY__strobe__WIDTH 5 -#define R_PAR1_DELAY__fine_setup__BITNR 5 -#define R_PAR1_DELAY__fine_setup__WIDTH 3 -#define R_PAR1_DELAY__setup__BITNR 0 -#define R_PAR1_DELAY__setup__WIDTH 5 - -/* -!* ATA interface registers -!*/ - -#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_ATA_CTRL_DATA__sel__BITNR 30 -#define R_ATA_CTRL_DATA__sel__WIDTH 2 -#define R_ATA_CTRL_DATA__cs1__BITNR 29 -#define R_ATA_CTRL_DATA__cs1__WIDTH 1 -#define R_ATA_CTRL_DATA__cs1__active 1 -#define R_ATA_CTRL_DATA__cs1__inactive 0 -#define R_ATA_CTRL_DATA__cs0__BITNR 28 -#define R_ATA_CTRL_DATA__cs0__WIDTH 1 -#define R_ATA_CTRL_DATA__cs0__active 1 -#define R_ATA_CTRL_DATA__cs0__inactive 0 -#define R_ATA_CTRL_DATA__addr__BITNR 25 -#define R_ATA_CTRL_DATA__addr__WIDTH 3 -#define R_ATA_CTRL_DATA__rw__BITNR 24 -#define R_ATA_CTRL_DATA__rw__WIDTH 1 -#define R_ATA_CTRL_DATA__rw__read 1 -#define R_ATA_CTRL_DATA__rw__write 0 -#define R_ATA_CTRL_DATA__src_dst__BITNR 23 -#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 -#define R_ATA_CTRL_DATA__src_dst__dma 1 -#define R_ATA_CTRL_DATA__src_dst__register 0 -#define R_ATA_CTRL_DATA__handsh__BITNR 22 -#define R_ATA_CTRL_DATA__handsh__WIDTH 1 -#define R_ATA_CTRL_DATA__handsh__dma 1 -#define R_ATA_CTRL_DATA__handsh__pio 0 -#define R_ATA_CTRL_DATA__multi__BITNR 21 -#define R_ATA_CTRL_DATA__multi__WIDTH 1 -#define R_ATA_CTRL_DATA__multi__on 1 -#define R_ATA_CTRL_DATA__multi__off 0 -#define R_ATA_CTRL_DATA__dma_size__BITNR 20 -#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 -#define R_ATA_CTRL_DATA__dma_size__byte 1 -#define R_ATA_CTRL_DATA__dma_size__word 0 -#define R_ATA_CTRL_DATA__data__BITNR 0 -#define R_ATA_CTRL_DATA__data__WIDTH 16 - -#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) -#define R_ATA_STATUS_DATA__busy__BITNR 18 -#define R_ATA_STATUS_DATA__busy__WIDTH 1 -#define R_ATA_STATUS_DATA__busy__yes 1 -#define R_ATA_STATUS_DATA__busy__no 0 -#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 -#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 -#define R_ATA_STATUS_DATA__tr_rdy__ready 1 -#define R_ATA_STATUS_DATA__tr_rdy__busy 0 -#define R_ATA_STATUS_DATA__dav__BITNR 16 -#define R_ATA_STATUS_DATA__dav__WIDTH 1 -#define R_ATA_STATUS_DATA__dav__data 1 -#define R_ATA_STATUS_DATA__dav__nodata 0 -#define R_ATA_STATUS_DATA__data__BITNR 0 -#define R_ATA_STATUS_DATA__data__WIDTH 16 - -#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) -#define R_ATA_CONFIG__enable__BITNR 25 -#define R_ATA_CONFIG__enable__WIDTH 1 -#define R_ATA_CONFIG__enable__on 1 -#define R_ATA_CONFIG__enable__off 0 -#define R_ATA_CONFIG__dma_strobe__BITNR 20 -#define R_ATA_CONFIG__dma_strobe__WIDTH 5 -#define R_ATA_CONFIG__dma_hold__BITNR 15 -#define R_ATA_CONFIG__dma_hold__WIDTH 5 -#define R_ATA_CONFIG__pio_setup__BITNR 10 -#define R_ATA_CONFIG__pio_setup__WIDTH 5 -#define R_ATA_CONFIG__pio_strobe__BITNR 5 -#define R_ATA_CONFIG__pio_strobe__WIDTH 5 -#define R_ATA_CONFIG__pio_hold__BITNR 0 -#define R_ATA_CONFIG__pio_hold__WIDTH 5 - -#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) -#define R_ATA_TRANSFER_CNT__count__BITNR 0 -#define R_ATA_TRANSFER_CNT__count__WIDTH 17 - -/* -!* SCSI registers -!*/ - -#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) -#define R_SCSI0_CTRL__id_type__BITNR 31 -#define R_SCSI0_CTRL__id_type__WIDTH 1 -#define R_SCSI0_CTRL__id_type__software 1 -#define R_SCSI0_CTRL__id_type__hardware 0 -#define R_SCSI0_CTRL__sel_timeout__BITNR 24 -#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI0_CTRL__synch_per__BITNR 16 -#define R_SCSI0_CTRL__synch_per__WIDTH 8 -#define R_SCSI0_CTRL__rst__BITNR 15 -#define R_SCSI0_CTRL__rst__WIDTH 1 -#define R_SCSI0_CTRL__rst__yes 1 -#define R_SCSI0_CTRL__rst__no 0 -#define R_SCSI0_CTRL__atn__BITNR 14 -#define R_SCSI0_CTRL__atn__WIDTH 1 -#define R_SCSI0_CTRL__atn__yes 1 -#define R_SCSI0_CTRL__atn__no 0 -#define R_SCSI0_CTRL__my_id__BITNR 9 -#define R_SCSI0_CTRL__my_id__WIDTH 4 -#define R_SCSI0_CTRL__target_id__BITNR 4 -#define R_SCSI0_CTRL__target_id__WIDTH 4 -#define R_SCSI0_CTRL__fast_20__BITNR 3 -#define R_SCSI0_CTRL__fast_20__WIDTH 1 -#define R_SCSI0_CTRL__fast_20__yes 1 -#define R_SCSI0_CTRL__fast_20__no 0 -#define R_SCSI0_CTRL__bus_width__BITNR 2 -#define R_SCSI0_CTRL__bus_width__WIDTH 1 -#define R_SCSI0_CTRL__bus_width__wide 1 -#define R_SCSI0_CTRL__bus_width__narrow 0 -#define R_SCSI0_CTRL__synch__BITNR 1 -#define R_SCSI0_CTRL__synch__WIDTH 1 -#define R_SCSI0_CTRL__synch__synch 1 -#define R_SCSI0_CTRL__synch__asynch 0 -#define R_SCSI0_CTRL__enable__BITNR 0 -#define R_SCSI0_CTRL__enable__WIDTH 1 -#define R_SCSI0_CTRL__enable__on 1 -#define R_SCSI0_CTRL__enable__off 0 - -#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) -#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI0_CMD_DATA__parity_in__on 0 -#define R_SCSI0_CMD_DATA__parity_in__off 1 -#define R_SCSI0_CMD_DATA__skip__BITNR 25 -#define R_SCSI0_CMD_DATA__skip__WIDTH 1 -#define R_SCSI0_CMD_DATA__skip__on 1 -#define R_SCSI0_CMD_DATA__skip__off 0 -#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI0_CMD_DATA__clr_status__yes 1 -#define R_SCSI0_CMD_DATA__clr_status__nop 0 -#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__BITNR 16 -#define R_SCSI0_CMD_DATA__command__WIDTH 4 -#define R_SCSI0_CMD_DATA__command__full_din_1 0 -#define R_SCSI0_CMD_DATA__command__full_dout_1 1 -#define R_SCSI0_CMD_DATA__command__full_stat_1 2 -#define R_SCSI0_CMD_DATA__command__resel_din 3 -#define R_SCSI0_CMD_DATA__command__resel_dout 4 -#define R_SCSI0_CMD_DATA__command__resel_stat 5 -#define R_SCSI0_CMD_DATA__command__arb_only 6 -#define R_SCSI0_CMD_DATA__command__full_din_3 8 -#define R_SCSI0_CMD_DATA__command__full_dout_3 9 -#define R_SCSI0_CMD_DATA__command__full_stat_3 10 -#define R_SCSI0_CMD_DATA__command__man_data_in 11 -#define R_SCSI0_CMD_DATA__command__man_data_out 12 -#define R_SCSI0_CMD_DATA__command__man_rat 13 -#define R_SCSI0_CMD_DATA__data_out__BITNR 0 -#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) -#define R_SCSI0_DATA__data_out__BITNR 0 -#define R_SCSI0_DATA__data_out__WIDTH 16 - -#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) -#define R_SCSI0_CMD__asynch_setup__BITNR 4 -#define R_SCSI0_CMD__asynch_setup__WIDTH 4 -#define R_SCSI0_CMD__command__BITNR 0 -#define R_SCSI0_CMD__command__WIDTH 4 -#define R_SCSI0_CMD__command__full_din_1 0 -#define R_SCSI0_CMD__command__full_dout_1 1 -#define R_SCSI0_CMD__command__full_stat_1 2 -#define R_SCSI0_CMD__command__resel_din 3 -#define R_SCSI0_CMD__command__resel_dout 4 -#define R_SCSI0_CMD__command__resel_stat 5 -#define R_SCSI0_CMD__command__arb_only 6 -#define R_SCSI0_CMD__command__full_din_3 8 -#define R_SCSI0_CMD__command__full_dout_3 9 -#define R_SCSI0_CMD__command__full_stat_3 10 -#define R_SCSI0_CMD__command__man_data_in 11 -#define R_SCSI0_CMD__command__man_data_out 12 -#define R_SCSI0_CMD__command__man_rat 13 - -#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) -#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__parity_in__on 0 -#define R_SCSI0_STATUS_CTRL__parity_in__off 1 -#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__skip__on 1 -#define R_SCSI0_STATUS_CTRL__skip__off 0 -#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) -#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI0_STATUS__tst_resel__BITNR 22 -#define R_SCSI0_STATUS__tst_resel__WIDTH 1 -#define R_SCSI0_STATUS__parity_error__BITNR 21 -#define R_SCSI0_STATUS__parity_error__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__BITNR 20 -#define R_SCSI0_STATUS__bus_reset__WIDTH 1 -#define R_SCSI0_STATUS__bus_reset__yes 1 -#define R_SCSI0_STATUS__bus_reset__no 0 -#define R_SCSI0_STATUS__resel_target__BITNR 15 -#define R_SCSI0_STATUS__resel_target__WIDTH 4 -#define R_SCSI0_STATUS__resel__BITNR 14 -#define R_SCSI0_STATUS__resel__WIDTH 1 -#define R_SCSI0_STATUS__resel__yes 1 -#define R_SCSI0_STATUS__resel__no 0 -#define R_SCSI0_STATUS__curr_phase__BITNR 11 -#define R_SCSI0_STATUS__curr_phase__WIDTH 3 -#define R_SCSI0_STATUS__curr_phase__ph_undef 0 -#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI0_STATUS__curr_phase__ph_status 3 -#define R_SCSI0_STATUS__curr_phase__ph_command 2 -#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI0_STATUS__curr_phase__ph_resel 1 -#define R_SCSI0_STATUS__last_seq_step__BITNR 6 -#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI0_STATUS__last_seq_step__st_manual 28 -#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI0_STATUS__last_seq_step__st_answer 3 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI0_STATUS__last_seq_step__st_cc 31 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI0_STATUS__valid_status__BITNR 5 -#define R_SCSI0_STATUS__valid_status__WIDTH 1 -#define R_SCSI0_STATUS__valid_status__yes 1 -#define R_SCSI0_STATUS__valid_status__no 0 -#define R_SCSI0_STATUS__seq_status__BITNR 0 -#define R_SCSI0_STATUS__seq_status__WIDTH 5 -#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI0_STATUS__seq_status__info_parity_error 1 -#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI0_STATUS__seq_status__info_reselected 9 -#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI0_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) -#define R_SCSI0_DATA_IN__data_in__BITNR 0 -#define R_SCSI0_DATA_IN__data_in__WIDTH 16 - -#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) -#define R_SCSI1_CTRL__id_type__BITNR 31 -#define R_SCSI1_CTRL__id_type__WIDTH 1 -#define R_SCSI1_CTRL__id_type__software 1 -#define R_SCSI1_CTRL__id_type__hardware 0 -#define R_SCSI1_CTRL__sel_timeout__BITNR 24 -#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 -#define R_SCSI1_CTRL__synch_per__BITNR 16 -#define R_SCSI1_CTRL__synch_per__WIDTH 8 -#define R_SCSI1_CTRL__rst__BITNR 15 -#define R_SCSI1_CTRL__rst__WIDTH 1 -#define R_SCSI1_CTRL__rst__yes 1 -#define R_SCSI1_CTRL__rst__no 0 -#define R_SCSI1_CTRL__atn__BITNR 14 -#define R_SCSI1_CTRL__atn__WIDTH 1 -#define R_SCSI1_CTRL__atn__yes 1 -#define R_SCSI1_CTRL__atn__no 0 -#define R_SCSI1_CTRL__my_id__BITNR 9 -#define R_SCSI1_CTRL__my_id__WIDTH 4 -#define R_SCSI1_CTRL__target_id__BITNR 4 -#define R_SCSI1_CTRL__target_id__WIDTH 4 -#define R_SCSI1_CTRL__fast_20__BITNR 3 -#define R_SCSI1_CTRL__fast_20__WIDTH 1 -#define R_SCSI1_CTRL__fast_20__yes 1 -#define R_SCSI1_CTRL__fast_20__no 0 -#define R_SCSI1_CTRL__bus_width__BITNR 2 -#define R_SCSI1_CTRL__bus_width__WIDTH 1 -#define R_SCSI1_CTRL__bus_width__wide 1 -#define R_SCSI1_CTRL__bus_width__narrow 0 -#define R_SCSI1_CTRL__synch__BITNR 1 -#define R_SCSI1_CTRL__synch__WIDTH 1 -#define R_SCSI1_CTRL__synch__synch 1 -#define R_SCSI1_CTRL__synch__asynch 0 -#define R_SCSI1_CTRL__enable__BITNR 0 -#define R_SCSI1_CTRL__enable__WIDTH 1 -#define R_SCSI1_CTRL__enable__on 1 -#define R_SCSI1_CTRL__enable__off 0 - -#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) -#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 -#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 -#define R_SCSI1_CMD_DATA__parity_in__on 0 -#define R_SCSI1_CMD_DATA__parity_in__off 1 -#define R_SCSI1_CMD_DATA__skip__BITNR 25 -#define R_SCSI1_CMD_DATA__skip__WIDTH 1 -#define R_SCSI1_CMD_DATA__skip__on 1 -#define R_SCSI1_CMD_DATA__skip__off 0 -#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 -#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 -#define R_SCSI1_CMD_DATA__clr_status__yes 1 -#define R_SCSI1_CMD_DATA__clr_status__nop 0 -#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 -#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__BITNR 16 -#define R_SCSI1_CMD_DATA__command__WIDTH 4 -#define R_SCSI1_CMD_DATA__command__full_din_1 0 -#define R_SCSI1_CMD_DATA__command__full_dout_1 1 -#define R_SCSI1_CMD_DATA__command__full_stat_1 2 -#define R_SCSI1_CMD_DATA__command__resel_din 3 -#define R_SCSI1_CMD_DATA__command__resel_dout 4 -#define R_SCSI1_CMD_DATA__command__resel_stat 5 -#define R_SCSI1_CMD_DATA__command__arb_only 6 -#define R_SCSI1_CMD_DATA__command__full_din_3 8 -#define R_SCSI1_CMD_DATA__command__full_dout_3 9 -#define R_SCSI1_CMD_DATA__command__full_stat_3 10 -#define R_SCSI1_CMD_DATA__command__man_data_in 11 -#define R_SCSI1_CMD_DATA__command__man_data_out 12 -#define R_SCSI1_CMD_DATA__command__man_rat 13 -#define R_SCSI1_CMD_DATA__data_out__BITNR 0 -#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 - -#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) -#define R_SCSI1_DATA__data_out__BITNR 0 -#define R_SCSI1_DATA__data_out__WIDTH 16 - -#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) -#define R_SCSI1_CMD__asynch_setup__BITNR 4 -#define R_SCSI1_CMD__asynch_setup__WIDTH 4 -#define R_SCSI1_CMD__command__BITNR 0 -#define R_SCSI1_CMD__command__WIDTH 4 -#define R_SCSI1_CMD__command__full_din_1 0 -#define R_SCSI1_CMD__command__full_dout_1 1 -#define R_SCSI1_CMD__command__full_stat_1 2 -#define R_SCSI1_CMD__command__resel_din 3 -#define R_SCSI1_CMD__command__resel_dout 4 -#define R_SCSI1_CMD__command__resel_stat 5 -#define R_SCSI1_CMD__command__arb_only 6 -#define R_SCSI1_CMD__command__full_din_3 8 -#define R_SCSI1_CMD__command__full_dout_3 9 -#define R_SCSI1_CMD__command__full_stat_3 10 -#define R_SCSI1_CMD__command__man_data_in 11 -#define R_SCSI1_CMD__command__man_data_out 12 -#define R_SCSI1_CMD__command__man_rat 13 - -#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) -#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 -#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__parity_in__on 0 -#define R_SCSI1_STATUS_CTRL__parity_in__off 1 -#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 -#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__skip__on 1 -#define R_SCSI1_STATUS_CTRL__skip__off 0 -#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 -#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 -#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 -#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 - -#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) -#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 -#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 -#define R_SCSI1_STATUS__tst_resel__BITNR 22 -#define R_SCSI1_STATUS__tst_resel__WIDTH 1 -#define R_SCSI1_STATUS__parity_error__BITNR 21 -#define R_SCSI1_STATUS__parity_error__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__BITNR 20 -#define R_SCSI1_STATUS__bus_reset__WIDTH 1 -#define R_SCSI1_STATUS__bus_reset__yes 1 -#define R_SCSI1_STATUS__bus_reset__no 0 -#define R_SCSI1_STATUS__resel_target__BITNR 15 -#define R_SCSI1_STATUS__resel_target__WIDTH 4 -#define R_SCSI1_STATUS__resel__BITNR 14 -#define R_SCSI1_STATUS__resel__WIDTH 1 -#define R_SCSI1_STATUS__resel__yes 1 -#define R_SCSI1_STATUS__resel__no 0 -#define R_SCSI1_STATUS__curr_phase__BITNR 11 -#define R_SCSI1_STATUS__curr_phase__WIDTH 3 -#define R_SCSI1_STATUS__curr_phase__ph_undef 0 -#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 -#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 -#define R_SCSI1_STATUS__curr_phase__ph_status 3 -#define R_SCSI1_STATUS__curr_phase__ph_command 2 -#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 -#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 -#define R_SCSI1_STATUS__curr_phase__ph_resel 1 -#define R_SCSI1_STATUS__last_seq_step__BITNR 6 -#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 -#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 -#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 -#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 -#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 -#define R_SCSI1_STATUS__last_seq_step__st_manual 28 -#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 -#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 -#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 -#define R_SCSI1_STATUS__last_seq_step__st_answer 3 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 -#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 -#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 -#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 -#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 -#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 -#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 -#define R_SCSI1_STATUS__last_seq_step__st_cc 31 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 -#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 -#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 -#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 -#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 -#define R_SCSI1_STATUS__valid_status__BITNR 5 -#define R_SCSI1_STATUS__valid_status__WIDTH 1 -#define R_SCSI1_STATUS__valid_status__yes 1 -#define R_SCSI1_STATUS__valid_status__no 0 -#define R_SCSI1_STATUS__seq_status__BITNR 0 -#define R_SCSI1_STATUS__seq_status__WIDTH 5 -#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 -#define R_SCSI1_STATUS__seq_status__info_parity_error 1 -#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 -#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 -#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 -#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 -#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 -#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 -#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 -#define R_SCSI1_STATUS__seq_status__info_reselected 9 -#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 -#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 -#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 -#define R_SCSI1_STATUS__seq_status__info_bus_free 13 - -#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) -#define R_SCSI1_DATA_IN__data_in__BITNR 0 -#define R_SCSI1_DATA_IN__data_in__WIDTH 16 - -/* -!* Interrupt mask and status registers -!*/ - -#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_RD__nmi_pin__active 1 -#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 -#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 -#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 -#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_RD__sqe_test_error__active 1 -#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 -#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_RD__carrier_loss__active 1 -#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 -#define R_IRQ_MASK0_RD__deferred__BITNR 27 -#define R_IRQ_MASK0_RD__deferred__WIDTH 1 -#define R_IRQ_MASK0_RD__deferred__active 1 -#define R_IRQ_MASK0_RD__deferred__inactive 0 -#define R_IRQ_MASK0_RD__late_col__BITNR 26 -#define R_IRQ_MASK0_RD__late_col__WIDTH 1 -#define R_IRQ_MASK0_RD__late_col__active 1 -#define R_IRQ_MASK0_RD__late_col__inactive 0 -#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 -#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_RD__multiple_col__active 1 -#define R_IRQ_MASK0_RD__multiple_col__inactive 0 -#define R_IRQ_MASK0_RD__single_col__BITNR 24 -#define R_IRQ_MASK0_RD__single_col__WIDTH 1 -#define R_IRQ_MASK0_RD__single_col__active 1 -#define R_IRQ_MASK0_RD__single_col__inactive 0 -#define R_IRQ_MASK0_RD__congestion__BITNR 23 -#define R_IRQ_MASK0_RD__congestion__WIDTH 1 -#define R_IRQ_MASK0_RD__congestion__active 1 -#define R_IRQ_MASK0_RD__congestion__inactive 0 -#define R_IRQ_MASK0_RD__oversize__BITNR 22 -#define R_IRQ_MASK0_RD__oversize__WIDTH 1 -#define R_IRQ_MASK0_RD__oversize__active 1 -#define R_IRQ_MASK0_RD__oversize__inactive 0 -#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 -#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_RD__alignment_error__active 1 -#define R_IRQ_MASK0_RD__alignment_error__inactive 0 -#define R_IRQ_MASK0_RD__crc_error__BITNR 20 -#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 -#define R_IRQ_MASK0_RD__crc_error__active 1 -#define R_IRQ_MASK0_RD__crc_error__inactive 0 -#define R_IRQ_MASK0_RD__overrun__BITNR 19 -#define R_IRQ_MASK0_RD__overrun__WIDTH 1 -#define R_IRQ_MASK0_RD__overrun__active 1 -#define R_IRQ_MASK0_RD__overrun__inactive 0 -#define R_IRQ_MASK0_RD__underrun__BITNR 18 -#define R_IRQ_MASK0_RD__underrun__WIDTH 1 -#define R_IRQ_MASK0_RD__underrun__active 1 -#define R_IRQ_MASK0_RD__underrun__inactive 0 -#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 -#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_RD__excessive_col__active 1 -#define R_IRQ_MASK0_RD__excessive_col__inactive 0 -#define R_IRQ_MASK0_RD__mdio__BITNR 16 -#define R_IRQ_MASK0_RD__mdio__WIDTH 1 -#define R_IRQ_MASK0_RD__mdio__active 1 -#define R_IRQ_MASK0_RD__mdio__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq3__active 1 -#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq2__active 1 -#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq1__active 1 -#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 -#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_drq0__active 1 -#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 -#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq3__active 1 -#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 -#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 -#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_peri__active 1 -#define R_IRQ_MASK0_RD__par0_peri__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq2__active 1 -#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 -#define R_IRQ_MASK0_RD__par0_data__BITNR 9 -#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_data__active 1 -#define R_IRQ_MASK0_RD__par0_data__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq1__active 1 -#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 -#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 -#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_RD__par0_ready__active 1 -#define R_IRQ_MASK0_RD__par0_ready__inactive 0 -#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_irq0__active 1 -#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 -#define R_IRQ_MASK0_RD__mio__BITNR 8 -#define R_IRQ_MASK0_RD__mio__WIDTH 1 -#define R_IRQ_MASK0_RD__mio__active 1 -#define R_IRQ_MASK0_RD__mio__inactive 0 -#define R_IRQ_MASK0_RD__scsi0__BITNR 8 -#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 -#define R_IRQ_MASK0_RD__scsi0__active 1 -#define R_IRQ_MASK0_RD__scsi0__inactive 0 -#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_RD__ata_dmaend__active 1 -#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 -#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma1__active 1 -#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 -#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_RD__ext_dma0__active 1 -#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 -#define R_IRQ_MASK0_RD__timer1__BITNR 1 -#define R_IRQ_MASK0_RD__timer1__WIDTH 1 -#define R_IRQ_MASK0_RD__timer1__active 1 -#define R_IRQ_MASK0_RD__timer1__inactive 0 -#define R_IRQ_MASK0_RD__timer0__BITNR 0 -#define R_IRQ_MASK0_RD__timer0__WIDTH 1 -#define R_IRQ_MASK0_RD__timer0__active 1 -#define R_IRQ_MASK0_RD__timer0__inactive 0 - -#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) -#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 -#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 -#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 -#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 -#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 -#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 -#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 -#define R_IRQ_MASK0_CLR__deferred__BITNR 27 -#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 -#define R_IRQ_MASK0_CLR__deferred__clr 1 -#define R_IRQ_MASK0_CLR__deferred__nop 0 -#define R_IRQ_MASK0_CLR__late_col__BITNR 26 -#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__late_col__clr 1 -#define R_IRQ_MASK0_CLR__late_col__nop 0 -#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 -#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__multiple_col__clr 1 -#define R_IRQ_MASK0_CLR__multiple_col__nop 0 -#define R_IRQ_MASK0_CLR__single_col__BITNR 24 -#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__single_col__clr 1 -#define R_IRQ_MASK0_CLR__single_col__nop 0 -#define R_IRQ_MASK0_CLR__congestion__BITNR 23 -#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 -#define R_IRQ_MASK0_CLR__congestion__clr 1 -#define R_IRQ_MASK0_CLR__congestion__nop 0 -#define R_IRQ_MASK0_CLR__oversize__BITNR 22 -#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 -#define R_IRQ_MASK0_CLR__oversize__clr 1 -#define R_IRQ_MASK0_CLR__oversize__nop 0 -#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 -#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__alignment_error__clr 1 -#define R_IRQ_MASK0_CLR__alignment_error__nop 0 -#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 -#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 -#define R_IRQ_MASK0_CLR__crc_error__clr 1 -#define R_IRQ_MASK0_CLR__crc_error__nop 0 -#define R_IRQ_MASK0_CLR__overrun__BITNR 19 -#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__overrun__clr 1 -#define R_IRQ_MASK0_CLR__overrun__nop 0 -#define R_IRQ_MASK0_CLR__underrun__BITNR 18 -#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 -#define R_IRQ_MASK0_CLR__underrun__clr 1 -#define R_IRQ_MASK0_CLR__underrun__nop 0 -#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 -#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_CLR__excessive_col__clr 1 -#define R_IRQ_MASK0_CLR__excessive_col__nop 0 -#define R_IRQ_MASK0_CLR__mdio__BITNR 16 -#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mdio__clr 1 -#define R_IRQ_MASK0_CLR__mdio__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 -#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 -#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 -#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 -#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_peri__clr 1 -#define R_IRQ_MASK0_CLR__par0_peri__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 -#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 -#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_data__clr 1 -#define R_IRQ_MASK0_CLR__par0_data__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 -#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 -#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_CLR__par0_ready__clr 1 -#define R_IRQ_MASK0_CLR__par0_ready__nop 0 -#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 -#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 -#define R_IRQ_MASK0_CLR__mio__BITNR 8 -#define R_IRQ_MASK0_CLR__mio__WIDTH 1 -#define R_IRQ_MASK0_CLR__mio__clr 1 -#define R_IRQ_MASK0_CLR__mio__nop 0 -#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 -#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 -#define R_IRQ_MASK0_CLR__scsi0__clr 1 -#define R_IRQ_MASK0_CLR__scsi0__nop 0 -#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 -#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 -#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 -#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 -#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 -#define R_IRQ_MASK0_CLR__timer1__BITNR 1 -#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer1__clr 1 -#define R_IRQ_MASK0_CLR__timer1__nop 0 -#define R_IRQ_MASK0_CLR__timer0__BITNR 0 -#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 -#define R_IRQ_MASK0_CLR__timer0__clr 1 -#define R_IRQ_MASK0_CLR__timer0__nop 0 - -#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) -#define R_IRQ_READ0__nmi_pin__BITNR 31 -#define R_IRQ_READ0__nmi_pin__WIDTH 1 -#define R_IRQ_READ0__nmi_pin__active 1 -#define R_IRQ_READ0__nmi_pin__inactive 0 -#define R_IRQ_READ0__watchdog_nmi__BITNR 30 -#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 -#define R_IRQ_READ0__watchdog_nmi__active 1 -#define R_IRQ_READ0__watchdog_nmi__inactive 0 -#define R_IRQ_READ0__sqe_test_error__BITNR 29 -#define R_IRQ_READ0__sqe_test_error__WIDTH 1 -#define R_IRQ_READ0__sqe_test_error__active 1 -#define R_IRQ_READ0__sqe_test_error__inactive 0 -#define R_IRQ_READ0__carrier_loss__BITNR 28 -#define R_IRQ_READ0__carrier_loss__WIDTH 1 -#define R_IRQ_READ0__carrier_loss__active 1 -#define R_IRQ_READ0__carrier_loss__inactive 0 -#define R_IRQ_READ0__deferred__BITNR 27 -#define R_IRQ_READ0__deferred__WIDTH 1 -#define R_IRQ_READ0__deferred__active 1 -#define R_IRQ_READ0__deferred__inactive 0 -#define R_IRQ_READ0__late_col__BITNR 26 -#define R_IRQ_READ0__late_col__WIDTH 1 -#define R_IRQ_READ0__late_col__active 1 -#define R_IRQ_READ0__late_col__inactive 0 -#define R_IRQ_READ0__multiple_col__BITNR 25 -#define R_IRQ_READ0__multiple_col__WIDTH 1 -#define R_IRQ_READ0__multiple_col__active 1 -#define R_IRQ_READ0__multiple_col__inactive 0 -#define R_IRQ_READ0__single_col__BITNR 24 -#define R_IRQ_READ0__single_col__WIDTH 1 -#define R_IRQ_READ0__single_col__active 1 -#define R_IRQ_READ0__single_col__inactive 0 -#define R_IRQ_READ0__congestion__BITNR 23 -#define R_IRQ_READ0__congestion__WIDTH 1 -#define R_IRQ_READ0__congestion__active 1 -#define R_IRQ_READ0__congestion__inactive 0 -#define R_IRQ_READ0__oversize__BITNR 22 -#define R_IRQ_READ0__oversize__WIDTH 1 -#define R_IRQ_READ0__oversize__active 1 -#define R_IRQ_READ0__oversize__inactive 0 -#define R_IRQ_READ0__alignment_error__BITNR 21 -#define R_IRQ_READ0__alignment_error__WIDTH 1 -#define R_IRQ_READ0__alignment_error__active 1 -#define R_IRQ_READ0__alignment_error__inactive 0 -#define R_IRQ_READ0__crc_error__BITNR 20 -#define R_IRQ_READ0__crc_error__WIDTH 1 -#define R_IRQ_READ0__crc_error__active 1 -#define R_IRQ_READ0__crc_error__inactive 0 -#define R_IRQ_READ0__overrun__BITNR 19 -#define R_IRQ_READ0__overrun__WIDTH 1 -#define R_IRQ_READ0__overrun__active 1 -#define R_IRQ_READ0__overrun__inactive 0 -#define R_IRQ_READ0__underrun__BITNR 18 -#define R_IRQ_READ0__underrun__WIDTH 1 -#define R_IRQ_READ0__underrun__active 1 -#define R_IRQ_READ0__underrun__inactive 0 -#define R_IRQ_READ0__excessive_col__BITNR 17 -#define R_IRQ_READ0__excessive_col__WIDTH 1 -#define R_IRQ_READ0__excessive_col__active 1 -#define R_IRQ_READ0__excessive_col__inactive 0 -#define R_IRQ_READ0__mdio__BITNR 16 -#define R_IRQ_READ0__mdio__WIDTH 1 -#define R_IRQ_READ0__mdio__active 1 -#define R_IRQ_READ0__mdio__inactive 0 -#define R_IRQ_READ0__ata_drq3__BITNR 15 -#define R_IRQ_READ0__ata_drq3__WIDTH 1 -#define R_IRQ_READ0__ata_drq3__active 1 -#define R_IRQ_READ0__ata_drq3__inactive 0 -#define R_IRQ_READ0__ata_drq2__BITNR 14 -#define R_IRQ_READ0__ata_drq2__WIDTH 1 -#define R_IRQ_READ0__ata_drq2__active 1 -#define R_IRQ_READ0__ata_drq2__inactive 0 -#define R_IRQ_READ0__ata_drq1__BITNR 13 -#define R_IRQ_READ0__ata_drq1__WIDTH 1 -#define R_IRQ_READ0__ata_drq1__active 1 -#define R_IRQ_READ0__ata_drq1__inactive 0 -#define R_IRQ_READ0__ata_drq0__BITNR 12 -#define R_IRQ_READ0__ata_drq0__WIDTH 1 -#define R_IRQ_READ0__ata_drq0__active 1 -#define R_IRQ_READ0__ata_drq0__inactive 0 -#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 -#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_READ0__par0_ecp_cmd__active 1 -#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 -#define R_IRQ_READ0__ata_irq3__BITNR 11 -#define R_IRQ_READ0__ata_irq3__WIDTH 1 -#define R_IRQ_READ0__ata_irq3__active 1 -#define R_IRQ_READ0__ata_irq3__inactive 0 -#define R_IRQ_READ0__par0_peri__BITNR 10 -#define R_IRQ_READ0__par0_peri__WIDTH 1 -#define R_IRQ_READ0__par0_peri__active 1 -#define R_IRQ_READ0__par0_peri__inactive 0 -#define R_IRQ_READ0__ata_irq2__BITNR 10 -#define R_IRQ_READ0__ata_irq2__WIDTH 1 -#define R_IRQ_READ0__ata_irq2__active 1 -#define R_IRQ_READ0__ata_irq2__inactive 0 -#define R_IRQ_READ0__par0_data__BITNR 9 -#define R_IRQ_READ0__par0_data__WIDTH 1 -#define R_IRQ_READ0__par0_data__active 1 -#define R_IRQ_READ0__par0_data__inactive 0 -#define R_IRQ_READ0__ata_irq1__BITNR 9 -#define R_IRQ_READ0__ata_irq1__WIDTH 1 -#define R_IRQ_READ0__ata_irq1__active 1 -#define R_IRQ_READ0__ata_irq1__inactive 0 -#define R_IRQ_READ0__par0_ready__BITNR 8 -#define R_IRQ_READ0__par0_ready__WIDTH 1 -#define R_IRQ_READ0__par0_ready__active 1 -#define R_IRQ_READ0__par0_ready__inactive 0 -#define R_IRQ_READ0__ata_irq0__BITNR 8 -#define R_IRQ_READ0__ata_irq0__WIDTH 1 -#define R_IRQ_READ0__ata_irq0__active 1 -#define R_IRQ_READ0__ata_irq0__inactive 0 -#define R_IRQ_READ0__mio__BITNR 8 -#define R_IRQ_READ0__mio__WIDTH 1 -#define R_IRQ_READ0__mio__active 1 -#define R_IRQ_READ0__mio__inactive 0 -#define R_IRQ_READ0__scsi0__BITNR 8 -#define R_IRQ_READ0__scsi0__WIDTH 1 -#define R_IRQ_READ0__scsi0__active 1 -#define R_IRQ_READ0__scsi0__inactive 0 -#define R_IRQ_READ0__ata_dmaend__BITNR 7 -#define R_IRQ_READ0__ata_dmaend__WIDTH 1 -#define R_IRQ_READ0__ata_dmaend__active 1 -#define R_IRQ_READ0__ata_dmaend__inactive 0 -#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_ext_vector_nr__active 1 -#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 -#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 -#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_READ0__irq_int_vector_nr__active 1 -#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 -#define R_IRQ_READ0__ext_dma1__BITNR 3 -#define R_IRQ_READ0__ext_dma1__WIDTH 1 -#define R_IRQ_READ0__ext_dma1__active 1 -#define R_IRQ_READ0__ext_dma1__inactive 0 -#define R_IRQ_READ0__ext_dma0__BITNR 2 -#define R_IRQ_READ0__ext_dma0__WIDTH 1 -#define R_IRQ_READ0__ext_dma0__active 1 -#define R_IRQ_READ0__ext_dma0__inactive 0 -#define R_IRQ_READ0__timer1__BITNR 1 -#define R_IRQ_READ0__timer1__WIDTH 1 -#define R_IRQ_READ0__timer1__active 1 -#define R_IRQ_READ0__timer1__inactive 0 -#define R_IRQ_READ0__timer0__BITNR 0 -#define R_IRQ_READ0__timer0__WIDTH 1 -#define R_IRQ_READ0__timer0__active 1 -#define R_IRQ_READ0__timer0__inactive 0 - -#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) -#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 -#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 -#define R_IRQ_MASK0_SET__nmi_pin__set 1 -#define R_IRQ_MASK0_SET__nmi_pin__nop 0 -#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 -#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 -#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 -#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 -#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 -#define R_IRQ_MASK0_SET__sqe_test_error__set 1 -#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 -#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 -#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 -#define R_IRQ_MASK0_SET__carrier_loss__set 1 -#define R_IRQ_MASK0_SET__carrier_loss__nop 0 -#define R_IRQ_MASK0_SET__deferred__BITNR 27 -#define R_IRQ_MASK0_SET__deferred__WIDTH 1 -#define R_IRQ_MASK0_SET__deferred__set 1 -#define R_IRQ_MASK0_SET__deferred__nop 0 -#define R_IRQ_MASK0_SET__late_col__BITNR 26 -#define R_IRQ_MASK0_SET__late_col__WIDTH 1 -#define R_IRQ_MASK0_SET__late_col__set 1 -#define R_IRQ_MASK0_SET__late_col__nop 0 -#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 -#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 -#define R_IRQ_MASK0_SET__multiple_col__set 1 -#define R_IRQ_MASK0_SET__multiple_col__nop 0 -#define R_IRQ_MASK0_SET__single_col__BITNR 24 -#define R_IRQ_MASK0_SET__single_col__WIDTH 1 -#define R_IRQ_MASK0_SET__single_col__set 1 -#define R_IRQ_MASK0_SET__single_col__nop 0 -#define R_IRQ_MASK0_SET__congestion__BITNR 23 -#define R_IRQ_MASK0_SET__congestion__WIDTH 1 -#define R_IRQ_MASK0_SET__congestion__set 1 -#define R_IRQ_MASK0_SET__congestion__nop 0 -#define R_IRQ_MASK0_SET__oversize__BITNR 22 -#define R_IRQ_MASK0_SET__oversize__WIDTH 1 -#define R_IRQ_MASK0_SET__oversize__set 1 -#define R_IRQ_MASK0_SET__oversize__nop 0 -#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 -#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 -#define R_IRQ_MASK0_SET__alignment_error__set 1 -#define R_IRQ_MASK0_SET__alignment_error__nop 0 -#define R_IRQ_MASK0_SET__crc_error__BITNR 20 -#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 -#define R_IRQ_MASK0_SET__crc_error__set 1 -#define R_IRQ_MASK0_SET__crc_error__nop 0 -#define R_IRQ_MASK0_SET__overrun__BITNR 19 -#define R_IRQ_MASK0_SET__overrun__WIDTH 1 -#define R_IRQ_MASK0_SET__overrun__set 1 -#define R_IRQ_MASK0_SET__overrun__nop 0 -#define R_IRQ_MASK0_SET__underrun__BITNR 18 -#define R_IRQ_MASK0_SET__underrun__WIDTH 1 -#define R_IRQ_MASK0_SET__underrun__set 1 -#define R_IRQ_MASK0_SET__underrun__nop 0 -#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 -#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 -#define R_IRQ_MASK0_SET__excessive_col__set 1 -#define R_IRQ_MASK0_SET__excessive_col__nop 0 -#define R_IRQ_MASK0_SET__mdio__BITNR 16 -#define R_IRQ_MASK0_SET__mdio__WIDTH 1 -#define R_IRQ_MASK0_SET__mdio__set 1 -#define R_IRQ_MASK0_SET__mdio__nop 0 -#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 -#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq3__set 1 -#define R_IRQ_MASK0_SET__ata_drq3__nop 0 -#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 -#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq2__set 1 -#define R_IRQ_MASK0_SET__ata_drq2__nop 0 -#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 -#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq1__set 1 -#define R_IRQ_MASK0_SET__ata_drq1__nop 0 -#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 -#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_drq0__set 1 -#define R_IRQ_MASK0_SET__ata_drq0__nop 0 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 -#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 -#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 -#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq3__set 1 -#define R_IRQ_MASK0_SET__ata_irq3__nop 0 -#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 -#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_peri__set 1 -#define R_IRQ_MASK0_SET__par0_peri__nop 0 -#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 -#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq2__set 1 -#define R_IRQ_MASK0_SET__ata_irq2__nop 0 -#define R_IRQ_MASK0_SET__par0_data__BITNR 9 -#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_data__set 1 -#define R_IRQ_MASK0_SET__par0_data__nop 0 -#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 -#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq1__set 1 -#define R_IRQ_MASK0_SET__ata_irq1__nop 0 -#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 -#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 -#define R_IRQ_MASK0_SET__par0_ready__set 1 -#define R_IRQ_MASK0_SET__par0_ready__nop 0 -#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 -#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_irq0__set 1 -#define R_IRQ_MASK0_SET__ata_irq0__nop 0 -#define R_IRQ_MASK0_SET__mio__BITNR 8 -#define R_IRQ_MASK0_SET__mio__WIDTH 1 -#define R_IRQ_MASK0_SET__mio__set 1 -#define R_IRQ_MASK0_SET__mio__nop 0 -#define R_IRQ_MASK0_SET__scsi0__BITNR 8 -#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 -#define R_IRQ_MASK0_SET__scsi0__set 1 -#define R_IRQ_MASK0_SET__scsi0__nop 0 -#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 -#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 -#define R_IRQ_MASK0_SET__ata_dmaend__set 1 -#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 -#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 -#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 -#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma1__set 1 -#define R_IRQ_MASK0_SET__ext_dma1__nop 0 -#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 -#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 -#define R_IRQ_MASK0_SET__ext_dma0__set 1 -#define R_IRQ_MASK0_SET__ext_dma0__nop 0 -#define R_IRQ_MASK0_SET__timer1__BITNR 1 -#define R_IRQ_MASK0_SET__timer1__WIDTH 1 -#define R_IRQ_MASK0_SET__timer1__set 1 -#define R_IRQ_MASK0_SET__timer1__nop 0 -#define R_IRQ_MASK0_SET__timer0__BITNR 0 -#define R_IRQ_MASK0_SET__timer0__WIDTH 1 -#define R_IRQ_MASK0_SET__timer0__set 1 -#define R_IRQ_MASK0_SET__timer0__nop 0 - -#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 -#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int7__active 1 -#define R_IRQ_MASK1_RD__sw_int7__inactive 0 -#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 -#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int6__active 1 -#define R_IRQ_MASK1_RD__sw_int6__inactive 0 -#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 -#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int5__active 1 -#define R_IRQ_MASK1_RD__sw_int5__inactive 0 -#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 -#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int4__active 1 -#define R_IRQ_MASK1_RD__sw_int4__inactive 0 -#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 -#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int3__active 1 -#define R_IRQ_MASK1_RD__sw_int3__inactive 0 -#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 -#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int2__active 1 -#define R_IRQ_MASK1_RD__sw_int2__inactive 0 -#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 -#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int1__active 1 -#define R_IRQ_MASK1_RD__sw_int1__inactive 0 -#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 -#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_RD__sw_int0__active 1 -#define R_IRQ_MASK1_RD__sw_int0__inactive 0 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 -#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 -#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 -#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_peri__active 1 -#define R_IRQ_MASK1_RD__par1_peri__inactive 0 -#define R_IRQ_MASK1_RD__par1_data__BITNR 17 -#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_data__active 1 -#define R_IRQ_MASK1_RD__par1_data__inactive 0 -#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 -#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__par1_ready__active 1 -#define R_IRQ_MASK1_RD__par1_ready__inactive 0 -#define R_IRQ_MASK1_RD__scsi1__BITNR 16 -#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 -#define R_IRQ_MASK1_RD__scsi1__active 1 -#define R_IRQ_MASK1_RD__scsi1__inactive 0 -#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_ready__active 1 -#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 -#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser3_data__active 1 -#define R_IRQ_MASK1_RD__ser3_data__inactive 0 -#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_ready__active 1 -#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 -#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser2_data__active 1 -#define R_IRQ_MASK1_RD__ser2_data__inactive 0 -#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_ready__active 1 -#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 -#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser1_data__active 1 -#define R_IRQ_MASK1_RD__ser1_data__inactive 0 -#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_ready__active 1 -#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 -#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 -#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_RD__ser0_data__active 1 -#define R_IRQ_MASK1_RD__ser0_data__inactive 0 -#define R_IRQ_MASK1_RD__pa7__BITNR 7 -#define R_IRQ_MASK1_RD__pa7__WIDTH 1 -#define R_IRQ_MASK1_RD__pa7__active 1 -#define R_IRQ_MASK1_RD__pa7__inactive 0 -#define R_IRQ_MASK1_RD__pa6__BITNR 6 -#define R_IRQ_MASK1_RD__pa6__WIDTH 1 -#define R_IRQ_MASK1_RD__pa6__active 1 -#define R_IRQ_MASK1_RD__pa6__inactive 0 -#define R_IRQ_MASK1_RD__pa5__BITNR 5 -#define R_IRQ_MASK1_RD__pa5__WIDTH 1 -#define R_IRQ_MASK1_RD__pa5__active 1 -#define R_IRQ_MASK1_RD__pa5__inactive 0 -#define R_IRQ_MASK1_RD__pa4__BITNR 4 -#define R_IRQ_MASK1_RD__pa4__WIDTH 1 -#define R_IRQ_MASK1_RD__pa4__active 1 -#define R_IRQ_MASK1_RD__pa4__inactive 0 -#define R_IRQ_MASK1_RD__pa3__BITNR 3 -#define R_IRQ_MASK1_RD__pa3__WIDTH 1 -#define R_IRQ_MASK1_RD__pa3__active 1 -#define R_IRQ_MASK1_RD__pa3__inactive 0 -#define R_IRQ_MASK1_RD__pa2__BITNR 2 -#define R_IRQ_MASK1_RD__pa2__WIDTH 1 -#define R_IRQ_MASK1_RD__pa2__active 1 -#define R_IRQ_MASK1_RD__pa2__inactive 0 -#define R_IRQ_MASK1_RD__pa1__BITNR 1 -#define R_IRQ_MASK1_RD__pa1__WIDTH 1 -#define R_IRQ_MASK1_RD__pa1__active 1 -#define R_IRQ_MASK1_RD__pa1__inactive 0 -#define R_IRQ_MASK1_RD__pa0__BITNR 0 -#define R_IRQ_MASK1_RD__pa0__WIDTH 1 -#define R_IRQ_MASK1_RD__pa0__active 1 -#define R_IRQ_MASK1_RD__pa0__inactive 0 - -#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) -#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 -#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int7__clr 1 -#define R_IRQ_MASK1_CLR__sw_int7__nop 0 -#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 -#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int6__clr 1 -#define R_IRQ_MASK1_CLR__sw_int6__nop 0 -#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 -#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int5__clr 1 -#define R_IRQ_MASK1_CLR__sw_int5__nop 0 -#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 -#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int4__clr 1 -#define R_IRQ_MASK1_CLR__sw_int4__nop 0 -#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 -#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int3__clr 1 -#define R_IRQ_MASK1_CLR__sw_int3__nop 0 -#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 -#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int2__clr 1 -#define R_IRQ_MASK1_CLR__sw_int2__nop 0 -#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 -#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int1__clr 1 -#define R_IRQ_MASK1_CLR__sw_int1__nop 0 -#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 -#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_CLR__sw_int0__clr 1 -#define R_IRQ_MASK1_CLR__sw_int0__nop 0 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 -#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 -#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_peri__clr 1 -#define R_IRQ_MASK1_CLR__par1_peri__nop 0 -#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 -#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_data__clr 1 -#define R_IRQ_MASK1_CLR__par1_data__nop 0 -#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 -#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__par1_ready__clr 1 -#define R_IRQ_MASK1_CLR__par1_ready__nop 0 -#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 -#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 -#define R_IRQ_MASK1_CLR__scsi1__clr 1 -#define R_IRQ_MASK1_CLR__scsi1__nop 0 -#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 -#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser3_data__clr 1 -#define R_IRQ_MASK1_CLR__ser3_data__nop 0 -#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 -#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser2_data__clr 1 -#define R_IRQ_MASK1_CLR__ser2_data__nop 0 -#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 -#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser1_data__clr 1 -#define R_IRQ_MASK1_CLR__ser1_data__nop 0 -#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 -#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 -#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 -#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_CLR__ser0_data__clr 1 -#define R_IRQ_MASK1_CLR__ser0_data__nop 0 -#define R_IRQ_MASK1_CLR__pa7__BITNR 7 -#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa7__clr 1 -#define R_IRQ_MASK1_CLR__pa7__nop 0 -#define R_IRQ_MASK1_CLR__pa6__BITNR 6 -#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa6__clr 1 -#define R_IRQ_MASK1_CLR__pa6__nop 0 -#define R_IRQ_MASK1_CLR__pa5__BITNR 5 -#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa5__clr 1 -#define R_IRQ_MASK1_CLR__pa5__nop 0 -#define R_IRQ_MASK1_CLR__pa4__BITNR 4 -#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa4__clr 1 -#define R_IRQ_MASK1_CLR__pa4__nop 0 -#define R_IRQ_MASK1_CLR__pa3__BITNR 3 -#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa3__clr 1 -#define R_IRQ_MASK1_CLR__pa3__nop 0 -#define R_IRQ_MASK1_CLR__pa2__BITNR 2 -#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa2__clr 1 -#define R_IRQ_MASK1_CLR__pa2__nop 0 -#define R_IRQ_MASK1_CLR__pa1__BITNR 1 -#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa1__clr 1 -#define R_IRQ_MASK1_CLR__pa1__nop 0 -#define R_IRQ_MASK1_CLR__pa0__BITNR 0 -#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 -#define R_IRQ_MASK1_CLR__pa0__clr 1 -#define R_IRQ_MASK1_CLR__pa0__nop 0 - -#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) -#define R_IRQ_READ1__sw_int7__BITNR 31 -#define R_IRQ_READ1__sw_int7__WIDTH 1 -#define R_IRQ_READ1__sw_int7__active 1 -#define R_IRQ_READ1__sw_int7__inactive 0 -#define R_IRQ_READ1__sw_int6__BITNR 30 -#define R_IRQ_READ1__sw_int6__WIDTH 1 -#define R_IRQ_READ1__sw_int6__active 1 -#define R_IRQ_READ1__sw_int6__inactive 0 -#define R_IRQ_READ1__sw_int5__BITNR 29 -#define R_IRQ_READ1__sw_int5__WIDTH 1 -#define R_IRQ_READ1__sw_int5__active 1 -#define R_IRQ_READ1__sw_int5__inactive 0 -#define R_IRQ_READ1__sw_int4__BITNR 28 -#define R_IRQ_READ1__sw_int4__WIDTH 1 -#define R_IRQ_READ1__sw_int4__active 1 -#define R_IRQ_READ1__sw_int4__inactive 0 -#define R_IRQ_READ1__sw_int3__BITNR 27 -#define R_IRQ_READ1__sw_int3__WIDTH 1 -#define R_IRQ_READ1__sw_int3__active 1 -#define R_IRQ_READ1__sw_int3__inactive 0 -#define R_IRQ_READ1__sw_int2__BITNR 26 -#define R_IRQ_READ1__sw_int2__WIDTH 1 -#define R_IRQ_READ1__sw_int2__active 1 -#define R_IRQ_READ1__sw_int2__inactive 0 -#define R_IRQ_READ1__sw_int1__BITNR 25 -#define R_IRQ_READ1__sw_int1__WIDTH 1 -#define R_IRQ_READ1__sw_int1__active 1 -#define R_IRQ_READ1__sw_int1__inactive 0 -#define R_IRQ_READ1__sw_int0__BITNR 24 -#define R_IRQ_READ1__sw_int0__WIDTH 1 -#define R_IRQ_READ1__sw_int0__active 1 -#define R_IRQ_READ1__sw_int0__inactive 0 -#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 -#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_READ1__par1_ecp_cmd__active 1 -#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 -#define R_IRQ_READ1__par1_peri__BITNR 18 -#define R_IRQ_READ1__par1_peri__WIDTH 1 -#define R_IRQ_READ1__par1_peri__active 1 -#define R_IRQ_READ1__par1_peri__inactive 0 -#define R_IRQ_READ1__par1_data__BITNR 17 -#define R_IRQ_READ1__par1_data__WIDTH 1 -#define R_IRQ_READ1__par1_data__active 1 -#define R_IRQ_READ1__par1_data__inactive 0 -#define R_IRQ_READ1__par1_ready__BITNR 16 -#define R_IRQ_READ1__par1_ready__WIDTH 1 -#define R_IRQ_READ1__par1_ready__active 1 -#define R_IRQ_READ1__par1_ready__inactive 0 -#define R_IRQ_READ1__scsi1__BITNR 16 -#define R_IRQ_READ1__scsi1__WIDTH 1 -#define R_IRQ_READ1__scsi1__active 1 -#define R_IRQ_READ1__scsi1__inactive 0 -#define R_IRQ_READ1__ser3_ready__BITNR 15 -#define R_IRQ_READ1__ser3_ready__WIDTH 1 -#define R_IRQ_READ1__ser3_ready__active 1 -#define R_IRQ_READ1__ser3_ready__inactive 0 -#define R_IRQ_READ1__ser3_data__BITNR 14 -#define R_IRQ_READ1__ser3_data__WIDTH 1 -#define R_IRQ_READ1__ser3_data__active 1 -#define R_IRQ_READ1__ser3_data__inactive 0 -#define R_IRQ_READ1__ser2_ready__BITNR 13 -#define R_IRQ_READ1__ser2_ready__WIDTH 1 -#define R_IRQ_READ1__ser2_ready__active 1 -#define R_IRQ_READ1__ser2_ready__inactive 0 -#define R_IRQ_READ1__ser2_data__BITNR 12 -#define R_IRQ_READ1__ser2_data__WIDTH 1 -#define R_IRQ_READ1__ser2_data__active 1 -#define R_IRQ_READ1__ser2_data__inactive 0 -#define R_IRQ_READ1__ser1_ready__BITNR 11 -#define R_IRQ_READ1__ser1_ready__WIDTH 1 -#define R_IRQ_READ1__ser1_ready__active 1 -#define R_IRQ_READ1__ser1_ready__inactive 0 -#define R_IRQ_READ1__ser1_data__BITNR 10 -#define R_IRQ_READ1__ser1_data__WIDTH 1 -#define R_IRQ_READ1__ser1_data__active 1 -#define R_IRQ_READ1__ser1_data__inactive 0 -#define R_IRQ_READ1__ser0_ready__BITNR 9 -#define R_IRQ_READ1__ser0_ready__WIDTH 1 -#define R_IRQ_READ1__ser0_ready__active 1 -#define R_IRQ_READ1__ser0_ready__inactive 0 -#define R_IRQ_READ1__ser0_data__BITNR 8 -#define R_IRQ_READ1__ser0_data__WIDTH 1 -#define R_IRQ_READ1__ser0_data__active 1 -#define R_IRQ_READ1__ser0_data__inactive 0 -#define R_IRQ_READ1__pa7__BITNR 7 -#define R_IRQ_READ1__pa7__WIDTH 1 -#define R_IRQ_READ1__pa7__active 1 -#define R_IRQ_READ1__pa7__inactive 0 -#define R_IRQ_READ1__pa6__BITNR 6 -#define R_IRQ_READ1__pa6__WIDTH 1 -#define R_IRQ_READ1__pa6__active 1 -#define R_IRQ_READ1__pa6__inactive 0 -#define R_IRQ_READ1__pa5__BITNR 5 -#define R_IRQ_READ1__pa5__WIDTH 1 -#define R_IRQ_READ1__pa5__active 1 -#define R_IRQ_READ1__pa5__inactive 0 -#define R_IRQ_READ1__pa4__BITNR 4 -#define R_IRQ_READ1__pa4__WIDTH 1 -#define R_IRQ_READ1__pa4__active 1 -#define R_IRQ_READ1__pa4__inactive 0 -#define R_IRQ_READ1__pa3__BITNR 3 -#define R_IRQ_READ1__pa3__WIDTH 1 -#define R_IRQ_READ1__pa3__active 1 -#define R_IRQ_READ1__pa3__inactive 0 -#define R_IRQ_READ1__pa2__BITNR 2 -#define R_IRQ_READ1__pa2__WIDTH 1 -#define R_IRQ_READ1__pa2__active 1 -#define R_IRQ_READ1__pa2__inactive 0 -#define R_IRQ_READ1__pa1__BITNR 1 -#define R_IRQ_READ1__pa1__WIDTH 1 -#define R_IRQ_READ1__pa1__active 1 -#define R_IRQ_READ1__pa1__inactive 0 -#define R_IRQ_READ1__pa0__BITNR 0 -#define R_IRQ_READ1__pa0__WIDTH 1 -#define R_IRQ_READ1__pa0__active 1 -#define R_IRQ_READ1__pa0__inactive 0 - -#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) -#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 -#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int7__set 1 -#define R_IRQ_MASK1_SET__sw_int7__nop 0 -#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 -#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int6__set 1 -#define R_IRQ_MASK1_SET__sw_int6__nop 0 -#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 -#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int5__set 1 -#define R_IRQ_MASK1_SET__sw_int5__nop 0 -#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 -#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int4__set 1 -#define R_IRQ_MASK1_SET__sw_int4__nop 0 -#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 -#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int3__set 1 -#define R_IRQ_MASK1_SET__sw_int3__nop 0 -#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 -#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int2__set 1 -#define R_IRQ_MASK1_SET__sw_int2__nop 0 -#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 -#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int1__set 1 -#define R_IRQ_MASK1_SET__sw_int1__nop 0 -#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 -#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 -#define R_IRQ_MASK1_SET__sw_int0__set 1 -#define R_IRQ_MASK1_SET__sw_int0__nop 0 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 -#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 -#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 -#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_peri__set 1 -#define R_IRQ_MASK1_SET__par1_peri__nop 0 -#define R_IRQ_MASK1_SET__par1_data__BITNR 17 -#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_data__set 1 -#define R_IRQ_MASK1_SET__par1_data__nop 0 -#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 -#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__par1_ready__set 1 -#define R_IRQ_MASK1_SET__par1_ready__nop 0 -#define R_IRQ_MASK1_SET__scsi1__BITNR 16 -#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 -#define R_IRQ_MASK1_SET__scsi1__set 1 -#define R_IRQ_MASK1_SET__scsi1__nop 0 -#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 -#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_ready__set 1 -#define R_IRQ_MASK1_SET__ser3_ready__nop 0 -#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 -#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser3_data__set 1 -#define R_IRQ_MASK1_SET__ser3_data__nop 0 -#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 -#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_ready__set 1 -#define R_IRQ_MASK1_SET__ser2_ready__nop 0 -#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 -#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser2_data__set 1 -#define R_IRQ_MASK1_SET__ser2_data__nop 0 -#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 -#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_ready__set 1 -#define R_IRQ_MASK1_SET__ser1_ready__nop 0 -#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 -#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser1_data__set 1 -#define R_IRQ_MASK1_SET__ser1_data__nop 0 -#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 -#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_ready__set 1 -#define R_IRQ_MASK1_SET__ser0_ready__nop 0 -#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 -#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 -#define R_IRQ_MASK1_SET__ser0_data__set 1 -#define R_IRQ_MASK1_SET__ser0_data__nop 0 -#define R_IRQ_MASK1_SET__pa7__BITNR 7 -#define R_IRQ_MASK1_SET__pa7__WIDTH 1 -#define R_IRQ_MASK1_SET__pa7__set 1 -#define R_IRQ_MASK1_SET__pa7__nop 0 -#define R_IRQ_MASK1_SET__pa6__BITNR 6 -#define R_IRQ_MASK1_SET__pa6__WIDTH 1 -#define R_IRQ_MASK1_SET__pa6__set 1 -#define R_IRQ_MASK1_SET__pa6__nop 0 -#define R_IRQ_MASK1_SET__pa5__BITNR 5 -#define R_IRQ_MASK1_SET__pa5__WIDTH 1 -#define R_IRQ_MASK1_SET__pa5__set 1 -#define R_IRQ_MASK1_SET__pa5__nop 0 -#define R_IRQ_MASK1_SET__pa4__BITNR 4 -#define R_IRQ_MASK1_SET__pa4__WIDTH 1 -#define R_IRQ_MASK1_SET__pa4__set 1 -#define R_IRQ_MASK1_SET__pa4__nop 0 -#define R_IRQ_MASK1_SET__pa3__BITNR 3 -#define R_IRQ_MASK1_SET__pa3__WIDTH 1 -#define R_IRQ_MASK1_SET__pa3__set 1 -#define R_IRQ_MASK1_SET__pa3__nop 0 -#define R_IRQ_MASK1_SET__pa2__BITNR 2 -#define R_IRQ_MASK1_SET__pa2__WIDTH 1 -#define R_IRQ_MASK1_SET__pa2__set 1 -#define R_IRQ_MASK1_SET__pa2__nop 0 -#define R_IRQ_MASK1_SET__pa1__BITNR 1 -#define R_IRQ_MASK1_SET__pa1__WIDTH 1 -#define R_IRQ_MASK1_SET__pa1__set 1 -#define R_IRQ_MASK1_SET__pa1__nop 0 -#define R_IRQ_MASK1_SET__pa0__BITNR 0 -#define R_IRQ_MASK1_SET__pa0__WIDTH 1 -#define R_IRQ_MASK1_SET__pa0__set 1 -#define R_IRQ_MASK1_SET__pa0__nop 0 - -#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_eop__active 1 -#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma9_descr__active 1 -#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_eop__active 1 -#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma8_descr__active 1 -#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_eop__active 1 -#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma7_descr__active 1 -#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_eop__active 1 -#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma6_descr__active 1 -#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_eop__active 1 -#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma5_descr__active 1 -#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_eop__active 1 -#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma4_descr__active 1 -#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_eop__active 1 -#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma3_descr__active 1 -#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_eop__active 1 -#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma2_descr__active 1 -#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_eop__active 1 -#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma1_descr__active 1 -#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 -#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_eop__active 1 -#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 -#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_RD__dma0_descr__active 1 -#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 -#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 -#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 -#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 -#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 - -#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) -#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 -#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub3_descr__active 1 -#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 -#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub2_descr__active 1 -#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 -#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub1_descr__active 1 -#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 -#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 -#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_sub0_descr__active 1 -#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 -#define R_IRQ_READ2__dma9_eop__BITNR 19 -#define R_IRQ_READ2__dma9_eop__WIDTH 1 -#define R_IRQ_READ2__dma9_eop__active 1 -#define R_IRQ_READ2__dma9_eop__inactive 0 -#define R_IRQ_READ2__dma9_descr__BITNR 18 -#define R_IRQ_READ2__dma9_descr__WIDTH 1 -#define R_IRQ_READ2__dma9_descr__active 1 -#define R_IRQ_READ2__dma9_descr__inactive 0 -#define R_IRQ_READ2__dma8_eop__BITNR 17 -#define R_IRQ_READ2__dma8_eop__WIDTH 1 -#define R_IRQ_READ2__dma8_eop__active 1 -#define R_IRQ_READ2__dma8_eop__inactive 0 -#define R_IRQ_READ2__dma8_descr__BITNR 16 -#define R_IRQ_READ2__dma8_descr__WIDTH 1 -#define R_IRQ_READ2__dma8_descr__active 1 -#define R_IRQ_READ2__dma8_descr__inactive 0 -#define R_IRQ_READ2__dma7_eop__BITNR 15 -#define R_IRQ_READ2__dma7_eop__WIDTH 1 -#define R_IRQ_READ2__dma7_eop__active 1 -#define R_IRQ_READ2__dma7_eop__inactive 0 -#define R_IRQ_READ2__dma7_descr__BITNR 14 -#define R_IRQ_READ2__dma7_descr__WIDTH 1 -#define R_IRQ_READ2__dma7_descr__active 1 -#define R_IRQ_READ2__dma7_descr__inactive 0 -#define R_IRQ_READ2__dma6_eop__BITNR 13 -#define R_IRQ_READ2__dma6_eop__WIDTH 1 -#define R_IRQ_READ2__dma6_eop__active 1 -#define R_IRQ_READ2__dma6_eop__inactive 0 -#define R_IRQ_READ2__dma6_descr__BITNR 12 -#define R_IRQ_READ2__dma6_descr__WIDTH 1 -#define R_IRQ_READ2__dma6_descr__active 1 -#define R_IRQ_READ2__dma6_descr__inactive 0 -#define R_IRQ_READ2__dma5_eop__BITNR 11 -#define R_IRQ_READ2__dma5_eop__WIDTH 1 -#define R_IRQ_READ2__dma5_eop__active 1 -#define R_IRQ_READ2__dma5_eop__inactive 0 -#define R_IRQ_READ2__dma5_descr__BITNR 10 -#define R_IRQ_READ2__dma5_descr__WIDTH 1 -#define R_IRQ_READ2__dma5_descr__active 1 -#define R_IRQ_READ2__dma5_descr__inactive 0 -#define R_IRQ_READ2__dma4_eop__BITNR 9 -#define R_IRQ_READ2__dma4_eop__WIDTH 1 -#define R_IRQ_READ2__dma4_eop__active 1 -#define R_IRQ_READ2__dma4_eop__inactive 0 -#define R_IRQ_READ2__dma4_descr__BITNR 8 -#define R_IRQ_READ2__dma4_descr__WIDTH 1 -#define R_IRQ_READ2__dma4_descr__active 1 -#define R_IRQ_READ2__dma4_descr__inactive 0 -#define R_IRQ_READ2__dma3_eop__BITNR 7 -#define R_IRQ_READ2__dma3_eop__WIDTH 1 -#define R_IRQ_READ2__dma3_eop__active 1 -#define R_IRQ_READ2__dma3_eop__inactive 0 -#define R_IRQ_READ2__dma3_descr__BITNR 6 -#define R_IRQ_READ2__dma3_descr__WIDTH 1 -#define R_IRQ_READ2__dma3_descr__active 1 -#define R_IRQ_READ2__dma3_descr__inactive 0 -#define R_IRQ_READ2__dma2_eop__BITNR 5 -#define R_IRQ_READ2__dma2_eop__WIDTH 1 -#define R_IRQ_READ2__dma2_eop__active 1 -#define R_IRQ_READ2__dma2_eop__inactive 0 -#define R_IRQ_READ2__dma2_descr__BITNR 4 -#define R_IRQ_READ2__dma2_descr__WIDTH 1 -#define R_IRQ_READ2__dma2_descr__active 1 -#define R_IRQ_READ2__dma2_descr__inactive 0 -#define R_IRQ_READ2__dma1_eop__BITNR 3 -#define R_IRQ_READ2__dma1_eop__WIDTH 1 -#define R_IRQ_READ2__dma1_eop__active 1 -#define R_IRQ_READ2__dma1_eop__inactive 0 -#define R_IRQ_READ2__dma1_descr__BITNR 2 -#define R_IRQ_READ2__dma1_descr__WIDTH 1 -#define R_IRQ_READ2__dma1_descr__active 1 -#define R_IRQ_READ2__dma1_descr__inactive 0 -#define R_IRQ_READ2__dma0_eop__BITNR 1 -#define R_IRQ_READ2__dma0_eop__WIDTH 1 -#define R_IRQ_READ2__dma0_eop__active 1 -#define R_IRQ_READ2__dma0_eop__inactive 0 -#define R_IRQ_READ2__dma0_descr__BITNR 0 -#define R_IRQ_READ2__dma0_descr__WIDTH 1 -#define R_IRQ_READ2__dma0_descr__active 1 -#define R_IRQ_READ2__dma0_descr__inactive 0 - -#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) -#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 -#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 -#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_eop__set 1 -#define R_IRQ_MASK2_SET__dma9_eop__nop 0 -#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 -#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma9_descr__set 1 -#define R_IRQ_MASK2_SET__dma9_descr__nop 0 -#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 -#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_eop__set 1 -#define R_IRQ_MASK2_SET__dma8_eop__nop 0 -#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 -#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma8_descr__set 1 -#define R_IRQ_MASK2_SET__dma8_descr__nop 0 -#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 -#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_eop__set 1 -#define R_IRQ_MASK2_SET__dma7_eop__nop 0 -#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 -#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma7_descr__set 1 -#define R_IRQ_MASK2_SET__dma7_descr__nop 0 -#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 -#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_eop__set 1 -#define R_IRQ_MASK2_SET__dma6_eop__nop 0 -#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 -#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma6_descr__set 1 -#define R_IRQ_MASK2_SET__dma6_descr__nop 0 -#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 -#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_eop__set 1 -#define R_IRQ_MASK2_SET__dma5_eop__nop 0 -#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 -#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma5_descr__set 1 -#define R_IRQ_MASK2_SET__dma5_descr__nop 0 -#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 -#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_eop__set 1 -#define R_IRQ_MASK2_SET__dma4_eop__nop 0 -#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 -#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma4_descr__set 1 -#define R_IRQ_MASK2_SET__dma4_descr__nop 0 -#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 -#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_eop__set 1 -#define R_IRQ_MASK2_SET__dma3_eop__nop 0 -#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 -#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma3_descr__set 1 -#define R_IRQ_MASK2_SET__dma3_descr__nop 0 -#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 -#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_eop__set 1 -#define R_IRQ_MASK2_SET__dma2_eop__nop 0 -#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 -#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma2_descr__set 1 -#define R_IRQ_MASK2_SET__dma2_descr__nop 0 -#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 -#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_eop__set 1 -#define R_IRQ_MASK2_SET__dma1_eop__nop 0 -#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 -#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma1_descr__set 1 -#define R_IRQ_MASK2_SET__dma1_descr__nop 0 -#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 -#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_eop__set 1 -#define R_IRQ_MASK2_SET__dma0_eop__nop 0 -#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 -#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 -#define R_IRQ_MASK2_SET__dma0_descr__set 1 -#define R_IRQ_MASK2_SET__dma0_descr__nop 0 - -#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) -#define R_VECT_MASK_RD__usb__BITNR 31 -#define R_VECT_MASK_RD__usb__WIDTH 1 -#define R_VECT_MASK_RD__usb__active 1 -#define R_VECT_MASK_RD__usb__inactive 0 -#define R_VECT_MASK_RD__dma9__BITNR 25 -#define R_VECT_MASK_RD__dma9__WIDTH 1 -#define R_VECT_MASK_RD__dma9__active 1 -#define R_VECT_MASK_RD__dma9__inactive 0 -#define R_VECT_MASK_RD__dma8__BITNR 24 -#define R_VECT_MASK_RD__dma8__WIDTH 1 -#define R_VECT_MASK_RD__dma8__active 1 -#define R_VECT_MASK_RD__dma8__inactive 0 -#define R_VECT_MASK_RD__dma7__BITNR 23 -#define R_VECT_MASK_RD__dma7__WIDTH 1 -#define R_VECT_MASK_RD__dma7__active 1 -#define R_VECT_MASK_RD__dma7__inactive 0 -#define R_VECT_MASK_RD__dma6__BITNR 22 -#define R_VECT_MASK_RD__dma6__WIDTH 1 -#define R_VECT_MASK_RD__dma6__active 1 -#define R_VECT_MASK_RD__dma6__inactive 0 -#define R_VECT_MASK_RD__dma5__BITNR 21 -#define R_VECT_MASK_RD__dma5__WIDTH 1 -#define R_VECT_MASK_RD__dma5__active 1 -#define R_VECT_MASK_RD__dma5__inactive 0 -#define R_VECT_MASK_RD__dma4__BITNR 20 -#define R_VECT_MASK_RD__dma4__WIDTH 1 -#define R_VECT_MASK_RD__dma4__active 1 -#define R_VECT_MASK_RD__dma4__inactive 0 -#define R_VECT_MASK_RD__dma3__BITNR 19 -#define R_VECT_MASK_RD__dma3__WIDTH 1 -#define R_VECT_MASK_RD__dma3__active 1 -#define R_VECT_MASK_RD__dma3__inactive 0 -#define R_VECT_MASK_RD__dma2__BITNR 18 -#define R_VECT_MASK_RD__dma2__WIDTH 1 -#define R_VECT_MASK_RD__dma2__active 1 -#define R_VECT_MASK_RD__dma2__inactive 0 -#define R_VECT_MASK_RD__dma1__BITNR 17 -#define R_VECT_MASK_RD__dma1__WIDTH 1 -#define R_VECT_MASK_RD__dma1__active 1 -#define R_VECT_MASK_RD__dma1__inactive 0 -#define R_VECT_MASK_RD__dma0__BITNR 16 -#define R_VECT_MASK_RD__dma0__WIDTH 1 -#define R_VECT_MASK_RD__dma0__active 1 -#define R_VECT_MASK_RD__dma0__inactive 0 -#define R_VECT_MASK_RD__ext_dma1__BITNR 13 -#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma1__active 1 -#define R_VECT_MASK_RD__ext_dma1__inactive 0 -#define R_VECT_MASK_RD__ext_dma0__BITNR 12 -#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 -#define R_VECT_MASK_RD__ext_dma0__active 1 -#define R_VECT_MASK_RD__ext_dma0__inactive 0 -#define R_VECT_MASK_RD__pa__BITNR 11 -#define R_VECT_MASK_RD__pa__WIDTH 1 -#define R_VECT_MASK_RD__pa__active 1 -#define R_VECT_MASK_RD__pa__inactive 0 -#define R_VECT_MASK_RD__irq_intnr__BITNR 10 -#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 -#define R_VECT_MASK_RD__irq_intnr__active 1 -#define R_VECT_MASK_RD__irq_intnr__inactive 0 -#define R_VECT_MASK_RD__sw__BITNR 9 -#define R_VECT_MASK_RD__sw__WIDTH 1 -#define R_VECT_MASK_RD__sw__active 1 -#define R_VECT_MASK_RD__sw__inactive 0 -#define R_VECT_MASK_RD__serial__BITNR 8 -#define R_VECT_MASK_RD__serial__WIDTH 1 -#define R_VECT_MASK_RD__serial__active 1 -#define R_VECT_MASK_RD__serial__inactive 0 -#define R_VECT_MASK_RD__snmp__BITNR 7 -#define R_VECT_MASK_RD__snmp__WIDTH 1 -#define R_VECT_MASK_RD__snmp__active 1 -#define R_VECT_MASK_RD__snmp__inactive 0 -#define R_VECT_MASK_RD__network__BITNR 6 -#define R_VECT_MASK_RD__network__WIDTH 1 -#define R_VECT_MASK_RD__network__active 1 -#define R_VECT_MASK_RD__network__inactive 0 -#define R_VECT_MASK_RD__scsi1__BITNR 5 -#define R_VECT_MASK_RD__scsi1__WIDTH 1 -#define R_VECT_MASK_RD__scsi1__active 1 -#define R_VECT_MASK_RD__scsi1__inactive 0 -#define R_VECT_MASK_RD__par1__BITNR 5 -#define R_VECT_MASK_RD__par1__WIDTH 1 -#define R_VECT_MASK_RD__par1__active 1 -#define R_VECT_MASK_RD__par1__inactive 0 -#define R_VECT_MASK_RD__scsi0__BITNR 4 -#define R_VECT_MASK_RD__scsi0__WIDTH 1 -#define R_VECT_MASK_RD__scsi0__active 1 -#define R_VECT_MASK_RD__scsi0__inactive 0 -#define R_VECT_MASK_RD__par0__BITNR 4 -#define R_VECT_MASK_RD__par0__WIDTH 1 -#define R_VECT_MASK_RD__par0__active 1 -#define R_VECT_MASK_RD__par0__inactive 0 -#define R_VECT_MASK_RD__ata__BITNR 4 -#define R_VECT_MASK_RD__ata__WIDTH 1 -#define R_VECT_MASK_RD__ata__active 1 -#define R_VECT_MASK_RD__ata__inactive 0 -#define R_VECT_MASK_RD__mio__BITNR 4 -#define R_VECT_MASK_RD__mio__WIDTH 1 -#define R_VECT_MASK_RD__mio__active 1 -#define R_VECT_MASK_RD__mio__inactive 0 -#define R_VECT_MASK_RD__timer1__BITNR 3 -#define R_VECT_MASK_RD__timer1__WIDTH 1 -#define R_VECT_MASK_RD__timer1__active 1 -#define R_VECT_MASK_RD__timer1__inactive 0 -#define R_VECT_MASK_RD__timer0__BITNR 2 -#define R_VECT_MASK_RD__timer0__WIDTH 1 -#define R_VECT_MASK_RD__timer0__active 1 -#define R_VECT_MASK_RD__timer0__inactive 0 -#define R_VECT_MASK_RD__nmi__BITNR 1 -#define R_VECT_MASK_RD__nmi__WIDTH 1 -#define R_VECT_MASK_RD__nmi__active 1 -#define R_VECT_MASK_RD__nmi__inactive 0 -#define R_VECT_MASK_RD__some__BITNR 0 -#define R_VECT_MASK_RD__some__WIDTH 1 -#define R_VECT_MASK_RD__some__active 1 -#define R_VECT_MASK_RD__some__inactive 0 - -#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) -#define R_VECT_MASK_CLR__usb__BITNR 31 -#define R_VECT_MASK_CLR__usb__WIDTH 1 -#define R_VECT_MASK_CLR__usb__clr 1 -#define R_VECT_MASK_CLR__usb__nop 0 -#define R_VECT_MASK_CLR__dma9__BITNR 25 -#define R_VECT_MASK_CLR__dma9__WIDTH 1 -#define R_VECT_MASK_CLR__dma9__clr 1 -#define R_VECT_MASK_CLR__dma9__nop 0 -#define R_VECT_MASK_CLR__dma8__BITNR 24 -#define R_VECT_MASK_CLR__dma8__WIDTH 1 -#define R_VECT_MASK_CLR__dma8__clr 1 -#define R_VECT_MASK_CLR__dma8__nop 0 -#define R_VECT_MASK_CLR__dma7__BITNR 23 -#define R_VECT_MASK_CLR__dma7__WIDTH 1 -#define R_VECT_MASK_CLR__dma7__clr 1 -#define R_VECT_MASK_CLR__dma7__nop 0 -#define R_VECT_MASK_CLR__dma6__BITNR 22 -#define R_VECT_MASK_CLR__dma6__WIDTH 1 -#define R_VECT_MASK_CLR__dma6__clr 1 -#define R_VECT_MASK_CLR__dma6__nop 0 -#define R_VECT_MASK_CLR__dma5__BITNR 21 -#define R_VECT_MASK_CLR__dma5__WIDTH 1 -#define R_VECT_MASK_CLR__dma5__clr 1 -#define R_VECT_MASK_CLR__dma5__nop 0 -#define R_VECT_MASK_CLR__dma4__BITNR 20 -#define R_VECT_MASK_CLR__dma4__WIDTH 1 -#define R_VECT_MASK_CLR__dma4__clr 1 -#define R_VECT_MASK_CLR__dma4__nop 0 -#define R_VECT_MASK_CLR__dma3__BITNR 19 -#define R_VECT_MASK_CLR__dma3__WIDTH 1 -#define R_VECT_MASK_CLR__dma3__clr 1 -#define R_VECT_MASK_CLR__dma3__nop 0 -#define R_VECT_MASK_CLR__dma2__BITNR 18 -#define R_VECT_MASK_CLR__dma2__WIDTH 1 -#define R_VECT_MASK_CLR__dma2__clr 1 -#define R_VECT_MASK_CLR__dma2__nop 0 -#define R_VECT_MASK_CLR__dma1__BITNR 17 -#define R_VECT_MASK_CLR__dma1__WIDTH 1 -#define R_VECT_MASK_CLR__dma1__clr 1 -#define R_VECT_MASK_CLR__dma1__nop 0 -#define R_VECT_MASK_CLR__dma0__BITNR 16 -#define R_VECT_MASK_CLR__dma0__WIDTH 1 -#define R_VECT_MASK_CLR__dma0__clr 1 -#define R_VECT_MASK_CLR__dma0__nop 0 -#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 -#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma1__clr 1 -#define R_VECT_MASK_CLR__ext_dma1__nop 0 -#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 -#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 -#define R_VECT_MASK_CLR__ext_dma0__clr 1 -#define R_VECT_MASK_CLR__ext_dma0__nop 0 -#define R_VECT_MASK_CLR__pa__BITNR 11 -#define R_VECT_MASK_CLR__pa__WIDTH 1 -#define R_VECT_MASK_CLR__pa__clr 1 -#define R_VECT_MASK_CLR__pa__nop 0 -#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 -#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 -#define R_VECT_MASK_CLR__irq_intnr__clr 1 -#define R_VECT_MASK_CLR__irq_intnr__nop 0 -#define R_VECT_MASK_CLR__sw__BITNR 9 -#define R_VECT_MASK_CLR__sw__WIDTH 1 -#define R_VECT_MASK_CLR__sw__clr 1 -#define R_VECT_MASK_CLR__sw__nop 0 -#define R_VECT_MASK_CLR__serial__BITNR 8 -#define R_VECT_MASK_CLR__serial__WIDTH 1 -#define R_VECT_MASK_CLR__serial__clr 1 -#define R_VECT_MASK_CLR__serial__nop 0 -#define R_VECT_MASK_CLR__snmp__BITNR 7 -#define R_VECT_MASK_CLR__snmp__WIDTH 1 -#define R_VECT_MASK_CLR__snmp__clr 1 -#define R_VECT_MASK_CLR__snmp__nop 0 -#define R_VECT_MASK_CLR__network__BITNR 6 -#define R_VECT_MASK_CLR__network__WIDTH 1 -#define R_VECT_MASK_CLR__network__clr 1 -#define R_VECT_MASK_CLR__network__nop 0 -#define R_VECT_MASK_CLR__scsi1__BITNR 5 -#define R_VECT_MASK_CLR__scsi1__WIDTH 1 -#define R_VECT_MASK_CLR__scsi1__clr 1 -#define R_VECT_MASK_CLR__scsi1__nop 0 -#define R_VECT_MASK_CLR__par1__BITNR 5 -#define R_VECT_MASK_CLR__par1__WIDTH 1 -#define R_VECT_MASK_CLR__par1__clr 1 -#define R_VECT_MASK_CLR__par1__nop 0 -#define R_VECT_MASK_CLR__scsi0__BITNR 4 -#define R_VECT_MASK_CLR__scsi0__WIDTH 1 -#define R_VECT_MASK_CLR__scsi0__clr 1 -#define R_VECT_MASK_CLR__scsi0__nop 0 -#define R_VECT_MASK_CLR__par0__BITNR 4 -#define R_VECT_MASK_CLR__par0__WIDTH 1 -#define R_VECT_MASK_CLR__par0__clr 1 -#define R_VECT_MASK_CLR__par0__nop 0 -#define R_VECT_MASK_CLR__ata__BITNR 4 -#define R_VECT_MASK_CLR__ata__WIDTH 1 -#define R_VECT_MASK_CLR__ata__clr 1 -#define R_VECT_MASK_CLR__ata__nop 0 -#define R_VECT_MASK_CLR__mio__BITNR 4 -#define R_VECT_MASK_CLR__mio__WIDTH 1 -#define R_VECT_MASK_CLR__mio__clr 1 -#define R_VECT_MASK_CLR__mio__nop 0 -#define R_VECT_MASK_CLR__timer1__BITNR 3 -#define R_VECT_MASK_CLR__timer1__WIDTH 1 -#define R_VECT_MASK_CLR__timer1__clr 1 -#define R_VECT_MASK_CLR__timer1__nop 0 -#define R_VECT_MASK_CLR__timer0__BITNR 2 -#define R_VECT_MASK_CLR__timer0__WIDTH 1 -#define R_VECT_MASK_CLR__timer0__clr 1 -#define R_VECT_MASK_CLR__timer0__nop 0 -#define R_VECT_MASK_CLR__nmi__BITNR 1 -#define R_VECT_MASK_CLR__nmi__WIDTH 1 -#define R_VECT_MASK_CLR__nmi__clr 1 -#define R_VECT_MASK_CLR__nmi__nop 0 -#define R_VECT_MASK_CLR__some__BITNR 0 -#define R_VECT_MASK_CLR__some__WIDTH 1 -#define R_VECT_MASK_CLR__some__clr 1 -#define R_VECT_MASK_CLR__some__nop 0 - -#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) -#define R_VECT_READ__usb__BITNR 31 -#define R_VECT_READ__usb__WIDTH 1 -#define R_VECT_READ__usb__active 1 -#define R_VECT_READ__usb__inactive 0 -#define R_VECT_READ__dma9__BITNR 25 -#define R_VECT_READ__dma9__WIDTH 1 -#define R_VECT_READ__dma9__active 1 -#define R_VECT_READ__dma9__inactive 0 -#define R_VECT_READ__dma8__BITNR 24 -#define R_VECT_READ__dma8__WIDTH 1 -#define R_VECT_READ__dma8__active 1 -#define R_VECT_READ__dma8__inactive 0 -#define R_VECT_READ__dma7__BITNR 23 -#define R_VECT_READ__dma7__WIDTH 1 -#define R_VECT_READ__dma7__active 1 -#define R_VECT_READ__dma7__inactive 0 -#define R_VECT_READ__dma6__BITNR 22 -#define R_VECT_READ__dma6__WIDTH 1 -#define R_VECT_READ__dma6__active 1 -#define R_VECT_READ__dma6__inactive 0 -#define R_VECT_READ__dma5__BITNR 21 -#define R_VECT_READ__dma5__WIDTH 1 -#define R_VECT_READ__dma5__active 1 -#define R_VECT_READ__dma5__inactive 0 -#define R_VECT_READ__dma4__BITNR 20 -#define R_VECT_READ__dma4__WIDTH 1 -#define R_VECT_READ__dma4__active 1 -#define R_VECT_READ__dma4__inactive 0 -#define R_VECT_READ__dma3__BITNR 19 -#define R_VECT_READ__dma3__WIDTH 1 -#define R_VECT_READ__dma3__active 1 -#define R_VECT_READ__dma3__inactive 0 -#define R_VECT_READ__dma2__BITNR 18 -#define R_VECT_READ__dma2__WIDTH 1 -#define R_VECT_READ__dma2__active 1 -#define R_VECT_READ__dma2__inactive 0 -#define R_VECT_READ__dma1__BITNR 17 -#define R_VECT_READ__dma1__WIDTH 1 -#define R_VECT_READ__dma1__active 1 -#define R_VECT_READ__dma1__inactive 0 -#define R_VECT_READ__dma0__BITNR 16 -#define R_VECT_READ__dma0__WIDTH 1 -#define R_VECT_READ__dma0__active 1 -#define R_VECT_READ__dma0__inactive 0 -#define R_VECT_READ__ext_dma1__BITNR 13 -#define R_VECT_READ__ext_dma1__WIDTH 1 -#define R_VECT_READ__ext_dma1__active 1 -#define R_VECT_READ__ext_dma1__inactive 0 -#define R_VECT_READ__ext_dma0__BITNR 12 -#define R_VECT_READ__ext_dma0__WIDTH 1 -#define R_VECT_READ__ext_dma0__active 1 -#define R_VECT_READ__ext_dma0__inactive 0 -#define R_VECT_READ__pa__BITNR 11 -#define R_VECT_READ__pa__WIDTH 1 -#define R_VECT_READ__pa__active 1 -#define R_VECT_READ__pa__inactive 0 -#define R_VECT_READ__irq_intnr__BITNR 10 -#define R_VECT_READ__irq_intnr__WIDTH 1 -#define R_VECT_READ__irq_intnr__active 1 -#define R_VECT_READ__irq_intnr__inactive 0 -#define R_VECT_READ__sw__BITNR 9 -#define R_VECT_READ__sw__WIDTH 1 -#define R_VECT_READ__sw__active 1 -#define R_VECT_READ__sw__inactive 0 -#define R_VECT_READ__serial__BITNR 8 -#define R_VECT_READ__serial__WIDTH 1 -#define R_VECT_READ__serial__active 1 -#define R_VECT_READ__serial__inactive 0 -#define R_VECT_READ__snmp__BITNR 7 -#define R_VECT_READ__snmp__WIDTH 1 -#define R_VECT_READ__snmp__active 1 -#define R_VECT_READ__snmp__inactive 0 -#define R_VECT_READ__network__BITNR 6 -#define R_VECT_READ__network__WIDTH 1 -#define R_VECT_READ__network__active 1 -#define R_VECT_READ__network__inactive 0 -#define R_VECT_READ__scsi1__BITNR 5 -#define R_VECT_READ__scsi1__WIDTH 1 -#define R_VECT_READ__scsi1__active 1 -#define R_VECT_READ__scsi1__inactive 0 -#define R_VECT_READ__par1__BITNR 5 -#define R_VECT_READ__par1__WIDTH 1 -#define R_VECT_READ__par1__active 1 -#define R_VECT_READ__par1__inactive 0 -#define R_VECT_READ__scsi0__BITNR 4 -#define R_VECT_READ__scsi0__WIDTH 1 -#define R_VECT_READ__scsi0__active 1 -#define R_VECT_READ__scsi0__inactive 0 -#define R_VECT_READ__par0__BITNR 4 -#define R_VECT_READ__par0__WIDTH 1 -#define R_VECT_READ__par0__active 1 -#define R_VECT_READ__par0__inactive 0 -#define R_VECT_READ__ata__BITNR 4 -#define R_VECT_READ__ata__WIDTH 1 -#define R_VECT_READ__ata__active 1 -#define R_VECT_READ__ata__inactive 0 -#define R_VECT_READ__mio__BITNR 4 -#define R_VECT_READ__mio__WIDTH 1 -#define R_VECT_READ__mio__active 1 -#define R_VECT_READ__mio__inactive 0 -#define R_VECT_READ__timer1__BITNR 3 -#define R_VECT_READ__timer1__WIDTH 1 -#define R_VECT_READ__timer1__active 1 -#define R_VECT_READ__timer1__inactive 0 -#define R_VECT_READ__timer0__BITNR 2 -#define R_VECT_READ__timer0__WIDTH 1 -#define R_VECT_READ__timer0__active 1 -#define R_VECT_READ__timer0__inactive 0 -#define R_VECT_READ__nmi__BITNR 1 -#define R_VECT_READ__nmi__WIDTH 1 -#define R_VECT_READ__nmi__active 1 -#define R_VECT_READ__nmi__inactive 0 -#define R_VECT_READ__some__BITNR 0 -#define R_VECT_READ__some__WIDTH 1 -#define R_VECT_READ__some__active 1 -#define R_VECT_READ__some__inactive 0 - -#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) -#define R_VECT_MASK_SET__usb__BITNR 31 -#define R_VECT_MASK_SET__usb__WIDTH 1 -#define R_VECT_MASK_SET__usb__set 1 -#define R_VECT_MASK_SET__usb__nop 0 -#define R_VECT_MASK_SET__dma9__BITNR 25 -#define R_VECT_MASK_SET__dma9__WIDTH 1 -#define R_VECT_MASK_SET__dma9__set 1 -#define R_VECT_MASK_SET__dma9__nop 0 -#define R_VECT_MASK_SET__dma8__BITNR 24 -#define R_VECT_MASK_SET__dma8__WIDTH 1 -#define R_VECT_MASK_SET__dma8__set 1 -#define R_VECT_MASK_SET__dma8__nop 0 -#define R_VECT_MASK_SET__dma7__BITNR 23 -#define R_VECT_MASK_SET__dma7__WIDTH 1 -#define R_VECT_MASK_SET__dma7__set 1 -#define R_VECT_MASK_SET__dma7__nop 0 -#define R_VECT_MASK_SET__dma6__BITNR 22 -#define R_VECT_MASK_SET__dma6__WIDTH 1 -#define R_VECT_MASK_SET__dma6__set 1 -#define R_VECT_MASK_SET__dma6__nop 0 -#define R_VECT_MASK_SET__dma5__BITNR 21 -#define R_VECT_MASK_SET__dma5__WIDTH 1 -#define R_VECT_MASK_SET__dma5__set 1 -#define R_VECT_MASK_SET__dma5__nop 0 -#define R_VECT_MASK_SET__dma4__BITNR 20 -#define R_VECT_MASK_SET__dma4__WIDTH 1 -#define R_VECT_MASK_SET__dma4__set 1 -#define R_VECT_MASK_SET__dma4__nop 0 -#define R_VECT_MASK_SET__dma3__BITNR 19 -#define R_VECT_MASK_SET__dma3__WIDTH 1 -#define R_VECT_MASK_SET__dma3__set 1 -#define R_VECT_MASK_SET__dma3__nop 0 -#define R_VECT_MASK_SET__dma2__BITNR 18 -#define R_VECT_MASK_SET__dma2__WIDTH 1 -#define R_VECT_MASK_SET__dma2__set 1 -#define R_VECT_MASK_SET__dma2__nop 0 -#define R_VECT_MASK_SET__dma1__BITNR 17 -#define R_VECT_MASK_SET__dma1__WIDTH 1 -#define R_VECT_MASK_SET__dma1__set 1 -#define R_VECT_MASK_SET__dma1__nop 0 -#define R_VECT_MASK_SET__dma0__BITNR 16 -#define R_VECT_MASK_SET__dma0__WIDTH 1 -#define R_VECT_MASK_SET__dma0__set 1 -#define R_VECT_MASK_SET__dma0__nop 0 -#define R_VECT_MASK_SET__ext_dma1__BITNR 13 -#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma1__set 1 -#define R_VECT_MASK_SET__ext_dma1__nop 0 -#define R_VECT_MASK_SET__ext_dma0__BITNR 12 -#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 -#define R_VECT_MASK_SET__ext_dma0__set 1 -#define R_VECT_MASK_SET__ext_dma0__nop 0 -#define R_VECT_MASK_SET__pa__BITNR 11 -#define R_VECT_MASK_SET__pa__WIDTH 1 -#define R_VECT_MASK_SET__pa__set 1 -#define R_VECT_MASK_SET__pa__nop 0 -#define R_VECT_MASK_SET__irq_intnr__BITNR 10 -#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 -#define R_VECT_MASK_SET__irq_intnr__set 1 -#define R_VECT_MASK_SET__irq_intnr__nop 0 -#define R_VECT_MASK_SET__sw__BITNR 9 -#define R_VECT_MASK_SET__sw__WIDTH 1 -#define R_VECT_MASK_SET__sw__set 1 -#define R_VECT_MASK_SET__sw__nop 0 -#define R_VECT_MASK_SET__serial__BITNR 8 -#define R_VECT_MASK_SET__serial__WIDTH 1 -#define R_VECT_MASK_SET__serial__set 1 -#define R_VECT_MASK_SET__serial__nop 0 -#define R_VECT_MASK_SET__snmp__BITNR 7 -#define R_VECT_MASK_SET__snmp__WIDTH 1 -#define R_VECT_MASK_SET__snmp__set 1 -#define R_VECT_MASK_SET__snmp__nop 0 -#define R_VECT_MASK_SET__network__BITNR 6 -#define R_VECT_MASK_SET__network__WIDTH 1 -#define R_VECT_MASK_SET__network__set 1 -#define R_VECT_MASK_SET__network__nop 0 -#define R_VECT_MASK_SET__scsi1__BITNR 5 -#define R_VECT_MASK_SET__scsi1__WIDTH 1 -#define R_VECT_MASK_SET__scsi1__set 1 -#define R_VECT_MASK_SET__scsi1__nop 0 -#define R_VECT_MASK_SET__par1__BITNR 5 -#define R_VECT_MASK_SET__par1__WIDTH 1 -#define R_VECT_MASK_SET__par1__set 1 -#define R_VECT_MASK_SET__par1__nop 0 -#define R_VECT_MASK_SET__scsi0__BITNR 4 -#define R_VECT_MASK_SET__scsi0__WIDTH 1 -#define R_VECT_MASK_SET__scsi0__set 1 -#define R_VECT_MASK_SET__scsi0__nop 0 -#define R_VECT_MASK_SET__par0__BITNR 4 -#define R_VECT_MASK_SET__par0__WIDTH 1 -#define R_VECT_MASK_SET__par0__set 1 -#define R_VECT_MASK_SET__par0__nop 0 -#define R_VECT_MASK_SET__ata__BITNR 4 -#define R_VECT_MASK_SET__ata__WIDTH 1 -#define R_VECT_MASK_SET__ata__set 1 -#define R_VECT_MASK_SET__ata__nop 0 -#define R_VECT_MASK_SET__mio__BITNR 4 -#define R_VECT_MASK_SET__mio__WIDTH 1 -#define R_VECT_MASK_SET__mio__set 1 -#define R_VECT_MASK_SET__mio__nop 0 -#define R_VECT_MASK_SET__timer1__BITNR 3 -#define R_VECT_MASK_SET__timer1__WIDTH 1 -#define R_VECT_MASK_SET__timer1__set 1 -#define R_VECT_MASK_SET__timer1__nop 0 -#define R_VECT_MASK_SET__timer0__BITNR 2 -#define R_VECT_MASK_SET__timer0__WIDTH 1 -#define R_VECT_MASK_SET__timer0__set 1 -#define R_VECT_MASK_SET__timer0__nop 0 -#define R_VECT_MASK_SET__nmi__BITNR 1 -#define R_VECT_MASK_SET__nmi__WIDTH 1 -#define R_VECT_MASK_SET__nmi__set 1 -#define R_VECT_MASK_SET__nmi__nop 0 -#define R_VECT_MASK_SET__some__BITNR 0 -#define R_VECT_MASK_SET__some__WIDTH 1 -#define R_VECT_MASK_SET__some__set 1 -#define R_VECT_MASK_SET__some__nop 0 - -/* -!* DMA registers -!*/ - -#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) -#define R_SET_EOP__ch9_eop__BITNR 3 -#define R_SET_EOP__ch9_eop__WIDTH 1 -#define R_SET_EOP__ch9_eop__set 1 -#define R_SET_EOP__ch9_eop__nop 0 -#define R_SET_EOP__ch7_eop__BITNR 2 -#define R_SET_EOP__ch7_eop__WIDTH 1 -#define R_SET_EOP__ch7_eop__set 1 -#define R_SET_EOP__ch7_eop__nop 0 -#define R_SET_EOP__ch5_eop__BITNR 1 -#define R_SET_EOP__ch5_eop__WIDTH 1 -#define R_SET_EOP__ch5_eop__set 1 -#define R_SET_EOP__ch5_eop__nop 0 -#define R_SET_EOP__ch3_eop__BITNR 0 -#define R_SET_EOP__ch3_eop__WIDTH 1 -#define R_SET_EOP__ch3_eop__set 1 -#define R_SET_EOP__ch3_eop__nop 0 - -#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) -#define R_DMA_CH0_HWSW__hw__BITNR 16 -#define R_DMA_CH0_HWSW__hw__WIDTH 16 -#define R_DMA_CH0_HWSW__sw__BITNR 0 -#define R_DMA_CH0_HWSW__sw__WIDTH 16 - -#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) -#define R_DMA_CH0_DESCR__descr__BITNR 0 -#define R_DMA_CH0_DESCR__descr__WIDTH 32 - -#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) -#define R_DMA_CH0_NEXT__next__BITNR 0 -#define R_DMA_CH0_NEXT__next__WIDTH 32 - -#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) -#define R_DMA_CH0_BUF__buf__BITNR 0 -#define R_DMA_CH0_BUF__buf__WIDTH 32 - -#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) -#define R_DMA_CH0_FIRST__first__BITNR 0 -#define R_DMA_CH0_FIRST__first__WIDTH 32 - -#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) -#define R_DMA_CH0_CMD__cmd__BITNR 0 -#define R_DMA_CH0_CMD__cmd__WIDTH 3 -#define R_DMA_CH0_CMD__cmd__hold 0 -#define R_DMA_CH0_CMD__cmd__start 1 -#define R_DMA_CH0_CMD__cmd__restart 3 -#define R_DMA_CH0_CMD__cmd__continue 3 -#define R_DMA_CH0_CMD__cmd__reset 4 - -#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) -#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) -#define R_DMA_CH0_STATUS__avail__BITNR 0 -#define R_DMA_CH0_STATUS__avail__WIDTH 7 - -#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) -#define R_DMA_CH1_HWSW__hw__BITNR 16 -#define R_DMA_CH1_HWSW__hw__WIDTH 16 -#define R_DMA_CH1_HWSW__sw__BITNR 0 -#define R_DMA_CH1_HWSW__sw__WIDTH 16 - -#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) -#define R_DMA_CH1_DESCR__descr__BITNR 0 -#define R_DMA_CH1_DESCR__descr__WIDTH 32 - -#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) -#define R_DMA_CH1_NEXT__next__BITNR 0 -#define R_DMA_CH1_NEXT__next__WIDTH 32 - -#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) -#define R_DMA_CH1_BUF__buf__BITNR 0 -#define R_DMA_CH1_BUF__buf__WIDTH 32 - -#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) -#define R_DMA_CH1_FIRST__first__BITNR 0 -#define R_DMA_CH1_FIRST__first__WIDTH 32 - -#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) -#define R_DMA_CH1_CMD__cmd__BITNR 0 -#define R_DMA_CH1_CMD__cmd__WIDTH 3 -#define R_DMA_CH1_CMD__cmd__hold 0 -#define R_DMA_CH1_CMD__cmd__start 1 -#define R_DMA_CH1_CMD__cmd__restart 3 -#define R_DMA_CH1_CMD__cmd__continue 3 -#define R_DMA_CH1_CMD__cmd__reset 4 - -#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) -#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) -#define R_DMA_CH1_STATUS__avail__BITNR 0 -#define R_DMA_CH1_STATUS__avail__WIDTH 7 - -#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) -#define R_DMA_CH2_HWSW__hw__BITNR 16 -#define R_DMA_CH2_HWSW__hw__WIDTH 16 -#define R_DMA_CH2_HWSW__sw__BITNR 0 -#define R_DMA_CH2_HWSW__sw__WIDTH 16 - -#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) -#define R_DMA_CH2_DESCR__descr__BITNR 0 -#define R_DMA_CH2_DESCR__descr__WIDTH 32 - -#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) -#define R_DMA_CH2_NEXT__next__BITNR 0 -#define R_DMA_CH2_NEXT__next__WIDTH 32 - -#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) -#define R_DMA_CH2_BUF__buf__BITNR 0 -#define R_DMA_CH2_BUF__buf__WIDTH 32 - -#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) -#define R_DMA_CH2_FIRST__first__BITNR 0 -#define R_DMA_CH2_FIRST__first__WIDTH 32 - -#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) -#define R_DMA_CH2_CMD__cmd__BITNR 0 -#define R_DMA_CH2_CMD__cmd__WIDTH 3 -#define R_DMA_CH2_CMD__cmd__hold 0 -#define R_DMA_CH2_CMD__cmd__start 1 -#define R_DMA_CH2_CMD__cmd__restart 3 -#define R_DMA_CH2_CMD__cmd__continue 3 -#define R_DMA_CH2_CMD__cmd__reset 4 - -#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) -#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) -#define R_DMA_CH2_STATUS__avail__BITNR 0 -#define R_DMA_CH2_STATUS__avail__WIDTH 7 - -#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) -#define R_DMA_CH3_HWSW__hw__BITNR 16 -#define R_DMA_CH3_HWSW__hw__WIDTH 16 -#define R_DMA_CH3_HWSW__sw__BITNR 0 -#define R_DMA_CH3_HWSW__sw__WIDTH 16 - -#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) -#define R_DMA_CH3_DESCR__descr__BITNR 0 -#define R_DMA_CH3_DESCR__descr__WIDTH 32 - -#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) -#define R_DMA_CH3_NEXT__next__BITNR 0 -#define R_DMA_CH3_NEXT__next__WIDTH 32 - -#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) -#define R_DMA_CH3_BUF__buf__BITNR 0 -#define R_DMA_CH3_BUF__buf__WIDTH 32 - -#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) -#define R_DMA_CH3_FIRST__first__BITNR 0 -#define R_DMA_CH3_FIRST__first__WIDTH 32 - -#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) -#define R_DMA_CH3_CMD__cmd__BITNR 0 -#define R_DMA_CH3_CMD__cmd__WIDTH 3 -#define R_DMA_CH3_CMD__cmd__hold 0 -#define R_DMA_CH3_CMD__cmd__start 1 -#define R_DMA_CH3_CMD__cmd__restart 3 -#define R_DMA_CH3_CMD__cmd__continue 3 -#define R_DMA_CH3_CMD__cmd__reset 4 - -#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) -#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) -#define R_DMA_CH3_STATUS__avail__BITNR 0 -#define R_DMA_CH3_STATUS__avail__WIDTH 7 - -#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) -#define R_DMA_CH4_HWSW__hw__BITNR 16 -#define R_DMA_CH4_HWSW__hw__WIDTH 16 -#define R_DMA_CH4_HWSW__sw__BITNR 0 -#define R_DMA_CH4_HWSW__sw__WIDTH 16 - -#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) -#define R_DMA_CH4_DESCR__descr__BITNR 0 -#define R_DMA_CH4_DESCR__descr__WIDTH 32 - -#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) -#define R_DMA_CH4_NEXT__next__BITNR 0 -#define R_DMA_CH4_NEXT__next__WIDTH 32 - -#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) -#define R_DMA_CH4_BUF__buf__BITNR 0 -#define R_DMA_CH4_BUF__buf__WIDTH 32 - -#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) -#define R_DMA_CH4_FIRST__first__BITNR 0 -#define R_DMA_CH4_FIRST__first__WIDTH 32 - -#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) -#define R_DMA_CH4_CMD__cmd__BITNR 0 -#define R_DMA_CH4_CMD__cmd__WIDTH 3 -#define R_DMA_CH4_CMD__cmd__hold 0 -#define R_DMA_CH4_CMD__cmd__start 1 -#define R_DMA_CH4_CMD__cmd__restart 3 -#define R_DMA_CH4_CMD__cmd__continue 3 -#define R_DMA_CH4_CMD__cmd__reset 4 - -#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) -#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) -#define R_DMA_CH4_STATUS__avail__BITNR 0 -#define R_DMA_CH4_STATUS__avail__WIDTH 7 - -#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) -#define R_DMA_CH5_HWSW__hw__BITNR 16 -#define R_DMA_CH5_HWSW__hw__WIDTH 16 -#define R_DMA_CH5_HWSW__sw__BITNR 0 -#define R_DMA_CH5_HWSW__sw__WIDTH 16 - -#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) -#define R_DMA_CH5_DESCR__descr__BITNR 0 -#define R_DMA_CH5_DESCR__descr__WIDTH 32 - -#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) -#define R_DMA_CH5_NEXT__next__BITNR 0 -#define R_DMA_CH5_NEXT__next__WIDTH 32 - -#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) -#define R_DMA_CH5_BUF__buf__BITNR 0 -#define R_DMA_CH5_BUF__buf__WIDTH 32 - -#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) -#define R_DMA_CH5_FIRST__first__BITNR 0 -#define R_DMA_CH5_FIRST__first__WIDTH 32 - -#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) -#define R_DMA_CH5_CMD__cmd__BITNR 0 -#define R_DMA_CH5_CMD__cmd__WIDTH 3 -#define R_DMA_CH5_CMD__cmd__hold 0 -#define R_DMA_CH5_CMD__cmd__start 1 -#define R_DMA_CH5_CMD__cmd__restart 3 -#define R_DMA_CH5_CMD__cmd__continue 3 -#define R_DMA_CH5_CMD__cmd__reset 4 - -#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) -#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) -#define R_DMA_CH5_STATUS__avail__BITNR 0 -#define R_DMA_CH5_STATUS__avail__WIDTH 7 - -#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) -#define R_DMA_CH6_HWSW__hw__BITNR 16 -#define R_DMA_CH6_HWSW__hw__WIDTH 16 -#define R_DMA_CH6_HWSW__sw__BITNR 0 -#define R_DMA_CH6_HWSW__sw__WIDTH 16 - -#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) -#define R_DMA_CH6_DESCR__descr__BITNR 0 -#define R_DMA_CH6_DESCR__descr__WIDTH 32 - -#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) -#define R_DMA_CH6_NEXT__next__BITNR 0 -#define R_DMA_CH6_NEXT__next__WIDTH 32 - -#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) -#define R_DMA_CH6_BUF__buf__BITNR 0 -#define R_DMA_CH6_BUF__buf__WIDTH 32 - -#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) -#define R_DMA_CH6_FIRST__first__BITNR 0 -#define R_DMA_CH6_FIRST__first__WIDTH 32 - -#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) -#define R_DMA_CH6_CMD__cmd__BITNR 0 -#define R_DMA_CH6_CMD__cmd__WIDTH 3 -#define R_DMA_CH6_CMD__cmd__hold 0 -#define R_DMA_CH6_CMD__cmd__start 1 -#define R_DMA_CH6_CMD__cmd__restart 3 -#define R_DMA_CH6_CMD__cmd__continue 3 -#define R_DMA_CH6_CMD__cmd__reset 4 - -#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) -#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) -#define R_DMA_CH6_STATUS__avail__BITNR 0 -#define R_DMA_CH6_STATUS__avail__WIDTH 7 - -#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) -#define R_DMA_CH7_HWSW__hw__BITNR 16 -#define R_DMA_CH7_HWSW__hw__WIDTH 16 -#define R_DMA_CH7_HWSW__sw__BITNR 0 -#define R_DMA_CH7_HWSW__sw__WIDTH 16 - -#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) -#define R_DMA_CH7_DESCR__descr__BITNR 0 -#define R_DMA_CH7_DESCR__descr__WIDTH 32 - -#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) -#define R_DMA_CH7_NEXT__next__BITNR 0 -#define R_DMA_CH7_NEXT__next__WIDTH 32 - -#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) -#define R_DMA_CH7_BUF__buf__BITNR 0 -#define R_DMA_CH7_BUF__buf__WIDTH 32 - -#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) -#define R_DMA_CH7_FIRST__first__BITNR 0 -#define R_DMA_CH7_FIRST__first__WIDTH 32 - -#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) -#define R_DMA_CH7_CMD__cmd__BITNR 0 -#define R_DMA_CH7_CMD__cmd__WIDTH 3 -#define R_DMA_CH7_CMD__cmd__hold 0 -#define R_DMA_CH7_CMD__cmd__start 1 -#define R_DMA_CH7_CMD__cmd__restart 3 -#define R_DMA_CH7_CMD__cmd__continue 3 -#define R_DMA_CH7_CMD__cmd__reset 4 - -#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) -#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) -#define R_DMA_CH7_STATUS__avail__BITNR 0 -#define R_DMA_CH7_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) -#define R_DMA_CH8_HWSW__hw__BITNR 16 -#define R_DMA_CH8_HWSW__hw__WIDTH 16 -#define R_DMA_CH8_HWSW__sw__BITNR 0 -#define R_DMA_CH8_HWSW__sw__WIDTH 16 - -#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_DESCR__descr__BITNR 0 -#define R_DMA_CH8_DESCR__descr__WIDTH 32 - -#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) -#define R_DMA_CH8_NEXT__next__BITNR 0 -#define R_DMA_CH8_NEXT__next__WIDTH 32 - -#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) -#define R_DMA_CH8_BUF__buf__BITNR 0 -#define R_DMA_CH8_BUF__buf__WIDTH 32 - -#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_FIRST__first__BITNR 0 -#define R_DMA_CH8_FIRST__first__WIDTH 32 - -#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) -#define R_DMA_CH8_CMD__cmd__BITNR 0 -#define R_DMA_CH8_CMD__cmd__WIDTH 3 -#define R_DMA_CH8_CMD__cmd__hold 0 -#define R_DMA_CH8_CMD__cmd__start 1 -#define R_DMA_CH8_CMD__cmd__restart 3 -#define R_DMA_CH8_CMD__cmd__continue 3 -#define R_DMA_CH8_CMD__cmd__reset 4 - -#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) -#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) -#define R_DMA_CH8_STATUS__avail__BITNR 0 -#define R_DMA_CH8_STATUS__avail__WIDTH 7 - -#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) -#define R_DMA_CH8_SUB__sub__BITNR 0 -#define R_DMA_CH8_SUB__sub__WIDTH 32 - -#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) -#define R_DMA_CH8_NEP__nep__BITNR 0 -#define R_DMA_CH8_NEP__nep__WIDTH 32 - -#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) -#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) -#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB0_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) -#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) -#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB1_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) -#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) -#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB2_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) -#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 -#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 - -#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) -#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 -#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 -#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 -#define R_DMA_CH8_SUB3_CMD__cmd__start 1 - -#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 -#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 - -#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) -#define R_DMA_CH9_HWSW__hw__BITNR 16 -#define R_DMA_CH9_HWSW__hw__WIDTH 16 -#define R_DMA_CH9_HWSW__sw__BITNR 0 -#define R_DMA_CH9_HWSW__sw__WIDTH 16 - -#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) -#define R_DMA_CH9_DESCR__descr__BITNR 0 -#define R_DMA_CH9_DESCR__descr__WIDTH 32 - -#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) -#define R_DMA_CH9_NEXT__next__BITNR 0 -#define R_DMA_CH9_NEXT__next__WIDTH 32 - -#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) -#define R_DMA_CH9_BUF__buf__BITNR 0 -#define R_DMA_CH9_BUF__buf__WIDTH 32 - -#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) -#define R_DMA_CH9_FIRST__first__BITNR 0 -#define R_DMA_CH9_FIRST__first__WIDTH 32 - -#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) -#define R_DMA_CH9_CMD__cmd__BITNR 0 -#define R_DMA_CH9_CMD__cmd__WIDTH 3 -#define R_DMA_CH9_CMD__cmd__hold 0 -#define R_DMA_CH9_CMD__cmd__start 1 -#define R_DMA_CH9_CMD__cmd__restart 3 -#define R_DMA_CH9_CMD__cmd__continue 3 -#define R_DMA_CH9_CMD__cmd__reset 4 - -#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) -#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 -#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 -#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 -#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 - -#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) -#define R_DMA_CH9_STATUS__avail__BITNR 0 -#define R_DMA_CH9_STATUS__avail__WIDTH 7 - -/* -!* Test mode registers -!*/ - -#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) -#define R_TEST_MODE__single_step__BITNR 19 -#define R_TEST_MODE__single_step__WIDTH 1 -#define R_TEST_MODE__single_step__on 1 -#define R_TEST_MODE__single_step__off 0 -#define R_TEST_MODE__step_wr__BITNR 18 -#define R_TEST_MODE__step_wr__WIDTH 1 -#define R_TEST_MODE__step_wr__on 1 -#define R_TEST_MODE__step_wr__off 0 -#define R_TEST_MODE__step_rd__BITNR 17 -#define R_TEST_MODE__step_rd__WIDTH 1 -#define R_TEST_MODE__step_rd__on 1 -#define R_TEST_MODE__step_rd__off 0 -#define R_TEST_MODE__step_fetch__BITNR 16 -#define R_TEST_MODE__step_fetch__WIDTH 1 -#define R_TEST_MODE__step_fetch__on 1 -#define R_TEST_MODE__step_fetch__off 0 -#define R_TEST_MODE__mmu_test__BITNR 12 -#define R_TEST_MODE__mmu_test__WIDTH 1 -#define R_TEST_MODE__mmu_test__on 1 -#define R_TEST_MODE__mmu_test__off 0 -#define R_TEST_MODE__usb_test__BITNR 11 -#define R_TEST_MODE__usb_test__WIDTH 1 -#define R_TEST_MODE__usb_test__on 1 -#define R_TEST_MODE__usb_test__off 0 -#define R_TEST_MODE__scsi_timer_test__BITNR 10 -#define R_TEST_MODE__scsi_timer_test__WIDTH 1 -#define R_TEST_MODE__scsi_timer_test__on 1 -#define R_TEST_MODE__scsi_timer_test__off 0 -#define R_TEST_MODE__backoff__BITNR 9 -#define R_TEST_MODE__backoff__WIDTH 1 -#define R_TEST_MODE__backoff__on 1 -#define R_TEST_MODE__backoff__off 0 -#define R_TEST_MODE__snmp_test__BITNR 8 -#define R_TEST_MODE__snmp_test__WIDTH 1 -#define R_TEST_MODE__snmp_test__on 1 -#define R_TEST_MODE__snmp_test__off 0 -#define R_TEST_MODE__snmp_inc__BITNR 7 -#define R_TEST_MODE__snmp_inc__WIDTH 1 -#define R_TEST_MODE__snmp_inc__do 1 -#define R_TEST_MODE__snmp_inc__dont 0 -#define R_TEST_MODE__ser_loop__BITNR 6 -#define R_TEST_MODE__ser_loop__WIDTH 1 -#define R_TEST_MODE__ser_loop__on 1 -#define R_TEST_MODE__ser_loop__off 0 -#define R_TEST_MODE__baudrate__BITNR 5 -#define R_TEST_MODE__baudrate__WIDTH 1 -#define R_TEST_MODE__baudrate__on 1 -#define R_TEST_MODE__baudrate__off 0 -#define R_TEST_MODE__timer__BITNR 3 -#define R_TEST_MODE__timer__WIDTH 2 -#define R_TEST_MODE__timer__off 0 -#define R_TEST_MODE__timer__even 1 -#define R_TEST_MODE__timer__odd 2 -#define R_TEST_MODE__timer__all 3 -#define R_TEST_MODE__cache_test__BITNR 2 -#define R_TEST_MODE__cache_test__WIDTH 1 -#define R_TEST_MODE__cache_test__normal 0 -#define R_TEST_MODE__cache_test__test 1 -#define R_TEST_MODE__tag_test__BITNR 1 -#define R_TEST_MODE__tag_test__WIDTH 1 -#define R_TEST_MODE__tag_test__normal 0 -#define R_TEST_MODE__tag_test__test 1 -#define R_TEST_MODE__cache_enable__BITNR 0 -#define R_TEST_MODE__cache_enable__WIDTH 1 -#define R_TEST_MODE__cache_enable__enable 1 -#define R_TEST_MODE__cache_enable__disable 0 - -#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) -#define R_SINGLE_STEP__single_step__BITNR 3 -#define R_SINGLE_STEP__single_step__WIDTH 1 -#define R_SINGLE_STEP__single_step__on 1 -#define R_SINGLE_STEP__single_step__off 0 -#define R_SINGLE_STEP__step_wr__BITNR 2 -#define R_SINGLE_STEP__step_wr__WIDTH 1 -#define R_SINGLE_STEP__step_wr__on 1 -#define R_SINGLE_STEP__step_wr__off 0 -#define R_SINGLE_STEP__step_rd__BITNR 1 -#define R_SINGLE_STEP__step_rd__WIDTH 1 -#define R_SINGLE_STEP__step_rd__on 1 -#define R_SINGLE_STEP__step_rd__off 0 -#define R_SINGLE_STEP__step_fetch__BITNR 0 -#define R_SINGLE_STEP__step_fetch__WIDTH 1 -#define R_SINGLE_STEP__step_fetch__on 1 -#define R_SINGLE_STEP__step_fetch__off 0 - -/* -!* USB interface control registers -!*/ - -#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) -#define R_USB_REVISION__major__BITNR 4 -#define R_USB_REVISION__major__WIDTH 4 -#define R_USB_REVISION__minor__BITNR 0 -#define R_USB_REVISION__minor__WIDTH 4 - -#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND__port_sel__BITNR 6 -#define R_USB_COMMAND__port_sel__WIDTH 2 -#define R_USB_COMMAND__port_sel__nop 0 -#define R_USB_COMMAND__port_sel__port1 1 -#define R_USB_COMMAND__port_sel__port2 2 -#define R_USB_COMMAND__port_sel__both 3 -#define R_USB_COMMAND__port_cmd__BITNR 4 -#define R_USB_COMMAND__port_cmd__WIDTH 2 -#define R_USB_COMMAND__port_cmd__reset 0 -#define R_USB_COMMAND__port_cmd__disable 1 -#define R_USB_COMMAND__port_cmd__suspend 2 -#define R_USB_COMMAND__port_cmd__resume 3 -#define R_USB_COMMAND__busy__BITNR 3 -#define R_USB_COMMAND__busy__WIDTH 1 -#define R_USB_COMMAND__busy__no 0 -#define R_USB_COMMAND__busy__yes 1 -#define R_USB_COMMAND__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND__ctrl_cmd__nop 0 -#define R_USB_COMMAND__ctrl_cmd__reset 1 -#define R_USB_COMMAND__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND__ctrl_cmd__host_config 3 -#define R_USB_COMMAND__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND__ctrl_cmd__host_nop 5 -#define R_USB_COMMAND__ctrl_cmd__host_run 6 -#define R_USB_COMMAND__ctrl_cmd__host_stop 7 - -#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) -#define R_USB_COMMAND_DEV__port_sel__BITNR 6 -#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 -#define R_USB_COMMAND_DEV__port_sel__nop 0 -#define R_USB_COMMAND_DEV__port_sel__dummy1 1 -#define R_USB_COMMAND_DEV__port_sel__dummy2 2 -#define R_USB_COMMAND_DEV__port_sel__any 3 -#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 -#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 -#define R_USB_COMMAND_DEV__port_cmd__active 0 -#define R_USB_COMMAND_DEV__port_cmd__passive 1 -#define R_USB_COMMAND_DEV__port_cmd__nop 2 -#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 -#define R_USB_COMMAND_DEV__busy__BITNR 3 -#define R_USB_COMMAND_DEV__busy__WIDTH 1 -#define R_USB_COMMAND_DEV__busy__no 0 -#define R_USB_COMMAND_DEV__busy__yes 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 -#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 -#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 -#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 -#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 - -#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) -#define R_USB_STATUS__ourun__BITNR 5 -#define R_USB_STATUS__ourun__WIDTH 1 -#define R_USB_STATUS__ourun__no 0 -#define R_USB_STATUS__ourun__yes 1 -#define R_USB_STATUS__perror__BITNR 4 -#define R_USB_STATUS__perror__WIDTH 1 -#define R_USB_STATUS__perror__no 0 -#define R_USB_STATUS__perror__yes 1 -#define R_USB_STATUS__device_mode__BITNR 3 -#define R_USB_STATUS__device_mode__WIDTH 1 -#define R_USB_STATUS__device_mode__no 0 -#define R_USB_STATUS__device_mode__yes 1 -#define R_USB_STATUS__host_mode__BITNR 2 -#define R_USB_STATUS__host_mode__WIDTH 1 -#define R_USB_STATUS__host_mode__no 0 -#define R_USB_STATUS__host_mode__yes 1 -#define R_USB_STATUS__started__BITNR 1 -#define R_USB_STATUS__started__WIDTH 1 -#define R_USB_STATUS__started__no 0 -#define R_USB_STATUS__started__yes 1 -#define R_USB_STATUS__running__BITNR 0 -#define R_USB_STATUS__running__WIDTH 1 -#define R_USB_STATUS__running__no 0 -#define R_USB_STATUS__running__yes 1 - -#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eof__set 1 -#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eof__set 1 -#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 -#define R_USB_IRQ_MASK_SET__iso_eot__set 1 -#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 -#define R_USB_IRQ_MASK_SET__intr_eot__set 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 -#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET__sof__nop 0 -#define R_USB_IRQ_MASK_SET__sof__set 1 -#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__port_status__nop 0 -#define R_USB_IRQ_MASK_SET__port_status__set 1 -#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 -#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 -#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 -#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ__sof__pend 1 -#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__port_status__pend 1 -#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 -#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 -#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 -#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__sof__nop 0 -#define R_USB_IRQ_MASK_CLR__sof__clr 1 -#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 - -#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ__iso_eof__BITNR 13 -#define R_USB_IRQ_READ__iso_eof__WIDTH 1 -#define R_USB_IRQ_READ__iso_eof__no_pend 0 -#define R_USB_IRQ_READ__iso_eof__pend 1 -#define R_USB_IRQ_READ__intr_eof__BITNR 12 -#define R_USB_IRQ_READ__intr_eof__WIDTH 1 -#define R_USB_IRQ_READ__intr_eof__no_pend 0 -#define R_USB_IRQ_READ__intr_eof__pend 1 -#define R_USB_IRQ_READ__iso_eot__BITNR 11 -#define R_USB_IRQ_READ__iso_eot__WIDTH 1 -#define R_USB_IRQ_READ__iso_eot__no_pend 0 -#define R_USB_IRQ_READ__iso_eot__pend 1 -#define R_USB_IRQ_READ__intr_eot__BITNR 10 -#define R_USB_IRQ_READ__intr_eot__WIDTH 1 -#define R_USB_IRQ_READ__intr_eot__no_pend 0 -#define R_USB_IRQ_READ__intr_eot__pend 1 -#define R_USB_IRQ_READ__ctl_eot__BITNR 9 -#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 -#define R_USB_IRQ_READ__ctl_eot__no_pend 0 -#define R_USB_IRQ_READ__ctl_eot__pend 1 -#define R_USB_IRQ_READ__bulk_eot__BITNR 8 -#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 -#define R_USB_IRQ_READ__bulk_eot__no_pend 0 -#define R_USB_IRQ_READ__bulk_eot__pend 1 -#define R_USB_IRQ_READ__epid_attn__BITNR 3 -#define R_USB_IRQ_READ__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ__epid_attn__no_pend 0 -#define R_USB_IRQ_READ__epid_attn__pend 1 -#define R_USB_IRQ_READ__sof__BITNR 2 -#define R_USB_IRQ_READ__sof__WIDTH 1 -#define R_USB_IRQ_READ__sof__no_pend 0 -#define R_USB_IRQ_READ__sof__pend 1 -#define R_USB_IRQ_READ__port_status__BITNR 1 -#define R_USB_IRQ_READ__port_status__WIDTH 1 -#define R_USB_IRQ_READ__port_status__no_pend 0 -#define R_USB_IRQ_READ__port_status__pend 1 -#define R_USB_IRQ_READ__ctl_status__BITNR 0 -#define R_USB_IRQ_READ__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ__ctl_status__no_pend 0 -#define R_USB_IRQ_READ__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 - -#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) -#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 - -#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 -#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 -#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 - -#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) -#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 -#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__out_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 -#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 -#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 -#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 -#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 -#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 -#define R_USB_IRQ_READ_DEV__sof__BITNR 2 -#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 -#define R_USB_IRQ_READ_DEV__sof__no_pend 0 -#define R_USB_IRQ_READ_DEV__sof__pend 1 -#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 -#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__port_status__pend 1 -#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 -#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 -#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 -#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 - -#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) -#define R_USB_FM_NUMBER__value__BITNR 0 -#define R_USB_FM_NUMBER__value__WIDTH 32 - -#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) -#define R_USB_FM_INTERVAL__fixed__BITNR 6 -#define R_USB_FM_INTERVAL__fixed__WIDTH 8 -#define R_USB_FM_INTERVAL__adj__BITNR 0 -#define R_USB_FM_INTERVAL__adj__WIDTH 6 - -#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) -#define R_USB_FM_REMAINING__value__BITNR 0 -#define R_USB_FM_REMAINING__value__WIDTH 14 - -#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) -#define R_USB_FM_PSTART__value__BITNR 0 -#define R_USB_FM_PSTART__value__WIDTH 14 - -#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) -#define R_USB_RH_STATUS__babble2__BITNR 7 -#define R_USB_RH_STATUS__babble2__WIDTH 1 -#define R_USB_RH_STATUS__babble2__no 0 -#define R_USB_RH_STATUS__babble2__yes 1 -#define R_USB_RH_STATUS__babble1__BITNR 6 -#define R_USB_RH_STATUS__babble1__WIDTH 1 -#define R_USB_RH_STATUS__babble1__no 0 -#define R_USB_RH_STATUS__babble1__yes 1 -#define R_USB_RH_STATUS__bus1__BITNR 4 -#define R_USB_RH_STATUS__bus1__WIDTH 2 -#define R_USB_RH_STATUS__bus1__SE0 0 -#define R_USB_RH_STATUS__bus1__Diff0 1 -#define R_USB_RH_STATUS__bus1__Diff1 2 -#define R_USB_RH_STATUS__bus1__SE1 3 -#define R_USB_RH_STATUS__bus2__BITNR 2 -#define R_USB_RH_STATUS__bus2__WIDTH 2 -#define R_USB_RH_STATUS__bus2__SE0 0 -#define R_USB_RH_STATUS__bus2__Diff0 1 -#define R_USB_RH_STATUS__bus2__Diff1 2 -#define R_USB_RH_STATUS__bus2__SE1 3 -#define R_USB_RH_STATUS__nports__BITNR 0 -#define R_USB_RH_STATUS__nports__WIDTH 2 - -#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) -#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__speed__full 0 -#define R_USB_RH_PORT_STATUS_1__speed__low 1 -#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__reset__no 0 -#define R_USB_RH_PORT_STATUS_1__reset__yes 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__suspended__no 0 -#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__enabled__no 0 -#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_1__connected__no 0 -#define R_USB_RH_PORT_STATUS_1__connected__yes 1 - -#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) -#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 -#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__speed__full 0 -#define R_USB_RH_PORT_STATUS_2__speed__low 1 -#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 -#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 -#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__reset__no 0 -#define R_USB_RH_PORT_STATUS_2__reset__yes 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 -#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 -#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 -#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 -#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__suspended__no 0 -#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 -#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 -#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__enabled__no 0 -#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 -#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 -#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 -#define R_USB_RH_PORT_STATUS_2__connected__no 0 -#define R_USB_RH_PORT_STATUS_2__connected__yes 1 - -#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) -#define R_USB_EPT_INDEX__value__BITNR 0 -#define R_USB_EPT_INDEX__value__WIDTH 5 - -#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA__valid__BITNR 31 -#define R_USB_EPT_DATA__valid__WIDTH 1 -#define R_USB_EPT_DATA__valid__no 0 -#define R_USB_EPT_DATA__valid__yes 1 -#define R_USB_EPT_DATA__hold__BITNR 30 -#define R_USB_EPT_DATA__hold__WIDTH 1 -#define R_USB_EPT_DATA__hold__no 0 -#define R_USB_EPT_DATA__hold__yes 1 -#define R_USB_EPT_DATA__error_count_in__BITNR 28 -#define R_USB_EPT_DATA__error_count_in__WIDTH 2 -#define R_USB_EPT_DATA__t_in__BITNR 27 -#define R_USB_EPT_DATA__t_in__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__BITNR 26 -#define R_USB_EPT_DATA__low_speed__WIDTH 1 -#define R_USB_EPT_DATA__low_speed__no 0 -#define R_USB_EPT_DATA__low_speed__yes 1 -#define R_USB_EPT_DATA__port__BITNR 24 -#define R_USB_EPT_DATA__port__WIDTH 2 -#define R_USB_EPT_DATA__port__any 0 -#define R_USB_EPT_DATA__port__p1 1 -#define R_USB_EPT_DATA__port__p2 2 -#define R_USB_EPT_DATA__port__undef 3 -#define R_USB_EPT_DATA__error_code__BITNR 22 -#define R_USB_EPT_DATA__error_code__WIDTH 2 -#define R_USB_EPT_DATA__error_code__no_error 0 -#define R_USB_EPT_DATA__error_code__stall 1 -#define R_USB_EPT_DATA__error_code__bus_error 2 -#define R_USB_EPT_DATA__error_code__buffer_error 3 -#define R_USB_EPT_DATA__t_out__BITNR 21 -#define R_USB_EPT_DATA__t_out__WIDTH 1 -#define R_USB_EPT_DATA__error_count_out__BITNR 19 -#define R_USB_EPT_DATA__error_count_out__WIDTH 2 -#define R_USB_EPT_DATA__max_len__BITNR 11 -#define R_USB_EPT_DATA__max_len__WIDTH 7 -#define R_USB_EPT_DATA__ep__BITNR 7 -#define R_USB_EPT_DATA__ep__WIDTH 4 -#define R_USB_EPT_DATA__dev__BITNR 0 -#define R_USB_EPT_DATA__dev__WIDTH 7 - -#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_ISO__valid__BITNR 31 -#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 -#define R_USB_EPT_DATA_ISO__valid__no 0 -#define R_USB_EPT_DATA_ISO__valid__yes 1 -#define R_USB_EPT_DATA_ISO__port__BITNR 24 -#define R_USB_EPT_DATA_ISO__port__WIDTH 2 -#define R_USB_EPT_DATA_ISO__port__any 0 -#define R_USB_EPT_DATA_ISO__port__p1 1 -#define R_USB_EPT_DATA_ISO__port__p2 2 -#define R_USB_EPT_DATA_ISO__port__undef 3 -#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 -#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 -#define R_USB_EPT_DATA_ISO__error_code__no_error 0 -#define R_USB_EPT_DATA_ISO__error_code__stall 1 -#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 -#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 -#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 -#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 -#define R_USB_EPT_DATA_ISO__ep__BITNR 7 -#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 -#define R_USB_EPT_DATA_ISO__dev__BITNR 0 -#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 - -#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) -#define R_USB_EPT_DATA_DEV__valid__BITNR 31 -#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 -#define R_USB_EPT_DATA_DEV__valid__no 0 -#define R_USB_EPT_DATA_DEV__valid__yes 1 -#define R_USB_EPT_DATA_DEV__hold__BITNR 30 -#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 -#define R_USB_EPT_DATA_DEV__hold__no 0 -#define R_USB_EPT_DATA_DEV__hold__yes 1 -#define R_USB_EPT_DATA_DEV__stall__BITNR 29 -#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 -#define R_USB_EPT_DATA_DEV__stall__no 0 -#define R_USB_EPT_DATA_DEV__stall__yes 1 -#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 -#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 -#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 -#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 -#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 -#define R_USB_EPT_DATA_DEV__ctrl__no 0 -#define R_USB_EPT_DATA_DEV__ctrl__yes 1 -#define R_USB_EPT_DATA_DEV__iso__BITNR 26 -#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 -#define R_USB_EPT_DATA_DEV__iso__no 0 -#define R_USB_EPT_DATA_DEV__iso__yes 1 -#define R_USB_EPT_DATA_DEV__port__BITNR 24 -#define R_USB_EPT_DATA_DEV__port__WIDTH 2 -#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 -#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 -#define R_USB_EPT_DATA_DEV__t__BITNR 21 -#define R_USB_EPT_DATA_DEV__t__WIDTH 1 -#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 -#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 -#define R_USB_EPT_DATA_DEV__ep__BITNR 7 -#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 -#define R_USB_EPT_DATA_DEV__dev__BITNR 0 -#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 - -#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) -#define R_USB_SNMP_TERROR__value__BITNR 0 -#define R_USB_SNMP_TERROR__value__WIDTH 32 - -#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) -#define R_USB_EPID_ATTN__value__BITNR 0 -#define R_USB_EPID_ATTN__value__WIDTH 32 - -#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) -#define R_USB_PORT1_DISABLE__disable__BITNR 0 -#define R_USB_PORT1_DISABLE__disable__WIDTH 1 -#define R_USB_PORT1_DISABLE__disable__yes 0 -#define R_USB_PORT1_DISABLE__disable__no 1 - -#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) -#define R_USB_PORT2_DISABLE__disable__BITNR 0 -#define R_USB_PORT2_DISABLE__disable__WIDTH 1 -#define R_USB_PORT2_DISABLE__disable__yes 0 -#define R_USB_PORT2_DISABLE__disable__no 1 - -/* -!* MMU registers -!*/ - -#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) -#define R_MMU_CONFIG__mmu_enable__BITNR 31 -#define R_MMU_CONFIG__mmu_enable__WIDTH 1 -#define R_MMU_CONFIG__mmu_enable__enable 1 -#define R_MMU_CONFIG__mmu_enable__disable 0 -#define R_MMU_CONFIG__inv_excp__BITNR 18 -#define R_MMU_CONFIG__inv_excp__WIDTH 1 -#define R_MMU_CONFIG__inv_excp__enable 1 -#define R_MMU_CONFIG__inv_excp__disable 0 -#define R_MMU_CONFIG__acc_excp__BITNR 17 -#define R_MMU_CONFIG__acc_excp__WIDTH 1 -#define R_MMU_CONFIG__acc_excp__enable 1 -#define R_MMU_CONFIG__acc_excp__disable 0 -#define R_MMU_CONFIG__we_excp__BITNR 16 -#define R_MMU_CONFIG__we_excp__WIDTH 1 -#define R_MMU_CONFIG__we_excp__enable 1 -#define R_MMU_CONFIG__we_excp__disable 0 -#define R_MMU_CONFIG__seg_f__BITNR 15 -#define R_MMU_CONFIG__seg_f__WIDTH 1 -#define R_MMU_CONFIG__seg_f__seg 1 -#define R_MMU_CONFIG__seg_f__page 0 -#define R_MMU_CONFIG__seg_e__BITNR 14 -#define R_MMU_CONFIG__seg_e__WIDTH 1 -#define R_MMU_CONFIG__seg_e__seg 1 -#define R_MMU_CONFIG__seg_e__page 0 -#define R_MMU_CONFIG__seg_d__BITNR 13 -#define R_MMU_CONFIG__seg_d__WIDTH 1 -#define R_MMU_CONFIG__seg_d__seg 1 -#define R_MMU_CONFIG__seg_d__page 0 -#define R_MMU_CONFIG__seg_c__BITNR 12 -#define R_MMU_CONFIG__seg_c__WIDTH 1 -#define R_MMU_CONFIG__seg_c__seg 1 -#define R_MMU_CONFIG__seg_c__page 0 -#define R_MMU_CONFIG__seg_b__BITNR 11 -#define R_MMU_CONFIG__seg_b__WIDTH 1 -#define R_MMU_CONFIG__seg_b__seg 1 -#define R_MMU_CONFIG__seg_b__page 0 -#define R_MMU_CONFIG__seg_a__BITNR 10 -#define R_MMU_CONFIG__seg_a__WIDTH 1 -#define R_MMU_CONFIG__seg_a__seg 1 -#define R_MMU_CONFIG__seg_a__page 0 -#define R_MMU_CONFIG__seg_9__BITNR 9 -#define R_MMU_CONFIG__seg_9__WIDTH 1 -#define R_MMU_CONFIG__seg_9__seg 1 -#define R_MMU_CONFIG__seg_9__page 0 -#define R_MMU_CONFIG__seg_8__BITNR 8 -#define R_MMU_CONFIG__seg_8__WIDTH 1 -#define R_MMU_CONFIG__seg_8__seg 1 -#define R_MMU_CONFIG__seg_8__page 0 -#define R_MMU_CONFIG__seg_7__BITNR 7 -#define R_MMU_CONFIG__seg_7__WIDTH 1 -#define R_MMU_CONFIG__seg_7__seg 1 -#define R_MMU_CONFIG__seg_7__page 0 -#define R_MMU_CONFIG__seg_6__BITNR 6 -#define R_MMU_CONFIG__seg_6__WIDTH 1 -#define R_MMU_CONFIG__seg_6__seg 1 -#define R_MMU_CONFIG__seg_6__page 0 -#define R_MMU_CONFIG__seg_5__BITNR 5 -#define R_MMU_CONFIG__seg_5__WIDTH 1 -#define R_MMU_CONFIG__seg_5__seg 1 -#define R_MMU_CONFIG__seg_5__page 0 -#define R_MMU_CONFIG__seg_4__BITNR 4 -#define R_MMU_CONFIG__seg_4__WIDTH 1 -#define R_MMU_CONFIG__seg_4__seg 1 -#define R_MMU_CONFIG__seg_4__page 0 -#define R_MMU_CONFIG__seg_3__BITNR 3 -#define R_MMU_CONFIG__seg_3__WIDTH 1 -#define R_MMU_CONFIG__seg_3__seg 1 -#define R_MMU_CONFIG__seg_3__page 0 -#define R_MMU_CONFIG__seg_2__BITNR 2 -#define R_MMU_CONFIG__seg_2__WIDTH 1 -#define R_MMU_CONFIG__seg_2__seg 1 -#define R_MMU_CONFIG__seg_2__page 0 -#define R_MMU_CONFIG__seg_1__BITNR 1 -#define R_MMU_CONFIG__seg_1__WIDTH 1 -#define R_MMU_CONFIG__seg_1__seg 1 -#define R_MMU_CONFIG__seg_1__page 0 -#define R_MMU_CONFIG__seg_0__BITNR 0 -#define R_MMU_CONFIG__seg_0__WIDTH 1 -#define R_MMU_CONFIG__seg_0__seg 1 -#define R_MMU_CONFIG__seg_0__page 0 - -#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) -#define R_MMU_KSEG__seg_f__BITNR 15 -#define R_MMU_KSEG__seg_f__WIDTH 1 -#define R_MMU_KSEG__seg_f__seg 1 -#define R_MMU_KSEG__seg_f__page 0 -#define R_MMU_KSEG__seg_e__BITNR 14 -#define R_MMU_KSEG__seg_e__WIDTH 1 -#define R_MMU_KSEG__seg_e__seg 1 -#define R_MMU_KSEG__seg_e__page 0 -#define R_MMU_KSEG__seg_d__BITNR 13 -#define R_MMU_KSEG__seg_d__WIDTH 1 -#define R_MMU_KSEG__seg_d__seg 1 -#define R_MMU_KSEG__seg_d__page 0 -#define R_MMU_KSEG__seg_c__BITNR 12 -#define R_MMU_KSEG__seg_c__WIDTH 1 -#define R_MMU_KSEG__seg_c__seg 1 -#define R_MMU_KSEG__seg_c__page 0 -#define R_MMU_KSEG__seg_b__BITNR 11 -#define R_MMU_KSEG__seg_b__WIDTH 1 -#define R_MMU_KSEG__seg_b__seg 1 -#define R_MMU_KSEG__seg_b__page 0 -#define R_MMU_KSEG__seg_a__BITNR 10 -#define R_MMU_KSEG__seg_a__WIDTH 1 -#define R_MMU_KSEG__seg_a__seg 1 -#define R_MMU_KSEG__seg_a__page 0 -#define R_MMU_KSEG__seg_9__BITNR 9 -#define R_MMU_KSEG__seg_9__WIDTH 1 -#define R_MMU_KSEG__seg_9__seg 1 -#define R_MMU_KSEG__seg_9__page 0 -#define R_MMU_KSEG__seg_8__BITNR 8 -#define R_MMU_KSEG__seg_8__WIDTH 1 -#define R_MMU_KSEG__seg_8__seg 1 -#define R_MMU_KSEG__seg_8__page 0 -#define R_MMU_KSEG__seg_7__BITNR 7 -#define R_MMU_KSEG__seg_7__WIDTH 1 -#define R_MMU_KSEG__seg_7__seg 1 -#define R_MMU_KSEG__seg_7__page 0 -#define R_MMU_KSEG__seg_6__BITNR 6 -#define R_MMU_KSEG__seg_6__WIDTH 1 -#define R_MMU_KSEG__seg_6__seg 1 -#define R_MMU_KSEG__seg_6__page 0 -#define R_MMU_KSEG__seg_5__BITNR 5 -#define R_MMU_KSEG__seg_5__WIDTH 1 -#define R_MMU_KSEG__seg_5__seg 1 -#define R_MMU_KSEG__seg_5__page 0 -#define R_MMU_KSEG__seg_4__BITNR 4 -#define R_MMU_KSEG__seg_4__WIDTH 1 -#define R_MMU_KSEG__seg_4__seg 1 -#define R_MMU_KSEG__seg_4__page 0 -#define R_MMU_KSEG__seg_3__BITNR 3 -#define R_MMU_KSEG__seg_3__WIDTH 1 -#define R_MMU_KSEG__seg_3__seg 1 -#define R_MMU_KSEG__seg_3__page 0 -#define R_MMU_KSEG__seg_2__BITNR 2 -#define R_MMU_KSEG__seg_2__WIDTH 1 -#define R_MMU_KSEG__seg_2__seg 1 -#define R_MMU_KSEG__seg_2__page 0 -#define R_MMU_KSEG__seg_1__BITNR 1 -#define R_MMU_KSEG__seg_1__WIDTH 1 -#define R_MMU_KSEG__seg_1__seg 1 -#define R_MMU_KSEG__seg_1__page 0 -#define R_MMU_KSEG__seg_0__BITNR 0 -#define R_MMU_KSEG__seg_0__WIDTH 1 -#define R_MMU_KSEG__seg_0__seg 1 -#define R_MMU_KSEG__seg_0__page 0 - -#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) -#define R_MMU_CTRL__inv_excp__BITNR 2 -#define R_MMU_CTRL__inv_excp__WIDTH 1 -#define R_MMU_CTRL__inv_excp__enable 1 -#define R_MMU_CTRL__inv_excp__disable 0 -#define R_MMU_CTRL__acc_excp__BITNR 1 -#define R_MMU_CTRL__acc_excp__WIDTH 1 -#define R_MMU_CTRL__acc_excp__enable 1 -#define R_MMU_CTRL__acc_excp__disable 0 -#define R_MMU_CTRL__we_excp__BITNR 0 -#define R_MMU_CTRL__we_excp__WIDTH 1 -#define R_MMU_CTRL__we_excp__enable 1 -#define R_MMU_CTRL__we_excp__disable 0 - -#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) -#define R_MMU_ENABLE__mmu_enable__BITNR 7 -#define R_MMU_ENABLE__mmu_enable__WIDTH 1 -#define R_MMU_ENABLE__mmu_enable__enable 1 -#define R_MMU_ENABLE__mmu_enable__disable 0 - -#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) -#define R_MMU_KBASE_LO__base_7__BITNR 28 -#define R_MMU_KBASE_LO__base_7__WIDTH 4 -#define R_MMU_KBASE_LO__base_6__BITNR 24 -#define R_MMU_KBASE_LO__base_6__WIDTH 4 -#define R_MMU_KBASE_LO__base_5__BITNR 20 -#define R_MMU_KBASE_LO__base_5__WIDTH 4 -#define R_MMU_KBASE_LO__base_4__BITNR 16 -#define R_MMU_KBASE_LO__base_4__WIDTH 4 -#define R_MMU_KBASE_LO__base_3__BITNR 12 -#define R_MMU_KBASE_LO__base_3__WIDTH 4 -#define R_MMU_KBASE_LO__base_2__BITNR 8 -#define R_MMU_KBASE_LO__base_2__WIDTH 4 -#define R_MMU_KBASE_LO__base_1__BITNR 4 -#define R_MMU_KBASE_LO__base_1__WIDTH 4 -#define R_MMU_KBASE_LO__base_0__BITNR 0 -#define R_MMU_KBASE_LO__base_0__WIDTH 4 - -#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) -#define R_MMU_KBASE_HI__base_f__BITNR 28 -#define R_MMU_KBASE_HI__base_f__WIDTH 4 -#define R_MMU_KBASE_HI__base_e__BITNR 24 -#define R_MMU_KBASE_HI__base_e__WIDTH 4 -#define R_MMU_KBASE_HI__base_d__BITNR 20 -#define R_MMU_KBASE_HI__base_d__WIDTH 4 -#define R_MMU_KBASE_HI__base_c__BITNR 16 -#define R_MMU_KBASE_HI__base_c__WIDTH 4 -#define R_MMU_KBASE_HI__base_b__BITNR 12 -#define R_MMU_KBASE_HI__base_b__WIDTH 4 -#define R_MMU_KBASE_HI__base_a__BITNR 8 -#define R_MMU_KBASE_HI__base_a__WIDTH 4 -#define R_MMU_KBASE_HI__base_9__BITNR 4 -#define R_MMU_KBASE_HI__base_9__WIDTH 4 -#define R_MMU_KBASE_HI__base_8__BITNR 0 -#define R_MMU_KBASE_HI__base_8__WIDTH 4 - -#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) -#define R_MMU_CONTEXT__page_id__BITNR 0 -#define R_MMU_CONTEXT__page_id__WIDTH 6 - -#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) -#define R_MMU_CAUSE__vpn__BITNR 13 -#define R_MMU_CAUSE__vpn__WIDTH 19 -#define R_MMU_CAUSE__miss_excp__BITNR 12 -#define R_MMU_CAUSE__miss_excp__WIDTH 1 -#define R_MMU_CAUSE__miss_excp__yes 1 -#define R_MMU_CAUSE__miss_excp__no 0 -#define R_MMU_CAUSE__inv_excp__BITNR 11 -#define R_MMU_CAUSE__inv_excp__WIDTH 1 -#define R_MMU_CAUSE__inv_excp__yes 1 -#define R_MMU_CAUSE__inv_excp__no 0 -#define R_MMU_CAUSE__acc_excp__BITNR 10 -#define R_MMU_CAUSE__acc_excp__WIDTH 1 -#define R_MMU_CAUSE__acc_excp__yes 1 -#define R_MMU_CAUSE__acc_excp__no 0 -#define R_MMU_CAUSE__we_excp__BITNR 9 -#define R_MMU_CAUSE__we_excp__WIDTH 1 -#define R_MMU_CAUSE__we_excp__yes 1 -#define R_MMU_CAUSE__we_excp__no 0 -#define R_MMU_CAUSE__wr_rd__BITNR 8 -#define R_MMU_CAUSE__wr_rd__WIDTH 1 -#define R_MMU_CAUSE__wr_rd__write 1 -#define R_MMU_CAUSE__wr_rd__read 0 -#define R_MMU_CAUSE__page_id__BITNR 0 -#define R_MMU_CAUSE__page_id__WIDTH 6 - -#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) -#define R_TLB_SELECT__index__BITNR 0 -#define R_TLB_SELECT__index__WIDTH 6 - -#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) -#define R_TLB_LO__pfn__BITNR 13 -#define R_TLB_LO__pfn__WIDTH 19 -#define R_TLB_LO__global__BITNR 3 -#define R_TLB_LO__global__WIDTH 1 -#define R_TLB_LO__global__yes 1 -#define R_TLB_LO__global__no 0 -#define R_TLB_LO__valid__BITNR 2 -#define R_TLB_LO__valid__WIDTH 1 -#define R_TLB_LO__valid__yes 1 -#define R_TLB_LO__valid__no 0 -#define R_TLB_LO__kernel__BITNR 1 -#define R_TLB_LO__kernel__WIDTH 1 -#define R_TLB_LO__kernel__yes 1 -#define R_TLB_LO__kernel__no 0 -#define R_TLB_LO__we__BITNR 0 -#define R_TLB_LO__we__WIDTH 1 -#define R_TLB_LO__we__yes 1 -#define R_TLB_LO__we__no 0 - -#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) -#define R_TLB_HI__vpn__BITNR 13 -#define R_TLB_HI__vpn__WIDTH 19 -#define R_TLB_HI__page_id__BITNR 0 -#define R_TLB_HI__page_id__WIDTH 6 - -/* -!* Syncrounous serial port registers -!*/ - -#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__underflow__no 0 -#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__overrun__no 0 -#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) -#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) -#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) -#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__error__normal 0 -#define R_SYNC_SERIAL1_CTRL__error__ignore 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 - -#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 - -#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 - -#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 -#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 - -#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 -#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 -#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 -#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 -#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 -#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 -#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 -#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 -#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 -#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 -#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 -#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__underflow__no 0 -#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 -#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 -#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__overrun__no 0 -#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 -#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 -#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 -#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 -#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 -#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 - -#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 - -#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) -#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 - -#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) -#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 -#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 - -#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) -#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 -#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 -#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 -#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 -#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 -#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 -#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 -#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 -#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 -#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 -#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 -#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 -#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 -#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 -#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 -#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__error__normal 0 -#define R_SYNC_SERIAL3_CTRL__error__ignore 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 -#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 -#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 -#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 -#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 -#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 -#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 -#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 -#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 -#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 -#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 -#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 -#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 -#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 -#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 -#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 -#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 -#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 -#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 -#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 -#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 -#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 -#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 -#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 -#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 -#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 -#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 -#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 -#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 -#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 -#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 -#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 -#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 - diff --git a/arch/cris/include/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/arch-v10/arch/sv_addr_ag.h deleted file mode 100644 index 5517f04153a..00000000000 --- a/arch/cris/include/arch-v10/arch/sv_addr_ag.h +++ /dev/null @@ -1,139 +0,0 @@ -/*!************************************************************************** -*! -*! MACROS: -*! IO_MASK(reg,field) -*! IO_STATE(reg,field,state) -*! IO_EXTRACT(reg,field,val) -*! IO_STATE_VALUE(reg,field,state) -*! IO_BITNR(reg,field) -*! IO_WIDTH(reg,field) -*! IO_FIELD(reg,field,val) -*! IO_RD(reg) -*! All moderegister addresses and fields of these. -*! -*!**************************************************************************/ - -#ifndef __sv_addr_ag_h__ -#define __sv_addr_ag_h__ - - -#define __test_sv_addr__ 0 - -/*------------------------------------------------------------ -!* General macros to manipulate moderegisters. -!*-----------------------------------------------------------*/ - -/* IO_MASK returns a mask for a specified bitfield in a register. - Note that this macro doesn't work when field width is 32 bits. */ -#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) -#define IO_MASK_(reg_, field_) \ - ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) - -/* IO_STATE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Shifted to correct position) */ -#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) -#define IO_STATE_(reg_, field_, _state) \ - ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) - -/* IO_EXTRACT returns the masked and shifted value corresponding to the - bitfield can have. */ -#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) -#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ - - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) - -/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic - states that the bitfield can have. (Not shifted) */ -#define IO_STATE_VALUE(reg, field, state) \ - IO_STATE_VALUE_ (reg##_, field##_, _##state) -#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) - -/* IO_FIELD shifts the val parameter to be aligned with the bitfield - specified. */ -#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) -#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) - -/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is - LSB and the returned bitnumber is LSB of the field. */ -#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) -#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) - -/* IO_WIDTH returns the width, in bits, of a bitfield. */ -#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) -#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) - -/*--- Obsolete. Kept for backw compatibility. ---*/ -/* Reads (or writes) a byte/uword/udword from the specified mode - register. */ -#define IO_RD(reg) (*(volatile u32*)(reg)) -#define IO_RD_B(reg) (*(volatile u8*)(reg)) -#define IO_RD_W(reg) (*(volatile u16*)(reg)) -#define IO_RD_D(reg) (*(volatile u32*)(reg)) - -/*------------------------------------------------------------ -!* Start addresses of the different memory areas. -!*-----------------------------------------------------------*/ - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -/*------------------------------------------------------------ -!* Type casts used in mode register macros, making pointer -!* dereferencing possible. Empty in assembler. -!*-----------------------------------------------------------*/ - -#ifndef __ASSEMBLER__ -# define IO_TYPECAST_UDWORD (volatile u32*) -# define IO_TYPECAST_RO_UDWORD (const volatile u32*) -# define IO_TYPECAST_UWORD (volatile u16*) -# define IO_TYPECAST_RO_UWORD (const volatile u16*) -# define IO_TYPECAST_BYTE (volatile u8*) -# define IO_TYPECAST_RO_BYTE (const volatile u8*) -#else -# define IO_TYPECAST_UDWORD -# define IO_TYPECAST_RO_UDWORD -# define IO_TYPECAST_UWORD -# define IO_TYPECAST_RO_UWORD -# define IO_TYPECAST_BYTE -# define IO_TYPECAST_RO_BYTE -#endif - -/*------------------------------------------------------------*/ - -#include - -#if __test_sv_addr__ -/* IO_MASK( R_BUS_CONFIG , CE ) */ -IO_MASK( R_WAITSTATES , SRAM_WS ) -IO_MASK( R_TEST , W32 ) - -IO_STATE( R_BUS_CONFIG, CE, DISABLE ) -IO_STATE( R_BUS_CONFIG, CE, ENABLE ) - -IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) - -IO_MASK( R_DRAM_TIMING, REF ) - -IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) - -IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) - == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) -#endif - - -#endif /* ifndef __sv_addr_ag_h__ */ - diff --git a/arch/cris/include/arch-v10/arch/svinto.h b/arch/cris/include/arch-v10/arch/svinto.h deleted file mode 100644 index da5c1527265..00000000000 --- a/arch/cris/include/arch-v10/arch/svinto.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CRIS_SVINTO_H -#define _ASM_CRIS_SVINTO_H - -#include - -extern unsigned int genconfig_shadow; /* defined and set in head.S */ - -/* dma stuff */ - -enum { /* Available in: */ - d_eol = (1 << 0), /* flags */ - d_eop = (1 << 1), /* flags & status */ - d_wait = (1 << 2), /* flags */ - d_int = (1 << 3), /* flags */ - d_txerr = (1 << 4), /* flags */ - d_stop = (1 << 4), /* status */ - d_ecp = (1 << 4), /* flags & status */ - d_pri = (1 << 5), /* flags & status */ - d_alignerr = (1 << 6), /* status */ - d_crcerr = (1 << 7) /* status */ -}; - -/* Do remember that DMA does not go through the MMU and needs - * a real physical address, not an address virtually mapped or - * paged. Therefore the buf/next ptrs below are unsigned long instead - * of void * to give a warning if you try to put a pointer directly - * to them instead of going through virt_to_phys/phys_to_virt. - */ - -typedef struct etrax_dma_descr { - unsigned short sw_len; /* 0-1 */ - unsigned short ctrl; /* 2-3 */ - unsigned long next; /* 4-7 */ - unsigned long buf; /* 8-11 */ - unsigned short hw_len; /* 12-13 */ - unsigned char status; /* 14 */ - unsigned char fifo_len; /* 15 */ -} etrax_dma_descr; - - -/* Use this for constant numbers only */ -#define RESET_DMA_NUM( n ) \ - *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) - -/* Use this for constant numbers or symbols, - * having two macros makes it possible to use constant expressions. - */ -#define RESET_DMA( n ) RESET_DMA_NUM( n ) - - -/* Use this for constant numbers only */ -#define WAIT_DMA_NUM( n ) \ - while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ - IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) - -/* Use this for constant numbers or symbols - * having two macros makes it possible to use constant expressions. - */ -#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) - -extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); -extern void flush_etrax_cache(void); - -#endif diff --git a/arch/cris/include/arch-v10/arch/user.h b/arch/cris/include/arch-v10/arch/user.h deleted file mode 100644 index 9303ea77c91..00000000000 --- a/arch/cris/include/arch-v10/arch/user.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __ASM_CRIS_ARCH_USER_H -#define __ASM_CRIS_ARCH_USER_H - -/* User mode registers, used for core dumps. In order to keep ELF_NGREG - sensible we let all registers be 32 bits. The csr registers are included - for future use. */ -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* Stack pointer. */ - unsigned long pc; /* Program counter. */ - unsigned long p0; /* Constant zero (only 8 bits). */ - unsigned long vr; /* Version register (only 8 bits). */ - unsigned long p2; /* Reserved. */ - unsigned long p3; /* Reserved. */ - unsigned long p4; /* Constant zero (only 16 bits). */ - unsigned long ccr; /* Condition code register (only 16 bits). */ - unsigned long p6; /* Reserved. */ - unsigned long mof; /* Multiply overflow register. */ - unsigned long p8; /* Constant zero. */ - unsigned long ibr; /* Not accessible. */ - unsigned long irp; /* Not accessible. */ - unsigned long srp; /* Subroutine return pointer. */ - unsigned long bar; /* Not accessible. */ - unsigned long dccr; /* Dword condition code register. */ - unsigned long brp; /* Not accessible. */ - unsigned long usp; /* User-mode stack pointer. Same as sp when - in user mode. */ - unsigned long csrinstr; /* Internal status registers. */ - unsigned long csraddr; - unsigned long csrdata; -}; - -#endif diff --git a/arch/cris/include/uapi/arch-v10/arch/Kbuild b/arch/cris/include/uapi/arch-v10/arch/Kbuild index aafaa5aa54d..9048c87a782 100644 --- a/arch/cris/include/uapi/arch-v10/arch/Kbuild +++ b/arch/cris/include/uapi/arch-v10/arch/Kbuild @@ -1 +1,5 @@ # UAPI Header export list +header-y += sv_addr.agh +header-y += sv_addr_ag.h +header-y += svinto.h +header-y += user.h diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh new file mode 100644 index 00000000000..6ac3a7bc976 --- /dev/null +++ b/arch/cris/include/uapi/arch-v10/arch/sv_addr.agh @@ -0,0 +1,7306 @@ +/* +!* This file was automatically generated by /n/asic/bin/reg_macro_gen +!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd'. +!* Editing within this file is thus not recommended, +!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead. +!*/ + + +/* +!* Bus interface configuration registers +!*/ + +#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000) +#define R_WAITSTATES__pcs4_7_zw__BITNR 30 +#define R_WAITSTATES__pcs4_7_zw__WIDTH 2 +#define R_WAITSTATES__pcs4_7_ew__BITNR 28 +#define R_WAITSTATES__pcs4_7_ew__WIDTH 2 +#define R_WAITSTATES__pcs4_7_lw__BITNR 24 +#define R_WAITSTATES__pcs4_7_lw__WIDTH 4 +#define R_WAITSTATES__pcs0_3_zw__BITNR 22 +#define R_WAITSTATES__pcs0_3_zw__WIDTH 2 +#define R_WAITSTATES__pcs0_3_ew__BITNR 20 +#define R_WAITSTATES__pcs0_3_ew__WIDTH 2 +#define R_WAITSTATES__pcs0_3_lw__BITNR 16 +#define R_WAITSTATES__pcs0_3_lw__WIDTH 4 +#define R_WAITSTATES__sram_zw__BITNR 14 +#define R_WAITSTATES__sram_zw__WIDTH 2 +#define R_WAITSTATES__sram_ew__BITNR 12 +#define R_WAITSTATES__sram_ew__WIDTH 2 +#define R_WAITSTATES__sram_lw__BITNR 8 +#define R_WAITSTATES__sram_lw__WIDTH 4 +#define R_WAITSTATES__flash_zw__BITNR 6 +#define R_WAITSTATES__flash_zw__WIDTH 2 +#define R_WAITSTATES__flash_ew__BITNR 4 +#define R_WAITSTATES__flash_ew__WIDTH 2 +#define R_WAITSTATES__flash_lw__BITNR 0 +#define R_WAITSTATES__flash_lw__WIDTH 4 + +#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004) +#define R_BUS_CONFIG__sram_type__BITNR 9 +#define R_BUS_CONFIG__sram_type__WIDTH 1 +#define R_BUS_CONFIG__sram_type__cwe 1 +#define R_BUS_CONFIG__sram_type__bwe 0 +#define R_BUS_CONFIG__dma_burst__BITNR 8 +#define R_BUS_CONFIG__dma_burst__WIDTH 1 +#define R_BUS_CONFIG__dma_burst__burst16 1 +#define R_BUS_CONFIG__dma_burst__burst32 0 +#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7 +#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_wr__ext 1 +#define R_BUS_CONFIG__pcs4_7_wr__norm 0 +#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6 +#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_wr__ext 1 +#define R_BUS_CONFIG__pcs0_3_wr__norm 0 +#define R_BUS_CONFIG__sram_wr__BITNR 5 +#define R_BUS_CONFIG__sram_wr__WIDTH 1 +#define R_BUS_CONFIG__sram_wr__ext 1 +#define R_BUS_CONFIG__sram_wr__norm 0 +#define R_BUS_CONFIG__flash_wr__BITNR 4 +#define R_BUS_CONFIG__flash_wr__WIDTH 1 +#define R_BUS_CONFIG__flash_wr__ext 1 +#define R_BUS_CONFIG__flash_wr__norm 0 +#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3 +#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw32 1 +#define R_BUS_CONFIG__pcs4_7_bw__bw16 0 +#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2 +#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw32 1 +#define R_BUS_CONFIG__pcs0_3_bw__bw16 0 +#define R_BUS_CONFIG__sram_bw__BITNR 1 +#define R_BUS_CONFIG__sram_bw__WIDTH 1 +#define R_BUS_CONFIG__sram_bw__bw32 1 +#define R_BUS_CONFIG__sram_bw__bw16 0 +#define R_BUS_CONFIG__flash_bw__BITNR 0 +#define R_BUS_CONFIG__flash_bw__WIDTH 1 +#define R_BUS_CONFIG__flash_bw__bw32 1 +#define R_BUS_CONFIG__flash_bw__bw16 0 + +#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004) +#define R_BUS_STATUS__pll_lock_tm__BITNR 5 +#define R_BUS_STATUS__pll_lock_tm__WIDTH 1 +#define R_BUS_STATUS__pll_lock_tm__expired 0 +#define R_BUS_STATUS__pll_lock_tm__counting 1 +#define R_BUS_STATUS__both_faults__BITNR 4 +#define R_BUS_STATUS__both_faults__WIDTH 1 +#define R_BUS_STATUS__both_faults__no 0 +#define R_BUS_STATUS__both_faults__yes 1 +#define R_BUS_STATUS__bsen___BITNR 3 +#define R_BUS_STATUS__bsen___WIDTH 1 +#define R_BUS_STATUS__bsen___enable 0 +#define R_BUS_STATUS__bsen___disable 1 +#define R_BUS_STATUS__boot__BITNR 1 +#define R_BUS_STATUS__boot__WIDTH 2 +#define R_BUS_STATUS__boot__uncached 0 +#define R_BUS_STATUS__boot__serial 1 +#define R_BUS_STATUS__boot__network 2 +#define R_BUS_STATUS__boot__parallel 3 +#define R_BUS_STATUS__flashw__BITNR 0 +#define R_BUS_STATUS__flashw__WIDTH 1 +#define R_BUS_STATUS__flashw__bw32 1 +#define R_BUS_STATUS__flashw__bw16 0 + +#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_DRAM_TIMING__sdram__BITNR 31 +#define R_DRAM_TIMING__sdram__WIDTH 1 +#define R_DRAM_TIMING__sdram__enable 1 +#define R_DRAM_TIMING__sdram__disable 0 +#define R_DRAM_TIMING__ref__BITNR 14 +#define R_DRAM_TIMING__ref__WIDTH 2 +#define R_DRAM_TIMING__ref__e52us 0 +#define R_DRAM_TIMING__ref__e13us 1 +#define R_DRAM_TIMING__ref__e8700ns 2 +#define R_DRAM_TIMING__ref__disable 3 +#define R_DRAM_TIMING__rp__BITNR 12 +#define R_DRAM_TIMING__rp__WIDTH 2 +#define R_DRAM_TIMING__rs__BITNR 10 +#define R_DRAM_TIMING__rs__WIDTH 2 +#define R_DRAM_TIMING__rh__BITNR 8 +#define R_DRAM_TIMING__rh__WIDTH 2 +#define R_DRAM_TIMING__w__BITNR 7 +#define R_DRAM_TIMING__w__WIDTH 1 +#define R_DRAM_TIMING__w__norm 0 +#define R_DRAM_TIMING__w__ext 1 +#define R_DRAM_TIMING__c__BITNR 6 +#define R_DRAM_TIMING__c__WIDTH 1 +#define R_DRAM_TIMING__c__norm 0 +#define R_DRAM_TIMING__c__ext 1 +#define R_DRAM_TIMING__cz__BITNR 4 +#define R_DRAM_TIMING__cz__WIDTH 2 +#define R_DRAM_TIMING__cp__BITNR 2 +#define R_DRAM_TIMING__cp__WIDTH 2 +#define R_DRAM_TIMING__cw__BITNR 0 +#define R_DRAM_TIMING__cw__WIDTH 2 + +#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008) +#define R_SDRAM_TIMING__sdram__BITNR 31 +#define R_SDRAM_TIMING__sdram__WIDTH 1 +#define R_SDRAM_TIMING__sdram__enable 1 +#define R_SDRAM_TIMING__sdram__disable 0 +#define R_SDRAM_TIMING__mrs_data__BITNR 16 +#define R_SDRAM_TIMING__mrs_data__WIDTH 15 +#define R_SDRAM_TIMING__ref__BITNR 14 +#define R_SDRAM_TIMING__ref__WIDTH 2 +#define R_SDRAM_TIMING__ref__e52us 0 +#define R_SDRAM_TIMING__ref__e13us 1 +#define R_SDRAM_TIMING__ref__e6500ns 2 +#define R_SDRAM_TIMING__ref__disable 3 +#define R_SDRAM_TIMING__ddr__BITNR 13 +#define R_SDRAM_TIMING__ddr__WIDTH 1 +#define R_SDRAM_TIMING__ddr__on 1 +#define R_SDRAM_TIMING__ddr__off 0 +#define R_SDRAM_TIMING__clk100__BITNR 12 +#define R_SDRAM_TIMING__clk100__WIDTH 1 +#define R_SDRAM_TIMING__clk100__on 1 +#define R_SDRAM_TIMING__clk100__off 0 +#define R_SDRAM_TIMING__ps__BITNR 11 +#define R_SDRAM_TIMING__ps__WIDTH 1 +#define R_SDRAM_TIMING__ps__on 1 +#define R_SDRAM_TIMING__ps__off 0 +#define R_SDRAM_TIMING__cmd__BITNR 9 +#define R_SDRAM_TIMING__cmd__WIDTH 2 +#define R_SDRAM_TIMING__cmd__pre 3 +#define R_SDRAM_TIMING__cmd__ref 2 +#define R_SDRAM_TIMING__cmd__mrs 1 +#define R_SDRAM_TIMING__cmd__nop 0 +#define R_SDRAM_TIMING__pde__BITNR 8 +#define R_SDRAM_TIMING__pde__WIDTH 1 +#define R_SDRAM_TIMING__rc__BITNR 6 +#define R_SDRAM_TIMING__rc__WIDTH 2 +#define R_SDRAM_TIMING__rp__BITNR 4 +#define R_SDRAM_TIMING__rp__WIDTH 2 +#define R_SDRAM_TIMING__rcd__BITNR 2 +#define R_SDRAM_TIMING__rcd__WIDTH 2 +#define R_SDRAM_TIMING__cl__BITNR 0 +#define R_SDRAM_TIMING__cl__WIDTH 2 + +#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_DRAM_CONFIG__wmm1__BITNR 31 +#define R_DRAM_CONFIG__wmm1__WIDTH 1 +#define R_DRAM_CONFIG__wmm1__wmm 1 +#define R_DRAM_CONFIG__wmm1__norm 0 +#define R_DRAM_CONFIG__wmm0__BITNR 30 +#define R_DRAM_CONFIG__wmm0__WIDTH 1 +#define R_DRAM_CONFIG__wmm0__wmm 1 +#define R_DRAM_CONFIG__wmm0__norm 0 +#define R_DRAM_CONFIG__sh1__BITNR 27 +#define R_DRAM_CONFIG__sh1__WIDTH 3 +#define R_DRAM_CONFIG__sh0__BITNR 24 +#define R_DRAM_CONFIG__sh0__WIDTH 3 +#define R_DRAM_CONFIG__w__BITNR 23 +#define R_DRAM_CONFIG__w__WIDTH 1 +#define R_DRAM_CONFIG__w__bw16 0 +#define R_DRAM_CONFIG__w__bw32 1 +#define R_DRAM_CONFIG__c__BITNR 22 +#define R_DRAM_CONFIG__c__WIDTH 1 +#define R_DRAM_CONFIG__c__byte 0 +#define R_DRAM_CONFIG__c__bank 1 +#define R_DRAM_CONFIG__e__BITNR 21 +#define R_DRAM_CONFIG__e__WIDTH 1 +#define R_DRAM_CONFIG__e__fast 0 +#define R_DRAM_CONFIG__e__edo 1 +#define R_DRAM_CONFIG__group_sel__BITNR 16 +#define R_DRAM_CONFIG__group_sel__WIDTH 5 +#define R_DRAM_CONFIG__group_sel__grp0 0 +#define R_DRAM_CONFIG__group_sel__grp1 1 +#define R_DRAM_CONFIG__group_sel__bit9 9 +#define R_DRAM_CONFIG__group_sel__bit10 10 +#define R_DRAM_CONFIG__group_sel__bit11 11 +#define R_DRAM_CONFIG__group_sel__bit12 12 +#define R_DRAM_CONFIG__group_sel__bit13 13 +#define R_DRAM_CONFIG__group_sel__bit14 14 +#define R_DRAM_CONFIG__group_sel__bit15 15 +#define R_DRAM_CONFIG__group_sel__bit16 16 +#define R_DRAM_CONFIG__group_sel__bit17 17 +#define R_DRAM_CONFIG__group_sel__bit18 18 +#define R_DRAM_CONFIG__group_sel__bit19 19 +#define R_DRAM_CONFIG__group_sel__bit20 20 +#define R_DRAM_CONFIG__group_sel__bit21 21 +#define R_DRAM_CONFIG__group_sel__bit22 22 +#define R_DRAM_CONFIG__group_sel__bit23 23 +#define R_DRAM_CONFIG__group_sel__bit24 24 +#define R_DRAM_CONFIG__group_sel__bit25 25 +#define R_DRAM_CONFIG__group_sel__bit26 26 +#define R_DRAM_CONFIG__group_sel__bit27 27 +#define R_DRAM_CONFIG__group_sel__bit28 28 +#define R_DRAM_CONFIG__group_sel__bit29 29 +#define R_DRAM_CONFIG__ca1__BITNR 13 +#define R_DRAM_CONFIG__ca1__WIDTH 3 +#define R_DRAM_CONFIG__bank23sel__BITNR 8 +#define R_DRAM_CONFIG__bank23sel__WIDTH 5 +#define R_DRAM_CONFIG__bank23sel__bank0 0 +#define R_DRAM_CONFIG__bank23sel__bank1 1 +#define R_DRAM_CONFIG__bank23sel__bit9 9 +#define R_DRAM_CONFIG__bank23sel__bit10 10 +#define R_DRAM_CONFIG__bank23sel__bit11 11 +#define R_DRAM_CONFIG__bank23sel__bit12 12 +#define R_DRAM_CONFIG__bank23sel__bit13 13 +#define R_DRAM_CONFIG__bank23sel__bit14 14 +#define R_DRAM_CONFIG__bank23sel__bit15 15 +#define R_DRAM_CONFIG__bank23sel__bit16 16 +#define R_DRAM_CONFIG__bank23sel__bit17 17 +#define R_DRAM_CONFIG__bank23sel__bit18 18 +#define R_DRAM_CONFIG__bank23sel__bit19 19 +#define R_DRAM_CONFIG__bank23sel__bit20 20 +#define R_DRAM_CONFIG__bank23sel__bit21 21 +#define R_DRAM_CONFIG__bank23sel__bit22 22 +#define R_DRAM_CONFIG__bank23sel__bit23 23 +#define R_DRAM_CONFIG__bank23sel__bit24 24 +#define R_DRAM_CONFIG__bank23sel__bit25 25 +#define R_DRAM_CONFIG__bank23sel__bit26 26 +#define R_DRAM_CONFIG__bank23sel__bit27 27 +#define R_DRAM_CONFIG__bank23sel__bit28 28 +#define R_DRAM_CONFIG__bank23sel__bit29 29 +#define R_DRAM_CONFIG__ca0__BITNR 5 +#define R_DRAM_CONFIG__ca0__WIDTH 3 +#define R_DRAM_CONFIG__bank01sel__BITNR 0 +#define R_DRAM_CONFIG__bank01sel__WIDTH 5 +#define R_DRAM_CONFIG__bank01sel__bank0 0 +#define R_DRAM_CONFIG__bank01sel__bank1 1 +#define R_DRAM_CONFIG__bank01sel__bit9 9 +#define R_DRAM_CONFIG__bank01sel__bit10 10 +#define R_DRAM_CONFIG__bank01sel__bit11 11 +#define R_DRAM_CONFIG__bank01sel__bit12 12 +#define R_DRAM_CONFIG__bank01sel__bit13 13 +#define R_DRAM_CONFIG__bank01sel__bit14 14 +#define R_DRAM_CONFIG__bank01sel__bit15 15 +#define R_DRAM_CONFIG__bank01sel__bit16 16 +#define R_DRAM_CONFIG__bank01sel__bit17 17 +#define R_DRAM_CONFIG__bank01sel__bit18 18 +#define R_DRAM_CONFIG__bank01sel__bit19 19 +#define R_DRAM_CONFIG__bank01sel__bit20 20 +#define R_DRAM_CONFIG__bank01sel__bit21 21 +#define R_DRAM_CONFIG__bank01sel__bit22 22 +#define R_DRAM_CONFIG__bank01sel__bit23 23 +#define R_DRAM_CONFIG__bank01sel__bit24 24 +#define R_DRAM_CONFIG__bank01sel__bit25 25 +#define R_DRAM_CONFIG__bank01sel__bit26 26 +#define R_DRAM_CONFIG__bank01sel__bit27 27 +#define R_DRAM_CONFIG__bank01sel__bit28 28 +#define R_DRAM_CONFIG__bank01sel__bit29 29 + +#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c) +#define R_SDRAM_CONFIG__wmm1__BITNR 31 +#define R_SDRAM_CONFIG__wmm1__WIDTH 1 +#define R_SDRAM_CONFIG__wmm1__wmm 1 +#define R_SDRAM_CONFIG__wmm1__norm 0 +#define R_SDRAM_CONFIG__wmm0__BITNR 30 +#define R_SDRAM_CONFIG__wmm0__WIDTH 1 +#define R_SDRAM_CONFIG__wmm0__wmm 1 +#define R_SDRAM_CONFIG__wmm0__norm 0 +#define R_SDRAM_CONFIG__sh1__BITNR 27 +#define R_SDRAM_CONFIG__sh1__WIDTH 3 +#define R_SDRAM_CONFIG__sh0__BITNR 24 +#define R_SDRAM_CONFIG__sh0__WIDTH 3 +#define R_SDRAM_CONFIG__w__BITNR 23 +#define R_SDRAM_CONFIG__w__WIDTH 1 +#define R_SDRAM_CONFIG__w__bw16 0 +#define R_SDRAM_CONFIG__w__bw32 1 +#define R_SDRAM_CONFIG__type1__BITNR 22 +#define R_SDRAM_CONFIG__type1__WIDTH 1 +#define R_SDRAM_CONFIG__type1__bank2 0 +#define R_SDRAM_CONFIG__type1__bank4 1 +#define R_SDRAM_CONFIG__type0__BITNR 21 +#define R_SDRAM_CONFIG__type0__WIDTH 1 +#define R_SDRAM_CONFIG__type0__bank2 0 +#define R_SDRAM_CONFIG__type0__bank4 1 +#define R_SDRAM_CONFIG__group_sel__BITNR 16 +#define R_SDRAM_CONFIG__group_sel__WIDTH 5 +#define R_SDRAM_CONFIG__group_sel__grp0 0 +#define R_SDRAM_CONFIG__group_sel__grp1 1 +#define R_SDRAM_CONFIG__group_sel__bit9 9 +#define R_SDRAM_CONFIG__group_sel__bit10 10 +#define R_SDRAM_CONFIG__group_sel__bit11 11 +#define R_SDRAM_CONFIG__group_sel__bit12 12 +#define R_SDRAM_CONFIG__group_sel__bit13 13 +#define R_SDRAM_CONFIG__group_sel__bit14 14 +#define R_SDRAM_CONFIG__group_sel__bit15 15 +#define R_SDRAM_CONFIG__group_sel__bit16 16 +#define R_SDRAM_CONFIG__group_sel__bit17 17 +#define R_SDRAM_CONFIG__group_sel__bit18 18 +#define R_SDRAM_CONFIG__group_sel__bit19 19 +#define R_SDRAM_CONFIG__group_sel__bit20 20 +#define R_SDRAM_CONFIG__group_sel__bit21 21 +#define R_SDRAM_CONFIG__group_sel__bit22 22 +#define R_SDRAM_CONFIG__group_sel__bit23 23 +#define R_SDRAM_CONFIG__group_sel__bit24 24 +#define R_SDRAM_CONFIG__group_sel__bit25 25 +#define R_SDRAM_CONFIG__group_sel__bit26 26 +#define R_SDRAM_CONFIG__group_sel__bit27 27 +#define R_SDRAM_CONFIG__group_sel__bit28 28 +#define R_SDRAM_CONFIG__group_sel__bit29 29 +#define R_SDRAM_CONFIG__ca1__BITNR 13 +#define R_SDRAM_CONFIG__ca1__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel1__BITNR 8 +#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel1__bit9 9 +#define R_SDRAM_CONFIG__bank_sel1__bit10 10 +#define R_SDRAM_CONFIG__bank_sel1__bit11 11 +#define R_SDRAM_CONFIG__bank_sel1__bit12 12 +#define R_SDRAM_CONFIG__bank_sel1__bit13 13 +#define R_SDRAM_CONFIG__bank_sel1__bit14 14 +#define R_SDRAM_CONFIG__bank_sel1__bit15 15 +#define R_SDRAM_CONFIG__bank_sel1__bit16 16 +#define R_SDRAM_CONFIG__bank_sel1__bit17 17 +#define R_SDRAM_CONFIG__bank_sel1__bit18 18 +#define R_SDRAM_CONFIG__bank_sel1__bit19 19 +#define R_SDRAM_CONFIG__bank_sel1__bit20 20 +#define R_SDRAM_CONFIG__bank_sel1__bit21 21 +#define R_SDRAM_CONFIG__bank_sel1__bit22 22 +#define R_SDRAM_CONFIG__bank_sel1__bit23 23 +#define R_SDRAM_CONFIG__bank_sel1__bit24 24 +#define R_SDRAM_CONFIG__bank_sel1__bit25 25 +#define R_SDRAM_CONFIG__bank_sel1__bit26 26 +#define R_SDRAM_CONFIG__bank_sel1__bit27 27 +#define R_SDRAM_CONFIG__bank_sel1__bit28 28 +#define R_SDRAM_CONFIG__bank_sel1__bit29 29 +#define R_SDRAM_CONFIG__ca0__BITNR 5 +#define R_SDRAM_CONFIG__ca0__WIDTH 3 +#define R_SDRAM_CONFIG__bank_sel0__BITNR 0 +#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5 +#define R_SDRAM_CONFIG__bank_sel0__bit9 9 +#define R_SDRAM_CONFIG__bank_sel0__bit10 10 +#define R_SDRAM_CONFIG__bank_sel0__bit11 11 +#define R_SDRAM_CONFIG__bank_sel0__bit12 12 +#define R_SDRAM_CONFIG__bank_sel0__bit13 13 +#define R_SDRAM_CONFIG__bank_sel0__bit14 14 +#define R_SDRAM_CONFIG__bank_sel0__bit15 15 +#define R_SDRAM_CONFIG__bank_sel0__bit16 16 +#define R_SDRAM_CONFIG__bank_sel0__bit17 17 +#define R_SDRAM_CONFIG__bank_sel0__bit18 18 +#define R_SDRAM_CONFIG__bank_sel0__bit19 19 +#define R_SDRAM_CONFIG__bank_sel0__bit20 20 +#define R_SDRAM_CONFIG__bank_sel0__bit21 21 +#define R_SDRAM_CONFIG__bank_sel0__bit22 22 +#define R_SDRAM_CONFIG__bank_sel0__bit23 23 +#define R_SDRAM_CONFIG__bank_sel0__bit24 24 +#define R_SDRAM_CONFIG__bank_sel0__bit25 25 +#define R_SDRAM_CONFIG__bank_sel0__bit26 26 +#define R_SDRAM_CONFIG__bank_sel0__bit27 27 +#define R_SDRAM_CONFIG__bank_sel0__bit28 28 +#define R_SDRAM_CONFIG__bank_sel0__bit29 29 + +/* +!* External DMA registers +!*/ + +#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010) +#define R_EXT_DMA_0_CMD__cnt__BITNR 23 +#define R_EXT_DMA_0_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_0_CMD__cnt__enable 1 +#define R_EXT_DMA_0_CMD__cnt__disable 0 +#define R_EXT_DMA_0_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_0_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_0_CMD__rqpol__alow 1 +#define R_EXT_DMA_0_CMD__apol__BITNR 21 +#define R_EXT_DMA_0_CMD__apol__WIDTH 1 +#define R_EXT_DMA_0_CMD__apol__ahigh 0 +#define R_EXT_DMA_0_CMD__apol__alow 1 +#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_0_CMD__rq_ack__burst 0 +#define R_EXT_DMA_0_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_0_CMD__wid__BITNR 18 +#define R_EXT_DMA_0_CMD__wid__WIDTH 2 +#define R_EXT_DMA_0_CMD__wid__byte 0 +#define R_EXT_DMA_0_CMD__wid__word 1 +#define R_EXT_DMA_0_CMD__wid__dword 2 +#define R_EXT_DMA_0_CMD__dir__BITNR 17 +#define R_EXT_DMA_0_CMD__dir__WIDTH 1 +#define R_EXT_DMA_0_CMD__dir__input 0 +#define R_EXT_DMA_0_CMD__dir__output 1 +#define R_EXT_DMA_0_CMD__run__BITNR 16 +#define R_EXT_DMA_0_CMD__run__WIDTH 1 +#define R_EXT_DMA_0_CMD__run__start 1 +#define R_EXT_DMA_0_CMD__run__stop 0 +#define R_EXT_DMA_0_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010) +#define R_EXT_DMA_0_STAT__run__BITNR 16 +#define R_EXT_DMA_0_STAT__run__WIDTH 1 +#define R_EXT_DMA_0_STAT__run__start 1 +#define R_EXT_DMA_0_STAT__run__stop 0 +#define R_EXT_DMA_0_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014) +#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28 + +#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018) +#define R_EXT_DMA_1_CMD__cnt__BITNR 23 +#define R_EXT_DMA_1_CMD__cnt__WIDTH 1 +#define R_EXT_DMA_1_CMD__cnt__enable 1 +#define R_EXT_DMA_1_CMD__cnt__disable 0 +#define R_EXT_DMA_1_CMD__rqpol__BITNR 22 +#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1 +#define R_EXT_DMA_1_CMD__rqpol__ahigh 0 +#define R_EXT_DMA_1_CMD__rqpol__alow 1 +#define R_EXT_DMA_1_CMD__apol__BITNR 21 +#define R_EXT_DMA_1_CMD__apol__WIDTH 1 +#define R_EXT_DMA_1_CMD__apol__ahigh 0 +#define R_EXT_DMA_1_CMD__apol__alow 1 +#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20 +#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1 +#define R_EXT_DMA_1_CMD__rq_ack__burst 0 +#define R_EXT_DMA_1_CMD__rq_ack__handsh 1 +#define R_EXT_DMA_1_CMD__wid__BITNR 18 +#define R_EXT_DMA_1_CMD__wid__WIDTH 2 +#define R_EXT_DMA_1_CMD__wid__byte 0 +#define R_EXT_DMA_1_CMD__wid__word 1 +#define R_EXT_DMA_1_CMD__wid__dword 2 +#define R_EXT_DMA_1_CMD__dir__BITNR 17 +#define R_EXT_DMA_1_CMD__dir__WIDTH 1 +#define R_EXT_DMA_1_CMD__dir__input 0 +#define R_EXT_DMA_1_CMD__dir__output 1 +#define R_EXT_DMA_1_CMD__run__BITNR 16 +#define R_EXT_DMA_1_CMD__run__WIDTH 1 +#define R_EXT_DMA_1_CMD__run__start 1 +#define R_EXT_DMA_1_CMD__run__stop 0 +#define R_EXT_DMA_1_CMD__trf_count__BITNR 0 +#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018) +#define R_EXT_DMA_1_STAT__run__BITNR 16 +#define R_EXT_DMA_1_STAT__run__WIDTH 1 +#define R_EXT_DMA_1_STAT__run__start 1 +#define R_EXT_DMA_1_STAT__run__stop 0 +#define R_EXT_DMA_1_STAT__trf_count__BITNR 0 +#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16 + +#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c) +#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2 +#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28 + +/* +!* Timer registers +!*/ + +#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020) +#define R_TIMER_CTRL__timerdiv1__BITNR 24 +#define R_TIMER_CTRL__timerdiv1__WIDTH 8 +#define R_TIMER_CTRL__timerdiv0__BITNR 16 +#define R_TIMER_CTRL__timerdiv0__WIDTH 8 +#define R_TIMER_CTRL__presc_timer1__BITNR 15 +#define R_TIMER_CTRL__presc_timer1__WIDTH 1 +#define R_TIMER_CTRL__presc_timer1__normal 0 +#define R_TIMER_CTRL__presc_timer1__prescale 1 +#define R_TIMER_CTRL__i1__BITNR 14 +#define R_TIMER_CTRL__i1__WIDTH 1 +#define R_TIMER_CTRL__i1__clr 1 +#define R_TIMER_CTRL__i1__nop 0 +#define R_TIMER_CTRL__tm1__BITNR 12 +#define R_TIMER_CTRL__tm1__WIDTH 2 +#define R_TIMER_CTRL__tm1__stop_ld 0 +#define R_TIMER_CTRL__tm1__freeze 1 +#define R_TIMER_CTRL__tm1__run 2 +#define R_TIMER_CTRL__tm1__reserved 3 +#define R_TIMER_CTRL__clksel1__BITNR 8 +#define R_TIMER_CTRL__clksel1__WIDTH 4 +#define R_TIMER_CTRL__clksel1__c300Hz 0 +#define R_TIMER_CTRL__clksel1__c600Hz 1 +#define R_TIMER_CTRL__clksel1__c1200Hz 2 +#define R_TIMER_CTRL__clksel1__c2400Hz 3 +#define R_TIMER_CTRL__clksel1__c4800Hz 4 +#define R_TIMER_CTRL__clksel1__c9600Hz 5 +#define R_TIMER_CTRL__clksel1__c19k2Hz 6 +#define R_TIMER_CTRL__clksel1__c38k4Hz 7 +#define R_TIMER_CTRL__clksel1__c57k6Hz 8 +#define R_TIMER_CTRL__clksel1__c115k2Hz 9 +#define R_TIMER_CTRL__clksel1__c230k4Hz 10 +#define R_TIMER_CTRL__clksel1__c460k8Hz 11 +#define R_TIMER_CTRL__clksel1__c921k6Hz 12 +#define R_TIMER_CTRL__clksel1__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel1__c6250kHz 14 +#define R_TIMER_CTRL__clksel1__cascade0 15 +#define R_TIMER_CTRL__presc_ext__BITNR 7 +#define R_TIMER_CTRL__presc_ext__WIDTH 1 +#define R_TIMER_CTRL__presc_ext__prescale 0 +#define R_TIMER_CTRL__presc_ext__external 1 +#define R_TIMER_CTRL__i0__BITNR 6 +#define R_TIMER_CTRL__i0__WIDTH 1 +#define R_TIMER_CTRL__i0__clr 1 +#define R_TIMER_CTRL__i0__nop 0 +#define R_TIMER_CTRL__tm0__BITNR 4 +#define R_TIMER_CTRL__tm0__WIDTH 2 +#define R_TIMER_CTRL__tm0__stop_ld 0 +#define R_TIMER_CTRL__tm0__freeze 1 +#define R_TIMER_CTRL__tm0__run 2 +#define R_TIMER_CTRL__tm0__reserved 3 +#define R_TIMER_CTRL__clksel0__BITNR 0 +#define R_TIMER_CTRL__clksel0__WIDTH 4 +#define R_TIMER_CTRL__clksel0__c300Hz 0 +#define R_TIMER_CTRL__clksel0__c600Hz 1 +#define R_TIMER_CTRL__clksel0__c1200Hz 2 +#define R_TIMER_CTRL__clksel0__c2400Hz 3 +#define R_TIMER_CTRL__clksel0__c4800Hz 4 +#define R_TIMER_CTRL__clksel0__c9600Hz 5 +#define R_TIMER_CTRL__clksel0__c19k2Hz 6 +#define R_TIMER_CTRL__clksel0__c38k4Hz 7 +#define R_TIMER_CTRL__clksel0__c57k6Hz 8 +#define R_TIMER_CTRL__clksel0__c115k2Hz 9 +#define R_TIMER_CTRL__clksel0__c230k4Hz 10 +#define R_TIMER_CTRL__clksel0__c460k8Hz 11 +#define R_TIMER_CTRL__clksel0__c921k6Hz 12 +#define R_TIMER_CTRL__clksel0__c1843k2Hz 13 +#define R_TIMER_CTRL__clksel0__c6250kHz 14 +#define R_TIMER_CTRL__clksel0__flexible 15 + +#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020) +#define R_TIMER_DATA__timer1__BITNR 24 +#define R_TIMER_DATA__timer1__WIDTH 8 +#define R_TIMER_DATA__timer0__BITNR 16 +#define R_TIMER_DATA__timer0__WIDTH 8 +#define R_TIMER_DATA__clkdiv_high__BITNR 8 +#define R_TIMER_DATA__clkdiv_high__WIDTH 8 +#define R_TIMER_DATA__clkdiv_low__BITNR 0 +#define R_TIMER_DATA__clkdiv_low__WIDTH 8 + +#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022) +#define R_TIMER01_DATA__count__BITNR 0 +#define R_TIMER01_DATA__count__WIDTH 16 + +#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022) +#define R_TIMER0_DATA__count__BITNR 0 +#define R_TIMER0_DATA__count__WIDTH 8 + +#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023) +#define R_TIMER1_DATA__count__BITNR 0 +#define R_TIMER1_DATA__count__WIDTH 8 + +#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024) +#define R_WATCHDOG__key__BITNR 1 +#define R_WATCHDOG__key__WIDTH 3 +#define R_WATCHDOG__enable__BITNR 0 +#define R_WATCHDOG__enable__WIDTH 1 +#define R_WATCHDOG__enable__stop 0 +#define R_WATCHDOG__enable__start 1 + +#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0) +#define R_CLOCK_PRESCALE__ser_presc__BITNR 16 +#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16 +#define R_CLOCK_PRESCALE__tim_presc__BITNR 0 +#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16 + +#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2) +#define R_SERIAL_PRESCALE__ser_presc__BITNR 0 +#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16 + +#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0) +#define R_TIMER_PRESCALE__tim_presc__BITNR 0 +#define R_TIMER_PRESCALE__tim_presc__WIDTH 16 + +#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0) +#define R_PRESCALE_STATUS__ser_status__BITNR 16 +#define R_PRESCALE_STATUS__ser_status__WIDTH 16 +#define R_PRESCALE_STATUS__tim_status__BITNR 0 +#define R_PRESCALE_STATUS__tim_status__WIDTH 16 + +#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2) +#define R_SER_PRESC_STATUS__ser_status__BITNR 0 +#define R_SER_PRESC_STATUS__ser_status__WIDTH 16 + +#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0) +#define R_TIM_PRESC_STATUS__tim_status__BITNR 0 +#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16 + +#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4) +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0 +#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0 +#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16 +#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6 +#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0 +#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11 +#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4 +#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0 +#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10 + +/* +!* Shared RAM interface registers +!*/ + +#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SHARED_RAM_CONFIG__width__BITNR 3 +#define R_SHARED_RAM_CONFIG__width__WIDTH 1 +#define R_SHARED_RAM_CONFIG__width__byte 0 +#define R_SHARED_RAM_CONFIG__width__word 1 +#define R_SHARED_RAM_CONFIG__enable__BITNR 2 +#define R_SHARED_RAM_CONFIG__enable__WIDTH 1 +#define R_SHARED_RAM_CONFIG__enable__yes 1 +#define R_SHARED_RAM_CONFIG__enable__no 0 +#define R_SHARED_RAM_CONFIG__pint__BITNR 1 +#define R_SHARED_RAM_CONFIG__pint__WIDTH 1 +#define R_SHARED_RAM_CONFIG__pint__int 1 +#define R_SHARED_RAM_CONFIG__pint__nop 0 +#define R_SHARED_RAM_CONFIG__clri__BITNR 0 +#define R_SHARED_RAM_CONFIG__clri__WIDTH 1 +#define R_SHARED_RAM_CONFIG__clri__clr 1 +#define R_SHARED_RAM_CONFIG__clri__nop 0 + +#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SHARED_RAM_ADDR__base_addr__BITNR 8 +#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22 + +/* +!* General config registers +!*/ + +#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c) +#define R_GEN_CONFIG__par_w__BITNR 31 +#define R_GEN_CONFIG__par_w__WIDTH 1 +#define R_GEN_CONFIG__par_w__select 1 +#define R_GEN_CONFIG__par_w__disable 0 +#define R_GEN_CONFIG__usb2__BITNR 30 +#define R_GEN_CONFIG__usb2__WIDTH 1 +#define R_GEN_CONFIG__usb2__select 1 +#define R_GEN_CONFIG__usb2__disable 0 +#define R_GEN_CONFIG__usb1__BITNR 29 +#define R_GEN_CONFIG__usb1__WIDTH 1 +#define R_GEN_CONFIG__usb1__select 1 +#define R_GEN_CONFIG__usb1__disable 0 +#define R_GEN_CONFIG__g24dir__BITNR 27 +#define R_GEN_CONFIG__g24dir__WIDTH 1 +#define R_GEN_CONFIG__g24dir__in 0 +#define R_GEN_CONFIG__g24dir__out 1 +#define R_GEN_CONFIG__g16_23dir__BITNR 26 +#define R_GEN_CONFIG__g16_23dir__WIDTH 1 +#define R_GEN_CONFIG__g16_23dir__in 0 +#define R_GEN_CONFIG__g16_23dir__out 1 +#define R_GEN_CONFIG__g8_15dir__BITNR 25 +#define R_GEN_CONFIG__g8_15dir__WIDTH 1 +#define R_GEN_CONFIG__g8_15dir__in 0 +#define R_GEN_CONFIG__g8_15dir__out 1 +#define R_GEN_CONFIG__g0dir__BITNR 24 +#define R_GEN_CONFIG__g0dir__WIDTH 1 +#define R_GEN_CONFIG__g0dir__in 0 +#define R_GEN_CONFIG__g0dir__out 1 +#define R_GEN_CONFIG__dma9__BITNR 23 +#define R_GEN_CONFIG__dma9__WIDTH 1 +#define R_GEN_CONFIG__dma9__usb 0 +#define R_GEN_CONFIG__dma9__serial1 1 +#define R_GEN_CONFIG__dma8__BITNR 22 +#define R_GEN_CONFIG__dma8__WIDTH 1 +#define R_GEN_CONFIG__dma8__usb 0 +#define R_GEN_CONFIG__dma8__serial1 1 +#define R_GEN_CONFIG__dma7__BITNR 20 +#define R_GEN_CONFIG__dma7__WIDTH 2 +#define R_GEN_CONFIG__dma7__unused 0 +#define R_GEN_CONFIG__dma7__serial0 1 +#define R_GEN_CONFIG__dma7__extdma1 2 +#define R_GEN_CONFIG__dma7__intdma6 3 +#define R_GEN_CONFIG__dma6__BITNR 18 +#define R_GEN_CONFIG__dma6__WIDTH 2 +#define R_GEN_CONFIG__dma6__unused 0 +#define R_GEN_CONFIG__dma6__serial0 1 +#define R_GEN_CONFIG__dma6__extdma1 2 +#define R_GEN_CONFIG__dma6__intdma7 3 +#define R_GEN_CONFIG__dma5__BITNR 16 +#define R_GEN_CONFIG__dma5__WIDTH 2 +#define R_GEN_CONFIG__dma5__par1 0 +#define R_GEN_CONFIG__dma5__scsi1 1 +#define R_GEN_CONFIG__dma5__serial3 2 +#define R_GEN_CONFIG__dma5__extdma0 3 +#define R_GEN_CONFIG__dma4__BITNR 14 +#define R_GEN_CONFIG__dma4__WIDTH 2 +#define R_GEN_CONFIG__dma4__par1 0 +#define R_GEN_CONFIG__dma4__scsi1 1 +#define R_GEN_CONFIG__dma4__serial3 2 +#define R_GEN_CONFIG__dma4__extdma0 3 +#define R_GEN_CONFIG__dma3__BITNR 12 +#define R_GEN_CONFIG__dma3__WIDTH 2 +#define R_GEN_CONFIG__dma3__par0 0 +#define R_GEN_CONFIG__dma3__scsi0 1 +#define R_GEN_CONFIG__dma3__serial2 2 +#define R_GEN_CONFIG__dma3__ata 3 +#define R_GEN_CONFIG__dma2__BITNR 10 +#define R_GEN_CONFIG__dma2__WIDTH 2 +#define R_GEN_CONFIG__dma2__par0 0 +#define R_GEN_CONFIG__dma2__scsi0 1 +#define R_GEN_CONFIG__dma2__serial2 2 +#define R_GEN_CONFIG__dma2__ata 3 +#define R_GEN_CONFIG__mio_w__BITNR 9 +#define R_GEN_CONFIG__mio_w__WIDTH 1 +#define R_GEN_CONFIG__mio_w__select 1 +#define R_GEN_CONFIG__mio_w__disable 0 +#define R_GEN_CONFIG__ser3__BITNR 8 +#define R_GEN_CONFIG__ser3__WIDTH 1 +#define R_GEN_CONFIG__ser3__select 1 +#define R_GEN_CONFIG__ser3__disable 0 +#define R_GEN_CONFIG__par1__BITNR 7 +#define R_GEN_CONFIG__par1__WIDTH 1 +#define R_GEN_CONFIG__par1__select 1 +#define R_GEN_CONFIG__par1__disable 0 +#define R_GEN_CONFIG__scsi0w__BITNR 6 +#define R_GEN_CONFIG__scsi0w__WIDTH 1 +#define R_GEN_CONFIG__scsi0w__select 1 +#define R_GEN_CONFIG__scsi0w__disable 0 +#define R_GEN_CONFIG__scsi1__BITNR 5 +#define R_GEN_CONFIG__scsi1__WIDTH 1 +#define R_GEN_CONFIG__scsi1__select 1 +#define R_GEN_CONFIG__scsi1__disable 0 +#define R_GEN_CONFIG__mio__BITNR 4 +#define R_GEN_CONFIG__mio__WIDTH 1 +#define R_GEN_CONFIG__mio__select 1 +#define R_GEN_CONFIG__mio__disable 0 +#define R_GEN_CONFIG__ser2__BITNR 3 +#define R_GEN_CONFIG__ser2__WIDTH 1 +#define R_GEN_CONFIG__ser2__select 1 +#define R_GEN_CONFIG__ser2__disable 0 +#define R_GEN_CONFIG__par0__BITNR 2 +#define R_GEN_CONFIG__par0__WIDTH 1 +#define R_GEN_CONFIG__par0__select 1 +#define R_GEN_CONFIG__par0__disable 0 +#define R_GEN_CONFIG__ata__BITNR 1 +#define R_GEN_CONFIG__ata__WIDTH 1 +#define R_GEN_CONFIG__ata__select 1 +#define R_GEN_CONFIG__ata__disable 0 +#define R_GEN_CONFIG__scsi0__BITNR 0 +#define R_GEN_CONFIG__scsi0__WIDTH 1 +#define R_GEN_CONFIG__scsi0__select 1 +#define R_GEN_CONFIG__scsi0__disable 0 + +#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034) +#define R_GEN_CONFIG_II__sermode3__BITNR 6 +#define R_GEN_CONFIG_II__sermode3__WIDTH 1 +#define R_GEN_CONFIG_II__sermode3__async 0 +#define R_GEN_CONFIG_II__sermode3__sync 1 +#define R_GEN_CONFIG_II__sermode1__BITNR 4 +#define R_GEN_CONFIG_II__sermode1__WIDTH 1 +#define R_GEN_CONFIG_II__sermode1__async 0 +#define R_GEN_CONFIG_II__sermode1__sync 1 +#define R_GEN_CONFIG_II__ext_clk__BITNR 2 +#define R_GEN_CONFIG_II__ext_clk__WIDTH 1 +#define R_GEN_CONFIG_II__ext_clk__select 1 +#define R_GEN_CONFIG_II__ext_clk__disable 0 +#define R_GEN_CONFIG_II__ser2__BITNR 1 +#define R_GEN_CONFIG_II__ser2__WIDTH 1 +#define R_GEN_CONFIG_II__ser2__select 1 +#define R_GEN_CONFIG_II__ser2__disable 0 +#define R_GEN_CONFIG_II__ser3__BITNR 0 +#define R_GEN_CONFIG_II__ser3__WIDTH 1 +#define R_GEN_CONFIG_II__ser3__select 1 +#define R_GEN_CONFIG_II__ser3__disable 0 + +#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028) +#define R_PORT_G_DATA__data__BITNR 0 +#define R_PORT_G_DATA__data__WIDTH 32 + +/* +!* General port configuration registers +!*/ + +#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030) +#define R_PORT_PA_SET__dir7__BITNR 15 +#define R_PORT_PA_SET__dir7__WIDTH 1 +#define R_PORT_PA_SET__dir7__input 0 +#define R_PORT_PA_SET__dir7__output 1 +#define R_PORT_PA_SET__dir6__BITNR 14 +#define R_PORT_PA_SET__dir6__WIDTH 1 +#define R_PORT_PA_SET__dir6__input 0 +#define R_PORT_PA_SET__dir6__output 1 +#define R_PORT_PA_SET__dir5__BITNR 13 +#define R_PORT_PA_SET__dir5__WIDTH 1 +#define R_PORT_PA_SET__dir5__input 0 +#define R_PORT_PA_SET__dir5__output 1 +#define R_PORT_PA_SET__dir4__BITNR 12 +#define R_PORT_PA_SET__dir4__WIDTH 1 +#define R_PORT_PA_SET__dir4__input 0 +#define R_PORT_PA_SET__dir4__output 1 +#define R_PORT_PA_SET__dir3__BITNR 11 +#define R_PORT_PA_SET__dir3__WIDTH 1 +#define R_PORT_PA_SET__dir3__input 0 +#define R_PORT_PA_SET__dir3__output 1 +#define R_PORT_PA_SET__dir2__BITNR 10 +#define R_PORT_PA_SET__dir2__WIDTH 1 +#define R_PORT_PA_SET__dir2__input 0 +#define R_PORT_PA_SET__dir2__output 1 +#define R_PORT_PA_SET__dir1__BITNR 9 +#define R_PORT_PA_SET__dir1__WIDTH 1 +#define R_PORT_PA_SET__dir1__input 0 +#define R_PORT_PA_SET__dir1__output 1 +#define R_PORT_PA_SET__dir0__BITNR 8 +#define R_PORT_PA_SET__dir0__WIDTH 1 +#define R_PORT_PA_SET__dir0__input 0 +#define R_PORT_PA_SET__dir0__output 1 +#define R_PORT_PA_SET__data_out__BITNR 0 +#define R_PORT_PA_SET__data_out__WIDTH 8 + +#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030) +#define R_PORT_PA_DATA__data_out__BITNR 0 +#define R_PORT_PA_DATA__data_out__WIDTH 8 + +#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031) +#define R_PORT_PA_DIR__dir7__BITNR 7 +#define R_PORT_PA_DIR__dir7__WIDTH 1 +#define R_PORT_PA_DIR__dir7__input 0 +#define R_PORT_PA_DIR__dir7__output 1 +#define R_PORT_PA_DIR__dir6__BITNR 6 +#define R_PORT_PA_DIR__dir6__WIDTH 1 +#define R_PORT_PA_DIR__dir6__input 0 +#define R_PORT_PA_DIR__dir6__output 1 +#define R_PORT_PA_DIR__dir5__BITNR 5 +#define R_PORT_PA_DIR__dir5__WIDTH 1 +#define R_PORT_PA_DIR__dir5__input 0 +#define R_PORT_PA_DIR__dir5__output 1 +#define R_PORT_PA_DIR__dir4__BITNR 4 +#define R_PORT_PA_DIR__dir4__WIDTH 1 +#define R_PORT_PA_DIR__dir4__input 0 +#define R_PORT_PA_DIR__dir4__output 1 +#define R_PORT_PA_DIR__dir3__BITNR 3 +#define R_PORT_PA_DIR__dir3__WIDTH 1 +#define R_PORT_PA_DIR__dir3__input 0 +#define R_PORT_PA_DIR__dir3__output 1 +#define R_PORT_PA_DIR__dir2__BITNR 2 +#define R_PORT_PA_DIR__dir2__WIDTH 1 +#define R_PORT_PA_DIR__dir2__input 0 +#define R_PORT_PA_DIR__dir2__output 1 +#define R_PORT_PA_DIR__dir1__BITNR 1 +#define R_PORT_PA_DIR__dir1__WIDTH 1 +#define R_PORT_PA_DIR__dir1__input 0 +#define R_PORT_PA_DIR__dir1__output 1 +#define R_PORT_PA_DIR__dir0__BITNR 0 +#define R_PORT_PA_DIR__dir0__WIDTH 1 +#define R_PORT_PA_DIR__dir0__input 0 +#define R_PORT_PA_DIR__dir0__output 1 + +#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030) +#define R_PORT_PA_READ__data_in__BITNR 0 +#define R_PORT_PA_READ__data_in__WIDTH 8 + +#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038) +#define R_PORT_PB_SET__syncser3__BITNR 29 +#define R_PORT_PB_SET__syncser3__WIDTH 1 +#define R_PORT_PB_SET__syncser3__port_cs 0 +#define R_PORT_PB_SET__syncser3__ss3extra 1 +#define R_PORT_PB_SET__syncser1__BITNR 28 +#define R_PORT_PB_SET__syncser1__WIDTH 1 +#define R_PORT_PB_SET__syncser1__port_cs 0 +#define R_PORT_PB_SET__syncser1__ss1extra 1 +#define R_PORT_PB_SET__i2c_en__BITNR 27 +#define R_PORT_PB_SET__i2c_en__WIDTH 1 +#define R_PORT_PB_SET__i2c_en__off 0 +#define R_PORT_PB_SET__i2c_en__on 1 +#define R_PORT_PB_SET__i2c_d__BITNR 26 +#define R_PORT_PB_SET__i2c_d__WIDTH 1 +#define R_PORT_PB_SET__i2c_clk__BITNR 25 +#define R_PORT_PB_SET__i2c_clk__WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___BITNR 24 +#define R_PORT_PB_SET__i2c_oe___WIDTH 1 +#define R_PORT_PB_SET__i2c_oe___enable 0 +#define R_PORT_PB_SET__i2c_oe___disable 1 +#define R_PORT_PB_SET__cs7__BITNR 23 +#define R_PORT_PB_SET__cs7__WIDTH 1 +#define R_PORT_PB_SET__cs7__port 0 +#define R_PORT_PB_SET__cs7__cs 1 +#define R_PORT_PB_SET__cs6__BITNR 22 +#define R_PORT_PB_SET__cs6__WIDTH 1 +#define R_PORT_PB_SET__cs6__port 0 +#define R_PORT_PB_SET__cs6__cs 1 +#define R_PORT_PB_SET__cs5__BITNR 21 +#define R_PORT_PB_SET__cs5__WIDTH 1 +#define R_PORT_PB_SET__cs5__port 0 +#define R_PORT_PB_SET__cs5__cs 1 +#define R_PORT_PB_SET__cs4__BITNR 20 +#define R_PORT_PB_SET__cs4__WIDTH 1 +#define R_PORT_PB_SET__cs4__port 0 +#define R_PORT_PB_SET__cs4__cs 1 +#define R_PORT_PB_SET__cs3__BITNR 19 +#define R_PORT_PB_SET__cs3__WIDTH 1 +#define R_PORT_PB_SET__cs3__port 0 +#define R_PORT_PB_SET__cs3__cs 1 +#define R_PORT_PB_SET__cs2__BITNR 18 +#define R_PORT_PB_SET__cs2__WIDTH 1 +#define R_PORT_PB_SET__cs2__port 0 +#define R_PORT_PB_SET__cs2__cs 1 +#define R_PORT_PB_SET__scsi1__BITNR 17 +#define R_PORT_PB_SET__scsi1__WIDTH 1 +#define R_PORT_PB_SET__scsi1__port_cs 0 +#define R_PORT_PB_SET__scsi1__enph 1 +#define R_PORT_PB_SET__scsi0__BITNR 16 +#define R_PORT_PB_SET__scsi0__WIDTH 1 +#define R_PORT_PB_SET__scsi0__port_cs 0 +#define R_PORT_PB_SET__scsi0__enph 1 +#define R_PORT_PB_SET__dir7__BITNR 15 +#define R_PORT_PB_SET__dir7__WIDTH 1 +#define R_PORT_PB_SET__dir7__input 0 +#define R_PORT_PB_SET__dir7__output 1 +#define R_PORT_PB_SET__dir6__BITNR 14 +#define R_PORT_PB_SET__dir6__WIDTH 1 +#define R_PORT_PB_SET__dir6__input 0 +#define R_PORT_PB_SET__dir6__output 1 +#define R_PORT_PB_SET__dir5__BITNR 13 +#define R_PORT_PB_SET__dir5__WIDTH 1 +#define R_PORT_PB_SET__dir5__input 0 +#define R_PORT_PB_SET__dir5__output 1 +#define R_PORT_PB_SET__dir4__BITNR 12 +#define R_PORT_PB_SET__dir4__WIDTH 1 +#define R_PORT_PB_SET__dir4__input 0 +#define R_PORT_PB_SET__dir4__output 1 +#define R_PORT_PB_SET__dir3__BITNR 11 +#define R_PORT_PB_SET__dir3__WIDTH 1 +#define R_PORT_PB_SET__dir3__input 0 +#define R_PORT_PB_SET__dir3__output 1 +#define R_PORT_PB_SET__dir2__BITNR 10 +#define R_PORT_PB_SET__dir2__WIDTH 1 +#define R_PORT_PB_SET__dir2__input 0 +#define R_PORT_PB_SET__dir2__output 1 +#define R_PORT_PB_SET__dir1__BITNR 9 +#define R_PORT_PB_SET__dir1__WIDTH 1 +#define R_PORT_PB_SET__dir1__input 0 +#define R_PORT_PB_SET__dir1__output 1 +#define R_PORT_PB_SET__dir0__BITNR 8 +#define R_PORT_PB_SET__dir0__WIDTH 1 +#define R_PORT_PB_SET__dir0__input 0 +#define R_PORT_PB_SET__dir0__output 1 +#define R_PORT_PB_SET__data_out__BITNR 0 +#define R_PORT_PB_SET__data_out__WIDTH 8 + +#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038) +#define R_PORT_PB_DATA__data_out__BITNR 0 +#define R_PORT_PB_DATA__data_out__WIDTH 8 + +#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039) +#define R_PORT_PB_DIR__dir7__BITNR 7 +#define R_PORT_PB_DIR__dir7__WIDTH 1 +#define R_PORT_PB_DIR__dir7__input 0 +#define R_PORT_PB_DIR__dir7__output 1 +#define R_PORT_PB_DIR__dir6__BITNR 6 +#define R_PORT_PB_DIR__dir6__WIDTH 1 +#define R_PORT_PB_DIR__dir6__input 0 +#define R_PORT_PB_DIR__dir6__output 1 +#define R_PORT_PB_DIR__dir5__BITNR 5 +#define R_PORT_PB_DIR__dir5__WIDTH 1 +#define R_PORT_PB_DIR__dir5__input 0 +#define R_PORT_PB_DIR__dir5__output 1 +#define R_PORT_PB_DIR__dir4__BITNR 4 +#define R_PORT_PB_DIR__dir4__WIDTH 1 +#define R_PORT_PB_DIR__dir4__input 0 +#define R_PORT_PB_DIR__dir4__output 1 +#define R_PORT_PB_DIR__dir3__BITNR 3 +#define R_PORT_PB_DIR__dir3__WIDTH 1 +#define R_PORT_PB_DIR__dir3__input 0 +#define R_PORT_PB_DIR__dir3__output 1 +#define R_PORT_PB_DIR__dir2__BITNR 2 +#define R_PORT_PB_DIR__dir2__WIDTH 1 +#define R_PORT_PB_DIR__dir2__input 0 +#define R_PORT_PB_DIR__dir2__output 1 +#define R_PORT_PB_DIR__dir1__BITNR 1 +#define R_PORT_PB_DIR__dir1__WIDTH 1 +#define R_PORT_PB_DIR__dir1__input 0 +#define R_PORT_PB_DIR__dir1__output 1 +#define R_PORT_PB_DIR__dir0__BITNR 0 +#define R_PORT_PB_DIR__dir0__WIDTH 1 +#define R_PORT_PB_DIR__dir0__input 0 +#define R_PORT_PB_DIR__dir0__output 1 + +#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a) +#define R_PORT_PB_CONFIG__cs7__BITNR 7 +#define R_PORT_PB_CONFIG__cs7__WIDTH 1 +#define R_PORT_PB_CONFIG__cs7__port 0 +#define R_PORT_PB_CONFIG__cs7__cs 1 +#define R_PORT_PB_CONFIG__cs6__BITNR 6 +#define R_PORT_PB_CONFIG__cs6__WIDTH 1 +#define R_PORT_PB_CONFIG__cs6__port 0 +#define R_PORT_PB_CONFIG__cs6__cs 1 +#define R_PORT_PB_CONFIG__cs5__BITNR 5 +#define R_PORT_PB_CONFIG__cs5__WIDTH 1 +#define R_PORT_PB_CONFIG__cs5__port 0 +#define R_PORT_PB_CONFIG__cs5__cs 1 +#define R_PORT_PB_CONFIG__cs4__BITNR 4 +#define R_PORT_PB_CONFIG__cs4__WIDTH 1 +#define R_PORT_PB_CONFIG__cs4__port 0 +#define R_PORT_PB_CONFIG__cs4__cs 1 +#define R_PORT_PB_CONFIG__cs3__BITNR 3 +#define R_PORT_PB_CONFIG__cs3__WIDTH 1 +#define R_PORT_PB_CONFIG__cs3__port 0 +#define R_PORT_PB_CONFIG__cs3__cs 1 +#define R_PORT_PB_CONFIG__cs2__BITNR 2 +#define R_PORT_PB_CONFIG__cs2__WIDTH 1 +#define R_PORT_PB_CONFIG__cs2__port 0 +#define R_PORT_PB_CONFIG__cs2__cs 1 +#define R_PORT_PB_CONFIG__scsi1__BITNR 1 +#define R_PORT_PB_CONFIG__scsi1__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi1__port_cs 0 +#define R_PORT_PB_CONFIG__scsi1__enph 1 +#define R_PORT_PB_CONFIG__scsi0__BITNR 0 +#define R_PORT_PB_CONFIG__scsi0__WIDTH 1 +#define R_PORT_PB_CONFIG__scsi0__port_cs 0 +#define R_PORT_PB_CONFIG__scsi0__enph 1 + +#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b) +#define R_PORT_PB_I2C__syncser3__BITNR 5 +#define R_PORT_PB_I2C__syncser3__WIDTH 1 +#define R_PORT_PB_I2C__syncser3__port_cs 0 +#define R_PORT_PB_I2C__syncser3__ss3extra 1 +#define R_PORT_PB_I2C__syncser1__BITNR 4 +#define R_PORT_PB_I2C__syncser1__WIDTH 1 +#define R_PORT_PB_I2C__syncser1__port_cs 0 +#define R_PORT_PB_I2C__syncser1__ss1extra 1 +#define R_PORT_PB_I2C__i2c_en__BITNR 3 +#define R_PORT_PB_I2C__i2c_en__WIDTH 1 +#define R_PORT_PB_I2C__i2c_en__off 0 +#define R_PORT_PB_I2C__i2c_en__on 1 +#define R_PORT_PB_I2C__i2c_d__BITNR 2 +#define R_PORT_PB_I2C__i2c_d__WIDTH 1 +#define R_PORT_PB_I2C__i2c_clk__BITNR 1 +#define R_PORT_PB_I2C__i2c_clk__WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___BITNR 0 +#define R_PORT_PB_I2C__i2c_oe___WIDTH 1 +#define R_PORT_PB_I2C__i2c_oe___enable 0 +#define R_PORT_PB_I2C__i2c_oe___disable 1 + +#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038) +#define R_PORT_PB_READ__data_in__BITNR 0 +#define R_PORT_PB_READ__data_in__WIDTH 8 + +/* +!* Serial port registers +!*/ + +#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060) +#define R_SERIAL0_CTRL__tr_baud__BITNR 28 +#define R_SERIAL0_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL0_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL0_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__tr_baud__reserved 15 +#define R_SERIAL0_CTRL__rec_baud__BITNR 24 +#define R_SERIAL0_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL0_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL0_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL0_CTRL__rec_baud__reserved 15 +#define R_SERIAL0_CTRL__dma_err__BITNR 23 +#define R_SERIAL0_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_CTRL__dma_err__stop 0 +#define R_SERIAL0_CTRL__dma_err__ignore 1 +#define R_SERIAL0_CTRL__rec_enable__BITNR 22 +#define R_SERIAL0_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_CTRL__rec_enable__disable 0 +#define R_SERIAL0_CTRL__rec_enable__enable 1 +#define R_SERIAL0_CTRL__rts___BITNR 21 +#define R_SERIAL0_CTRL__rts___WIDTH 1 +#define R_SERIAL0_CTRL__rts___active 0 +#define R_SERIAL0_CTRL__rts___inactive 1 +#define R_SERIAL0_CTRL__sampling__BITNR 20 +#define R_SERIAL0_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_CTRL__sampling__middle 0 +#define R_SERIAL0_CTRL__sampling__majority 1 +#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_CTRL__rec_par__BITNR 18 +#define R_SERIAL0_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par__even 0 +#define R_SERIAL0_CTRL__rec_par__odd 1 +#define R_SERIAL0_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL0_CTRL__txd__BITNR 15 +#define R_SERIAL0_CTRL__txd__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__BITNR 14 +#define R_SERIAL0_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_CTRL__tr_enable__disable 0 +#define R_SERIAL0_CTRL__tr_enable__enable 1 +#define R_SERIAL0_CTRL__auto_cts__BITNR 13 +#define R_SERIAL0_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_CTRL__auto_cts__active 1 +#define R_SERIAL0_CTRL__stop_bits__BITNR 12 +#define R_SERIAL0_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_CTRL__tr_par__BITNR 10 +#define R_SERIAL0_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par__even 0 +#define R_SERIAL0_CTRL__tr_par__odd 1 +#define R_SERIAL0_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL0_CTRL__data_out__BITNR 0 +#define R_SERIAL0_CTRL__data_out__WIDTH 8 + +#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063) +#define R_SERIAL0_BAUD__tr_baud__BITNR 4 +#define R_SERIAL0_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL0_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL0_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__tr_baud__reserved 15 +#define R_SERIAL0_BAUD__rec_baud__BITNR 0 +#define R_SERIAL0_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL0_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL0_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL0_BAUD__rec_baud__reserved 15 + +#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062) +#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL0_REC_CTRL__dma_err__stop 0 +#define R_SERIAL0_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL0_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL0_REC_CTRL__rts___BITNR 5 +#define R_SERIAL0_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL0_REC_CTRL__rts___active 0 +#define R_SERIAL0_REC_CTRL__rts___inactive 1 +#define R_SERIAL0_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL0_REC_CTRL__sampling__middle 0 +#define R_SERIAL0_REC_CTRL__sampling__majority 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par__even 0 +#define R_SERIAL0_REC_CTRL__rec_par__odd 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061) +#define R_SERIAL0_TR_CTRL__txd__BITNR 7 +#define R_SERIAL0_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL0_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL0_TR_CTRL__auto_cts__active 1 +#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par__even 0 +#define R_SERIAL0_TR_CTRL__tr_par__odd 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060) +#define R_SERIAL0_TR_DATA__data_out__BITNR 0 +#define R_SERIAL0_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060) +#define R_SERIAL0_READ__xoff_detect__BITNR 15 +#define R_SERIAL0_READ__xoff_detect__WIDTH 1 +#define R_SERIAL0_READ__xoff_detect__no_xoff 0 +#define R_SERIAL0_READ__xoff_detect__xoff 1 +#define R_SERIAL0_READ__cts___BITNR 14 +#define R_SERIAL0_READ__cts___WIDTH 1 +#define R_SERIAL0_READ__cts___active 0 +#define R_SERIAL0_READ__cts___inactive 1 +#define R_SERIAL0_READ__tr_ready__BITNR 13 +#define R_SERIAL0_READ__tr_ready__WIDTH 1 +#define R_SERIAL0_READ__tr_ready__full 0 +#define R_SERIAL0_READ__tr_ready__ready 1 +#define R_SERIAL0_READ__rxd__BITNR 12 +#define R_SERIAL0_READ__rxd__WIDTH 1 +#define R_SERIAL0_READ__overrun__BITNR 11 +#define R_SERIAL0_READ__overrun__WIDTH 1 +#define R_SERIAL0_READ__overrun__no 0 +#define R_SERIAL0_READ__overrun__yes 1 +#define R_SERIAL0_READ__par_err__BITNR 10 +#define R_SERIAL0_READ__par_err__WIDTH 1 +#define R_SERIAL0_READ__par_err__no 0 +#define R_SERIAL0_READ__par_err__yes 1 +#define R_SERIAL0_READ__framing_err__BITNR 9 +#define R_SERIAL0_READ__framing_err__WIDTH 1 +#define R_SERIAL0_READ__framing_err__no 0 +#define R_SERIAL0_READ__framing_err__yes 1 +#define R_SERIAL0_READ__data_avail__BITNR 8 +#define R_SERIAL0_READ__data_avail__WIDTH 1 +#define R_SERIAL0_READ__data_avail__no 0 +#define R_SERIAL0_READ__data_avail__yes 1 +#define R_SERIAL0_READ__data_in__BITNR 0 +#define R_SERIAL0_READ__data_in__WIDTH 8 + +#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061) +#define R_SERIAL0_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL0_STATUS__xoff_detect__xoff 1 +#define R_SERIAL0_STATUS__cts___BITNR 6 +#define R_SERIAL0_STATUS__cts___WIDTH 1 +#define R_SERIAL0_STATUS__cts___active 0 +#define R_SERIAL0_STATUS__cts___inactive 1 +#define R_SERIAL0_STATUS__tr_ready__BITNR 5 +#define R_SERIAL0_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL0_STATUS__tr_ready__full 0 +#define R_SERIAL0_STATUS__tr_ready__ready 1 +#define R_SERIAL0_STATUS__rxd__BITNR 4 +#define R_SERIAL0_STATUS__rxd__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__BITNR 3 +#define R_SERIAL0_STATUS__overrun__WIDTH 1 +#define R_SERIAL0_STATUS__overrun__no 0 +#define R_SERIAL0_STATUS__overrun__yes 1 +#define R_SERIAL0_STATUS__par_err__BITNR 2 +#define R_SERIAL0_STATUS__par_err__WIDTH 1 +#define R_SERIAL0_STATUS__par_err__no 0 +#define R_SERIAL0_STATUS__par_err__yes 1 +#define R_SERIAL0_STATUS__framing_err__BITNR 1 +#define R_SERIAL0_STATUS__framing_err__WIDTH 1 +#define R_SERIAL0_STATUS__framing_err__no 0 +#define R_SERIAL0_STATUS__framing_err__yes 1 +#define R_SERIAL0_STATUS__data_avail__BITNR 0 +#define R_SERIAL0_STATUS__data_avail__WIDTH 1 +#define R_SERIAL0_STATUS__data_avail__no 0 +#define R_SERIAL0_STATUS__data_avail__yes 1 + +#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060) +#define R_SERIAL0_REC_DATA__data_in__BITNR 0 +#define R_SERIAL0_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064) +#define R_SERIAL0_XOFF__tx_stop__BITNR 9 +#define R_SERIAL0_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL0_XOFF__tx_stop__enable 0 +#define R_SERIAL0_XOFF__tx_stop__stop 1 +#define R_SERIAL0_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL0_XOFF__auto_xoff__disable 0 +#define R_SERIAL0_XOFF__auto_xoff__enable 1 +#define R_SERIAL0_XOFF__xoff_char__BITNR 0 +#define R_SERIAL0_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL1_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL1_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SERIAL1_CTRL__rec_baud__BITNR 24 +#define R_SERIAL1_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL1_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL1_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL1_CTRL__rec_baud__reserved 15 +#define R_SERIAL1_CTRL__dma_err__BITNR 23 +#define R_SERIAL1_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_CTRL__dma_err__stop 0 +#define R_SERIAL1_CTRL__dma_err__ignore 1 +#define R_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SERIAL1_CTRL__rts___BITNR 21 +#define R_SERIAL1_CTRL__rts___WIDTH 1 +#define R_SERIAL1_CTRL__rts___active 0 +#define R_SERIAL1_CTRL__rts___inactive 1 +#define R_SERIAL1_CTRL__sampling__BITNR 20 +#define R_SERIAL1_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_CTRL__sampling__middle 0 +#define R_SERIAL1_CTRL__sampling__majority 1 +#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_CTRL__rec_par__BITNR 18 +#define R_SERIAL1_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par__even 0 +#define R_SERIAL1_CTRL__rec_par__odd 1 +#define R_SERIAL1_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL1_CTRL__txd__BITNR 15 +#define R_SERIAL1_CTRL__txd__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SERIAL1_CTRL__auto_cts__BITNR 13 +#define R_SERIAL1_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_CTRL__auto_cts__active 1 +#define R_SERIAL1_CTRL__stop_bits__BITNR 12 +#define R_SERIAL1_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_CTRL__tr_par__BITNR 10 +#define R_SERIAL1_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par__even 0 +#define R_SERIAL1_CTRL__tr_par__odd 1 +#define R_SERIAL1_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL1_CTRL__data_out__BITNR 0 +#define R_SERIAL1_CTRL__data_out__WIDTH 8 + +#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b) +#define R_SERIAL1_BAUD__tr_baud__BITNR 4 +#define R_SERIAL1_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL1_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL1_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__tr_baud__reserved 15 +#define R_SERIAL1_BAUD__rec_baud__BITNR 0 +#define R_SERIAL1_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL1_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL1_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL1_BAUD__rec_baud__reserved 15 + +#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a) +#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL1_REC_CTRL__dma_err__stop 0 +#define R_SERIAL1_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL1_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL1_REC_CTRL__rts___BITNR 5 +#define R_SERIAL1_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL1_REC_CTRL__rts___active 0 +#define R_SERIAL1_REC_CTRL__rts___inactive 1 +#define R_SERIAL1_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL1_REC_CTRL__sampling__middle 0 +#define R_SERIAL1_REC_CTRL__sampling__majority 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par__even 0 +#define R_SERIAL1_REC_CTRL__rec_par__odd 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069) +#define R_SERIAL1_TR_CTRL__txd__BITNR 7 +#define R_SERIAL1_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL1_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL1_TR_CTRL__auto_cts__active 1 +#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par__even 0 +#define R_SERIAL1_TR_CTRL__tr_par__odd 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068) +#define R_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SERIAL1_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SERIAL1_READ__xoff_detect__BITNR 15 +#define R_SERIAL1_READ__xoff_detect__WIDTH 1 +#define R_SERIAL1_READ__xoff_detect__no_xoff 0 +#define R_SERIAL1_READ__xoff_detect__xoff 1 +#define R_SERIAL1_READ__cts___BITNR 14 +#define R_SERIAL1_READ__cts___WIDTH 1 +#define R_SERIAL1_READ__cts___active 0 +#define R_SERIAL1_READ__cts___inactive 1 +#define R_SERIAL1_READ__tr_ready__BITNR 13 +#define R_SERIAL1_READ__tr_ready__WIDTH 1 +#define R_SERIAL1_READ__tr_ready__full 0 +#define R_SERIAL1_READ__tr_ready__ready 1 +#define R_SERIAL1_READ__rxd__BITNR 12 +#define R_SERIAL1_READ__rxd__WIDTH 1 +#define R_SERIAL1_READ__overrun__BITNR 11 +#define R_SERIAL1_READ__overrun__WIDTH 1 +#define R_SERIAL1_READ__overrun__no 0 +#define R_SERIAL1_READ__overrun__yes 1 +#define R_SERIAL1_READ__par_err__BITNR 10 +#define R_SERIAL1_READ__par_err__WIDTH 1 +#define R_SERIAL1_READ__par_err__no 0 +#define R_SERIAL1_READ__par_err__yes 1 +#define R_SERIAL1_READ__framing_err__BITNR 9 +#define R_SERIAL1_READ__framing_err__WIDTH 1 +#define R_SERIAL1_READ__framing_err__no 0 +#define R_SERIAL1_READ__framing_err__yes 1 +#define R_SERIAL1_READ__data_avail__BITNR 8 +#define R_SERIAL1_READ__data_avail__WIDTH 1 +#define R_SERIAL1_READ__data_avail__no 0 +#define R_SERIAL1_READ__data_avail__yes 1 +#define R_SERIAL1_READ__data_in__BITNR 0 +#define R_SERIAL1_READ__data_in__WIDTH 8 + +#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069) +#define R_SERIAL1_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL1_STATUS__xoff_detect__xoff 1 +#define R_SERIAL1_STATUS__cts___BITNR 6 +#define R_SERIAL1_STATUS__cts___WIDTH 1 +#define R_SERIAL1_STATUS__cts___active 0 +#define R_SERIAL1_STATUS__cts___inactive 1 +#define R_SERIAL1_STATUS__tr_ready__BITNR 5 +#define R_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL1_STATUS__tr_ready__full 0 +#define R_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SERIAL1_STATUS__rxd__BITNR 4 +#define R_SERIAL1_STATUS__rxd__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__BITNR 3 +#define R_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SERIAL1_STATUS__overrun__no 0 +#define R_SERIAL1_STATUS__overrun__yes 1 +#define R_SERIAL1_STATUS__par_err__BITNR 2 +#define R_SERIAL1_STATUS__par_err__WIDTH 1 +#define R_SERIAL1_STATUS__par_err__no 0 +#define R_SERIAL1_STATUS__par_err__yes 1 +#define R_SERIAL1_STATUS__framing_err__BITNR 1 +#define R_SERIAL1_STATUS__framing_err__WIDTH 1 +#define R_SERIAL1_STATUS__framing_err__no 0 +#define R_SERIAL1_STATUS__framing_err__yes 1 +#define R_SERIAL1_STATUS__data_avail__BITNR 0 +#define R_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SERIAL1_STATUS__data_avail__no 0 +#define R_SERIAL1_STATUS__data_avail__yes 1 + +#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068) +#define R_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SERIAL1_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SERIAL1_XOFF__tx_stop__BITNR 9 +#define R_SERIAL1_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL1_XOFF__tx_stop__enable 0 +#define R_SERIAL1_XOFF__tx_stop__stop 1 +#define R_SERIAL1_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL1_XOFF__auto_xoff__disable 0 +#define R_SERIAL1_XOFF__auto_xoff__enable 1 +#define R_SERIAL1_XOFF__xoff_char__BITNR 0 +#define R_SERIAL1_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070) +#define R_SERIAL2_CTRL__tr_baud__BITNR 28 +#define R_SERIAL2_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL2_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL2_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__tr_baud__reserved 15 +#define R_SERIAL2_CTRL__rec_baud__BITNR 24 +#define R_SERIAL2_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL2_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL2_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL2_CTRL__rec_baud__reserved 15 +#define R_SERIAL2_CTRL__dma_err__BITNR 23 +#define R_SERIAL2_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_CTRL__dma_err__stop 0 +#define R_SERIAL2_CTRL__dma_err__ignore 1 +#define R_SERIAL2_CTRL__rec_enable__BITNR 22 +#define R_SERIAL2_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_CTRL__rec_enable__disable 0 +#define R_SERIAL2_CTRL__rec_enable__enable 1 +#define R_SERIAL2_CTRL__rts___BITNR 21 +#define R_SERIAL2_CTRL__rts___WIDTH 1 +#define R_SERIAL2_CTRL__rts___active 0 +#define R_SERIAL2_CTRL__rts___inactive 1 +#define R_SERIAL2_CTRL__sampling__BITNR 20 +#define R_SERIAL2_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_CTRL__sampling__middle 0 +#define R_SERIAL2_CTRL__sampling__majority 1 +#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_CTRL__rec_par__BITNR 18 +#define R_SERIAL2_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par__even 0 +#define R_SERIAL2_CTRL__rec_par__odd 1 +#define R_SERIAL2_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL2_CTRL__txd__BITNR 15 +#define R_SERIAL2_CTRL__txd__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__BITNR 14 +#define R_SERIAL2_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_CTRL__tr_enable__disable 0 +#define R_SERIAL2_CTRL__tr_enable__enable 1 +#define R_SERIAL2_CTRL__auto_cts__BITNR 13 +#define R_SERIAL2_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_CTRL__auto_cts__active 1 +#define R_SERIAL2_CTRL__stop_bits__BITNR 12 +#define R_SERIAL2_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_CTRL__tr_par__BITNR 10 +#define R_SERIAL2_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par__even 0 +#define R_SERIAL2_CTRL__tr_par__odd 1 +#define R_SERIAL2_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL2_CTRL__data_out__BITNR 0 +#define R_SERIAL2_CTRL__data_out__WIDTH 8 + +#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073) +#define R_SERIAL2_BAUD__tr_baud__BITNR 4 +#define R_SERIAL2_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL2_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL2_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__tr_baud__reserved 15 +#define R_SERIAL2_BAUD__rec_baud__BITNR 0 +#define R_SERIAL2_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL2_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL2_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL2_BAUD__rec_baud__reserved 15 + +#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072) +#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL2_REC_CTRL__dma_err__stop 0 +#define R_SERIAL2_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL2_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL2_REC_CTRL__rts___BITNR 5 +#define R_SERIAL2_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL2_REC_CTRL__rts___active 0 +#define R_SERIAL2_REC_CTRL__rts___inactive 1 +#define R_SERIAL2_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL2_REC_CTRL__sampling__middle 0 +#define R_SERIAL2_REC_CTRL__sampling__majority 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par__even 0 +#define R_SERIAL2_REC_CTRL__rec_par__odd 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071) +#define R_SERIAL2_TR_CTRL__txd__BITNR 7 +#define R_SERIAL2_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL2_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL2_TR_CTRL__auto_cts__active 1 +#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par__even 0 +#define R_SERIAL2_TR_CTRL__tr_par__odd 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070) +#define R_SERIAL2_TR_DATA__data_out__BITNR 0 +#define R_SERIAL2_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070) +#define R_SERIAL2_READ__xoff_detect__BITNR 15 +#define R_SERIAL2_READ__xoff_detect__WIDTH 1 +#define R_SERIAL2_READ__xoff_detect__no_xoff 0 +#define R_SERIAL2_READ__xoff_detect__xoff 1 +#define R_SERIAL2_READ__cts___BITNR 14 +#define R_SERIAL2_READ__cts___WIDTH 1 +#define R_SERIAL2_READ__cts___active 0 +#define R_SERIAL2_READ__cts___inactive 1 +#define R_SERIAL2_READ__tr_ready__BITNR 13 +#define R_SERIAL2_READ__tr_ready__WIDTH 1 +#define R_SERIAL2_READ__tr_ready__full 0 +#define R_SERIAL2_READ__tr_ready__ready 1 +#define R_SERIAL2_READ__rxd__BITNR 12 +#define R_SERIAL2_READ__rxd__WIDTH 1 +#define R_SERIAL2_READ__overrun__BITNR 11 +#define R_SERIAL2_READ__overrun__WIDTH 1 +#define R_SERIAL2_READ__overrun__no 0 +#define R_SERIAL2_READ__overrun__yes 1 +#define R_SERIAL2_READ__par_err__BITNR 10 +#define R_SERIAL2_READ__par_err__WIDTH 1 +#define R_SERIAL2_READ__par_err__no 0 +#define R_SERIAL2_READ__par_err__yes 1 +#define R_SERIAL2_READ__framing_err__BITNR 9 +#define R_SERIAL2_READ__framing_err__WIDTH 1 +#define R_SERIAL2_READ__framing_err__no 0 +#define R_SERIAL2_READ__framing_err__yes 1 +#define R_SERIAL2_READ__data_avail__BITNR 8 +#define R_SERIAL2_READ__data_avail__WIDTH 1 +#define R_SERIAL2_READ__data_avail__no 0 +#define R_SERIAL2_READ__data_avail__yes 1 +#define R_SERIAL2_READ__data_in__BITNR 0 +#define R_SERIAL2_READ__data_in__WIDTH 8 + +#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071) +#define R_SERIAL2_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL2_STATUS__xoff_detect__xoff 1 +#define R_SERIAL2_STATUS__cts___BITNR 6 +#define R_SERIAL2_STATUS__cts___WIDTH 1 +#define R_SERIAL2_STATUS__cts___active 0 +#define R_SERIAL2_STATUS__cts___inactive 1 +#define R_SERIAL2_STATUS__tr_ready__BITNR 5 +#define R_SERIAL2_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL2_STATUS__tr_ready__full 0 +#define R_SERIAL2_STATUS__tr_ready__ready 1 +#define R_SERIAL2_STATUS__rxd__BITNR 4 +#define R_SERIAL2_STATUS__rxd__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__BITNR 3 +#define R_SERIAL2_STATUS__overrun__WIDTH 1 +#define R_SERIAL2_STATUS__overrun__no 0 +#define R_SERIAL2_STATUS__overrun__yes 1 +#define R_SERIAL2_STATUS__par_err__BITNR 2 +#define R_SERIAL2_STATUS__par_err__WIDTH 1 +#define R_SERIAL2_STATUS__par_err__no 0 +#define R_SERIAL2_STATUS__par_err__yes 1 +#define R_SERIAL2_STATUS__framing_err__BITNR 1 +#define R_SERIAL2_STATUS__framing_err__WIDTH 1 +#define R_SERIAL2_STATUS__framing_err__no 0 +#define R_SERIAL2_STATUS__framing_err__yes 1 +#define R_SERIAL2_STATUS__data_avail__BITNR 0 +#define R_SERIAL2_STATUS__data_avail__WIDTH 1 +#define R_SERIAL2_STATUS__data_avail__no 0 +#define R_SERIAL2_STATUS__data_avail__yes 1 + +#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070) +#define R_SERIAL2_REC_DATA__data_in__BITNR 0 +#define R_SERIAL2_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074) +#define R_SERIAL2_XOFF__tx_stop__BITNR 9 +#define R_SERIAL2_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL2_XOFF__tx_stop__enable 0 +#define R_SERIAL2_XOFF__tx_stop__stop 1 +#define R_SERIAL2_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL2_XOFF__auto_xoff__disable 0 +#define R_SERIAL2_XOFF__auto_xoff__enable 1 +#define R_SERIAL2_XOFF__xoff_char__BITNR 0 +#define R_SERIAL2_XOFF__xoff_char__WIDTH 8 + +#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SERIAL3_CTRL__tr_baud__c300Hz 0 +#define R_SERIAL3_CTRL__tr_baud__c600Hz 1 +#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SERIAL3_CTRL__rec_baud__BITNR 24 +#define R_SERIAL3_CTRL__rec_baud__WIDTH 4 +#define R_SERIAL3_CTRL__rec_baud__c300Hz 0 +#define R_SERIAL3_CTRL__rec_baud__c600Hz 1 +#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2 +#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3 +#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4 +#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5 +#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6 +#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7 +#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8 +#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9 +#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10 +#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11 +#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12 +#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14 +#define R_SERIAL3_CTRL__rec_baud__reserved 15 +#define R_SERIAL3_CTRL__dma_err__BITNR 23 +#define R_SERIAL3_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_CTRL__dma_err__stop 0 +#define R_SERIAL3_CTRL__dma_err__ignore 1 +#define R_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SERIAL3_CTRL__rts___BITNR 21 +#define R_SERIAL3_CTRL__rts___WIDTH 1 +#define R_SERIAL3_CTRL__rts___active 0 +#define R_SERIAL3_CTRL__rts___inactive 1 +#define R_SERIAL3_CTRL__sampling__BITNR 20 +#define R_SERIAL3_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_CTRL__sampling__middle 0 +#define R_SERIAL3_CTRL__sampling__majority 1 +#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19 +#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_CTRL__rec_par__BITNR 18 +#define R_SERIAL3_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par__even 0 +#define R_SERIAL3_CTRL__rec_par__odd 1 +#define R_SERIAL3_CTRL__rec_par_en__BITNR 17 +#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16 +#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1 +#define R_SERIAL3_CTRL__txd__BITNR 15 +#define R_SERIAL3_CTRL__txd__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SERIAL3_CTRL__auto_cts__BITNR 13 +#define R_SERIAL3_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_CTRL__auto_cts__active 1 +#define R_SERIAL3_CTRL__stop_bits__BITNR 12 +#define R_SERIAL3_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11 +#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_CTRL__tr_par__BITNR 10 +#define R_SERIAL3_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par__even 0 +#define R_SERIAL3_CTRL__tr_par__odd 1 +#define R_SERIAL3_CTRL__tr_par_en__BITNR 9 +#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8 +#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1 +#define R_SERIAL3_CTRL__data_out__BITNR 0 +#define R_SERIAL3_CTRL__data_out__WIDTH 8 + +#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b) +#define R_SERIAL3_BAUD__tr_baud__BITNR 4 +#define R_SERIAL3_BAUD__tr_baud__WIDTH 4 +#define R_SERIAL3_BAUD__tr_baud__c300Hz 0 +#define R_SERIAL3_BAUD__tr_baud__c600Hz 1 +#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__tr_baud__reserved 15 +#define R_SERIAL3_BAUD__rec_baud__BITNR 0 +#define R_SERIAL3_BAUD__rec_baud__WIDTH 4 +#define R_SERIAL3_BAUD__rec_baud__c300Hz 0 +#define R_SERIAL3_BAUD__rec_baud__c600Hz 1 +#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2 +#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3 +#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4 +#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5 +#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6 +#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7 +#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8 +#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9 +#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10 +#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11 +#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12 +#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13 +#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14 +#define R_SERIAL3_BAUD__rec_baud__reserved 15 + +#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a) +#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7 +#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1 +#define R_SERIAL3_REC_CTRL__dma_err__stop 0 +#define R_SERIAL3_REC_CTRL__dma_err__ignore 1 +#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6 +#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_enable__disable 0 +#define R_SERIAL3_REC_CTRL__rec_enable__enable 1 +#define R_SERIAL3_REC_CTRL__rts___BITNR 5 +#define R_SERIAL3_REC_CTRL__rts___WIDTH 1 +#define R_SERIAL3_REC_CTRL__rts___active 0 +#define R_SERIAL3_REC_CTRL__rts___inactive 1 +#define R_SERIAL3_REC_CTRL__sampling__BITNR 4 +#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1 +#define R_SERIAL3_REC_CTRL__sampling__middle 0 +#define R_SERIAL3_REC_CTRL__sampling__majority 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3 +#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0 +#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1 +#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2 +#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par__even 0 +#define R_SERIAL3_REC_CTRL__rec_par__odd 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0 +#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0 +#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1 + +#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079) +#define R_SERIAL3_TR_CTRL__txd__BITNR 7 +#define R_SERIAL3_TR_CTRL__txd__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6 +#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_enable__disable 0 +#define R_SERIAL3_TR_CTRL__tr_enable__enable 1 +#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5 +#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1 +#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0 +#define R_SERIAL3_TR_CTRL__auto_cts__active 1 +#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4 +#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1 +#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0 +#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3 +#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0 +#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1 +#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2 +#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par__even 0 +#define R_SERIAL3_TR_CTRL__tr_par__odd 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0 +#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0 +#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1 + +#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078) +#define R_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SERIAL3_TR_DATA__data_out__WIDTH 8 + +#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SERIAL3_READ__xoff_detect__BITNR 15 +#define R_SERIAL3_READ__xoff_detect__WIDTH 1 +#define R_SERIAL3_READ__xoff_detect__no_xoff 0 +#define R_SERIAL3_READ__xoff_detect__xoff 1 +#define R_SERIAL3_READ__cts___BITNR 14 +#define R_SERIAL3_READ__cts___WIDTH 1 +#define R_SERIAL3_READ__cts___active 0 +#define R_SERIAL3_READ__cts___inactive 1 +#define R_SERIAL3_READ__tr_ready__BITNR 13 +#define R_SERIAL3_READ__tr_ready__WIDTH 1 +#define R_SERIAL3_READ__tr_ready__full 0 +#define R_SERIAL3_READ__tr_ready__ready 1 +#define R_SERIAL3_READ__rxd__BITNR 12 +#define R_SERIAL3_READ__rxd__WIDTH 1 +#define R_SERIAL3_READ__overrun__BITNR 11 +#define R_SERIAL3_READ__overrun__WIDTH 1 +#define R_SERIAL3_READ__overrun__no 0 +#define R_SERIAL3_READ__overrun__yes 1 +#define R_SERIAL3_READ__par_err__BITNR 10 +#define R_SERIAL3_READ__par_err__WIDTH 1 +#define R_SERIAL3_READ__par_err__no 0 +#define R_SERIAL3_READ__par_err__yes 1 +#define R_SERIAL3_READ__framing_err__BITNR 9 +#define R_SERIAL3_READ__framing_err__WIDTH 1 +#define R_SERIAL3_READ__framing_err__no 0 +#define R_SERIAL3_READ__framing_err__yes 1 +#define R_SERIAL3_READ__data_avail__BITNR 8 +#define R_SERIAL3_READ__data_avail__WIDTH 1 +#define R_SERIAL3_READ__data_avail__no 0 +#define R_SERIAL3_READ__data_avail__yes 1 +#define R_SERIAL3_READ__data_in__BITNR 0 +#define R_SERIAL3_READ__data_in__WIDTH 8 + +#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079) +#define R_SERIAL3_STATUS__xoff_detect__BITNR 7 +#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1 +#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0 +#define R_SERIAL3_STATUS__xoff_detect__xoff 1 +#define R_SERIAL3_STATUS__cts___BITNR 6 +#define R_SERIAL3_STATUS__cts___WIDTH 1 +#define R_SERIAL3_STATUS__cts___active 0 +#define R_SERIAL3_STATUS__cts___inactive 1 +#define R_SERIAL3_STATUS__tr_ready__BITNR 5 +#define R_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SERIAL3_STATUS__tr_ready__full 0 +#define R_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SERIAL3_STATUS__rxd__BITNR 4 +#define R_SERIAL3_STATUS__rxd__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__BITNR 3 +#define R_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SERIAL3_STATUS__overrun__no 0 +#define R_SERIAL3_STATUS__overrun__yes 1 +#define R_SERIAL3_STATUS__par_err__BITNR 2 +#define R_SERIAL3_STATUS__par_err__WIDTH 1 +#define R_SERIAL3_STATUS__par_err__no 0 +#define R_SERIAL3_STATUS__par_err__yes 1 +#define R_SERIAL3_STATUS__framing_err__BITNR 1 +#define R_SERIAL3_STATUS__framing_err__WIDTH 1 +#define R_SERIAL3_STATUS__framing_err__no 0 +#define R_SERIAL3_STATUS__framing_err__yes 1 +#define R_SERIAL3_STATUS__data_avail__BITNR 0 +#define R_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SERIAL3_STATUS__data_avail__no 0 +#define R_SERIAL3_STATUS__data_avail__yes 1 + +#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078) +#define R_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SERIAL3_REC_DATA__data_in__WIDTH 8 + +#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SERIAL3_XOFF__tx_stop__BITNR 9 +#define R_SERIAL3_XOFF__tx_stop__WIDTH 1 +#define R_SERIAL3_XOFF__tx_stop__enable 0 +#define R_SERIAL3_XOFF__tx_stop__stop 1 +#define R_SERIAL3_XOFF__auto_xoff__BITNR 8 +#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1 +#define R_SERIAL3_XOFF__auto_xoff__disable 0 +#define R_SERIAL3_XOFF__auto_xoff__enable 1 +#define R_SERIAL3_XOFF__xoff_char__BITNR 0 +#define R_SERIAL3_XOFF__xoff_char__WIDTH 8 + +#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c) +#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28 +#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24 +#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20 +#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16 +#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12 +#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8 +#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4 +#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3 +#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0 +#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1 +#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2 +#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3 + +/* +!* Network interface registers +!*/ + +#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080) +#define R_NETWORK_SA_0__ma0_low__BITNR 0 +#define R_NETWORK_SA_0__ma0_low__WIDTH 32 + +#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084) +#define R_NETWORK_SA_1__ma1_low__BITNR 16 +#define R_NETWORK_SA_1__ma1_low__WIDTH 16 +#define R_NETWORK_SA_1__ma0_high__BITNR 0 +#define R_NETWORK_SA_1__ma0_high__WIDTH 16 + +#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088) +#define R_NETWORK_SA_2__ma1_high__BITNR 0 +#define R_NETWORK_SA_2__ma1_high__WIDTH 32 + +#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c) +#define R_NETWORK_GA_0__ga_low__BITNR 0 +#define R_NETWORK_GA_0__ga_low__WIDTH 32 + +#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090) +#define R_NETWORK_GA_1__ga_high__BITNR 0 +#define R_NETWORK_GA_1__ga_high__WIDTH 32 + +#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094) +#define R_NETWORK_REC_CONFIG__max_size__BITNR 10 +#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1 +#define R_NETWORK_REC_CONFIG__max_size__size1518 0 +#define R_NETWORK_REC_CONFIG__max_size__size1522 1 +#define R_NETWORK_REC_CONFIG__duplex__BITNR 9 +#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1 +#define R_NETWORK_REC_CONFIG__duplex__full 1 +#define R_NETWORK_REC_CONFIG__duplex__half 0 +#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8 +#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1 +#define R_NETWORK_REC_CONFIG__bad_crc__receive 1 +#define R_NETWORK_REC_CONFIG__bad_crc__discard 0 +#define R_NETWORK_REC_CONFIG__oversize__BITNR 7 +#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__oversize__receive 1 +#define R_NETWORK_REC_CONFIG__oversize__discard 0 +#define R_NETWORK_REC_CONFIG__undersize__BITNR 6 +#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1 +#define R_NETWORK_REC_CONFIG__undersize__receive 1 +#define R_NETWORK_REC_CONFIG__undersize__discard 0 +#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5 +#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1 +#define R_NETWORK_REC_CONFIG__all_roots__receive 1 +#define R_NETWORK_REC_CONFIG__all_roots__discard 0 +#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4 +#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3 +#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1 +#define R_NETWORK_REC_CONFIG__broadcast__receive 1 +#define R_NETWORK_REC_CONFIG__broadcast__discard 0 +#define R_NETWORK_REC_CONFIG__individual__BITNR 2 +#define R_NETWORK_REC_CONFIG__individual__WIDTH 1 +#define R_NETWORK_REC_CONFIG__individual__receive 1 +#define R_NETWORK_REC_CONFIG__individual__discard 0 +#define R_NETWORK_REC_CONFIG__ma1__BITNR 1 +#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma1__enable 1 +#define R_NETWORK_REC_CONFIG__ma1__disable 0 +#define R_NETWORK_REC_CONFIG__ma0__BITNR 0 +#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1 +#define R_NETWORK_REC_CONFIG__ma0__enable 1 +#define R_NETWORK_REC_CONFIG__ma0__disable 0 + +#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098) +#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5 +#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__loopback__on 1 +#define R_NETWORK_GEN_CONFIG__loopback__off 0 +#define R_NETWORK_GEN_CONFIG__frame__BITNR 4 +#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__frame__tokenr 1 +#define R_NETWORK_GEN_CONFIG__frame__ether 0 +#define R_NETWORK_GEN_CONFIG__vg__BITNR 3 +#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__vg__on 1 +#define R_NETWORK_GEN_CONFIG__vg__off 0 +#define R_NETWORK_GEN_CONFIG__phy__BITNR 1 +#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2 +#define R_NETWORK_GEN_CONFIG__phy__sni 0 +#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1 +#define R_NETWORK_GEN_CONFIG__phy__mii_err 2 +#define R_NETWORK_GEN_CONFIG__phy__mii_req 3 +#define R_NETWORK_GEN_CONFIG__enable__BITNR 0 +#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1 +#define R_NETWORK_GEN_CONFIG__enable__on 1 +#define R_NETWORK_GEN_CONFIG__enable__off 0 + +#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c) +#define R_NETWORK_TR_CTRL__clr_error__BITNR 8 +#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1 +#define R_NETWORK_TR_CTRL__clr_error__clr 1 +#define R_NETWORK_TR_CTRL__clr_error__nop 0 +#define R_NETWORK_TR_CTRL__delay__BITNR 5 +#define R_NETWORK_TR_CTRL__delay__WIDTH 1 +#define R_NETWORK_TR_CTRL__delay__d2us 1 +#define R_NETWORK_TR_CTRL__delay__none 0 +#define R_NETWORK_TR_CTRL__cancel__BITNR 4 +#define R_NETWORK_TR_CTRL__cancel__WIDTH 1 +#define R_NETWORK_TR_CTRL__cancel__do 1 +#define R_NETWORK_TR_CTRL__cancel__dont 0 +#define R_NETWORK_TR_CTRL__cd__BITNR 3 +#define R_NETWORK_TR_CTRL__cd__WIDTH 1 +#define R_NETWORK_TR_CTRL__cd__enable 0 +#define R_NETWORK_TR_CTRL__cd__disable 1 +#define R_NETWORK_TR_CTRL__cd__ack_col 0 +#define R_NETWORK_TR_CTRL__cd__ack_crs 1 +#define R_NETWORK_TR_CTRL__retry__BITNR 2 +#define R_NETWORK_TR_CTRL__retry__WIDTH 1 +#define R_NETWORK_TR_CTRL__retry__enable 0 +#define R_NETWORK_TR_CTRL__retry__disable 1 +#define R_NETWORK_TR_CTRL__pad__BITNR 1 +#define R_NETWORK_TR_CTRL__pad__WIDTH 1 +#define R_NETWORK_TR_CTRL__pad__enable 1 +#define R_NETWORK_TR_CTRL__pad__disable 0 +#define R_NETWORK_TR_CTRL__crc__BITNR 0 +#define R_NETWORK_TR_CTRL__crc__WIDTH 1 +#define R_NETWORK_TR_CTRL__crc__enable 0 +#define R_NETWORK_TR_CTRL__crc__disable 1 + +#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0) +#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4 +#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4 +#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3 +#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdck__BITNR 2 +#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1 +#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1 +#define R_NETWORK_MGM_CTRL__mdoe__enable 1 +#define R_NETWORK_MGM_CTRL__mdoe__disable 0 +#define R_NETWORK_MGM_CTRL__mdio__BITNR 0 +#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1 + +#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0) +#define R_NETWORK_STAT__rxd_pins__BITNR 4 +#define R_NETWORK_STAT__rxd_pins__WIDTH 4 +#define R_NETWORK_STAT__rxer__BITNR 3 +#define R_NETWORK_STAT__rxer__WIDTH 1 +#define R_NETWORK_STAT__underrun__BITNR 2 +#define R_NETWORK_STAT__underrun__WIDTH 1 +#define R_NETWORK_STAT__underrun__yes 1 +#define R_NETWORK_STAT__underrun__no 0 +#define R_NETWORK_STAT__exc_col__BITNR 1 +#define R_NETWORK_STAT__exc_col__WIDTH 1 +#define R_NETWORK_STAT__exc_col__yes 1 +#define R_NETWORK_STAT__exc_col__no 0 +#define R_NETWORK_STAT__mdio__BITNR 0 +#define R_NETWORK_STAT__mdio__WIDTH 1 + +#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4) +#define R_REC_COUNTERS__congestion__BITNR 24 +#define R_REC_COUNTERS__congestion__WIDTH 8 +#define R_REC_COUNTERS__oversize__BITNR 16 +#define R_REC_COUNTERS__oversize__WIDTH 8 +#define R_REC_COUNTERS__alignment_error__BITNR 8 +#define R_REC_COUNTERS__alignment_error__WIDTH 8 +#define R_REC_COUNTERS__crc_error__BITNR 0 +#define R_REC_COUNTERS__crc_error__WIDTH 8 + +#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8) +#define R_TR_COUNTERS__deferred__BITNR 24 +#define R_TR_COUNTERS__deferred__WIDTH 8 +#define R_TR_COUNTERS__late_col__BITNR 16 +#define R_TR_COUNTERS__late_col__WIDTH 8 +#define R_TR_COUNTERS__multiple_col__BITNR 8 +#define R_TR_COUNTERS__multiple_col__WIDTH 8 +#define R_TR_COUNTERS__single_col__BITNR 0 +#define R_TR_COUNTERS__single_col__WIDTH 8 + +#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac) +#define R_PHY_COUNTERS__sqe_test_error__BITNR 8 +#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8 +#define R_PHY_COUNTERS__carrier_loss__BITNR 0 +#define R_PHY_COUNTERS__carrier_loss__WIDTH 8 + +/* +!* Parallel printer port registers +!*/ + +#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_PAR0_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR0_CTRL_DATA__peri_int__ack 1 +#define R_PAR0_CTRL_DATA__peri_int__nop 0 +#define R_PAR0_CTRL_DATA__oe__BITNR 20 +#define R_PAR0_CTRL_DATA__oe__WIDTH 1 +#define R_PAR0_CTRL_DATA__oe__enable 1 +#define R_PAR0_CTRL_DATA__oe__disable 0 +#define R_PAR0_CTRL_DATA__seli__BITNR 19 +#define R_PAR0_CTRL_DATA__seli__WIDTH 1 +#define R_PAR0_CTRL_DATA__seli__active 1 +#define R_PAR0_CTRL_DATA__seli__inactive 0 +#define R_PAR0_CTRL_DATA__autofd__BITNR 18 +#define R_PAR0_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR0_CTRL_DATA__autofd__active 1 +#define R_PAR0_CTRL_DATA__autofd__inactive 0 +#define R_PAR0_CTRL_DATA__strb__BITNR 17 +#define R_PAR0_CTRL_DATA__strb__WIDTH 1 +#define R_PAR0_CTRL_DATA__strb__active 1 +#define R_PAR0_CTRL_DATA__strb__inactive 0 +#define R_PAR0_CTRL_DATA__init__BITNR 16 +#define R_PAR0_CTRL_DATA__init__WIDTH 1 +#define R_PAR0_CTRL_DATA__init__active 1 +#define R_PAR0_CTRL_DATA__init__inactive 0 +#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR0_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR0_CTRL_DATA__data__BITNR 0 +#define R_PAR0_CTRL_DATA__data__WIDTH 8 + +#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042) +#define R_PAR0_CTRL__ctrl__BITNR 0 +#define R_PAR0_CTRL__ctrl__WIDTH 5 + +#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_PAR0_STATUS_DATA__mode__BITNR 29 +#define R_PAR0_STATUS_DATA__mode__WIDTH 3 +#define R_PAR0_STATUS_DATA__mode__manual 0 +#define R_PAR0_STATUS_DATA__mode__centronics 1 +#define R_PAR0_STATUS_DATA__mode__fastbyte 2 +#define R_PAR0_STATUS_DATA__mode__nibble 3 +#define R_PAR0_STATUS_DATA__mode__byte 4 +#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR0_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR0_STATUS_DATA__mode__off 7 +#define R_PAR0_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR0_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR0_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR0_STATUS_DATA__mode__epp_rd 0 +#define R_PAR0_STATUS_DATA__perr__BITNR 28 +#define R_PAR0_STATUS_DATA__perr__WIDTH 1 +#define R_PAR0_STATUS_DATA__perr__active 1 +#define R_PAR0_STATUS_DATA__perr__inactive 0 +#define R_PAR0_STATUS_DATA__ack__BITNR 27 +#define R_PAR0_STATUS_DATA__ack__WIDTH 1 +#define R_PAR0_STATUS_DATA__ack__active 0 +#define R_PAR0_STATUS_DATA__ack__inactive 1 +#define R_PAR0_STATUS_DATA__busy__BITNR 26 +#define R_PAR0_STATUS_DATA__busy__WIDTH 1 +#define R_PAR0_STATUS_DATA__busy__active 1 +#define R_PAR0_STATUS_DATA__busy__inactive 0 +#define R_PAR0_STATUS_DATA__fault__BITNR 25 +#define R_PAR0_STATUS_DATA__fault__WIDTH 1 +#define R_PAR0_STATUS_DATA__fault__active 0 +#define R_PAR0_STATUS_DATA__fault__inactive 1 +#define R_PAR0_STATUS_DATA__sel__BITNR 24 +#define R_PAR0_STATUS_DATA__sel__WIDTH 1 +#define R_PAR0_STATUS_DATA__sel__active 1 +#define R_PAR0_STATUS_DATA__sel__inactive 0 +#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR0_STATUS_DATA__ext_mode__enable 1 +#define R_PAR0_STATUS_DATA__ext_mode__disable 0 +#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22 +#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_16__active 1 +#define R_PAR0_STATUS_DATA__ecp_16__inactive 0 +#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR0_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR0_STATUS_DATA__dav__BITNR 16 +#define R_PAR0_STATUS_DATA__dav__WIDTH 1 +#define R_PAR0_STATUS_DATA__dav__data 1 +#define R_PAR0_STATUS_DATA__dav__nodata 0 +#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR0_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR0_STATUS_DATA__data__BITNR 0 +#define R_PAR0_STATUS_DATA__data__WIDTH 8 + +#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042) +#define R_PAR0_STATUS__mode__BITNR 13 +#define R_PAR0_STATUS__mode__WIDTH 3 +#define R_PAR0_STATUS__mode__manual 0 +#define R_PAR0_STATUS__mode__centronics 1 +#define R_PAR0_STATUS__mode__fastbyte 2 +#define R_PAR0_STATUS__mode__nibble 3 +#define R_PAR0_STATUS__mode__byte 4 +#define R_PAR0_STATUS__mode__ecp_fwd 5 +#define R_PAR0_STATUS__mode__ecp_rev 6 +#define R_PAR0_STATUS__mode__off 7 +#define R_PAR0_STATUS__mode__epp_wr1 5 +#define R_PAR0_STATUS__mode__epp_wr2 6 +#define R_PAR0_STATUS__mode__epp_wr3 7 +#define R_PAR0_STATUS__mode__epp_rd 0 +#define R_PAR0_STATUS__perr__BITNR 12 +#define R_PAR0_STATUS__perr__WIDTH 1 +#define R_PAR0_STATUS__perr__active 1 +#define R_PAR0_STATUS__perr__inactive 0 +#define R_PAR0_STATUS__ack__BITNR 11 +#define R_PAR0_STATUS__ack__WIDTH 1 +#define R_PAR0_STATUS__ack__active 0 +#define R_PAR0_STATUS__ack__inactive 1 +#define R_PAR0_STATUS__busy__BITNR 10 +#define R_PAR0_STATUS__busy__WIDTH 1 +#define R_PAR0_STATUS__busy__active 1 +#define R_PAR0_STATUS__busy__inactive 0 +#define R_PAR0_STATUS__fault__BITNR 9 +#define R_PAR0_STATUS__fault__WIDTH 1 +#define R_PAR0_STATUS__fault__active 0 +#define R_PAR0_STATUS__fault__inactive 1 +#define R_PAR0_STATUS__sel__BITNR 8 +#define R_PAR0_STATUS__sel__WIDTH 1 +#define R_PAR0_STATUS__sel__active 1 +#define R_PAR0_STATUS__sel__inactive 0 +#define R_PAR0_STATUS__ext_mode__BITNR 7 +#define R_PAR0_STATUS__ext_mode__WIDTH 1 +#define R_PAR0_STATUS__ext_mode__enable 1 +#define R_PAR0_STATUS__ext_mode__disable 0 +#define R_PAR0_STATUS__ecp_16__BITNR 6 +#define R_PAR0_STATUS__ecp_16__WIDTH 1 +#define R_PAR0_STATUS__ecp_16__active 1 +#define R_PAR0_STATUS__ecp_16__inactive 0 +#define R_PAR0_STATUS__tr_rdy__BITNR 1 +#define R_PAR0_STATUS__tr_rdy__WIDTH 1 +#define R_PAR0_STATUS__tr_rdy__ready 1 +#define R_PAR0_STATUS__tr_rdy__busy 0 +#define R_PAR0_STATUS__dav__BITNR 0 +#define R_PAR0_STATUS__dav__WIDTH 1 +#define R_PAR0_STATUS__dav__data 1 +#define R_PAR0_STATUS__dav__nodata 0 + +#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_PAR_ECP16_DATA__data__BITNR 0 +#define R_PAR_ECP16_DATA__data__WIDTH 16 + +#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_PAR0_CONFIG__ioe__BITNR 25 +#define R_PAR0_CONFIG__ioe__WIDTH 1 +#define R_PAR0_CONFIG__ioe__inv 1 +#define R_PAR0_CONFIG__ioe__noninv 0 +#define R_PAR0_CONFIG__iseli__BITNR 24 +#define R_PAR0_CONFIG__iseli__WIDTH 1 +#define R_PAR0_CONFIG__iseli__inv 1 +#define R_PAR0_CONFIG__iseli__noninv 0 +#define R_PAR0_CONFIG__iautofd__BITNR 23 +#define R_PAR0_CONFIG__iautofd__WIDTH 1 +#define R_PAR0_CONFIG__iautofd__inv 1 +#define R_PAR0_CONFIG__iautofd__noninv 0 +#define R_PAR0_CONFIG__istrb__BITNR 22 +#define R_PAR0_CONFIG__istrb__WIDTH 1 +#define R_PAR0_CONFIG__istrb__inv 1 +#define R_PAR0_CONFIG__istrb__noninv 0 +#define R_PAR0_CONFIG__iinit__BITNR 21 +#define R_PAR0_CONFIG__iinit__WIDTH 1 +#define R_PAR0_CONFIG__iinit__inv 1 +#define R_PAR0_CONFIG__iinit__noninv 0 +#define R_PAR0_CONFIG__iperr__BITNR 20 +#define R_PAR0_CONFIG__iperr__WIDTH 1 +#define R_PAR0_CONFIG__iperr__inv 1 +#define R_PAR0_CONFIG__iperr__noninv 0 +#define R_PAR0_CONFIG__iack__BITNR 19 +#define R_PAR0_CONFIG__iack__WIDTH 1 +#define R_PAR0_CONFIG__iack__inv 1 +#define R_PAR0_CONFIG__iack__noninv 0 +#define R_PAR0_CONFIG__ibusy__BITNR 18 +#define R_PAR0_CONFIG__ibusy__WIDTH 1 +#define R_PAR0_CONFIG__ibusy__inv 1 +#define R_PAR0_CONFIG__ibusy__noninv 0 +#define R_PAR0_CONFIG__ifault__BITNR 17 +#define R_PAR0_CONFIG__ifault__WIDTH 1 +#define R_PAR0_CONFIG__ifault__inv 1 +#define R_PAR0_CONFIG__ifault__noninv 0 +#define R_PAR0_CONFIG__isel__BITNR 16 +#define R_PAR0_CONFIG__isel__WIDTH 1 +#define R_PAR0_CONFIG__isel__inv 1 +#define R_PAR0_CONFIG__isel__noninv 0 +#define R_PAR0_CONFIG__ext_mode__BITNR 11 +#define R_PAR0_CONFIG__ext_mode__WIDTH 1 +#define R_PAR0_CONFIG__ext_mode__enable 1 +#define R_PAR0_CONFIG__ext_mode__disable 0 +#define R_PAR0_CONFIG__wide__BITNR 10 +#define R_PAR0_CONFIG__wide__WIDTH 1 +#define R_PAR0_CONFIG__wide__enable 1 +#define R_PAR0_CONFIG__wide__disable 0 +#define R_PAR0_CONFIG__dma__BITNR 9 +#define R_PAR0_CONFIG__dma__WIDTH 1 +#define R_PAR0_CONFIG__dma__enable 1 +#define R_PAR0_CONFIG__dma__disable 0 +#define R_PAR0_CONFIG__rle_in__BITNR 8 +#define R_PAR0_CONFIG__rle_in__WIDTH 1 +#define R_PAR0_CONFIG__rle_in__enable 1 +#define R_PAR0_CONFIG__rle_in__disable 0 +#define R_PAR0_CONFIG__rle_out__BITNR 7 +#define R_PAR0_CONFIG__rle_out__WIDTH 1 +#define R_PAR0_CONFIG__rle_out__enable 1 +#define R_PAR0_CONFIG__rle_out__disable 0 +#define R_PAR0_CONFIG__enable__BITNR 6 +#define R_PAR0_CONFIG__enable__WIDTH 1 +#define R_PAR0_CONFIG__enable__on 1 +#define R_PAR0_CONFIG__enable__reset 0 +#define R_PAR0_CONFIG__force__BITNR 5 +#define R_PAR0_CONFIG__force__WIDTH 1 +#define R_PAR0_CONFIG__force__on 1 +#define R_PAR0_CONFIG__force__off 0 +#define R_PAR0_CONFIG__ign_ack__BITNR 4 +#define R_PAR0_CONFIG__ign_ack__WIDTH 1 +#define R_PAR0_CONFIG__ign_ack__ignore 1 +#define R_PAR0_CONFIG__ign_ack__wait 0 +#define R_PAR0_CONFIG__oe_ack__BITNR 3 +#define R_PAR0_CONFIG__oe_ack__WIDTH 1 +#define R_PAR0_CONFIG__oe_ack__wait_oe 1 +#define R_PAR0_CONFIG__oe_ack__dont_wait 0 +#define R_PAR0_CONFIG__oe_ack__epp_addr 1 +#define R_PAR0_CONFIG__oe_ack__epp_data 0 +#define R_PAR0_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR0_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR0_CONFIG__mode__BITNR 0 +#define R_PAR0_CONFIG__mode__WIDTH 3 +#define R_PAR0_CONFIG__mode__manual 0 +#define R_PAR0_CONFIG__mode__centronics 1 +#define R_PAR0_CONFIG__mode__fastbyte 2 +#define R_PAR0_CONFIG__mode__nibble 3 +#define R_PAR0_CONFIG__mode__byte 4 +#define R_PAR0_CONFIG__mode__ecp_fwd 5 +#define R_PAR0_CONFIG__mode__ecp_rev 6 +#define R_PAR0_CONFIG__mode__off 7 +#define R_PAR0_CONFIG__mode__epp_wr1 5 +#define R_PAR0_CONFIG__mode__epp_wr2 6 +#define R_PAR0_CONFIG__mode__epp_wr3 7 +#define R_PAR0_CONFIG__mode__epp_rd 0 + +#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048) +#define R_PAR0_DELAY__fine_hold__BITNR 21 +#define R_PAR0_DELAY__fine_hold__WIDTH 3 +#define R_PAR0_DELAY__hold__BITNR 16 +#define R_PAR0_DELAY__hold__WIDTH 5 +#define R_PAR0_DELAY__fine_strb__BITNR 13 +#define R_PAR0_DELAY__fine_strb__WIDTH 3 +#define R_PAR0_DELAY__strobe__BITNR 8 +#define R_PAR0_DELAY__strobe__WIDTH 5 +#define R_PAR0_DELAY__fine_setup__BITNR 5 +#define R_PAR0_DELAY__fine_setup__WIDTH 3 +#define R_PAR0_DELAY__setup__BITNR 0 +#define R_PAR0_DELAY__setup__WIDTH 5 + +#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_PAR1_CTRL_DATA__peri_int__BITNR 24 +#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1 +#define R_PAR1_CTRL_DATA__peri_int__ack 1 +#define R_PAR1_CTRL_DATA__peri_int__nop 0 +#define R_PAR1_CTRL_DATA__oe__BITNR 20 +#define R_PAR1_CTRL_DATA__oe__WIDTH 1 +#define R_PAR1_CTRL_DATA__oe__enable 1 +#define R_PAR1_CTRL_DATA__oe__disable 0 +#define R_PAR1_CTRL_DATA__seli__BITNR 19 +#define R_PAR1_CTRL_DATA__seli__WIDTH 1 +#define R_PAR1_CTRL_DATA__seli__active 1 +#define R_PAR1_CTRL_DATA__seli__inactive 0 +#define R_PAR1_CTRL_DATA__autofd__BITNR 18 +#define R_PAR1_CTRL_DATA__autofd__WIDTH 1 +#define R_PAR1_CTRL_DATA__autofd__active 1 +#define R_PAR1_CTRL_DATA__autofd__inactive 0 +#define R_PAR1_CTRL_DATA__strb__BITNR 17 +#define R_PAR1_CTRL_DATA__strb__WIDTH 1 +#define R_PAR1_CTRL_DATA__strb__active 1 +#define R_PAR1_CTRL_DATA__strb__inactive 0 +#define R_PAR1_CTRL_DATA__init__BITNR 16 +#define R_PAR1_CTRL_DATA__init__WIDTH 1 +#define R_PAR1_CTRL_DATA__init__active 1 +#define R_PAR1_CTRL_DATA__init__inactive 0 +#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__command 1 +#define R_PAR1_CTRL_DATA__ecp_cmd__data 0 +#define R_PAR1_CTRL_DATA__data__BITNR 0 +#define R_PAR1_CTRL_DATA__data__WIDTH 8 + +#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052) +#define R_PAR1_CTRL__ctrl__BITNR 0 +#define R_PAR1_CTRL__ctrl__WIDTH 5 + +#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050) +#define R_PAR1_STATUS_DATA__mode__BITNR 29 +#define R_PAR1_STATUS_DATA__mode__WIDTH 3 +#define R_PAR1_STATUS_DATA__mode__manual 0 +#define R_PAR1_STATUS_DATA__mode__centronics 1 +#define R_PAR1_STATUS_DATA__mode__fastbyte 2 +#define R_PAR1_STATUS_DATA__mode__nibble 3 +#define R_PAR1_STATUS_DATA__mode__byte 4 +#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5 +#define R_PAR1_STATUS_DATA__mode__ecp_rev 6 +#define R_PAR1_STATUS_DATA__mode__off 7 +#define R_PAR1_STATUS_DATA__mode__epp_wr1 5 +#define R_PAR1_STATUS_DATA__mode__epp_wr2 6 +#define R_PAR1_STATUS_DATA__mode__epp_wr3 7 +#define R_PAR1_STATUS_DATA__mode__epp_rd 0 +#define R_PAR1_STATUS_DATA__perr__BITNR 28 +#define R_PAR1_STATUS_DATA__perr__WIDTH 1 +#define R_PAR1_STATUS_DATA__perr__active 1 +#define R_PAR1_STATUS_DATA__perr__inactive 0 +#define R_PAR1_STATUS_DATA__ack__BITNR 27 +#define R_PAR1_STATUS_DATA__ack__WIDTH 1 +#define R_PAR1_STATUS_DATA__ack__active 0 +#define R_PAR1_STATUS_DATA__ack__inactive 1 +#define R_PAR1_STATUS_DATA__busy__BITNR 26 +#define R_PAR1_STATUS_DATA__busy__WIDTH 1 +#define R_PAR1_STATUS_DATA__busy__active 1 +#define R_PAR1_STATUS_DATA__busy__inactive 0 +#define R_PAR1_STATUS_DATA__fault__BITNR 25 +#define R_PAR1_STATUS_DATA__fault__WIDTH 1 +#define R_PAR1_STATUS_DATA__fault__active 0 +#define R_PAR1_STATUS_DATA__fault__inactive 1 +#define R_PAR1_STATUS_DATA__sel__BITNR 24 +#define R_PAR1_STATUS_DATA__sel__WIDTH 1 +#define R_PAR1_STATUS_DATA__sel__active 1 +#define R_PAR1_STATUS_DATA__sel__inactive 0 +#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23 +#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1 +#define R_PAR1_STATUS_DATA__ext_mode__enable 1 +#define R_PAR1_STATUS_DATA__ext_mode__disable 0 +#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17 +#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS_DATA__tr_rdy__ready 1 +#define R_PAR1_STATUS_DATA__tr_rdy__busy 0 +#define R_PAR1_STATUS_DATA__dav__BITNR 16 +#define R_PAR1_STATUS_DATA__dav__WIDTH 1 +#define R_PAR1_STATUS_DATA__dav__data 1 +#define R_PAR1_STATUS_DATA__dav__nodata 0 +#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8 +#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__command 1 +#define R_PAR1_STATUS_DATA__ecp_cmd__data 0 +#define R_PAR1_STATUS_DATA__data__BITNR 0 +#define R_PAR1_STATUS_DATA__data__WIDTH 8 + +#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052) +#define R_PAR1_STATUS__mode__BITNR 13 +#define R_PAR1_STATUS__mode__WIDTH 3 +#define R_PAR1_STATUS__mode__manual 0 +#define R_PAR1_STATUS__mode__centronics 1 +#define R_PAR1_STATUS__mode__fastbyte 2 +#define R_PAR1_STATUS__mode__nibble 3 +#define R_PAR1_STATUS__mode__byte 4 +#define R_PAR1_STATUS__mode__ecp_fwd 5 +#define R_PAR1_STATUS__mode__ecp_rev 6 +#define R_PAR1_STATUS__mode__off 7 +#define R_PAR1_STATUS__mode__epp_wr1 5 +#define R_PAR1_STATUS__mode__epp_wr2 6 +#define R_PAR1_STATUS__mode__epp_wr3 7 +#define R_PAR1_STATUS__mode__epp_rd 0 +#define R_PAR1_STATUS__perr__BITNR 12 +#define R_PAR1_STATUS__perr__WIDTH 1 +#define R_PAR1_STATUS__perr__active 1 +#define R_PAR1_STATUS__perr__inactive 0 +#define R_PAR1_STATUS__ack__BITNR 11 +#define R_PAR1_STATUS__ack__WIDTH 1 +#define R_PAR1_STATUS__ack__active 0 +#define R_PAR1_STATUS__ack__inactive 1 +#define R_PAR1_STATUS__busy__BITNR 10 +#define R_PAR1_STATUS__busy__WIDTH 1 +#define R_PAR1_STATUS__busy__active 1 +#define R_PAR1_STATUS__busy__inactive 0 +#define R_PAR1_STATUS__fault__BITNR 9 +#define R_PAR1_STATUS__fault__WIDTH 1 +#define R_PAR1_STATUS__fault__active 0 +#define R_PAR1_STATUS__fault__inactive 1 +#define R_PAR1_STATUS__sel__BITNR 8 +#define R_PAR1_STATUS__sel__WIDTH 1 +#define R_PAR1_STATUS__sel__active 1 +#define R_PAR1_STATUS__sel__inactive 0 +#define R_PAR1_STATUS__ext_mode__BITNR 7 +#define R_PAR1_STATUS__ext_mode__WIDTH 1 +#define R_PAR1_STATUS__ext_mode__enable 1 +#define R_PAR1_STATUS__ext_mode__disable 0 +#define R_PAR1_STATUS__tr_rdy__BITNR 1 +#define R_PAR1_STATUS__tr_rdy__WIDTH 1 +#define R_PAR1_STATUS__tr_rdy__ready 1 +#define R_PAR1_STATUS__tr_rdy__busy 0 +#define R_PAR1_STATUS__dav__BITNR 0 +#define R_PAR1_STATUS__dav__WIDTH 1 +#define R_PAR1_STATUS__dav__data 1 +#define R_PAR1_STATUS__dav__nodata 0 + +#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054) +#define R_PAR1_CONFIG__ioe__BITNR 25 +#define R_PAR1_CONFIG__ioe__WIDTH 1 +#define R_PAR1_CONFIG__ioe__inv 1 +#define R_PAR1_CONFIG__ioe__noninv 0 +#define R_PAR1_CONFIG__iseli__BITNR 24 +#define R_PAR1_CONFIG__iseli__WIDTH 1 +#define R_PAR1_CONFIG__iseli__inv 1 +#define R_PAR1_CONFIG__iseli__noninv 0 +#define R_PAR1_CONFIG__iautofd__BITNR 23 +#define R_PAR1_CONFIG__iautofd__WIDTH 1 +#define R_PAR1_CONFIG__iautofd__inv 1 +#define R_PAR1_CONFIG__iautofd__noninv 0 +#define R_PAR1_CONFIG__istrb__BITNR 22 +#define R_PAR1_CONFIG__istrb__WIDTH 1 +#define R_PAR1_CONFIG__istrb__inv 1 +#define R_PAR1_CONFIG__istrb__noninv 0 +#define R_PAR1_CONFIG__iinit__BITNR 21 +#define R_PAR1_CONFIG__iinit__WIDTH 1 +#define R_PAR1_CONFIG__iinit__inv 1 +#define R_PAR1_CONFIG__iinit__noninv 0 +#define R_PAR1_CONFIG__iperr__BITNR 20 +#define R_PAR1_CONFIG__iperr__WIDTH 1 +#define R_PAR1_CONFIG__iperr__inv 1 +#define R_PAR1_CONFIG__iperr__noninv 0 +#define R_PAR1_CONFIG__iack__BITNR 19 +#define R_PAR1_CONFIG__iack__WIDTH 1 +#define R_PAR1_CONFIG__iack__inv 1 +#define R_PAR1_CONFIG__iack__noninv 0 +#define R_PAR1_CONFIG__ibusy__BITNR 18 +#define R_PAR1_CONFIG__ibusy__WIDTH 1 +#define R_PAR1_CONFIG__ibusy__inv 1 +#define R_PAR1_CONFIG__ibusy__noninv 0 +#define R_PAR1_CONFIG__ifault__BITNR 17 +#define R_PAR1_CONFIG__ifault__WIDTH 1 +#define R_PAR1_CONFIG__ifault__inv 1 +#define R_PAR1_CONFIG__ifault__noninv 0 +#define R_PAR1_CONFIG__isel__BITNR 16 +#define R_PAR1_CONFIG__isel__WIDTH 1 +#define R_PAR1_CONFIG__isel__inv 1 +#define R_PAR1_CONFIG__isel__noninv 0 +#define R_PAR1_CONFIG__ext_mode__BITNR 11 +#define R_PAR1_CONFIG__ext_mode__WIDTH 1 +#define R_PAR1_CONFIG__ext_mode__enable 1 +#define R_PAR1_CONFIG__ext_mode__disable 0 +#define R_PAR1_CONFIG__dma__BITNR 9 +#define R_PAR1_CONFIG__dma__WIDTH 1 +#define R_PAR1_CONFIG__dma__enable 1 +#define R_PAR1_CONFIG__dma__disable 0 +#define R_PAR1_CONFIG__rle_in__BITNR 8 +#define R_PAR1_CONFIG__rle_in__WIDTH 1 +#define R_PAR1_CONFIG__rle_in__enable 1 +#define R_PAR1_CONFIG__rle_in__disable 0 +#define R_PAR1_CONFIG__rle_out__BITNR 7 +#define R_PAR1_CONFIG__rle_out__WIDTH 1 +#define R_PAR1_CONFIG__rle_out__enable 1 +#define R_PAR1_CONFIG__rle_out__disable 0 +#define R_PAR1_CONFIG__enable__BITNR 6 +#define R_PAR1_CONFIG__enable__WIDTH 1 +#define R_PAR1_CONFIG__enable__on 1 +#define R_PAR1_CONFIG__enable__reset 0 +#define R_PAR1_CONFIG__force__BITNR 5 +#define R_PAR1_CONFIG__force__WIDTH 1 +#define R_PAR1_CONFIG__force__on 1 +#define R_PAR1_CONFIG__force__off 0 +#define R_PAR1_CONFIG__ign_ack__BITNR 4 +#define R_PAR1_CONFIG__ign_ack__WIDTH 1 +#define R_PAR1_CONFIG__ign_ack__ignore 1 +#define R_PAR1_CONFIG__ign_ack__wait 0 +#define R_PAR1_CONFIG__oe_ack__BITNR 3 +#define R_PAR1_CONFIG__oe_ack__WIDTH 1 +#define R_PAR1_CONFIG__oe_ack__wait_oe 1 +#define R_PAR1_CONFIG__oe_ack__dont_wait 0 +#define R_PAR1_CONFIG__oe_ack__epp_addr 1 +#define R_PAR1_CONFIG__oe_ack__epp_data 0 +#define R_PAR1_CONFIG__epp_addr_data__BITNR 3 +#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1 +#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1 +#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0 +#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1 +#define R_PAR1_CONFIG__epp_addr_data__epp_data 0 +#define R_PAR1_CONFIG__mode__BITNR 0 +#define R_PAR1_CONFIG__mode__WIDTH 3 +#define R_PAR1_CONFIG__mode__manual 0 +#define R_PAR1_CONFIG__mode__centronics 1 +#define R_PAR1_CONFIG__mode__fastbyte 2 +#define R_PAR1_CONFIG__mode__nibble 3 +#define R_PAR1_CONFIG__mode__byte 4 +#define R_PAR1_CONFIG__mode__ecp_fwd 5 +#define R_PAR1_CONFIG__mode__ecp_rev 6 +#define R_PAR1_CONFIG__mode__off 7 +#define R_PAR1_CONFIG__mode__epp_wr1 5 +#define R_PAR1_CONFIG__mode__epp_wr2 6 +#define R_PAR1_CONFIG__mode__epp_wr3 7 +#define R_PAR1_CONFIG__mode__epp_rd 0 + +#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058) +#define R_PAR1_DELAY__fine_hold__BITNR 21 +#define R_PAR1_DELAY__fine_hold__WIDTH 3 +#define R_PAR1_DELAY__hold__BITNR 16 +#define R_PAR1_DELAY__hold__WIDTH 5 +#define R_PAR1_DELAY__fine_strb__BITNR 13 +#define R_PAR1_DELAY__fine_strb__WIDTH 3 +#define R_PAR1_DELAY__strobe__BITNR 8 +#define R_PAR1_DELAY__strobe__WIDTH 5 +#define R_PAR1_DELAY__fine_setup__BITNR 5 +#define R_PAR1_DELAY__fine_setup__WIDTH 3 +#define R_PAR1_DELAY__setup__BITNR 0 +#define R_PAR1_DELAY__setup__WIDTH 5 + +/* +!* ATA interface registers +!*/ + +#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_ATA_CTRL_DATA__sel__BITNR 30 +#define R_ATA_CTRL_DATA__sel__WIDTH 2 +#define R_ATA_CTRL_DATA__cs1__BITNR 29 +#define R_ATA_CTRL_DATA__cs1__WIDTH 1 +#define R_ATA_CTRL_DATA__cs1__active 1 +#define R_ATA_CTRL_DATA__cs1__inactive 0 +#define R_ATA_CTRL_DATA__cs0__BITNR 28 +#define R_ATA_CTRL_DATA__cs0__WIDTH 1 +#define R_ATA_CTRL_DATA__cs0__active 1 +#define R_ATA_CTRL_DATA__cs0__inactive 0 +#define R_ATA_CTRL_DATA__addr__BITNR 25 +#define R_ATA_CTRL_DATA__addr__WIDTH 3 +#define R_ATA_CTRL_DATA__rw__BITNR 24 +#define R_ATA_CTRL_DATA__rw__WIDTH 1 +#define R_ATA_CTRL_DATA__rw__read 1 +#define R_ATA_CTRL_DATA__rw__write 0 +#define R_ATA_CTRL_DATA__src_dst__BITNR 23 +#define R_ATA_CTRL_DATA__src_dst__WIDTH 1 +#define R_ATA_CTRL_DATA__src_dst__dma 1 +#define R_ATA_CTRL_DATA__src_dst__register 0 +#define R_ATA_CTRL_DATA__handsh__BITNR 22 +#define R_ATA_CTRL_DATA__handsh__WIDTH 1 +#define R_ATA_CTRL_DATA__handsh__dma 1 +#define R_ATA_CTRL_DATA__handsh__pio 0 +#define R_ATA_CTRL_DATA__multi__BITNR 21 +#define R_ATA_CTRL_DATA__multi__WIDTH 1 +#define R_ATA_CTRL_DATA__multi__on 1 +#define R_ATA_CTRL_DATA__multi__off 0 +#define R_ATA_CTRL_DATA__dma_size__BITNR 20 +#define R_ATA_CTRL_DATA__dma_size__WIDTH 1 +#define R_ATA_CTRL_DATA__dma_size__byte 1 +#define R_ATA_CTRL_DATA__dma_size__word 0 +#define R_ATA_CTRL_DATA__data__BITNR 0 +#define R_ATA_CTRL_DATA__data__WIDTH 16 + +#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040) +#define R_ATA_STATUS_DATA__busy__BITNR 18 +#define R_ATA_STATUS_DATA__busy__WIDTH 1 +#define R_ATA_STATUS_DATA__busy__yes 1 +#define R_ATA_STATUS_DATA__busy__no 0 +#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17 +#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1 +#define R_ATA_STATUS_DATA__tr_rdy__ready 1 +#define R_ATA_STATUS_DATA__tr_rdy__busy 0 +#define R_ATA_STATUS_DATA__dav__BITNR 16 +#define R_ATA_STATUS_DATA__dav__WIDTH 1 +#define R_ATA_STATUS_DATA__dav__data 1 +#define R_ATA_STATUS_DATA__dav__nodata 0 +#define R_ATA_STATUS_DATA__data__BITNR 0 +#define R_ATA_STATUS_DATA__data__WIDTH 16 + +#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044) +#define R_ATA_CONFIG__enable__BITNR 25 +#define R_ATA_CONFIG__enable__WIDTH 1 +#define R_ATA_CONFIG__enable__on 1 +#define R_ATA_CONFIG__enable__off 0 +#define R_ATA_CONFIG__dma_strobe__BITNR 20 +#define R_ATA_CONFIG__dma_strobe__WIDTH 5 +#define R_ATA_CONFIG__dma_hold__BITNR 15 +#define R_ATA_CONFIG__dma_hold__WIDTH 5 +#define R_ATA_CONFIG__pio_setup__BITNR 10 +#define R_ATA_CONFIG__pio_setup__WIDTH 5 +#define R_ATA_CONFIG__pio_strobe__BITNR 5 +#define R_ATA_CONFIG__pio_strobe__WIDTH 5 +#define R_ATA_CONFIG__pio_hold__BITNR 0 +#define R_ATA_CONFIG__pio_hold__WIDTH 5 + +#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048) +#define R_ATA_TRANSFER_CNT__count__BITNR 0 +#define R_ATA_TRANSFER_CNT__count__WIDTH 17 + +/* +!* SCSI registers +!*/ + +#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044) +#define R_SCSI0_CTRL__id_type__BITNR 31 +#define R_SCSI0_CTRL__id_type__WIDTH 1 +#define R_SCSI0_CTRL__id_type__software 1 +#define R_SCSI0_CTRL__id_type__hardware 0 +#define R_SCSI0_CTRL__sel_timeout__BITNR 24 +#define R_SCSI0_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI0_CTRL__synch_per__BITNR 16 +#define R_SCSI0_CTRL__synch_per__WIDTH 8 +#define R_SCSI0_CTRL__rst__BITNR 15 +#define R_SCSI0_CTRL__rst__WIDTH 1 +#define R_SCSI0_CTRL__rst__yes 1 +#define R_SCSI0_CTRL__rst__no 0 +#define R_SCSI0_CTRL__atn__BITNR 14 +#define R_SCSI0_CTRL__atn__WIDTH 1 +#define R_SCSI0_CTRL__atn__yes 1 +#define R_SCSI0_CTRL__atn__no 0 +#define R_SCSI0_CTRL__my_id__BITNR 9 +#define R_SCSI0_CTRL__my_id__WIDTH 4 +#define R_SCSI0_CTRL__target_id__BITNR 4 +#define R_SCSI0_CTRL__target_id__WIDTH 4 +#define R_SCSI0_CTRL__fast_20__BITNR 3 +#define R_SCSI0_CTRL__fast_20__WIDTH 1 +#define R_SCSI0_CTRL__fast_20__yes 1 +#define R_SCSI0_CTRL__fast_20__no 0 +#define R_SCSI0_CTRL__bus_width__BITNR 2 +#define R_SCSI0_CTRL__bus_width__WIDTH 1 +#define R_SCSI0_CTRL__bus_width__wide 1 +#define R_SCSI0_CTRL__bus_width__narrow 0 +#define R_SCSI0_CTRL__synch__BITNR 1 +#define R_SCSI0_CTRL__synch__WIDTH 1 +#define R_SCSI0_CTRL__synch__synch 1 +#define R_SCSI0_CTRL__synch__asynch 0 +#define R_SCSI0_CTRL__enable__BITNR 0 +#define R_SCSI0_CTRL__enable__WIDTH 1 +#define R_SCSI0_CTRL__enable__on 1 +#define R_SCSI0_CTRL__enable__off 0 + +#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040) +#define R_SCSI0_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI0_CMD_DATA__parity_in__on 0 +#define R_SCSI0_CMD_DATA__parity_in__off 1 +#define R_SCSI0_CMD_DATA__skip__BITNR 25 +#define R_SCSI0_CMD_DATA__skip__WIDTH 1 +#define R_SCSI0_CMD_DATA__skip__on 1 +#define R_SCSI0_CMD_DATA__skip__off 0 +#define R_SCSI0_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI0_CMD_DATA__clr_status__yes 1 +#define R_SCSI0_CMD_DATA__clr_status__nop 0 +#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__BITNR 16 +#define R_SCSI0_CMD_DATA__command__WIDTH 4 +#define R_SCSI0_CMD_DATA__command__full_din_1 0 +#define R_SCSI0_CMD_DATA__command__full_dout_1 1 +#define R_SCSI0_CMD_DATA__command__full_stat_1 2 +#define R_SCSI0_CMD_DATA__command__resel_din 3 +#define R_SCSI0_CMD_DATA__command__resel_dout 4 +#define R_SCSI0_CMD_DATA__command__resel_stat 5 +#define R_SCSI0_CMD_DATA__command__arb_only 6 +#define R_SCSI0_CMD_DATA__command__full_din_3 8 +#define R_SCSI0_CMD_DATA__command__full_dout_3 9 +#define R_SCSI0_CMD_DATA__command__full_stat_3 10 +#define R_SCSI0_CMD_DATA__command__man_data_in 11 +#define R_SCSI0_CMD_DATA__command__man_data_out 12 +#define R_SCSI0_CMD_DATA__command__man_rat 13 +#define R_SCSI0_CMD_DATA__data_out__BITNR 0 +#define R_SCSI0_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040) +#define R_SCSI0_DATA__data_out__BITNR 0 +#define R_SCSI0_DATA__data_out__WIDTH 16 + +#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042) +#define R_SCSI0_CMD__asynch_setup__BITNR 4 +#define R_SCSI0_CMD__asynch_setup__WIDTH 4 +#define R_SCSI0_CMD__command__BITNR 0 +#define R_SCSI0_CMD__command__WIDTH 4 +#define R_SCSI0_CMD__command__full_din_1 0 +#define R_SCSI0_CMD__command__full_dout_1 1 +#define R_SCSI0_CMD__command__full_stat_1 2 +#define R_SCSI0_CMD__command__resel_din 3 +#define R_SCSI0_CMD__command__resel_dout 4 +#define R_SCSI0_CMD__command__resel_stat 5 +#define R_SCSI0_CMD__command__arb_only 6 +#define R_SCSI0_CMD__command__full_din_3 8 +#define R_SCSI0_CMD__command__full_dout_3 9 +#define R_SCSI0_CMD__command__full_stat_3 10 +#define R_SCSI0_CMD__command__man_data_in 11 +#define R_SCSI0_CMD__command__man_data_out 12 +#define R_SCSI0_CMD__command__man_rat 13 + +#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043) +#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__parity_in__on 0 +#define R_SCSI0_STATUS_CTRL__parity_in__off 1 +#define R_SCSI0_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__skip__on 1 +#define R_SCSI0_STATUS_CTRL__skip__off 0 +#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI0_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI0_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048) +#define R_SCSI0_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI0_STATUS__tst_resel__BITNR 22 +#define R_SCSI0_STATUS__tst_resel__WIDTH 1 +#define R_SCSI0_STATUS__parity_error__BITNR 21 +#define R_SCSI0_STATUS__parity_error__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__BITNR 20 +#define R_SCSI0_STATUS__bus_reset__WIDTH 1 +#define R_SCSI0_STATUS__bus_reset__yes 1 +#define R_SCSI0_STATUS__bus_reset__no 0 +#define R_SCSI0_STATUS__resel_target__BITNR 15 +#define R_SCSI0_STATUS__resel_target__WIDTH 4 +#define R_SCSI0_STATUS__resel__BITNR 14 +#define R_SCSI0_STATUS__resel__WIDTH 1 +#define R_SCSI0_STATUS__resel__yes 1 +#define R_SCSI0_STATUS__resel__no 0 +#define R_SCSI0_STATUS__curr_phase__BITNR 11 +#define R_SCSI0_STATUS__curr_phase__WIDTH 3 +#define R_SCSI0_STATUS__curr_phase__ph_undef 0 +#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI0_STATUS__curr_phase__ph_status 3 +#define R_SCSI0_STATUS__curr_phase__ph_command 2 +#define R_SCSI0_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI0_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI0_STATUS__curr_phase__ph_resel 1 +#define R_SCSI0_STATUS__last_seq_step__BITNR 6 +#define R_SCSI0_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI0_STATUS__last_seq_step__st_manual 28 +#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI0_STATUS__last_seq_step__st_answer 3 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI0_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI0_STATUS__last_seq_step__st_cc 31 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI0_STATUS__valid_status__BITNR 5 +#define R_SCSI0_STATUS__valid_status__WIDTH 1 +#define R_SCSI0_STATUS__valid_status__yes 1 +#define R_SCSI0_STATUS__valid_status__no 0 +#define R_SCSI0_STATUS__seq_status__BITNR 0 +#define R_SCSI0_STATUS__seq_status__WIDTH 5 +#define R_SCSI0_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI0_STATUS__seq_status__info_parity_error 1 +#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI0_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI0_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI0_STATUS__seq_status__info_reselected 9 +#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI0_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI0_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040) +#define R_SCSI0_DATA_IN__data_in__BITNR 0 +#define R_SCSI0_DATA_IN__data_in__WIDTH 16 + +#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054) +#define R_SCSI1_CTRL__id_type__BITNR 31 +#define R_SCSI1_CTRL__id_type__WIDTH 1 +#define R_SCSI1_CTRL__id_type__software 1 +#define R_SCSI1_CTRL__id_type__hardware 0 +#define R_SCSI1_CTRL__sel_timeout__BITNR 24 +#define R_SCSI1_CTRL__sel_timeout__WIDTH 7 +#define R_SCSI1_CTRL__synch_per__BITNR 16 +#define R_SCSI1_CTRL__synch_per__WIDTH 8 +#define R_SCSI1_CTRL__rst__BITNR 15 +#define R_SCSI1_CTRL__rst__WIDTH 1 +#define R_SCSI1_CTRL__rst__yes 1 +#define R_SCSI1_CTRL__rst__no 0 +#define R_SCSI1_CTRL__atn__BITNR 14 +#define R_SCSI1_CTRL__atn__WIDTH 1 +#define R_SCSI1_CTRL__atn__yes 1 +#define R_SCSI1_CTRL__atn__no 0 +#define R_SCSI1_CTRL__my_id__BITNR 9 +#define R_SCSI1_CTRL__my_id__WIDTH 4 +#define R_SCSI1_CTRL__target_id__BITNR 4 +#define R_SCSI1_CTRL__target_id__WIDTH 4 +#define R_SCSI1_CTRL__fast_20__BITNR 3 +#define R_SCSI1_CTRL__fast_20__WIDTH 1 +#define R_SCSI1_CTRL__fast_20__yes 1 +#define R_SCSI1_CTRL__fast_20__no 0 +#define R_SCSI1_CTRL__bus_width__BITNR 2 +#define R_SCSI1_CTRL__bus_width__WIDTH 1 +#define R_SCSI1_CTRL__bus_width__wide 1 +#define R_SCSI1_CTRL__bus_width__narrow 0 +#define R_SCSI1_CTRL__synch__BITNR 1 +#define R_SCSI1_CTRL__synch__WIDTH 1 +#define R_SCSI1_CTRL__synch__synch 1 +#define R_SCSI1_CTRL__synch__asynch 0 +#define R_SCSI1_CTRL__enable__BITNR 0 +#define R_SCSI1_CTRL__enable__WIDTH 1 +#define R_SCSI1_CTRL__enable__on 1 +#define R_SCSI1_CTRL__enable__off 0 + +#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050) +#define R_SCSI1_CMD_DATA__parity_in__BITNR 26 +#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1 +#define R_SCSI1_CMD_DATA__parity_in__on 0 +#define R_SCSI1_CMD_DATA__parity_in__off 1 +#define R_SCSI1_CMD_DATA__skip__BITNR 25 +#define R_SCSI1_CMD_DATA__skip__WIDTH 1 +#define R_SCSI1_CMD_DATA__skip__on 1 +#define R_SCSI1_CMD_DATA__skip__off 0 +#define R_SCSI1_CMD_DATA__clr_status__BITNR 24 +#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1 +#define R_SCSI1_CMD_DATA__clr_status__yes 1 +#define R_SCSI1_CMD_DATA__clr_status__nop 0 +#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20 +#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__BITNR 16 +#define R_SCSI1_CMD_DATA__command__WIDTH 4 +#define R_SCSI1_CMD_DATA__command__full_din_1 0 +#define R_SCSI1_CMD_DATA__command__full_dout_1 1 +#define R_SCSI1_CMD_DATA__command__full_stat_1 2 +#define R_SCSI1_CMD_DATA__command__resel_din 3 +#define R_SCSI1_CMD_DATA__command__resel_dout 4 +#define R_SCSI1_CMD_DATA__command__resel_stat 5 +#define R_SCSI1_CMD_DATA__command__arb_only 6 +#define R_SCSI1_CMD_DATA__command__full_din_3 8 +#define R_SCSI1_CMD_DATA__command__full_dout_3 9 +#define R_SCSI1_CMD_DATA__command__full_stat_3 10 +#define R_SCSI1_CMD_DATA__command__man_data_in 11 +#define R_SCSI1_CMD_DATA__command__man_data_out 12 +#define R_SCSI1_CMD_DATA__command__man_rat 13 +#define R_SCSI1_CMD_DATA__data_out__BITNR 0 +#define R_SCSI1_CMD_DATA__data_out__WIDTH 16 + +#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050) +#define R_SCSI1_DATA__data_out__BITNR 0 +#define R_SCSI1_DATA__data_out__WIDTH 16 + +#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052) +#define R_SCSI1_CMD__asynch_setup__BITNR 4 +#define R_SCSI1_CMD__asynch_setup__WIDTH 4 +#define R_SCSI1_CMD__command__BITNR 0 +#define R_SCSI1_CMD__command__WIDTH 4 +#define R_SCSI1_CMD__command__full_din_1 0 +#define R_SCSI1_CMD__command__full_dout_1 1 +#define R_SCSI1_CMD__command__full_stat_1 2 +#define R_SCSI1_CMD__command__resel_din 3 +#define R_SCSI1_CMD__command__resel_dout 4 +#define R_SCSI1_CMD__command__resel_stat 5 +#define R_SCSI1_CMD__command__arb_only 6 +#define R_SCSI1_CMD__command__full_din_3 8 +#define R_SCSI1_CMD__command__full_dout_3 9 +#define R_SCSI1_CMD__command__full_stat_3 10 +#define R_SCSI1_CMD__command__man_data_in 11 +#define R_SCSI1_CMD__command__man_data_out 12 +#define R_SCSI1_CMD__command__man_rat 13 + +#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053) +#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2 +#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__parity_in__on 0 +#define R_SCSI1_STATUS_CTRL__parity_in__off 1 +#define R_SCSI1_STATUS_CTRL__skip__BITNR 1 +#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__skip__on 1 +#define R_SCSI1_STATUS_CTRL__skip__off 0 +#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0 +#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1 +#define R_SCSI1_STATUS_CTRL__clr_status__yes 1 +#define R_SCSI1_STATUS_CTRL__clr_status__nop 0 + +#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058) +#define R_SCSI1_STATUS__tst_arb_won__BITNR 23 +#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1 +#define R_SCSI1_STATUS__tst_resel__BITNR 22 +#define R_SCSI1_STATUS__tst_resel__WIDTH 1 +#define R_SCSI1_STATUS__parity_error__BITNR 21 +#define R_SCSI1_STATUS__parity_error__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__BITNR 20 +#define R_SCSI1_STATUS__bus_reset__WIDTH 1 +#define R_SCSI1_STATUS__bus_reset__yes 1 +#define R_SCSI1_STATUS__bus_reset__no 0 +#define R_SCSI1_STATUS__resel_target__BITNR 15 +#define R_SCSI1_STATUS__resel_target__WIDTH 4 +#define R_SCSI1_STATUS__resel__BITNR 14 +#define R_SCSI1_STATUS__resel__WIDTH 1 +#define R_SCSI1_STATUS__resel__yes 1 +#define R_SCSI1_STATUS__resel__no 0 +#define R_SCSI1_STATUS__curr_phase__BITNR 11 +#define R_SCSI1_STATUS__curr_phase__WIDTH 3 +#define R_SCSI1_STATUS__curr_phase__ph_undef 0 +#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7 +#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6 +#define R_SCSI1_STATUS__curr_phase__ph_status 3 +#define R_SCSI1_STATUS__curr_phase__ph_command 2 +#define R_SCSI1_STATUS__curr_phase__ph_data_in 5 +#define R_SCSI1_STATUS__curr_phase__ph_data_out 4 +#define R_SCSI1_STATUS__curr_phase__ph_resel 1 +#define R_SCSI1_STATUS__last_seq_step__BITNR 6 +#define R_SCSI1_STATUS__last_seq_step__WIDTH 5 +#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24 +#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8 +#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29 +#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2 +#define R_SCSI1_STATUS__last_seq_step__st_manual 28 +#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30 +#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6 +#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22 +#define R_SCSI1_STATUS__last_seq_step__st_answer 3 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1 +#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9 +#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12 +#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5 +#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11 +#define R_SCSI1_STATUS__last_seq_step__st_iwr 27 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21 +#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7 +#define R_SCSI1_STATUS__last_seq_step__st_cc 31 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14 +#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20 +#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16 +#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10 +#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18 +#define R_SCSI1_STATUS__valid_status__BITNR 5 +#define R_SCSI1_STATUS__valid_status__WIDTH 1 +#define R_SCSI1_STATUS__valid_status__yes 1 +#define R_SCSI1_STATUS__valid_status__no 0 +#define R_SCSI1_STATUS__seq_status__BITNR 0 +#define R_SCSI1_STATUS__seq_status__WIDTH 5 +#define R_SCSI1_STATUS__seq_status__info_seq_complete 0 +#define R_SCSI1_STATUS__seq_status__info_parity_error 1 +#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2 +#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3 +#define R_SCSI1_STATUS__seq_status__info_arb_lost 4 +#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5 +#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6 +#define R_SCSI1_STATUS__seq_status__info_illegal_op 7 +#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8 +#define R_SCSI1_STATUS__seq_status__info_reselected 9 +#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10 +#define R_SCSI1_STATUS__seq_status__info_bus_reset 11 +#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12 +#define R_SCSI1_STATUS__seq_status__info_bus_free 13 + +#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050) +#define R_SCSI1_DATA_IN__data_in__BITNR 0 +#define R_SCSI1_DATA_IN__data_in__WIDTH 16 + +/* +!* Interrupt mask and status registers +!*/ + +#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_RD__nmi_pin__active 1 +#define R_IRQ_MASK0_RD__nmi_pin__inactive 0 +#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__active 1 +#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0 +#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_RD__sqe_test_error__active 1 +#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0 +#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_RD__carrier_loss__active 1 +#define R_IRQ_MASK0_RD__carrier_loss__inactive 0 +#define R_IRQ_MASK0_RD__deferred__BITNR 27 +#define R_IRQ_MASK0_RD__deferred__WIDTH 1 +#define R_IRQ_MASK0_RD__deferred__active 1 +#define R_IRQ_MASK0_RD__deferred__inactive 0 +#define R_IRQ_MASK0_RD__late_col__BITNR 26 +#define R_IRQ_MASK0_RD__late_col__WIDTH 1 +#define R_IRQ_MASK0_RD__late_col__active 1 +#define R_IRQ_MASK0_RD__late_col__inactive 0 +#define R_IRQ_MASK0_RD__multiple_col__BITNR 25 +#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_RD__multiple_col__active 1 +#define R_IRQ_MASK0_RD__multiple_col__inactive 0 +#define R_IRQ_MASK0_RD__single_col__BITNR 24 +#define R_IRQ_MASK0_RD__single_col__WIDTH 1 +#define R_IRQ_MASK0_RD__single_col__active 1 +#define R_IRQ_MASK0_RD__single_col__inactive 0 +#define R_IRQ_MASK0_RD__congestion__BITNR 23 +#define R_IRQ_MASK0_RD__congestion__WIDTH 1 +#define R_IRQ_MASK0_RD__congestion__active 1 +#define R_IRQ_MASK0_RD__congestion__inactive 0 +#define R_IRQ_MASK0_RD__oversize__BITNR 22 +#define R_IRQ_MASK0_RD__oversize__WIDTH 1 +#define R_IRQ_MASK0_RD__oversize__active 1 +#define R_IRQ_MASK0_RD__oversize__inactive 0 +#define R_IRQ_MASK0_RD__alignment_error__BITNR 21 +#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_RD__alignment_error__active 1 +#define R_IRQ_MASK0_RD__alignment_error__inactive 0 +#define R_IRQ_MASK0_RD__crc_error__BITNR 20 +#define R_IRQ_MASK0_RD__crc_error__WIDTH 1 +#define R_IRQ_MASK0_RD__crc_error__active 1 +#define R_IRQ_MASK0_RD__crc_error__inactive 0 +#define R_IRQ_MASK0_RD__overrun__BITNR 19 +#define R_IRQ_MASK0_RD__overrun__WIDTH 1 +#define R_IRQ_MASK0_RD__overrun__active 1 +#define R_IRQ_MASK0_RD__overrun__inactive 0 +#define R_IRQ_MASK0_RD__underrun__BITNR 18 +#define R_IRQ_MASK0_RD__underrun__WIDTH 1 +#define R_IRQ_MASK0_RD__underrun__active 1 +#define R_IRQ_MASK0_RD__underrun__inactive 0 +#define R_IRQ_MASK0_RD__excessive_col__BITNR 17 +#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_RD__excessive_col__active 1 +#define R_IRQ_MASK0_RD__excessive_col__inactive 0 +#define R_IRQ_MASK0_RD__mdio__BITNR 16 +#define R_IRQ_MASK0_RD__mdio__WIDTH 1 +#define R_IRQ_MASK0_RD__mdio__active 1 +#define R_IRQ_MASK0_RD__mdio__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq3__active 1 +#define R_IRQ_MASK0_RD__ata_drq3__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq2__active 1 +#define R_IRQ_MASK0_RD__ata_drq2__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq1__active 1 +#define R_IRQ_MASK0_RD__ata_drq1__inactive 0 +#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_drq0__active 1 +#define R_IRQ_MASK0_RD__ata_drq0__inactive 0 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1 +#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq3__active 1 +#define R_IRQ_MASK0_RD__ata_irq3__inactive 0 +#define R_IRQ_MASK0_RD__par0_peri__BITNR 10 +#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_peri__active 1 +#define R_IRQ_MASK0_RD__par0_peri__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq2__active 1 +#define R_IRQ_MASK0_RD__ata_irq2__inactive 0 +#define R_IRQ_MASK0_RD__par0_data__BITNR 9 +#define R_IRQ_MASK0_RD__par0_data__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_data__active 1 +#define R_IRQ_MASK0_RD__par0_data__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq1__active 1 +#define R_IRQ_MASK0_RD__ata_irq1__inactive 0 +#define R_IRQ_MASK0_RD__par0_ready__BITNR 8 +#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_RD__par0_ready__active 1 +#define R_IRQ_MASK0_RD__par0_ready__inactive 0 +#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_irq0__active 1 +#define R_IRQ_MASK0_RD__ata_irq0__inactive 0 +#define R_IRQ_MASK0_RD__mio__BITNR 8 +#define R_IRQ_MASK0_RD__mio__WIDTH 1 +#define R_IRQ_MASK0_RD__mio__active 1 +#define R_IRQ_MASK0_RD__mio__inactive 0 +#define R_IRQ_MASK0_RD__scsi0__BITNR 8 +#define R_IRQ_MASK0_RD__scsi0__WIDTH 1 +#define R_IRQ_MASK0_RD__scsi0__active 1 +#define R_IRQ_MASK0_RD__scsi0__inactive 0 +#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_RD__ata_dmaend__active 1 +#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1 +#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma1__active 1 +#define R_IRQ_MASK0_RD__ext_dma1__inactive 0 +#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_RD__ext_dma0__active 1 +#define R_IRQ_MASK0_RD__ext_dma0__inactive 0 +#define R_IRQ_MASK0_RD__timer1__BITNR 1 +#define R_IRQ_MASK0_RD__timer1__WIDTH 1 +#define R_IRQ_MASK0_RD__timer1__active 1 +#define R_IRQ_MASK0_RD__timer1__inactive 0 +#define R_IRQ_MASK0_RD__timer0__BITNR 0 +#define R_IRQ_MASK0_RD__timer0__WIDTH 1 +#define R_IRQ_MASK0_RD__timer0__active 1 +#define R_IRQ_MASK0_RD__timer0__inactive 0 + +#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0) +#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_CLR__nmi_pin__clr 1 +#define R_IRQ_MASK0_CLR__nmi_pin__nop 0 +#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1 +#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1 +#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0 +#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_CLR__carrier_loss__clr 1 +#define R_IRQ_MASK0_CLR__carrier_loss__nop 0 +#define R_IRQ_MASK0_CLR__deferred__BITNR 27 +#define R_IRQ_MASK0_CLR__deferred__WIDTH 1 +#define R_IRQ_MASK0_CLR__deferred__clr 1 +#define R_IRQ_MASK0_CLR__deferred__nop 0 +#define R_IRQ_MASK0_CLR__late_col__BITNR 26 +#define R_IRQ_MASK0_CLR__late_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__late_col__clr 1 +#define R_IRQ_MASK0_CLR__late_col__nop 0 +#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25 +#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__multiple_col__clr 1 +#define R_IRQ_MASK0_CLR__multiple_col__nop 0 +#define R_IRQ_MASK0_CLR__single_col__BITNR 24 +#define R_IRQ_MASK0_CLR__single_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__single_col__clr 1 +#define R_IRQ_MASK0_CLR__single_col__nop 0 +#define R_IRQ_MASK0_CLR__congestion__BITNR 23 +#define R_IRQ_MASK0_CLR__congestion__WIDTH 1 +#define R_IRQ_MASK0_CLR__congestion__clr 1 +#define R_IRQ_MASK0_CLR__congestion__nop 0 +#define R_IRQ_MASK0_CLR__oversize__BITNR 22 +#define R_IRQ_MASK0_CLR__oversize__WIDTH 1 +#define R_IRQ_MASK0_CLR__oversize__clr 1 +#define R_IRQ_MASK0_CLR__oversize__nop 0 +#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21 +#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__alignment_error__clr 1 +#define R_IRQ_MASK0_CLR__alignment_error__nop 0 +#define R_IRQ_MASK0_CLR__crc_error__BITNR 20 +#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1 +#define R_IRQ_MASK0_CLR__crc_error__clr 1 +#define R_IRQ_MASK0_CLR__crc_error__nop 0 +#define R_IRQ_MASK0_CLR__overrun__BITNR 19 +#define R_IRQ_MASK0_CLR__overrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__overrun__clr 1 +#define R_IRQ_MASK0_CLR__overrun__nop 0 +#define R_IRQ_MASK0_CLR__underrun__BITNR 18 +#define R_IRQ_MASK0_CLR__underrun__WIDTH 1 +#define R_IRQ_MASK0_CLR__underrun__clr 1 +#define R_IRQ_MASK0_CLR__underrun__nop 0 +#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17 +#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_CLR__excessive_col__clr 1 +#define R_IRQ_MASK0_CLR__excessive_col__nop 0 +#define R_IRQ_MASK0_CLR__mdio__BITNR 16 +#define R_IRQ_MASK0_CLR__mdio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mdio__clr 1 +#define R_IRQ_MASK0_CLR__mdio__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq3__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq2__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq1__nop 0 +#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_drq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_drq0__nop 0 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1 +#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq3__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq3__nop 0 +#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10 +#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_peri__clr 1 +#define R_IRQ_MASK0_CLR__par0_peri__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq2__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq2__nop 0 +#define R_IRQ_MASK0_CLR__par0_data__BITNR 9 +#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_data__clr 1 +#define R_IRQ_MASK0_CLR__par0_data__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq1__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq1__nop 0 +#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8 +#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_CLR__par0_ready__clr 1 +#define R_IRQ_MASK0_CLR__par0_ready__nop 0 +#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_irq0__clr 1 +#define R_IRQ_MASK0_CLR__ata_irq0__nop 0 +#define R_IRQ_MASK0_CLR__mio__BITNR 8 +#define R_IRQ_MASK0_CLR__mio__WIDTH 1 +#define R_IRQ_MASK0_CLR__mio__clr 1 +#define R_IRQ_MASK0_CLR__mio__nop 0 +#define R_IRQ_MASK0_CLR__scsi0__BITNR 8 +#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1 +#define R_IRQ_MASK0_CLR__scsi0__clr 1 +#define R_IRQ_MASK0_CLR__scsi0__nop 0 +#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1 +#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1 +#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma1__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma1__nop 0 +#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_CLR__ext_dma0__clr 1 +#define R_IRQ_MASK0_CLR__ext_dma0__nop 0 +#define R_IRQ_MASK0_CLR__timer1__BITNR 1 +#define R_IRQ_MASK0_CLR__timer1__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer1__clr 1 +#define R_IRQ_MASK0_CLR__timer1__nop 0 +#define R_IRQ_MASK0_CLR__timer0__BITNR 0 +#define R_IRQ_MASK0_CLR__timer0__WIDTH 1 +#define R_IRQ_MASK0_CLR__timer0__clr 1 +#define R_IRQ_MASK0_CLR__timer0__nop 0 + +#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4) +#define R_IRQ_READ0__nmi_pin__BITNR 31 +#define R_IRQ_READ0__nmi_pin__WIDTH 1 +#define R_IRQ_READ0__nmi_pin__active 1 +#define R_IRQ_READ0__nmi_pin__inactive 0 +#define R_IRQ_READ0__watchdog_nmi__BITNR 30 +#define R_IRQ_READ0__watchdog_nmi__WIDTH 1 +#define R_IRQ_READ0__watchdog_nmi__active 1 +#define R_IRQ_READ0__watchdog_nmi__inactive 0 +#define R_IRQ_READ0__sqe_test_error__BITNR 29 +#define R_IRQ_READ0__sqe_test_error__WIDTH 1 +#define R_IRQ_READ0__sqe_test_error__active 1 +#define R_IRQ_READ0__sqe_test_error__inactive 0 +#define R_IRQ_READ0__carrier_loss__BITNR 28 +#define R_IRQ_READ0__carrier_loss__WIDTH 1 +#define R_IRQ_READ0__carrier_loss__active 1 +#define R_IRQ_READ0__carrier_loss__inactive 0 +#define R_IRQ_READ0__deferred__BITNR 27 +#define R_IRQ_READ0__deferred__WIDTH 1 +#define R_IRQ_READ0__deferred__active 1 +#define R_IRQ_READ0__deferred__inactive 0 +#define R_IRQ_READ0__late_col__BITNR 26 +#define R_IRQ_READ0__late_col__WIDTH 1 +#define R_IRQ_READ0__late_col__active 1 +#define R_IRQ_READ0__late_col__inactive 0 +#define R_IRQ_READ0__multiple_col__BITNR 25 +#define R_IRQ_READ0__multiple_col__WIDTH 1 +#define R_IRQ_READ0__multiple_col__active 1 +#define R_IRQ_READ0__multiple_col__inactive 0 +#define R_IRQ_READ0__single_col__BITNR 24 +#define R_IRQ_READ0__single_col__WIDTH 1 +#define R_IRQ_READ0__single_col__active 1 +#define R_IRQ_READ0__single_col__inactive 0 +#define R_IRQ_READ0__congestion__BITNR 23 +#define R_IRQ_READ0__congestion__WIDTH 1 +#define R_IRQ_READ0__congestion__active 1 +#define R_IRQ_READ0__congestion__inactive 0 +#define R_IRQ_READ0__oversize__BITNR 22 +#define R_IRQ_READ0__oversize__WIDTH 1 +#define R_IRQ_READ0__oversize__active 1 +#define R_IRQ_READ0__oversize__inactive 0 +#define R_IRQ_READ0__alignment_error__BITNR 21 +#define R_IRQ_READ0__alignment_error__WIDTH 1 +#define R_IRQ_READ0__alignment_error__active 1 +#define R_IRQ_READ0__alignment_error__inactive 0 +#define R_IRQ_READ0__crc_error__BITNR 20 +#define R_IRQ_READ0__crc_error__WIDTH 1 +#define R_IRQ_READ0__crc_error__active 1 +#define R_IRQ_READ0__crc_error__inactive 0 +#define R_IRQ_READ0__overrun__BITNR 19 +#define R_IRQ_READ0__overrun__WIDTH 1 +#define R_IRQ_READ0__overrun__active 1 +#define R_IRQ_READ0__overrun__inactive 0 +#define R_IRQ_READ0__underrun__BITNR 18 +#define R_IRQ_READ0__underrun__WIDTH 1 +#define R_IRQ_READ0__underrun__active 1 +#define R_IRQ_READ0__underrun__inactive 0 +#define R_IRQ_READ0__excessive_col__BITNR 17 +#define R_IRQ_READ0__excessive_col__WIDTH 1 +#define R_IRQ_READ0__excessive_col__active 1 +#define R_IRQ_READ0__excessive_col__inactive 0 +#define R_IRQ_READ0__mdio__BITNR 16 +#define R_IRQ_READ0__mdio__WIDTH 1 +#define R_IRQ_READ0__mdio__active 1 +#define R_IRQ_READ0__mdio__inactive 0 +#define R_IRQ_READ0__ata_drq3__BITNR 15 +#define R_IRQ_READ0__ata_drq3__WIDTH 1 +#define R_IRQ_READ0__ata_drq3__active 1 +#define R_IRQ_READ0__ata_drq3__inactive 0 +#define R_IRQ_READ0__ata_drq2__BITNR 14 +#define R_IRQ_READ0__ata_drq2__WIDTH 1 +#define R_IRQ_READ0__ata_drq2__active 1 +#define R_IRQ_READ0__ata_drq2__inactive 0 +#define R_IRQ_READ0__ata_drq1__BITNR 13 +#define R_IRQ_READ0__ata_drq1__WIDTH 1 +#define R_IRQ_READ0__ata_drq1__active 1 +#define R_IRQ_READ0__ata_drq1__inactive 0 +#define R_IRQ_READ0__ata_drq0__BITNR 12 +#define R_IRQ_READ0__ata_drq0__WIDTH 1 +#define R_IRQ_READ0__ata_drq0__active 1 +#define R_IRQ_READ0__ata_drq0__inactive 0 +#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11 +#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_READ0__par0_ecp_cmd__active 1 +#define R_IRQ_READ0__par0_ecp_cmd__inactive 0 +#define R_IRQ_READ0__ata_irq3__BITNR 11 +#define R_IRQ_READ0__ata_irq3__WIDTH 1 +#define R_IRQ_READ0__ata_irq3__active 1 +#define R_IRQ_READ0__ata_irq3__inactive 0 +#define R_IRQ_READ0__par0_peri__BITNR 10 +#define R_IRQ_READ0__par0_peri__WIDTH 1 +#define R_IRQ_READ0__par0_peri__active 1 +#define R_IRQ_READ0__par0_peri__inactive 0 +#define R_IRQ_READ0__ata_irq2__BITNR 10 +#define R_IRQ_READ0__ata_irq2__WIDTH 1 +#define R_IRQ_READ0__ata_irq2__active 1 +#define R_IRQ_READ0__ata_irq2__inactive 0 +#define R_IRQ_READ0__par0_data__BITNR 9 +#define R_IRQ_READ0__par0_data__WIDTH 1 +#define R_IRQ_READ0__par0_data__active 1 +#define R_IRQ_READ0__par0_data__inactive 0 +#define R_IRQ_READ0__ata_irq1__BITNR 9 +#define R_IRQ_READ0__ata_irq1__WIDTH 1 +#define R_IRQ_READ0__ata_irq1__active 1 +#define R_IRQ_READ0__ata_irq1__inactive 0 +#define R_IRQ_READ0__par0_ready__BITNR 8 +#define R_IRQ_READ0__par0_ready__WIDTH 1 +#define R_IRQ_READ0__par0_ready__active 1 +#define R_IRQ_READ0__par0_ready__inactive 0 +#define R_IRQ_READ0__ata_irq0__BITNR 8 +#define R_IRQ_READ0__ata_irq0__WIDTH 1 +#define R_IRQ_READ0__ata_irq0__active 1 +#define R_IRQ_READ0__ata_irq0__inactive 0 +#define R_IRQ_READ0__mio__BITNR 8 +#define R_IRQ_READ0__mio__WIDTH 1 +#define R_IRQ_READ0__mio__active 1 +#define R_IRQ_READ0__mio__inactive 0 +#define R_IRQ_READ0__scsi0__BITNR 8 +#define R_IRQ_READ0__scsi0__WIDTH 1 +#define R_IRQ_READ0__scsi0__active 1 +#define R_IRQ_READ0__scsi0__inactive 0 +#define R_IRQ_READ0__ata_dmaend__BITNR 7 +#define R_IRQ_READ0__ata_dmaend__WIDTH 1 +#define R_IRQ_READ0__ata_dmaend__active 1 +#define R_IRQ_READ0__ata_dmaend__inactive 0 +#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_ext_vector_nr__active 1 +#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0 +#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4 +#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_READ0__irq_int_vector_nr__active 1 +#define R_IRQ_READ0__irq_int_vector_nr__inactive 0 +#define R_IRQ_READ0__ext_dma1__BITNR 3 +#define R_IRQ_READ0__ext_dma1__WIDTH 1 +#define R_IRQ_READ0__ext_dma1__active 1 +#define R_IRQ_READ0__ext_dma1__inactive 0 +#define R_IRQ_READ0__ext_dma0__BITNR 2 +#define R_IRQ_READ0__ext_dma0__WIDTH 1 +#define R_IRQ_READ0__ext_dma0__active 1 +#define R_IRQ_READ0__ext_dma0__inactive 0 +#define R_IRQ_READ0__timer1__BITNR 1 +#define R_IRQ_READ0__timer1__WIDTH 1 +#define R_IRQ_READ0__timer1__active 1 +#define R_IRQ_READ0__timer1__inactive 0 +#define R_IRQ_READ0__timer0__BITNR 0 +#define R_IRQ_READ0__timer0__WIDTH 1 +#define R_IRQ_READ0__timer0__active 1 +#define R_IRQ_READ0__timer0__inactive 0 + +#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4) +#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31 +#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1 +#define R_IRQ_MASK0_SET__nmi_pin__set 1 +#define R_IRQ_MASK0_SET__nmi_pin__nop 0 +#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30 +#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__set 1 +#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0 +#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29 +#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1 +#define R_IRQ_MASK0_SET__sqe_test_error__set 1 +#define R_IRQ_MASK0_SET__sqe_test_error__nop 0 +#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28 +#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1 +#define R_IRQ_MASK0_SET__carrier_loss__set 1 +#define R_IRQ_MASK0_SET__carrier_loss__nop 0 +#define R_IRQ_MASK0_SET__deferred__BITNR 27 +#define R_IRQ_MASK0_SET__deferred__WIDTH 1 +#define R_IRQ_MASK0_SET__deferred__set 1 +#define R_IRQ_MASK0_SET__deferred__nop 0 +#define R_IRQ_MASK0_SET__late_col__BITNR 26 +#define R_IRQ_MASK0_SET__late_col__WIDTH 1 +#define R_IRQ_MASK0_SET__late_col__set 1 +#define R_IRQ_MASK0_SET__late_col__nop 0 +#define R_IRQ_MASK0_SET__multiple_col__BITNR 25 +#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1 +#define R_IRQ_MASK0_SET__multiple_col__set 1 +#define R_IRQ_MASK0_SET__multiple_col__nop 0 +#define R_IRQ_MASK0_SET__single_col__BITNR 24 +#define R_IRQ_MASK0_SET__single_col__WIDTH 1 +#define R_IRQ_MASK0_SET__single_col__set 1 +#define R_IRQ_MASK0_SET__single_col__nop 0 +#define R_IRQ_MASK0_SET__congestion__BITNR 23 +#define R_IRQ_MASK0_SET__congestion__WIDTH 1 +#define R_IRQ_MASK0_SET__congestion__set 1 +#define R_IRQ_MASK0_SET__congestion__nop 0 +#define R_IRQ_MASK0_SET__oversize__BITNR 22 +#define R_IRQ_MASK0_SET__oversize__WIDTH 1 +#define R_IRQ_MASK0_SET__oversize__set 1 +#define R_IRQ_MASK0_SET__oversize__nop 0 +#define R_IRQ_MASK0_SET__alignment_error__BITNR 21 +#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1 +#define R_IRQ_MASK0_SET__alignment_error__set 1 +#define R_IRQ_MASK0_SET__alignment_error__nop 0 +#define R_IRQ_MASK0_SET__crc_error__BITNR 20 +#define R_IRQ_MASK0_SET__crc_error__WIDTH 1 +#define R_IRQ_MASK0_SET__crc_error__set 1 +#define R_IRQ_MASK0_SET__crc_error__nop 0 +#define R_IRQ_MASK0_SET__overrun__BITNR 19 +#define R_IRQ_MASK0_SET__overrun__WIDTH 1 +#define R_IRQ_MASK0_SET__overrun__set 1 +#define R_IRQ_MASK0_SET__overrun__nop 0 +#define R_IRQ_MASK0_SET__underrun__BITNR 18 +#define R_IRQ_MASK0_SET__underrun__WIDTH 1 +#define R_IRQ_MASK0_SET__underrun__set 1 +#define R_IRQ_MASK0_SET__underrun__nop 0 +#define R_IRQ_MASK0_SET__excessive_col__BITNR 17 +#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1 +#define R_IRQ_MASK0_SET__excessive_col__set 1 +#define R_IRQ_MASK0_SET__excessive_col__nop 0 +#define R_IRQ_MASK0_SET__mdio__BITNR 16 +#define R_IRQ_MASK0_SET__mdio__WIDTH 1 +#define R_IRQ_MASK0_SET__mdio__set 1 +#define R_IRQ_MASK0_SET__mdio__nop 0 +#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15 +#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq3__set 1 +#define R_IRQ_MASK0_SET__ata_drq3__nop 0 +#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14 +#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq2__set 1 +#define R_IRQ_MASK0_SET__ata_drq2__nop 0 +#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13 +#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq1__set 1 +#define R_IRQ_MASK0_SET__ata_drq1__nop 0 +#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12 +#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_drq0__set 1 +#define R_IRQ_MASK0_SET__ata_drq0__nop 0 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1 +#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0 +#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11 +#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq3__set 1 +#define R_IRQ_MASK0_SET__ata_irq3__nop 0 +#define R_IRQ_MASK0_SET__par0_peri__BITNR 10 +#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_peri__set 1 +#define R_IRQ_MASK0_SET__par0_peri__nop 0 +#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10 +#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq2__set 1 +#define R_IRQ_MASK0_SET__ata_irq2__nop 0 +#define R_IRQ_MASK0_SET__par0_data__BITNR 9 +#define R_IRQ_MASK0_SET__par0_data__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_data__set 1 +#define R_IRQ_MASK0_SET__par0_data__nop 0 +#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9 +#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq1__set 1 +#define R_IRQ_MASK0_SET__ata_irq1__nop 0 +#define R_IRQ_MASK0_SET__par0_ready__BITNR 8 +#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1 +#define R_IRQ_MASK0_SET__par0_ready__set 1 +#define R_IRQ_MASK0_SET__par0_ready__nop 0 +#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8 +#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_irq0__set 1 +#define R_IRQ_MASK0_SET__ata_irq0__nop 0 +#define R_IRQ_MASK0_SET__mio__BITNR 8 +#define R_IRQ_MASK0_SET__mio__WIDTH 1 +#define R_IRQ_MASK0_SET__mio__set 1 +#define R_IRQ_MASK0_SET__mio__nop 0 +#define R_IRQ_MASK0_SET__scsi0__BITNR 8 +#define R_IRQ_MASK0_SET__scsi0__WIDTH 1 +#define R_IRQ_MASK0_SET__scsi0__set 1 +#define R_IRQ_MASK0_SET__scsi0__nop 0 +#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7 +#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1 +#define R_IRQ_MASK0_SET__ata_dmaend__set 1 +#define R_IRQ_MASK0_SET__ata_dmaend__nop 0 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1 +#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0 +#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3 +#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma1__set 1 +#define R_IRQ_MASK0_SET__ext_dma1__nop 0 +#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2 +#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1 +#define R_IRQ_MASK0_SET__ext_dma0__set 1 +#define R_IRQ_MASK0_SET__ext_dma0__nop 0 +#define R_IRQ_MASK0_SET__timer1__BITNR 1 +#define R_IRQ_MASK0_SET__timer1__WIDTH 1 +#define R_IRQ_MASK0_SET__timer1__set 1 +#define R_IRQ_MASK0_SET__timer1__nop 0 +#define R_IRQ_MASK0_SET__timer0__BITNR 0 +#define R_IRQ_MASK0_SET__timer0__WIDTH 1 +#define R_IRQ_MASK0_SET__timer0__set 1 +#define R_IRQ_MASK0_SET__timer0__nop 0 + +#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_RD__sw_int7__BITNR 31 +#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int7__active 1 +#define R_IRQ_MASK1_RD__sw_int7__inactive 0 +#define R_IRQ_MASK1_RD__sw_int6__BITNR 30 +#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int6__active 1 +#define R_IRQ_MASK1_RD__sw_int6__inactive 0 +#define R_IRQ_MASK1_RD__sw_int5__BITNR 29 +#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int5__active 1 +#define R_IRQ_MASK1_RD__sw_int5__inactive 0 +#define R_IRQ_MASK1_RD__sw_int4__BITNR 28 +#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int4__active 1 +#define R_IRQ_MASK1_RD__sw_int4__inactive 0 +#define R_IRQ_MASK1_RD__sw_int3__BITNR 27 +#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int3__active 1 +#define R_IRQ_MASK1_RD__sw_int3__inactive 0 +#define R_IRQ_MASK1_RD__sw_int2__BITNR 26 +#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int2__active 1 +#define R_IRQ_MASK1_RD__sw_int2__inactive 0 +#define R_IRQ_MASK1_RD__sw_int1__BITNR 25 +#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int1__active 1 +#define R_IRQ_MASK1_RD__sw_int1__inactive 0 +#define R_IRQ_MASK1_RD__sw_int0__BITNR 24 +#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_RD__sw_int0__active 1 +#define R_IRQ_MASK1_RD__sw_int0__inactive 0 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1 +#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0 +#define R_IRQ_MASK1_RD__par1_peri__BITNR 18 +#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_peri__active 1 +#define R_IRQ_MASK1_RD__par1_peri__inactive 0 +#define R_IRQ_MASK1_RD__par1_data__BITNR 17 +#define R_IRQ_MASK1_RD__par1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_data__active 1 +#define R_IRQ_MASK1_RD__par1_data__inactive 0 +#define R_IRQ_MASK1_RD__par1_ready__BITNR 16 +#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__par1_ready__active 1 +#define R_IRQ_MASK1_RD__par1_ready__inactive 0 +#define R_IRQ_MASK1_RD__scsi1__BITNR 16 +#define R_IRQ_MASK1_RD__scsi1__WIDTH 1 +#define R_IRQ_MASK1_RD__scsi1__active 1 +#define R_IRQ_MASK1_RD__scsi1__inactive 0 +#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_ready__active 1 +#define R_IRQ_MASK1_RD__ser3_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser3_data__BITNR 14 +#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser3_data__active 1 +#define R_IRQ_MASK1_RD__ser3_data__inactive 0 +#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_ready__active 1 +#define R_IRQ_MASK1_RD__ser2_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser2_data__BITNR 12 +#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser2_data__active 1 +#define R_IRQ_MASK1_RD__ser2_data__inactive 0 +#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_ready__active 1 +#define R_IRQ_MASK1_RD__ser1_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser1_data__BITNR 10 +#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser1_data__active 1 +#define R_IRQ_MASK1_RD__ser1_data__inactive 0 +#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_ready__active 1 +#define R_IRQ_MASK1_RD__ser0_ready__inactive 0 +#define R_IRQ_MASK1_RD__ser0_data__BITNR 8 +#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_RD__ser0_data__active 1 +#define R_IRQ_MASK1_RD__ser0_data__inactive 0 +#define R_IRQ_MASK1_RD__pa7__BITNR 7 +#define R_IRQ_MASK1_RD__pa7__WIDTH 1 +#define R_IRQ_MASK1_RD__pa7__active 1 +#define R_IRQ_MASK1_RD__pa7__inactive 0 +#define R_IRQ_MASK1_RD__pa6__BITNR 6 +#define R_IRQ_MASK1_RD__pa6__WIDTH 1 +#define R_IRQ_MASK1_RD__pa6__active 1 +#define R_IRQ_MASK1_RD__pa6__inactive 0 +#define R_IRQ_MASK1_RD__pa5__BITNR 5 +#define R_IRQ_MASK1_RD__pa5__WIDTH 1 +#define R_IRQ_MASK1_RD__pa5__active 1 +#define R_IRQ_MASK1_RD__pa5__inactive 0 +#define R_IRQ_MASK1_RD__pa4__BITNR 4 +#define R_IRQ_MASK1_RD__pa4__WIDTH 1 +#define R_IRQ_MASK1_RD__pa4__active 1 +#define R_IRQ_MASK1_RD__pa4__inactive 0 +#define R_IRQ_MASK1_RD__pa3__BITNR 3 +#define R_IRQ_MASK1_RD__pa3__WIDTH 1 +#define R_IRQ_MASK1_RD__pa3__active 1 +#define R_IRQ_MASK1_RD__pa3__inactive 0 +#define R_IRQ_MASK1_RD__pa2__BITNR 2 +#define R_IRQ_MASK1_RD__pa2__WIDTH 1 +#define R_IRQ_MASK1_RD__pa2__active 1 +#define R_IRQ_MASK1_RD__pa2__inactive 0 +#define R_IRQ_MASK1_RD__pa1__BITNR 1 +#define R_IRQ_MASK1_RD__pa1__WIDTH 1 +#define R_IRQ_MASK1_RD__pa1__active 1 +#define R_IRQ_MASK1_RD__pa1__inactive 0 +#define R_IRQ_MASK1_RD__pa0__BITNR 0 +#define R_IRQ_MASK1_RD__pa0__WIDTH 1 +#define R_IRQ_MASK1_RD__pa0__active 1 +#define R_IRQ_MASK1_RD__pa0__inactive 0 + +#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8) +#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31 +#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int7__clr 1 +#define R_IRQ_MASK1_CLR__sw_int7__nop 0 +#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30 +#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int6__clr 1 +#define R_IRQ_MASK1_CLR__sw_int6__nop 0 +#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29 +#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int5__clr 1 +#define R_IRQ_MASK1_CLR__sw_int5__nop 0 +#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28 +#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int4__clr 1 +#define R_IRQ_MASK1_CLR__sw_int4__nop 0 +#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27 +#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int3__clr 1 +#define R_IRQ_MASK1_CLR__sw_int3__nop 0 +#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26 +#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int2__clr 1 +#define R_IRQ_MASK1_CLR__sw_int2__nop 0 +#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25 +#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int1__clr 1 +#define R_IRQ_MASK1_CLR__sw_int1__nop 0 +#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24 +#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_CLR__sw_int0__clr 1 +#define R_IRQ_MASK1_CLR__sw_int0__nop 0 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1 +#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18 +#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_peri__clr 1 +#define R_IRQ_MASK1_CLR__par1_peri__nop 0 +#define R_IRQ_MASK1_CLR__par1_data__BITNR 17 +#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_data__clr 1 +#define R_IRQ_MASK1_CLR__par1_data__nop 0 +#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16 +#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__par1_ready__clr 1 +#define R_IRQ_MASK1_CLR__par1_ready__nop 0 +#define R_IRQ_MASK1_CLR__scsi1__BITNR 16 +#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1 +#define R_IRQ_MASK1_CLR__scsi1__clr 1 +#define R_IRQ_MASK1_CLR__scsi1__nop 0 +#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser3_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14 +#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser3_data__clr 1 +#define R_IRQ_MASK1_CLR__ser3_data__nop 0 +#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser2_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12 +#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser2_data__clr 1 +#define R_IRQ_MASK1_CLR__ser2_data__nop 0 +#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser1_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10 +#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser1_data__clr 1 +#define R_IRQ_MASK1_CLR__ser1_data__nop 0 +#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_ready__clr 1 +#define R_IRQ_MASK1_CLR__ser0_ready__nop 0 +#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8 +#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_CLR__ser0_data__clr 1 +#define R_IRQ_MASK1_CLR__ser0_data__nop 0 +#define R_IRQ_MASK1_CLR__pa7__BITNR 7 +#define R_IRQ_MASK1_CLR__pa7__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa7__clr 1 +#define R_IRQ_MASK1_CLR__pa7__nop 0 +#define R_IRQ_MASK1_CLR__pa6__BITNR 6 +#define R_IRQ_MASK1_CLR__pa6__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa6__clr 1 +#define R_IRQ_MASK1_CLR__pa6__nop 0 +#define R_IRQ_MASK1_CLR__pa5__BITNR 5 +#define R_IRQ_MASK1_CLR__pa5__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa5__clr 1 +#define R_IRQ_MASK1_CLR__pa5__nop 0 +#define R_IRQ_MASK1_CLR__pa4__BITNR 4 +#define R_IRQ_MASK1_CLR__pa4__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa4__clr 1 +#define R_IRQ_MASK1_CLR__pa4__nop 0 +#define R_IRQ_MASK1_CLR__pa3__BITNR 3 +#define R_IRQ_MASK1_CLR__pa3__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa3__clr 1 +#define R_IRQ_MASK1_CLR__pa3__nop 0 +#define R_IRQ_MASK1_CLR__pa2__BITNR 2 +#define R_IRQ_MASK1_CLR__pa2__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa2__clr 1 +#define R_IRQ_MASK1_CLR__pa2__nop 0 +#define R_IRQ_MASK1_CLR__pa1__BITNR 1 +#define R_IRQ_MASK1_CLR__pa1__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa1__clr 1 +#define R_IRQ_MASK1_CLR__pa1__nop 0 +#define R_IRQ_MASK1_CLR__pa0__BITNR 0 +#define R_IRQ_MASK1_CLR__pa0__WIDTH 1 +#define R_IRQ_MASK1_CLR__pa0__clr 1 +#define R_IRQ_MASK1_CLR__pa0__nop 0 + +#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc) +#define R_IRQ_READ1__sw_int7__BITNR 31 +#define R_IRQ_READ1__sw_int7__WIDTH 1 +#define R_IRQ_READ1__sw_int7__active 1 +#define R_IRQ_READ1__sw_int7__inactive 0 +#define R_IRQ_READ1__sw_int6__BITNR 30 +#define R_IRQ_READ1__sw_int6__WIDTH 1 +#define R_IRQ_READ1__sw_int6__active 1 +#define R_IRQ_READ1__sw_int6__inactive 0 +#define R_IRQ_READ1__sw_int5__BITNR 29 +#define R_IRQ_READ1__sw_int5__WIDTH 1 +#define R_IRQ_READ1__sw_int5__active 1 +#define R_IRQ_READ1__sw_int5__inactive 0 +#define R_IRQ_READ1__sw_int4__BITNR 28 +#define R_IRQ_READ1__sw_int4__WIDTH 1 +#define R_IRQ_READ1__sw_int4__active 1 +#define R_IRQ_READ1__sw_int4__inactive 0 +#define R_IRQ_READ1__sw_int3__BITNR 27 +#define R_IRQ_READ1__sw_int3__WIDTH 1 +#define R_IRQ_READ1__sw_int3__active 1 +#define R_IRQ_READ1__sw_int3__inactive 0 +#define R_IRQ_READ1__sw_int2__BITNR 26 +#define R_IRQ_READ1__sw_int2__WIDTH 1 +#define R_IRQ_READ1__sw_int2__active 1 +#define R_IRQ_READ1__sw_int2__inactive 0 +#define R_IRQ_READ1__sw_int1__BITNR 25 +#define R_IRQ_READ1__sw_int1__WIDTH 1 +#define R_IRQ_READ1__sw_int1__active 1 +#define R_IRQ_READ1__sw_int1__inactive 0 +#define R_IRQ_READ1__sw_int0__BITNR 24 +#define R_IRQ_READ1__sw_int0__WIDTH 1 +#define R_IRQ_READ1__sw_int0__active 1 +#define R_IRQ_READ1__sw_int0__inactive 0 +#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19 +#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_READ1__par1_ecp_cmd__active 1 +#define R_IRQ_READ1__par1_ecp_cmd__inactive 0 +#define R_IRQ_READ1__par1_peri__BITNR 18 +#define R_IRQ_READ1__par1_peri__WIDTH 1 +#define R_IRQ_READ1__par1_peri__active 1 +#define R_IRQ_READ1__par1_peri__inactive 0 +#define R_IRQ_READ1__par1_data__BITNR 17 +#define R_IRQ_READ1__par1_data__WIDTH 1 +#define R_IRQ_READ1__par1_data__active 1 +#define R_IRQ_READ1__par1_data__inactive 0 +#define R_IRQ_READ1__par1_ready__BITNR 16 +#define R_IRQ_READ1__par1_ready__WIDTH 1 +#define R_IRQ_READ1__par1_ready__active 1 +#define R_IRQ_READ1__par1_ready__inactive 0 +#define R_IRQ_READ1__scsi1__BITNR 16 +#define R_IRQ_READ1__scsi1__WIDTH 1 +#define R_IRQ_READ1__scsi1__active 1 +#define R_IRQ_READ1__scsi1__inactive 0 +#define R_IRQ_READ1__ser3_ready__BITNR 15 +#define R_IRQ_READ1__ser3_ready__WIDTH 1 +#define R_IRQ_READ1__ser3_ready__active 1 +#define R_IRQ_READ1__ser3_ready__inactive 0 +#define R_IRQ_READ1__ser3_data__BITNR 14 +#define R_IRQ_READ1__ser3_data__WIDTH 1 +#define R_IRQ_READ1__ser3_data__active 1 +#define R_IRQ_READ1__ser3_data__inactive 0 +#define R_IRQ_READ1__ser2_ready__BITNR 13 +#define R_IRQ_READ1__ser2_ready__WIDTH 1 +#define R_IRQ_READ1__ser2_ready__active 1 +#define R_IRQ_READ1__ser2_ready__inactive 0 +#define R_IRQ_READ1__ser2_data__BITNR 12 +#define R_IRQ_READ1__ser2_data__WIDTH 1 +#define R_IRQ_READ1__ser2_data__active 1 +#define R_IRQ_READ1__ser2_data__inactive 0 +#define R_IRQ_READ1__ser1_ready__BITNR 11 +#define R_IRQ_READ1__ser1_ready__WIDTH 1 +#define R_IRQ_READ1__ser1_ready__active 1 +#define R_IRQ_READ1__ser1_ready__inactive 0 +#define R_IRQ_READ1__ser1_data__BITNR 10 +#define R_IRQ_READ1__ser1_data__WIDTH 1 +#define R_IRQ_READ1__ser1_data__active 1 +#define R_IRQ_READ1__ser1_data__inactive 0 +#define R_IRQ_READ1__ser0_ready__BITNR 9 +#define R_IRQ_READ1__ser0_ready__WIDTH 1 +#define R_IRQ_READ1__ser0_ready__active 1 +#define R_IRQ_READ1__ser0_ready__inactive 0 +#define R_IRQ_READ1__ser0_data__BITNR 8 +#define R_IRQ_READ1__ser0_data__WIDTH 1 +#define R_IRQ_READ1__ser0_data__active 1 +#define R_IRQ_READ1__ser0_data__inactive 0 +#define R_IRQ_READ1__pa7__BITNR 7 +#define R_IRQ_READ1__pa7__WIDTH 1 +#define R_IRQ_READ1__pa7__active 1 +#define R_IRQ_READ1__pa7__inactive 0 +#define R_IRQ_READ1__pa6__BITNR 6 +#define R_IRQ_READ1__pa6__WIDTH 1 +#define R_IRQ_READ1__pa6__active 1 +#define R_IRQ_READ1__pa6__inactive 0 +#define R_IRQ_READ1__pa5__BITNR 5 +#define R_IRQ_READ1__pa5__WIDTH 1 +#define R_IRQ_READ1__pa5__active 1 +#define R_IRQ_READ1__pa5__inactive 0 +#define R_IRQ_READ1__pa4__BITNR 4 +#define R_IRQ_READ1__pa4__WIDTH 1 +#define R_IRQ_READ1__pa4__active 1 +#define R_IRQ_READ1__pa4__inactive 0 +#define R_IRQ_READ1__pa3__BITNR 3 +#define R_IRQ_READ1__pa3__WIDTH 1 +#define R_IRQ_READ1__pa3__active 1 +#define R_IRQ_READ1__pa3__inactive 0 +#define R_IRQ_READ1__pa2__BITNR 2 +#define R_IRQ_READ1__pa2__WIDTH 1 +#define R_IRQ_READ1__pa2__active 1 +#define R_IRQ_READ1__pa2__inactive 0 +#define R_IRQ_READ1__pa1__BITNR 1 +#define R_IRQ_READ1__pa1__WIDTH 1 +#define R_IRQ_READ1__pa1__active 1 +#define R_IRQ_READ1__pa1__inactive 0 +#define R_IRQ_READ1__pa0__BITNR 0 +#define R_IRQ_READ1__pa0__WIDTH 1 +#define R_IRQ_READ1__pa0__active 1 +#define R_IRQ_READ1__pa0__inactive 0 + +#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc) +#define R_IRQ_MASK1_SET__sw_int7__BITNR 31 +#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int7__set 1 +#define R_IRQ_MASK1_SET__sw_int7__nop 0 +#define R_IRQ_MASK1_SET__sw_int6__BITNR 30 +#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int6__set 1 +#define R_IRQ_MASK1_SET__sw_int6__nop 0 +#define R_IRQ_MASK1_SET__sw_int5__BITNR 29 +#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int5__set 1 +#define R_IRQ_MASK1_SET__sw_int5__nop 0 +#define R_IRQ_MASK1_SET__sw_int4__BITNR 28 +#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int4__set 1 +#define R_IRQ_MASK1_SET__sw_int4__nop 0 +#define R_IRQ_MASK1_SET__sw_int3__BITNR 27 +#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int3__set 1 +#define R_IRQ_MASK1_SET__sw_int3__nop 0 +#define R_IRQ_MASK1_SET__sw_int2__BITNR 26 +#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int2__set 1 +#define R_IRQ_MASK1_SET__sw_int2__nop 0 +#define R_IRQ_MASK1_SET__sw_int1__BITNR 25 +#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int1__set 1 +#define R_IRQ_MASK1_SET__sw_int1__nop 0 +#define R_IRQ_MASK1_SET__sw_int0__BITNR 24 +#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1 +#define R_IRQ_MASK1_SET__sw_int0__set 1 +#define R_IRQ_MASK1_SET__sw_int0__nop 0 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1 +#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0 +#define R_IRQ_MASK1_SET__par1_peri__BITNR 18 +#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_peri__set 1 +#define R_IRQ_MASK1_SET__par1_peri__nop 0 +#define R_IRQ_MASK1_SET__par1_data__BITNR 17 +#define R_IRQ_MASK1_SET__par1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_data__set 1 +#define R_IRQ_MASK1_SET__par1_data__nop 0 +#define R_IRQ_MASK1_SET__par1_ready__BITNR 16 +#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__par1_ready__set 1 +#define R_IRQ_MASK1_SET__par1_ready__nop 0 +#define R_IRQ_MASK1_SET__scsi1__BITNR 16 +#define R_IRQ_MASK1_SET__scsi1__WIDTH 1 +#define R_IRQ_MASK1_SET__scsi1__set 1 +#define R_IRQ_MASK1_SET__scsi1__nop 0 +#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15 +#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_ready__set 1 +#define R_IRQ_MASK1_SET__ser3_ready__nop 0 +#define R_IRQ_MASK1_SET__ser3_data__BITNR 14 +#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser3_data__set 1 +#define R_IRQ_MASK1_SET__ser3_data__nop 0 +#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13 +#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_ready__set 1 +#define R_IRQ_MASK1_SET__ser2_ready__nop 0 +#define R_IRQ_MASK1_SET__ser2_data__BITNR 12 +#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser2_data__set 1 +#define R_IRQ_MASK1_SET__ser2_data__nop 0 +#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11 +#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_ready__set 1 +#define R_IRQ_MASK1_SET__ser1_ready__nop 0 +#define R_IRQ_MASK1_SET__ser1_data__BITNR 10 +#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser1_data__set 1 +#define R_IRQ_MASK1_SET__ser1_data__nop 0 +#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9 +#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_ready__set 1 +#define R_IRQ_MASK1_SET__ser0_ready__nop 0 +#define R_IRQ_MASK1_SET__ser0_data__BITNR 8 +#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1 +#define R_IRQ_MASK1_SET__ser0_data__set 1 +#define R_IRQ_MASK1_SET__ser0_data__nop 0 +#define R_IRQ_MASK1_SET__pa7__BITNR 7 +#define R_IRQ_MASK1_SET__pa7__WIDTH 1 +#define R_IRQ_MASK1_SET__pa7__set 1 +#define R_IRQ_MASK1_SET__pa7__nop 0 +#define R_IRQ_MASK1_SET__pa6__BITNR 6 +#define R_IRQ_MASK1_SET__pa6__WIDTH 1 +#define R_IRQ_MASK1_SET__pa6__set 1 +#define R_IRQ_MASK1_SET__pa6__nop 0 +#define R_IRQ_MASK1_SET__pa5__BITNR 5 +#define R_IRQ_MASK1_SET__pa5__WIDTH 1 +#define R_IRQ_MASK1_SET__pa5__set 1 +#define R_IRQ_MASK1_SET__pa5__nop 0 +#define R_IRQ_MASK1_SET__pa4__BITNR 4 +#define R_IRQ_MASK1_SET__pa4__WIDTH 1 +#define R_IRQ_MASK1_SET__pa4__set 1 +#define R_IRQ_MASK1_SET__pa4__nop 0 +#define R_IRQ_MASK1_SET__pa3__BITNR 3 +#define R_IRQ_MASK1_SET__pa3__WIDTH 1 +#define R_IRQ_MASK1_SET__pa3__set 1 +#define R_IRQ_MASK1_SET__pa3__nop 0 +#define R_IRQ_MASK1_SET__pa2__BITNR 2 +#define R_IRQ_MASK1_SET__pa2__WIDTH 1 +#define R_IRQ_MASK1_SET__pa2__set 1 +#define R_IRQ_MASK1_SET__pa2__nop 0 +#define R_IRQ_MASK1_SET__pa1__BITNR 1 +#define R_IRQ_MASK1_SET__pa1__WIDTH 1 +#define R_IRQ_MASK1_SET__pa1__set 1 +#define R_IRQ_MASK1_SET__pa1__nop 0 +#define R_IRQ_MASK1_SET__pa0__BITNR 0 +#define R_IRQ_MASK1_SET__pa0__WIDTH 1 +#define R_IRQ_MASK1_SET__pa0__set 1 +#define R_IRQ_MASK1_SET__pa0__nop 0 + +#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_eop__active 1 +#define R_IRQ_MASK2_RD__dma9_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma9_descr__active 1 +#define R_IRQ_MASK2_RD__dma9_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_eop__active 1 +#define R_IRQ_MASK2_RD__dma8_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma8_descr__active 1 +#define R_IRQ_MASK2_RD__dma8_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_eop__active 1 +#define R_IRQ_MASK2_RD__dma7_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma7_descr__active 1 +#define R_IRQ_MASK2_RD__dma7_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_eop__active 1 +#define R_IRQ_MASK2_RD__dma6_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma6_descr__active 1 +#define R_IRQ_MASK2_RD__dma6_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_eop__active 1 +#define R_IRQ_MASK2_RD__dma5_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma5_descr__active 1 +#define R_IRQ_MASK2_RD__dma5_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_eop__active 1 +#define R_IRQ_MASK2_RD__dma4_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma4_descr__active 1 +#define R_IRQ_MASK2_RD__dma4_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_eop__active 1 +#define R_IRQ_MASK2_RD__dma3_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma3_descr__active 1 +#define R_IRQ_MASK2_RD__dma3_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_eop__active 1 +#define R_IRQ_MASK2_RD__dma2_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma2_descr__active 1 +#define R_IRQ_MASK2_RD__dma2_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_eop__active 1 +#define R_IRQ_MASK2_RD__dma1_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma1_descr__active 1 +#define R_IRQ_MASK2_RD__dma1_descr__inactive 0 +#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_eop__active 1 +#define R_IRQ_MASK2_RD__dma0_eop__inactive 0 +#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_RD__dma0_descr__active 1 +#define R_IRQ_MASK2_RD__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0) +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma9_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma9_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma9_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma8_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma8_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma8_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma7_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma7_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma7_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma6_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma6_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma6_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma5_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma5_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma5_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma4_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma4_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma4_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma3_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma3_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma3_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma2_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma2_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma2_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma1_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma1_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma1_descr__nop 0 +#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_eop__clr 1 +#define R_IRQ_MASK2_CLR__dma0_eop__nop 0 +#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_CLR__dma0_descr__clr 1 +#define R_IRQ_MASK2_CLR__dma0_descr__nop 0 + +#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4) +#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23 +#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub3_descr__active 1 +#define R_IRQ_READ2__dma8_sub3_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22 +#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub2_descr__active 1 +#define R_IRQ_READ2__dma8_sub2_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21 +#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub1_descr__active 1 +#define R_IRQ_READ2__dma8_sub1_descr__inactive 0 +#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20 +#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_sub0_descr__active 1 +#define R_IRQ_READ2__dma8_sub0_descr__inactive 0 +#define R_IRQ_READ2__dma9_eop__BITNR 19 +#define R_IRQ_READ2__dma9_eop__WIDTH 1 +#define R_IRQ_READ2__dma9_eop__active 1 +#define R_IRQ_READ2__dma9_eop__inactive 0 +#define R_IRQ_READ2__dma9_descr__BITNR 18 +#define R_IRQ_READ2__dma9_descr__WIDTH 1 +#define R_IRQ_READ2__dma9_descr__active 1 +#define R_IRQ_READ2__dma9_descr__inactive 0 +#define R_IRQ_READ2__dma8_eop__BITNR 17 +#define R_IRQ_READ2__dma8_eop__WIDTH 1 +#define R_IRQ_READ2__dma8_eop__active 1 +#define R_IRQ_READ2__dma8_eop__inactive 0 +#define R_IRQ_READ2__dma8_descr__BITNR 16 +#define R_IRQ_READ2__dma8_descr__WIDTH 1 +#define R_IRQ_READ2__dma8_descr__active 1 +#define R_IRQ_READ2__dma8_descr__inactive 0 +#define R_IRQ_READ2__dma7_eop__BITNR 15 +#define R_IRQ_READ2__dma7_eop__WIDTH 1 +#define R_IRQ_READ2__dma7_eop__active 1 +#define R_IRQ_READ2__dma7_eop__inactive 0 +#define R_IRQ_READ2__dma7_descr__BITNR 14 +#define R_IRQ_READ2__dma7_descr__WIDTH 1 +#define R_IRQ_READ2__dma7_descr__active 1 +#define R_IRQ_READ2__dma7_descr__inactive 0 +#define R_IRQ_READ2__dma6_eop__BITNR 13 +#define R_IRQ_READ2__dma6_eop__WIDTH 1 +#define R_IRQ_READ2__dma6_eop__active 1 +#define R_IRQ_READ2__dma6_eop__inactive 0 +#define R_IRQ_READ2__dma6_descr__BITNR 12 +#define R_IRQ_READ2__dma6_descr__WIDTH 1 +#define R_IRQ_READ2__dma6_descr__active 1 +#define R_IRQ_READ2__dma6_descr__inactive 0 +#define R_IRQ_READ2__dma5_eop__BITNR 11 +#define R_IRQ_READ2__dma5_eop__WIDTH 1 +#define R_IRQ_READ2__dma5_eop__active 1 +#define R_IRQ_READ2__dma5_eop__inactive 0 +#define R_IRQ_READ2__dma5_descr__BITNR 10 +#define R_IRQ_READ2__dma5_descr__WIDTH 1 +#define R_IRQ_READ2__dma5_descr__active 1 +#define R_IRQ_READ2__dma5_descr__inactive 0 +#define R_IRQ_READ2__dma4_eop__BITNR 9 +#define R_IRQ_READ2__dma4_eop__WIDTH 1 +#define R_IRQ_READ2__dma4_eop__active 1 +#define R_IRQ_READ2__dma4_eop__inactive 0 +#define R_IRQ_READ2__dma4_descr__BITNR 8 +#define R_IRQ_READ2__dma4_descr__WIDTH 1 +#define R_IRQ_READ2__dma4_descr__active 1 +#define R_IRQ_READ2__dma4_descr__inactive 0 +#define R_IRQ_READ2__dma3_eop__BITNR 7 +#define R_IRQ_READ2__dma3_eop__WIDTH 1 +#define R_IRQ_READ2__dma3_eop__active 1 +#define R_IRQ_READ2__dma3_eop__inactive 0 +#define R_IRQ_READ2__dma3_descr__BITNR 6 +#define R_IRQ_READ2__dma3_descr__WIDTH 1 +#define R_IRQ_READ2__dma3_descr__active 1 +#define R_IRQ_READ2__dma3_descr__inactive 0 +#define R_IRQ_READ2__dma2_eop__BITNR 5 +#define R_IRQ_READ2__dma2_eop__WIDTH 1 +#define R_IRQ_READ2__dma2_eop__active 1 +#define R_IRQ_READ2__dma2_eop__inactive 0 +#define R_IRQ_READ2__dma2_descr__BITNR 4 +#define R_IRQ_READ2__dma2_descr__WIDTH 1 +#define R_IRQ_READ2__dma2_descr__active 1 +#define R_IRQ_READ2__dma2_descr__inactive 0 +#define R_IRQ_READ2__dma1_eop__BITNR 3 +#define R_IRQ_READ2__dma1_eop__WIDTH 1 +#define R_IRQ_READ2__dma1_eop__active 1 +#define R_IRQ_READ2__dma1_eop__inactive 0 +#define R_IRQ_READ2__dma1_descr__BITNR 2 +#define R_IRQ_READ2__dma1_descr__WIDTH 1 +#define R_IRQ_READ2__dma1_descr__active 1 +#define R_IRQ_READ2__dma1_descr__inactive 0 +#define R_IRQ_READ2__dma0_eop__BITNR 1 +#define R_IRQ_READ2__dma0_eop__WIDTH 1 +#define R_IRQ_READ2__dma0_eop__active 1 +#define R_IRQ_READ2__dma0_eop__inactive 0 +#define R_IRQ_READ2__dma0_descr__BITNR 0 +#define R_IRQ_READ2__dma0_descr__WIDTH 1 +#define R_IRQ_READ2__dma0_descr__active 1 +#define R_IRQ_READ2__dma0_descr__inactive 0 + +#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4) +#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0 +#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19 +#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_eop__set 1 +#define R_IRQ_MASK2_SET__dma9_eop__nop 0 +#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18 +#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma9_descr__set 1 +#define R_IRQ_MASK2_SET__dma9_descr__nop 0 +#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17 +#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_eop__set 1 +#define R_IRQ_MASK2_SET__dma8_eop__nop 0 +#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16 +#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma8_descr__set 1 +#define R_IRQ_MASK2_SET__dma8_descr__nop 0 +#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15 +#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_eop__set 1 +#define R_IRQ_MASK2_SET__dma7_eop__nop 0 +#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14 +#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma7_descr__set 1 +#define R_IRQ_MASK2_SET__dma7_descr__nop 0 +#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13 +#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_eop__set 1 +#define R_IRQ_MASK2_SET__dma6_eop__nop 0 +#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12 +#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma6_descr__set 1 +#define R_IRQ_MASK2_SET__dma6_descr__nop 0 +#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11 +#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_eop__set 1 +#define R_IRQ_MASK2_SET__dma5_eop__nop 0 +#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10 +#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma5_descr__set 1 +#define R_IRQ_MASK2_SET__dma5_descr__nop 0 +#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9 +#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_eop__set 1 +#define R_IRQ_MASK2_SET__dma4_eop__nop 0 +#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8 +#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma4_descr__set 1 +#define R_IRQ_MASK2_SET__dma4_descr__nop 0 +#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7 +#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_eop__set 1 +#define R_IRQ_MASK2_SET__dma3_eop__nop 0 +#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6 +#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma3_descr__set 1 +#define R_IRQ_MASK2_SET__dma3_descr__nop 0 +#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5 +#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_eop__set 1 +#define R_IRQ_MASK2_SET__dma2_eop__nop 0 +#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4 +#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma2_descr__set 1 +#define R_IRQ_MASK2_SET__dma2_descr__nop 0 +#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3 +#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_eop__set 1 +#define R_IRQ_MASK2_SET__dma1_eop__nop 0 +#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2 +#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma1_descr__set 1 +#define R_IRQ_MASK2_SET__dma1_descr__nop 0 +#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1 +#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_eop__set 1 +#define R_IRQ_MASK2_SET__dma0_eop__nop 0 +#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0 +#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1 +#define R_IRQ_MASK2_SET__dma0_descr__set 1 +#define R_IRQ_MASK2_SET__dma0_descr__nop 0 + +#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8) +#define R_VECT_MASK_RD__usb__BITNR 31 +#define R_VECT_MASK_RD__usb__WIDTH 1 +#define R_VECT_MASK_RD__usb__active 1 +#define R_VECT_MASK_RD__usb__inactive 0 +#define R_VECT_MASK_RD__dma9__BITNR 25 +#define R_VECT_MASK_RD__dma9__WIDTH 1 +#define R_VECT_MASK_RD__dma9__active 1 +#define R_VECT_MASK_RD__dma9__inactive 0 +#define R_VECT_MASK_RD__dma8__BITNR 24 +#define R_VECT_MASK_RD__dma8__WIDTH 1 +#define R_VECT_MASK_RD__dma8__active 1 +#define R_VECT_MASK_RD__dma8__inactive 0 +#define R_VECT_MASK_RD__dma7__BITNR 23 +#define R_VECT_MASK_RD__dma7__WIDTH 1 +#define R_VECT_MASK_RD__dma7__active 1 +#define R_VECT_MASK_RD__dma7__inactive 0 +#define R_VECT_MASK_RD__dma6__BITNR 22 +#define R_VECT_MASK_RD__dma6__WIDTH 1 +#define R_VECT_MASK_RD__dma6__active 1 +#define R_VECT_MASK_RD__dma6__inactive 0 +#define R_VECT_MASK_RD__dma5__BITNR 21 +#define R_VECT_MASK_RD__dma5__WIDTH 1 +#define R_VECT_MASK_RD__dma5__active 1 +#define R_VECT_MASK_RD__dma5__inactive 0 +#define R_VECT_MASK_RD__dma4__BITNR 20 +#define R_VECT_MASK_RD__dma4__WIDTH 1 +#define R_VECT_MASK_RD__dma4__active 1 +#define R_VECT_MASK_RD__dma4__inactive 0 +#define R_VECT_MASK_RD__dma3__BITNR 19 +#define R_VECT_MASK_RD__dma3__WIDTH 1 +#define R_VECT_MASK_RD__dma3__active 1 +#define R_VECT_MASK_RD__dma3__inactive 0 +#define R_VECT_MASK_RD__dma2__BITNR 18 +#define R_VECT_MASK_RD__dma2__WIDTH 1 +#define R_VECT_MASK_RD__dma2__active 1 +#define R_VECT_MASK_RD__dma2__inactive 0 +#define R_VECT_MASK_RD__dma1__BITNR 17 +#define R_VECT_MASK_RD__dma1__WIDTH 1 +#define R_VECT_MASK_RD__dma1__active 1 +#define R_VECT_MASK_RD__dma1__inactive 0 +#define R_VECT_MASK_RD__dma0__BITNR 16 +#define R_VECT_MASK_RD__dma0__WIDTH 1 +#define R_VECT_MASK_RD__dma0__active 1 +#define R_VECT_MASK_RD__dma0__inactive 0 +#define R_VECT_MASK_RD__ext_dma1__BITNR 13 +#define R_VECT_MASK_RD__ext_dma1__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma1__active 1 +#define R_VECT_MASK_RD__ext_dma1__inactive 0 +#define R_VECT_MASK_RD__ext_dma0__BITNR 12 +#define R_VECT_MASK_RD__ext_dma0__WIDTH 1 +#define R_VECT_MASK_RD__ext_dma0__active 1 +#define R_VECT_MASK_RD__ext_dma0__inactive 0 +#define R_VECT_MASK_RD__pa__BITNR 11 +#define R_VECT_MASK_RD__pa__WIDTH 1 +#define R_VECT_MASK_RD__pa__active 1 +#define R_VECT_MASK_RD__pa__inactive 0 +#define R_VECT_MASK_RD__irq_intnr__BITNR 10 +#define R_VECT_MASK_RD__irq_intnr__WIDTH 1 +#define R_VECT_MASK_RD__irq_intnr__active 1 +#define R_VECT_MASK_RD__irq_intnr__inactive 0 +#define R_VECT_MASK_RD__sw__BITNR 9 +#define R_VECT_MASK_RD__sw__WIDTH 1 +#define R_VECT_MASK_RD__sw__active 1 +#define R_VECT_MASK_RD__sw__inactive 0 +#define R_VECT_MASK_RD__serial__BITNR 8 +#define R_VECT_MASK_RD__serial__WIDTH 1 +#define R_VECT_MASK_RD__serial__active 1 +#define R_VECT_MASK_RD__serial__inactive 0 +#define R_VECT_MASK_RD__snmp__BITNR 7 +#define R_VECT_MASK_RD__snmp__WIDTH 1 +#define R_VECT_MASK_RD__snmp__active 1 +#define R_VECT_MASK_RD__snmp__inactive 0 +#define R_VECT_MASK_RD__network__BITNR 6 +#define R_VECT_MASK_RD__network__WIDTH 1 +#define R_VECT_MASK_RD__network__active 1 +#define R_VECT_MASK_RD__network__inactive 0 +#define R_VECT_MASK_RD__scsi1__BITNR 5 +#define R_VECT_MASK_RD__scsi1__WIDTH 1 +#define R_VECT_MASK_RD__scsi1__active 1 +#define R_VECT_MASK_RD__scsi1__inactive 0 +#define R_VECT_MASK_RD__par1__BITNR 5 +#define R_VECT_MASK_RD__par1__WIDTH 1 +#define R_VECT_MASK_RD__par1__active 1 +#define R_VECT_MASK_RD__par1__inactive 0 +#define R_VECT_MASK_RD__scsi0__BITNR 4 +#define R_VECT_MASK_RD__scsi0__WIDTH 1 +#define R_VECT_MASK_RD__scsi0__active 1 +#define R_VECT_MASK_RD__scsi0__inactive 0 +#define R_VECT_MASK_RD__par0__BITNR 4 +#define R_VECT_MASK_RD__par0__WIDTH 1 +#define R_VECT_MASK_RD__par0__active 1 +#define R_VECT_MASK_RD__par0__inactive 0 +#define R_VECT_MASK_RD__ata__BITNR 4 +#define R_VECT_MASK_RD__ata__WIDTH 1 +#define R_VECT_MASK_RD__ata__active 1 +#define R_VECT_MASK_RD__ata__inactive 0 +#define R_VECT_MASK_RD__mio__BITNR 4 +#define R_VECT_MASK_RD__mio__WIDTH 1 +#define R_VECT_MASK_RD__mio__active 1 +#define R_VECT_MASK_RD__mio__inactive 0 +#define R_VECT_MASK_RD__timer1__BITNR 3 +#define R_VECT_MASK_RD__timer1__WIDTH 1 +#define R_VECT_MASK_RD__timer1__active 1 +#define R_VECT_MASK_RD__timer1__inactive 0 +#define R_VECT_MASK_RD__timer0__BITNR 2 +#define R_VECT_MASK_RD__timer0__WIDTH 1 +#define R_VECT_MASK_RD__timer0__active 1 +#define R_VECT_MASK_RD__timer0__inactive 0 +#define R_VECT_MASK_RD__nmi__BITNR 1 +#define R_VECT_MASK_RD__nmi__WIDTH 1 +#define R_VECT_MASK_RD__nmi__active 1 +#define R_VECT_MASK_RD__nmi__inactive 0 +#define R_VECT_MASK_RD__some__BITNR 0 +#define R_VECT_MASK_RD__some__WIDTH 1 +#define R_VECT_MASK_RD__some__active 1 +#define R_VECT_MASK_RD__some__inactive 0 + +#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8) +#define R_VECT_MASK_CLR__usb__BITNR 31 +#define R_VECT_MASK_CLR__usb__WIDTH 1 +#define R_VECT_MASK_CLR__usb__clr 1 +#define R_VECT_MASK_CLR__usb__nop 0 +#define R_VECT_MASK_CLR__dma9__BITNR 25 +#define R_VECT_MASK_CLR__dma9__WIDTH 1 +#define R_VECT_MASK_CLR__dma9__clr 1 +#define R_VECT_MASK_CLR__dma9__nop 0 +#define R_VECT_MASK_CLR__dma8__BITNR 24 +#define R_VECT_MASK_CLR__dma8__WIDTH 1 +#define R_VECT_MASK_CLR__dma8__clr 1 +#define R_VECT_MASK_CLR__dma8__nop 0 +#define R_VECT_MASK_CLR__dma7__BITNR 23 +#define R_VECT_MASK_CLR__dma7__WIDTH 1 +#define R_VECT_MASK_CLR__dma7__clr 1 +#define R_VECT_MASK_CLR__dma7__nop 0 +#define R_VECT_MASK_CLR__dma6__BITNR 22 +#define R_VECT_MASK_CLR__dma6__WIDTH 1 +#define R_VECT_MASK_CLR__dma6__clr 1 +#define R_VECT_MASK_CLR__dma6__nop 0 +#define R_VECT_MASK_CLR__dma5__BITNR 21 +#define R_VECT_MASK_CLR__dma5__WIDTH 1 +#define R_VECT_MASK_CLR__dma5__clr 1 +#define R_VECT_MASK_CLR__dma5__nop 0 +#define R_VECT_MASK_CLR__dma4__BITNR 20 +#define R_VECT_MASK_CLR__dma4__WIDTH 1 +#define R_VECT_MASK_CLR__dma4__clr 1 +#define R_VECT_MASK_CLR__dma4__nop 0 +#define R_VECT_MASK_CLR__dma3__BITNR 19 +#define R_VECT_MASK_CLR__dma3__WIDTH 1 +#define R_VECT_MASK_CLR__dma3__clr 1 +#define R_VECT_MASK_CLR__dma3__nop 0 +#define R_VECT_MASK_CLR__dma2__BITNR 18 +#define R_VECT_MASK_CLR__dma2__WIDTH 1 +#define R_VECT_MASK_CLR__dma2__clr 1 +#define R_VECT_MASK_CLR__dma2__nop 0 +#define R_VECT_MASK_CLR__dma1__BITNR 17 +#define R_VECT_MASK_CLR__dma1__WIDTH 1 +#define R_VECT_MASK_CLR__dma1__clr 1 +#define R_VECT_MASK_CLR__dma1__nop 0 +#define R_VECT_MASK_CLR__dma0__BITNR 16 +#define R_VECT_MASK_CLR__dma0__WIDTH 1 +#define R_VECT_MASK_CLR__dma0__clr 1 +#define R_VECT_MASK_CLR__dma0__nop 0 +#define R_VECT_MASK_CLR__ext_dma1__BITNR 13 +#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma1__clr 1 +#define R_VECT_MASK_CLR__ext_dma1__nop 0 +#define R_VECT_MASK_CLR__ext_dma0__BITNR 12 +#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1 +#define R_VECT_MASK_CLR__ext_dma0__clr 1 +#define R_VECT_MASK_CLR__ext_dma0__nop 0 +#define R_VECT_MASK_CLR__pa__BITNR 11 +#define R_VECT_MASK_CLR__pa__WIDTH 1 +#define R_VECT_MASK_CLR__pa__clr 1 +#define R_VECT_MASK_CLR__pa__nop 0 +#define R_VECT_MASK_CLR__irq_intnr__BITNR 10 +#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1 +#define R_VECT_MASK_CLR__irq_intnr__clr 1 +#define R_VECT_MASK_CLR__irq_intnr__nop 0 +#define R_VECT_MASK_CLR__sw__BITNR 9 +#define R_VECT_MASK_CLR__sw__WIDTH 1 +#define R_VECT_MASK_CLR__sw__clr 1 +#define R_VECT_MASK_CLR__sw__nop 0 +#define R_VECT_MASK_CLR__serial__BITNR 8 +#define R_VECT_MASK_CLR__serial__WIDTH 1 +#define R_VECT_MASK_CLR__serial__clr 1 +#define R_VECT_MASK_CLR__serial__nop 0 +#define R_VECT_MASK_CLR__snmp__BITNR 7 +#define R_VECT_MASK_CLR__snmp__WIDTH 1 +#define R_VECT_MASK_CLR__snmp__clr 1 +#define R_VECT_MASK_CLR__snmp__nop 0 +#define R_VECT_MASK_CLR__network__BITNR 6 +#define R_VECT_MASK_CLR__network__WIDTH 1 +#define R_VECT_MASK_CLR__network__clr 1 +#define R_VECT_MASK_CLR__network__nop 0 +#define R_VECT_MASK_CLR__scsi1__BITNR 5 +#define R_VECT_MASK_CLR__scsi1__WIDTH 1 +#define R_VECT_MASK_CLR__scsi1__clr 1 +#define R_VECT_MASK_CLR__scsi1__nop 0 +#define R_VECT_MASK_CLR__par1__BITNR 5 +#define R_VECT_MASK_CLR__par1__WIDTH 1 +#define R_VECT_MASK_CLR__par1__clr 1 +#define R_VECT_MASK_CLR__par1__nop 0 +#define R_VECT_MASK_CLR__scsi0__BITNR 4 +#define R_VECT_MASK_CLR__scsi0__WIDTH 1 +#define R_VECT_MASK_CLR__scsi0__clr 1 +#define R_VECT_MASK_CLR__scsi0__nop 0 +#define R_VECT_MASK_CLR__par0__BITNR 4 +#define R_VECT_MASK_CLR__par0__WIDTH 1 +#define R_VECT_MASK_CLR__par0__clr 1 +#define R_VECT_MASK_CLR__par0__nop 0 +#define R_VECT_MASK_CLR__ata__BITNR 4 +#define R_VECT_MASK_CLR__ata__WIDTH 1 +#define R_VECT_MASK_CLR__ata__clr 1 +#define R_VECT_MASK_CLR__ata__nop 0 +#define R_VECT_MASK_CLR__mio__BITNR 4 +#define R_VECT_MASK_CLR__mio__WIDTH 1 +#define R_VECT_MASK_CLR__mio__clr 1 +#define R_VECT_MASK_CLR__mio__nop 0 +#define R_VECT_MASK_CLR__timer1__BITNR 3 +#define R_VECT_MASK_CLR__timer1__WIDTH 1 +#define R_VECT_MASK_CLR__timer1__clr 1 +#define R_VECT_MASK_CLR__timer1__nop 0 +#define R_VECT_MASK_CLR__timer0__BITNR 2 +#define R_VECT_MASK_CLR__timer0__WIDTH 1 +#define R_VECT_MASK_CLR__timer0__clr 1 +#define R_VECT_MASK_CLR__timer0__nop 0 +#define R_VECT_MASK_CLR__nmi__BITNR 1 +#define R_VECT_MASK_CLR__nmi__WIDTH 1 +#define R_VECT_MASK_CLR__nmi__clr 1 +#define R_VECT_MASK_CLR__nmi__nop 0 +#define R_VECT_MASK_CLR__some__BITNR 0 +#define R_VECT_MASK_CLR__some__WIDTH 1 +#define R_VECT_MASK_CLR__some__clr 1 +#define R_VECT_MASK_CLR__some__nop 0 + +#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc) +#define R_VECT_READ__usb__BITNR 31 +#define R_VECT_READ__usb__WIDTH 1 +#define R_VECT_READ__usb__active 1 +#define R_VECT_READ__usb__inactive 0 +#define R_VECT_READ__dma9__BITNR 25 +#define R_VECT_READ__dma9__WIDTH 1 +#define R_VECT_READ__dma9__active 1 +#define R_VECT_READ__dma9__inactive 0 +#define R_VECT_READ__dma8__BITNR 24 +#define R_VECT_READ__dma8__WIDTH 1 +#define R_VECT_READ__dma8__active 1 +#define R_VECT_READ__dma8__inactive 0 +#define R_VECT_READ__dma7__BITNR 23 +#define R_VECT_READ__dma7__WIDTH 1 +#define R_VECT_READ__dma7__active 1 +#define R_VECT_READ__dma7__inactive 0 +#define R_VECT_READ__dma6__BITNR 22 +#define R_VECT_READ__dma6__WIDTH 1 +#define R_VECT_READ__dma6__active 1 +#define R_VECT_READ__dma6__inactive 0 +#define R_VECT_READ__dma5__BITNR 21 +#define R_VECT_READ__dma5__WIDTH 1 +#define R_VECT_READ__dma5__active 1 +#define R_VECT_READ__dma5__inactive 0 +#define R_VECT_READ__dma4__BITNR 20 +#define R_VECT_READ__dma4__WIDTH 1 +#define R_VECT_READ__dma4__active 1 +#define R_VECT_READ__dma4__inactive 0 +#define R_VECT_READ__dma3__BITNR 19 +#define R_VECT_READ__dma3__WIDTH 1 +#define R_VECT_READ__dma3__active 1 +#define R_VECT_READ__dma3__inactive 0 +#define R_VECT_READ__dma2__BITNR 18 +#define R_VECT_READ__dma2__WIDTH 1 +#define R_VECT_READ__dma2__active 1 +#define R_VECT_READ__dma2__inactive 0 +#define R_VECT_READ__dma1__BITNR 17 +#define R_VECT_READ__dma1__WIDTH 1 +#define R_VECT_READ__dma1__active 1 +#define R_VECT_READ__dma1__inactive 0 +#define R_VECT_READ__dma0__BITNR 16 +#define R_VECT_READ__dma0__WIDTH 1 +#define R_VECT_READ__dma0__active 1 +#define R_VECT_READ__dma0__inactive 0 +#define R_VECT_READ__ext_dma1__BITNR 13 +#define R_VECT_READ__ext_dma1__WIDTH 1 +#define R_VECT_READ__ext_dma1__active 1 +#define R_VECT_READ__ext_dma1__inactive 0 +#define R_VECT_READ__ext_dma0__BITNR 12 +#define R_VECT_READ__ext_dma0__WIDTH 1 +#define R_VECT_READ__ext_dma0__active 1 +#define R_VECT_READ__ext_dma0__inactive 0 +#define R_VECT_READ__pa__BITNR 11 +#define R_VECT_READ__pa__WIDTH 1 +#define R_VECT_READ__pa__active 1 +#define R_VECT_READ__pa__inactive 0 +#define R_VECT_READ__irq_intnr__BITNR 10 +#define R_VECT_READ__irq_intnr__WIDTH 1 +#define R_VECT_READ__irq_intnr__active 1 +#define R_VECT_READ__irq_intnr__inactive 0 +#define R_VECT_READ__sw__BITNR 9 +#define R_VECT_READ__sw__WIDTH 1 +#define R_VECT_READ__sw__active 1 +#define R_VECT_READ__sw__inactive 0 +#define R_VECT_READ__serial__BITNR 8 +#define R_VECT_READ__serial__WIDTH 1 +#define R_VECT_READ__serial__active 1 +#define R_VECT_READ__serial__inactive 0 +#define R_VECT_READ__snmp__BITNR 7 +#define R_VECT_READ__snmp__WIDTH 1 +#define R_VECT_READ__snmp__active 1 +#define R_VECT_READ__snmp__inactive 0 +#define R_VECT_READ__network__BITNR 6 +#define R_VECT_READ__network__WIDTH 1 +#define R_VECT_READ__network__active 1 +#define R_VECT_READ__network__inactive 0 +#define R_VECT_READ__scsi1__BITNR 5 +#define R_VECT_READ__scsi1__WIDTH 1 +#define R_VECT_READ__scsi1__active 1 +#define R_VECT_READ__scsi1__inactive 0 +#define R_VECT_READ__par1__BITNR 5 +#define R_VECT_READ__par1__WIDTH 1 +#define R_VECT_READ__par1__active 1 +#define R_VECT_READ__par1__inactive 0 +#define R_VECT_READ__scsi0__BITNR 4 +#define R_VECT_READ__scsi0__WIDTH 1 +#define R_VECT_READ__scsi0__active 1 +#define R_VECT_READ__scsi0__inactive 0 +#define R_VECT_READ__par0__BITNR 4 +#define R_VECT_READ__par0__WIDTH 1 +#define R_VECT_READ__par0__active 1 +#define R_VECT_READ__par0__inactive 0 +#define R_VECT_READ__ata__BITNR 4 +#define R_VECT_READ__ata__WIDTH 1 +#define R_VECT_READ__ata__active 1 +#define R_VECT_READ__ata__inactive 0 +#define R_VECT_READ__mio__BITNR 4 +#define R_VECT_READ__mio__WIDTH 1 +#define R_VECT_READ__mio__active 1 +#define R_VECT_READ__mio__inactive 0 +#define R_VECT_READ__timer1__BITNR 3 +#define R_VECT_READ__timer1__WIDTH 1 +#define R_VECT_READ__timer1__active 1 +#define R_VECT_READ__timer1__inactive 0 +#define R_VECT_READ__timer0__BITNR 2 +#define R_VECT_READ__timer0__WIDTH 1 +#define R_VECT_READ__timer0__active 1 +#define R_VECT_READ__timer0__inactive 0 +#define R_VECT_READ__nmi__BITNR 1 +#define R_VECT_READ__nmi__WIDTH 1 +#define R_VECT_READ__nmi__active 1 +#define R_VECT_READ__nmi__inactive 0 +#define R_VECT_READ__some__BITNR 0 +#define R_VECT_READ__some__WIDTH 1 +#define R_VECT_READ__some__active 1 +#define R_VECT_READ__some__inactive 0 + +#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc) +#define R_VECT_MASK_SET__usb__BITNR 31 +#define R_VECT_MASK_SET__usb__WIDTH 1 +#define R_VECT_MASK_SET__usb__set 1 +#define R_VECT_MASK_SET__usb__nop 0 +#define R_VECT_MASK_SET__dma9__BITNR 25 +#define R_VECT_MASK_SET__dma9__WIDTH 1 +#define R_VECT_MASK_SET__dma9__set 1 +#define R_VECT_MASK_SET__dma9__nop 0 +#define R_VECT_MASK_SET__dma8__BITNR 24 +#define R_VECT_MASK_SET__dma8__WIDTH 1 +#define R_VECT_MASK_SET__dma8__set 1 +#define R_VECT_MASK_SET__dma8__nop 0 +#define R_VECT_MASK_SET__dma7__BITNR 23 +#define R_VECT_MASK_SET__dma7__WIDTH 1 +#define R_VECT_MASK_SET__dma7__set 1 +#define R_VECT_MASK_SET__dma7__nop 0 +#define R_VECT_MASK_SET__dma6__BITNR 22 +#define R_VECT_MASK_SET__dma6__WIDTH 1 +#define R_VECT_MASK_SET__dma6__set 1 +#define R_VECT_MASK_SET__dma6__nop 0 +#define R_VECT_MASK_SET__dma5__BITNR 21 +#define R_VECT_MASK_SET__dma5__WIDTH 1 +#define R_VECT_MASK_SET__dma5__set 1 +#define R_VECT_MASK_SET__dma5__nop 0 +#define R_VECT_MASK_SET__dma4__BITNR 20 +#define R_VECT_MASK_SET__dma4__WIDTH 1 +#define R_VECT_MASK_SET__dma4__set 1 +#define R_VECT_MASK_SET__dma4__nop 0 +#define R_VECT_MASK_SET__dma3__BITNR 19 +#define R_VECT_MASK_SET__dma3__WIDTH 1 +#define R_VECT_MASK_SET__dma3__set 1 +#define R_VECT_MASK_SET__dma3__nop 0 +#define R_VECT_MASK_SET__dma2__BITNR 18 +#define R_VECT_MASK_SET__dma2__WIDTH 1 +#define R_VECT_MASK_SET__dma2__set 1 +#define R_VECT_MASK_SET__dma2__nop 0 +#define R_VECT_MASK_SET__dma1__BITNR 17 +#define R_VECT_MASK_SET__dma1__WIDTH 1 +#define R_VECT_MASK_SET__dma1__set 1 +#define R_VECT_MASK_SET__dma1__nop 0 +#define R_VECT_MASK_SET__dma0__BITNR 16 +#define R_VECT_MASK_SET__dma0__WIDTH 1 +#define R_VECT_MASK_SET__dma0__set 1 +#define R_VECT_MASK_SET__dma0__nop 0 +#define R_VECT_MASK_SET__ext_dma1__BITNR 13 +#define R_VECT_MASK_SET__ext_dma1__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma1__set 1 +#define R_VECT_MASK_SET__ext_dma1__nop 0 +#define R_VECT_MASK_SET__ext_dma0__BITNR 12 +#define R_VECT_MASK_SET__ext_dma0__WIDTH 1 +#define R_VECT_MASK_SET__ext_dma0__set 1 +#define R_VECT_MASK_SET__ext_dma0__nop 0 +#define R_VECT_MASK_SET__pa__BITNR 11 +#define R_VECT_MASK_SET__pa__WIDTH 1 +#define R_VECT_MASK_SET__pa__set 1 +#define R_VECT_MASK_SET__pa__nop 0 +#define R_VECT_MASK_SET__irq_intnr__BITNR 10 +#define R_VECT_MASK_SET__irq_intnr__WIDTH 1 +#define R_VECT_MASK_SET__irq_intnr__set 1 +#define R_VECT_MASK_SET__irq_intnr__nop 0 +#define R_VECT_MASK_SET__sw__BITNR 9 +#define R_VECT_MASK_SET__sw__WIDTH 1 +#define R_VECT_MASK_SET__sw__set 1 +#define R_VECT_MASK_SET__sw__nop 0 +#define R_VECT_MASK_SET__serial__BITNR 8 +#define R_VECT_MASK_SET__serial__WIDTH 1 +#define R_VECT_MASK_SET__serial__set 1 +#define R_VECT_MASK_SET__serial__nop 0 +#define R_VECT_MASK_SET__snmp__BITNR 7 +#define R_VECT_MASK_SET__snmp__WIDTH 1 +#define R_VECT_MASK_SET__snmp__set 1 +#define R_VECT_MASK_SET__snmp__nop 0 +#define R_VECT_MASK_SET__network__BITNR 6 +#define R_VECT_MASK_SET__network__WIDTH 1 +#define R_VECT_MASK_SET__network__set 1 +#define R_VECT_MASK_SET__network__nop 0 +#define R_VECT_MASK_SET__scsi1__BITNR 5 +#define R_VECT_MASK_SET__scsi1__WIDTH 1 +#define R_VECT_MASK_SET__scsi1__set 1 +#define R_VECT_MASK_SET__scsi1__nop 0 +#define R_VECT_MASK_SET__par1__BITNR 5 +#define R_VECT_MASK_SET__par1__WIDTH 1 +#define R_VECT_MASK_SET__par1__set 1 +#define R_VECT_MASK_SET__par1__nop 0 +#define R_VECT_MASK_SET__scsi0__BITNR 4 +#define R_VECT_MASK_SET__scsi0__WIDTH 1 +#define R_VECT_MASK_SET__scsi0__set 1 +#define R_VECT_MASK_SET__scsi0__nop 0 +#define R_VECT_MASK_SET__par0__BITNR 4 +#define R_VECT_MASK_SET__par0__WIDTH 1 +#define R_VECT_MASK_SET__par0__set 1 +#define R_VECT_MASK_SET__par0__nop 0 +#define R_VECT_MASK_SET__ata__BITNR 4 +#define R_VECT_MASK_SET__ata__WIDTH 1 +#define R_VECT_MASK_SET__ata__set 1 +#define R_VECT_MASK_SET__ata__nop 0 +#define R_VECT_MASK_SET__mio__BITNR 4 +#define R_VECT_MASK_SET__mio__WIDTH 1 +#define R_VECT_MASK_SET__mio__set 1 +#define R_VECT_MASK_SET__mio__nop 0 +#define R_VECT_MASK_SET__timer1__BITNR 3 +#define R_VECT_MASK_SET__timer1__WIDTH 1 +#define R_VECT_MASK_SET__timer1__set 1 +#define R_VECT_MASK_SET__timer1__nop 0 +#define R_VECT_MASK_SET__timer0__BITNR 2 +#define R_VECT_MASK_SET__timer0__WIDTH 1 +#define R_VECT_MASK_SET__timer0__set 1 +#define R_VECT_MASK_SET__timer0__nop 0 +#define R_VECT_MASK_SET__nmi__BITNR 1 +#define R_VECT_MASK_SET__nmi__WIDTH 1 +#define R_VECT_MASK_SET__nmi__set 1 +#define R_VECT_MASK_SET__nmi__nop 0 +#define R_VECT_MASK_SET__some__BITNR 0 +#define R_VECT_MASK_SET__some__WIDTH 1 +#define R_VECT_MASK_SET__some__set 1 +#define R_VECT_MASK_SET__some__nop 0 + +/* +!* DMA registers +!*/ + +#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c) +#define R_SET_EOP__ch9_eop__BITNR 3 +#define R_SET_EOP__ch9_eop__WIDTH 1 +#define R_SET_EOP__ch9_eop__set 1 +#define R_SET_EOP__ch9_eop__nop 0 +#define R_SET_EOP__ch7_eop__BITNR 2 +#define R_SET_EOP__ch7_eop__WIDTH 1 +#define R_SET_EOP__ch7_eop__set 1 +#define R_SET_EOP__ch7_eop__nop 0 +#define R_SET_EOP__ch5_eop__BITNR 1 +#define R_SET_EOP__ch5_eop__WIDTH 1 +#define R_SET_EOP__ch5_eop__set 1 +#define R_SET_EOP__ch5_eop__nop 0 +#define R_SET_EOP__ch3_eop__BITNR 0 +#define R_SET_EOP__ch3_eop__WIDTH 1 +#define R_SET_EOP__ch3_eop__set 1 +#define R_SET_EOP__ch3_eop__nop 0 + +#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100) +#define R_DMA_CH0_HWSW__hw__BITNR 16 +#define R_DMA_CH0_HWSW__hw__WIDTH 16 +#define R_DMA_CH0_HWSW__sw__BITNR 0 +#define R_DMA_CH0_HWSW__sw__WIDTH 16 + +#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c) +#define R_DMA_CH0_DESCR__descr__BITNR 0 +#define R_DMA_CH0_DESCR__descr__WIDTH 32 + +#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104) +#define R_DMA_CH0_NEXT__next__BITNR 0 +#define R_DMA_CH0_NEXT__next__WIDTH 32 + +#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108) +#define R_DMA_CH0_BUF__buf__BITNR 0 +#define R_DMA_CH0_BUF__buf__WIDTH 32 + +#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0) +#define R_DMA_CH0_FIRST__first__BITNR 0 +#define R_DMA_CH0_FIRST__first__WIDTH 32 + +#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0) +#define R_DMA_CH0_CMD__cmd__BITNR 0 +#define R_DMA_CH0_CMD__cmd__WIDTH 3 +#define R_DMA_CH0_CMD__cmd__hold 0 +#define R_DMA_CH0_CMD__cmd__start 1 +#define R_DMA_CH0_CMD__cmd__restart 3 +#define R_DMA_CH0_CMD__cmd__continue 3 +#define R_DMA_CH0_CMD__cmd__reset 4 + +#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1) +#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2) +#define R_DMA_CH0_STATUS__avail__BITNR 0 +#define R_DMA_CH0_STATUS__avail__WIDTH 7 + +#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110) +#define R_DMA_CH1_HWSW__hw__BITNR 16 +#define R_DMA_CH1_HWSW__hw__WIDTH 16 +#define R_DMA_CH1_HWSW__sw__BITNR 0 +#define R_DMA_CH1_HWSW__sw__WIDTH 16 + +#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c) +#define R_DMA_CH1_DESCR__descr__BITNR 0 +#define R_DMA_CH1_DESCR__descr__WIDTH 32 + +#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114) +#define R_DMA_CH1_NEXT__next__BITNR 0 +#define R_DMA_CH1_NEXT__next__WIDTH 32 + +#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118) +#define R_DMA_CH1_BUF__buf__BITNR 0 +#define R_DMA_CH1_BUF__buf__WIDTH 32 + +#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4) +#define R_DMA_CH1_FIRST__first__BITNR 0 +#define R_DMA_CH1_FIRST__first__WIDTH 32 + +#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4) +#define R_DMA_CH1_CMD__cmd__BITNR 0 +#define R_DMA_CH1_CMD__cmd__WIDTH 3 +#define R_DMA_CH1_CMD__cmd__hold 0 +#define R_DMA_CH1_CMD__cmd__start 1 +#define R_DMA_CH1_CMD__cmd__restart 3 +#define R_DMA_CH1_CMD__cmd__continue 3 +#define R_DMA_CH1_CMD__cmd__reset 4 + +#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5) +#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6) +#define R_DMA_CH1_STATUS__avail__BITNR 0 +#define R_DMA_CH1_STATUS__avail__WIDTH 7 + +#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120) +#define R_DMA_CH2_HWSW__hw__BITNR 16 +#define R_DMA_CH2_HWSW__hw__WIDTH 16 +#define R_DMA_CH2_HWSW__sw__BITNR 0 +#define R_DMA_CH2_HWSW__sw__WIDTH 16 + +#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c) +#define R_DMA_CH2_DESCR__descr__BITNR 0 +#define R_DMA_CH2_DESCR__descr__WIDTH 32 + +#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124) +#define R_DMA_CH2_NEXT__next__BITNR 0 +#define R_DMA_CH2_NEXT__next__WIDTH 32 + +#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128) +#define R_DMA_CH2_BUF__buf__BITNR 0 +#define R_DMA_CH2_BUF__buf__WIDTH 32 + +#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8) +#define R_DMA_CH2_FIRST__first__BITNR 0 +#define R_DMA_CH2_FIRST__first__WIDTH 32 + +#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8) +#define R_DMA_CH2_CMD__cmd__BITNR 0 +#define R_DMA_CH2_CMD__cmd__WIDTH 3 +#define R_DMA_CH2_CMD__cmd__hold 0 +#define R_DMA_CH2_CMD__cmd__start 1 +#define R_DMA_CH2_CMD__cmd__restart 3 +#define R_DMA_CH2_CMD__cmd__continue 3 +#define R_DMA_CH2_CMD__cmd__reset 4 + +#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9) +#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da) +#define R_DMA_CH2_STATUS__avail__BITNR 0 +#define R_DMA_CH2_STATUS__avail__WIDTH 7 + +#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130) +#define R_DMA_CH3_HWSW__hw__BITNR 16 +#define R_DMA_CH3_HWSW__hw__WIDTH 16 +#define R_DMA_CH3_HWSW__sw__BITNR 0 +#define R_DMA_CH3_HWSW__sw__WIDTH 16 + +#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c) +#define R_DMA_CH3_DESCR__descr__BITNR 0 +#define R_DMA_CH3_DESCR__descr__WIDTH 32 + +#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134) +#define R_DMA_CH3_NEXT__next__BITNR 0 +#define R_DMA_CH3_NEXT__next__WIDTH 32 + +#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138) +#define R_DMA_CH3_BUF__buf__BITNR 0 +#define R_DMA_CH3_BUF__buf__WIDTH 32 + +#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac) +#define R_DMA_CH3_FIRST__first__BITNR 0 +#define R_DMA_CH3_FIRST__first__WIDTH 32 + +#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc) +#define R_DMA_CH3_CMD__cmd__BITNR 0 +#define R_DMA_CH3_CMD__cmd__WIDTH 3 +#define R_DMA_CH3_CMD__cmd__hold 0 +#define R_DMA_CH3_CMD__cmd__start 1 +#define R_DMA_CH3_CMD__cmd__restart 3 +#define R_DMA_CH3_CMD__cmd__continue 3 +#define R_DMA_CH3_CMD__cmd__reset 4 + +#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd) +#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de) +#define R_DMA_CH3_STATUS__avail__BITNR 0 +#define R_DMA_CH3_STATUS__avail__WIDTH 7 + +#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140) +#define R_DMA_CH4_HWSW__hw__BITNR 16 +#define R_DMA_CH4_HWSW__hw__WIDTH 16 +#define R_DMA_CH4_HWSW__sw__BITNR 0 +#define R_DMA_CH4_HWSW__sw__WIDTH 16 + +#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c) +#define R_DMA_CH4_DESCR__descr__BITNR 0 +#define R_DMA_CH4_DESCR__descr__WIDTH 32 + +#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144) +#define R_DMA_CH4_NEXT__next__BITNR 0 +#define R_DMA_CH4_NEXT__next__WIDTH 32 + +#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148) +#define R_DMA_CH4_BUF__buf__BITNR 0 +#define R_DMA_CH4_BUF__buf__WIDTH 32 + +#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0) +#define R_DMA_CH4_FIRST__first__BITNR 0 +#define R_DMA_CH4_FIRST__first__WIDTH 32 + +#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0) +#define R_DMA_CH4_CMD__cmd__BITNR 0 +#define R_DMA_CH4_CMD__cmd__WIDTH 3 +#define R_DMA_CH4_CMD__cmd__hold 0 +#define R_DMA_CH4_CMD__cmd__start 1 +#define R_DMA_CH4_CMD__cmd__restart 3 +#define R_DMA_CH4_CMD__cmd__continue 3 +#define R_DMA_CH4_CMD__cmd__reset 4 + +#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1) +#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2) +#define R_DMA_CH4_STATUS__avail__BITNR 0 +#define R_DMA_CH4_STATUS__avail__WIDTH 7 + +#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150) +#define R_DMA_CH5_HWSW__hw__BITNR 16 +#define R_DMA_CH5_HWSW__hw__WIDTH 16 +#define R_DMA_CH5_HWSW__sw__BITNR 0 +#define R_DMA_CH5_HWSW__sw__WIDTH 16 + +#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c) +#define R_DMA_CH5_DESCR__descr__BITNR 0 +#define R_DMA_CH5_DESCR__descr__WIDTH 32 + +#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154) +#define R_DMA_CH5_NEXT__next__BITNR 0 +#define R_DMA_CH5_NEXT__next__WIDTH 32 + +#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158) +#define R_DMA_CH5_BUF__buf__BITNR 0 +#define R_DMA_CH5_BUF__buf__WIDTH 32 + +#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4) +#define R_DMA_CH5_FIRST__first__BITNR 0 +#define R_DMA_CH5_FIRST__first__WIDTH 32 + +#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4) +#define R_DMA_CH5_CMD__cmd__BITNR 0 +#define R_DMA_CH5_CMD__cmd__WIDTH 3 +#define R_DMA_CH5_CMD__cmd__hold 0 +#define R_DMA_CH5_CMD__cmd__start 1 +#define R_DMA_CH5_CMD__cmd__restart 3 +#define R_DMA_CH5_CMD__cmd__continue 3 +#define R_DMA_CH5_CMD__cmd__reset 4 + +#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5) +#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6) +#define R_DMA_CH5_STATUS__avail__BITNR 0 +#define R_DMA_CH5_STATUS__avail__WIDTH 7 + +#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160) +#define R_DMA_CH6_HWSW__hw__BITNR 16 +#define R_DMA_CH6_HWSW__hw__WIDTH 16 +#define R_DMA_CH6_HWSW__sw__BITNR 0 +#define R_DMA_CH6_HWSW__sw__WIDTH 16 + +#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c) +#define R_DMA_CH6_DESCR__descr__BITNR 0 +#define R_DMA_CH6_DESCR__descr__WIDTH 32 + +#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164) +#define R_DMA_CH6_NEXT__next__BITNR 0 +#define R_DMA_CH6_NEXT__next__WIDTH 32 + +#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168) +#define R_DMA_CH6_BUF__buf__BITNR 0 +#define R_DMA_CH6_BUF__buf__WIDTH 32 + +#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8) +#define R_DMA_CH6_FIRST__first__BITNR 0 +#define R_DMA_CH6_FIRST__first__WIDTH 32 + +#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8) +#define R_DMA_CH6_CMD__cmd__BITNR 0 +#define R_DMA_CH6_CMD__cmd__WIDTH 3 +#define R_DMA_CH6_CMD__cmd__hold 0 +#define R_DMA_CH6_CMD__cmd__start 1 +#define R_DMA_CH6_CMD__cmd__restart 3 +#define R_DMA_CH6_CMD__cmd__continue 3 +#define R_DMA_CH6_CMD__cmd__reset 4 + +#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9) +#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea) +#define R_DMA_CH6_STATUS__avail__BITNR 0 +#define R_DMA_CH6_STATUS__avail__WIDTH 7 + +#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170) +#define R_DMA_CH7_HWSW__hw__BITNR 16 +#define R_DMA_CH7_HWSW__hw__WIDTH 16 +#define R_DMA_CH7_HWSW__sw__BITNR 0 +#define R_DMA_CH7_HWSW__sw__WIDTH 16 + +#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c) +#define R_DMA_CH7_DESCR__descr__BITNR 0 +#define R_DMA_CH7_DESCR__descr__WIDTH 32 + +#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174) +#define R_DMA_CH7_NEXT__next__BITNR 0 +#define R_DMA_CH7_NEXT__next__WIDTH 32 + +#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178) +#define R_DMA_CH7_BUF__buf__BITNR 0 +#define R_DMA_CH7_BUF__buf__WIDTH 32 + +#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc) +#define R_DMA_CH7_FIRST__first__BITNR 0 +#define R_DMA_CH7_FIRST__first__WIDTH 32 + +#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec) +#define R_DMA_CH7_CMD__cmd__BITNR 0 +#define R_DMA_CH7_CMD__cmd__WIDTH 3 +#define R_DMA_CH7_CMD__cmd__hold 0 +#define R_DMA_CH7_CMD__cmd__start 1 +#define R_DMA_CH7_CMD__cmd__restart 3 +#define R_DMA_CH7_CMD__cmd__continue 3 +#define R_DMA_CH7_CMD__cmd__reset 4 + +#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed) +#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee) +#define R_DMA_CH7_STATUS__avail__BITNR 0 +#define R_DMA_CH7_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180) +#define R_DMA_CH8_HWSW__hw__BITNR 16 +#define R_DMA_CH8_HWSW__hw__WIDTH 16 +#define R_DMA_CH8_HWSW__sw__BITNR 0 +#define R_DMA_CH8_HWSW__sw__WIDTH 16 + +#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_DESCR__descr__BITNR 0 +#define R_DMA_CH8_DESCR__descr__WIDTH 32 + +#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184) +#define R_DMA_CH8_NEXT__next__BITNR 0 +#define R_DMA_CH8_NEXT__next__WIDTH 32 + +#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188) +#define R_DMA_CH8_BUF__buf__BITNR 0 +#define R_DMA_CH8_BUF__buf__WIDTH 32 + +#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_FIRST__first__BITNR 0 +#define R_DMA_CH8_FIRST__first__WIDTH 32 + +#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0) +#define R_DMA_CH8_CMD__cmd__BITNR 0 +#define R_DMA_CH8_CMD__cmd__WIDTH 3 +#define R_DMA_CH8_CMD__cmd__hold 0 +#define R_DMA_CH8_CMD__cmd__start 1 +#define R_DMA_CH8_CMD__cmd__restart 3 +#define R_DMA_CH8_CMD__cmd__continue 3 +#define R_DMA_CH8_CMD__cmd__reset 4 + +#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1) +#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2) +#define R_DMA_CH8_STATUS__avail__BITNR 0 +#define R_DMA_CH8_STATUS__avail__WIDTH 7 + +#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c) +#define R_DMA_CH8_SUB__sub__BITNR 0 +#define R_DMA_CH8_SUB__sub__WIDTH 32 + +#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0) +#define R_DMA_CH8_NEP__nep__BITNR 0 +#define R_DMA_CH8_NEP__nep__WIDTH 32 + +#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8) +#define R_DMA_CH8_SUB0_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3) +#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB0_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB0_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3) +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc) +#define R_DMA_CH8_SUB1_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7) +#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB1_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB1_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7) +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8) +#define R_DMA_CH8_SUB2_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db) +#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB2_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB2_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb) +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc) +#define R_DMA_CH8_SUB3_EP__ep__BITNR 0 +#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32 + +#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df) +#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0 +#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1 +#define R_DMA_CH8_SUB3_CMD__cmd__stop 0 +#define R_DMA_CH8_SUB3_CMD__cmd__start 1 + +#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef) +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0 +#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1 + +#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190) +#define R_DMA_CH9_HWSW__hw__BITNR 16 +#define R_DMA_CH9_HWSW__hw__WIDTH 16 +#define R_DMA_CH9_HWSW__sw__BITNR 0 +#define R_DMA_CH9_HWSW__sw__WIDTH 16 + +#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c) +#define R_DMA_CH9_DESCR__descr__BITNR 0 +#define R_DMA_CH9_DESCR__descr__WIDTH 32 + +#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194) +#define R_DMA_CH9_NEXT__next__BITNR 0 +#define R_DMA_CH9_NEXT__next__WIDTH 32 + +#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198) +#define R_DMA_CH9_BUF__buf__BITNR 0 +#define R_DMA_CH9_BUF__buf__WIDTH 32 + +#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4) +#define R_DMA_CH9_FIRST__first__BITNR 0 +#define R_DMA_CH9_FIRST__first__WIDTH 32 + +#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4) +#define R_DMA_CH9_CMD__cmd__BITNR 0 +#define R_DMA_CH9_CMD__cmd__WIDTH 3 +#define R_DMA_CH9_CMD__cmd__hold 0 +#define R_DMA_CH9_CMD__cmd__start 1 +#define R_DMA_CH9_CMD__cmd__restart 3 +#define R_DMA_CH9_CMD__cmd__continue 3 +#define R_DMA_CH9_CMD__cmd__reset 4 + +#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5) +#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__do 1 +#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0 +#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__do 1 +#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0 + +#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6) +#define R_DMA_CH9_STATUS__avail__BITNR 0 +#define R_DMA_CH9_STATUS__avail__WIDTH 7 + +/* +!* Test mode registers +!*/ + +#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc) +#define R_TEST_MODE__single_step__BITNR 19 +#define R_TEST_MODE__single_step__WIDTH 1 +#define R_TEST_MODE__single_step__on 1 +#define R_TEST_MODE__single_step__off 0 +#define R_TEST_MODE__step_wr__BITNR 18 +#define R_TEST_MODE__step_wr__WIDTH 1 +#define R_TEST_MODE__step_wr__on 1 +#define R_TEST_MODE__step_wr__off 0 +#define R_TEST_MODE__step_rd__BITNR 17 +#define R_TEST_MODE__step_rd__WIDTH 1 +#define R_TEST_MODE__step_rd__on 1 +#define R_TEST_MODE__step_rd__off 0 +#define R_TEST_MODE__step_fetch__BITNR 16 +#define R_TEST_MODE__step_fetch__WIDTH 1 +#define R_TEST_MODE__step_fetch__on 1 +#define R_TEST_MODE__step_fetch__off 0 +#define R_TEST_MODE__mmu_test__BITNR 12 +#define R_TEST_MODE__mmu_test__WIDTH 1 +#define R_TEST_MODE__mmu_test__on 1 +#define R_TEST_MODE__mmu_test__off 0 +#define R_TEST_MODE__usb_test__BITNR 11 +#define R_TEST_MODE__usb_test__WIDTH 1 +#define R_TEST_MODE__usb_test__on 1 +#define R_TEST_MODE__usb_test__off 0 +#define R_TEST_MODE__scsi_timer_test__BITNR 10 +#define R_TEST_MODE__scsi_timer_test__WIDTH 1 +#define R_TEST_MODE__scsi_timer_test__on 1 +#define R_TEST_MODE__scsi_timer_test__off 0 +#define R_TEST_MODE__backoff__BITNR 9 +#define R_TEST_MODE__backoff__WIDTH 1 +#define R_TEST_MODE__backoff__on 1 +#define R_TEST_MODE__backoff__off 0 +#define R_TEST_MODE__snmp_test__BITNR 8 +#define R_TEST_MODE__snmp_test__WIDTH 1 +#define R_TEST_MODE__snmp_test__on 1 +#define R_TEST_MODE__snmp_test__off 0 +#define R_TEST_MODE__snmp_inc__BITNR 7 +#define R_TEST_MODE__snmp_inc__WIDTH 1 +#define R_TEST_MODE__snmp_inc__do 1 +#define R_TEST_MODE__snmp_inc__dont 0 +#define R_TEST_MODE__ser_loop__BITNR 6 +#define R_TEST_MODE__ser_loop__WIDTH 1 +#define R_TEST_MODE__ser_loop__on 1 +#define R_TEST_MODE__ser_loop__off 0 +#define R_TEST_MODE__baudrate__BITNR 5 +#define R_TEST_MODE__baudrate__WIDTH 1 +#define R_TEST_MODE__baudrate__on 1 +#define R_TEST_MODE__baudrate__off 0 +#define R_TEST_MODE__timer__BITNR 3 +#define R_TEST_MODE__timer__WIDTH 2 +#define R_TEST_MODE__timer__off 0 +#define R_TEST_MODE__timer__even 1 +#define R_TEST_MODE__timer__odd 2 +#define R_TEST_MODE__timer__all 3 +#define R_TEST_MODE__cache_test__BITNR 2 +#define R_TEST_MODE__cache_test__WIDTH 1 +#define R_TEST_MODE__cache_test__normal 0 +#define R_TEST_MODE__cache_test__test 1 +#define R_TEST_MODE__tag_test__BITNR 1 +#define R_TEST_MODE__tag_test__WIDTH 1 +#define R_TEST_MODE__tag_test__normal 0 +#define R_TEST_MODE__tag_test__test 1 +#define R_TEST_MODE__cache_enable__BITNR 0 +#define R_TEST_MODE__cache_enable__WIDTH 1 +#define R_TEST_MODE__cache_enable__enable 1 +#define R_TEST_MODE__cache_enable__disable 0 + +#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe) +#define R_SINGLE_STEP__single_step__BITNR 3 +#define R_SINGLE_STEP__single_step__WIDTH 1 +#define R_SINGLE_STEP__single_step__on 1 +#define R_SINGLE_STEP__single_step__off 0 +#define R_SINGLE_STEP__step_wr__BITNR 2 +#define R_SINGLE_STEP__step_wr__WIDTH 1 +#define R_SINGLE_STEP__step_wr__on 1 +#define R_SINGLE_STEP__step_wr__off 0 +#define R_SINGLE_STEP__step_rd__BITNR 1 +#define R_SINGLE_STEP__step_rd__WIDTH 1 +#define R_SINGLE_STEP__step_rd__on 1 +#define R_SINGLE_STEP__step_rd__off 0 +#define R_SINGLE_STEP__step_fetch__BITNR 0 +#define R_SINGLE_STEP__step_fetch__WIDTH 1 +#define R_SINGLE_STEP__step_fetch__on 1 +#define R_SINGLE_STEP__step_fetch__off 0 + +/* +!* USB interface control registers +!*/ + +#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200) +#define R_USB_REVISION__major__BITNR 4 +#define R_USB_REVISION__major__WIDTH 4 +#define R_USB_REVISION__minor__BITNR 0 +#define R_USB_REVISION__minor__WIDTH 4 + +#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND__port_sel__BITNR 6 +#define R_USB_COMMAND__port_sel__WIDTH 2 +#define R_USB_COMMAND__port_sel__nop 0 +#define R_USB_COMMAND__port_sel__port1 1 +#define R_USB_COMMAND__port_sel__port2 2 +#define R_USB_COMMAND__port_sel__both 3 +#define R_USB_COMMAND__port_cmd__BITNR 4 +#define R_USB_COMMAND__port_cmd__WIDTH 2 +#define R_USB_COMMAND__port_cmd__reset 0 +#define R_USB_COMMAND__port_cmd__disable 1 +#define R_USB_COMMAND__port_cmd__suspend 2 +#define R_USB_COMMAND__port_cmd__resume 3 +#define R_USB_COMMAND__busy__BITNR 3 +#define R_USB_COMMAND__busy__WIDTH 1 +#define R_USB_COMMAND__busy__no 0 +#define R_USB_COMMAND__busy__yes 1 +#define R_USB_COMMAND__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND__ctrl_cmd__nop 0 +#define R_USB_COMMAND__ctrl_cmd__reset 1 +#define R_USB_COMMAND__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND__ctrl_cmd__host_config 3 +#define R_USB_COMMAND__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND__ctrl_cmd__host_nop 5 +#define R_USB_COMMAND__ctrl_cmd__host_run 6 +#define R_USB_COMMAND__ctrl_cmd__host_stop 7 + +#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201) +#define R_USB_COMMAND_DEV__port_sel__BITNR 6 +#define R_USB_COMMAND_DEV__port_sel__WIDTH 2 +#define R_USB_COMMAND_DEV__port_sel__nop 0 +#define R_USB_COMMAND_DEV__port_sel__dummy1 1 +#define R_USB_COMMAND_DEV__port_sel__dummy2 2 +#define R_USB_COMMAND_DEV__port_sel__any 3 +#define R_USB_COMMAND_DEV__port_cmd__BITNR 4 +#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2 +#define R_USB_COMMAND_DEV__port_cmd__active 0 +#define R_USB_COMMAND_DEV__port_cmd__passive 1 +#define R_USB_COMMAND_DEV__port_cmd__nop 2 +#define R_USB_COMMAND_DEV__port_cmd__wakeup 3 +#define R_USB_COMMAND_DEV__busy__BITNR 3 +#define R_USB_COMMAND_DEV__busy__WIDTH 1 +#define R_USB_COMMAND_DEV__busy__no 0 +#define R_USB_COMMAND_DEV__busy__yes 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0 +#define R_USB_COMMAND_DEV__ctrl_cmd__reset 1 +#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2 +#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_active 5 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_passive 6 +#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 7 + +#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202) +#define R_USB_STATUS__ourun__BITNR 5 +#define R_USB_STATUS__ourun__WIDTH 1 +#define R_USB_STATUS__ourun__no 0 +#define R_USB_STATUS__ourun__yes 1 +#define R_USB_STATUS__perror__BITNR 4 +#define R_USB_STATUS__perror__WIDTH 1 +#define R_USB_STATUS__perror__no 0 +#define R_USB_STATUS__perror__yes 1 +#define R_USB_STATUS__device_mode__BITNR 3 +#define R_USB_STATUS__device_mode__WIDTH 1 +#define R_USB_STATUS__device_mode__no 0 +#define R_USB_STATUS__device_mode__yes 1 +#define R_USB_STATUS__host_mode__BITNR 2 +#define R_USB_STATUS__host_mode__WIDTH 1 +#define R_USB_STATUS__host_mode__no 0 +#define R_USB_STATUS__host_mode__yes 1 +#define R_USB_STATUS__started__BITNR 1 +#define R_USB_STATUS__started__WIDTH 1 +#define R_USB_STATUS__started__no 0 +#define R_USB_STATUS__started__yes 1 +#define R_USB_STATUS__running__BITNR 0 +#define R_USB_STATUS__running__WIDTH 1 +#define R_USB_STATUS__running__no 0 +#define R_USB_STATUS__running__yes 1 + +#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eof__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eof__set 1 +#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eof__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eof__set 1 +#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__iso_eot__nop 0 +#define R_USB_IRQ_MASK_SET__iso_eot__set 1 +#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__intr_eot__nop 0 +#define R_USB_IRQ_MASK_SET__intr_eot__set 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_eot__set 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_SET__bulk_eot__set 1 +#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET__sof__nop 0 +#define R_USB_IRQ_MASK_SET__sof__set 1 +#define R_USB_IRQ_MASK_SET__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__port_status__nop 0 +#define R_USB_IRQ_MASK_SET__port_status__set 1 +#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eof__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eof__pend 1 +#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__iso_eot__pend 1 +#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__intr_eot__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1 +#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ__sof__pend 1 +#define R_USB_IRQ_MASK_READ__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__port_status__pend 1 +#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13 +#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12 +#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0 +#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__sof__nop 0 +#define R_USB_IRQ_MASK_CLR__sof__clr 1 +#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1 + +#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ__iso_eof__BITNR 13 +#define R_USB_IRQ_READ__iso_eof__WIDTH 1 +#define R_USB_IRQ_READ__iso_eof__no_pend 0 +#define R_USB_IRQ_READ__iso_eof__pend 1 +#define R_USB_IRQ_READ__intr_eof__BITNR 12 +#define R_USB_IRQ_READ__intr_eof__WIDTH 1 +#define R_USB_IRQ_READ__intr_eof__no_pend 0 +#define R_USB_IRQ_READ__intr_eof__pend 1 +#define R_USB_IRQ_READ__iso_eot__BITNR 11 +#define R_USB_IRQ_READ__iso_eot__WIDTH 1 +#define R_USB_IRQ_READ__iso_eot__no_pend 0 +#define R_USB_IRQ_READ__iso_eot__pend 1 +#define R_USB_IRQ_READ__intr_eot__BITNR 10 +#define R_USB_IRQ_READ__intr_eot__WIDTH 1 +#define R_USB_IRQ_READ__intr_eot__no_pend 0 +#define R_USB_IRQ_READ__intr_eot__pend 1 +#define R_USB_IRQ_READ__ctl_eot__BITNR 9 +#define R_USB_IRQ_READ__ctl_eot__WIDTH 1 +#define R_USB_IRQ_READ__ctl_eot__no_pend 0 +#define R_USB_IRQ_READ__ctl_eot__pend 1 +#define R_USB_IRQ_READ__bulk_eot__BITNR 8 +#define R_USB_IRQ_READ__bulk_eot__WIDTH 1 +#define R_USB_IRQ_READ__bulk_eot__no_pend 0 +#define R_USB_IRQ_READ__bulk_eot__pend 1 +#define R_USB_IRQ_READ__epid_attn__BITNR 3 +#define R_USB_IRQ_READ__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ__epid_attn__no_pend 0 +#define R_USB_IRQ_READ__epid_attn__pend 1 +#define R_USB_IRQ_READ__sof__BITNR 2 +#define R_USB_IRQ_READ__sof__WIDTH 1 +#define R_USB_IRQ_READ__sof__no_pend 0 +#define R_USB_IRQ_READ__sof__pend 1 +#define R_USB_IRQ_READ__port_status__BITNR 1 +#define R_USB_IRQ_READ__port_status__WIDTH 1 +#define R_USB_IRQ_READ__port_status__no_pend 0 +#define R_USB_IRQ_READ__port_status__pend 1 +#define R_USB_IRQ_READ__ctl_status__BITNR 0 +#define R_USB_IRQ_READ__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ__ctl_status__no_pend 0 +#define R_USB_IRQ_READ__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__sof__set 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1 + +#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204) +#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1 + +#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206) +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2 +#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0 +#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1 + +#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206) +#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12 +#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__out_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0 +#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1 +#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3 +#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1 +#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0 +#define R_USB_IRQ_READ_DEV__epid_attn__pend 1 +#define R_USB_IRQ_READ_DEV__sof__BITNR 2 +#define R_USB_IRQ_READ_DEV__sof__WIDTH 1 +#define R_USB_IRQ_READ_DEV__sof__no_pend 0 +#define R_USB_IRQ_READ_DEV__sof__pend 1 +#define R_USB_IRQ_READ_DEV__port_status__BITNR 1 +#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__port_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__port_status__pend 1 +#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0 +#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1 +#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0 +#define R_USB_IRQ_READ_DEV__ctl_status__pend 1 + +#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c) +#define R_USB_FM_NUMBER__value__BITNR 0 +#define R_USB_FM_NUMBER__value__WIDTH 32 + +#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210) +#define R_USB_FM_INTERVAL__fixed__BITNR 6 +#define R_USB_FM_INTERVAL__fixed__WIDTH 8 +#define R_USB_FM_INTERVAL__adj__BITNR 0 +#define R_USB_FM_INTERVAL__adj__WIDTH 6 + +#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212) +#define R_USB_FM_REMAINING__value__BITNR 0 +#define R_USB_FM_REMAINING__value__WIDTH 14 + +#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214) +#define R_USB_FM_PSTART__value__BITNR 0 +#define R_USB_FM_PSTART__value__WIDTH 14 + +#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203) +#define R_USB_RH_STATUS__babble2__BITNR 7 +#define R_USB_RH_STATUS__babble2__WIDTH 1 +#define R_USB_RH_STATUS__babble2__no 0 +#define R_USB_RH_STATUS__babble2__yes 1 +#define R_USB_RH_STATUS__babble1__BITNR 6 +#define R_USB_RH_STATUS__babble1__WIDTH 1 +#define R_USB_RH_STATUS__babble1__no 0 +#define R_USB_RH_STATUS__babble1__yes 1 +#define R_USB_RH_STATUS__bus1__BITNR 4 +#define R_USB_RH_STATUS__bus1__WIDTH 2 +#define R_USB_RH_STATUS__bus1__SE0 0 +#define R_USB_RH_STATUS__bus1__Diff0 1 +#define R_USB_RH_STATUS__bus1__Diff1 2 +#define R_USB_RH_STATUS__bus1__SE1 3 +#define R_USB_RH_STATUS__bus2__BITNR 2 +#define R_USB_RH_STATUS__bus2__WIDTH 2 +#define R_USB_RH_STATUS__bus2__SE0 0 +#define R_USB_RH_STATUS__bus2__Diff0 1 +#define R_USB_RH_STATUS__bus2__Diff1 2 +#define R_USB_RH_STATUS__bus2__SE1 3 +#define R_USB_RH_STATUS__nports__BITNR 0 +#define R_USB_RH_STATUS__nports__WIDTH 2 + +#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218) +#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__speed__full 0 +#define R_USB_RH_PORT_STATUS_1__speed__low 1 +#define R_USB_RH_PORT_STATUS_1__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__reset__no 0 +#define R_USB_RH_PORT_STATUS_1__reset__yes 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__suspended__no 0 +#define R_USB_RH_PORT_STATUS_1__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__enabled__no 0 +#define R_USB_RH_PORT_STATUS_1__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_1__connected__no 0 +#define R_USB_RH_PORT_STATUS_1__connected__yes 1 + +#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a) +#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9 +#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__speed__full 0 +#define R_USB_RH_PORT_STATUS_2__speed__low 1 +#define R_USB_RH_PORT_STATUS_2__power__BITNR 8 +#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4 +#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__reset__no 0 +#define R_USB_RH_PORT_STATUS_2__reset__yes 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3 +#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0 +#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1 +#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2 +#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__suspended__no 0 +#define R_USB_RH_PORT_STATUS_2__suspended__yes 1 +#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1 +#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__enabled__no 0 +#define R_USB_RH_PORT_STATUS_2__enabled__yes 1 +#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0 +#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1 +#define R_USB_RH_PORT_STATUS_2__connected__no 0 +#define R_USB_RH_PORT_STATUS_2__connected__yes 1 + +#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208) +#define R_USB_EPT_INDEX__value__BITNR 0 +#define R_USB_EPT_INDEX__value__WIDTH 5 + +#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA__valid__BITNR 31 +#define R_USB_EPT_DATA__valid__WIDTH 1 +#define R_USB_EPT_DATA__valid__no 0 +#define R_USB_EPT_DATA__valid__yes 1 +#define R_USB_EPT_DATA__hold__BITNR 30 +#define R_USB_EPT_DATA__hold__WIDTH 1 +#define R_USB_EPT_DATA__hold__no 0 +#define R_USB_EPT_DATA__hold__yes 1 +#define R_USB_EPT_DATA__error_count_in__BITNR 28 +#define R_USB_EPT_DATA__error_count_in__WIDTH 2 +#define R_USB_EPT_DATA__t_in__BITNR 27 +#define R_USB_EPT_DATA__t_in__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__BITNR 26 +#define R_USB_EPT_DATA__low_speed__WIDTH 1 +#define R_USB_EPT_DATA__low_speed__no 0 +#define R_USB_EPT_DATA__low_speed__yes 1 +#define R_USB_EPT_DATA__port__BITNR 24 +#define R_USB_EPT_DATA__port__WIDTH 2 +#define R_USB_EPT_DATA__port__any 0 +#define R_USB_EPT_DATA__port__p1 1 +#define R_USB_EPT_DATA__port__p2 2 +#define R_USB_EPT_DATA__port__undef 3 +#define R_USB_EPT_DATA__error_code__BITNR 22 +#define R_USB_EPT_DATA__error_code__WIDTH 2 +#define R_USB_EPT_DATA__error_code__no_error 0 +#define R_USB_EPT_DATA__error_code__stall 1 +#define R_USB_EPT_DATA__error_code__bus_error 2 +#define R_USB_EPT_DATA__error_code__buffer_error 3 +#define R_USB_EPT_DATA__t_out__BITNR 21 +#define R_USB_EPT_DATA__t_out__WIDTH 1 +#define R_USB_EPT_DATA__error_count_out__BITNR 19 +#define R_USB_EPT_DATA__error_count_out__WIDTH 2 +#define R_USB_EPT_DATA__max_len__BITNR 11 +#define R_USB_EPT_DATA__max_len__WIDTH 7 +#define R_USB_EPT_DATA__ep__BITNR 7 +#define R_USB_EPT_DATA__ep__WIDTH 4 +#define R_USB_EPT_DATA__dev__BITNR 0 +#define R_USB_EPT_DATA__dev__WIDTH 7 + +#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_ISO__valid__BITNR 31 +#define R_USB_EPT_DATA_ISO__valid__WIDTH 1 +#define R_USB_EPT_DATA_ISO__valid__no 0 +#define R_USB_EPT_DATA_ISO__valid__yes 1 +#define R_USB_EPT_DATA_ISO__port__BITNR 24 +#define R_USB_EPT_DATA_ISO__port__WIDTH 2 +#define R_USB_EPT_DATA_ISO__port__any 0 +#define R_USB_EPT_DATA_ISO__port__p1 1 +#define R_USB_EPT_DATA_ISO__port__p2 2 +#define R_USB_EPT_DATA_ISO__port__undef 3 +#define R_USB_EPT_DATA_ISO__error_code__BITNR 22 +#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2 +#define R_USB_EPT_DATA_ISO__error_code__no_error 0 +#define R_USB_EPT_DATA_ISO__error_code__stall 1 +#define R_USB_EPT_DATA_ISO__error_code__bus_error 2 +#define R_USB_EPT_DATA_ISO__error_code__TBD3 3 +#define R_USB_EPT_DATA_ISO__max_len__BITNR 11 +#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10 +#define R_USB_EPT_DATA_ISO__ep__BITNR 7 +#define R_USB_EPT_DATA_ISO__ep__WIDTH 4 +#define R_USB_EPT_DATA_ISO__dev__BITNR 0 +#define R_USB_EPT_DATA_ISO__dev__WIDTH 7 + +#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c) +#define R_USB_EPT_DATA_DEV__valid__BITNR 31 +#define R_USB_EPT_DATA_DEV__valid__WIDTH 1 +#define R_USB_EPT_DATA_DEV__valid__no 0 +#define R_USB_EPT_DATA_DEV__valid__yes 1 +#define R_USB_EPT_DATA_DEV__hold__BITNR 30 +#define R_USB_EPT_DATA_DEV__hold__WIDTH 1 +#define R_USB_EPT_DATA_DEV__hold__no 0 +#define R_USB_EPT_DATA_DEV__hold__yes 1 +#define R_USB_EPT_DATA_DEV__stall__BITNR 29 +#define R_USB_EPT_DATA_DEV__stall__WIDTH 1 +#define R_USB_EPT_DATA_DEV__stall__no 0 +#define R_USB_EPT_DATA_DEV__stall__yes 1 +#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28 +#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0 +#define R_USB_EPT_DATA_DEV__iso_resp__yes 1 +#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27 +#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1 +#define R_USB_EPT_DATA_DEV__ctrl__no 0 +#define R_USB_EPT_DATA_DEV__ctrl__yes 1 +#define R_USB_EPT_DATA_DEV__iso__BITNR 26 +#define R_USB_EPT_DATA_DEV__iso__WIDTH 1 +#define R_USB_EPT_DATA_DEV__iso__no 0 +#define R_USB_EPT_DATA_DEV__iso__yes 1 +#define R_USB_EPT_DATA_DEV__port__BITNR 24 +#define R_USB_EPT_DATA_DEV__port__WIDTH 2 +#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22 +#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1 +#define R_USB_EPT_DATA_DEV__t__BITNR 21 +#define R_USB_EPT_DATA_DEV__t__WIDTH 1 +#define R_USB_EPT_DATA_DEV__max_len__BITNR 11 +#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10 +#define R_USB_EPT_DATA_DEV__ep__BITNR 7 +#define R_USB_EPT_DATA_DEV__ep__WIDTH 4 +#define R_USB_EPT_DATA_DEV__dev__BITNR 0 +#define R_USB_EPT_DATA_DEV__dev__WIDTH 7 + +#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220) +#define R_USB_SNMP_TERROR__value__BITNR 0 +#define R_USB_SNMP_TERROR__value__WIDTH 32 + +#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224) +#define R_USB_EPID_ATTN__value__BITNR 0 +#define R_USB_EPID_ATTN__value__WIDTH 32 + +#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a) +#define R_USB_PORT1_DISABLE__disable__BITNR 0 +#define R_USB_PORT1_DISABLE__disable__WIDTH 1 +#define R_USB_PORT1_DISABLE__disable__yes 0 +#define R_USB_PORT1_DISABLE__disable__no 1 + +#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052) +#define R_USB_PORT2_DISABLE__disable__BITNR 0 +#define R_USB_PORT2_DISABLE__disable__WIDTH 1 +#define R_USB_PORT2_DISABLE__disable__yes 0 +#define R_USB_PORT2_DISABLE__disable__no 1 + +/* +!* MMU registers +!*/ + +#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240) +#define R_MMU_CONFIG__mmu_enable__BITNR 31 +#define R_MMU_CONFIG__mmu_enable__WIDTH 1 +#define R_MMU_CONFIG__mmu_enable__enable 1 +#define R_MMU_CONFIG__mmu_enable__disable 0 +#define R_MMU_CONFIG__inv_excp__BITNR 18 +#define R_MMU_CONFIG__inv_excp__WIDTH 1 +#define R_MMU_CONFIG__inv_excp__enable 1 +#define R_MMU_CONFIG__inv_excp__disable 0 +#define R_MMU_CONFIG__acc_excp__BITNR 17 +#define R_MMU_CONFIG__acc_excp__WIDTH 1 +#define R_MMU_CONFIG__acc_excp__enable 1 +#define R_MMU_CONFIG__acc_excp__disable 0 +#define R_MMU_CONFIG__we_excp__BITNR 16 +#define R_MMU_CONFIG__we_excp__WIDTH 1 +#define R_MMU_CONFIG__we_excp__enable 1 +#define R_MMU_CONFIG__we_excp__disable 0 +#define R_MMU_CONFIG__seg_f__BITNR 15 +#define R_MMU_CONFIG__seg_f__WIDTH 1 +#define R_MMU_CONFIG__seg_f__seg 1 +#define R_MMU_CONFIG__seg_f__page 0 +#define R_MMU_CONFIG__seg_e__BITNR 14 +#define R_MMU_CONFIG__seg_e__WIDTH 1 +#define R_MMU_CONFIG__seg_e__seg 1 +#define R_MMU_CONFIG__seg_e__page 0 +#define R_MMU_CONFIG__seg_d__BITNR 13 +#define R_MMU_CONFIG__seg_d__WIDTH 1 +#define R_MMU_CONFIG__seg_d__seg 1 +#define R_MMU_CONFIG__seg_d__page 0 +#define R_MMU_CONFIG__seg_c__BITNR 12 +#define R_MMU_CONFIG__seg_c__WIDTH 1 +#define R_MMU_CONFIG__seg_c__seg 1 +#define R_MMU_CONFIG__seg_c__page 0 +#define R_MMU_CONFIG__seg_b__BITNR 11 +#define R_MMU_CONFIG__seg_b__WIDTH 1 +#define R_MMU_CONFIG__seg_b__seg 1 +#define R_MMU_CONFIG__seg_b__page 0 +#define R_MMU_CONFIG__seg_a__BITNR 10 +#define R_MMU_CONFIG__seg_a__WIDTH 1 +#define R_MMU_CONFIG__seg_a__seg 1 +#define R_MMU_CONFIG__seg_a__page 0 +#define R_MMU_CONFIG__seg_9__BITNR 9 +#define R_MMU_CONFIG__seg_9__WIDTH 1 +#define R_MMU_CONFIG__seg_9__seg 1 +#define R_MMU_CONFIG__seg_9__page 0 +#define R_MMU_CONFIG__seg_8__BITNR 8 +#define R_MMU_CONFIG__seg_8__WIDTH 1 +#define R_MMU_CONFIG__seg_8__seg 1 +#define R_MMU_CONFIG__seg_8__page 0 +#define R_MMU_CONFIG__seg_7__BITNR 7 +#define R_MMU_CONFIG__seg_7__WIDTH 1 +#define R_MMU_CONFIG__seg_7__seg 1 +#define R_MMU_CONFIG__seg_7__page 0 +#define R_MMU_CONFIG__seg_6__BITNR 6 +#define R_MMU_CONFIG__seg_6__WIDTH 1 +#define R_MMU_CONFIG__seg_6__seg 1 +#define R_MMU_CONFIG__seg_6__page 0 +#define R_MMU_CONFIG__seg_5__BITNR 5 +#define R_MMU_CONFIG__seg_5__WIDTH 1 +#define R_MMU_CONFIG__seg_5__seg 1 +#define R_MMU_CONFIG__seg_5__page 0 +#define R_MMU_CONFIG__seg_4__BITNR 4 +#define R_MMU_CONFIG__seg_4__WIDTH 1 +#define R_MMU_CONFIG__seg_4__seg 1 +#define R_MMU_CONFIG__seg_4__page 0 +#define R_MMU_CONFIG__seg_3__BITNR 3 +#define R_MMU_CONFIG__seg_3__WIDTH 1 +#define R_MMU_CONFIG__seg_3__seg 1 +#define R_MMU_CONFIG__seg_3__page 0 +#define R_MMU_CONFIG__seg_2__BITNR 2 +#define R_MMU_CONFIG__seg_2__WIDTH 1 +#define R_MMU_CONFIG__seg_2__seg 1 +#define R_MMU_CONFIG__seg_2__page 0 +#define R_MMU_CONFIG__seg_1__BITNR 1 +#define R_MMU_CONFIG__seg_1__WIDTH 1 +#define R_MMU_CONFIG__seg_1__seg 1 +#define R_MMU_CONFIG__seg_1__page 0 +#define R_MMU_CONFIG__seg_0__BITNR 0 +#define R_MMU_CONFIG__seg_0__WIDTH 1 +#define R_MMU_CONFIG__seg_0__seg 1 +#define R_MMU_CONFIG__seg_0__page 0 + +#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240) +#define R_MMU_KSEG__seg_f__BITNR 15 +#define R_MMU_KSEG__seg_f__WIDTH 1 +#define R_MMU_KSEG__seg_f__seg 1 +#define R_MMU_KSEG__seg_f__page 0 +#define R_MMU_KSEG__seg_e__BITNR 14 +#define R_MMU_KSEG__seg_e__WIDTH 1 +#define R_MMU_KSEG__seg_e__seg 1 +#define R_MMU_KSEG__seg_e__page 0 +#define R_MMU_KSEG__seg_d__BITNR 13 +#define R_MMU_KSEG__seg_d__WIDTH 1 +#define R_MMU_KSEG__seg_d__seg 1 +#define R_MMU_KSEG__seg_d__page 0 +#define R_MMU_KSEG__seg_c__BITNR 12 +#define R_MMU_KSEG__seg_c__WIDTH 1 +#define R_MMU_KSEG__seg_c__seg 1 +#define R_MMU_KSEG__seg_c__page 0 +#define R_MMU_KSEG__seg_b__BITNR 11 +#define R_MMU_KSEG__seg_b__WIDTH 1 +#define R_MMU_KSEG__seg_b__seg 1 +#define R_MMU_KSEG__seg_b__page 0 +#define R_MMU_KSEG__seg_a__BITNR 10 +#define R_MMU_KSEG__seg_a__WIDTH 1 +#define R_MMU_KSEG__seg_a__seg 1 +#define R_MMU_KSEG__seg_a__page 0 +#define R_MMU_KSEG__seg_9__BITNR 9 +#define R_MMU_KSEG__seg_9__WIDTH 1 +#define R_MMU_KSEG__seg_9__seg 1 +#define R_MMU_KSEG__seg_9__page 0 +#define R_MMU_KSEG__seg_8__BITNR 8 +#define R_MMU_KSEG__seg_8__WIDTH 1 +#define R_MMU_KSEG__seg_8__seg 1 +#define R_MMU_KSEG__seg_8__page 0 +#define R_MMU_KSEG__seg_7__BITNR 7 +#define R_MMU_KSEG__seg_7__WIDTH 1 +#define R_MMU_KSEG__seg_7__seg 1 +#define R_MMU_KSEG__seg_7__page 0 +#define R_MMU_KSEG__seg_6__BITNR 6 +#define R_MMU_KSEG__seg_6__WIDTH 1 +#define R_MMU_KSEG__seg_6__seg 1 +#define R_MMU_KSEG__seg_6__page 0 +#define R_MMU_KSEG__seg_5__BITNR 5 +#define R_MMU_KSEG__seg_5__WIDTH 1 +#define R_MMU_KSEG__seg_5__seg 1 +#define R_MMU_KSEG__seg_5__page 0 +#define R_MMU_KSEG__seg_4__BITNR 4 +#define R_MMU_KSEG__seg_4__WIDTH 1 +#define R_MMU_KSEG__seg_4__seg 1 +#define R_MMU_KSEG__seg_4__page 0 +#define R_MMU_KSEG__seg_3__BITNR 3 +#define R_MMU_KSEG__seg_3__WIDTH 1 +#define R_MMU_KSEG__seg_3__seg 1 +#define R_MMU_KSEG__seg_3__page 0 +#define R_MMU_KSEG__seg_2__BITNR 2 +#define R_MMU_KSEG__seg_2__WIDTH 1 +#define R_MMU_KSEG__seg_2__seg 1 +#define R_MMU_KSEG__seg_2__page 0 +#define R_MMU_KSEG__seg_1__BITNR 1 +#define R_MMU_KSEG__seg_1__WIDTH 1 +#define R_MMU_KSEG__seg_1__seg 1 +#define R_MMU_KSEG__seg_1__page 0 +#define R_MMU_KSEG__seg_0__BITNR 0 +#define R_MMU_KSEG__seg_0__WIDTH 1 +#define R_MMU_KSEG__seg_0__seg 1 +#define R_MMU_KSEG__seg_0__page 0 + +#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242) +#define R_MMU_CTRL__inv_excp__BITNR 2 +#define R_MMU_CTRL__inv_excp__WIDTH 1 +#define R_MMU_CTRL__inv_excp__enable 1 +#define R_MMU_CTRL__inv_excp__disable 0 +#define R_MMU_CTRL__acc_excp__BITNR 1 +#define R_MMU_CTRL__acc_excp__WIDTH 1 +#define R_MMU_CTRL__acc_excp__enable 1 +#define R_MMU_CTRL__acc_excp__disable 0 +#define R_MMU_CTRL__we_excp__BITNR 0 +#define R_MMU_CTRL__we_excp__WIDTH 1 +#define R_MMU_CTRL__we_excp__enable 1 +#define R_MMU_CTRL__we_excp__disable 0 + +#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243) +#define R_MMU_ENABLE__mmu_enable__BITNR 7 +#define R_MMU_ENABLE__mmu_enable__WIDTH 1 +#define R_MMU_ENABLE__mmu_enable__enable 1 +#define R_MMU_ENABLE__mmu_enable__disable 0 + +#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244) +#define R_MMU_KBASE_LO__base_7__BITNR 28 +#define R_MMU_KBASE_LO__base_7__WIDTH 4 +#define R_MMU_KBASE_LO__base_6__BITNR 24 +#define R_MMU_KBASE_LO__base_6__WIDTH 4 +#define R_MMU_KBASE_LO__base_5__BITNR 20 +#define R_MMU_KBASE_LO__base_5__WIDTH 4 +#define R_MMU_KBASE_LO__base_4__BITNR 16 +#define R_MMU_KBASE_LO__base_4__WIDTH 4 +#define R_MMU_KBASE_LO__base_3__BITNR 12 +#define R_MMU_KBASE_LO__base_3__WIDTH 4 +#define R_MMU_KBASE_LO__base_2__BITNR 8 +#define R_MMU_KBASE_LO__base_2__WIDTH 4 +#define R_MMU_KBASE_LO__base_1__BITNR 4 +#define R_MMU_KBASE_LO__base_1__WIDTH 4 +#define R_MMU_KBASE_LO__base_0__BITNR 0 +#define R_MMU_KBASE_LO__base_0__WIDTH 4 + +#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248) +#define R_MMU_KBASE_HI__base_f__BITNR 28 +#define R_MMU_KBASE_HI__base_f__WIDTH 4 +#define R_MMU_KBASE_HI__base_e__BITNR 24 +#define R_MMU_KBASE_HI__base_e__WIDTH 4 +#define R_MMU_KBASE_HI__base_d__BITNR 20 +#define R_MMU_KBASE_HI__base_d__WIDTH 4 +#define R_MMU_KBASE_HI__base_c__BITNR 16 +#define R_MMU_KBASE_HI__base_c__WIDTH 4 +#define R_MMU_KBASE_HI__base_b__BITNR 12 +#define R_MMU_KBASE_HI__base_b__WIDTH 4 +#define R_MMU_KBASE_HI__base_a__BITNR 8 +#define R_MMU_KBASE_HI__base_a__WIDTH 4 +#define R_MMU_KBASE_HI__base_9__BITNR 4 +#define R_MMU_KBASE_HI__base_9__WIDTH 4 +#define R_MMU_KBASE_HI__base_8__BITNR 0 +#define R_MMU_KBASE_HI__base_8__WIDTH 4 + +#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c) +#define R_MMU_CONTEXT__page_id__BITNR 0 +#define R_MMU_CONTEXT__page_id__WIDTH 6 + +#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250) +#define R_MMU_CAUSE__vpn__BITNR 13 +#define R_MMU_CAUSE__vpn__WIDTH 19 +#define R_MMU_CAUSE__miss_excp__BITNR 12 +#define R_MMU_CAUSE__miss_excp__WIDTH 1 +#define R_MMU_CAUSE__miss_excp__yes 1 +#define R_MMU_CAUSE__miss_excp__no 0 +#define R_MMU_CAUSE__inv_excp__BITNR 11 +#define R_MMU_CAUSE__inv_excp__WIDTH 1 +#define R_MMU_CAUSE__inv_excp__yes 1 +#define R_MMU_CAUSE__inv_excp__no 0 +#define R_MMU_CAUSE__acc_excp__BITNR 10 +#define R_MMU_CAUSE__acc_excp__WIDTH 1 +#define R_MMU_CAUSE__acc_excp__yes 1 +#define R_MMU_CAUSE__acc_excp__no 0 +#define R_MMU_CAUSE__we_excp__BITNR 9 +#define R_MMU_CAUSE__we_excp__WIDTH 1 +#define R_MMU_CAUSE__we_excp__yes 1 +#define R_MMU_CAUSE__we_excp__no 0 +#define R_MMU_CAUSE__wr_rd__BITNR 8 +#define R_MMU_CAUSE__wr_rd__WIDTH 1 +#define R_MMU_CAUSE__wr_rd__write 1 +#define R_MMU_CAUSE__wr_rd__read 0 +#define R_MMU_CAUSE__page_id__BITNR 0 +#define R_MMU_CAUSE__page_id__WIDTH 6 + +#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254) +#define R_TLB_SELECT__index__BITNR 0 +#define R_TLB_SELECT__index__WIDTH 6 + +#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258) +#define R_TLB_LO__pfn__BITNR 13 +#define R_TLB_LO__pfn__WIDTH 19 +#define R_TLB_LO__global__BITNR 3 +#define R_TLB_LO__global__WIDTH 1 +#define R_TLB_LO__global__yes 1 +#define R_TLB_LO__global__no 0 +#define R_TLB_LO__valid__BITNR 2 +#define R_TLB_LO__valid__WIDTH 1 +#define R_TLB_LO__valid__yes 1 +#define R_TLB_LO__valid__no 0 +#define R_TLB_LO__kernel__BITNR 1 +#define R_TLB_LO__kernel__WIDTH 1 +#define R_TLB_LO__kernel__yes 1 +#define R_TLB_LO__kernel__no 0 +#define R_TLB_LO__we__BITNR 0 +#define R_TLB_LO__we__WIDTH 1 +#define R_TLB_LO__we__yes 1 +#define R_TLB_LO__we__no 0 + +#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c) +#define R_TLB_HI__vpn__BITNR 13 +#define R_TLB_HI__vpn__WIDTH 19 +#define R_TLB_HI__page_id__BITNR 0 +#define R_TLB_HI__page_id__WIDTH 6 + +/* +!* Syncrounous serial port registers +!*/ + +#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL1_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__underflow__no 0 +#define R_SYNC_SERIAL1_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__overrun__no 0 +#define R_SYNC_SERIAL1_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL1_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL1_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c) +#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c) +#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068) +#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL1_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL1_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__error__normal 0 +#define R_SYNC_SERIAL1_CTRL__error__ignore 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL1_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL1_CTRL__def_out0__low 0 + +#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32 + +#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16 + +#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0 +#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8 + +#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15 +#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__rec_status__running 0 +#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14 +#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1 +#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13 +#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0 +#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12 +#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_1__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_1__high 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11 +#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__pin_0__low 0 +#define R_SYNC_SERIAL3_STATUS__pin_0__high 1 +#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10 +#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__underflow__no 0 +#define R_SYNC_SERIAL3_STATUS__underflow__yes 1 +#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9 +#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__overrun__no 0 +#define R_SYNC_SERIAL3_STATUS__overrun__yes 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8 +#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1 +#define R_SYNC_SERIAL3_STATUS__data_avail__no 0 +#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1 +#define R_SYNC_SERIAL3_STATUS__data__BITNR 0 +#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8 + +#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32 + +#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c) +#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16 + +#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c) +#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0 +#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8 + +#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078) +#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28 +#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13 +#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14 +#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15 +#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27 +#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1 +#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0 +#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24 +#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_output 0 +#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1 +#define R_SYNC_SERIAL3_CTRL__mode__master_input 2 +#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3 +#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4 +#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5 +#define R_SYNC_SERIAL3_CTRL__error__BITNR 23 +#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__error__normal 0 +#define R_SYNC_SERIAL3_CTRL__error__ignore 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22 +#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21 +#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0 +#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2 +#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3 +#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18 +#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__f_sync__on 0 +#define R_SYNC_SERIAL3_CTRL__f_sync__off 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17 +#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16 +#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0 +#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15 +#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0 +#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14 +#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0 +#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11 +#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0 +#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1 +#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2 +#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3 +#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4 +#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10 +#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0 +#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9 +#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0 +#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0 +#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0 +#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4 +#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3 +#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2 +#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0 +#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0 +#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__high 1 +#define R_SYNC_SERIAL3_CTRL__def_out0__low 0 + diff --git a/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h new file mode 100644 index 00000000000..5517f04153a --- /dev/null +++ b/arch/cris/include/uapi/arch-v10/arch/sv_addr_ag.h @@ -0,0 +1,139 @@ +/*!************************************************************************** +*! +*! MACROS: +*! IO_MASK(reg,field) +*! IO_STATE(reg,field,state) +*! IO_EXTRACT(reg,field,val) +*! IO_STATE_VALUE(reg,field,state) +*! IO_BITNR(reg,field) +*! IO_WIDTH(reg,field) +*! IO_FIELD(reg,field,val) +*! IO_RD(reg) +*! All moderegister addresses and fields of these. +*! +*!**************************************************************************/ + +#ifndef __sv_addr_ag_h__ +#define __sv_addr_ag_h__ + + +#define __test_sv_addr__ 0 + +/*------------------------------------------------------------ +!* General macros to manipulate moderegisters. +!*-----------------------------------------------------------*/ + +/* IO_MASK returns a mask for a specified bitfield in a register. + Note that this macro doesn't work when field width is 32 bits. */ +#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) +#define IO_MASK_(reg_, field_) \ + ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) + +/* IO_STATE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Shifted to correct position) */ +#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) +#define IO_STATE_(reg_, field_, _state) \ + ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) + +/* IO_EXTRACT returns the masked and shifted value corresponding to the + bitfield can have. */ +#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) +#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ + - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) + +/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic + states that the bitfield can have. (Not shifted) */ +#define IO_STATE_VALUE(reg, field, state) \ + IO_STATE_VALUE_ (reg##_, field##_, _##state) +#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) + +/* IO_FIELD shifts the val parameter to be aligned with the bitfield + specified. */ +#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) +#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) + +/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is + LSB and the returned bitnumber is LSB of the field. */ +#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) +#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) + +/* IO_WIDTH returns the width, in bits, of a bitfield. */ +#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) +#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) + +/*--- Obsolete. Kept for backw compatibility. ---*/ +/* Reads (or writes) a byte/uword/udword from the specified mode + register. */ +#define IO_RD(reg) (*(volatile u32*)(reg)) +#define IO_RD_B(reg) (*(volatile u8*)(reg)) +#define IO_RD_W(reg) (*(volatile u16*)(reg)) +#define IO_RD_D(reg) (*(volatile u32*)(reg)) + +/*------------------------------------------------------------ +!* Start addresses of the different memory areas. +!*-----------------------------------------------------------*/ + +#define MEM_CSE0_START (0x00000000) +#define MEM_CSE0_SIZE (0x04000000) +#define MEM_CSE1_START (0x04000000) +#define MEM_CSE1_SIZE (0x04000000) +#define MEM_CSR0_START (0x08000000) +#define MEM_CSR1_START (0x0c000000) +#define MEM_CSP0_START (0x10000000) +#define MEM_CSP1_START (0x14000000) +#define MEM_CSP2_START (0x18000000) +#define MEM_CSP3_START (0x1c000000) +#define MEM_CSP4_START (0x20000000) +#define MEM_CSP5_START (0x24000000) +#define MEM_CSP6_START (0x28000000) +#define MEM_CSP7_START (0x2c000000) +#define MEM_DRAM_START (0x40000000) + +#define MEM_NON_CACHEABLE (0x80000000) + +/*------------------------------------------------------------ +!* Type casts used in mode register macros, making pointer +!* dereferencing possible. Empty in assembler. +!*-----------------------------------------------------------*/ + +#ifndef __ASSEMBLER__ +# define IO_TYPECAST_UDWORD (volatile u32*) +# define IO_TYPECAST_RO_UDWORD (const volatile u32*) +# define IO_TYPECAST_UWORD (volatile u16*) +# define IO_TYPECAST_RO_UWORD (const volatile u16*) +# define IO_TYPECAST_BYTE (volatile u8*) +# define IO_TYPECAST_RO_BYTE (const volatile u8*) +#else +# define IO_TYPECAST_UDWORD +# define IO_TYPECAST_RO_UDWORD +# define IO_TYPECAST_UWORD +# define IO_TYPECAST_RO_UWORD +# define IO_TYPECAST_BYTE +# define IO_TYPECAST_RO_BYTE +#endif + +/*------------------------------------------------------------*/ + +#include + +#if __test_sv_addr__ +/* IO_MASK( R_BUS_CONFIG , CE ) */ +IO_MASK( R_WAITSTATES , SRAM_WS ) +IO_MASK( R_TEST , W32 ) + +IO_STATE( R_BUS_CONFIG, CE, DISABLE ) +IO_STATE( R_BUS_CONFIG, CE, ENABLE ) + +IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) + +IO_MASK( R_DRAM_TIMING, REF ) + +IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) + +IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) + == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) +#endif + + +#endif /* ifndef __sv_addr_ag_h__ */ + diff --git a/arch/cris/include/uapi/arch-v10/arch/svinto.h b/arch/cris/include/uapi/arch-v10/arch/svinto.h new file mode 100644 index 00000000000..da5c1527265 --- /dev/null +++ b/arch/cris/include/uapi/arch-v10/arch/svinto.h @@ -0,0 +1,64 @@ +#ifndef _ASM_CRIS_SVINTO_H +#define _ASM_CRIS_SVINTO_H + +#include + +extern unsigned int genconfig_shadow; /* defined and set in head.S */ + +/* dma stuff */ + +enum { /* Available in: */ + d_eol = (1 << 0), /* flags */ + d_eop = (1 << 1), /* flags & status */ + d_wait = (1 << 2), /* flags */ + d_int = (1 << 3), /* flags */ + d_txerr = (1 << 4), /* flags */ + d_stop = (1 << 4), /* status */ + d_ecp = (1 << 4), /* flags & status */ + d_pri = (1 << 5), /* flags & status */ + d_alignerr = (1 << 6), /* status */ + d_crcerr = (1 << 7) /* status */ +}; + +/* Do remember that DMA does not go through the MMU and needs + * a real physical address, not an address virtually mapped or + * paged. Therefore the buf/next ptrs below are unsigned long instead + * of void * to give a warning if you try to put a pointer directly + * to them instead of going through virt_to_phys/phys_to_virt. + */ + +typedef struct etrax_dma_descr { + unsigned short sw_len; /* 0-1 */ + unsigned short ctrl; /* 2-3 */ + unsigned long next; /* 4-7 */ + unsigned long buf; /* 8-11 */ + unsigned short hw_len; /* 12-13 */ + unsigned char status; /* 14 */ + unsigned char fifo_len; /* 15 */ +} etrax_dma_descr; + + +/* Use this for constant numbers only */ +#define RESET_DMA_NUM( n ) \ + *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset ) + +/* Use this for constant numbers or symbols, + * having two macros makes it possible to use constant expressions. + */ +#define RESET_DMA( n ) RESET_DMA_NUM( n ) + + +/* Use this for constant numbers only */ +#define WAIT_DMA_NUM( n ) \ + while( (*R_DMA_CH##n##_CMD & IO_MASK( R_DMA_CH0_CMD, cmd )) != \ + IO_STATE( R_DMA_CH0_CMD, cmd, hold ) ) + +/* Use this for constant numbers or symbols + * having two macros makes it possible to use constant expressions. + */ +#define WAIT_DMA( n ) WAIT_DMA_NUM( n ) + +extern void prepare_rx_descriptor(struct etrax_dma_descr *desc); +extern void flush_etrax_cache(void); + +#endif diff --git a/arch/cris/include/uapi/arch-v10/arch/user.h b/arch/cris/include/uapi/arch-v10/arch/user.h new file mode 100644 index 00000000000..9303ea77c91 --- /dev/null +++ b/arch/cris/include/uapi/arch-v10/arch/user.h @@ -0,0 +1,46 @@ +#ifndef __ASM_CRIS_ARCH_USER_H +#define __ASM_CRIS_ARCH_USER_H + +/* User mode registers, used for core dumps. In order to keep ELF_NGREG + sensible we let all registers be 32 bits. The csr registers are included + for future use. */ +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* Stack pointer. */ + unsigned long pc; /* Program counter. */ + unsigned long p0; /* Constant zero (only 8 bits). */ + unsigned long vr; /* Version register (only 8 bits). */ + unsigned long p2; /* Reserved. */ + unsigned long p3; /* Reserved. */ + unsigned long p4; /* Constant zero (only 16 bits). */ + unsigned long ccr; /* Condition code register (only 16 bits). */ + unsigned long p6; /* Reserved. */ + unsigned long mof; /* Multiply overflow register. */ + unsigned long p8; /* Constant zero. */ + unsigned long ibr; /* Not accessible. */ + unsigned long irp; /* Not accessible. */ + unsigned long srp; /* Subroutine return pointer. */ + unsigned long bar; /* Not accessible. */ + unsigned long dccr; /* Dword condition code register. */ + unsigned long brp; /* Not accessible. */ + unsigned long usp; /* User-mode stack pointer. Same as sp when + in user mode. */ + unsigned long csrinstr; /* Internal status registers. */ + unsigned long csraddr; + unsigned long csrdata; +}; + +#endif -- cgit v1.2.3-70-g09d2 From 98d848ea4c017101f7e4a85917d0e0991f388cd8 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 9 Oct 2012 09:46:42 +0100 Subject: UAPI: (Scripted) Disintegrate arch/cris/include/arch-v32/arch Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones --- arch/cris/include/arch-v32/arch/Kbuild | 2 - arch/cris/include/arch-v32/arch/cryptocop.h | 116 +-------------------- arch/cris/include/arch-v32/arch/user.h | 41 -------- arch/cris/include/uapi/arch-v32/arch/Kbuild | 2 + arch/cris/include/uapi/arch-v32/arch/cryptocop.h | 122 +++++++++++++++++++++++ arch/cris/include/uapi/arch-v32/arch/user.h | 41 ++++++++ 6 files changed, 166 insertions(+), 158 deletions(-) delete mode 100644 arch/cris/include/arch-v32/arch/user.h create mode 100644 arch/cris/include/uapi/arch-v32/arch/cryptocop.h create mode 100644 arch/cris/include/uapi/arch-v32/arch/user.h (limited to 'arch') diff --git a/arch/cris/include/arch-v32/arch/Kbuild b/arch/cris/include/arch-v32/arch/Kbuild index 35f2fc4f993..e69de29bb2d 100644 --- a/arch/cris/include/arch-v32/arch/Kbuild +++ b/arch/cris/include/arch-v32/arch/Kbuild @@ -1,2 +0,0 @@ -header-y += user.h -header-y += cryptocop.h diff --git a/arch/cris/include/arch-v32/arch/cryptocop.h b/arch/cris/include/arch-v32/arch/cryptocop.h index e1cd83dfabb..716e434e926 100644 --- a/arch/cris/include/arch-v32/arch/cryptocop.h +++ b/arch/cris/include/arch-v32/arch/cryptocop.h @@ -2,124 +2,12 @@ * The device /dev/cryptocop is accessible using this driver using * CRYPTOCOP_MAJOR (254) and minor number 0. */ - #ifndef CRYPTOCOP_H #define CRYPTOCOP_H -#include - - -#define CRYPTOCOP_SESSION_ID_NONE (0) - -typedef unsigned long long int cryptocop_session_id; - -/* cryptocop ioctls */ -#define ETRAXCRYPTOCOP_IOCTYPE (250) - -#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) -#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) -#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) -#define CRYPTOCOP_IO_MAXNR (3) - -typedef enum { - cryptocop_cipher_des = 0, - cryptocop_cipher_3des = 1, - cryptocop_cipher_aes = 2, - cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ - cryptocop_cipher_none -} cryptocop_cipher_type; - -typedef enum { - cryptocop_digest_sha1 = 0, - cryptocop_digest_md5 = 1, - cryptocop_digest_none -} cryptocop_digest_type; - -typedef enum { - cryptocop_csum_le = 0, - cryptocop_csum_be = 1, - cryptocop_csum_none -} cryptocop_csum_type; - -typedef enum { - cryptocop_cipher_mode_ecb = 0, - cryptocop_cipher_mode_cbc, - cryptocop_cipher_mode_none -} cryptocop_cipher_mode; - -typedef enum { - cryptocop_3des_eee = 0, - cryptocop_3des_eed = 1, - cryptocop_3des_ede = 2, - cryptocop_3des_edd = 3, - cryptocop_3des_dee = 4, - cryptocop_3des_ded = 5, - cryptocop_3des_dde = 6, - cryptocop_3des_ddd = 7 -} cryptocop_3des_mode; - -/* Usermode accessible (ioctl) operations. */ -struct strcop_session_op{ - cryptocop_session_id ses_id; - - cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ - - cryptocop_cipher_mode cmode; /* ECB, CBC, none */ - cryptocop_3des_mode des3_mode; - - cryptocop_digest_type digest; /* MD5, SHA1, none */ - - cryptocop_csum_type csum; /* BE, LE, none */ - - unsigned char *key; - size_t keylen; -}; - -#define CRYPTOCOP_CSUM_LENGTH (2) -#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ -#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ -#define CRYPTOCOP_MAX_KEY_LENGTH (32) - -struct strcop_crypto_op{ - cryptocop_session_id ses_id; - - /* Indata. */ - unsigned char *indata; - size_t inlen; /* Total indata length. */ - - /* Cipher configuration. */ - unsigned char do_cipher:1; - unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ - unsigned char cipher_explicit:1; - size_t cipher_start; - size_t cipher_len; - /* cipher_iv is used if do_cipher and cipher_explicit and the cipher - mode is CBC. The length is controlled by the type of cipher, - e.g. DES/3DES 8 octets and AES 16 octets. */ - unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; - /* Outdata. */ - unsigned char *cipher_outdata; - size_t cipher_outlen; - - /* digest configuration. */ - unsigned char do_digest:1; - size_t digest_start; - size_t digest_len; - /* Outdata. The actual length is determined by the type of the digest. */ - unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; - - /* Checksum configuration. */ - unsigned char do_csum:1; - size_t csum_start; - size_t csum_len; - /* Outdata. */ - unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; -}; +#include - -#ifdef __KERNEL__ - /********** The API to use from inside the kernel. ************/ #include @@ -267,6 +155,4 @@ int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation); int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation); -#endif /* __KERNEL__ */ - #endif /* CRYPTOCOP_H */ diff --git a/arch/cris/include/arch-v32/arch/user.h b/arch/cris/include/arch-v32/arch/user.h deleted file mode 100644 index 03fa1f3c3c0..00000000000 --- a/arch/cris/include/arch-v32/arch/user.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CRIS_ARCH_USER_H -#define _ASM_CRIS_ARCH_USER_H - -/* User-mode register used for core dumps. */ - -struct user_regs_struct { - unsigned long r0; /* General registers. */ - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long sp; /* R14, Stack pointer. */ - unsigned long acr; /* R15, Address calculation register. */ - unsigned long bz; /* P0, Constant zero (8-bits). */ - unsigned long vr; /* P1, Version register (8-bits). */ - unsigned long pid; /* P2, Process ID (8-bits). */ - unsigned long srs; /* P3, Support register select (8-bits). */ - unsigned long wz; /* P4, Constant zero (16-bits). */ - unsigned long exs; /* P5, Exception status. */ - unsigned long eda; /* P6, Exception data address. */ - unsigned long mof; /* P7, Multiply overflow regiter. */ - unsigned long dz; /* P8, Constant zero (32-bits). */ - unsigned long ebp; /* P9, Exception base pointer. */ - unsigned long erp; /* P10, Exception return pointer. */ - unsigned long srp; /* P11, Subroutine return pointer. */ - unsigned long nrp; /* P12, NMI return pointer. */ - unsigned long ccs; /* P13, Condition code stack. */ - unsigned long usp; /* P14, User mode stack pointer. */ - unsigned long spc; /* P15, Single step PC. */ -}; - -#endif /* _ASM_CRIS_ARCH_USER_H */ diff --git a/arch/cris/include/uapi/arch-v32/arch/Kbuild b/arch/cris/include/uapi/arch-v32/arch/Kbuild index aafaa5aa54d..59efffd16b6 100644 --- a/arch/cris/include/uapi/arch-v32/arch/Kbuild +++ b/arch/cris/include/uapi/arch-v32/arch/Kbuild @@ -1 +1,3 @@ # UAPI Header export list +header-y += cryptocop.h +header-y += user.h diff --git a/arch/cris/include/uapi/arch-v32/arch/cryptocop.h b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h new file mode 100644 index 00000000000..694fd13ce1c --- /dev/null +++ b/arch/cris/include/uapi/arch-v32/arch/cryptocop.h @@ -0,0 +1,122 @@ +/* + * The device /dev/cryptocop is accessible using this driver using + * CRYPTOCOP_MAJOR (254) and minor number 0. + */ + +#ifndef _UAPICRYPTOCOP_H +#define _UAPICRYPTOCOP_H + +#include + + +#define CRYPTOCOP_SESSION_ID_NONE (0) + +typedef unsigned long long int cryptocop_session_id; + +/* cryptocop ioctls */ +#define ETRAXCRYPTOCOP_IOCTYPE (250) + +#define CRYPTOCOP_IO_CREATE_SESSION _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 1, struct strcop_session_op) +#define CRYPTOCOP_IO_CLOSE_SESSION _IOW(ETRAXCRYPTOCOP_IOCTYPE, 2, struct strcop_session_op) +#define CRYPTOCOP_IO_PROCESS_OP _IOWR(ETRAXCRYPTOCOP_IOCTYPE, 3, struct strcop_crypto_op) +#define CRYPTOCOP_IO_MAXNR (3) + +typedef enum { + cryptocop_cipher_des = 0, + cryptocop_cipher_3des = 1, + cryptocop_cipher_aes = 2, + cryptocop_cipher_m2m = 3, /* mem2mem is essentially a NULL cipher with blocklength=1 */ + cryptocop_cipher_none +} cryptocop_cipher_type; + +typedef enum { + cryptocop_digest_sha1 = 0, + cryptocop_digest_md5 = 1, + cryptocop_digest_none +} cryptocop_digest_type; + +typedef enum { + cryptocop_csum_le = 0, + cryptocop_csum_be = 1, + cryptocop_csum_none +} cryptocop_csum_type; + +typedef enum { + cryptocop_cipher_mode_ecb = 0, + cryptocop_cipher_mode_cbc, + cryptocop_cipher_mode_none +} cryptocop_cipher_mode; + +typedef enum { + cryptocop_3des_eee = 0, + cryptocop_3des_eed = 1, + cryptocop_3des_ede = 2, + cryptocop_3des_edd = 3, + cryptocop_3des_dee = 4, + cryptocop_3des_ded = 5, + cryptocop_3des_dde = 6, + cryptocop_3des_ddd = 7 +} cryptocop_3des_mode; + +/* Usermode accessible (ioctl) operations. */ +struct strcop_session_op{ + cryptocop_session_id ses_id; + + cryptocop_cipher_type cipher; /* AES, DES, 3DES, m2m, none */ + + cryptocop_cipher_mode cmode; /* ECB, CBC, none */ + cryptocop_3des_mode des3_mode; + + cryptocop_digest_type digest; /* MD5, SHA1, none */ + + cryptocop_csum_type csum; /* BE, LE, none */ + + unsigned char *key; + size_t keylen; +}; + +#define CRYPTOCOP_CSUM_LENGTH (2) +#define CRYPTOCOP_MAX_DIGEST_LENGTH (20) /* SHA-1 20, MD5 16 */ +#define CRYPTOCOP_MAX_IV_LENGTH (16) /* (3)DES==8, AES == 16 */ +#define CRYPTOCOP_MAX_KEY_LENGTH (32) + +struct strcop_crypto_op{ + cryptocop_session_id ses_id; + + /* Indata. */ + unsigned char *indata; + size_t inlen; /* Total indata length. */ + + /* Cipher configuration. */ + unsigned char do_cipher:1; + unsigned char decrypt:1; /* 1 == decrypt, 0 == encrypt */ + unsigned char cipher_explicit:1; + size_t cipher_start; + size_t cipher_len; + /* cipher_iv is used if do_cipher and cipher_explicit and the cipher + mode is CBC. The length is controlled by the type of cipher, + e.g. DES/3DES 8 octets and AES 16 octets. */ + unsigned char cipher_iv[CRYPTOCOP_MAX_IV_LENGTH]; + /* Outdata. */ + unsigned char *cipher_outdata; + size_t cipher_outlen; + + /* digest configuration. */ + unsigned char do_digest:1; + size_t digest_start; + size_t digest_len; + /* Outdata. The actual length is determined by the type of the digest. */ + unsigned char digest[CRYPTOCOP_MAX_DIGEST_LENGTH]; + + /* Checksum configuration. */ + unsigned char do_csum:1; + size_t csum_start; + size_t csum_len; + /* Outdata. */ + unsigned char csum[CRYPTOCOP_CSUM_LENGTH]; +}; + + + + +#endif /* _UAPICRYPTOCOP_H */ diff --git a/arch/cris/include/uapi/arch-v32/arch/user.h b/arch/cris/include/uapi/arch-v32/arch/user.h new file mode 100644 index 00000000000..03fa1f3c3c0 --- /dev/null +++ b/arch/cris/include/uapi/arch-v32/arch/user.h @@ -0,0 +1,41 @@ +#ifndef _ASM_CRIS_ARCH_USER_H +#define _ASM_CRIS_ARCH_USER_H + +/* User-mode register used for core dumps. */ + +struct user_regs_struct { + unsigned long r0; /* General registers. */ + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long r11; + unsigned long r12; + unsigned long r13; + unsigned long sp; /* R14, Stack pointer. */ + unsigned long acr; /* R15, Address calculation register. */ + unsigned long bz; /* P0, Constant zero (8-bits). */ + unsigned long vr; /* P1, Version register (8-bits). */ + unsigned long pid; /* P2, Process ID (8-bits). */ + unsigned long srs; /* P3, Support register select (8-bits). */ + unsigned long wz; /* P4, Constant zero (16-bits). */ + unsigned long exs; /* P5, Exception status. */ + unsigned long eda; /* P6, Exception data address. */ + unsigned long mof; /* P7, Multiply overflow regiter. */ + unsigned long dz; /* P8, Constant zero (32-bits). */ + unsigned long ebp; /* P9, Exception base pointer. */ + unsigned long erp; /* P10, Exception return pointer. */ + unsigned long srp; /* P11, Subroutine return pointer. */ + unsigned long nrp; /* P12, NMI return pointer. */ + unsigned long ccs; /* P13, Condition code stack. */ + unsigned long usp; /* P14, User mode stack pointer. */ + unsigned long spc; /* P15, Single step PC. */ +}; + +#endif /* _ASM_CRIS_ARCH_USER_H */ -- cgit v1.2.3-70-g09d2 From e717abac8a9f65eee6de3bb37e10c6916bced483 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 9 Oct 2012 09:46:45 +0100 Subject: UAPI: (Scripted) Disintegrate arch/cris/include/asm Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones --- arch/cris/include/asm/Kbuild | 5 - arch/cris/include/asm/auxvec.h | 4 - arch/cris/include/asm/bitsperlong.h | 1 - arch/cris/include/asm/byteorder.h | 8 - arch/cris/include/asm/errno.h | 6 - arch/cris/include/asm/ethernet.h | 21 -- arch/cris/include/asm/etraxgpio.h | 239 --------------------- arch/cris/include/asm/fcntl.h | 1 - arch/cris/include/asm/ioctl.h | 1 - arch/cris/include/asm/ioctls.h | 11 - arch/cris/include/asm/ipcbuf.h | 1 - arch/cris/include/asm/mman.h | 1 - arch/cris/include/asm/msgbuf.h | 33 --- arch/cris/include/asm/param.h | 10 - arch/cris/include/asm/poll.h | 1 - arch/cris/include/asm/posix_types.h | 35 ---- arch/cris/include/asm/ptrace.h | 5 +- arch/cris/include/asm/resource.h | 6 - arch/cris/include/asm/rs485.h | 18 -- arch/cris/include/asm/sembuf.h | 25 --- arch/cris/include/asm/setup.h | 6 - arch/cris/include/asm/shmbuf.h | 42 ---- arch/cris/include/asm/sigcontext.h | 24 --- arch/cris/include/asm/siginfo.h | 6 - arch/cris/include/asm/signal.h | 122 +---------- arch/cris/include/asm/socket.h | 76 ------- arch/cris/include/asm/sockios.h | 13 -- arch/cris/include/asm/stat.h | 81 -------- arch/cris/include/asm/statfs.h | 6 - arch/cris/include/asm/swab.h | 3 +- arch/cris/include/asm/sync_serial.h | 132 ------------ arch/cris/include/asm/termbits.h | 235 --------------------- arch/cris/include/asm/termios.h | 43 +--- arch/cris/include/asm/types.h | 5 +- arch/cris/include/asm/unistd.h | 342 +----------------------------- arch/cris/include/uapi/asm/Kbuild | 34 +++ arch/cris/include/uapi/asm/auxvec.h | 4 + arch/cris/include/uapi/asm/bitsperlong.h | 1 + arch/cris/include/uapi/asm/byteorder.h | 8 + arch/cris/include/uapi/asm/errno.h | 6 + arch/cris/include/uapi/asm/ethernet.h | 21 ++ arch/cris/include/uapi/asm/etraxgpio.h | 239 +++++++++++++++++++++ arch/cris/include/uapi/asm/fcntl.h | 1 + arch/cris/include/uapi/asm/ioctl.h | 1 + arch/cris/include/uapi/asm/ioctls.h | 11 + arch/cris/include/uapi/asm/ipcbuf.h | 1 + arch/cris/include/uapi/asm/mman.h | 1 + arch/cris/include/uapi/asm/msgbuf.h | 33 +++ arch/cris/include/uapi/asm/param.h | 10 + arch/cris/include/uapi/asm/poll.h | 1 + arch/cris/include/uapi/asm/posix_types.h | 35 ++++ arch/cris/include/uapi/asm/ptrace.h | 1 + arch/cris/include/uapi/asm/resource.h | 6 + arch/cris/include/uapi/asm/rs485.h | 18 ++ arch/cris/include/uapi/asm/sembuf.h | 25 +++ arch/cris/include/uapi/asm/setup.h | 6 + arch/cris/include/uapi/asm/shmbuf.h | 42 ++++ arch/cris/include/uapi/asm/sigcontext.h | 24 +++ arch/cris/include/uapi/asm/siginfo.h | 6 + arch/cris/include/uapi/asm/signal.h | 122 +++++++++++ arch/cris/include/uapi/asm/socket.h | 76 +++++++ arch/cris/include/uapi/asm/sockios.h | 13 ++ arch/cris/include/uapi/asm/stat.h | 81 ++++++++ arch/cris/include/uapi/asm/statfs.h | 6 + arch/cris/include/uapi/asm/swab.h | 0 arch/cris/include/uapi/asm/sync_serial.h | 132 ++++++++++++ arch/cris/include/uapi/asm/termbits.h | 235 +++++++++++++++++++++ arch/cris/include/uapi/asm/termios.h | 45 ++++ arch/cris/include/uapi/asm/types.h | 1 + arch/cris/include/uapi/asm/unistd.h | 344 +++++++++++++++++++++++++++++++ 70 files changed, 1596 insertions(+), 1562 deletions(-) delete mode 100644 arch/cris/include/asm/auxvec.h delete mode 100644 arch/cris/include/asm/bitsperlong.h delete mode 100644 arch/cris/include/asm/byteorder.h delete mode 100644 arch/cris/include/asm/errno.h delete mode 100644 arch/cris/include/asm/ethernet.h delete mode 100644 arch/cris/include/asm/etraxgpio.h delete mode 100644 arch/cris/include/asm/fcntl.h delete mode 100644 arch/cris/include/asm/ioctl.h delete mode 100644 arch/cris/include/asm/ioctls.h delete mode 100644 arch/cris/include/asm/ipcbuf.h delete mode 100644 arch/cris/include/asm/mman.h delete mode 100644 arch/cris/include/asm/msgbuf.h delete mode 100644 arch/cris/include/asm/param.h delete mode 100644 arch/cris/include/asm/poll.h delete mode 100644 arch/cris/include/asm/posix_types.h delete mode 100644 arch/cris/include/asm/resource.h delete mode 100644 arch/cris/include/asm/rs485.h delete mode 100644 arch/cris/include/asm/sembuf.h delete mode 100644 arch/cris/include/asm/setup.h delete mode 100644 arch/cris/include/asm/shmbuf.h delete mode 100644 arch/cris/include/asm/sigcontext.h delete mode 100644 arch/cris/include/asm/siginfo.h delete mode 100644 arch/cris/include/asm/socket.h delete mode 100644 arch/cris/include/asm/sockios.h delete mode 100644 arch/cris/include/asm/stat.h delete mode 100644 arch/cris/include/asm/statfs.h delete mode 100644 arch/cris/include/asm/sync_serial.h delete mode 100644 arch/cris/include/asm/termbits.h create mode 100644 arch/cris/include/uapi/asm/auxvec.h create mode 100644 arch/cris/include/uapi/asm/bitsperlong.h create mode 100644 arch/cris/include/uapi/asm/byteorder.h create mode 100644 arch/cris/include/uapi/asm/errno.h create mode 100644 arch/cris/include/uapi/asm/ethernet.h create mode 100644 arch/cris/include/uapi/asm/etraxgpio.h create mode 100644 arch/cris/include/uapi/asm/fcntl.h create mode 100644 arch/cris/include/uapi/asm/ioctl.h create mode 100644 arch/cris/include/uapi/asm/ioctls.h create mode 100644 arch/cris/include/uapi/asm/ipcbuf.h create mode 100644 arch/cris/include/uapi/asm/mman.h create mode 100644 arch/cris/include/uapi/asm/msgbuf.h create mode 100644 arch/cris/include/uapi/asm/param.h create mode 100644 arch/cris/include/uapi/asm/poll.h create mode 100644 arch/cris/include/uapi/asm/posix_types.h create mode 100644 arch/cris/include/uapi/asm/ptrace.h create mode 100644 arch/cris/include/uapi/asm/resource.h create mode 100644 arch/cris/include/uapi/asm/rs485.h create mode 100644 arch/cris/include/uapi/asm/sembuf.h create mode 100644 arch/cris/include/uapi/asm/setup.h create mode 100644 arch/cris/include/uapi/asm/shmbuf.h create mode 100644 arch/cris/include/uapi/asm/sigcontext.h create mode 100644 arch/cris/include/uapi/asm/siginfo.h create mode 100644 arch/cris/include/uapi/asm/signal.h create mode 100644 arch/cris/include/uapi/asm/socket.h create mode 100644 arch/cris/include/uapi/asm/sockios.h create mode 100644 arch/cris/include/uapi/asm/stat.h create mode 100644 arch/cris/include/uapi/asm/statfs.h create mode 100644 arch/cris/include/uapi/asm/swab.h create mode 100644 arch/cris/include/uapi/asm/sync_serial.h create mode 100644 arch/cris/include/uapi/asm/termbits.h create mode 100644 arch/cris/include/uapi/asm/termios.h create mode 100644 arch/cris/include/uapi/asm/types.h create mode 100644 arch/cris/include/uapi/asm/unistd.h (limited to 'arch') diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild index a8eab26a1ec..9fa0059df4c 100644 --- a/arch/cris/include/asm/Kbuild +++ b/arch/cris/include/asm/Kbuild @@ -1,11 +1,6 @@ -include include/asm-generic/Kbuild.asm header-y += arch-v10/ header-y += arch-v32/ -header-y += ethernet.h -header-y += etraxgpio.h -header-y += rs485.h -header-y += sync_serial.h generic-y += clkdev.h diff --git a/arch/cris/include/asm/auxvec.h b/arch/cris/include/asm/auxvec.h deleted file mode 100644 index cb30b01bf19..00000000000 --- a/arch/cris/include/asm/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMCRIS_AUXVEC_H -#define __ASMCRIS_AUXVEC_H - -#endif diff --git a/arch/cris/include/asm/bitsperlong.h b/arch/cris/include/asm/bitsperlong.h deleted file mode 100644 index 6dc0bb0c13b..00000000000 --- a/arch/cris/include/asm/bitsperlong.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/byteorder.h b/arch/cris/include/asm/byteorder.h deleted file mode 100644 index bcd189798e2..00000000000 --- a/arch/cris/include/asm/byteorder.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _CRIS_BYTEORDER_H -#define _CRIS_BYTEORDER_H - -#include - -#endif - - diff --git a/arch/cris/include/asm/errno.h b/arch/cris/include/asm/errno.h deleted file mode 100644 index 2bf5eb5fa77..00000000000 --- a/arch/cris/include/asm/errno.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_ERRNO_H -#define _CRIS_ERRNO_H - -#include - -#endif diff --git a/arch/cris/include/asm/ethernet.h b/arch/cris/include/asm/ethernet.h deleted file mode 100644 index 4d58652c3a4..00000000000 --- a/arch/cris/include/asm/ethernet.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * ioctl defines for ethernet driver - * - * Copyright (c) 2001 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef _CRIS_ETHERNET_H -#define _CRIS_ETHERNET_H -#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ -#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ -#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ -#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ -#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ -#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ -#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ -#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ -#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 -#endif /* _CRIS_ETHERNET_H */ diff --git a/arch/cris/include/asm/etraxgpio.h b/arch/cris/include/asm/etraxgpio.h deleted file mode 100644 index 461c089db76..00000000000 --- a/arch/cris/include/asm/etraxgpio.h +++ /dev/null @@ -1,239 +0,0 @@ -/* - * The following devices are accessible using this driver using - * GPIO_MAJOR (120) and a couple of minor numbers. - * - * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/gpiog minor 3 - * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG - * g1-g7 and g25-g31 is both input and outputs but on different pins - * Also note that some bits change pins depending on what interfaces - * are enabled. - * - * For ETRAX FS (CONFIG_ETRAXFS): - * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction - * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction - * /dev/leds minor 2, Access to leds depending on kernelconfig - * - * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): - * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction - * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction - * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction - * /dev/gpiod minor 4, 32 bit GPIO, input only - * /dev/leds minor 2, Access to leds depending on kernelconfig - * /dev/pwm0 minor 16, PWM channel 0 on PA30 - * /dev/pwm1 minor 17, PWM channel 1 on PA31 - * /dev/pwm2 minor 18, PWM channel 2 on PB26 - * /dev/ppwm minor 19, PPWM channel - * - */ -#ifndef _ASM_ETRAXGPIO_H -#define _ASM_ETRAXGPIO_H - -#define GPIO_MINOR_FIRST 0 - -#define ETRAXGPIO_IOCTYPE 43 - -/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ -#ifdef CONFIG_ETRAX_ARCH_V10 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_G 3 -#define GPIO_MINOR_LAST 3 -#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST -#endif - -#ifdef CONFIG_ETRAXFS -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#define GPIO_MINOR_E 5 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 5 -#endif -#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST -#endif - -#ifdef CONFIG_CRIS_MACH_ARTPEC3 -#define GPIO_MINOR_A 0 -#define GPIO_MINOR_B 1 -#define GPIO_MINOR_LEDS 2 -#define GPIO_MINOR_C 3 -#define GPIO_MINOR_D 4 -#ifdef CONFIG_ETRAX_VIRTUAL_GPIO -#define GPIO_MINOR_V 6 -#define GPIO_MINOR_LAST 6 -#else -#define GPIO_MINOR_LAST 4 -#endif -#define GPIO_MINOR_FIRST_PWM 16 -#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0) -#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1) -#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2) -#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3) -#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM -#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM -#endif - - - -/* supported ioctl _IOC_NR's */ - -#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ -#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ -#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ - -/* the alarm is waited for by select() */ - -#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ -#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ -#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ - -/* LED ioctl */ -#define IO_LEDACTIVE_SET 0x7 /* set active led - * 0=off, 1=green, 2=red, 3=yellow */ - -/* GPIO direction ioctl's */ -#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ -#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, - returns mask with current inputs (obsolete) */ -#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, - returns mask with current outputs (obsolete)*/ - -/* LED ioctl extended */ -#define IO_LED_SETBIT 0xB -#define IO_LED_CLRBIT 0xC - -/* SHUTDOWN ioctl */ -#define IO_SHUTDOWN 0xD -#define IO_GET_PWR_BT 0xE - -/* Bit toggling in driver settings */ -/* bit set in low byte0 is CLK mask (0x00FF), - bit set in byte1 is DATA mask (0xFF00) - msb, data_mask[7:0] , clk_mask[7:0] - */ -#define IO_CFG_WRITE_MODE 0xF -#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ - ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) - -/* The following 4 ioctl's take a pointer as argument and handles - * 32 bit ports (port G) properly. - * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT - */ -#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ -#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ -#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ - /* *arg updated with current input pins. */ -#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ - /* *arg updated with current output pins. */ - -/* The following ioctl's are applicable to the PWM channels only */ - -#define IO_PWM_SET_MODE 0x20 - -enum io_pwm_mode { - PWM_OFF = 0, /* disabled, deallocated */ - PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ - PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ - PWM_VARFREQ = 3, /* individually configurable high/low periods */ - PWM_SOFT = 4 /* software generated */ -}; - -struct io_pwm_set_mode { - enum io_pwm_mode mode; -}; - -/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns - * from 10ns (value = 0) to 81920ns (value = 8191) - * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to - * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty - * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) - */ -#define IO_PWM_SET_PERIOD 0x21 - -struct io_pwm_set_period { - unsigned int lo; /* 0..8191 */ - unsigned int hi; /* 0..8191 */ -}; - -/* Only for modes PWM_STANDARD and PWM_FAST. - * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from - * 0 (value = 0) to 255/256 (value = 255). - * For PWM_FAST, set duty cycle of PWM output signal from - * 0% (value = 0) to 100% (value = 255). Output signal in this mode - * is a 10ns pulse surrounded by a high or low level depending on duty - * cycle (except for 0% and 100% which result in a constant output). - * Resulting output frequency varies from 50 MHz at 50% duty cycle, - * down to 390 kHz at min/max duty cycle. - */ -#define IO_PWM_SET_DUTY 0x22 - -struct io_pwm_set_duty { - int duty; /* 0..255 */ -}; - -/* Returns information about the latest PWM pulse. - * lo: Length of the latest low period, in units of 10ns. - * hi: Length of the latest high period, in units of 10ns. - * cnt: Time since last detected edge, in units of 10ns. - * - * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC. - * - * NOTE: All PWM devices is connected to the same input source. - */ -#define IO_PWM_GET_PERIOD 0x23 - -struct io_pwm_get_period { - unsigned int lo; - unsigned int hi; - unsigned int cnt; -}; - -/* Sets the input source for the PWM input. For the src value see the - * register description for gio:rw_pwm_in_cfg. - * - * NOTE: All PWM devices is connected to the same input source. - */ -#define IO_PWM_SET_INPUT_SRC 0x24 -struct io_pwm_set_input_src { - unsigned int src; /* 0..7 */ -}; - -/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */ -#define IO_PPWM_SET_DUTY 0x25 - -struct io_ppwm_set_duty { - int duty; /* 0..255 */ -}; - -/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure - * PWM capable gpio pins: - */ -#define IO_PWMCLK_SETGET_CONFIG 0x26 -struct gpio_pwmclk_conf { - unsigned int gpiopin; /* The pin number based on the opened device */ - unsigned int baseclk; /* The base clock to use, or sw will select one close*/ - unsigned int low; /* The number of low periods of the baseclk */ - unsigned int high; /* The number of high periods of the baseclk */ -}; - -/* Examples: - * To get a symmetric 12 MHz clock without knowing anything about the hardware: - * baseclk = 12000000, low = 0, high = 0 - * To just get info of current setting: - * baseclk = 0, low = 0, high = 0, the values will be updated by driver. - */ - -#endif diff --git a/arch/cris/include/asm/fcntl.h b/arch/cris/include/asm/fcntl.h deleted file mode 100644 index 46ab12db573..00000000000 --- a/arch/cris/include/asm/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/ioctl.h b/arch/cris/include/asm/ioctl.h deleted file mode 100644 index b279fe06dfe..00000000000 --- a/arch/cris/include/asm/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/ioctls.h b/arch/cris/include/asm/ioctls.h deleted file mode 100644 index 488fbb3f5e8..00000000000 --- a/arch/cris/include/asm/ioctls.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __ARCH_CRIS_IOCTLS_H__ -#define __ARCH_CRIS_IOCTLS_H__ - -#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ -#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ -#define TIOCSERWRRS485 0x5462 /* write rs-485 */ -#define TIOCSRS485 0x5463 /* enable rs-485 */ - -#include - -#endif diff --git a/arch/cris/include/asm/ipcbuf.h b/arch/cris/include/asm/ipcbuf.h deleted file mode 100644 index 84c7e51cb6d..00000000000 --- a/arch/cris/include/asm/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/mman.h b/arch/cris/include/asm/mman.h deleted file mode 100644 index 8eebf89f5ab..00000000000 --- a/arch/cris/include/asm/mman.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/msgbuf.h b/arch/cris/include/asm/msgbuf.h deleted file mode 100644 index ada63df1d57..00000000000 --- a/arch/cris/include/asm/msgbuf.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef _CRIS_MSGBUF_H -#define _CRIS_MSGBUF_H - -/* verbatim copy of asm-i386 version */ - -/* - * The msqid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct msqid64_ds { - struct ipc64_perm msg_perm; - __kernel_time_t msg_stime; /* last msgsnd time */ - unsigned long __unused1; - __kernel_time_t msg_rtime; /* last msgrcv time */ - unsigned long __unused2; - __kernel_time_t msg_ctime; /* last change time */ - unsigned long __unused3; - unsigned long msg_cbytes; /* current number of bytes on queue */ - unsigned long msg_qnum; /* number of messages in queue */ - unsigned long msg_qbytes; /* max number of bytes on queue */ - __kernel_pid_t msg_lspid; /* pid of last msgsnd */ - __kernel_pid_t msg_lrpid; /* last receive pid */ - unsigned long __unused4; - unsigned long __unused5; -}; - -#endif /* _CRIS_MSGBUF_H */ diff --git a/arch/cris/include/asm/param.h b/arch/cris/include/asm/param.h deleted file mode 100644 index 484fcf8667c..00000000000 --- a/arch/cris/include/asm/param.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _ASMCRIS_PARAM_H -#define _ASMCRIS_PARAM_H - -/* Currently we assume that HZ=100 is good for CRIS. */ - -#define EXEC_PAGESIZE 8192 - -#include - -#endif /* _ASMCRIS_PARAM_H */ diff --git a/arch/cris/include/asm/poll.h b/arch/cris/include/asm/poll.h deleted file mode 100644 index c98509d3149..00000000000 --- a/arch/cris/include/asm/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/cris/include/asm/posix_types.h b/arch/cris/include/asm/posix_types.h deleted file mode 100644 index ce4e5179315..00000000000 --- a/arch/cris/include/asm/posix_types.h +++ /dev/null @@ -1,35 +0,0 @@ -/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ -/* I guess we should write these in assembler because they are used often. */ - -#ifndef __ARCH_CRIS_POSIX_TYPES_H -#define __ARCH_CRIS_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned short __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -#define __kernel_uid_t __kernel_uid_t - -typedef __SIZE_TYPE__ __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -#define __kernel_size_t __kernel_size_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include - -#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/arch/cris/include/asm/ptrace.h b/arch/cris/include/asm/ptrace.h index 6618893bfe8..2de84d7061c 100644 --- a/arch/cris/include/asm/ptrace.h +++ b/arch/cris/include/asm/ptrace.h @@ -1,9 +1,8 @@ #ifndef _CRIS_PTRACE_H #define _CRIS_PTRACE_H -#include +#include -#ifdef __KERNEL__ /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ #define PTRACE_GETREGS 12 @@ -11,6 +10,4 @@ #define profile_pc(regs) instruction_pointer(regs) -#endif /* __KERNEL__ */ - #endif /* _CRIS_PTRACE_H */ diff --git a/arch/cris/include/asm/resource.h b/arch/cris/include/asm/resource.h deleted file mode 100644 index b5d29448de4..00000000000 --- a/arch/cris/include/asm/resource.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_RESOURCE_H -#define _CRIS_RESOURCE_H - -#include - -#endif diff --git a/arch/cris/include/asm/rs485.h b/arch/cris/include/asm/rs485.h deleted file mode 100644 index ad40f9fbcb8..00000000000 --- a/arch/cris/include/asm/rs485.h +++ /dev/null @@ -1,18 +0,0 @@ -/* RS-485 structures */ - -/* Used with ioctl() TIOCSERSETRS485 for backward compatibility! - * XXX: Do not use it for new code! - */ -struct rs485_control { - unsigned short rts_on_send; - unsigned short rts_after_sent; - unsigned long delay_rts_before_send; - unsigned short enabled; -}; - -/* Used with ioctl() TIOCSERWRRS485 */ -struct rs485_write { - unsigned short outc_size; - unsigned char *outc; -}; - diff --git a/arch/cris/include/asm/sembuf.h b/arch/cris/include/asm/sembuf.h deleted file mode 100644 index 7fed9843796..00000000000 --- a/arch/cris/include/asm/sembuf.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _CRIS_SEMBUF_H -#define _CRIS_SEMBUF_H - -/* - * The semid64_ds structure for CRIS architecture. - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct semid64_ds { - struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ - __kernel_time_t sem_otime; /* last semop time */ - unsigned long __unused1; - __kernel_time_t sem_ctime; /* last change time */ - unsigned long __unused2; - unsigned long sem_nsems; /* no. of semaphores in array */ - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SEMBUF_H */ diff --git a/arch/cris/include/asm/setup.h b/arch/cris/include/asm/setup.h deleted file mode 100644 index b90728652d1..00000000000 --- a/arch/cris/include/asm/setup.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SETUP_H -#define _CRIS_SETUP_H - -#define COMMAND_LINE_SIZE 256 - -#endif diff --git a/arch/cris/include/asm/shmbuf.h b/arch/cris/include/asm/shmbuf.h deleted file mode 100644 index 3239e3f000e..00000000000 --- a/arch/cris/include/asm/shmbuf.h +++ /dev/null @@ -1,42 +0,0 @@ -#ifndef _CRIS_SHMBUF_H -#define _CRIS_SHMBUF_H - -/* - * The shmid64_ds structure for CRIS architecture (same as for i386) - * Note extra padding because this structure is passed back and forth - * between kernel and user space. - * - * Pad space is left for: - * - 64-bit time_t to solve y2038 problem - * - 2 miscellaneous 32-bit values - */ - -struct shmid64_ds { - struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ - __kernel_time_t shm_atime; /* last attach time */ - unsigned long __unused1; - __kernel_time_t shm_dtime; /* last detach time */ - unsigned long __unused2; - __kernel_time_t shm_ctime; /* last change time */ - unsigned long __unused3; - __kernel_pid_t shm_cpid; /* pid of creator */ - __kernel_pid_t shm_lpid; /* pid of last operator */ - unsigned long shm_nattch; /* no. of current attaches */ - unsigned long __unused4; - unsigned long __unused5; -}; - -struct shminfo64 { - unsigned long shmmax; - unsigned long shmmin; - unsigned long shmmni; - unsigned long shmseg; - unsigned long shmall; - unsigned long __unused1; - unsigned long __unused2; - unsigned long __unused3; - unsigned long __unused4; -}; - -#endif /* _CRIS_SHMBUF_H */ diff --git a/arch/cris/include/asm/sigcontext.h b/arch/cris/include/asm/sigcontext.h deleted file mode 100644 index a1d634e120d..00000000000 --- a/arch/cris/include/asm/sigcontext.h +++ /dev/null @@ -1,24 +0,0 @@ -/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef _ASM_CRIS_SIGCONTEXT_H -#define _ASM_CRIS_SIGCONTEXT_H - -#include - -/* This struct is saved by setup_frame in signal.c, to keep the current context while - a signal handler is executed. It's restored by sys_sigreturn. - - To keep things simple, we use pt_regs here even though normally you just specify - the list of regs to save. Then we can use copy_from_user on the entire regs instead - of a bunch of get_user's as well... - -*/ - -struct sigcontext { - struct pt_regs regs; /* needs to be first */ - unsigned long oldmask; - unsigned long usp; /* usp before stacking this gunk on it */ -}; - -#endif - diff --git a/arch/cris/include/asm/siginfo.h b/arch/cris/include/asm/siginfo.h deleted file mode 100644 index c1cd6d16928..00000000000 --- a/arch/cris/include/asm/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_SIGINFO_H -#define _CRIS_SIGINFO_H - -#include - -#endif diff --git a/arch/cris/include/asm/signal.h b/arch/cris/include/asm/signal.h index ea6af9aad76..b3c5ef05011 100644 --- a/arch/cris/include/asm/signal.h +++ b/arch/cris/include/asm/signal.h @@ -1,12 +1,8 @@ #ifndef _ASM_CRIS_SIGNAL_H #define _ASM_CRIS_SIGNAL_H -#include +#include -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ /* Most things should be clean enough to redefine this at will, if care is taken to make libc match. */ @@ -20,95 +16,6 @@ typedef struct { unsigned long sig[_NSIG_WORDS]; } sigset_t; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ - -#define SA_NOCLDSTOP 0x00000001u -#define SA_NOCLDWAIT 0x00000002u -#define SA_SIGINFO 0x00000004u -#define SA_ONSTACK 0x08000000u -#define SA_RESTART 0x10000000u -#define SA_NODEFER 0x40000000u -#define SA_RESETHAND 0x80000000u - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -#define SA_RESTORER 0x04000000 - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifdef __KERNEL__ struct old_sigaction { __sighandler_t sa_handler; old_sigset_t sa_mask; @@ -126,31 +33,6 @@ struct sigaction { struct k_sigaction { struct sigaction sa; }; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ #include /* here we could define asm-optimized sigaddset, sigdelset etc. operations. @@ -158,6 +40,4 @@ typedef struct sigaltstack { */ #define ptrace_signal_deliver(regs, cookie) do { } while (0) -#endif /* __KERNEL__ */ - #endif diff --git a/arch/cris/include/asm/socket.h b/arch/cris/include/asm/socket.h deleted file mode 100644 index ae52825021a..00000000000 --- a/arch/cris/include/asm/socket.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _ASM_SOCKET_H -#define _ASM_SOCKET_H - -/* almost the same as asm-i386/socket.h */ - -#include - -/* For setsockoptions(2) */ -#define SOL_SOCKET 1 - -#define SO_DEBUG 1 -#define SO_REUSEADDR 2 -#define SO_TYPE 3 -#define SO_ERROR 4 -#define SO_DONTROUTE 5 -#define SO_BROADCAST 6 -#define SO_SNDBUF 7 -#define SO_RCVBUF 8 -#define SO_SNDBUFFORCE 32 -#define SO_RCVBUFFORCE 33 -#define SO_KEEPALIVE 9 -#define SO_OOBINLINE 10 -#define SO_NO_CHECK 11 -#define SO_PRIORITY 12 -#define SO_LINGER 13 -#define SO_BSDCOMPAT 14 -/* To add :#define SO_REUSEPORT 15 */ -#define SO_PASSCRED 16 -#define SO_PEERCRED 17 -#define SO_RCVLOWAT 18 -#define SO_SNDLOWAT 19 -#define SO_RCVTIMEO 20 -#define SO_SNDTIMEO 21 - -/* Security levels - as per NRL IPv6 - don't actually do anything */ -#define SO_SECURITY_AUTHENTICATION 22 -#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 -#define SO_SECURITY_ENCRYPTION_NETWORK 24 - -#define SO_BINDTODEVICE 25 - -/* Socket filtering */ -#define SO_ATTACH_FILTER 26 -#define SO_DETACH_FILTER 27 - -#define SO_PEERNAME 28 -#define SO_TIMESTAMP 29 -#define SCM_TIMESTAMP SO_TIMESTAMP - -#define SO_ACCEPTCONN 30 - -#define SO_PEERSEC 31 -#define SO_PASSSEC 34 -#define SO_TIMESTAMPNS 35 -#define SCM_TIMESTAMPNS SO_TIMESTAMPNS - -#define SO_MARK 36 - -#define SO_TIMESTAMPING 37 -#define SCM_TIMESTAMPING SO_TIMESTAMPING - -#define SO_PROTOCOL 38 -#define SO_DOMAIN 39 - -#define SO_RXQ_OVFL 40 - -#define SO_WIFI_STATUS 41 -#define SCM_WIFI_STATUS SO_WIFI_STATUS -#define SO_PEEK_OFF 42 - -/* Instruct lower device to use last 4-bytes of skb data as FCS */ -#define SO_NOFCS 43 - -#endif /* _ASM_SOCKET_H */ - - diff --git a/arch/cris/include/asm/sockios.h b/arch/cris/include/asm/sockios.h deleted file mode 100644 index cfe7bfecf59..00000000000 --- a/arch/cris/include/asm/sockios.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef __ARCH_CRIS_SOCKIOS__ -#define __ARCH_CRIS_SOCKIOS__ - -/* Socket-level I/O control calls. */ -#define FIOSETOWN 0x8901 -#define SIOCSPGRP 0x8902 -#define FIOGETOWN 0x8903 -#define SIOCGPGRP 0x8904 -#define SIOCATMARK 0x8905 -#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ -#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ - -#endif diff --git a/arch/cris/include/asm/stat.h b/arch/cris/include/asm/stat.h deleted file mode 100644 index 9e558cc3c43..00000000000 --- a/arch/cris/include/asm/stat.h +++ /dev/null @@ -1,81 +0,0 @@ -#ifndef _CRIS_STAT_H -#define _CRIS_STAT_H - -/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in - the kernel if necessary. */ - -struct __old_kernel_stat { - unsigned short st_dev; - unsigned short st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned long st_size; - unsigned long st_atime; - unsigned long st_mtime; - unsigned long st_ctime; -}; - -#define STAT_HAVE_NSEC 1 - -struct stat { - unsigned long st_dev; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned long st_rdev; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long st_atime_nsec; - unsigned long st_mtime; - unsigned long st_mtime_nsec; - unsigned long st_ctime; - unsigned long st_ctime_nsec; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad0[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad3[4]; - - long long st_size; - unsigned long st_blksize; - - unsigned long st_blocks; /* Number 512-byte blocks allocated. */ - unsigned long __pad4; /* future possible st_blocks high bits */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ - - unsigned long long st_ino; -}; - -#endif diff --git a/arch/cris/include/asm/statfs.h b/arch/cris/include/asm/statfs.h deleted file mode 100644 index fdaf921844b..00000000000 --- a/arch/cris/include/asm/statfs.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _CRIS_STATFS_H -#define _CRIS_STATFS_H - -#include - -#endif diff --git a/arch/cris/include/asm/swab.h b/arch/cris/include/asm/swab.h index 80668e88419..991b6ace1ba 100644 --- a/arch/cris/include/asm/swab.h +++ b/arch/cris/include/asm/swab.h @@ -1,8 +1,7 @@ #ifndef _CRIS_SWAB_H #define _CRIS_SWAB_H -#ifdef __KERNEL__ #include -#endif /* __KERNEL__ */ +#include #endif /* _CRIS_SWAB_H */ diff --git a/arch/cris/include/asm/sync_serial.h b/arch/cris/include/asm/sync_serial.h deleted file mode 100644 index 7f827fea30e..00000000000 --- a/arch/cris/include/asm/sync_serial.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * ioctl defines for synchronous serial port driver - * - * Copyright (c) 2001-2003 Axis Communications AB - * - * Author: Mikael Starvik - * - */ - -#ifndef SYNC_SERIAL_H -#define SYNC_SERIAL_H - -#include - -#define SSP_SPEED _IOR('S', 0, unsigned int) -#define SSP_MODE _IOR('S', 1, unsigned int) -#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) -#define SSP_IPOLARITY _IOR('S', 3, unsigned int) -#define SSP_OPOLARITY _IOR('S', 4, unsigned int) -#define SSP_SPI _IOR('S', 5, unsigned int) -#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) -#define SSP_INPUT _IOR('S', 7, unsigned int) - -/* Values for SSP_SPEED */ -#define SSP150 0 -#define SSP300 1 -#define SSP600 2 -#define SSP1200 3 -#define SSP2400 4 -#define SSP4800 5 -#define SSP9600 6 -#define SSP19200 7 -#define SSP28800 8 -#define SSP57600 9 -#define SSP115200 10 -#define SSP230400 11 -#define SSP460800 12 -#define SSP921600 13 -#define SSP3125000 14 -#define CODEC 15 -#define CODEC_f32768 16 - -#define FREQ_4MHz 0 -#define FREQ_2MHz 1 -#define FREQ_1MHz 2 -#define FREQ_512kHz 3 -#define FREQ_256kHz 4 -#define FREQ_128kHz 5 -#define FREQ_64kHz 6 -#define FREQ_32kHz 7 -/* FREQ_* with values where bit (value & 0x10) is set are */ -/* used for CODEC_f32768 */ -#define FREQ_4096kHz 16 /* CODEC_f32768 */ - -/* Used by application to set CODEC divider, word rate and frame rate */ -#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \ - ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \ - (clk_per_sync << 16) | (sync_per_frame << 28)) - -/* Used by driver to extract speed */ -#define GET_SPEED(x) (x & 0xff) -#define GET_FREQ(x) ((x & 0xff00) >> 8) -#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) -#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) - -/* Values for SSP_MODE */ -#define MASTER_OUTPUT 0 -#define SLAVE_OUTPUT 1 -#define MASTER_INPUT 2 -#define SLAVE_INPUT 3 -#define MASTER_BIDIR 4 -#define SLAVE_BIDIR 5 - -/* Values for SSP_FRAME_SYNC */ -#define NORMAL_SYNC 1 -#define EARLY_SYNC 2 -#define SECOND_WORD_SYNC 0x40000 -#define LATE_SYNC 0x80000 - -#define BIT_SYNC 4 -#define WORD_SYNC 8 -#define EXTENDED_SYNC 0x10 - -#define SYNC_OFF 0x20 -#define SYNC_ON 0x40 -#define WORD_SIZE_8 0x80 -#define WORD_SIZE_12 0x100 -#define WORD_SIZE_16 0x200 -#define WORD_SIZE_24 0x400 -#define WORD_SIZE_32 0x800 -#define BIT_ORDER_LSB 0x1000 -#define BIT_ORDER_MSB 0x2000 -#define FLOW_CONTROL_ENABLE 0x4000 -#define FLOW_CONTROL_DISABLE 0x8000 -#define CLOCK_GATED 0x10000 -#define CLOCK_NOT_GATED 0x20000 - -/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ -#define CLOCK_NORMAL 1 -#define CLOCK_INVERT 2 -#define CLOCK_INEGEDGE CLOCK_NORMAL -#define CLOCK_IPOSEDGE CLOCK_INVERT -#define FRAME_NORMAL 4 -#define FRAME_INVERT 8 -#define STATUS_NORMAL 0x10 -#define STATUS_INVERT 0x20 - -/* Values for SSP_SPI */ -#define SPI_MASTER 0 -#define SPI_SLAVE 1 - -/* Values for SSP_INBUFCHUNK */ -/* plain integer with the size of DMA chunks */ - -/* To ensure that the timestamps are aligned with the data being read - * the read length MUST be a multiple of the length of the DMA buffers. - * - * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below. - */ -#define SSP_INPUT_CHUNK_SIZE 256 - -/* Request struct to pass through the ioctl interface to read - * data with timestamps. - */ -struct ssp_request { - char __user *buf; /* Where to put the data. */ - size_t len; /* Size of buf. MUST be a multiple of */ - /* SSP_INPUT_CHUNK_SIZE! */ - struct timespec ts; /* The time the data was sampled. */ -}; - -#endif diff --git a/arch/cris/include/asm/termbits.h b/arch/cris/include/asm/termbits.h deleted file mode 100644 index 1c43bc874cc..00000000000 --- a/arch/cris/include/asm/termbits.h +++ /dev/null @@ -1,235 +0,0 @@ -/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ - -#ifndef __ARCH_ETRAX100_TERMBITS_H__ -#define __ARCH_ETRAX100_TERMBITS_H__ - -#include - -typedef unsigned char cc_t; -typedef unsigned int speed_t; -typedef unsigned int tcflag_t; - -#define NCCS 19 -struct termios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ -}; - -struct termios2 { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -struct ktermios { - tcflag_t c_iflag; /* input mode flags */ - tcflag_t c_oflag; /* output mode flags */ - tcflag_t c_cflag; /* control mode flags */ - tcflag_t c_lflag; /* local mode flags */ - cc_t c_line; /* line discipline */ - cc_t c_cc[NCCS]; /* control characters */ - speed_t c_ispeed; /* input speed */ - speed_t c_ospeed; /* output speed */ -}; - -/* c_cc characters */ -#define VINTR 0 -#define VQUIT 1 -#define VERASE 2 -#define VKILL 3 -#define VEOF 4 -#define VTIME 5 -#define VMIN 6 -#define VSWTC 7 -#define VSTART 8 -#define VSTOP 9 -#define VSUSP 10 -#define VEOL 11 -#define VREPRINT 12 -#define VDISCARD 13 -#define VWERASE 14 -#define VLNEXT 15 -#define VEOL2 16 - -/* c_iflag bits */ -#define IGNBRK 0000001 -#define BRKINT 0000002 -#define IGNPAR 0000004 -#define PARMRK 0000010 -#define INPCK 0000020 -#define ISTRIP 0000040 -#define INLCR 0000100 -#define IGNCR 0000200 -#define ICRNL 0000400 -#define IUCLC 0001000 -#define IXON 0002000 -#define IXANY 0004000 -#define IXOFF 0010000 -#define IMAXBEL 0020000 -#define IUTF8 0040000 - -/* c_oflag bits */ -#define OPOST 0000001 -#define OLCUC 0000002 -#define ONLCR 0000004 -#define OCRNL 0000010 -#define ONOCR 0000020 -#define ONLRET 0000040 -#define OFILL 0000100 -#define OFDEL 0000200 -#define NLDLY 0000400 -#define NL0 0000000 -#define NL1 0000400 -#define CRDLY 0003000 -#define CR0 0000000 -#define CR1 0001000 -#define CR2 0002000 -#define CR3 0003000 -#define TABDLY 0014000 -#define TAB0 0000000 -#define TAB1 0004000 -#define TAB2 0010000 -#define TAB3 0014000 -#define XTABS 0014000 -#define BSDLY 0020000 -#define BS0 0000000 -#define BS1 0020000 -#define VTDLY 0040000 -#define VT0 0000000 -#define VT1 0040000 -#define FFDLY 0100000 -#define FF0 0000000 -#define FF1 0100000 - -/* c_cflag bit meaning */ -/* - * 3 2 1 - * 10 987 654 321 098 765 432 109 876 543 210 - * | | ||| CBAUD - * obaud - * - * ||CSIZE - * - * |CSTOP - * |CREAD - * |CPARENB - * - * |CPARODD - * |HUPCL - * |CLOCAL - * |CBAUDEX - * 10 987 654 321 098 765 432 109 876 543 210 - * | || || CIBAUD, IBSHIFT=16 - * ibaud - * |CMSPAR - * | CRTSCTS - * x x xxx xxx x x xx Free bits - */ - -#define CBAUD 0010017 -#define B0 0000000 /* hang up */ -#define B50 0000001 -#define B75 0000002 -#define B110 0000003 -#define B134 0000004 -#define B150 0000005 -#define B200 0000006 -#define B300 0000007 -#define B600 0000010 -#define B1200 0000011 -#define B1800 0000012 -#define B2400 0000013 -#define B4800 0000014 -#define B9600 0000015 -#define B19200 0000016 -#define B38400 0000017 -#define EXTA B19200 -#define EXTB B38400 -#define CSIZE 0000060 -#define CS5 0000000 -#define CS6 0000020 -#define CS7 0000040 -#define CS8 0000060 -#define CSTOPB 0000100 -#define CREAD 0000200 -#define PARENB 0000400 -#define PARODD 0001000 -#define HUPCL 0002000 -#define CLOCAL 0004000 -#define CBAUDEX 0010000 -#define BOTHER 0010000 -#define B57600 0010001 -#define B115200 0010002 -#define B230400 0010003 -#define B460800 0010004 - -/* Unsupported rates, but needed to avoid compile error. */ -#define B500000 0010005 -#define B576000 0010006 -#define B1000000 0010010 -#define B1152000 0010011 -#define B1500000 0010012 -#define B2000000 0010013 -#define B2500000 0010014 -#define B3000000 0010015 -#define B3500000 0010016 -#define B4000000 0010017 - -/* etrax supports these additional three baud rates */ -#define B921600 0010005 -#define B1843200 0010006 -#define B6250000 0010007 -/* ETRAX FS supports this as well */ -#define B12500000 0010010 -#define CIBAUD 002003600000 /* input baud rate (used in v32) */ -/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX - * shifted left IBSHIFT bits. - */ -#define IBSHIFT 16 -#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ -#define CRTSCTS 020000000000 /* flow control */ - -/* c_lflag bits */ -#define ISIG 0000001 -#define ICANON 0000002 -#define XCASE 0000004 -#define ECHO 0000010 -#define ECHOE 0000020 -#define ECHOK 0000040 -#define ECHONL 0000100 -#define NOFLSH 0000200 -#define TOSTOP 0000400 -#define ECHOCTL 0001000 -#define ECHOPRT 0002000 -#define ECHOKE 0004000 -#define FLUSHO 0010000 -#define PENDIN 0040000 -#define IEXTEN 0100000 -#define EXTPROC 0200000 - -/* tcflow() and TCXONC use these */ -#define TCOOFF 0 -#define TCOON 1 -#define TCIOFF 2 -#define TCION 3 - -/* tcflush() and TCFLSH use these */ -#define TCIFLUSH 0 -#define TCOFLUSH 1 -#define TCIOFLUSH 2 - -/* tcsetattr uses these */ -#define TCSANOW 0 -#define TCSADRAIN 1 -#define TCSAFLUSH 2 - -#endif diff --git a/arch/cris/include/asm/termios.h b/arch/cris/include/asm/termios.h index 1265109f4ce..1991cd9e408 100644 --- a/arch/cris/include/asm/termios.h +++ b/arch/cris/include/asm/termios.h @@ -1,47 +1,8 @@ #ifndef _CRIS_TERMIOS_H #define _CRIS_TERMIOS_H -#include -#include -#include -#include +#include -struct winsize { - unsigned short ws_row; - unsigned short ws_col; - unsigned short ws_xpixel; - unsigned short ws_ypixel; -}; - -#define NCC 8 -struct termio { - unsigned short c_iflag; /* input mode flags */ - unsigned short c_oflag; /* output mode flags */ - unsigned short c_cflag; /* control mode flags */ - unsigned short c_lflag; /* local mode flags */ - unsigned char c_line; /* line discipline */ - unsigned char c_cc[NCC]; /* control characters */ -}; - -/* modem lines */ -#define TIOCM_LE 0x001 -#define TIOCM_DTR 0x002 -#define TIOCM_RTS 0x004 -#define TIOCM_ST 0x008 -#define TIOCM_SR 0x010 -#define TIOCM_CTS 0x020 -#define TIOCM_CAR 0x040 -#define TIOCM_RNG 0x080 -#define TIOCM_DSR 0x100 -#define TIOCM_CD TIOCM_CAR -#define TIOCM_RI TIOCM_RNG -#define TIOCM_OUT1 0x2000 -#define TIOCM_OUT2 0x4000 -#define TIOCM_LOOP 0x8000 - -/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ - -#ifdef __KERNEL__ /* intr=^C quit=^\ erase=del kill=^U eof=^D vtime=\0 vmin=\1 sxtc=\0 @@ -87,6 +48,4 @@ struct termio { #define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) #define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) -#endif /* __KERNEL__ */ - #endif /* _CRIS_TERMIOS_H */ diff --git a/arch/cris/include/asm/types.h b/arch/cris/include/asm/types.h index adaf82780bb..a3cac7757c7 100644 --- a/arch/cris/include/asm/types.h +++ b/arch/cris/include/asm/types.h @@ -1,15 +1,12 @@ #ifndef _ETRAX_TYPES_H #define _ETRAX_TYPES_H -#include +#include /* * These aren't exported outside the kernel to avoid name space clashes */ -#ifdef __KERNEL__ #define BITS_PER_LONG 32 -#endif /* __KERNEL__ */ - #endif diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h index 51873a446f8..4fb59e10702 100644 --- a/arch/cris/include/asm/unistd.h +++ b/arch/cris/include/asm/unistd.h @@ -1,347 +1,8 @@ #ifndef _ASM_CRIS_UNISTD_H_ #define _ASM_CRIS_UNISTD_H_ -/* - * This file contains the system call numbers, and stub macros for libc. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_lchown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl 110 -#define __NR_vhangup 111 -#define __NR_idle 112 -#define __NR_vm86 113 -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_modify_ldt 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_chown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_lchown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_chown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_mincore 218 -#define __NR_madvise 219 -#define __NR_getdents64 220 -#define __NR_fcntl64 221 -/* 223 is unused */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 -#define __NR_set_thread_area 243 -#define __NR_get_thread_area 244 -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 -#define __NR_fadvise64 250 -/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_epoll_create 254 -#define __NR_epoll_ctl 255 -#define __NR_epoll_wait 256 -#define __NR_remap_file_pages 257 -#define __NR_set_tid_address 258 -#define __NR_timer_create 259 -#define __NR_timer_settime (__NR_timer_create+1) -#define __NR_timer_gettime (__NR_timer_create+2) -#define __NR_timer_getoverrun (__NR_timer_create+3) -#define __NR_timer_delete (__NR_timer_create+4) -#define __NR_clock_settime (__NR_timer_create+5) -#define __NR_clock_gettime (__NR_timer_create+6) -#define __NR_clock_getres (__NR_timer_create+7) -#define __NR_clock_nanosleep (__NR_timer_create+8) -#define __NR_statfs64 268 -#define __NR_fstatfs64 269 -#define __NR_tgkill 270 -#define __NR_utimes 271 -#define __NR_fadvise64_64 272 -#define __NR_vserver 273 -#define __NR_mbind 274 -#define __NR_get_mempolicy 275 -#define __NR_set_mempolicy 276 -#define __NR_mq_open 277 -#define __NR_mq_unlink (__NR_mq_open+1) -#define __NR_mq_timedsend (__NR_mq_open+2) -#define __NR_mq_timedreceive (__NR_mq_open+3) -#define __NR_mq_notify (__NR_mq_open+4) -#define __NR_mq_getsetattr (__NR_mq_open+5) -#define __NR_kexec_load 283 -#define __NR_waitid 284 -/* #define __NR_sys_setaltroot 285 */ -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 -#define __NR_migrate_pages 294 -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 -#define __NR_set_robust_list 311 -#define __NR_get_robust_list 312 -#define __NR_splice 313 -#define __NR_sync_file_range 314 -#define __NR_tee 315 -#define __NR_vmsplice 316 -#define __NR_move_pages 317 -#define __NR_getcpu 318 -#define __NR_epoll_pwait 319 -#define __NR_utimensat 320 -#define __NR_signalfd 321 -#define __NR_timerfd_create 322 -#define __NR_eventfd 323 -#define __NR_fallocate 324 -#define __NR_timerfd_settime 325 -#define __NR_timerfd_gettime 326 -#define __NR_signalfd4 327 -#define __NR_eventfd2 328 -#define __NR_epoll_create1 329 -#define __NR_dup3 330 -#define __NR_pipe2 331 -#define __NR_inotify_init1 332 -#define __NR_preadv 333 -#define __NR_pwritev 334 -#define __NR_setns 335 +#include -#ifdef __KERNEL__ #define NR_syscalls 336 @@ -380,5 +41,4 @@ */ #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") -#endif /* __KERNEL__ */ #endif /* _ASM_CRIS_UNISTD_H_ */ diff --git a/arch/cris/include/uapi/asm/Kbuild b/arch/cris/include/uapi/asm/Kbuild index f50236ae9ca..7d47b366ad8 100644 --- a/arch/cris/include/uapi/asm/Kbuild +++ b/arch/cris/include/uapi/asm/Kbuild @@ -3,3 +3,37 @@ include include/uapi/asm-generic/Kbuild.asm header-y += arch-v10/ header-y += arch-v32/ +header-y += auxvec.h +header-y += bitsperlong.h +header-y += byteorder.h +header-y += errno.h +header-y += ethernet.h +header-y += etraxgpio.h +header-y += fcntl.h +header-y += ioctl.h +header-y += ioctls.h +header-y += ipcbuf.h +header-y += mman.h +header-y += msgbuf.h +header-y += param.h +header-y += poll.h +header-y += posix_types.h +header-y += ptrace.h +header-y += resource.h +header-y += rs485.h +header-y += sembuf.h +header-y += setup.h +header-y += shmbuf.h +header-y += sigcontext.h +header-y += siginfo.h +header-y += signal.h +header-y += socket.h +header-y += sockios.h +header-y += stat.h +header-y += statfs.h +header-y += swab.h +header-y += sync_serial.h +header-y += termbits.h +header-y += termios.h +header-y += types.h +header-y += unistd.h diff --git a/arch/cris/include/uapi/asm/auxvec.h b/arch/cris/include/uapi/asm/auxvec.h new file mode 100644 index 00000000000..cb30b01bf19 --- /dev/null +++ b/arch/cris/include/uapi/asm/auxvec.h @@ -0,0 +1,4 @@ +#ifndef __ASMCRIS_AUXVEC_H +#define __ASMCRIS_AUXVEC_H + +#endif diff --git a/arch/cris/include/uapi/asm/bitsperlong.h b/arch/cris/include/uapi/asm/bitsperlong.h new file mode 100644 index 00000000000..6dc0bb0c13b --- /dev/null +++ b/arch/cris/include/uapi/asm/bitsperlong.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/byteorder.h b/arch/cris/include/uapi/asm/byteorder.h new file mode 100644 index 00000000000..bcd189798e2 --- /dev/null +++ b/arch/cris/include/uapi/asm/byteorder.h @@ -0,0 +1,8 @@ +#ifndef _CRIS_BYTEORDER_H +#define _CRIS_BYTEORDER_H + +#include + +#endif + + diff --git a/arch/cris/include/uapi/asm/errno.h b/arch/cris/include/uapi/asm/errno.h new file mode 100644 index 00000000000..2bf5eb5fa77 --- /dev/null +++ b/arch/cris/include/uapi/asm/errno.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_ERRNO_H +#define _CRIS_ERRNO_H + +#include + +#endif diff --git a/arch/cris/include/uapi/asm/ethernet.h b/arch/cris/include/uapi/asm/ethernet.h new file mode 100644 index 00000000000..4d58652c3a4 --- /dev/null +++ b/arch/cris/include/uapi/asm/ethernet.h @@ -0,0 +1,21 @@ +/* + * ioctl defines for ethernet driver + * + * Copyright (c) 2001 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef _CRIS_ETHERNET_H +#define _CRIS_ETHERNET_H +#define SET_ETH_SPEED_AUTO SIOCDEVPRIVATE /* Auto neg speed */ +#define SET_ETH_SPEED_10 SIOCDEVPRIVATE+1 /* 10 Mbps */ +#define SET_ETH_SPEED_100 SIOCDEVPRIVATE+2 /* 100 Mbps. */ +#define SET_ETH_DUPLEX_AUTO SIOCDEVPRIVATE+3 /* Auto neg duplex */ +#define SET_ETH_DUPLEX_HALF SIOCDEVPRIVATE+4 /* Full duplex */ +#define SET_ETH_DUPLEX_FULL SIOCDEVPRIVATE+5 /* Half duplex */ +#define SET_ETH_ENABLE_LEDS SIOCDEVPRIVATE+6 /* Enable net LEDs */ +#define SET_ETH_DISABLE_LEDS SIOCDEVPRIVATE+7 /* Disable net LEDs */ +#define SET_ETH_AUTONEG SIOCDEVPRIVATE+8 +#endif /* _CRIS_ETHERNET_H */ diff --git a/arch/cris/include/uapi/asm/etraxgpio.h b/arch/cris/include/uapi/asm/etraxgpio.h new file mode 100644 index 00000000000..461c089db76 --- /dev/null +++ b/arch/cris/include/uapi/asm/etraxgpio.h @@ -0,0 +1,239 @@ +/* + * The following devices are accessible using this driver using + * GPIO_MAJOR (120) and a couple of minor numbers. + * + * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/gpiog minor 3 + * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG + * g1-g7 and g25-g31 is both input and outputs but on different pins + * Also note that some bits change pins depending on what interfaces + * are enabled. + * + * For ETRAX FS (CONFIG_ETRAXFS): + * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction + * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction + * /dev/leds minor 2, Access to leds depending on kernelconfig + * + * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3): + * /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction + * /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction + * /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction + * /dev/gpiod minor 4, 32 bit GPIO, input only + * /dev/leds minor 2, Access to leds depending on kernelconfig + * /dev/pwm0 minor 16, PWM channel 0 on PA30 + * /dev/pwm1 minor 17, PWM channel 1 on PA31 + * /dev/pwm2 minor 18, PWM channel 2 on PB26 + * /dev/ppwm minor 19, PPWM channel + * + */ +#ifndef _ASM_ETRAXGPIO_H +#define _ASM_ETRAXGPIO_H + +#define GPIO_MINOR_FIRST 0 + +#define ETRAXGPIO_IOCTYPE 43 + +/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */ +#ifdef CONFIG_ETRAX_ARCH_V10 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_G 3 +#define GPIO_MINOR_LAST 3 +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST +#endif + +#ifdef CONFIG_ETRAXFS +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#define GPIO_MINOR_E 5 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 5 +#endif +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST +#endif + +#ifdef CONFIG_CRIS_MACH_ARTPEC3 +#define GPIO_MINOR_A 0 +#define GPIO_MINOR_B 1 +#define GPIO_MINOR_LEDS 2 +#define GPIO_MINOR_C 3 +#define GPIO_MINOR_D 4 +#ifdef CONFIG_ETRAX_VIRTUAL_GPIO +#define GPIO_MINOR_V 6 +#define GPIO_MINOR_LAST 6 +#else +#define GPIO_MINOR_LAST 4 +#endif +#define GPIO_MINOR_FIRST_PWM 16 +#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0) +#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1) +#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2) +#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3) +#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM +#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM +#endif + + + +/* supported ioctl _IOC_NR's */ + +#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */ +#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */ +#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */ + +/* the alarm is waited for by select() */ + +#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */ +#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */ +#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */ + +/* LED ioctl */ +#define IO_LEDACTIVE_SET 0x7 /* set active led + * 0=off, 1=green, 2=red, 3=yellow */ + +/* GPIO direction ioctl's */ +#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */ +#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input, + returns mask with current inputs (obsolete) */ +#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output, + returns mask with current outputs (obsolete)*/ + +/* LED ioctl extended */ +#define IO_LED_SETBIT 0xB +#define IO_LED_CLRBIT 0xC + +/* SHUTDOWN ioctl */ +#define IO_SHUTDOWN 0xD +#define IO_GET_PWR_BT 0xE + +/* Bit toggling in driver settings */ +/* bit set in low byte0 is CLK mask (0x00FF), + bit set in byte1 is DATA mask (0xFF00) + msb, data_mask[7:0] , clk_mask[7:0] + */ +#define IO_CFG_WRITE_MODE 0xF +#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \ + ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) ) + +/* The following 4 ioctl's take a pointer as argument and handles + * 32 bit ports (port G) properly. + * These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT + */ +#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */ +#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */ +#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */ + /* *arg updated with current input pins. */ +#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */ + /* *arg updated with current output pins. */ + +/* The following ioctl's are applicable to the PWM channels only */ + +#define IO_PWM_SET_MODE 0x20 + +enum io_pwm_mode { + PWM_OFF = 0, /* disabled, deallocated */ + PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */ + PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */ + PWM_VARFREQ = 3, /* individually configurable high/low periods */ + PWM_SOFT = 4 /* software generated */ +}; + +struct io_pwm_set_mode { + enum io_pwm_mode mode; +}; + +/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns + * from 10ns (value = 0) to 81920ns (value = 8191) + * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to + * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty + * cycle (81920 + 10ns or 10ns + 81920ns, respectively).) + */ +#define IO_PWM_SET_PERIOD 0x21 + +struct io_pwm_set_period { + unsigned int lo; /* 0..8191 */ + unsigned int hi; /* 0..8191 */ +}; + +/* Only for modes PWM_STANDARD and PWM_FAST. + * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from + * 0 (value = 0) to 255/256 (value = 255). + * For PWM_FAST, set duty cycle of PWM output signal from + * 0% (value = 0) to 100% (value = 255). Output signal in this mode + * is a 10ns pulse surrounded by a high or low level depending on duty + * cycle (except for 0% and 100% which result in a constant output). + * Resulting output frequency varies from 50 MHz at 50% duty cycle, + * down to 390 kHz at min/max duty cycle. + */ +#define IO_PWM_SET_DUTY 0x22 + +struct io_pwm_set_duty { + int duty; /* 0..255 */ +}; + +/* Returns information about the latest PWM pulse. + * lo: Length of the latest low period, in units of 10ns. + * hi: Length of the latest high period, in units of 10ns. + * cnt: Time since last detected edge, in units of 10ns. + * + * The input source to PWM is decied by IO_PWM_SET_INPUT_SRC. + * + * NOTE: All PWM devices is connected to the same input source. + */ +#define IO_PWM_GET_PERIOD 0x23 + +struct io_pwm_get_period { + unsigned int lo; + unsigned int hi; + unsigned int cnt; +}; + +/* Sets the input source for the PWM input. For the src value see the + * register description for gio:rw_pwm_in_cfg. + * + * NOTE: All PWM devices is connected to the same input source. + */ +#define IO_PWM_SET_INPUT_SRC 0x24 +struct io_pwm_set_input_src { + unsigned int src; /* 0..7 */ +}; + +/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */ +#define IO_PPWM_SET_DUTY 0x25 + +struct io_ppwm_set_duty { + int duty; /* 0..255 */ +}; + +/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure + * PWM capable gpio pins: + */ +#define IO_PWMCLK_SETGET_CONFIG 0x26 +struct gpio_pwmclk_conf { + unsigned int gpiopin; /* The pin number based on the opened device */ + unsigned int baseclk; /* The base clock to use, or sw will select one close*/ + unsigned int low; /* The number of low periods of the baseclk */ + unsigned int high; /* The number of high periods of the baseclk */ +}; + +/* Examples: + * To get a symmetric 12 MHz clock without knowing anything about the hardware: + * baseclk = 12000000, low = 0, high = 0 + * To just get info of current setting: + * baseclk = 0, low = 0, high = 0, the values will be updated by driver. + */ + +#endif diff --git a/arch/cris/include/uapi/asm/fcntl.h b/arch/cris/include/uapi/asm/fcntl.h new file mode 100644 index 00000000000..46ab12db573 --- /dev/null +++ b/arch/cris/include/uapi/asm/fcntl.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/ioctl.h b/arch/cris/include/uapi/asm/ioctl.h new file mode 100644 index 00000000000..b279fe06dfe --- /dev/null +++ b/arch/cris/include/uapi/asm/ioctl.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/ioctls.h b/arch/cris/include/uapi/asm/ioctls.h new file mode 100644 index 00000000000..488fbb3f5e8 --- /dev/null +++ b/arch/cris/include/uapi/asm/ioctls.h @@ -0,0 +1,11 @@ +#ifndef __ARCH_CRIS_IOCTLS_H__ +#define __ARCH_CRIS_IOCTLS_H__ + +#define TIOCSERGSTRUCT 0x5458 /* For debugging only */ +#define TIOCSERSETRS485 0x5461 /* enable rs-485 (deprecated) */ +#define TIOCSERWRRS485 0x5462 /* write rs-485 */ +#define TIOCSRS485 0x5463 /* enable rs-485 */ + +#include + +#endif diff --git a/arch/cris/include/uapi/asm/ipcbuf.h b/arch/cris/include/uapi/asm/ipcbuf.h new file mode 100644 index 00000000000..84c7e51cb6d --- /dev/null +++ b/arch/cris/include/uapi/asm/ipcbuf.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/mman.h b/arch/cris/include/uapi/asm/mman.h new file mode 100644 index 00000000000..8eebf89f5ab --- /dev/null +++ b/arch/cris/include/uapi/asm/mman.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/msgbuf.h b/arch/cris/include/uapi/asm/msgbuf.h new file mode 100644 index 00000000000..ada63df1d57 --- /dev/null +++ b/arch/cris/include/uapi/asm/msgbuf.h @@ -0,0 +1,33 @@ +#ifndef _CRIS_MSGBUF_H +#define _CRIS_MSGBUF_H + +/* verbatim copy of asm-i386 version */ + +/* + * The msqid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct msqid64_ds { + struct ipc64_perm msg_perm; + __kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* _CRIS_MSGBUF_H */ diff --git a/arch/cris/include/uapi/asm/param.h b/arch/cris/include/uapi/asm/param.h new file mode 100644 index 00000000000..484fcf8667c --- /dev/null +++ b/arch/cris/include/uapi/asm/param.h @@ -0,0 +1,10 @@ +#ifndef _ASMCRIS_PARAM_H +#define _ASMCRIS_PARAM_H + +/* Currently we assume that HZ=100 is good for CRIS. */ + +#define EXEC_PAGESIZE 8192 + +#include + +#endif /* _ASMCRIS_PARAM_H */ diff --git a/arch/cris/include/uapi/asm/poll.h b/arch/cris/include/uapi/asm/poll.h new file mode 100644 index 00000000000..c98509d3149 --- /dev/null +++ b/arch/cris/include/uapi/asm/poll.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/posix_types.h b/arch/cris/include/uapi/asm/posix_types.h new file mode 100644 index 00000000000..ce4e5179315 --- /dev/null +++ b/arch/cris/include/uapi/asm/posix_types.h @@ -0,0 +1,35 @@ +/* $Id: posix_types.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +/* We cheat a bit and use our C-coded bitops functions from asm/bitops.h */ +/* I guess we should write these in assembler because they are used often. */ + +#ifndef __ARCH_CRIS_POSIX_TYPES_H +#define __ARCH_CRIS_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_mode_t; +#define __kernel_mode_t __kernel_mode_t + +typedef unsigned short __kernel_ipc_pid_t; +#define __kernel_ipc_pid_t __kernel_ipc_pid_t + +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +#define __kernel_uid_t __kernel_uid_t + +typedef __SIZE_TYPE__ __kernel_size_t; +typedef long __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#define __kernel_size_t __kernel_size_t + +typedef unsigned short __kernel_old_dev_t; +#define __kernel_old_dev_t __kernel_old_dev_t + +#include + +#endif /* __ARCH_CRIS_POSIX_TYPES_H */ diff --git a/arch/cris/include/uapi/asm/ptrace.h b/arch/cris/include/uapi/asm/ptrace.h new file mode 100644 index 00000000000..c689c9bbbe5 --- /dev/null +++ b/arch/cris/include/uapi/asm/ptrace.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/resource.h b/arch/cris/include/uapi/asm/resource.h new file mode 100644 index 00000000000..b5d29448de4 --- /dev/null +++ b/arch/cris/include/uapi/asm/resource.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_RESOURCE_H +#define _CRIS_RESOURCE_H + +#include + +#endif diff --git a/arch/cris/include/uapi/asm/rs485.h b/arch/cris/include/uapi/asm/rs485.h new file mode 100644 index 00000000000..ad40f9fbcb8 --- /dev/null +++ b/arch/cris/include/uapi/asm/rs485.h @@ -0,0 +1,18 @@ +/* RS-485 structures */ + +/* Used with ioctl() TIOCSERSETRS485 for backward compatibility! + * XXX: Do not use it for new code! + */ +struct rs485_control { + unsigned short rts_on_send; + unsigned short rts_after_sent; + unsigned long delay_rts_before_send; + unsigned short enabled; +}; + +/* Used with ioctl() TIOCSERWRRS485 */ +struct rs485_write { + unsigned short outc_size; + unsigned char *outc; +}; + diff --git a/arch/cris/include/uapi/asm/sembuf.h b/arch/cris/include/uapi/asm/sembuf.h new file mode 100644 index 00000000000..7fed9843796 --- /dev/null +++ b/arch/cris/include/uapi/asm/sembuf.h @@ -0,0 +1,25 @@ +#ifndef _CRIS_SEMBUF_H +#define _CRIS_SEMBUF_H + +/* + * The semid64_ds structure for CRIS architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct semid64_ds { + struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SEMBUF_H */ diff --git a/arch/cris/include/uapi/asm/setup.h b/arch/cris/include/uapi/asm/setup.h new file mode 100644 index 00000000000..b90728652d1 --- /dev/null +++ b/arch/cris/include/uapi/asm/setup.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SETUP_H +#define _CRIS_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +#endif diff --git a/arch/cris/include/uapi/asm/shmbuf.h b/arch/cris/include/uapi/asm/shmbuf.h new file mode 100644 index 00000000000..3239e3f000e --- /dev/null +++ b/arch/cris/include/uapi/asm/shmbuf.h @@ -0,0 +1,42 @@ +#ifndef _CRIS_SHMBUF_H +#define _CRIS_SHMBUF_H + +/* + * The shmid64_ds structure for CRIS architecture (same as for i386) + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct shmid64_ds { + struct ipc64_perm shm_perm; /* operation perms */ + size_t shm_segsz; /* size of segment (bytes) */ + __kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __kernel_pid_t shm_cpid; /* pid of creator */ + __kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* _CRIS_SHMBUF_H */ diff --git a/arch/cris/include/uapi/asm/sigcontext.h b/arch/cris/include/uapi/asm/sigcontext.h new file mode 100644 index 00000000000..a1d634e120d --- /dev/null +++ b/arch/cris/include/uapi/asm/sigcontext.h @@ -0,0 +1,24 @@ +/* $Id: sigcontext.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef _ASM_CRIS_SIGCONTEXT_H +#define _ASM_CRIS_SIGCONTEXT_H + +#include + +/* This struct is saved by setup_frame in signal.c, to keep the current context while + a signal handler is executed. It's restored by sys_sigreturn. + + To keep things simple, we use pt_regs here even though normally you just specify + the list of regs to save. Then we can use copy_from_user on the entire regs instead + of a bunch of get_user's as well... + +*/ + +struct sigcontext { + struct pt_regs regs; /* needs to be first */ + unsigned long oldmask; + unsigned long usp; /* usp before stacking this gunk on it */ +}; + +#endif + diff --git a/arch/cris/include/uapi/asm/siginfo.h b/arch/cris/include/uapi/asm/siginfo.h new file mode 100644 index 00000000000..c1cd6d16928 --- /dev/null +++ b/arch/cris/include/uapi/asm/siginfo.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_SIGINFO_H +#define _CRIS_SIGINFO_H + +#include + +#endif diff --git a/arch/cris/include/uapi/asm/signal.h b/arch/cris/include/uapi/asm/signal.h new file mode 100644 index 00000000000..21624948a96 --- /dev/null +++ b/arch/cris/include/uapi/asm/signal.h @@ -0,0 +1,122 @@ +#ifndef _UAPI_ASM_CRIS_SIGNAL_H +#define _UAPI_ASM_CRIS_SIGNAL_H + +#include + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ + +#define SA_NOCLDSTOP 0x00000001u +#define SA_NOCLDWAIT 0x00000002u +#define SA_SIGINFO 0x00000004u +#define SA_ONSTACK 0x08000000u +#define SA_RESTART 0x10000000u +#define SA_NODEFER 0x40000000u +#define SA_RESETHAND 0x80000000u + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +#define SA_RESTORER 0x04000000 + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include + +#ifndef __KERNEL__ +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + + +#endif /* _UAPI_ASM_CRIS_SIGNAL_H */ diff --git a/arch/cris/include/uapi/asm/socket.h b/arch/cris/include/uapi/asm/socket.h new file mode 100644 index 00000000000..ae52825021a --- /dev/null +++ b/arch/cris/include/uapi/asm/socket.h @@ -0,0 +1,76 @@ +#ifndef _ASM_SOCKET_H +#define _ASM_SOCKET_H + +/* almost the same as asm-i386/socket.h */ + +#include + +/* For setsockoptions(2) */ +#define SOL_SOCKET 1 + +#define SO_DEBUG 1 +#define SO_REUSEADDR 2 +#define SO_TYPE 3 +#define SO_ERROR 4 +#define SO_DONTROUTE 5 +#define SO_BROADCAST 6 +#define SO_SNDBUF 7 +#define SO_RCVBUF 8 +#define SO_SNDBUFFORCE 32 +#define SO_RCVBUFFORCE 33 +#define SO_KEEPALIVE 9 +#define SO_OOBINLINE 10 +#define SO_NO_CHECK 11 +#define SO_PRIORITY 12 +#define SO_LINGER 13 +#define SO_BSDCOMPAT 14 +/* To add :#define SO_REUSEPORT 15 */ +#define SO_PASSCRED 16 +#define SO_PEERCRED 17 +#define SO_RCVLOWAT 18 +#define SO_SNDLOWAT 19 +#define SO_RCVTIMEO 20 +#define SO_SNDTIMEO 21 + +/* Security levels - as per NRL IPv6 - don't actually do anything */ +#define SO_SECURITY_AUTHENTICATION 22 +#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 +#define SO_SECURITY_ENCRYPTION_NETWORK 24 + +#define SO_BINDTODEVICE 25 + +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 + +#define SO_PEERNAME 28 +#define SO_TIMESTAMP 29 +#define SCM_TIMESTAMP SO_TIMESTAMP + +#define SO_ACCEPTCONN 30 + +#define SO_PEERSEC 31 +#define SO_PASSSEC 34 +#define SO_TIMESTAMPNS 35 +#define SCM_TIMESTAMPNS SO_TIMESTAMPNS + +#define SO_MARK 36 + +#define SO_TIMESTAMPING 37 +#define SCM_TIMESTAMPING SO_TIMESTAMPING + +#define SO_PROTOCOL 38 +#define SO_DOMAIN 39 + +#define SO_RXQ_OVFL 40 + +#define SO_WIFI_STATUS 41 +#define SCM_WIFI_STATUS SO_WIFI_STATUS +#define SO_PEEK_OFF 42 + +/* Instruct lower device to use last 4-bytes of skb data as FCS */ +#define SO_NOFCS 43 + +#endif /* _ASM_SOCKET_H */ + + diff --git a/arch/cris/include/uapi/asm/sockios.h b/arch/cris/include/uapi/asm/sockios.h new file mode 100644 index 00000000000..cfe7bfecf59 --- /dev/null +++ b/arch/cris/include/uapi/asm/sockios.h @@ -0,0 +1,13 @@ +#ifndef __ARCH_CRIS_SOCKIOS__ +#define __ARCH_CRIS_SOCKIOS__ + +/* Socket-level I/O control calls. */ +#define FIOSETOWN 0x8901 +#define SIOCSPGRP 0x8902 +#define FIOGETOWN 0x8903 +#define SIOCGPGRP 0x8904 +#define SIOCATMARK 0x8905 +#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */ +#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */ + +#endif diff --git a/arch/cris/include/uapi/asm/stat.h b/arch/cris/include/uapi/asm/stat.h new file mode 100644 index 00000000000..9e558cc3c43 --- /dev/null +++ b/arch/cris/include/uapi/asm/stat.h @@ -0,0 +1,81 @@ +#ifndef _CRIS_STAT_H +#define _CRIS_STAT_H + +/* Keep this a verbatim copy of i386 version; tweak CRIS-specific bits in + the kernel if necessary. */ + +struct __old_kernel_stat { + unsigned short st_dev; + unsigned short st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned long st_size; + unsigned long st_atime; + unsigned long st_mtime; + unsigned long st_ctime; +}; + +#define STAT_HAVE_NSEC 1 + +struct stat { + unsigned long st_dev; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned long st_rdev; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* future possible st_blocks high bits */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned long st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; /* will be high 32 bits of ctime someday */ + + unsigned long long st_ino; +}; + +#endif diff --git a/arch/cris/include/uapi/asm/statfs.h b/arch/cris/include/uapi/asm/statfs.h new file mode 100644 index 00000000000..fdaf921844b --- /dev/null +++ b/arch/cris/include/uapi/asm/statfs.h @@ -0,0 +1,6 @@ +#ifndef _CRIS_STATFS_H +#define _CRIS_STATFS_H + +#include + +#endif diff --git a/arch/cris/include/uapi/asm/swab.h b/arch/cris/include/uapi/asm/swab.h new file mode 100644 index 00000000000..e69de29bb2d diff --git a/arch/cris/include/uapi/asm/sync_serial.h b/arch/cris/include/uapi/asm/sync_serial.h new file mode 100644 index 00000000000..7f827fea30e --- /dev/null +++ b/arch/cris/include/uapi/asm/sync_serial.h @@ -0,0 +1,132 @@ +/* + * ioctl defines for synchronous serial port driver + * + * Copyright (c) 2001-2003 Axis Communications AB + * + * Author: Mikael Starvik + * + */ + +#ifndef SYNC_SERIAL_H +#define SYNC_SERIAL_H + +#include + +#define SSP_SPEED _IOR('S', 0, unsigned int) +#define SSP_MODE _IOR('S', 1, unsigned int) +#define SSP_FRAME_SYNC _IOR('S', 2, unsigned int) +#define SSP_IPOLARITY _IOR('S', 3, unsigned int) +#define SSP_OPOLARITY _IOR('S', 4, unsigned int) +#define SSP_SPI _IOR('S', 5, unsigned int) +#define SSP_INBUFCHUNK _IOR('S', 6, unsigned int) +#define SSP_INPUT _IOR('S', 7, unsigned int) + +/* Values for SSP_SPEED */ +#define SSP150 0 +#define SSP300 1 +#define SSP600 2 +#define SSP1200 3 +#define SSP2400 4 +#define SSP4800 5 +#define SSP9600 6 +#define SSP19200 7 +#define SSP28800 8 +#define SSP57600 9 +#define SSP115200 10 +#define SSP230400 11 +#define SSP460800 12 +#define SSP921600 13 +#define SSP3125000 14 +#define CODEC 15 +#define CODEC_f32768 16 + +#define FREQ_4MHz 0 +#define FREQ_2MHz 1 +#define FREQ_1MHz 2 +#define FREQ_512kHz 3 +#define FREQ_256kHz 4 +#define FREQ_128kHz 5 +#define FREQ_64kHz 6 +#define FREQ_32kHz 7 +/* FREQ_* with values where bit (value & 0x10) is set are */ +/* used for CODEC_f32768 */ +#define FREQ_4096kHz 16 /* CODEC_f32768 */ + +/* Used by application to set CODEC divider, word rate and frame rate */ +#define CODEC_VAL(freq, clk_per_sync, sync_per_frame) \ + ((CODEC + ((freq & 0x10) >> 4)) | (freq << 8) | \ + (clk_per_sync << 16) | (sync_per_frame << 28)) + +/* Used by driver to extract speed */ +#define GET_SPEED(x) (x & 0xff) +#define GET_FREQ(x) ((x & 0xff00) >> 8) +#define GET_WORD_RATE(x) (((x & 0x0fff0000) >> 16) - 1) +#define GET_FRAME_RATE(x) (((x & 0xf0000000) >> 28) - 1) + +/* Values for SSP_MODE */ +#define MASTER_OUTPUT 0 +#define SLAVE_OUTPUT 1 +#define MASTER_INPUT 2 +#define SLAVE_INPUT 3 +#define MASTER_BIDIR 4 +#define SLAVE_BIDIR 5 + +/* Values for SSP_FRAME_SYNC */ +#define NORMAL_SYNC 1 +#define EARLY_SYNC 2 +#define SECOND_WORD_SYNC 0x40000 +#define LATE_SYNC 0x80000 + +#define BIT_SYNC 4 +#define WORD_SYNC 8 +#define EXTENDED_SYNC 0x10 + +#define SYNC_OFF 0x20 +#define SYNC_ON 0x40 +#define WORD_SIZE_8 0x80 +#define WORD_SIZE_12 0x100 +#define WORD_SIZE_16 0x200 +#define WORD_SIZE_24 0x400 +#define WORD_SIZE_32 0x800 +#define BIT_ORDER_LSB 0x1000 +#define BIT_ORDER_MSB 0x2000 +#define FLOW_CONTROL_ENABLE 0x4000 +#define FLOW_CONTROL_DISABLE 0x8000 +#define CLOCK_GATED 0x10000 +#define CLOCK_NOT_GATED 0x20000 + +/* Values for SSP_IPOLARITY and SSP_OPOLARITY */ +#define CLOCK_NORMAL 1 +#define CLOCK_INVERT 2 +#define CLOCK_INEGEDGE CLOCK_NORMAL +#define CLOCK_IPOSEDGE CLOCK_INVERT +#define FRAME_NORMAL 4 +#define FRAME_INVERT 8 +#define STATUS_NORMAL 0x10 +#define STATUS_INVERT 0x20 + +/* Values for SSP_SPI */ +#define SPI_MASTER 0 +#define SPI_SLAVE 1 + +/* Values for SSP_INBUFCHUNK */ +/* plain integer with the size of DMA chunks */ + +/* To ensure that the timestamps are aligned with the data being read + * the read length MUST be a multiple of the length of the DMA buffers. + * + * Use a multiple of SSP_INPUT_CHUNK_SIZE defined below. + */ +#define SSP_INPUT_CHUNK_SIZE 256 + +/* Request struct to pass through the ioctl interface to read + * data with timestamps. + */ +struct ssp_request { + char __user *buf; /* Where to put the data. */ + size_t len; /* Size of buf. MUST be a multiple of */ + /* SSP_INPUT_CHUNK_SIZE! */ + struct timespec ts; /* The time the data was sampled. */ +}; + +#endif diff --git a/arch/cris/include/uapi/asm/termbits.h b/arch/cris/include/uapi/asm/termbits.h new file mode 100644 index 00000000000..1c43bc874cc --- /dev/null +++ b/arch/cris/include/uapi/asm/termbits.h @@ -0,0 +1,235 @@ +/* $Id: termbits.h,v 1.1 2000/07/10 16:32:31 bjornw Exp $ */ + +#ifndef __ARCH_ETRAX100_TERMBITS_H__ +#define __ARCH_ETRAX100_TERMBITS_H__ + +#include + +typedef unsigned char cc_t; +typedef unsigned int speed_t; +typedef unsigned int tcflag_t; + +#define NCCS 19 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +struct termios2 { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +struct ktermios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ + speed_t c_ispeed; /* input speed */ + speed_t c_ospeed; /* output speed */ +}; + +/* c_cc characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VTIME 5 +#define VMIN 6 +#define VSWTC 7 +#define VSTART 8 +#define VSTOP 9 +#define VSUSP 10 +#define VEOL 11 +#define VREPRINT 12 +#define VDISCARD 13 +#define VWERASE 14 +#define VLNEXT 15 +#define VEOL2 16 + +/* c_iflag bits */ +#define IGNBRK 0000001 +#define BRKINT 0000002 +#define IGNPAR 0000004 +#define PARMRK 0000010 +#define INPCK 0000020 +#define ISTRIP 0000040 +#define INLCR 0000100 +#define IGNCR 0000200 +#define ICRNL 0000400 +#define IUCLC 0001000 +#define IXON 0002000 +#define IXANY 0004000 +#define IXOFF 0010000 +#define IMAXBEL 0020000 +#define IUTF8 0040000 + +/* c_oflag bits */ +#define OPOST 0000001 +#define OLCUC 0000002 +#define ONLCR 0000004 +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 + +/* c_cflag bit meaning */ +/* + * 3 2 1 + * 10 987 654 321 098 765 432 109 876 543 210 + * | | ||| CBAUD + * obaud + * + * ||CSIZE + * + * |CSTOP + * |CREAD + * |CPARENB + * + * |CPARODD + * |HUPCL + * |CLOCAL + * |CBAUDEX + * 10 987 654 321 098 765 432 109 876 543 210 + * | || || CIBAUD, IBSHIFT=16 + * ibaud + * |CMSPAR + * | CRTSCTS + * x x xxx xxx x x xx Free bits + */ + +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 +#define CS5 0000000 +#define CS6 0000020 +#define CS7 0000040 +#define CS8 0000060 +#define CSTOPB 0000100 +#define CREAD 0000200 +#define PARENB 0000400 +#define PARODD 0001000 +#define HUPCL 0002000 +#define CLOCAL 0004000 +#define CBAUDEX 0010000 +#define BOTHER 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 + +/* Unsupported rates, but needed to avoid compile error. */ +#define B500000 0010005 +#define B576000 0010006 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 + +/* etrax supports these additional three baud rates */ +#define B921600 0010005 +#define B1843200 0010006 +#define B6250000 0010007 +/* ETRAX FS supports this as well */ +#define B12500000 0010010 +#define CIBAUD 002003600000 /* input baud rate (used in v32) */ +/* The values for CIBAUD bits are the same as the values for CBAUD and CBAUDEX + * shifted left IBSHIFT bits. + */ +#define IBSHIFT 16 +#define CMSPAR 010000000000 /* mark or space (stick) parity - PARODD=space*/ +#define CRTSCTS 020000000000 /* flow control */ + +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 +#define EXTPROC 0200000 + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 +#define TCOON 1 +#define TCIOFF 2 +#define TCION 3 + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 +#define TCOFLUSH 1 +#define TCIOFLUSH 2 + +/* tcsetattr uses these */ +#define TCSANOW 0 +#define TCSADRAIN 1 +#define TCSAFLUSH 2 + +#endif diff --git a/arch/cris/include/uapi/asm/termios.h b/arch/cris/include/uapi/asm/termios.h new file mode 100644 index 00000000000..0a0386a5502 --- /dev/null +++ b/arch/cris/include/uapi/asm/termios.h @@ -0,0 +1,45 @@ +#ifndef _UAPI_CRIS_TERMIOS_H +#define _UAPI_CRIS_TERMIOS_H + +#include +#include +#include +#include + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; + +/* modem lines */ +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ + + +#endif /* _UAPI_CRIS_TERMIOS_H */ diff --git a/arch/cris/include/uapi/asm/types.h b/arch/cris/include/uapi/asm/types.h new file mode 100644 index 00000000000..9ec9d4c5ac4 --- /dev/null +++ b/arch/cris/include/uapi/asm/types.h @@ -0,0 +1 @@ +#include diff --git a/arch/cris/include/uapi/asm/unistd.h b/arch/cris/include/uapi/asm/unistd.h new file mode 100644 index 00000000000..48842896f6c --- /dev/null +++ b/arch/cris/include/uapi/asm/unistd.h @@ -0,0 +1,344 @@ +#ifndef _UAPI_ASM_CRIS_UNISTD_H_ +#define _UAPI_ASM_CRIS_UNISTD_H_ + +/* + * This file contains the system call numbers, and stub macros for libc. + */ + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 + +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +/* 223 is unused */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 +#define __NR_fadvise64 250 +/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */ +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_epoll_create 254 +#define __NR_epoll_ctl 255 +#define __NR_epoll_wait 256 +#define __NR_remap_file_pages 257 +#define __NR_set_tid_address 258 +#define __NR_timer_create 259 +#define __NR_timer_settime (__NR_timer_create+1) +#define __NR_timer_gettime (__NR_timer_create+2) +#define __NR_timer_getoverrun (__NR_timer_create+3) +#define __NR_timer_delete (__NR_timer_create+4) +#define __NR_clock_settime (__NR_timer_create+5) +#define __NR_clock_gettime (__NR_timer_create+6) +#define __NR_clock_getres (__NR_timer_create+7) +#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_statfs64 268 +#define __NR_fstatfs64 269 +#define __NR_tgkill 270 +#define __NR_utimes 271 +#define __NR_fadvise64_64 272 +#define __NR_vserver 273 +#define __NR_mbind 274 +#define __NR_get_mempolicy 275 +#define __NR_set_mempolicy 276 +#define __NR_mq_open 277 +#define __NR_mq_unlink (__NR_mq_open+1) +#define __NR_mq_timedsend (__NR_mq_open+2) +#define __NR_mq_timedreceive (__NR_mq_open+3) +#define __NR_mq_notify (__NR_mq_open+4) +#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_kexec_load 283 +#define __NR_waitid 284 +/* #define __NR_sys_setaltroot 285 */ +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 +#define __NR_ioprio_set 289 +#define __NR_ioprio_get 290 +#define __NR_inotify_init 291 +#define __NR_inotify_add_watch 292 +#define __NR_inotify_rm_watch 293 +#define __NR_migrate_pages 294 +#define __NR_openat 295 +#define __NR_mkdirat 296 +#define __NR_mknodat 297 +#define __NR_fchownat 298 +#define __NR_futimesat 299 +#define __NR_fstatat64 300 +#define __NR_unlinkat 301 +#define __NR_renameat 302 +#define __NR_linkat 303 +#define __NR_symlinkat 304 +#define __NR_readlinkat 305 +#define __NR_fchmodat 306 +#define __NR_faccessat 307 +#define __NR_pselect6 308 +#define __NR_ppoll 309 +#define __NR_unshare 310 +#define __NR_set_robust_list 311 +#define __NR_get_robust_list 312 +#define __NR_splice 313 +#define __NR_sync_file_range 314 +#define __NR_tee 315 +#define __NR_vmsplice 316 +#define __NR_move_pages 317 +#define __NR_getcpu 318 +#define __NR_epoll_pwait 319 +#define __NR_utimensat 320 +#define __NR_signalfd 321 +#define __NR_timerfd_create 322 +#define __NR_eventfd 323 +#define __NR_fallocate 324 +#define __NR_timerfd_settime 325 +#define __NR_timerfd_gettime 326 +#define __NR_signalfd4 327 +#define __NR_eventfd2 328 +#define __NR_epoll_create1 329 +#define __NR_dup3 330 +#define __NR_pipe2 331 +#define __NR_inotify_init1 332 +#define __NR_preadv 333 +#define __NR_pwritev 334 +#define __NR_setns 335 + +#endif /* _UAPI_ASM_CRIS_UNISTD_H_ */ -- cgit v1.2.3-70-g09d2 From 6c9c6d6301287e369a754d628230fa6e50cdb74b Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Mon, 8 Oct 2012 11:08:06 -0600 Subject: dma-debug: New interfaces to debug dma mapping errors Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. This interface clears a flag set by debug_dma_map_page() to indicate that dma_mapping_error() has been called by the driver. When driver does unmap, debug_dma_unmap() checks the flag and if this flag is still set, prints warning message that includes call trace that leads up to the unmap. This interface can be called from dma_mapping_error() routines to enable dma mapping error check debugging. Tested: Intel iommu and swiotlb (iommu=soft) on x86-64 with CONFIG_DMA_API_DEBUG enabled and disabled. Signed-off-by: Shuah Khan Reviewed-by: Konrad Rzeszutek Wilk Signed-off-by: Joerg Roedel --- Documentation/DMA-API.txt | 12 +++++++ arch/x86/include/asm/dma-mapping.h | 1 + include/linux/dma-debug.h | 7 ++++ lib/dma-debug.c | 71 +++++++++++++++++++++++++++++++++++--- 4 files changed, 87 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/Documentation/DMA-API.txt b/Documentation/DMA-API.txt index 66bd97a95f1..78a6c569d20 100644 --- a/Documentation/DMA-API.txt +++ b/Documentation/DMA-API.txt @@ -678,3 +678,15 @@ out of dma_debug_entries. These entries are preallocated at boot. The number of preallocated entries is defined per architecture. If it is too low for you boot with 'dma_debug_entries=' to overwrite the architectural default. + +void debug_dmap_mapping_error(struct device *dev, dma_addr_t dma_addr); + +dma-debug interface debug_dma_mapping_error() to debug drivers that fail +to check dma mapping errors on addresses returned by dma_map_single() and +dma_map_page() interfaces. This interface clears a flag set by +debug_dma_map_page() to indicate that dma_mapping_error() has been called by +the driver. When driver does unmap, debug_dma_unmap() checks the flag and if +this flag is still set, prints warning message that includes call trace that +leads up to the unmap. This interface can be called from dma_mapping_error() +routines to enable dma mapping error check debugging. + diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h index f7b4c7903e7..808dae63eee 100644 --- a/arch/x86/include/asm/dma-mapping.h +++ b/arch/x86/include/asm/dma-mapping.h @@ -47,6 +47,7 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev) static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { struct dma_map_ops *ops = get_dma_ops(dev); + debug_dma_mapping_error(dev, dma_addr); if (ops->mapping_error) return ops->mapping_error(dev, dma_addr); diff --git a/include/linux/dma-debug.h b/include/linux/dma-debug.h index 171ad8aedc8..fc0e34ce038 100644 --- a/include/linux/dma-debug.h +++ b/include/linux/dma-debug.h @@ -39,6 +39,8 @@ extern void debug_dma_map_page(struct device *dev, struct page *page, int direction, dma_addr_t dma_addr, bool map_single); +extern void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr); + extern void debug_dma_unmap_page(struct device *dev, dma_addr_t addr, size_t size, int direction, bool map_single); @@ -105,6 +107,11 @@ static inline void debug_dma_map_page(struct device *dev, struct page *page, { } +static inline void debug_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ +} + static inline void debug_dma_unmap_page(struct device *dev, dma_addr_t addr, size_t size, int direction, bool map_single) diff --git a/lib/dma-debug.c b/lib/dma-debug.c index d84beb994f3..59f4a1a8187 100644 --- a/lib/dma-debug.c +++ b/lib/dma-debug.c @@ -45,6 +45,12 @@ enum { dma_debug_coherent, }; +enum map_err_types { + MAP_ERR_CHECK_NOT_APPLICABLE, + MAP_ERR_NOT_CHECKED, + MAP_ERR_CHECKED, +}; + #define DMA_DEBUG_STACKTRACE_ENTRIES 5 struct dma_debug_entry { @@ -57,6 +63,7 @@ struct dma_debug_entry { int direction; int sg_call_ents; int sg_mapped_ents; + enum map_err_types map_err_type; #ifdef CONFIG_STACKTRACE struct stack_trace stacktrace; unsigned long st_entries[DMA_DEBUG_STACKTRACE_ENTRIES]; @@ -114,6 +121,12 @@ static struct device_driver *current_driver __read_mostly; static DEFINE_RWLOCK(driver_name_lock); +static const char *const maperr2str[] = { + [MAP_ERR_CHECK_NOT_APPLICABLE] = "dma map error check not applicable", + [MAP_ERR_NOT_CHECKED] = "dma map error not checked", + [MAP_ERR_CHECKED] = "dma map error checked", +}; + static const char *type2name[4] = { "single", "page", "scather-gather", "coherent" }; @@ -376,11 +389,12 @@ void debug_dma_dump_mappings(struct device *dev) list_for_each_entry(entry, &bucket->list, list) { if (!dev || dev == entry->dev) { dev_info(entry->dev, - "%s idx %d P=%Lx D=%Lx L=%Lx %s\n", + "%s idx %d P=%Lx D=%Lx L=%Lx %s %s\n", type2name[entry->type], idx, (unsigned long long)entry->paddr, entry->dev_addr, entry->size, - dir2name[entry->direction]); + dir2name[entry->direction], + maperr2str[entry->map_err_type]); } } @@ -838,13 +852,28 @@ static __init int dma_debug_entries_cmdline(char *str) __setup("dma_debug=", dma_debug_cmdline); __setup("dma_debug_entries=", dma_debug_entries_cmdline); +/* Calling dma_mapping_error() from dma-debug api will result in calling + debug_dma_mapping_error() - need internal mapping error routine to + avoid debug checks */ +#ifndef DMA_ERROR_CODE +#define DMA_ERROR_CODE 0 +#endif +static inline int has_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + const struct dma_map_ops *ops = get_dma_ops(dev); + if (ops->mapping_error) + return ops->mapping_error(dev, dma_addr); + + return (dma_addr == DMA_ERROR_CODE); +} + static void check_unmap(struct dma_debug_entry *ref) { struct dma_debug_entry *entry; struct hash_bucket *bucket; unsigned long flags; - if (dma_mapping_error(ref->dev, ref->dev_addr)) { + if (unlikely(has_mapping_error(ref->dev, ref->dev_addr))) { err_printk(ref->dev, NULL, "DMA-API: device driver tries " "to free an invalid DMA memory address\n"); return; @@ -910,6 +939,15 @@ static void check_unmap(struct dma_debug_entry *ref) dir2name[ref->direction]); } + if (entry->map_err_type == MAP_ERR_NOT_CHECKED) { + err_printk(ref->dev, entry, + "DMA-API: device driver failed to check map error" + "[device address=0x%016llx] [size=%llu bytes] " + "[mapped as %s]", + ref->dev_addr, ref->size, + type2name[entry->type]); + } + hash_bucket_del(entry); dma_entry_free(entry); @@ -1017,7 +1055,7 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset, if (unlikely(global_disable)) return; - if (unlikely(dma_mapping_error(dev, dma_addr))) + if (unlikely(has_mapping_error(dev, dma_addr))) return; entry = dma_entry_alloc(); @@ -1030,6 +1068,7 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset, entry->dev_addr = dma_addr; entry->size = size; entry->direction = direction; + entry->map_err_type = MAP_ERR_NOT_CHECKED; if (map_single) entry->type = dma_debug_single; @@ -1045,6 +1084,30 @@ void debug_dma_map_page(struct device *dev, struct page *page, size_t offset, } EXPORT_SYMBOL(debug_dma_map_page); +void debug_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) +{ + struct dma_debug_entry ref; + struct dma_debug_entry *entry; + struct hash_bucket *bucket; + unsigned long flags; + + if (unlikely(global_disable)) + return; + + ref.dev = dev; + ref.dev_addr = dma_addr; + bucket = get_hash_bucket(&ref, &flags); + entry = bucket_find_exact(bucket, &ref); + + if (!entry) + goto out; + + entry->map_err_type = MAP_ERR_CHECKED; +out: + put_hash_bucket(bucket, &flags); +} +EXPORT_SYMBOL(debug_dma_mapping_error); + void debug_dma_unmap_page(struct device *dev, dma_addr_t addr, size_t size, int direction, bool map_single) { -- cgit v1.2.3-70-g09d2 From d48444cf39161bca014b9f6402e409d3e193e530 Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Wed, 24 Oct 2012 17:56:33 +0200 Subject: openrisc: Use Kbuild infrastructure for kvm_para.h All the headers but kvm_para.h use the Kbuild infrastructure to get to the asm-generic headers. Cc: linux-kbuild@vger.kernel.org Cc: linux@lists.openrisc.net Signed-off-by: Steven Rostedt Signed-off-by: Jonas Bonn --- arch/openrisc/include/asm/Kbuild | 1 + arch/openrisc/include/uapi/asm/kvm_para.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) delete mode 100644 arch/openrisc/include/uapi/asm/kvm_para.h (limited to 'arch') diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild index 78de6805268..9430b8c50a0 100644 --- a/arch/openrisc/include/asm/Kbuild +++ b/arch/openrisc/include/asm/Kbuild @@ -32,6 +32,7 @@ generic-y += ipcbuf.h generic-y += irq_regs.h generic-y += kdebug.h generic-y += kmap_types.h +generic-y += kvm_para.h generic-y += local.h generic-y += mman.h generic-y += module.h diff --git a/arch/openrisc/include/uapi/asm/kvm_para.h b/arch/openrisc/include/uapi/asm/kvm_para.h deleted file mode 100644 index 14fab8f0b95..00000000000 --- a/arch/openrisc/include/uapi/asm/kvm_para.h +++ /dev/null @@ -1 +0,0 @@ -#include -- cgit v1.2.3-70-g09d2 From 634bd40a894d64df09ba36c12bb6e70787989ba9 Mon Sep 17 00:00:00 2001 From: James Hogan Date: Thu, 11 Oct 2012 10:03:01 +0100 Subject: openrisc: use kbuild.h instead of defining macros in asm-offset.c This is modelled on commits such as the one below: Commit fc1c3a003edb8a6778e64e10ef671a38c76c969e ("sh: use kbuild.h instead of defining macros in asm-offsets.c") introduced in v2.6.26. Signed-off-by: James Hogan Signed-off-by: Jonas Bonn --- arch/openrisc/kernel/asm-offsets.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/openrisc/kernel/asm-offsets.c b/arch/openrisc/kernel/asm-offsets.c index 1a242a0d758..ddb73685586 100644 --- a/arch/openrisc/kernel/asm-offsets.c +++ b/arch/openrisc/kernel/asm-offsets.c @@ -34,15 +34,11 @@ #include #include #include +#include #include #include #include -#define DEFINE(sym, val) \ - asm volatile("\n->" #sym " %0 " #val : : "i" (val)) - -#define BLANK() asm volatile("\n->" : : ) - int main(void) { /* offsets into the task_struct */ -- cgit v1.2.3-70-g09d2 From 9b04ebd1584766229c58fedaa8fe4dfff575ac3a Mon Sep 17 00:00:00 2001 From: James Hogan Date: Tue, 23 Oct 2012 10:21:57 +0100 Subject: asm-generic/io.h: remove asm/cacheflush.h include Including from prevents cacheflush.h being able to use I/O functions like readl and writel due to circular include dependencies. It doesn't appear as if anything from cacheflush.h is actually used by the generic io.h, so remove the include. I've compile tested a defconfig compilation of blackfin, openrisc (which needed including from it's to get the PAGE_* definitions), and xtensa. Other architectures which use asm-generic/io.h are score and unicore32, and looking at their io.h I don't see any obvious problems. Signed-off-by: James Hogan Acked-by: Jonas Bonn Cc: Chris Zankel Cc: Max Filippov Cc: Mike Frysinger Cc: Chen Liqin Cc: Lennox Wu Cc: Guan Xuetao Signed-off-by: Arnd Bergmann --- arch/openrisc/include/asm/io.h | 1 + include/asm-generic/io.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h index 07f5299d6c2..7c691399da3 100644 --- a/arch/openrisc/include/asm/io.h +++ b/arch/openrisc/include/asm/io.h @@ -30,6 +30,7 @@ #define PIO_MASK 0 #include +#include extern void __iomem *__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot); diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 448303bdb85..616eea53d63 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -12,7 +12,6 @@ #define __ASM_GENERIC_IO_H #include /* I/O is all done through memory accesses */ -#include #include #ifdef CONFIG_GENERIC_IOMAP -- cgit v1.2.3-70-g09d2 From 49839dc93970789cea46f5171cd7f6ec11af64c7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 6 Nov 2012 16:31:32 +0000 Subject: Revert "ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints" This reverts commit 3db11feffc1ad2ab9dea27789e6b5b3032827adc (ARM: OMAP: convert I2C driver to PM QoS for MPU latency constraints). This commit causes I2C timeouts to appear on several OMAP3430/3530-based boards: http://marc.info/?l=linux-arm-kernel&m=135071372426971&w=2 http://marc.info/?l=linux-arm-kernel&m=135067558415214&w=2 http://marc.info/?l=linux-arm-kernel&m=135216013608196&w=2 and appears to have been sent for merging before one of its prerequisites was merged: http://marc.info/?l=linux-arm-kernel&m=135219411617621&w=2 Signed-off-by: Paul Walmsley Acked-by: Jean Pihet Signed-off-by: Wolfram Sang --- arch/arm/plat-omap/i2c.c | 21 +++++++++++++++++++++ drivers/i2c/busses/i2c-omap.c | 32 ++++++++++++++------------------ include/linux/i2c-omap.h | 1 + 3 files changed, 36 insertions(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5683a84c6e..6013831a043 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -26,12 +26,14 @@ #include #include #include +#include #include #include #include #include #include +#include #include #define OMAP_I2C_SIZE 0x3f @@ -127,6 +129,16 @@ static inline int omap1_i2c_add_bus(int bus_id) #ifdef CONFIG_ARCH_OMAP2PLUS +/* + * XXX This function is a temporary compatibility wrapper - only + * needed until the I2C driver can be converted to call + * omap_pm_set_max_dev_wakeup_lat() and handle a return code. + */ +static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) +{ + omap_pm_set_max_mpu_wakeup_lat(dev, t); +} + static inline int omap2_i2c_add_bus(int bus_id) { int l; @@ -158,6 +170,15 @@ static inline int omap2_i2c_add_bus(int bus_id) dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr; pdata->flags = dev_attr->flags; + /* + * When waiting for completion of a i2c transfer, we need to + * set a wake up latency constraint for the MPU. This is to + * ensure quick enough wakeup from idle, when transfer + * completes. + * Only omap3 has support for constraints + */ + if (cpu_is_omap34xx()) + pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(struct omap_i2c_bus_platform_data), NULL, 0, 0); diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index db31eaed6ea..0b0254312d2 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -43,7 +43,6 @@ #include #include #include -#include /* I2C controller revisions */ #define OMAP_I2C_OMAP1_REV_2 0x20 @@ -187,8 +186,9 @@ struct omap_i2c_dev { int reg_shift; /* bit shift for I2C register addresses */ struct completion cmd_complete; struct resource *ioarea; - u32 latency; /* maximum MPU wkup latency */ - struct pm_qos_request pm_qos_request; + u32 latency; /* maximum mpu wkup latency */ + void (*set_mpu_wkup_lat)(struct device *dev, + long latency); u32 speed; /* Speed of bus in kHz */ u32 dtrev; /* extra revision from DT */ u32 flags; @@ -494,7 +494,9 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) dev->b_hw = 1; /* Enable hardware fixes */ /* calculate wakeup latency constraint for MPU */ - dev->latency = (1000000 * dev->threshold) / (1000 * dev->speed / 8); + if (dev->set_mpu_wkup_lat != NULL) + dev->latency = (1000000 * dev->threshold) / + (1000 * dev->speed / 8); } /* @@ -629,16 +631,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) if (r < 0) goto out; - /* - * When waiting for completion of a i2c transfer, we need to - * set a wake up latency constraint for the MPU. This is to - * ensure quick enough wakeup from idle, when transfer - * completes. - */ - if (dev->latency) - pm_qos_add_request(&dev->pm_qos_request, - PM_QOS_CPU_DMA_LATENCY, - dev->latency); + if (dev->set_mpu_wkup_lat != NULL) + dev->set_mpu_wkup_lat(dev->dev, dev->latency); for (i = 0; i < num; i++) { r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1))); @@ -646,8 +640,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) break; } - if (dev->latency) - pm_qos_remove_request(&dev->pm_qos_request); + if (dev->set_mpu_wkup_lat != NULL) + dev->set_mpu_wkup_lat(dev->dev, -1); if (r == 0) r = num; @@ -1104,6 +1098,7 @@ omap_i2c_probe(struct platform_device *pdev) } else if (pdata != NULL) { dev->speed = pdata->clkrate; dev->flags = pdata->flags; + dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; dev->dtrev = pdata->rev; } @@ -1159,8 +1154,9 @@ omap_i2c_probe(struct platform_device *pdev) dev->b_hw = 1; /* Enable hardware fixes */ /* calculate wakeup latency constraint for MPU */ - dev->latency = (1000000 * dev->fifo_size) / - (1000 * dev->speed / 8); + if (dev->set_mpu_wkup_lat != NULL) + dev->latency = (1000000 * dev->fifo_size) / + (1000 * dev->speed / 8); } /* reset ASAP, clearing any IRQs */ diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index df804ba73e0..92a0dc75bc7 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -34,6 +34,7 @@ struct omap_i2c_bus_platform_data { u32 clkrate; u32 rev; u32 flags; + void (*set_mpu_wkup_lat)(struct device *dev, long set); }; #endif -- cgit v1.2.3-70-g09d2 From 2c88ab8c5af7d637d2a9d14b607fa6100fa64236 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti D Date: Mon, 5 Nov 2012 17:53:39 +0530 Subject: ARM: i2c: omap: Remove the i207 errata flag The commit [i2c: omap: use revision check for OMAP_I2C_FLAG_APPLY_ERRATA_I207] uses the revision id instead of the flag. So the flag can be safely removed. Reviewed-by: Felipe Balbi Signed-off-by: Shubhrajyoti D Signed-off-by: Wolfram Sang --- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 3 +-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +++------ drivers/i2c/busses/i2c-omap.c | 3 +-- include/linux/i2c-omap.h | 1 - 4 files changed, 5 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index c455e41b023..b79ccf6efbe 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -76,8 +76,7 @@ static struct omap_hwmod_class i2c_class = { static struct omap_i2c_dev_attr i2c_dev_attr = { .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_BUS_SHIFT_2 | + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 | OMAP_I2C_FLAG_FORCE_19200_INT_CLK, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index f67b7ee07dd..943222c4048 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -791,8 +791,7 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { /* I2C1 */ static struct omap_i2c_dev_attr i2c1_dev_attr = { .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | OMAP_I2C_FLAG_BUS_SHIFT_2, }; @@ -818,8 +817,7 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { /* I2C2 */ static struct omap_i2c_dev_attr i2c2_dev_attr = { .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | OMAP_I2C_FLAG_BUS_SHIFT_2, }; @@ -845,8 +843,7 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { /* I2C3 */ static struct omap_i2c_dev_attr i2c3_dev_attr = { .fifo_depth = 64, /* bytes */ - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | OMAP_I2C_FLAG_BUS_SHIFT_2, }; diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 0ca50e71731..11e645ab1e7 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1028,8 +1028,7 @@ static const struct i2c_algorithm omap_i2c_algo = { #ifdef CONFIG_OF static struct omap_i2c_bus_platform_data omap3_pdata = { .rev = OMAP_I2C_IP_VERSION_1, - .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | + .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | OMAP_I2C_FLAG_BUS_SHIFT_2, }; diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index 92a0dc75bc7..1b25c04f82d 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -21,7 +21,6 @@ #define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1) #define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2) #define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3) -#define OMAP_I2C_FLAG_APPLY_ERRATA_I207 BIT(4) #define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5) #define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6) /* how the CPU address bus must be translated for I2C unit access */ -- cgit v1.2.3-70-g09d2 From e81b3295bc54eb0d03f4cdfc8cbf72e731d1b402 Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Tue, 2 Oct 2012 16:55:01 +0000 Subject: powerpc+of: Add /proc device tree updating to of node add/remove When adding or removing a device tree node we should also update the device tree in /proc/device-tree. This action is already done in the generic OF code for adding/removing properties of a node. This patch adds this functionality for nodes. Signed-off-by: Nathan Fontenot Acked-by: Rob Herring Acked-by: Grant Likely Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/pseries/dlpar.c | 24 -------------- arch/powerpc/platforms/pseries/reconfig.c | 47 -------------------------- drivers/of/base.c | 55 ++++++++++++++++++++++++++++--- 3 files changed, 51 insertions(+), 75 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c index 0f1b706506e..e36789bd4e6 100644 --- a/arch/powerpc/platforms/pseries/dlpar.c +++ b/arch/powerpc/platforms/pseries/dlpar.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -255,9 +254,6 @@ static struct device_node *derive_parent(const char *path) int dlpar_attach_node(struct device_node *dn) { -#ifdef CONFIG_PROC_DEVICETREE - struct proc_dir_entry *ent; -#endif int rc; of_node_set_flag(dn, OF_DYNAMIC); @@ -274,32 +270,12 @@ int dlpar_attach_node(struct device_node *dn) } of_attach_node(dn); - -#ifdef CONFIG_PROC_DEVICETREE - ent = proc_mkdir(strrchr(dn->full_name, '/') + 1, dn->parent->pde); - if (ent) - proc_device_tree_add_node(dn, ent); -#endif - of_node_put(dn->parent); return 0; } int dlpar_detach_node(struct device_node *dn) { -#ifdef CONFIG_PROC_DEVICETREE - struct device_node *parent = dn->parent; - struct property *prop = dn->properties; - - while (prop) { - remove_proc_entry(prop->name, dn->pde); - prop = prop->next; - } - - if (dn->pde) - remove_proc_entry(dn->pde->name, parent->pde); -#endif - pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, dn); of_detach_node(dn); of_node_put(dn); /* Must decrement the refcount */ diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index 39f71fba9b3..f99f1ca8035 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -23,48 +23,6 @@ #include #include - - -/* - * Routines for "runtime" addition and removal of device tree nodes. - */ -#ifdef CONFIG_PROC_DEVICETREE -/* - * Add a node to /proc/device-tree. - */ -static void add_node_proc_entries(struct device_node *np) -{ - struct proc_dir_entry *ent; - - ent = proc_mkdir(strrchr(np->full_name, '/') + 1, np->parent->pde); - if (ent) - proc_device_tree_add_node(np, ent); -} - -static void remove_node_proc_entries(struct device_node *np) -{ - struct property *pp = np->properties; - struct device_node *parent = np->parent; - - while (pp) { - remove_proc_entry(pp->name, np->pde); - pp = pp->next; - } - if (np->pde) - remove_proc_entry(np->pde->name, parent->pde); -} -#else /* !CONFIG_PROC_DEVICETREE */ -static void add_node_proc_entries(struct device_node *np) -{ - return; -} - -static void remove_node_proc_entries(struct device_node *np) -{ - return; -} -#endif /* CONFIG_PROC_DEVICETREE */ - /** * derive_parent - basically like dirname(1) * @path: the full_name of a node to be added to the tree @@ -149,9 +107,6 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist } of_attach_node(np); - - add_node_proc_entries(np); - of_node_put(np->parent); return 0; @@ -179,8 +134,6 @@ static int pSeries_reconfig_remove_node(struct device_node *np) return -EBUSY; } - remove_node_proc_entries(np); - pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, np); of_detach_node(np); diff --git a/drivers/of/base.c b/drivers/of/base.c index af3b22ac762..bbd073f53c9 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1160,6 +1160,22 @@ int prom_update_property(struct device_node *np, * device tree nodes. */ +#ifdef CONFIG_PROC_DEVICETREE +static void of_add_proc_dt_entry(struct device_node *dn) +{ + struct proc_dir_entry *ent; + + ent = proc_mkdir(strrchr(dn->full_name, '/') + 1, dn->parent->pde); + if (ent) + proc_device_tree_add_node(dn, ent); +} +#else +static void of_add_proc_dt_entry(struct device_node *dn) +{ + return; +} +#endif + /** * of_attach_node - Plug a device node into the tree and global list. */ @@ -1173,8 +1189,31 @@ void of_attach_node(struct device_node *np) np->parent->child = np; allnodes = np; write_unlock_irqrestore(&devtree_lock, flags); + + of_add_proc_dt_entry(np); } +#ifdef CONFIG_PROC_DEVICETREE +static void of_remove_proc_dt_entry(struct device_node *dn) +{ + struct device_node *parent = dn->parent; + struct property *prop = dn->properties; + + while (prop) { + remove_proc_entry(prop->name, dn->pde); + prop = prop->next; + } + + if (dn->pde) + remove_proc_entry(dn->pde->name, parent->pde); +} +#else +static void of_remove_proc_dt_entry(struct device_node *dn) +{ + return; +} +#endif + /** * of_detach_node - "Unplug" a node from the device tree. * @@ -1188,9 +1227,17 @@ void of_detach_node(struct device_node *np) write_lock_irqsave(&devtree_lock, flags); + if (of_node_check_flag(np, OF_DETACHED)) { + /* someone already detached it */ + write_unlock_irqrestore(&devtree_lock, flags); + return; + } + parent = np->parent; - if (!parent) - goto out_unlock; + if (!parent) { + write_unlock_irqrestore(&devtree_lock, flags); + return; + } if (allnodes == np) allnodes = np->allnext; @@ -1215,9 +1262,9 @@ void of_detach_node(struct device_node *np) } of_node_set_flag(np, OF_DETACHED); - -out_unlock: write_unlock_irqrestore(&devtree_lock, flags); + + of_remove_proc_dt_entry(np); } #endif /* defined(CONFIG_OF_DYNAMIC) */ -- cgit v1.2.3-70-g09d2 From f59497208363f3dd9d62b79b7f7eafc95432de79 Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Tue, 2 Oct 2012 16:56:11 +0000 Subject: powerpc+of: Move of_drconf_cell struct definition to asm/prom.h This patch moves the definition of the of_drconf_cell struct to asm/prom.h to make it available for all powerpc/pseries code. Signed-off-by: Nathan Fontenot Acked-by: Rob Herring Acked-by: Grant Likely Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/prom.h | 16 ++++++++++++++++ arch/powerpc/mm/numa.c | 12 ------------ 2 files changed, 16 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h index b5c91901e38..99c92d5363e 100644 --- a/arch/powerpc/include/asm/prom.h +++ b/arch/powerpc/include/asm/prom.h @@ -58,6 +58,22 @@ static inline int of_node_to_nid(struct device_node *device) { return 0; } extern void of_instantiate_rtc(void); +/* The of_drconf_cell struct defines the layout of the LMB array + * specified in the device tree property + * ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory + */ +struct of_drconf_cell { + u64 base_addr; + u32 drc_index; + u32 reserved; + u32 aa_index; + u32 flags; +}; + +#define DRCONF_MEM_ASSIGNED 0x00000008 +#define DRCONF_MEM_AI_INVALID 0x00000040 +#define DRCONF_MEM_RESERVED 0x00000080 + /* These includes are put at the bottom because they may contain things * that are overridden by this file. Ideally they shouldn't be included * by this file, but there are a bunch of .c files that currently depend diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 59213cfaeca..bba87ca2b4d 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -399,18 +399,6 @@ static unsigned long read_n_cells(int n, const unsigned int **buf) return result; } -struct of_drconf_cell { - u64 base_addr; - u32 drc_index; - u32 reserved; - u32 aa_index; - u32 flags; -}; - -#define DRCONF_MEM_ASSIGNED 0x00000008 -#define DRCONF_MEM_AI_INVALID 0x00000040 -#define DRCONF_MEM_RESERVED 0x00000080 - /* * Read the next memblock list entry from the ibm,dynamic-memory property * and return the information in the provided of_drconf_cell structure. -- cgit v1.2.3-70-g09d2 From 1cf3d8b3d24cd383ddfd5442c83ec5c355ffc2f7 Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Tue, 2 Oct 2012 16:57:57 +0000 Subject: powerpc+of: Add of node/property notification chain for adds and removes This patch moves the notification chain for updates to the device tree from the powerpc/pseries code to the base OF code. This makes this functionality available to all architectures. Additionally the notification chain is updated to allow notifications for property add/remove/update. To make this work a pointer to a new struct (of_prop_reconfig) is passed to the routines in the notification chain. The of_prop_reconfig property contains a pointer to the node containing the property and a pointer to the property itself. In the case of property updates, the property pointer refers to the new property. Signed-off-by: Nathan Fontenot Acked-by: Rob Herring Acked-by: Grant Likely Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/pSeries_reconfig.h | 32 ----------- arch/powerpc/kernel/prom.c | 6 +- arch/powerpc/platforms/pseries/dlpar.c | 14 +++-- arch/powerpc/platforms/pseries/hotplug-cpu.c | 8 +-- arch/powerpc/platforms/pseries/hotplug-memory.c | 60 ++++++++++++++------ arch/powerpc/platforms/pseries/iommu.c | 6 +- arch/powerpc/platforms/pseries/reconfig.c | 68 ++--------------------- arch/powerpc/platforms/pseries/setup.c | 6 +- drivers/crypto/nx/nx-842.c | 20 +++---- drivers/crypto/nx/nx.c | 1 - drivers/of/base.c | 74 +++++++++++++++++++++++-- include/linux/of.h | 22 ++++++-- 12 files changed, 163 insertions(+), 154 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h index c07edfe98b9..adc00d2e75b 100644 --- a/arch/powerpc/include/asm/pSeries_reconfig.h +++ b/arch/powerpc/include/asm/pSeries_reconfig.h @@ -2,43 +2,11 @@ #define _PPC64_PSERIES_RECONFIG_H #ifdef __KERNEL__ -#include - -/* - * Use this API if your code needs to know about OF device nodes being - * added or removed on pSeries systems. - */ - -#define PSERIES_RECONFIG_ADD 0x0001 -#define PSERIES_RECONFIG_REMOVE 0x0002 -#define PSERIES_DRCONF_MEM_ADD 0x0003 -#define PSERIES_DRCONF_MEM_REMOVE 0x0004 -#define PSERIES_UPDATE_PROPERTY 0x0005 - -/** - * pSeries_reconfig_notify - Notifier value structure for OFDT property updates - * - * @node: Device tree node which owns the property being updated - * @property: Updated property - */ -struct pSeries_reconfig_prop_update { - struct device_node *node; - struct property *property; -}; - #ifdef CONFIG_PPC_PSERIES -extern int pSeries_reconfig_notifier_register(struct notifier_block *); -extern void pSeries_reconfig_notifier_unregister(struct notifier_block *); -extern int pSeries_reconfig_notify(unsigned long action, void *p); /* Not the best place to put this, will be fixed when we move some * of the rtas suspend-me stuff to pseries */ extern void pSeries_coalesce_init(void); #else /* !CONFIG_PPC_PSERIES */ -static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb) -{ - return 0; -} -static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { } static inline void pSeries_coalesce_init(void) { } #endif /* CONFIG_PPC_PSERIES */ diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 37725e86651..6feb60c3c6e 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -49,7 +50,6 @@ #include #include #include -#include #include #include #include @@ -802,7 +802,7 @@ static int prom_reconfig_notifier(struct notifier_block *nb, int err; switch (action) { - case PSERIES_RECONFIG_ADD: + case OF_RECONFIG_ATTACH_NODE: err = of_finish_dynamic_node(node); if (err < 0) printk(KERN_ERR "finish_node returned %d\n", err); @@ -821,7 +821,7 @@ static struct notifier_block prom_reconfig_nb = { static int __init prom_reconfig_setup(void) { - return pSeries_reconfig_notifier_register(&prom_reconfig_nb); + return of_reconfig_notifier_register(&prom_reconfig_nb); } __initcall(prom_reconfig_setup); #endif diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c index e36789bd4e6..a1a7b9a67ff 100644 --- a/arch/powerpc/platforms/pseries/dlpar.c +++ b/arch/powerpc/platforms/pseries/dlpar.c @@ -16,13 +16,13 @@ #include #include #include +#include #include "offline_states.h" #include #include #include #include -#include struct cc_workarea { u32 drc_index; @@ -262,24 +262,26 @@ int dlpar_attach_node(struct device_node *dn) if (!dn->parent) return -ENOMEM; - rc = pSeries_reconfig_notify(PSERIES_RECONFIG_ADD, dn); + rc = of_attach_node(dn); if (rc) { printk(KERN_ERR "Failed to add device node %s\n", dn->full_name); return rc; } - of_attach_node(dn); of_node_put(dn->parent); return 0; } int dlpar_detach_node(struct device_node *dn) { - pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, dn); - of_detach_node(dn); - of_node_put(dn); /* Must decrement the refcount */ + int rc; + + rc = of_detach_node(dn); + if (rc) + return rc; + of_node_put(dn); /* Must decrement the refcount */ return 0; } diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c index 64c97d8ac0c..a38956269fb 100644 --- a/arch/powerpc/platforms/pseries/hotplug-cpu.c +++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c @@ -23,12 +23,12 @@ #include #include /* for idle_task_exit */ #include +#include #include #include #include #include #include -#include #include #include "plpar_wrappers.h" #include "offline_states.h" @@ -333,10 +333,10 @@ static int pseries_smp_notifier(struct notifier_block *nb, int err = 0; switch (action) { - case PSERIES_RECONFIG_ADD: + case OF_RECONFIG_ATTACH_NODE: err = pseries_add_processor(node); break; - case PSERIES_RECONFIG_REMOVE: + case OF_RECONFIG_DETACH_NODE: pseries_remove_processor(node); break; } @@ -399,7 +399,7 @@ static int __init pseries_cpu_hotplug_init(void) /* Processors can be added/removed only on LPAR */ if (firmware_has_feature(FW_FEATURE_LPAR)) { - pSeries_reconfig_notifier_register(&pseries_smp_nb); + of_reconfig_notifier_register(&pseries_smp_nb); cpu_maps_update_begin(); if (cede_offline_enabled && parse_cede_parameters() == 0) { default_offline_state = CPU_STATE_INACTIVE; diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c index ecdb0a6b317..2372c609fa2 100644 --- a/arch/powerpc/platforms/pseries/hotplug-memory.c +++ b/arch/powerpc/platforms/pseries/hotplug-memory.c @@ -16,7 +16,6 @@ #include #include -#include #include static unsigned long get_memblock_size(void) @@ -187,42 +186,69 @@ static int pseries_add_memory(struct device_node *np) return (ret < 0) ? -EINVAL : 0; } -static int pseries_drconf_memory(unsigned long *base, unsigned int action) +static int pseries_update_drconf_memory(struct of_prop_reconfig *pr) { + struct of_drconf_cell *new_drmem, *old_drmem; unsigned long memblock_size; - int rc; + u32 entries; + u32 *p; + int i, rc = -EINVAL; memblock_size = get_memblock_size(); if (!memblock_size) return -EINVAL; - if (action == PSERIES_DRCONF_MEM_ADD) { - rc = memblock_add(*base, memblock_size); - rc = (rc < 0) ? -EINVAL : 0; - } else if (action == PSERIES_DRCONF_MEM_REMOVE) { - rc = pseries_remove_memblock(*base, memblock_size); - } else { - rc = -EINVAL; + p = (u32 *)of_get_property(pr->dn, "ibm,dynamic-memory", NULL); + if (!p) + return -EINVAL; + + /* The first int of the property is the number of lmb's described + * by the property. This is followed by an array of of_drconf_cell + * entries. Get the niumber of entries and skip to the array of + * of_drconf_cell's. + */ + entries = *p++; + old_drmem = (struct of_drconf_cell *)p; + + p = (u32 *)pr->prop->value; + p++; + new_drmem = (struct of_drconf_cell *)p; + + for (i = 0; i < entries; i++) { + if ((old_drmem[i].flags & DRCONF_MEM_ASSIGNED) && + (!(new_drmem[i].flags & DRCONF_MEM_ASSIGNED))) { + rc = pseries_remove_memblock(old_drmem[i].base_addr, + memblock_size); + break; + } else if ((!(old_drmem[i].flags & DRCONF_MEM_ASSIGNED)) && + (new_drmem[i].flags & DRCONF_MEM_ASSIGNED)) { + rc = memblock_add(old_drmem[i].base_addr, + memblock_size); + rc = (rc < 0) ? -EINVAL : 0; + break; + } } return rc; } static int pseries_memory_notifier(struct notifier_block *nb, - unsigned long action, void *node) + unsigned long action, void *node) { + struct of_prop_reconfig *pr; int err = 0; switch (action) { - case PSERIES_RECONFIG_ADD: + case OF_RECONFIG_ATTACH_NODE: err = pseries_add_memory(node); break; - case PSERIES_RECONFIG_REMOVE: + case OF_RECONFIG_DETACH_NODE: err = pseries_remove_memory(node); break; - case PSERIES_DRCONF_MEM_ADD: - case PSERIES_DRCONF_MEM_REMOVE: - err = pseries_drconf_memory(node, action); + case OF_RECONFIG_UPDATE_PROPERTY: + pr = (struct of_prop_reconfig *)node; + if (!strcmp(pr->prop->name, "ibm,dynamic-memory")) + err = pseries_update_drconf_memory(pr); break; } return notifier_from_errno(err); @@ -235,7 +261,7 @@ static struct notifier_block pseries_mem_nb = { static int __init pseries_memory_hotplug_init(void) { if (firmware_has_feature(FW_FEATURE_LPAR)) - pSeries_reconfig_notifier_register(&pseries_mem_nb); + of_reconfig_notifier_register(&pseries_mem_nb); return 0; } diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index 6153eea27ce..da5594c441e 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -36,13 +36,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -1294,7 +1294,7 @@ static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long acti struct direct_window *window; switch (action) { - case PSERIES_RECONFIG_REMOVE: + case OF_RECONFIG_DETACH_NODE: if (pci && pci->iommu_table) iommu_free_table(pci->iommu_table, np->full_name); @@ -1357,7 +1357,7 @@ void iommu_init_early_pSeries(void) } - pSeries_reconfig_notifier_register(&iommu_reconfig_nb); + of_reconfig_notifier_register(&iommu_reconfig_nb); register_memory_notifier(&iommu_mem_nb); set_pci_dma_ops(&dma_iommu_ops); diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index f99f1ca8035..720a0cc2e69 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -16,11 +16,11 @@ #include #include #include +#include #include #include #include -#include #include /** @@ -55,28 +55,6 @@ static struct device_node *derive_parent(const char *path) return parent; } -static BLOCKING_NOTIFIER_HEAD(pSeries_reconfig_chain); - -int pSeries_reconfig_notifier_register(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&pSeries_reconfig_chain, nb); -} -EXPORT_SYMBOL_GPL(pSeries_reconfig_notifier_register); - -void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) -{ - blocking_notifier_chain_unregister(&pSeries_reconfig_chain, nb); -} -EXPORT_SYMBOL_GPL(pSeries_reconfig_notifier_unregister); - -int pSeries_reconfig_notify(unsigned long action, void *p) -{ - int err = blocking_notifier_call_chain(&pSeries_reconfig_chain, - action, p); - - return notifier_to_errno(err); -} - static int pSeries_reconfig_add_node(const char *path, struct property *proplist) { struct device_node *np; @@ -100,13 +78,12 @@ static int pSeries_reconfig_add_node(const char *path, struct property *proplist goto out_err; } - err = pSeries_reconfig_notify(PSERIES_RECONFIG_ADD, np); + err = of_attach_node(np); if (err) { printk(KERN_ERR "Failed to add device node %s\n", path); goto out_err; } - of_attach_node(np); of_node_put(np->parent); return 0; @@ -134,9 +111,7 @@ static int pSeries_reconfig_remove_node(struct device_node *np) return -EBUSY; } - pSeries_reconfig_notify(PSERIES_RECONFIG_REMOVE, np); of_detach_node(np); - of_node_put(parent); of_node_put(np); /* Must decrement the refcount */ return 0; @@ -381,10 +356,9 @@ static int do_remove_property(char *buf, size_t bufsize) static int do_update_property(char *buf, size_t bufsize) { struct device_node *np; - struct pSeries_reconfig_prop_update upd_value; unsigned char *value; char *name, *end, *next_prop; - int rc, length; + int length; struct property *newprop; buf = parse_node(buf, bufsize, &np); end = buf + bufsize; @@ -406,41 +380,7 @@ static int do_update_property(char *buf, size_t bufsize) if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size")) slb_set_size(*(int *)value); - upd_value.node = np; - upd_value.property = newprop; - pSeries_reconfig_notify(PSERIES_UPDATE_PROPERTY, &upd_value); - - rc = prom_update_property(np, newprop); - if (rc) - return rc; - - /* For memory under the ibm,dynamic-reconfiguration-memory node - * of the device tree, adding and removing memory is just an update - * to the ibm,dynamic-memory property instead of adding/removing a - * memory node in the device tree. For these cases we still need to - * involve the notifier chain. - */ - if (!strcmp(name, "ibm,dynamic-memory")) { - int action; - - next_prop = parse_next_property(next_prop, end, &name, - &length, &value); - if (!next_prop) - return -EINVAL; - - if (!strcmp(name, "add")) - action = PSERIES_DRCONF_MEM_ADD; - else - action = PSERIES_DRCONF_MEM_REMOVE; - - rc = pSeries_reconfig_notify(action, value); - if (rc) { - prom_update_property(np, newprop); - return rc; - } - } - - return 0; + return prom_update_property(np, newprop); } /** diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index e3cb7ae6165..e1a5b8a32d2 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include @@ -63,7 +64,6 @@ #include #include #include -#include #include "plpar_wrappers.h" #include "pseries.h" @@ -258,7 +258,7 @@ static int pci_dn_reconfig_notifier(struct notifier_block *nb, unsigned long act int err = NOTIFY_OK; switch (action) { - case PSERIES_RECONFIG_ADD: + case OF_RECONFIG_ATTACH_NODE: pci = np->parent->data; if (pci) { update_dn_pci_info(np, pci->phb); @@ -389,7 +389,7 @@ static void __init pSeries_setup_arch(void) /* Find and initialize PCI host bridges */ init_pci_config_tokens(); find_and_init_phbs(); - pSeries_reconfig_notifier_register(&pci_dn_reconfig_nb); + of_reconfig_notifier_register(&pci_dn_reconfig_nb); pSeries_nvram_init(); diff --git a/drivers/crypto/nx/nx-842.c b/drivers/crypto/nx/nx-842.c index 0ce62573867..6c4c000671c 100644 --- a/drivers/crypto/nx/nx-842.c +++ b/drivers/crypto/nx/nx-842.c @@ -28,7 +28,6 @@ #include #include -#include #include #include "nx_csbcpb.h" /* struct nx_csbcpb */ @@ -1014,26 +1013,23 @@ error_out: * NOTIFY_BAD encoded with error number on failure, use * notifier_to_errno() to decode this value */ -static int nx842_OF_notifier(struct notifier_block *np, - unsigned long action, - void *update) +static int nx842_OF_notifier(struct notifier_block *np, unsigned long action, + void *update) { - struct pSeries_reconfig_prop_update *upd; + struct of_prop_reconfig *upd = update; struct nx842_devdata *local_devdata; struct device_node *node = NULL; - upd = (struct pSeries_reconfig_prop_update *)update; - rcu_read_lock(); local_devdata = rcu_dereference(devdata); if (local_devdata) node = local_devdata->dev->of_node; if (local_devdata && - action == PSERIES_UPDATE_PROPERTY && - !strcmp(upd->node->name, node->name)) { + action == OF_RECONFIG_UPDATE_PROPERTY && + !strcmp(upd->dn->name, node->name)) { rcu_read_unlock(); - nx842_OF_upd(upd->property); + nx842_OF_upd(upd->prop); } else rcu_read_unlock(); @@ -1182,7 +1178,7 @@ static int __init nx842_probe(struct vio_dev *viodev, synchronize_rcu(); kfree(old_devdata); - pSeries_reconfig_notifier_register(&nx842_of_nb); + of_reconfig_notifier_register(&nx842_of_nb); ret = nx842_OF_upd(NULL); if (ret && ret != -ENODEV) { @@ -1228,7 +1224,7 @@ static int __exit nx842_remove(struct vio_dev *viodev) spin_lock_irqsave(&devdata_mutex, flags); old_devdata = rcu_dereference_check(devdata, lockdep_is_held(&devdata_mutex)); - pSeries_reconfig_notifier_unregister(&nx842_of_nb); + of_reconfig_notifier_unregister(&nx842_of_nb); rcu_assign_pointer(devdata, NULL); spin_unlock_irqrestore(&devdata_mutex, flags); synchronize_rcu(); diff --git a/drivers/crypto/nx/nx.c b/drivers/crypto/nx/nx.c index 638110efae9..f7a8a16aa7d 100644 --- a/drivers/crypto/nx/nx.c +++ b/drivers/crypto/nx/nx.c @@ -33,7 +33,6 @@ #include #include #include -#include #include #include diff --git a/drivers/of/base.c b/drivers/of/base.c index bbd073f53c9..87b63850e8d 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1028,6 +1028,24 @@ int of_parse_phandle_with_args(struct device_node *np, const char *list_name, } EXPORT_SYMBOL(of_parse_phandle_with_args); +#if defined(CONFIG_OF_DYNAMIC) +static int of_property_notify(int action, struct device_node *np, + struct property *prop) +{ + struct of_prop_reconfig pr; + + pr.dn = np; + pr.prop = prop; + return of_reconfig_notify(action, &pr); +} +#else +static int of_property_notify(int action, struct device_node *np, + struct property *prop) +{ + return 0; +} +#endif + /** * prom_add_property - Add a property to a node */ @@ -1035,6 +1053,11 @@ int prom_add_property(struct device_node *np, struct property *prop) { struct property **next; unsigned long flags; + int rc; + + rc = of_property_notify(OF_RECONFIG_ADD_PROPERTY, np, prop); + if (rc) + return rc; prop->next = NULL; write_lock_irqsave(&devtree_lock, flags); @@ -1072,6 +1095,11 @@ int prom_remove_property(struct device_node *np, struct property *prop) struct property **next; unsigned long flags; int found = 0; + int rc; + + rc = of_property_notify(OF_RECONFIG_REMOVE_PROPERTY, np, prop); + if (rc) + return rc; write_lock_irqsave(&devtree_lock, flags); next = &np->properties; @@ -1114,7 +1142,11 @@ int prom_update_property(struct device_node *np, { struct property **next, *oldprop; unsigned long flags; - int found = 0; + int rc, found = 0; + + rc = of_property_notify(OF_RECONFIG_UPDATE_PROPERTY, np, newprop); + if (rc) + return rc; if (!newprop->name) return -EINVAL; @@ -1160,6 +1192,26 @@ int prom_update_property(struct device_node *np, * device tree nodes. */ +static BLOCKING_NOTIFIER_HEAD(of_reconfig_chain); + +int of_reconfig_notifier_register(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&of_reconfig_chain, nb); +} + +int of_reconfig_notifier_unregister(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&of_reconfig_chain, nb); +} + +int of_reconfig_notify(unsigned long action, void *p) +{ + int rc; + + rc = blocking_notifier_call_chain(&of_reconfig_chain, action, p); + return notifier_to_errno(rc); +} + #ifdef CONFIG_PROC_DEVICETREE static void of_add_proc_dt_entry(struct device_node *dn) { @@ -1179,9 +1231,14 @@ static void of_add_proc_dt_entry(struct device_node *dn) /** * of_attach_node - Plug a device node into the tree and global list. */ -void of_attach_node(struct device_node *np) +int of_attach_node(struct device_node *np) { unsigned long flags; + int rc; + + rc = of_reconfig_notify(OF_RECONFIG_ATTACH_NODE, np); + if (rc) + return rc; write_lock_irqsave(&devtree_lock, flags); np->sibling = np->parent->child; @@ -1191,6 +1248,7 @@ void of_attach_node(struct device_node *np) write_unlock_irqrestore(&devtree_lock, flags); of_add_proc_dt_entry(np); + return 0; } #ifdef CONFIG_PROC_DEVICETREE @@ -1220,23 +1278,28 @@ static void of_remove_proc_dt_entry(struct device_node *dn) * The caller must hold a reference to the node. The memory associated with * the node is not freed until its refcount goes to zero. */ -void of_detach_node(struct device_node *np) +int of_detach_node(struct device_node *np) { struct device_node *parent; unsigned long flags; + int rc = 0; + + rc = of_reconfig_notify(OF_RECONFIG_DETACH_NODE, np); + if (rc) + return rc; write_lock_irqsave(&devtree_lock, flags); if (of_node_check_flag(np, OF_DETACHED)) { /* someone already detached it */ write_unlock_irqrestore(&devtree_lock, flags); - return; + return rc; } parent = np->parent; if (!parent) { write_unlock_irqrestore(&devtree_lock, flags); - return; + return rc; } if (allnodes == np) @@ -1265,6 +1328,7 @@ void of_detach_node(struct device_node *np) write_unlock_irqrestore(&devtree_lock, flags); of_remove_proc_dt_entry(np); + return rc; } #endif /* defined(CONFIG_OF_DYNAMIC) */ diff --git a/include/linux/of.h b/include/linux/of.h index 72843b72a2b..fb5d87b66e3 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -272,11 +273,24 @@ extern int prom_remove_property(struct device_node *np, struct property *prop); extern int prom_update_property(struct device_node *np, struct property *newprop); -#if defined(CONFIG_OF_DYNAMIC) /* For updating the device tree at runtime */ -extern void of_attach_node(struct device_node *); -extern void of_detach_node(struct device_node *); -#endif +#define OF_RECONFIG_ATTACH_NODE 0x0001 +#define OF_RECONFIG_DETACH_NODE 0x0002 +#define OF_RECONFIG_ADD_PROPERTY 0x0003 +#define OF_RECONFIG_REMOVE_PROPERTY 0x0004 +#define OF_RECONFIG_UPDATE_PROPERTY 0x0005 + +struct of_prop_reconfig { + struct device_node *dn; + struct property *prop; +}; + +extern int of_reconfig_notifier_register(struct notifier_block *); +extern int of_reconfig_notifier_unregister(struct notifier_block *); +extern int of_reconfig_notify(unsigned long, void *); + +extern int of_attach_node(struct device_node *); +extern int of_detach_node(struct device_node *); #define of_match_ptr(_ptr) (_ptr) -- cgit v1.2.3-70-g09d2 From 79d1c712958f94372482ad74578b00f44e744c12 Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Tue, 2 Oct 2012 16:58:46 +0000 Subject: powerpc+of: Rename the drivers/of prom_* functions to of_* Rename the prom_*_property routines of the generic OF code to of_*_property. This brings them in line with the naming used by the rest of the OF code. Signed-off-by: Nathan Fontenot Acked-by: Geoff Levand Acked-by: Rob Herring Acked-by: Grant Likely Signed-off-by: Benjamin Herrenschmidt --- arch/arm/mach-mxs/mach-mxs.c | 2 +- arch/powerpc/kernel/machine_kexec.c | 14 +++++++------- arch/powerpc/kernel/machine_kexec_64.c | 8 ++++---- arch/powerpc/kernel/pci_32.c | 2 +- arch/powerpc/platforms/85xx/p1022_ds.c | 6 +++--- arch/powerpc/platforms/ps3/os-area.c | 6 +++--- arch/powerpc/platforms/pseries/iommu.c | 4 ++-- arch/powerpc/platforms/pseries/mobility.c | 4 ++-- arch/powerpc/platforms/pseries/reconfig.c | 6 +++--- drivers/macintosh/smu.c | 2 +- drivers/of/base.c | 15 +++++++-------- include/linux/of.h | 7 +++---- 12 files changed, 37 insertions(+), 39 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 4748ec551a6..d61b915ce52 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -211,7 +211,7 @@ static void __init update_fec_mac_prop(enum mac_oui oui) macaddr[4] = (val >> 8) & 0xff; macaddr[5] = (val >> 0) & 0xff; - prom_update_property(np, newmac); + of_update_property(np, newmac); } } diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index fa9f6c72f55..e1ec57e87b3 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c @@ -218,23 +218,23 @@ static void __init export_crashk_values(struct device_node *node) * be sure what's in them, so remove them. */ prop = of_find_property(node, "linux,crashkernel-base", NULL); if (prop) - prom_remove_property(node, prop); + of_remove_property(node, prop); prop = of_find_property(node, "linux,crashkernel-size", NULL); if (prop) - prom_remove_property(node, prop); + of_remove_property(node, prop); if (crashk_res.start != 0) { - prom_add_property(node, &crashk_base_prop); + of_add_property(node, &crashk_base_prop); crashk_size = resource_size(&crashk_res); - prom_add_property(node, &crashk_size_prop); + of_add_property(node, &crashk_size_prop); } /* * memory_limit is required by the kexec-tools to limit the * crash regions to the actual memory used. */ - prom_update_property(node, &memory_limit_prop); + of_update_property(node, &memory_limit_prop); } static int __init kexec_setup(void) @@ -249,11 +249,11 @@ static int __init kexec_setup(void) /* remove any stale properties so ours can be found */ prop = of_find_property(node, kernel_end_prop.name, NULL); if (prop) - prom_remove_property(node, prop); + of_remove_property(node, prop); /* information needed by userspace when using default_machine_kexec */ kernel_end = __pa(_end); - prom_add_property(node, &kernel_end_prop); + of_add_property(node, &kernel_end_prop); export_crashk_values(node); diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c index d7f609086a9..7206701b1ff 100644 --- a/arch/powerpc/kernel/machine_kexec_64.c +++ b/arch/powerpc/kernel/machine_kexec_64.c @@ -389,14 +389,14 @@ static int __init export_htab_values(void) /* remove any stale propertys so ours can be found */ prop = of_find_property(node, htab_base_prop.name, NULL); if (prop) - prom_remove_property(node, prop); + of_remove_property(node, prop); prop = of_find_property(node, htab_size_prop.name, NULL); if (prop) - prom_remove_property(node, prop); + of_remove_property(node, prop); htab_base = __pa(htab_address); - prom_add_property(node, &htab_base_prop); - prom_add_property(node, &htab_size_prop); + of_add_property(node, &htab_base_prop); + of_add_property(node, &htab_size_prop); of_node_put(node); return 0; diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c index 4b06ec5a502..64f526a321f 100644 --- a/arch/powerpc/kernel/pci_32.c +++ b/arch/powerpc/kernel/pci_32.c @@ -208,7 +208,7 @@ pci_create_OF_bus_map(void) of_prop->name = "pci-OF-bus-map"; of_prop->length = 256; of_prop->value = &of_prop[1]; - prom_add_property(dn, of_prop); + of_add_property(dn, of_prop); of_node_put(dn); } } diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index 848a3e98e1c..8fb12570b2f 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -539,7 +539,7 @@ static void __init p1022_ds_setup_arch(void) }; /* - * prom_update_property() is called before + * of_update_property() is called before * kmalloc() is available, so the 'new' object * should be allocated in the global area. * The easiest way is to do that is to @@ -548,7 +548,7 @@ static void __init p1022_ds_setup_arch(void) */ pr_info("p1022ds: disabling %s node", np2->full_name); - prom_update_property(np2, &nor_status); + of_update_property(np2, &nor_status); of_node_put(np2); } @@ -564,7 +564,7 @@ static void __init p1022_ds_setup_arch(void) pr_info("p1022ds: disabling %s node", np2->full_name); - prom_update_property(np2, &nand_status); + of_update_property(np2, &nand_status); of_node_put(np2); } diff --git a/arch/powerpc/platforms/ps3/os-area.c b/arch/powerpc/platforms/ps3/os-area.c index 56d26bc4fd4..09787139834 100644 --- a/arch/powerpc/platforms/ps3/os-area.c +++ b/arch/powerpc/platforms/ps3/os-area.c @@ -280,13 +280,13 @@ static void os_area_set_property(struct device_node *node, if (tmp) { pr_debug("%s:%d found %s\n", __func__, __LINE__, prop->name); - prom_remove_property(node, tmp); + of_remove_property(node, tmp); } - result = prom_add_property(node, prop); + result = of_add_property(node, prop); if (result) - pr_debug("%s:%d prom_set_property failed\n", __func__, + pr_debug("%s:%d of_set_property failed\n", __func__, __LINE__); } diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c index da5594c441e..e2685badb5d 100644 --- a/arch/powerpc/platforms/pseries/iommu.c +++ b/arch/powerpc/platforms/pseries/iommu.c @@ -760,7 +760,7 @@ static void remove_ddw(struct device_node *np) __remove_ddw(np, ddw_avail, liobn); delprop: - ret = prom_remove_property(np, win64); + ret = of_remove_property(np, win64); if (ret) pr_warning("%s: failed to remove direct window property: %d\n", np->full_name, ret); @@ -1070,7 +1070,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn) goto out_free_window; } - ret = prom_add_property(pdn, win64); + ret = of_add_property(pdn, win64); if (ret) { dev_err(&dev->dev, "unable to add dma window property for %s: %d", pdn->full_name, ret); diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c index dd30b12edfe..6573808cc5f 100644 --- a/arch/powerpc/platforms/pseries/mobility.c +++ b/arch/powerpc/platforms/pseries/mobility.c @@ -116,7 +116,7 @@ static int update_dt_property(struct device_node *dn, struct property **prop, } if (!more) { - prom_update_property(dn, new_prop); + of_update_property(dn, new_prop); new_prop = NULL; } @@ -172,7 +172,7 @@ static int update_dt_node(u32 phandle) case 0x80000000: prop = of_find_property(dn, prop_name, NULL); - prom_remove_property(dn, prop); + of_remove_property(dn, prop); prop = NULL; break; diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index 720a0cc2e69..30b358dc2be 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -326,7 +326,7 @@ static int do_add_property(char *buf, size_t bufsize) if (!prop) return -ENOMEM; - prom_add_property(np, prop); + of_add_property(np, prop); return 0; } @@ -350,7 +350,7 @@ static int do_remove_property(char *buf, size_t bufsize) prop = of_find_property(np, buf, NULL); - return prom_remove_property(np, prop); + return of_remove_property(np, prop); } static int do_update_property(char *buf, size_t bufsize) @@ -380,7 +380,7 @@ static int do_update_property(char *buf, size_t bufsize) if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size")) slb_set_size(*(int *)value); - return prom_update_property(np, newprop); + return of_update_property(np, newprop); } /** diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c index 7d5a6b40b31..5b939509db3 100644 --- a/drivers/macintosh/smu.c +++ b/drivers/macintosh/smu.c @@ -997,7 +997,7 @@ static struct smu_sdbp_header *smu_create_sdb_partition(int id) "%02x !\n", id, hdr->id); goto failure; } - if (prom_add_property(smu->of_node, prop)) { + if (of_add_property(smu->of_node, prop)) { printk(KERN_DEBUG "SMU: Failed creating sdb-partition-%02x " "property !\n", id); goto failure; diff --git a/drivers/of/base.c b/drivers/of/base.c index 87b63850e8d..02d94c4ea83 100644 --- a/drivers/of/base.c +++ b/drivers/of/base.c @@ -1047,9 +1047,9 @@ static int of_property_notify(int action, struct device_node *np, #endif /** - * prom_add_property - Add a property to a node + * of_add_property - Add a property to a node */ -int prom_add_property(struct device_node *np, struct property *prop) +int of_add_property(struct device_node *np, struct property *prop) { struct property **next; unsigned long flags; @@ -1083,14 +1083,14 @@ int prom_add_property(struct device_node *np, struct property *prop) } /** - * prom_remove_property - Remove a property from a node. + * of_remove_property - Remove a property from a node. * * Note that we don't actually remove it, since we have given out * who-knows-how-many pointers to the data using get-property. * Instead we just move the property to the "dead properties" * list, so it won't be found any more. */ -int prom_remove_property(struct device_node *np, struct property *prop) +int of_remove_property(struct device_node *np, struct property *prop) { struct property **next; unsigned long flags; @@ -1129,7 +1129,7 @@ int prom_remove_property(struct device_node *np, struct property *prop) } /* - * prom_update_property - Update a property in a node, if the property does + * of_update_property - Update a property in a node, if the property does * not exist, add it. * * Note that we don't actually remove it, since we have given out @@ -1137,8 +1137,7 @@ int prom_remove_property(struct device_node *np, struct property *prop) * Instead we just move the property to the "dead properties" list, * and add the new property to the property list */ -int prom_update_property(struct device_node *np, - struct property *newprop) +int of_update_property(struct device_node *np, struct property *newprop) { struct property **next, *oldprop; unsigned long flags; @@ -1153,7 +1152,7 @@ int prom_update_property(struct device_node *np, oldprop = of_find_property(np, newprop->name, NULL); if (!oldprop) - return prom_add_property(np, newprop); + return of_add_property(np, newprop); write_lock_irqsave(&devtree_lock, flags); next = &np->properties; diff --git a/include/linux/of.h b/include/linux/of.h index fb5d87b66e3..a093b2fe5df 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -268,10 +268,9 @@ extern int of_alias_get_id(struct device_node *np, const char *stem); extern int of_machine_is_compatible(const char *compat); -extern int prom_add_property(struct device_node* np, struct property* prop); -extern int prom_remove_property(struct device_node *np, struct property *prop); -extern int prom_update_property(struct device_node *np, - struct property *newprop); +extern int of_add_property(struct device_node *np, struct property *prop); +extern int of_remove_property(struct device_node *np, struct property *prop); +extern int of_update_property(struct device_node *np, struct property *newprop); /* For updating the device tree at runtime */ #define OF_RECONFIG_ATTACH_NODE 0x0001 -- cgit v1.2.3-70-g09d2 From f459d63e1689b16a2f5a965557e19b25bad5dbdc Mon Sep 17 00:00:00 2001 From: Nathan Fontenot Date: Tue, 2 Oct 2012 16:59:39 +0000 Subject: powerpc+of: Remove the pSeries_reconfig.h file Remove the pSeries_reconfig.h header file. At this point there is only one definition in the file, pSeries_coalesce_init(), which can be moved to rtas.h. Signed-off-by: Nathan Fontenot Acked-by: Rob Herring Acked-by: Grant Likely Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/pSeries_reconfig.h | 15 --------------- arch/powerpc/include/asm/rtas.h | 5 +++++ arch/powerpc/kernel/rtas.c | 1 - arch/powerpc/platforms/pseries/smp.c | 1 - 4 files changed, 5 insertions(+), 17 deletions(-) delete mode 100644 arch/powerpc/include/asm/pSeries_reconfig.h (limited to 'arch') diff --git a/arch/powerpc/include/asm/pSeries_reconfig.h b/arch/powerpc/include/asm/pSeries_reconfig.h deleted file mode 100644 index adc00d2e75b..00000000000 --- a/arch/powerpc/include/asm/pSeries_reconfig.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _PPC64_PSERIES_RECONFIG_H -#define _PPC64_PSERIES_RECONFIG_H -#ifdef __KERNEL__ - -#ifdef CONFIG_PPC_PSERIES -/* Not the best place to put this, will be fixed when we move some - * of the rtas suspend-me stuff to pseries */ -extern void pSeries_coalesce_init(void); -#else /* !CONFIG_PPC_PSERIES */ -static inline void pSeries_coalesce_init(void) { } -#endif /* CONFIG_PPC_PSERIES */ - - -#endif /* __KERNEL__ */ -#endif /* _PPC64_PSERIES_RECONFIG_H */ diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h index 557cff845de..aef00c67590 100644 --- a/arch/powerpc/include/asm/rtas.h +++ b/arch/powerpc/include/asm/rtas.h @@ -353,8 +353,13 @@ static inline int page_is_rtas_user_buf(unsigned long pfn) return 1; return 0; } + +/* Not the best place to put pSeries_coalesce_init, will be fixed when we + * move some of the rtas suspend-me stuff to pseries */ +extern void pSeries_coalesce_init(void); #else static inline int page_is_rtas_user_buf(unsigned long pfn) { return 0;} +static inline void pSeries_coalesce_init(void) { } #endif extern int call_rtas(const char *, int, int, unsigned long *, ...); diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index fcec38241f7..1fd6e7b2f39 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -42,7 +42,6 @@ #include #include #include -#include struct rtas_t rtas = { .lock = __ARCH_SPIN_LOCK_UNLOCKED diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c index 71706bc34a0..9fc0a494190 100644 --- a/arch/powerpc/platforms/pseries/smp.c +++ b/arch/powerpc/platforms/pseries/smp.c @@ -38,7 +38,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3-70-g09d2 From be812195d8ac536a62cb1eb5c29b5f2fefefb621 Mon Sep 17 00:00:00 2001 From: Nishanth Aravamudan Date: Wed, 12 Sep 2012 07:47:07 +0000 Subject: powerpc/pseries: Double NR_CPUS in defconfig Anticipating growth in coming years, we should ensure we are getting a good lead on testing. Signed-off-by: Nishanth Aravamudan Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/configs/pseries_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 1f710a32ffa..5b8e1e50827 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -2,7 +2,7 @@ CONFIG_PPC64=y CONFIG_ALTIVEC=y CONFIG_VSX=y CONFIG_SMP=y -CONFIG_NR_CPUS=1024 +CONFIG_NR_CPUS=2048 CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -- cgit v1.2.3-70-g09d2 From 8662d0bcab61032fb453550bed6945b09fbb7d73 Mon Sep 17 00:00:00 2001 From: Matthew McClintock Date: Tue, 18 Sep 2012 09:50:55 +0000 Subject: powerpc: dtc is required to build dtb files Fixes this following: $ make distclean; make corenet32_smp_defconfig; make p4080ds.dtb CLEAN arch/powerpc/boot CLEAN scripts/basic CLEAN scripts/dtc CLEAN scripts/genksyms CLEAN scripts/kconfig CLEAN scripts/mod CLEAN scripts CLEAN include/config include/generated CLEAN .config HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o SHIPPED scripts/kconfig/zconf.tab.c SHIPPED scripts/kconfig/zconf.lex.c SHIPPED scripts/kconfig/zconf.hash.c HOSTCC scripts/kconfig/zconf.tab.o HOSTLD scripts/kconfig/conf scripts/kconfig/conf --silentoldconfig Kconfig DTC arch/powerpc/boot/p4080ds.dtb /bin/sh: /local/home/mattsm/git/linux/scripts/dtc/dtc: No such file or directory make[1]: *** [arch/powerpc/boot/p4080ds.dtb] Error 1 make: *** [p4080ds.dtb] Error 2 Signed-off-by: Matthew McClintock Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 159e94f4b22..b639852116f 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -181,7 +181,7 @@ $(BOOT_TARGETS2): vmlinux bootwrapper_install: $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@) -%.dtb: +%.dtb: scripts $(Q)$(MAKE) ARCH=ppc64 $(build)=$(boot) $(patsubst %,$(boot)/%,$@) define archhelp -- cgit v1.2.3-70-g09d2 From 1afc149def25ac1c44a83882f6c0e42a8e88ce9f Mon Sep 17 00:00:00 2001 From: Tony Breeds Date: Tue, 2 Oct 2012 15:52:19 +0000 Subject: powerpc/47x: Use the new ppc-opcode infrastructure Don't use 47x only #defines for TLBIVAX or ICBT, supply and use helpers in ppc-opcode.h This fixes a compile breakage. Signed-off-by: Tony Breeds Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/ppc-opcode.h | 4 ++++ arch/powerpc/mm/tlb_nohash_low.S | 15 ++++----------- 2 files changed, 8 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 5f73ce63fca..66bec4611ca 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -86,6 +86,7 @@ #define PPC_INST_DCBA_MASK 0xfc0007fe #define PPC_INST_DCBAL 0x7c2005ec #define PPC_INST_DCBZL 0x7c2007ec +#define PPC_INST_ICBT 0x7c00002c #define PPC_INST_ISEL 0x7c00001e #define PPC_INST_ISEL_MASK 0xfc00003e #define PPC_INST_LDARX 0x7c0000a8 @@ -198,6 +199,7 @@ #define __PPC_MB(s) (((s) & 0x1f) << 6) #define __PPC_ME(s) (((s) & 0x1f) << 1) #define __PPC_BI(s) (((s) & 0x1f) << 16) +#define __PPC_CT(t) (((t) & 0x0f) << 21) /* * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a @@ -260,6 +262,8 @@ __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ __PPC_RT(t) | __PPC_RB(b)) +#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \ + __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b)) /* PASemi instructions */ #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index fab919fd138..626ad081639 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -190,12 +190,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) #ifdef CONFIG_PPC_47x -/* - * 47x variant of icbt - */ -# define ICBT(CT,RA,RB) \ - .long 0x7c00002c | ((CT) << 21) | ((RA) << 16) | ((RB) << 11) - /* * _tlbivax_bcast is only on 47x. We don't bother doing a runtime * check though, it will blow up soon enough if we mistakenly try @@ -208,8 +202,7 @@ _GLOBAL(_tlbivax_bcast) wrteei 0 mtspr SPRN_MMUCR,r5 isync -/* tlbivax 0,r3 - use .long to avoid binutils deps */ - .long 0x7c000624 | (r3 << 11) + PPC_TLBIVAX(0, R3) isync eieio tlbsync @@ -227,11 +220,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_476_DD2) bl 2f 2: mflr r6 li r7,32 - ICBT(0,r6,r7) /* touch next cache line */ + PPC_ICBT(0,R6,R7) /* touch next cache line */ add r6,r6,r7 - ICBT(0,r6,r7) /* touch next cache line */ + PPC_ICBT(0,R6,R7) /* touch next cache line */ add r6,r6,r7 - ICBT(0,r6,r7) /* touch next cache line */ + PPC_ICBT(0,R6,R7) /* touch next cache line */ sync nop nop -- cgit v1.2.3-70-g09d2 From 0dc3289c797ef9558af566802429212e0b58a5d9 Mon Sep 17 00:00:00 2001 From: Tony Breeds Date: Tue, 2 Oct 2012 15:52:41 +0000 Subject: powerpc: Add asm/debug.h to get powerpc_debugfs_root Since the "Disintegrate asm/system.h for PowerPC" (ae3a197e3d0bfe3f4bf1693723e82dc018c096f3) This has been failing when DEBUG is #defined. Signed-off-by: Tony Breeds Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/prom.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c index 37725e86651..f5ca76a79c8 100644 --- a/arch/powerpc/kernel/prom.c +++ b/arch/powerpc/kernel/prom.c @@ -54,6 +54,7 @@ #include #include #include +#include #include -- cgit v1.2.3-70-g09d2 From 6432200aa8de3242d64c02e0bf29305147df0171 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:28 +0000 Subject: powerpc/udbg: Remove unused udbg_read() The last user of udbg_read() was removed in 2005, in commit fca5dcd "Simplify and clean up the xmon terminal I/O". Given we haven't needed it for 7 years we can probably drop it. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/udbg.h | 1 - arch/powerpc/kernel/udbg.c | 23 ----------------------- 2 files changed, 24 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h index b3038817b8d..5a7510e9d09 100644 --- a/arch/powerpc/include/asm/udbg.h +++ b/arch/powerpc/include/asm/udbg.h @@ -21,7 +21,6 @@ extern int (*udbg_getc_poll)(void); extern void udbg_puts(const char *s); extern int udbg_write(const char *s, int n); -extern int udbg_read(char *buf, int buflen); extern void register_early_udbg_console(void); extern void udbg_printf(const char *fmt, ...) diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c index c39c1ca77f4..f9748498fe5 100644 --- a/arch/powerpc/kernel/udbg.c +++ b/arch/powerpc/kernel/udbg.c @@ -122,29 +122,6 @@ int udbg_write(const char *s, int n) return n - remain; } -int udbg_read(char *buf, int buflen) -{ - char *p = buf; - int i, c; - - if (!udbg_getc) - return 0; - - for (i = 0; i < buflen; ++i) { - do { - c = udbg_getc(); - if (c == -1 && i == 0) - return -1; - - } while (c == 0x11 || c == 0x13); - if (c == 0 || c == -1) - break; - *p++ = c; - } - - return i; -} - #define UDBG_BUFSIZE 256 void udbg_printf(const char *fmt, ...) { -- cgit v1.2.3-70-g09d2 From eb1c2abb611b51a935cdb36bbc0e364958ccb83c Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:29 +0000 Subject: powerpc/xmon: Remove unused xmon_expect() & xmon_read_poll() It looks like xmon_expect() was used for doing xmon over a modem (!?), that code was dropped in 2005 in commit 51d3082 "Unify udbg (#2)". Once xmon_expect() is gone xmon_read_poll() is unused, drop it too. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/nonstdio.c | 27 --------------------------- arch/powerpc/xmon/nonstdio.h | 2 -- arch/powerpc/xmon/start.c | 7 ------- 3 files changed, 36 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/nonstdio.c b/arch/powerpc/xmon/nonstdio.c index bfac84fbe78..a225d804665 100644 --- a/arch/powerpc/xmon/nonstdio.c +++ b/arch/powerpc/xmon/nonstdio.c @@ -23,33 +23,6 @@ static char line[256]; static char *lineptr; static int lineleft; -int xmon_expect(const char *str, unsigned long timeout) -{ - int c; - unsigned long t0; - - /* assume 25MHz default timebase if tb_ticks_per_sec not set yet */ - timeout *= tb_ticks_per_sec? tb_ticks_per_sec: 25000000; - t0 = get_tbl(); - do { - lineptr = line; - for (;;) { - c = xmon_read_poll(); - if (c == -1) { - if (get_tbl() - t0 > timeout) - return 0; - continue; - } - if (c == '\n') - break; - if (c != '\r' && lineptr < &line[sizeof(line) - 1]) - *lineptr++ = c; - } - *lineptr = 0; - } while (strstr(line, str) == NULL); - return 1; -} - int xmon_getchar(void) { int c; diff --git a/arch/powerpc/xmon/nonstdio.h b/arch/powerpc/xmon/nonstdio.h index 23dd95f4599..d8cec38ec52 100644 --- a/arch/powerpc/xmon/nonstdio.h +++ b/arch/powerpc/xmon/nonstdio.h @@ -9,7 +9,5 @@ extern void xmon_puts(const char *); extern char *xmon_gets(char *, int); extern void xmon_printf(const char *, ...); extern void xmon_map_scc(void); -extern int xmon_expect(const char *str, unsigned long timeout); extern int xmon_write(const void *ptr, int nb); extern int xmon_readchar(void); -extern int xmon_read_poll(void); diff --git a/arch/powerpc/xmon/start.c b/arch/powerpc/xmon/start.c index 8864de2af38..84f3a155eb4 100644 --- a/arch/powerpc/xmon/start.c +++ b/arch/powerpc/xmon/start.c @@ -25,10 +25,3 @@ int xmon_readchar(void) return udbg_getc(); return -1; } - -int xmon_read_poll(void) -{ - if (udbg_getc_poll) - return udbg_getc_poll(); - return -1; -} -- cgit v1.2.3-70-g09d2 From 08702c73a6182d0f6a429271383a553abc92c0b8 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:30 +0000 Subject: powerpc/xmon: Remove empty xmon_map_scc() This has been empty since 2005, commit 51d3082 "Unify udbg (#2)". Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/nonstdio.h | 1 - arch/powerpc/xmon/start.c | 4 ---- arch/powerpc/xmon/xmon.c | 1 - 3 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/nonstdio.h b/arch/powerpc/xmon/nonstdio.h index d8cec38ec52..8799ccf2911 100644 --- a/arch/powerpc/xmon/nonstdio.h +++ b/arch/powerpc/xmon/nonstdio.h @@ -8,6 +8,5 @@ extern int xmon_getchar(void); extern void xmon_puts(const char *); extern char *xmon_gets(char *, int); extern void xmon_printf(const char *, ...); -extern void xmon_map_scc(void); extern int xmon_write(const void *ptr, int nb); extern int xmon_readchar(void); diff --git a/arch/powerpc/xmon/start.c b/arch/powerpc/xmon/start.c index 84f3a155eb4..7769cb5e209 100644 --- a/arch/powerpc/xmon/start.c +++ b/arch/powerpc/xmon/start.c @@ -10,10 +10,6 @@ #include #include "nonstdio.h" -void xmon_map_scc(void) -{ -} - int xmon_write(const void *ptr, int nb) { return udbg_write(ptr, nb); diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 3a56a639a92..67d36ab445e 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -2943,7 +2943,6 @@ static void xmon_init(int enable) __debugger_dabr_match = NULL; __debugger_fault_handler = NULL; } - xmon_map_scc(); } #ifdef CONFIG_MAGIC_SYSRQ -- cgit v1.2.3-70-g09d2 From 88c6d62641514686e0b1b0e33d9faf1e39ec7e58 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:31 +0000 Subject: powerpc/xmon: Make xmon_getchar() static xmon_getchar() is only called from within nonstdio.c, so make it static. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/nonstdio.c | 2 +- arch/powerpc/xmon/nonstdio.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/nonstdio.c b/arch/powerpc/xmon/nonstdio.c index a225d804665..2209485e656 100644 --- a/arch/powerpc/xmon/nonstdio.c +++ b/arch/powerpc/xmon/nonstdio.c @@ -23,7 +23,7 @@ static char line[256]; static char *lineptr; static int lineleft; -int xmon_getchar(void) +static int xmon_getchar(void) { int c; diff --git a/arch/powerpc/xmon/nonstdio.h b/arch/powerpc/xmon/nonstdio.h index 8799ccf2911..321284f4281 100644 --- a/arch/powerpc/xmon/nonstdio.h +++ b/arch/powerpc/xmon/nonstdio.h @@ -4,7 +4,6 @@ #define putchar xmon_putchar extern int xmon_putchar(int c); -extern int xmon_getchar(void); extern void xmon_puts(const char *); extern char *xmon_gets(char *, int); extern void xmon_printf(const char *, ...); -- cgit v1.2.3-70-g09d2 From 33b5cd686649f56d40fa258a0881f6acdbd70134 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:32 +0000 Subject: powerpc/xmon: Merge start.c into nonstdio.c The routines in start.c are only ever called from nonstdio.c, so if we move them in there they can become static which is nice. I suspect the idea behind the separation was that start.c could be replaced in order to build xmon in userland. If anyone still cares about doing that we could handle that with an ifdef or two. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/Makefile | 2 +- arch/powerpc/xmon/nonstdio.c | 14 ++++++++++++++ arch/powerpc/xmon/nonstdio.h | 2 -- arch/powerpc/xmon/start.c | 23 ----------------------- 4 files changed, 15 insertions(+), 26 deletions(-) delete mode 100644 arch/powerpc/xmon/start.c (limited to 'arch') diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile index c168c54e3c4..b49fdbd1580 100644 --- a/arch/powerpc/xmon/Makefile +++ b/arch/powerpc/xmon/Makefile @@ -6,7 +6,7 @@ GCOV_PROFILE := n ccflags-$(CONFIG_PPC64) := -mno-minimal-toc -obj-y += xmon.o start.o nonstdio.o +obj-y += xmon.o nonstdio.o ifdef CONFIG_XMON_DISASSEMBLY obj-y += ppc-dis.o ppc-opc.o diff --git a/arch/powerpc/xmon/nonstdio.c b/arch/powerpc/xmon/nonstdio.c index 2209485e656..942d0f6b187 100644 --- a/arch/powerpc/xmon/nonstdio.c +++ b/arch/powerpc/xmon/nonstdio.c @@ -7,9 +7,23 @@ * 2 of the License, or (at your option) any later version. */ #include +#include #include #include "nonstdio.h" + +static int xmon_write(const void *ptr, int nb) +{ + return udbg_write(ptr, nb); +} + +static int xmon_readchar(void) +{ + if (udbg_getc) + return udbg_getc(); + return -1; +} + int xmon_putchar(int c) { char ch = c; diff --git a/arch/powerpc/xmon/nonstdio.h b/arch/powerpc/xmon/nonstdio.h index 321284f4281..18a51ded4ff 100644 --- a/arch/powerpc/xmon/nonstdio.h +++ b/arch/powerpc/xmon/nonstdio.h @@ -7,5 +7,3 @@ extern int xmon_putchar(int c); extern void xmon_puts(const char *); extern char *xmon_gets(char *, int); extern void xmon_printf(const char *, ...); -extern int xmon_write(const void *ptr, int nb); -extern int xmon_readchar(void); diff --git a/arch/powerpc/xmon/start.c b/arch/powerpc/xmon/start.c deleted file mode 100644 index 7769cb5e209..00000000000 --- a/arch/powerpc/xmon/start.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 1996 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#include -#include -#include "nonstdio.h" - -int xmon_write(const void *ptr, int nb) -{ - return udbg_write(ptr, nb); -} - -int xmon_readchar(void) -{ - if (udbg_getc) - return udbg_getc(); - return -1; -} -- cgit v1.2.3-70-g09d2 From b3dc19cddce37a1aaebc911c8db94e5209a9764d Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:33 +0000 Subject: powerpc/xmon: Remove renaming #defines of scanhex() and skipbl() We have two #defines that rename scanhex() and skipbl() to xmon_scanhex() and xmon_skipbl() - but no one ever uses those names. So the only effect is to rename the actual symbols in the generated code, and AFACIS there is no reason to do that, so drop them. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/xmon.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index 67d36ab445e..cc96a712975 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -52,9 +52,6 @@ #include "nonstdio.h" #include "dis-asm.h" -#define scanhex xmon_scanhex -#define skipbl xmon_skipbl - #ifdef CONFIG_SMP static cpumask_t cpus_in_xmon = CPU_MASK_NONE; static unsigned long xmon_taken = 1; -- cgit v1.2.3-70-g09d2 From c5c5714d5093e677ec962921210eae14156f7179 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:34 +0000 Subject: powerpc/xmon: Remove unused #defines Neither REGS_PER_LINE or LAST_VOLATILE are used, nor have they ever been as far back as I can see. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/xmon.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index cc96a712975..abf6be44635 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -166,12 +166,8 @@ extern void xmon_leave(void); #ifdef CONFIG_PPC64 #define REG "%.16lx" -#define REGS_PER_LINE 4 -#define LAST_VOLATILE 13 #else #define REG "%.8lx" -#define REGS_PER_LINE 8 -#define LAST_VOLATILE 12 #endif #define GETWORD(v) (((v)[0] << 24) + ((v)[1] << 16) + ((v)[2] << 8) + (v)[3]) -- cgit v1.2.3-70-g09d2 From c4de38093ed9fe94fa35c3adb14afc40bf05e1da Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:35 +0000 Subject: powerpc/xmon: Use STACK_FRAME_OVERHEAD in xmon_show_stack() We use STACK_FRAME_OVERHEAD in the exception vectors to establish the exception frame, so it should be good enough to use here. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/xmon.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index abf6be44635..d940234b09e 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -1286,12 +1286,6 @@ static int xmon_depth_to_print = 64; #define LRSAVE_OFFSET (STACK_FRAME_LR_SAVE * sizeof(unsigned long)) #define MARKER_OFFSET (STACK_FRAME_MARKER * sizeof(unsigned long)) -#ifdef __powerpc64__ -#define REGS_OFFSET 0x70 -#else -#define REGS_OFFSET 16 -#endif - static void xmon_show_stack(unsigned long sp, unsigned long lr, unsigned long pc) { @@ -1355,10 +1349,10 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr, an exception frame. */ if (mread(sp + MARKER_OFFSET, &marker, sizeof(unsigned long)) && marker == STACK_FRAME_REGS_MARKER) { - if (mread(sp + REGS_OFFSET, ®s, sizeof(regs)) + if (mread(sp + STACK_FRAME_OVERHEAD, ®s, sizeof(regs)) != sizeof(regs)) { printf("Couldn't read registers at %lx\n", - sp + REGS_OFFSET); + sp + STACK_FRAME_OVERHEAD); break; } printf("--- Exception: %lx %s at ", regs.trap, -- cgit v1.2.3-70-g09d2 From 0104cd6839bd575f0aa1af4125eb865dc0391aae Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:36 +0000 Subject: powerpc/xmon: Fiddle xmon_depth_to_print logic in xmon_show_stack() Currently xmon_depth_to_print is static and global, but it's only ever used in xmon_show_stack(). At least with a modern compiler it's inlined, so there's no point in it being static, we could #define it but it's only used in one place. By reworking the logic we can drop count and just decrement the max value as a loop counter. Also switch to a while loop so we actually print no more than 64 frames as you'd expect based on the variable name. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/xmon.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index d940234b09e..1f8d2f10a43 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -1281,21 +1281,19 @@ static void get_function_bounds(unsigned long pc, unsigned long *startp, catch_memory_errors = 0; } -static int xmon_depth_to_print = 64; - #define LRSAVE_OFFSET (STACK_FRAME_LR_SAVE * sizeof(unsigned long)) #define MARKER_OFFSET (STACK_FRAME_MARKER * sizeof(unsigned long)) static void xmon_show_stack(unsigned long sp, unsigned long lr, unsigned long pc) { + int max_to_print = 64; unsigned long ip; unsigned long newsp; unsigned long marker; - int count = 0; struct pt_regs regs; - do { + while (max_to_print--) { if (sp < PAGE_OFFSET) { if (sp != 0) printf("SP (%lx) is in userspace\n", sp); @@ -1366,7 +1364,7 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr, break; sp = newsp; - } while (count++ < xmon_depth_to_print); + } } static void backtrace(struct pt_regs *excp) -- cgit v1.2.3-70-g09d2 From b2bb65f680a7b2faa5d6332c02752dca83a49cd6 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 9 Oct 2012 04:20:47 +0000 Subject: powerpc/xmon: Fallback to printk() in xmon_printf() if udbg is not setup It is possible to configure a kernel which has xmon enabled, but has no udbg backend to provide IO. This can make xmon rather confusing, as it produces no output, blocks for two seconds, and then returns. As a last resort we can instead try to printk(), which may deadlock or otherwise crash, but tries quite hard not to. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/xmon/nonstdio.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/xmon/nonstdio.c b/arch/powerpc/xmon/nonstdio.c index 942d0f6b187..bce3dcfe505 100644 --- a/arch/powerpc/xmon/nonstdio.c +++ b/arch/powerpc/xmon/nonstdio.c @@ -111,13 +111,19 @@ char *xmon_gets(char *str, int nb) void xmon_printf(const char *format, ...) { va_list args; - int n; static char xmon_outbuf[1024]; + int rc, n; va_start(args, format); n = vsnprintf(xmon_outbuf, sizeof(xmon_outbuf), format, args); va_end(args); - xmon_write(xmon_outbuf, n); + + rc = xmon_write(xmon_outbuf, n); + + if (n && rc == 0) { + /* No udbg hooks, fallback to printk() - dangerous */ + printk(xmon_outbuf); + } } void xmon_puts(const char *str) -- cgit v1.2.3-70-g09d2 From 40c935ae3de413d6bbc5471c231c90e26a63d562 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 10 Oct 2012 08:32:30 +0000 Subject: powerpc/sysdev: Use module_platform_driver macro This patch removes some code duplication by using module_platform_driver. Signed-off-by: Srinivas Kandagatla Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/sysdev/pmi.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/sysdev/pmi.c b/arch/powerpc/sysdev/pmi.c index 8f0465422b1..5aaf86c0389 100644 --- a/arch/powerpc/sysdev/pmi.c +++ b/arch/powerpc/sysdev/pmi.c @@ -214,18 +214,7 @@ static struct platform_driver pmi_of_platform_driver = { .of_match_table = pmi_match, }, }; - -static int __init pmi_module_init(void) -{ - return platform_driver_register(&pmi_of_platform_driver); -} -module_init(pmi_module_init); - -static void __exit pmi_module_exit(void) -{ - platform_driver_unregister(&pmi_of_platform_driver); -} -module_exit(pmi_module_exit); +module_platform_driver(pmi_of_platform_driver); int pmi_send_message(pmi_message_t msg) { -- cgit v1.2.3-70-g09d2 From 490e078d6a21aa90d54f36cdcc544e87070175bd Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Wed, 17 Oct 2012 19:53:30 +0000 Subject: powerpc/pnv: Avoid bogus output There're couples of functions defined to print debugging messages during initializing P7IOC. However, we got bogus output from those functions like pe_info(). The problem here is that the message level (the first parameter to printk()) isn't printable and that caused the bogus output. The patch fixes the issue by merging __pe_printk() to the macro define_pe_printk_level() so that we can pass the message level directly to printk(). Reported-by: Benjamin Herrenschmidt Signed-off-by: Gavin Shan Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/powernv/pci-ioda.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index 471aa3ccd9f..53d052e95cf 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -34,24 +34,12 @@ #include "powernv.h" #include "pci.h" -static int __pe_printk(const char *level, const struct pnv_ioda_pe *pe, - struct va_format *vaf) -{ - char pfix[32]; - - if (pe->pdev) - strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); - else - sprintf(pfix, "%04x:%02x ", - pci_domain_nr(pe->pbus), pe->pbus->number); - return printk("pci %s%s: [PE# %.3d] %pV", level, pfix, pe->pe_number, vaf); -} - #define define_pe_printk_level(func, kern_level) \ static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ { \ struct va_format vaf; \ va_list args; \ + char pfix[32]; \ int r; \ \ va_start(args, fmt); \ @@ -59,7 +47,16 @@ static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...) \ vaf.fmt = fmt; \ vaf.va = &args; \ \ - r = __pe_printk(kern_level, pe, &vaf); \ + if (pe->pdev) \ + strlcpy(pfix, dev_name(&pe->pdev->dev), \ + sizeof(pfix)); \ + else \ + sprintf(pfix, "%04x:%02x ", \ + pci_domain_nr(pe->pbus), \ + pe->pbus->number); \ + r = printk(kern_level "pci %s: [PE# %.3d] %pV", \ + pfix, pe->pe_number, &vaf); \ + \ va_end(args); \ \ return r; \ -- cgit v1.2.3-70-g09d2 From bc26957c6cd913eaec9aac4ce17953efc1582c2e Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Sun, 21 Oct 2012 00:52:05 +0000 Subject: powerpc/rtas_flash: Eliminate possible double free The function initialize_flash_pde_data is only called four times. All four calls are in the function rtas_flash_init, and on the failure of any of the calls, remove_flash_pde is called on the third argument of each of the calls. There is thus no need for initialize_flash_pde_data to call remove_flash_pde on the same argument. remove_flash_pde kfrees the data field of its argument, and does not clear that field, so this amounts ot a possible double free. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @r@ identifier f,free,a; parameter list[n] ps; type T; expression e; @@ f(ps,T a,...) { ... when any when != a = e if(...) { ... free(a); ... return ...; } ... when any } @@ identifier r.f,r.free; expression x,a; expression list[r.n] xs; @@ * x = f(xs,a,...); if (...) { ... free(a); ... return ...; } // Signed-off-by: Julia Lawall Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/rtas_flash.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 20b0120db0c..8329190312c 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -650,10 +650,8 @@ static int initialize_flash_pde_data(const char *rtas_call_name, int token; dp->data = kzalloc(buf_size, GFP_KERNEL); - if (dp->data == NULL) { - remove_flash_pde(dp); + if (dp->data == NULL) return -ENOMEM; - } /* * This code assumes that the status int is the first member of the -- cgit v1.2.3-70-g09d2 From ab7f961a58b3d3390148d18cf95ae4ce6a411b21 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Sun, 21 Oct 2012 14:30:52 +0000 Subject: powerpc/powernv: Fix OPAL debug entry OPAL provides the firmware base/entry in registers at boot time for debugging purposes. We had a bug in the code trying to stash these into the appropriate kernel globals (a line of code was probably dropped by accident back when this was merged) Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/head_64.S | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 58bddee8e1e..694e3fa7885 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -703,6 +703,7 @@ _INIT_STATIC(start_here_multiplatform) #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL /* Setup OPAL entry */ + LOAD_REG_ADDR(r11, opal) std r28,0(r11); std r29,8(r11); #endif -- cgit v1.2.3-70-g09d2 From 12660b170253255c012cb1352449e61ae9727079 Mon Sep 17 00:00:00 2001 From: Li Zhong Date: Mon, 22 Oct 2012 23:46:27 +0000 Subject: powerpc: Fix MAX_STACK_TRACE_ENTRIES too low warning ! This patch tries to fix the following BUG report: [ 0.012313] BUG: MAX_STACK_TRACE_ENTRIES too low! [ 0.012318] turning off the locking correctness validator. [ 0.012321] Call Trace: [ 0.012330] [c00000017666f6d0] [c000000000012128] .show_stack+0x78/0x184 (unreliable) [ 0.012339] [c00000017666f780] [c0000000000b6348] .save_trace+0x12c/0x14c [ 0.012345] [c00000017666f800] [c0000000000b7448] .mark_lock+0x2bc/0x710 [ 0.012351] [c00000017666f8b0] [c0000000000bb198] .__lock_acquire+0x748/0xaec [ 0.012357] [c00000017666f9b0] [c0000000000bb684] .lock_acquire+0x148/0x194 [ 0.012365] [c00000017666fa80] [c00000000069371c] .mutex_lock_nested+0x84/0x4ec [ 0.012372] [c00000017666fb90] [c000000000096998] .smpboot_register_percpu_thread+0x3c/0x10c [ 0.012380] [c00000017666fc30] [c0000000009ba910] .spawn_ksoftirqd+0x28/0x48 [ 0.012386] [c00000017666fcb0] [c00000000000a98c] .do_one_initcall+0xd8/0x1d0 [ 0.012392] [c00000017666fd60] [c00000000000b1f8] .kernel_init+0x120/0x398 [ 0.012398] [c00000017666fe30] [c000000000009ad4] .ret_from_kernel_thread+0x5c/0x64 [ 0.012404] [c00000017666fa00] [c00000017666fb20] 0xc00000017666fb20 [ 0.012410] [c00000017666fa80] [c00000000069371c] .mutex_lock_nested+0x84/0x4ec [ 0.012416] [c00000017666fb90] [c000000000096998] .smpboot_register_percpu_thread+0x3c/0x10c [ 0.012422] [c00000017666fc30] [c0000000009ba910] .spawn_ksoftirqd+0x28/0x48 [ 0.012427] [c00000017666fcb0] [c00000000000a98c] .do_one_initcall+0xd8/0x1d0 [ 0.012433] [c00000017666fd60] [c00000000000b1f8] .kernel_init+0x120/0x398 [ 0.012439] [c00000017666fe30] [c000000000009ad4] .ret_from_kernel_thread+0x5c/0x64 ....... The reason is that the back chain of c00000017666fe30 (ret_from_kernel_thread) contains some invalid value, which might form a loop. Signed-off-by: Li Zhong Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/entry_64.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 56e0ff0878b..ad766669576 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -374,6 +374,8 @@ _GLOBAL(ret_from_kernel_thread) bl .schedule_tail REST_NVGPRS(r1) REST_GPR(2,r1) + li r3,0 + std r3,0(r1) mtlr r14 mr r3,r15 blrl -- cgit v1.2.3-70-g09d2 From 16b86bf2520ed29712ca7462dbfe76c856b445e9 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Wed, 24 Oct 2012 17:21:09 +0000 Subject: powerpc: Remove no longer used ppc_md.idle_loop() The last user of ppc_md.idle_loop() was removed when we dropped the legacy iSeries code, in commit 8ee3e0d. Signed-off-by: Michael Ellerman Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/machdep.h | 3 --- arch/powerpc/kernel/idle.c | 3 --- 2 files changed, 6 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h index c4231973edd..a338bc7cf9d 100644 --- a/arch/powerpc/include/asm/machdep.h +++ b/arch/powerpc/include/asm/machdep.h @@ -166,9 +166,6 @@ struct machdep_calls { unsigned long size, pgprot_t vma_prot); - /* Idle loop for this platform, leave empty for default idle loop */ - void (*idle_loop)(void); - /* * Function for waiting for work with reduced power in idle loop; * called with interrupts disabled. diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c index 2099d9a879e..ea78761aa16 100644 --- a/arch/powerpc/kernel/idle.c +++ b/arch/powerpc/kernel/idle.c @@ -55,9 +55,6 @@ __setup("powersave=off", powersave_off); */ void cpu_idle(void) { - if (ppc_md.idle_loop) - ppc_md.idle_loop(); /* doesn't return */ - set_thread_flag(TIF_POLLING_NRFLAG); while (1) { tick_nohz_idle_enter(); -- cgit v1.2.3-70-g09d2 From 6c7a2856ade6a58c20038024247d16a12a8d2323 Mon Sep 17 00:00:00 2001 From: "K.Prasad" Date: Sun, 28 Oct 2012 15:13:15 +0000 Subject: powerpc/hw-breakpoint: Use generic hw-breakpoint interfaces for new PPC ptrace flags PPC_PTRACE_GETHWDBGINFO, PPC_PTRACE_SETHWDEBUG and PPC_PTRACE_DELHWDEBUG are PowerPC specific ptrace flags that use the watchpoint register. While they are targeted primarily towards BookE users, user-space applications such as GDB have started using them for BookS too. This patch enables the use of generic hardware breakpoint interfaces for these new flags. Apart from the usual benefits of using generic hw-breakpoint interfaces, these changes allow debuggers (such as GDB) to use a common set of ptrace flags for their watchpoint needs and allow more precise breakpoint specification (length of the variable can be specified). Mikey added: rebased and added dbginfo.features around #ifdef CONFIG_HAVE_HW_BREAKPOINT Signed-off-by: K.Prasad Acked-by: David Gibson Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- Documentation/powerpc/ptrace.txt | 16 +++++++++ arch/powerpc/kernel/ptrace.c | 78 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 90 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/Documentation/powerpc/ptrace.txt b/Documentation/powerpc/ptrace.txt index f4a5499b7bc..f2a7a391977 100644 --- a/Documentation/powerpc/ptrace.txt +++ b/Documentation/powerpc/ptrace.txt @@ -127,6 +127,22 @@ Some examples of using the structure to: p.addr2 = (uint64_t) end_range; p.condition_value = 0; +- set a watchpoint in server processors (BookS) + + p.version = 1; + p.trigger_type = PPC_BREAKPOINT_TRIGGER_RW; + p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; + or + p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; + + p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; + p.addr = (uint64_t) begin_range; + /* For PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE addr2 needs to be specified, where + * addr2 - addr <= 8 Bytes. + */ + p.addr2 = (uint64_t) end_range; + p.condition_value = 0; + 3. PTRACE_DELHWDEBUG Takes an integer which identifies an existing breakpoint or watchpoint diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 79d8e56470d..140238aad71 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1338,6 +1338,12 @@ static int set_dac_range(struct task_struct *child, static long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) { +#ifdef CONFIG_HAVE_HW_BREAKPOINT + int len = 0; + struct thread_struct *thread = &(child->thread); + struct perf_event *bp; + struct perf_event_attr attr; +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #ifndef CONFIG_PPC_ADV_DEBUG_REGS unsigned long dabr; #endif @@ -1381,13 +1387,9 @@ static long ppc_set_hwdebug(struct task_struct *child, */ if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || - bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT || bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) return -EINVAL; - if (child->thread.dabr) - return -ENOSPC; - if ((unsigned long)bp_info->addr >= TASK_SIZE) return -EIO; @@ -1397,6 +1399,50 @@ static long ppc_set_hwdebug(struct task_struct *child, dabr |= DABR_DATA_READ; if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) dabr |= DABR_DATA_WRITE; +#ifdef CONFIG_HAVE_HW_BREAKPOINT + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + + /* + * Check if the request is for 'range' breakpoints. We can + * support it if range < 8 bytes. + */ + if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) { + len = bp_info->addr2 - bp_info->addr; + } else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { + ptrace_put_breakpoints(child); + return -EINVAL; + } + bp = thread->ptrace_bps[0]; + if (bp) { + ptrace_put_breakpoints(child); + return -ENOSPC; + } + + /* Create a new breakpoint request if one doesn't exist already */ + hw_breakpoint_init(&attr); + attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; + attr.bp_len = len; + arch_bp_generic_fields(dabr & (DABR_DATA_WRITE | DABR_DATA_READ), + &attr.bp_type); + + thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, + ptrace_triggered, NULL, child); + if (IS_ERR(bp)) { + thread->ptrace_bps[0] = NULL; + ptrace_put_breakpoints(child); + return PTR_ERR(bp); + } + + ptrace_put_breakpoints(child); + return 1; +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ + + if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) + return -EINVAL; + + if (child->thread.dabr) + return -ENOSPC; child->thread.dabr = dabr; child->thread.dabrx = DABRX_ALL; @@ -1407,6 +1453,11 @@ static long ppc_set_hwdebug(struct task_struct *child, static long ppc_del_hwdebug(struct task_struct *child, long addr, long data) { +#ifdef CONFIG_HAVE_HW_BREAKPOINT + int ret = 0; + struct thread_struct *thread = &(child->thread); + struct perf_event *bp; +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #ifdef CONFIG_PPC_ADV_DEBUG_REGS int rc; @@ -1426,10 +1477,25 @@ static long ppc_del_hwdebug(struct task_struct *child, long addr, long data) #else if (data != 1) return -EINVAL; + +#ifdef CONFIG_HAVE_HW_BREAKPOINT + if (ptrace_get_breakpoints(child) < 0) + return -ESRCH; + + bp = thread->ptrace_bps[0]; + if (bp) { + unregister_hw_breakpoint(bp); + thread->ptrace_bps[0] = NULL; + } else + ret = -ENOENT; + ptrace_put_breakpoints(child); + return ret; +#else /* CONFIG_HAVE_HW_BREAKPOINT */ if (child->thread.dabr == 0) return -ENOENT; child->thread.dabr = 0; +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ return 0; #endif @@ -1536,7 +1602,11 @@ long arch_ptrace(struct task_struct *child, long request, dbginfo.data_bp_alignment = 4; #endif dbginfo.sizeof_condition = 0; +#ifdef CONFIG_HAVE_HW_BREAKPOINT + dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; +#else dbginfo.features = 0; +#endif /* CONFIG_HAVE_HW_BREAKPOINT */ #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ if (!access_ok(VERIFY_WRITE, datavp, -- cgit v1.2.3-70-g09d2 From 84295dfc5989aaeb6e7d4a9df235451194a54bba Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Sun, 28 Oct 2012 15:13:16 +0000 Subject: powerpc/ptrace: Fix spelling mistake s/intruction/instruction/ Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/ptrace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 140238aad71..7dd32d17c46 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1037,7 +1037,7 @@ void ptrace_disable(struct task_struct *child) } #ifdef CONFIG_PPC_ADV_DEBUG_REGS -static long set_intruction_bp(struct task_struct *child, +static long set_instruction_bp(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) { int slot; @@ -1371,7 +1371,7 @@ static long ppc_set_hwdebug(struct task_struct *child, if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) return -EINVAL; - return set_intruction_bp(child, bp_info); + return set_instruction_bp(child, bp_info); } if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) return set_dac(child, bp_info); -- cgit v1.2.3-70-g09d2 From ec1b33dcd2c0ed773e6458d1c8b337966114562b Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Sun, 28 Oct 2012 15:13:17 +0000 Subject: powerpc/ptrace: Remove unused addr parameter in ppc_del_hwdebug() Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/ptrace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 7dd32d17c46..817b4116e5b 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -1451,7 +1451,7 @@ static long ppc_set_hwdebug(struct task_struct *child, #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ } -static long ppc_del_hwdebug(struct task_struct *child, long addr, long data) +static long ppc_del_hwdebug(struct task_struct *child, long data) { #ifdef CONFIG_HAVE_HW_BREAKPOINT int ret = 0; @@ -1633,7 +1633,7 @@ long arch_ptrace(struct task_struct *child, long request, } case PPC_PTRACE_DELHWDEBUG: { - ret = ppc_del_hwdebug(child, addr, data); + ret = ppc_del_hwdebug(child, data); break; } -- cgit v1.2.3-70-g09d2 From bb29b719372742939af05457aff1b59608764e89 Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Sun, 28 Oct 2012 23:15:14 +0000 Subject: powerpc/powermac/cpufreq_32: Set non-infinite transition time for 7447A driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The transition time for the 7447A is around 8ms which makes it possible to use the ondemand governor. This has been tested on the iBook G4 (PowerBook6,7). Signed-off-by: Andreas Schwab Tested-by: Michel Dänzer Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/powermac/cpufreq_32.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c index 64171198535..311b804353b 100644 --- a/arch/powerpc/platforms/powermac/cpufreq_32.c +++ b/arch/powerpc/platforms/powermac/cpufreq_32.c @@ -55,6 +55,7 @@ static unsigned int low_freq; static unsigned int hi_freq; static unsigned int cur_freq; static unsigned int sleep_freq; +static unsigned long transition_latency; /* * Different models uses different mechanisms to switch the frequency @@ -403,7 +404,7 @@ static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy) if (policy->cpu != 0) return -ENODEV; - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + policy->cpuinfo.transition_latency = transition_latency; policy->cur = cur_freq; cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu); @@ -658,12 +659,14 @@ static int __init pmac_cpufreq_setup(void) if (!value) goto out; cur_freq = (*value) / 1000; + transition_latency = CPUFREQ_ETERNAL; /* Check for 7447A based MacRISC3 */ if (of_machine_is_compatible("MacRISC3") && of_get_property(cpunode, "dynamic-power-step", NULL) && PVR_VER(mfspr(SPRN_PVR)) == 0x8003) { pmac_cpufreq_init_7447A(cpunode); + transition_latency = 8000000; /* Check for other MacRISC3 machines */ } else if (of_machine_is_compatible("PowerBook3,4") || of_machine_is_compatible("PowerBook3,5") || -- cgit v1.2.3-70-g09d2 From da111957796515755d95ec6773dc714350724a4e Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Tue, 30 Oct 2012 16:09:56 +0000 Subject: powerpc/perf: Add missing L2 constraint handling in Power7 PMU If we have two cache events that require different settings of the L2SEL bits in MMCR1 then we can not schedule those events simultaneously. Add logic to the constraint handling to express that. Signed-off-by: Michael Ellerman Acked-by: Paul Mackerras Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/perf/power7-pmu.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c index 441af08edf4..2ee01e38d5e 100644 --- a/arch/powerpc/perf/power7-pmu.c +++ b/arch/powerpc/perf/power7-pmu.c @@ -54,8 +54,10 @@ * Layout of constraint bits: * 6666555555555544444444443333333333222222222211111111110000000000 * 3210987654321098765432109876543210987654321098765432109876543210 - * [ ><><><><><><> - * NC P6P5P4P3P2P1 + * < >< ><><><><><><> + * L2 NC P6P5P4P3P2P1 + * + * L2 - 16-18 - Required L2SEL value (select field) * * NC - number of counters * 15: NC error 0x8000 @@ -72,7 +74,7 @@ static int power7_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) { - int pmc, sh; + int pmc, sh, unit; unsigned long mask = 0, value = 0; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; @@ -90,6 +92,15 @@ static int power7_get_constraint(u64 event, unsigned long *maskp, mask |= 0x8000; value |= 0x1000; } + + unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; + if (unit == 6) { + /* L2SEL must be identical across events */ + int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK; + mask |= 0x7 << 16; + value |= l2sel << 16; + } + *maskp = mask; *valp = value; return 0; -- cgit v1.2.3-70-g09d2 From cd5daaf713cf8d728a2be2a3673293fff9465d9a Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 30 Oct 2012 19:34:13 +0000 Subject: powerpc: make POWER7 setup code name generic We are going to reuse this in POWER8 so make the name generic. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/Makefile | 2 +- arch/powerpc/kernel/cpu_setup_power.S | 95 ++++++++++++++++++++++++++++++++++ arch/powerpc/kernel/cpu_setup_power7.S | 95 ---------------------------------- 3 files changed, 96 insertions(+), 96 deletions(-) create mode 100644 arch/powerpc/kernel/cpu_setup_power.S delete mode 100644 arch/powerpc/kernel/cpu_setup_power7.S (limited to 'arch') diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index cde12f8a4eb..8f619342f14 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -38,7 +38,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \ paca.o nvram_64.o firmware.o obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o -obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power7.o +obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_power.o obj64-$(CONFIG_RELOCATABLE) += reloc_64.o obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o obj-$(CONFIG_PPC_A2) += cpu_setup_a2.o diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S new file mode 100644 index 00000000000..76797c5105d --- /dev/null +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -0,0 +1,95 @@ +/* + * This file contains low level CPU setup functions. + * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include + +/* Entry: r3 = crap, r4 = ptr to cputable entry + * + * Note that we can be called twice for pseudo-PVRs + */ +_GLOBAL(__setup_cpu_power7) + mflr r11 + bl __init_hvmode_206 + mtlr r11 + beqlr + li r0,0 + mtspr SPRN_LPID,r0 + bl __init_LPCR + bl __init_TLB + mtlr r11 + blr + +_GLOBAL(__restore_cpu_power7) + mflr r11 + mfmsr r3 + rldicl. r0,r3,4,63 + beqlr + li r0,0 + mtspr SPRN_LPID,r0 + bl __init_LPCR + bl __init_TLB + mtlr r11 + blr + +__init_hvmode_206: + /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */ + mfmsr r3 + rldicl. r0,r3,4,63 + bnelr + ld r5,CPU_SPEC_FEATURES(r4) + LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) + xor r5,r5,r6 + std r5,CPU_SPEC_FEATURES(r4) + blr + +__init_LPCR: + /* Setup a sane LPCR: + * + * LPES = 0b01 (HSRR0/1 used for 0x500) + * PECE = 0b111 + * DPFD = 4 + * HDICE = 0 + * VC = 0b100 (VPM0=1, VPM1=0, ISL=0) + * VRMASD = 0b10000 (L=1, LP=00) + * + * Other bits untouched for now + */ + mfspr r3,SPRN_LPCR + li r5,1 + rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2 + ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) + li r5,4 + rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3 + clrrdi r3,r3,1 /* clear HDICE */ + li r5,4 + rldimi r3,r5, LPCR_VC_SH, 0 + li r5,0x10 + rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5 + mtspr SPRN_LPCR,r3 + isync + blr + +__init_TLB: + /* Clear the TLB */ + li r6,128 + mtctr r6 + li r7,0xc00 /* IS field = 0b11 */ + ptesync +2: tlbiel r7 + addi r7,r7,0x1000 + bdnz 2b + ptesync +1: blr diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S deleted file mode 100644 index 76797c5105d..00000000000 --- a/arch/powerpc/kernel/cpu_setup_power7.S +++ /dev/null @@ -1,95 +0,0 @@ -/* - * This file contains low level CPU setup functions. - * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -/* Entry: r3 = crap, r4 = ptr to cputable entry - * - * Note that we can be called twice for pseudo-PVRs - */ -_GLOBAL(__setup_cpu_power7) - mflr r11 - bl __init_hvmode_206 - mtlr r11 - beqlr - li r0,0 - mtspr SPRN_LPID,r0 - bl __init_LPCR - bl __init_TLB - mtlr r11 - blr - -_GLOBAL(__restore_cpu_power7) - mflr r11 - mfmsr r3 - rldicl. r0,r3,4,63 - beqlr - li r0,0 - mtspr SPRN_LPID,r0 - bl __init_LPCR - bl __init_TLB - mtlr r11 - blr - -__init_hvmode_206: - /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */ - mfmsr r3 - rldicl. r0,r3,4,63 - bnelr - ld r5,CPU_SPEC_FEATURES(r4) - LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE) - xor r5,r5,r6 - std r5,CPU_SPEC_FEATURES(r4) - blr - -__init_LPCR: - /* Setup a sane LPCR: - * - * LPES = 0b01 (HSRR0/1 used for 0x500) - * PECE = 0b111 - * DPFD = 4 - * HDICE = 0 - * VC = 0b100 (VPM0=1, VPM1=0, ISL=0) - * VRMASD = 0b10000 (L=1, LP=00) - * - * Other bits untouched for now - */ - mfspr r3,SPRN_LPCR - li r5,1 - rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2 - ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) - li r5,4 - rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3 - clrrdi r3,r3,1 /* clear HDICE */ - li r5,4 - rldimi r3,r5, LPCR_VC_SH, 0 - li r5,0x10 - rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5 - mtspr SPRN_LPCR,r3 - isync - blr - -__init_TLB: - /* Clear the TLB */ - li r6,128 - mtctr r6 - li r7,0xc00 /* IS field = 0b11 */ - ptesync -2: tlbiel r7 - addi r7,r7,0x1000 - bdnz 2b - ptesync -1: blr -- cgit v1.2.3-70-g09d2 From aec937b1ee6d7b28499d50ea6df1b2fe9edee91b Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 30 Oct 2012 19:34:14 +0000 Subject: powerpc: Add POWER8 setup code Just a copy of POWER7 for now. Will update with new code later. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/cpu_setup_power.S | 24 ++++++++++++++++++++++++ arch/powerpc/kernel/cputable.c | 2 ++ 2 files changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 76797c5105d..a92101d14b4 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -44,6 +44,30 @@ _GLOBAL(__restore_cpu_power7) mtlr r11 blr +_GLOBAL(__setup_cpu_power8) + mflr r11 + bl __init_hvmode_206 + mtlr r11 + beqlr + li r0,0 + mtspr SPRN_LPID,r0 + bl __init_LPCR + bl __init_TLB + mtlr r11 + blr + +_GLOBAL(__restore_cpu_power8) + mflr r11 + mfmsr r3 + rldicl. r0,r3,4,63 + beqlr + li r0,0 + mtspr SPRN_LPID,r0 + bl __init_LPCR + bl __init_TLB + mtlr r11 + blr + __init_hvmode_206: /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */ mfmsr r3 diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 0514c21f138..361f6d91ab1 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -68,6 +68,8 @@ extern void __restore_cpu_pa6t(void); extern void __restore_cpu_ppc970(void); extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec); extern void __restore_cpu_power7(void); +extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec); +extern void __restore_cpu_power8(void); extern void __restore_cpu_a2(void); #endif /* CONFIG_PPC64 */ #if defined(CONFIG_E500) -- cgit v1.2.3-70-g09d2 From 71e184972456a8095657e80fd1470a3857b441a0 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Tue, 30 Oct 2012 19:34:15 +0000 Subject: powerpc: POWER8 cputable entry Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/cputable.h | 12 ++++++++++-- arch/powerpc/include/asm/mmu.h | 1 + arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/cputable.c | 21 +++++++++++++++++++++ 4 files changed, 33 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 21a0687b8c4..76f81bd64f1 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -401,6 +401,14 @@ extern const char *powerpc_base_platform; CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY) +#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ + CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ + CPU_FTR_MMCRA | CPU_FTR_SMT | \ + CPU_FTR_COHERENT_ICACHE | \ + CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ + CPU_FTR_DSCR | CPU_FTR_SAO | \ + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ + CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY) #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ @@ -421,8 +429,8 @@ extern const char *powerpc_base_platform; #define CPU_FTRS_POSSIBLE \ (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ - CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ - CPU_FTR_VSX) + CPU_FTRS_POWER7 | CPU_FTRS_POWER8 | CPU_FTRS_CELL | \ + CPU_FTRS_PA6T | CPU_FTR_VSX) #endif #else enum { diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 5e38eedea21..691fd8aca93 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -101,6 +101,7 @@ #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE +#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ MMU_FTR_CI_LARGE_PAGE #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index d24c1416396..7b44a6e3e0f 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1029,6 +1029,7 @@ #define PVR_970MP 0x0044 #define PVR_970GX 0x0045 #define PVR_POWER7p 0x004A +#define PVR_POWER8 0x004B #define PVR_BE 0x0070 #define PVR_PA6T 0x0090 diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 361f6d91ab1..216ff845caf 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -96,6 +96,10 @@ extern void __restore_cpu_e5500(void); PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ PPC_FEATURE_TRUE_LE | \ PPC_FEATURE_PSERIES_PERFMON_COMPAT) +#define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\ + PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \ + PPC_FEATURE_TRUE_LE | \ + PPC_FEATURE_PSERIES_PERFMON_COMPAT) #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\ PPC_FEATURE_TRUE_LE | \ PPC_FEATURE_HAS_ALTIVEC_COMP) @@ -465,6 +469,23 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_power7, .platform = "power7+", }, + { /* Power8 */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x004b0000, + .cpu_name = "POWER8 (raw)", + .cpu_features = CPU_FTRS_POWER8, + .cpu_user_features = COMMON_USER_POWER8, + .mmu_features = MMU_FTRS_POWER8, + .icache_bsize = 128, + .dcache_bsize = 128, + .num_pmcs = 6, + .pmc_type = PPC_PMC_IBM, + .oprofile_cpu_type = "ppc64/power8", + .oprofile_type = PPC_OPROFILE_POWER4, + .cpu_setup = __setup_cpu_power8, + .cpu_restore = __restore_cpu_power8, + .platform = "power8", + }, { /* Cell Broadband Engine */ .pvr_mask = 0xffff0000, .pvr_value = 0x00700000, -- cgit v1.2.3-70-g09d2 From 51cf2b30a552fe890a1af83cc0bcf49f92d82e58 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Wed, 31 Oct 2012 18:58:36 +0000 Subject: powerpc: Fix denorm symbol name Fix global symbol name to match actual denorm_exception_hv label. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/exceptions-64s.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 10b658ad65e..56630189f2e 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -276,7 +276,7 @@ vsx_unavailable_pSeries_1: KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300) . = 0x1500 - .global denorm_Hypervisor + .global denorm_exception_hv denorm_exception_hv: HMT_MEDIUM mtspr SPRN_SPRG_HSCRATCH0,r13 -- cgit v1.2.3-70-g09d2 From 560285cd2c6f535b18b701900d3c028bb31f4dba Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 1 Nov 2012 14:55:04 +0000 Subject: powerpc: Move most of setup.h out of uapi Most of setup.h should not be exported to userspace, so move it back. All we are left with is the asm-generic include to pick up the COMMAND_LINE_SIZE define. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/setup.h | 33 +++++++++++++++++++++++++++++++++ arch/powerpc/include/uapi/asm/setup.h | 31 ------------------------------- 2 files changed, 33 insertions(+), 31 deletions(-) create mode 100644 arch/powerpc/include/asm/setup.h (limited to 'arch') diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h new file mode 100644 index 00000000000..8568c69364c --- /dev/null +++ b/arch/powerpc/include/asm/setup.h @@ -0,0 +1,33 @@ +#ifndef _ASM_POWERPC_SETUP_H +#define _ASM_POWERPC_SETUP_H + +#include + +#ifndef __ASSEMBLY__ +extern void ppc_printk_progress(char *s, unsigned short hex); + +extern unsigned int rtas_data; +extern int mem_init_done; /* set on boot once kmalloc can be called */ +extern int init_bootmem_done; /* set once bootmem is available */ +extern unsigned long long memory_limit; +extern unsigned long klimit; +extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); + +extern void via_cuda_init(void); +extern void read_rtc_time(void); +extern void pmac_find_display(void); + +struct device_node; +extern void note_scsi_host(struct device_node *, void *); + +/* Used in very early kernel initialization. */ +extern unsigned long reloc_offset(void); +extern unsigned long add_reloc_offset(unsigned long); +extern void reloc_got2(unsigned long); + +#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_POWERPC_SETUP_H */ + diff --git a/arch/powerpc/include/uapi/asm/setup.h b/arch/powerpc/include/uapi/asm/setup.h index 8b9a306260b..552df83f1a4 100644 --- a/arch/powerpc/include/uapi/asm/setup.h +++ b/arch/powerpc/include/uapi/asm/setup.h @@ -1,32 +1 @@ -#ifndef _ASM_POWERPC_SETUP_H -#define _ASM_POWERPC_SETUP_H - #include - -#ifndef __ASSEMBLY__ -extern void ppc_printk_progress(char *s, unsigned short hex); - -extern unsigned int rtas_data; -extern int mem_init_done; /* set on boot once kmalloc can be called */ -extern int init_bootmem_done; /* set once bootmem is available */ -extern unsigned long long memory_limit; -extern unsigned long klimit; -extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); - -extern void via_cuda_init(void); -extern void read_rtc_time(void); -extern void pmac_find_display(void); - -struct device_node; -extern void note_scsi_host(struct device_node *, void *); - -/* Used in very early kernel initialization. */ -extern unsigned long reloc_offset(void); -extern unsigned long add_reloc_offset(unsigned long); -extern void reloc_got2(unsigned long); - -#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_POWERPC_SETUP_H */ -- cgit v1.2.3-70-g09d2 From 5e0f9ea784036a3e62a25a9ab5e8f323cb25b321 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Thu, 1 Nov 2012 14:55:55 +0000 Subject: powerpc: Remove stale function prototypes from setup.h I noticed a couple of function prototypes for functions that no longer exist. Remove them. Signed-off-by: Anton Blanchard Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/setup.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h index 8568c69364c..d3ca85529b8 100644 --- a/arch/powerpc/include/asm/setup.h +++ b/arch/powerpc/include/asm/setup.h @@ -13,10 +13,6 @@ extern unsigned long long memory_limit; extern unsigned long klimit; extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); -extern void via_cuda_init(void); -extern void read_rtc_time(void); -extern void pmac_find_display(void); - struct device_node; extern void note_scsi_host(struct device_node *, void *); -- cgit v1.2.3-70-g09d2 From 8a56e1ee9229ef1c5c558b53f696af9152024a15 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Thu, 1 Nov 2012 18:53:42 +0000 Subject: powerpc: Fix typos in Freescale copyright claims There are many cases that Semiconductor is misspelled. The patch fix these typos. Signed-off-by: Li Yang Acked-by: Timur Tabi Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/dbell.h | 2 +- arch/powerpc/include/asm/fsl_gtm.h | 2 +- arch/powerpc/include/asm/immap_qe.h | 2 +- arch/powerpc/include/asm/ppc-opcode.h | 2 +- arch/powerpc/include/asm/qe.h | 2 +- arch/powerpc/include/asm/qe_ic.h | 2 +- arch/powerpc/include/asm/ucc.h | 2 +- arch/powerpc/include/asm/ucc_fast.h | 2 +- arch/powerpc/include/asm/ucc_slow.h | 2 +- arch/powerpc/platforms/52xx/lite5200.c | 2 +- arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +- arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +- arch/powerpc/platforms/83xx/mpc836x_rdk.c | 2 +- arch/powerpc/platforms/83xx/mpc837x_rdb.c | 2 +- arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +- arch/powerpc/sysdev/fsl_gtm.c | 2 +- arch/powerpc/sysdev/qe_lib/qe.c | 2 +- arch/powerpc/sysdev/qe_lib/qe_ic.c | 2 +- arch/powerpc/sysdev/qe_lib/qe_ic.h | 2 +- arch/powerpc/sysdev/qe_lib/qe_io.c | 2 +- arch/powerpc/sysdev/qe_lib/ucc.c | 2 +- arch/powerpc/sysdev/qe_lib/ucc_fast.c | 2 +- arch/powerpc/sysdev/qe_lib/ucc_slow.c | 2 +- arch/powerpc/sysdev/qe_lib/usb.c | 2 +- 24 files changed, 24 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/dbell.h b/arch/powerpc/include/asm/dbell.h index 154c067761b..607e4eeeb69 100644 --- a/arch/powerpc/include/asm/dbell.h +++ b/arch/powerpc/include/asm/dbell.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semicondutor, Inc. + * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/arch/powerpc/include/asm/fsl_gtm.h b/arch/powerpc/include/asm/fsl_gtm.h index 8e8c9b5032d..3b05808f9ca 100644 --- a/arch/powerpc/include/asm/fsl_gtm.h +++ b/arch/powerpc/include/asm/fsl_gtm.h @@ -1,7 +1,7 @@ /* * Freescale General-purpose Timers Module * - * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Copyright 2006 Freescale Semiconductor, Inc. * Shlomi Gridish * Jerry Huang * Copyright (c) MontaVista Software, Inc. 2008. diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h index 61e8490786b..bedbff89142 100644 --- a/arch/powerpc/include/asm/immap_qe.h +++ b/arch/powerpc/include/asm/immap_qe.h @@ -3,7 +3,7 @@ * The Internal Memory Map for devices with QE on them. This * is the superset of all QE devices (8360, etc.). - * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index 66bec4611ca..e434d8b68dd 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -1,5 +1,5 @@ /* - * Copyright 2009 Freescale Semicondutor, Inc. + * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 229571a4939..32b9bfa0c9b 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h index f706164b0bd..25784cc959a 100644 --- a/arch/powerpc/include/asm/qe_ic.h +++ b/arch/powerpc/include/asm/qe_ic.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/include/asm/ucc.h b/arch/powerpc/include/asm/ucc.h index 46b09ba6bea..6927ac26516 100644 --- a/arch/powerpc/include/asm/ucc.h +++ b/arch/powerpc/include/asm/ucc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/include/asm/ucc_fast.h b/arch/powerpc/include/asm/ucc_fast.h index 4644c840e2f..72ea9bab07d 100644 --- a/arch/powerpc/include/asm/ucc_fast.h +++ b/arch/powerpc/include/asm/ucc_fast.h @@ -1,7 +1,7 @@ /* * Internal header file for UCC FAST unit routines. * - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/include/asm/ucc_slow.h b/arch/powerpc/include/asm/ucc_slow.h index cf131ffdb8d..c44131e68e1 100644 --- a/arch/powerpc/include/asm/ucc_slow.h +++ b/arch/powerpc/include/asm/ucc_slow.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c index 448d862bcf3..1843bc93201 100644 --- a/arch/powerpc/platforms/52xx/lite5200.c +++ b/arch/powerpc/platforms/52xx/lite5200.c @@ -4,7 +4,7 @@ * Written by: Grant Likely * * Copyright (C) Secret Lab Technologies Ltd. 2006. All rights reserved. - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. * * Description: * This program is free software; you can redistribute it and/or modify it diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c index d440435e055..8d762203eef 100644 --- a/arch/powerpc/platforms/83xx/mpc832x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. * * Description: * MPC832xE MDS board specific routines. diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c index 1b1f6c8a1a1..1a26d2f8340 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_mds.c +++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Yin Olivia diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c index f8769d713d6..b63b42d11d6 100644 --- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c +++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c @@ -1,7 +1,7 @@ /* * MPC8360E-RDK board file. * - * Copyright (c) 2006 Freescale Semicondutor, Inc. + * Copyright (c) 2006 Freescale Semiconductor, Inc. * Copyright (c) 2007-2008 MontaVista Software, Inc. * * Author: Anton Vorontsov diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c index eca1f0960ff..9813c81e8e5 100644 --- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c +++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c @@ -1,7 +1,7 @@ /* * arch/powerpc/platforms/83xx/mpc837x_rdb.c * - * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * * MPC837x RDB board specific routines * diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 8498f732347..bd12588fa25 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc. + * Copyright (C) 2006-2010, 2012 Freescale Semiconductor, Inc. * All rights reserved. * * Author: Andy Fleming diff --git a/arch/powerpc/sysdev/fsl_gtm.c b/arch/powerpc/sysdev/fsl_gtm.c index 02cf1e7e77f..0eb871cc343 100644 --- a/arch/powerpc/sysdev/fsl_gtm.c +++ b/arch/powerpc/sysdev/fsl_gtm.c @@ -1,7 +1,7 @@ /* * Freescale General-purpose Timers Module * - * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Copyright (c) Freescale Semiconductor, Inc. 2006. * Shlomi Gridish * Jerry Huang * Copyright (c) MontaVista Software, Inc. 2008. diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c index b0436752972..238a07b97f2 100644 --- a/arch/powerpc/sysdev/qe_lib/qe.c +++ b/arch/powerpc/sysdev/qe_lib/qe.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006-2010 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c index 2fba6ef2f95..b2b87c30e26 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.c +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c @@ -1,7 +1,7 @@ /* * arch/powerpc/sysdev/qe_lib/qe_ic.c * - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Based on code from Shlomi Gridish diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.h b/arch/powerpc/sysdev/qe_lib/qe_ic.h index c327872ed35..efef7ab9b75 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_ic.h +++ b/arch/powerpc/sysdev/qe_lib/qe_ic.h @@ -3,7 +3,7 @@ * * QUICC ENGINE Interrupt Controller Header * - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Based on code from Shlomi Gridish diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c index fd1a6c3b172..a88807b3dd5 100644 --- a/arch/powerpc/sysdev/qe_lib/qe_io.c +++ b/arch/powerpc/sysdev/qe_lib/qe_io.c @@ -3,7 +3,7 @@ * * QE Parallel I/O ports configuration routines * - * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved. + * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved. * * Author: Li Yang * Based on code from Shlomi Gridish diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c index 04677505f20..134b07d2943 100644 --- a/arch/powerpc/sysdev/qe_lib/ucc.c +++ b/arch/powerpc/sysdev/qe_lib/ucc.c @@ -3,7 +3,7 @@ * * QE UCC API Set - UCC specific routines implementations. * - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c index fba02440d12..cceb2e36673 100644 --- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c +++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c index 524c0ead941..1c062f48f1a 100644 --- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c +++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. + * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. * * Authors: Shlomi Gridish * Li Yang diff --git a/arch/powerpc/sysdev/qe_lib/usb.c b/arch/powerpc/sysdev/qe_lib/usb.c index 9162828f5da..27f23bd15eb 100644 --- a/arch/powerpc/sysdev/qe_lib/usb.c +++ b/arch/powerpc/sysdev/qe_lib/usb.c @@ -1,7 +1,7 @@ /* * QE USB routines * - * Copyright (c) Freescale Semicondutor, Inc. 2006. + * Copyright 2006 Freescale Semiconductor, Inc. * Shlomi Gridish * Jerry Huang * Copyright (c) MontaVista Software, Inc. 2008. -- cgit v1.2.3-70-g09d2 From c5a0809a24c19fcefea5f3aeb07bde9a2dee5d80 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sun, 4 Nov 2012 02:03:43 +0000 Subject: powerpc/iommu: Use bitmap library - Caluculate the bitmap size with BITS_TO_LONGS() - Use bitmap_empty() to verify that all bits are cleared This also includes a printk to pr_warn() conversion. Signed-off-by: Akinobu Mita Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/iommu.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index 8226c6cb348..c862fd716fe 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -656,7 +656,7 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid) struct iommu_pool *p; /* number of bytes needed for the bitmap */ - sz = (tbl->it_size + 7) >> 3; + sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long); page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz)); if (!page) @@ -708,7 +708,7 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid) void iommu_free_table(struct iommu_table *tbl, const char *node_name) { - unsigned long bitmap_sz, i; + unsigned long bitmap_sz; unsigned int order; if (!tbl || !tbl->it_map) { @@ -718,17 +718,11 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name) } /* verify that table contains no entries */ - /* it_size is in entries, and we're examining 64 at a time */ - for (i = 0; i < (tbl->it_size/64); i++) { - if (tbl->it_map[i] != 0) { - printk(KERN_WARNING "%s: Unexpected TCEs for %s\n", - __func__, node_name); - break; - } - } + if (!bitmap_empty(tbl->it_map, tbl->it_size)) + pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name); /* calculate bitmap size in bytes */ - bitmap_sz = (tbl->it_size + 7) / 8; + bitmap_sz = BITS_TO_LONGS(tbl->it_size) * sizeof(unsigned long); /* free bitmap */ order = get_order(bitmap_sz); -- cgit v1.2.3-70-g09d2 From 2237f4f40af9ab57d5427b35d1514d3e65d31d1a Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sun, 4 Nov 2012 02:03:44 +0000 Subject: powerpc: Remove BITOP_MASK and BITOP_WORD from asm/bitops.h Replace BITOP_MASK and BITOP_WORD with BIT_MASK and BIT_WORD defined in linux/bitops.h and remove BITOP_* which are not used anymore. Signed-off-by: Akinobu Mita Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/bitops.h | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index dc2cf9c6d9e..920596f3b2a 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -52,8 +52,6 @@ #define smp_mb__before_clear_bit() smp_mb() #define smp_mb__after_clear_bit() smp_mb() -#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) #define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) /* Macro for generating the ***_bits() functions */ @@ -83,22 +81,22 @@ DEFINE_BITOP(change_bits, xor, "", "") static __inline__ void set_bit(int nr, volatile unsigned long *addr) { - set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)); + set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); } static __inline__ void clear_bit(int nr, volatile unsigned long *addr) { - clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)); + clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); } static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr) { - clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr)); + clear_bits_unlock(BIT_MASK(nr), addr + BIT_WORD(nr)); } static __inline__ void change_bit(int nr, volatile unsigned long *addr) { - change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)); + change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); } /* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output @@ -136,26 +134,26 @@ DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER, static __inline__ int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { - return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0; + return test_and_set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; } static __inline__ int test_and_set_bit_lock(unsigned long nr, volatile unsigned long *addr) { - return test_and_set_bits_lock(BITOP_MASK(nr), - addr + BITOP_WORD(nr)) != 0; + return test_and_set_bits_lock(BIT_MASK(nr), + addr + BIT_WORD(nr)) != 0; } static __inline__ int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { - return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0; + return test_and_clear_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; } static __inline__ int test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { - return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0; + return test_and_change_bits(BIT_MASK(nr), addr + BIT_WORD(nr)) != 0; } #include -- cgit v1.2.3-70-g09d2 From 79597be99ac96b1409eb7ae41c336696d7c4f4d9 Mon Sep 17 00:00:00 2001 From: Akinobu Mita Date: Sun, 4 Nov 2012 02:03:45 +0000 Subject: powerpc: Use asm-generic/bitops/le.h The only difference between powerpc and asm-generic le-bitops is test_bit_le(). Usually all bitops require a long aligned bitmap. But powerpc test_bit_le() can take an unaligned address. There is no special callsite of test_bit_le() that needs unaligned access in powerpc as far as I can see. So convert to use asm-generic/bitops/le.h for powerpc. Signed-off-by: Akinobu Mita Cc: Benjamin Herrenschmidt Cc: Paul Mackerras Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/bitops.h | 55 +-------------------------------------- 1 file changed, 1 insertion(+), 54 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h index 920596f3b2a..ef918a2328b 100644 --- a/arch/powerpc/include/asm/bitops.h +++ b/arch/powerpc/include/asm/bitops.h @@ -278,61 +278,8 @@ unsigned long __arch_hweight64(__u64 w); #include /* Little-endian versions */ +#include -static __inline__ int test_bit_le(unsigned long nr, - __const__ void *addr) -{ - __const__ unsigned char *tmp = (__const__ unsigned char *) addr; - return (tmp[nr >> 3] >> (nr & 7)) & 1; -} - -static inline void set_bit_le(int nr, void *addr) -{ - set_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline void clear_bit_le(int nr, void *addr) -{ - clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline void __set_bit_le(int nr, void *addr) -{ - __set_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline void __clear_bit_le(int nr, void *addr) -{ - __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline int test_and_set_bit_le(int nr, void *addr) -{ - return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline int test_and_clear_bit_le(int nr, void *addr) -{ - return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline int __test_and_set_bit_le(int nr, void *addr) -{ - return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -static inline int __test_and_clear_bit_le(int nr, void *addr) -{ - return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr); -} - -#define find_first_zero_bit_le(addr, size) \ - find_next_zero_bit_le((addr), (size), 0) -unsigned long find_next_zero_bit_le(const void *addr, - unsigned long size, unsigned long offset); - -unsigned long find_next_bit_le(const void *addr, - unsigned long size, unsigned long offset); /* Bitmap functions for the ext2 filesystem */ #include -- cgit v1.2.3-70-g09d2 From a53fd61ac2f411745471c1c877d5e072fbbf0e5c Mon Sep 17 00:00:00 2001 From: Aravinda Prasad Date: Sun, 4 Nov 2012 22:15:28 +0000 Subject: powerpc/ptrace: Enable hardware breakpoint upon re-registering On powerpc, ptrace will disable hardware breakpoint request once the breakpoint is hit. It is the responsibility of the caller to set it again. However, when the caller sets the hardware breakpoint again using ptrace(PTRACE_SET_DEBUGREG, child_pid, 0, addr), the hardware breakpoint is not enabled. While gdb's approach is to unregister and re-register the hardware breakpoint every time the breakpoint is hit - which is working fine, this could affect other programs trying to re-register hardware breakpoint without unregistering. This patch enables hardware breakpoint if the caller is re-registering. Signed-off-by: Aravinda Prasad Acked-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/ptrace.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c index 817b4116e5b..c4970004d44 100644 --- a/arch/powerpc/kernel/ptrace.c +++ b/arch/powerpc/kernel/ptrace.c @@ -952,6 +952,10 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ), &attr.bp_type); + + /* Enable breakpoint */ + attr.disabled = false; + ret = modify_user_hw_breakpoint(bp, &attr); if (ret) { ptrace_put_breakpoints(task); -- cgit v1.2.3-70-g09d2 From 03737439d83f4214b98a391f5ef9709b8d15af02 Mon Sep 17 00:00:00 2001 From: JoonSoo Kim Date: Mon, 12 Nov 2012 06:40:33 +0000 Subject: powerpc: Change free_bootmem() to kfree() commit ea96025a('Don't use alloc_bootmem() in init_IRQ() path') changed alloc_bootmem() to kzalloc(), but missed to change free_bootmem() to kfree(). So correct it. Signed-off-by: Joonsoo Kim Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c index 328d221fd1c..74861a7fb80 100644 --- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c +++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -149,7 +148,7 @@ int __init pq2ads_pci_init_irq(void) priv->regs = of_iomap(np, 0); if (!priv->regs) { printk(KERN_ERR "Cannot map PCI PIC registers.\n"); - goto out_free_bootmem; + goto out_free_kmalloc; } /* mask all PCI interrupts */ @@ -171,9 +170,8 @@ int __init pq2ads_pci_init_irq(void) out_unmap_regs: iounmap(priv->regs); -out_free_bootmem: - free_bootmem((unsigned long)priv, - sizeof(struct pq2ads_pci_pic)); +out_free_kmalloc: + kfree(priv); of_node_put(np); out_unmap_irq: irq_dispose_mapping(irq); -- cgit v1.2.3-70-g09d2 From df77c79920292673b2ce9a338c0da80fe2538b42 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 8 Nov 2012 20:23:11 +0000 Subject: powerpc/pseries: Update ibm,architecture.vec for PAPR 2.7/POWER8 Update ibm,architecture.vec for POWER8 and allows us to support more than one parition per core. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/prom_init.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c index cb6c123722a..779f34049a5 100644 --- a/arch/powerpc/kernel/prom_init.c +++ b/arch/powerpc/kernel/prom_init.c @@ -671,6 +671,7 @@ static void __init early_cmdline_parse(void) #define OV1_PPC_2_04 0x08 /* set if we support PowerPC 2.04 */ #define OV1_PPC_2_05 0x04 /* set if we support PowerPC 2.05 */ #define OV1_PPC_2_06 0x02 /* set if we support PowerPC 2.06 */ +#define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */ /* Option vector 2: Open Firmware options supported */ #define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */ @@ -707,6 +708,7 @@ static void __init early_cmdline_parse(void) #define OV5_PFO_HW_RNG 0x80 /* PFO Random Number Generator */ #define OV5_PFO_HW_842 0x40 /* PFO Compression Accelerator */ #define OV5_PFO_HW_ENCR 0x20 /* PFO Encryption Accelerator */ +#define OV5_SUB_PROCESSORS 0x01 /* 1,2,or 4 Sub-Processors supported */ /* Option Vector 6: IBM PAPR hints */ #define OV6_LINUX 0x02 /* Linux is our OS */ @@ -719,6 +721,8 @@ static unsigned char ibm_architecture_vec[] = { W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */ W(0xffff0000), W(0x003e0000), /* POWER6 */ W(0xffff0000), W(0x003f0000), /* POWER7 */ + W(0xffff0000), W(0x004b0000), /* POWER8 */ + W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */ W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */ W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */ W(0xfffffffe), W(0x0f000001), /* all 2.04-compliant and earlier */ @@ -728,7 +732,7 @@ static unsigned char ibm_architecture_vec[] = { 3 - 2, /* length */ 0, /* don't ignore, don't halt */ OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 | - OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06, + OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07, /* option vector 2: Open Firmware options supported */ 34 - 2, /* length */ @@ -755,7 +759,7 @@ static unsigned char ibm_architecture_vec[] = { OV4_MIN_ENT_CAP, /* minimum VP entitled capacity */ /* option vector 5: PAPR/OF options */ - 18 - 2, /* length */ + 19 - 2, /* length */ 0, /* don't ignore, don't halt */ OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY | OV5_DONATE_DEDICATE_CPU | OV5_MSI, @@ -769,13 +773,14 @@ static unsigned char ibm_architecture_vec[] = { * must match by the macro below. Update the definition if * the structure layout changes. */ -#define IBM_ARCH_VEC_NRCORES_OFFSET 101 +#define IBM_ARCH_VEC_NRCORES_OFFSET 117 W(NR_CPUS), /* number of cores supported */ 0, 0, 0, 0, OV5_PFO_HW_RNG | OV5_PFO_HW_ENCR | OV5_PFO_HW_842, + OV5_SUB_PROCESSORS, /* option vector 6: IBM PAPR hints */ 4 - 2, /* length */ 0, -- cgit v1.2.3-70-g09d2 From c674e703cb1028e468527163074810b4a17bf379 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Thu, 8 Nov 2012 20:26:42 +0000 Subject: powerpc: Add POWER8 architected mode to cputable A PVR of 0x0F000004 means we are arch v2.07 complicate ie, POWER8. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/cputable.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 216ff845caf..75a3d71b895 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -435,6 +435,21 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_restore = __restore_cpu_power7, .platform = "power7", }, + { /* 2.07-compliant processor, i.e. Power8 "architected" mode */ + .pvr_mask = 0xffffffff, + .pvr_value = 0x0f000004, + .cpu_name = "POWER8 (architected)", + .cpu_features = CPU_FTRS_POWER8, + .cpu_user_features = COMMON_USER_POWER8, + .mmu_features = MMU_FTRS_POWER8, + .icache_bsize = 128, + .dcache_bsize = 128, + .oprofile_type = PPC_OPROFILE_POWER4, + .oprofile_cpu_type = "ppc64/ibm-compat-v1", + .cpu_setup = __setup_cpu_power8, + .cpu_restore = __restore_cpu_power8, + .platform = "power8", + }, { /* Power7 */ .pvr_mask = 0xffff0000, .pvr_value = 0x003f0000, -- cgit v1.2.3-70-g09d2 From 11ee7e99f35ecb15f59b21da6a82d96d2cd3fcc8 Mon Sep 17 00:00:00 2001 From: Anton Blanchard Date: Sun, 11 Nov 2012 19:01:05 +0000 Subject: powerpc: Fix CONFIG_RELOCATABLE=y CONFIG_CRASH_DUMP=n build If we build a kernel with CONFIG_RELOCATABLE=y CONFIG_CRASH_DUMP=n, the kernel fails when we run at a non zero offset. It turns out we were incorrectly wrapping some of the relocatable kernel code with CONFIG_CRASH_DUMP. Signed-off-by: Anton Blanchard Cc: Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/head_64.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 694e3fa7885..11a4df9dd58 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -422,7 +422,7 @@ _STATIC(__after_prom_start) tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ #endif -#ifdef CONFIG_CRASH_DUMP +#ifdef CONFIG_RELOCATABLE /* * Check if the kernel has to be running as relocatable kernel based on the * variable __run_at_load, if it is set the kernel is treated as relocatable -- cgit v1.2.3-70-g09d2 From 278a6cdc39218c13c7a924d21cda71d829007b60 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 14:11:51 +1100 Subject: powerpc: Whitespace changes in exception64s.S Remove redundancy spaces and make tab usage consistent. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/exceptions-64s.S | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 56630189f2e..29cf7b1890a 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -613,8 +613,8 @@ machine_check_common: STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) - STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) - STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) + STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) + STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception) STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception) @@ -714,21 +714,21 @@ data_access_common: ld r3,PACA_EXGEN+EX_DAR(r13) lwz r4,PACA_EXGEN+EX_DSISR(r13) li r5,0x300 - b .do_hash_page /* Try to handle as hpte fault */ + b .do_hash_page /* Try to handle as hpte fault */ .align 7 - .globl h_data_storage_common + .globl h_data_storage_common h_data_storage_common: - mfspr r10,SPRN_HDAR - std r10,PACA_EXGEN+EX_DAR(r13) - mfspr r10,SPRN_HDSISR - stw r10,PACA_EXGEN+EX_DSISR(r13) - EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) - bl .save_nvgprs + mfspr r10,SPRN_HDAR + std r10,PACA_EXGEN+EX_DAR(r13) + mfspr r10,SPRN_HDSISR + stw r10,PACA_EXGEN+EX_DSISR(r13) + EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) + bl .save_nvgprs DISABLE_INTS - addi r3,r1,STACK_FRAME_OVERHEAD - bl .unknown_exception - b .ret_from_except + addi r3,r1,STACK_FRAME_OVERHEAD + bl .unknown_exception + b .ret_from_except .align 7 .globl instruction_access_common @@ -741,7 +741,7 @@ instruction_access_common: li r5,0x400 b .do_hash_page /* Try to handle as hpte fault */ - STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) + STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception) /* * Here is the common SLB miss user that is used when going to virtual @@ -1164,7 +1164,7 @@ fwnmi_data_area: /* pseries and powernv need to keep the whole page from * 0x7000 to 0x8000 free for use by the firmware */ - . = 0x8000 + . = 0x8000 #endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */ /* Space for CPU0's segment table */ -- cgit v1.2.3-70-g09d2 From faab4dd2d281d42cb46b16e36f769be59c0a7338 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 13:53:36 +1100 Subject: powerpc: Remove unessessary 0x3000 location enforcement This removes the large gap between 0x1800 and 0x3000. Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/exceptions-64s.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 29cf7b1890a..de029640ba2 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -311,12 +311,14 @@ denorm_exception_hv: #ifdef CONFIG_CBE_RAS STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal) KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802) +#else + . = 0x1800 #endif /* CONFIG_CBE_RAS */ - . = 0x3000 /*** Out of line interrupts support ***/ + .align 7 /* moved from 0x200 */ machine_check_pSeries: .globl machine_check_fwnmi -- cgit v1.2.3-70-g09d2 From 61e2390ede3cea186cc01f5f3d0c9eb570c42c40 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Mon, 5 Nov 2012 17:10:35 +1100 Subject: powerpc: Make load_hander handle upto 64k offset If we change load_hander() to use an ori instead of addi, we can load handlers upto 64k away provided we are still 64k aligned. Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/exception-64s.h | 3 ++- arch/powerpc/kernel/exceptions-64s.S | 4 ++-- arch/powerpc/kernel/setup_64.c | 5 +++++ 3 files changed, 9 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index a43c1473915..9258daac496 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -55,7 +55,8 @@ * word. */ #define LOAD_HANDLER(reg, label) \ - addi reg,reg,(label)-_stext; /* virt addr of handler ... */ + /* Handlers must be within 64K of kbase, which must be 64k aligned */ \ + ori reg,reg,(label)-_stext; /* virt addr of handler ... */ /* Exception register prefixes */ #define EXC_HV H diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index de029640ba2..0969b7ff0f8 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -585,8 +585,8 @@ __end_interrupts: * Code from here down to __end_handlers is invoked from the * exception prologs above. Because the prologs assemble the * addresses of these handlers using the LOAD_HANDLER macro, - * which uses an addi instruction, these handlers must be in - * the first 32k of the kernel image. + * which uses an ori instruction, these handlers must be in + * the first 64k of the kernel image. */ /*** Common interrupt handlers ***/ diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index efb6a41b313..6da881b35da 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -601,6 +601,11 @@ void __init setup_arch(char **cmdline_p) kvm_linear_init(); + /* Interrupt code needs to be 64K-aligned */ + if ((unsigned long)_stext & 0xffff) + panic("Kernelbase not 64K-aligned (0x%lx)!\n", + (unsigned long)_stext); + ppc64_boot_msg(0x15, "Setup Done"); } -- cgit v1.2.3-70-g09d2 From 742415d6b66bf09e3e73280178ef7ec85c90b7ee Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 17:16:01 +1100 Subject: powerpc: Turn syscall handler into macros This turns the syscall handler into macros as we are going to want to reuse them again later. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/exceptions-64s.S | 63 +++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 23 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 0969b7ff0f8..85b3c7e9dd6 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -25,6 +25,43 @@ * 0x7000 - 0x7fff : FWNMI data area * 0x8000 - : Early init and support code */ + /* Syscall routine is used twice, in reloc-off and reloc-on paths */ +#define SYSCALL_PSERIES_1 \ +BEGIN_FTR_SECTION \ + cmpdi r0,0x1ebe ; \ + beq- 1f ; \ +END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ + mr r9,r13 ; \ + GET_PACA(r13) ; \ + mfspr r11,SPRN_SRR0 ; \ +0: + +#define SYSCALL_PSERIES_2_RFID \ + mfspr r12,SPRN_SRR1 ; \ + ld r10,PACAKBASE(r13) ; \ + LOAD_HANDLER(r10, system_call_entry) ; \ + mtspr SPRN_SRR0,r10 ; \ + ld r10,PACAKMSR(r13) ; \ + mtspr SPRN_SRR1,r10 ; \ + rfid ; \ + b . ; /* prevent speculative execution */ + +#define SYSCALL_PSERIES_3 \ + /* Fast LE/BE switch system call */ \ +1: mfspr r12,SPRN_SRR1 ; \ + xori r12,r12,MSR_LE ; \ + mtspr SPRN_SRR1,r12 ; \ + rfid ; /* return to userspace */ \ + b . ; \ +2: mfspr r12,SPRN_SRR1 ; \ + andi. r12,r12,MSR_PR ; \ + bne 0b ; \ + mtspr SPRN_SRR0,r3 ; \ + mtspr SPRN_SRR1,r4 ; \ + mtspr SPRN_SDR1,r5 ; \ + rfid ; \ + b . ; /* prevent speculative execution */ + /* * This is the start of the interrupt handlers for pSeries @@ -207,31 +244,11 @@ system_call_pSeries: KVMTEST(0xc00) GET_SCRATCH0(r13) #endif -BEGIN_FTR_SECTION - cmpdi r0,0x1ebe - beq- 1f -END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) - mr r9,r13 - GET_PACA(r13) - mfspr r11,SPRN_SRR0 - mfspr r12,SPRN_SRR1 - ld r10,PACAKBASE(r13) - LOAD_HANDLER(r10, system_call_entry) - mtspr SPRN_SRR0,r10 - ld r10,PACAKMSR(r13) - mtspr SPRN_SRR1,r10 - rfid - b . /* prevent speculative execution */ - + SYSCALL_PSERIES_1 + SYSCALL_PSERIES_2_RFID + SYSCALL_PSERIES_3 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) -/* Fast LE/BE switch system call */ -1: mfspr r12,SPRN_SRR1 - xori r12,r12,MSR_LE - mtspr SPRN_SRR1,r12 - rfid /* return to userspace */ - b . - STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step) KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00) -- cgit v1.2.3-70-g09d2 From 4700dfaf1e988b785bd9791064df92d3353e8b88 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 17:21:28 +1100 Subject: powerpc: Add new macros needed for relocation on exceptions POWER8/v2.07 allows exceptions to be taken with the MMU still on. A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW takes us here, MSR IR/DR will be set already and we no longer need a costly RFID to turn the MMU back on again. The original 0x0 based exception vectors remain for when the HW can't leave the MMU on. Examples of this are when we can't trust the current the MMU mappings, like when we are changing from guest to hypervisor (HV 0 -> 1) or when the MMU was off already. In these cases the HW will take us to the original 0x0 based exception vectors with the MMU off as before. The below macros are copies of the macros used at the 0x0 offset but modified to handle the MMU being on. In these macros we use the link register to jump to the secondary handlers rather than using RFID (RFID was also use to turn on the MMU). Signed-off-by: Matt Evans Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/exception-64s.h | 90 ++++++++++++++++++++++++++++++++ arch/powerpc/kernel/exceptions-64s.S | 25 +++++++++ 2 files changed, 115 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 9258daac496..10787d3673a 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -48,6 +48,35 @@ #define EX_LR 72 #define EX_CFAR 80 +#ifdef CONFIG_RELOCATABLE +#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ + ld r12,PACAKBASE(r13); /* get high part of &label */ \ + mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ + LOAD_HANDLER(r12,label); \ + mtlr r12; \ + mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ + li r10,MSR_RI; \ + mtmsrd r10,1; /* Set RI (EE=0) */ \ + blr; +#else +/* If not relocatable, we can jump directly -- and save messing with LR */ +#define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ + mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ + mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ + li r10,MSR_RI; \ + mtmsrd r10,1; /* Set RI (EE=0) */ \ + b label; +#endif + +/* + * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on + * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which + * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. + */ +#define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ + EXCEPTION_PROLOG_1(area, extra, vec); \ + EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) + /* * We're short on space and time in the exception prolog, so we can't * use the normal SET_REG_IMMEDIATE macro. Normally we just need the @@ -62,6 +91,22 @@ #define EXC_HV H #define EXC_STD +#if defined(CONFIG_RELOCATABLE) +/* + * If we support interrupts with relocation on AND we're a relocatable + * kernel, we need to use LR to get to the 2nd level handler. So, save/restore + * it when required. + */ +#define SAVE_LR(reg, area) mflr reg ; std reg,area+EX_LR(r13) +#define GET_LR(reg, area) ld reg,area+EX_LR(r13) +#define RESTORE_LR(reg, area) ld reg,area+EX_LR(r13) ; mtlr reg +#else +/* ...else LR is unused and in register. */ +#define SAVE_LR(reg, area) +#define GET_LR(reg, area) mflr reg +#define RESTORE_LR(reg, area) +#endif + #define __EXCEPTION_PROLOG_1(area, extra, vec) \ GET_PACA(r13); \ std r9,area+EX_R9(r13); /* save r9 - r12 */ \ @@ -233,6 +278,26 @@ label##_hv: \ EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ EXC_HV, KVMTEST, vec) +#define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ + . = loc; \ + .globl label##_relon_pSeries; \ +label##_relon_pSeries: \ + HMT_MEDIUM; \ + /* No guest interrupts come through here */ \ + SET_SCRATCH0(r13); /* save r13 */ \ + EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ + EXC_STD, KVMTEST_PR, vec) + +#define STD_RELON_EXCEPTION_HV(loc, vec, label) \ + . = loc; \ + .globl label##_relon_hv; \ +label##_relon_hv: \ + HMT_MEDIUM; \ + /* No guest interrupts come through here */ \ + SET_SCRATCH0(r13); /* save r13 */ \ + EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \ + EXC_HV, KVMTEST, vec) + /* This associate vector numbers with bits in paca->irq_happened */ #define SOFTEN_VALUE_0x500 PACA_IRQ_EE #define SOFTEN_VALUE_0x502 PACA_IRQ_EE @@ -258,6 +323,9 @@ label##_hv: \ KVMTEST(vec); \ _SOFTEN_TEST(EXC_STD, vec) +#define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) +#define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) + #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ HMT_MEDIUM; \ SET_SCRATCH0(r13); /* save r13 */ \ @@ -280,6 +348,28 @@ label##_hv: \ _MASKABLE_EXCEPTION_PSERIES(vec, label, \ EXC_HV, SOFTEN_TEST_HV) +#define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ + HMT_MEDIUM; \ + SET_SCRATCH0(r13); /* save r13 */ \ + __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ + EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, h); +#define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ + __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) + +#define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ + . = loc; \ + .globl label##_relon_pSeries; \ +label##_relon_pSeries: \ + _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ + EXC_STD, SOFTEN_NOTEST_PR) + +#define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ + . = loc; \ + .globl label##_relon_hv; \ +label##_relon_hv: \ + _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ + EXC_HV, SOFTEN_NOTEST_HV) + /* * Our exception common code can be passed various "additions" * to specify the behaviour of interrupts, whether to kick the diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 85b3c7e9dd6..4dc1a045052 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -62,6 +62,31 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ rfid ; \ b . ; /* prevent speculative execution */ +#if defined(CONFIG_RELOCATABLE) + /* + * We can't branch directly; in the direct case we use LR + * and system_call_entry restores LR. (We thus need to move + * LR to r10 in the RFID case too.) + */ +#define SYSCALL_PSERIES_2_DIRECT \ + mflr r10 ; \ + ld r12,PACAKBASE(r13) ; \ + LOAD_HANDLER(r12, system_call_entry_direct) ; \ + mtlr r12 ; \ + mfspr r12,SPRN_SRR1 ; \ + /* Re-use of r13... No spare regs to do this */ \ + li r13,MSR_RI ; \ + mtmsrd r13,1 ; \ + GET_PACA(r13) ; /* get r13 back */ \ + blr ; +#else + /* We can branch directly */ +#define SYSCALL_PSERIES_2_DIRECT \ + mfspr r12,SPRN_SRR1 ; \ + li r10,MSR_RI ; \ + mtmsrd r10,1 ; /* Set RI (EE=0) */ \ + b system_call_entry_direct ; +#endif /* * This is the start of the interrupt handlers for pSeries -- cgit v1.2.3-70-g09d2 From c1fb6816fb1b78dd94b673b0fdaa9a7a16e97bd1 Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 17:21:43 +1100 Subject: powerpc: Add relocation on exception vector handlers POWER8/v2.07 allows exceptions to be taken with the MMU still on. A new set of exception vectors is added at 0xc000_0000_0000_4xxx. When the HW takes us here, MSR IR/DR will be set already and we no longer need a costly RFID to turn the MMU back on again. The original 0x0 based exception vectors remain for when the HW can't leave the MMU on. Examples of this are when we can't trust the current MMU mappings, like when we are changing from guest to hypervisor (HV 0 -> 1) or when the MMU was off already. In these cases the HW will take us to the original 0x0 based exception vectors with the MMU off as before. This uses the new macros added previously too implement these new execption vectors at 0xc000_0000_0000_4xxx. We exit these exception vectors using mflr/blr (rather than mtspr SSR0/RFID), since we don't need the costly MMU switch anymore. This moves the __end_interrupts marker down past these new 0x4000 vectors since they will need to be copied down to 0x0 when the kernel is not at 0x0. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/exception-64s.h | 4 +- arch/powerpc/kernel/exceptions-64s.S | 180 +++++++++++++++++++++++++++++-- arch/powerpc/kernel/head_64.S | 3 +- 3 files changed, 177 insertions(+), 10 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h index 10787d3673a..ad708dda3ba 100644 --- a/arch/powerpc/include/asm/exception-64s.h +++ b/arch/powerpc/include/asm/exception-64s.h @@ -115,6 +115,7 @@ mfspr r10,SPRN_CFAR; \ std r10,area+EX_CFAR(r13); \ END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ + SAVE_LR(r10, area); \ mfcr r9; \ extra(vec); \ std r11,area+EX_R11(r13); \ @@ -215,6 +216,7 @@ do_kvm_##n: \ sth r1,PACA_TRAP_SAVE(r13); \ std r3,area+EX_R3(r13); \ addi r3,r13,area; /* r3 -> where regs are saved*/ \ + RESTORE_LR(r1, area); \ b bad_stack; \ 3: std r9,_CCR(r1); /* save CR in stackframe */ \ std r11,_NIP(r1); /* save SRR0 in stackframe */ \ @@ -240,8 +242,8 @@ do_kvm_##n: \ ld r10,area+EX_CFAR(r13); \ std r10,ORIG_GPR3(r1); \ END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ + GET_LR(r9,area); /* Get LR, later save to stack */ \ ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ - mflr r9; /* save LR in stackframe */ \ std r9,_LINK(r1); \ mfctr r10; /* save CTR in stackframe */ \ std r10,_CTR(r1); \ diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index 4dc1a045052..4665e82fa37 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -19,11 +19,13 @@ /* * We layout physical memory as follows: * 0x0000 - 0x00ff : Secondary processor spin code - * 0x0100 - 0x2fff : pSeries Interrupt prologs - * 0x3000 - 0x5fff : interrupt support common interrupt prologs - * 0x6000 - 0x6fff : Initial (CPU0) segment table + * 0x0100 - 0x17ff : pSeries Interrupt prologs + * 0x1800 - 0x4000 : interrupt support common interrupt prologs + * 0x4000 - 0x5fff : pSeries interrupts with IR=1,DR=1 + * 0x6000 - 0x6fff : more interrupt support including for IR=1,DR=1 * 0x7000 - 0x7fff : FWNMI data area - * 0x8000 - : Early init and support code + * 0x8000 - 0x8fff : Initial (CPU0) segment table + * 0x9000 - : Early init and support code */ /* Syscall routine is used twice, in reloc-off and reloc-on paths */ #define SYSCALL_PSERIES_1 \ @@ -619,10 +621,6 @@ slb_miss_user_pseries: b . /* prevent spec. execution */ #endif /* __DISABLED__ */ - .align 7 - .globl __end_interrupts -__end_interrupts: - /* * Code from here down to __end_handlers is invoked from the * exception prologs above. Because the prologs assemble the @@ -673,7 +671,158 @@ machine_check_common: STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception) #endif /* CONFIG_CBE_RAS */ + /* + * Relocation-on interrupts: A subset of the interrupts can be delivered + * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering + * it. Addresses are the same as the original interrupt addresses, but + * offset by 0xc000000000004000. + * It's impossible to receive interrupts below 0x300 via this mechanism. + * KVM: None of these traps are from the guest ; anything that escalated + * to HV=1 from HV=0 is delivered via real mode handlers. + */ + + /* + * This uses the standard macro, since the original 0x300 vector + * only has extra guff for STAB-based processors -- which never + * come here. + */ + STD_RELON_EXCEPTION_PSERIES(0x4300, 0x300, data_access) + . = 0x4380 + .globl data_access_slb_relon_pSeries +data_access_slb_relon_pSeries: + HMT_MEDIUM + SET_SCRATCH0(r13) + EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) + std r3,PACA_EXSLB+EX_R3(r13) + mfspr r3,SPRN_DAR + mfspr r12,SPRN_SRR1 +#ifndef CONFIG_RELOCATABLE + b .slb_miss_realmode +#else + /* + * We can't just use a direct branch to .slb_miss_realmode + * because the distance from here to there depends on where + * the kernel ends up being put. + */ + mfctr r11 + ld r10,PACAKBASE(r13) + LOAD_HANDLER(r10, .slb_miss_realmode) + mtctr r10 + bctr +#endif + + STD_RELON_EXCEPTION_PSERIES(0x4400, 0x400, instruction_access) + . = 0x4480 + .globl instruction_access_slb_relon_pSeries +instruction_access_slb_relon_pSeries: + HMT_MEDIUM + SET_SCRATCH0(r13) + EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) + std r3,PACA_EXSLB+EX_R3(r13) + mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ + mfspr r12,SPRN_SRR1 +#ifndef CONFIG_RELOCATABLE + b .slb_miss_realmode +#else + mfctr r11 + ld r10,PACAKBASE(r13) + LOAD_HANDLER(r10, .slb_miss_realmode) + mtctr r10 + bctr +#endif + + . = 0x4500 + .globl hardware_interrupt_relon_pSeries; + .globl hardware_interrupt_relon_hv; +hardware_interrupt_relon_pSeries: +hardware_interrupt_relon_hv: + BEGIN_FTR_SECTION + _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV) + FTR_SECTION_ELSE + _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR) + ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206) + STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment) + STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check) + STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable) + MASKABLE_RELON_EXCEPTION_PSERIES(0x4900, 0x900, decrementer) + STD_RELON_EXCEPTION_HV(0x4980, 0x982, hdecrementer) + STD_RELON_EXCEPTION_PSERIES(0x4b00, 0xb00, trap_0b) + + . = 0x4c00 + .globl system_call_relon_pSeries +system_call_relon_pSeries: + HMT_MEDIUM + SYSCALL_PSERIES_1 + SYSCALL_PSERIES_2_DIRECT + SYSCALL_PSERIES_3 + + STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step) + + . = 0x4e00 + b h_data_storage_relon_hv + + . = 0x4e20 + b h_instr_storage_relon_hv + + . = 0x4e40 + b emulation_assist_relon_hv + + . = 0x4e50 + b hmi_exception_relon_hv + + . = 0x4e60 + b hmi_exception_relon_hv + + /* For when we support the doorbell interrupt: + STD_RELON_EXCEPTION_HYPERVISOR(0x4e80, 0xe80, doorbell_hyper) + */ + +performance_monitor_relon_pSeries_1: + . = 0x4f00 + b performance_monitor_relon_pSeries + +altivec_unavailable_relon_pSeries_1: + . = 0x4f20 + b altivec_unavailable_relon_pSeries + +vsx_unavailable_relon_pSeries_1: + . = 0x4f40 + b vsx_unavailable_relon_pSeries + +#ifdef CONFIG_CBE_RAS + STD_RELON_EXCEPTION_HV(0x5200, 0x1202, cbe_system_error) +#endif /* CONFIG_CBE_RAS */ + STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint) +#ifdef CONFIG_PPC_DENORMALISATION + . = 0x5500 + b denorm_exception_hv +#endif +#ifdef CONFIG_CBE_RAS + STD_RELON_EXCEPTION_HV(0x5600, 0x1602, cbe_maintenance) +#else +#ifdef CONFIG_HVC_SCOM + STD_RELON_EXCEPTION_HV(0x5600, 0x1600, maintence_interrupt) + KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1600) +#endif /* CONFIG_HVC_SCOM */ +#endif /* CONFIG_CBE_RAS */ + STD_RELON_EXCEPTION_PSERIES(0x5700, 0x1700, altivec_assist) +#ifdef CONFIG_CBE_RAS + STD_RELON_EXCEPTION_HV(0x5800, 0x1802, cbe_thermal) +#endif /* CONFIG_CBE_RAS */ + + /* Other future vectors */ + .align 7 + .globl __end_interrupts +__end_interrupts: + .align 7 +system_call_entry_direct: +#if defined(CONFIG_RELOCATABLE) + /* The first level prologue may have used LR to get here, saving + * orig in r10. To save hacking/ifdeffing common code, restore here. + */ + mtlr r10 +#endif system_call_entry: b system_call_common @@ -1196,6 +1345,21 @@ _GLOBAL(do_stab_bolted) rfid b . /* prevent speculative execution */ + + /* Equivalents to the above handlers for relocation-on interrupt vectors */ + STD_RELON_EXCEPTION_HV(., 0xe00, h_data_storage) + KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe00) + STD_RELON_EXCEPTION_HV(., 0xe20, h_instr_storage) + KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe20) + STD_RELON_EXCEPTION_HV(., 0xe40, emulation_assist) + KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe40) + STD_RELON_EXCEPTION_HV(., 0xe60, hmi_exception) + KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe60) + + STD_RELON_EXCEPTION_PSERIES(., 0xf00, performance_monitor) + STD_RELON_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable) + STD_RELON_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable) + #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) /* * Data area reserved for FWNMI option. diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 11a4df9dd58..116f0868695 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -432,7 +432,8 @@ _STATIC(__after_prom_start) cmplwi cr0,r7,1 bne 3f - li r5,__end_interrupts - _stext /* just copy interrupts */ + /* just copy interrupts */ + LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) b 5f 3: #endif -- cgit v1.2.3-70-g09d2 From f7c32c24f5788798f17d4e520a5d238335a859cb Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Mon, 5 Nov 2012 14:40:18 +1100 Subject: powerpc: Move initial mfspr LPCR out of __init_LPCR We want to change what's initially set in the LPCR, so start by taking the move from LPCR out of the function and into the caller. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/kernel/cpu_setup_power.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index a92101d14b4..52dd03396c5 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -27,6 +27,7 @@ _GLOBAL(__setup_cpu_power7) beqlr li r0,0 mtspr SPRN_LPID,r0 + mfspr r3,SPRN_LPCR bl __init_LPCR bl __init_TLB mtlr r11 @@ -39,6 +40,7 @@ _GLOBAL(__restore_cpu_power7) beqlr li r0,0 mtspr SPRN_LPID,r0 + mfspr r3,SPRN_LPCR bl __init_LPCR bl __init_TLB mtlr r11 @@ -51,6 +53,7 @@ _GLOBAL(__setup_cpu_power8) beqlr li r0,0 mtspr SPRN_LPID,r0 + mfspr r3,SPRN_LPCR bl __init_LPCR bl __init_TLB mtlr r11 @@ -63,6 +66,7 @@ _GLOBAL(__restore_cpu_power8) beqlr li r0,0 mtspr SPRN_LPID,r0 + mfspr r3,SPRN_LPCR bl __init_LPCR bl __init_TLB mtlr r11 @@ -81,6 +85,7 @@ __init_hvmode_206: __init_LPCR: /* Setup a sane LPCR: + * Called with initial LPCR in R3 * * LPES = 0b01 (HSRR0/1 used for 0x500) * PECE = 0b111 @@ -91,7 +96,6 @@ __init_LPCR: * * Other bits untouched for now */ - mfspr r3,SPRN_LPCR li r5,1 rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) -- cgit v1.2.3-70-g09d2 From b0302722eec7c086a31de6e3d9789304ef21df7b Mon Sep 17 00:00:00 2001 From: Michael Neuling Date: Fri, 2 Nov 2012 16:41:58 +1100 Subject: powerpc: Setup relocation on exceptions for bare metal systems This turns on MMU on execptions via AIL field in the LPCR. Signed-off-by: Matt Evans Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/reg.h | 2 ++ arch/powerpc/kernel/cpu_setup_power.S | 2 ++ 2 files changed, 4 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 7b44a6e3e0f..1b853f744f8 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -249,6 +249,8 @@ #define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ #define LPCR_RMLS_SH (63-37) #define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ +#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ +#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ #define LPCR_PECE 0x00007000 /* powersave exit cause enable */ #define LPCR_PECE0 0x00004000 /* ext. exceptions can cause exit */ #define LPCR_PECE1 0x00002000 /* decrementer can cause exit */ diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 52dd03396c5..57cf14065ae 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S @@ -54,6 +54,7 @@ _GLOBAL(__setup_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR + oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_TLB mtlr r11 @@ -67,6 +68,7 @@ _GLOBAL(__restore_cpu_power8) li r0,0 mtspr SPRN_LPID,r0 mfspr r3,SPRN_LPCR + oris r3, r3, LPCR_AIL_3@h bl __init_LPCR bl __init_TLB mtlr r11 -- cgit v1.2.3-70-g09d2 From d8f48ecc0e81cbc52a8eac907e02916d98dbfb5a Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Tue, 6 Nov 2012 16:15:17 +1100 Subject: powerpc: Add set_mode hcall This new hcall in POWER8 is used to set various resource mode registers. eg. it can set address translation mode on interrupt (note: partition wide scope) Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/firmware.h | 4 +++- arch/powerpc/include/asm/hvcall.h | 3 ++- arch/powerpc/platforms/pseries/firmware.c | 1 + arch/powerpc/platforms/pseries/plpar_wrappers.h | 6 ++++++ 4 files changed, 12 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h index ad0b751b0d7..973cc3be011 100644 --- a/arch/powerpc/include/asm/firmware.h +++ b/arch/powerpc/include/asm/firmware.h @@ -49,6 +49,7 @@ #define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000) #define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000) #define FW_FEATURE_OPALv2 ASM_CONST(0x0000000020000000) +#define FW_FEATURE_SET_MODE ASM_CONST(0x0000000040000000) #ifndef __ASSEMBLY__ @@ -62,7 +63,8 @@ enum { FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN | FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR | FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR | - FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO, + FW_FEATURE_CMO | FW_FEATURE_VPHN | FW_FEATURE_XCMO | + FW_FEATURE_SET_MODE, FW_FEATURE_PSERIES_ALWAYS = 0, FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_OPALv2, FW_FEATURE_POWERNV_ALWAYS = 0, diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index 7a867065db7..a3d26d8f63c 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -267,7 +267,8 @@ #define H_RANDOM 0x300 #define H_COP 0x304 #define H_GET_MPP_X 0x314 -#define MAX_HCALL_OPCODE H_GET_MPP_X +#define H_SET_MODE 0x31C +#define MAX_HCALL_OPCODE H_SET_MODE #ifndef __ASSEMBLY__ diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c index 0b0eff0cce3..7b56118f531 100644 --- a/arch/powerpc/platforms/pseries/firmware.c +++ b/arch/powerpc/platforms/pseries/firmware.c @@ -56,6 +56,7 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = { {FW_FEATURE_MULTITCE, "hcall-multi-tce"}, {FW_FEATURE_SPLPAR, "hcall-splpar"}, {FW_FEATURE_VPHN, "hcall-vphn"}, + {FW_FEATURE_SET_MODE, "hcall-set-mode"}, }; /* Build up the firmware features bitmask using the contents of diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h index 13e8cc43adf..44ad2140345 100644 --- a/arch/powerpc/platforms/pseries/plpar_wrappers.h +++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h @@ -273,4 +273,10 @@ static inline long plpar_put_term_char(unsigned long termno, unsigned long len, lbuf[1]); } +/* Set various resource mode parameters */ +static inline long plpar_set_mode(unsigned long mflags, unsigned long resource, + unsigned long value1, unsigned long value2) +{ + return plpar_hcall_norets(H_SET_MODE, mflags, resource, value1, value2); +} #endif /* _PSERIES_PLPAR_WRAPPERS_H */ -- cgit v1.2.3-70-g09d2 From 798042da4e039ef551ff6e1b1ead50a763181daa Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Thu, 8 Nov 2012 15:57:04 +1100 Subject: powerpc: Add wrappers to enable/disable relocation on exceptions These wrappers hide the parameters that have to be passed to H_SET_MODE to enable/disable relocation on during exceptions. As noted in the comments, since these have partition wide scope, they may take some time to complete and must be periodically retried until H_SUCCESS is returned. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/pseries/plpar_wrappers.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/pseries/plpar_wrappers.h b/arch/powerpc/platforms/pseries/plpar_wrappers.h index 44ad2140345..e6cc34a6705 100644 --- a/arch/powerpc/platforms/pseries/plpar_wrappers.h +++ b/arch/powerpc/platforms/pseries/plpar_wrappers.h @@ -279,4 +279,29 @@ static inline long plpar_set_mode(unsigned long mflags, unsigned long resource, { return plpar_hcall_norets(H_SET_MODE, mflags, resource, value1, value2); } + +/* + * Enable relocation on exceptions on this partition + * + * Note: this call has a partition wide scope and can take a while to complete. + * If it returns H_LONG_BUSY_* it should be retried periodically until it + * returns H_SUCCESS. + */ +static inline long enable_reloc_on_exceptions(void) +{ + /* mflags = 3: Exceptions at 0xC000000000004000 */ + return plpar_set_mode(3, 3, 0, 0); +} + +/* + * Disable relocation on exceptions on this partition + * + * Note: this call has a partition wide scope and can take a while to complete. + * If it returns H_LONG_BUSY_* it should be retried periodically until it + * returns H_SUCCESS. + */ +static inline long disable_reloc_on_exceptions(void) { + return plpar_set_mode(0, 3, 0, 0); +} + #endif /* _PSERIES_PLPAR_WRAPPERS_H */ -- cgit v1.2.3-70-g09d2 From cca55d9ddf6d431114ab9f7cad3e761b74255c9c Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Thu, 8 Nov 2012 16:10:29 +1100 Subject: powerpc: Move get_longbusy_msecs into hvcall.h and remove duplicate function I am going to use this in the next patch, better to have this code in one place rather than three. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/include/asm/hvcall.h | 20 ++++++++++++++++++++ drivers/infiniband/hw/ehca/hcp_if.c | 20 -------------------- drivers/net/ethernet/ibm/ehea/ehea_phyp.h | 20 -------------------- 3 files changed, 20 insertions(+), 40 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h index a3d26d8f63c..0975e5c0bb1 100644 --- a/arch/powerpc/include/asm/hvcall.h +++ b/arch/powerpc/include/asm/hvcall.h @@ -356,6 +356,26 @@ struct hvcall_mpp_x_data { int h_get_mpp_x(struct hvcall_mpp_x_data *mpp_x_data); +static inline unsigned int get_longbusy_msecs(int longbusy_rc) +{ + switch (longbusy_rc) { + case H_LONG_BUSY_ORDER_1_MSEC: + return 1; + case H_LONG_BUSY_ORDER_10_MSEC: + return 10; + case H_LONG_BUSY_ORDER_100_MSEC: + return 100; + case H_LONG_BUSY_ORDER_1_SEC: + return 1000; + case H_LONG_BUSY_ORDER_10_SEC: + return 10000; + case H_LONG_BUSY_ORDER_100_SEC: + return 100000; + default: + return 1; + } +} + #ifdef CONFIG_PPC_PSERIES extern int CMO_PrPSP; extern int CMO_SecPSP; diff --git a/drivers/infiniband/hw/ehca/hcp_if.c b/drivers/infiniband/hw/ehca/hcp_if.c index 2d41d04fd95..89517ffb438 100644 --- a/drivers/infiniband/hw/ehca/hcp_if.c +++ b/drivers/infiniband/hw/ehca/hcp_if.c @@ -90,26 +90,6 @@ static DEFINE_SPINLOCK(hcall_lock); -static u32 get_longbusy_msecs(int longbusy_rc) -{ - switch (longbusy_rc) { - case H_LONG_BUSY_ORDER_1_MSEC: - return 1; - case H_LONG_BUSY_ORDER_10_MSEC: - return 10; - case H_LONG_BUSY_ORDER_100_MSEC: - return 100; - case H_LONG_BUSY_ORDER_1_SEC: - return 1000; - case H_LONG_BUSY_ORDER_10_SEC: - return 10000; - case H_LONG_BUSY_ORDER_100_SEC: - return 100000; - default: - return 1; - } -} - static long ehca_plpar_hcall_norets(unsigned long opcode, unsigned long arg1, unsigned long arg2, diff --git a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h index 8364815c32f..99b6c2a38db 100644 --- a/drivers/net/ethernet/ibm/ehea/ehea_phyp.h +++ b/drivers/net/ethernet/ibm/ehea/ehea_phyp.h @@ -39,26 +39,6 @@ * hcp_* - structures, variables and functions releated to Hypervisor Calls */ -static inline u32 get_longbusy_msecs(int long_busy_ret_code) -{ - switch (long_busy_ret_code) { - case H_LONG_BUSY_ORDER_1_MSEC: - return 1; - case H_LONG_BUSY_ORDER_10_MSEC: - return 10; - case H_LONG_BUSY_ORDER_100_MSEC: - return 100; - case H_LONG_BUSY_ORDER_1_SEC: - return 1000; - case H_LONG_BUSY_ORDER_10_SEC: - return 10000; - case H_LONG_BUSY_ORDER_100_SEC: - return 100000; - default: - return 1; - } -} - /* Number of pages which can be registered at once by H_REGISTER_HEA_RPAGES */ #define EHEA_MAX_RPAGE 512 -- cgit v1.2.3-70-g09d2 From fc8effa4e46fb7bd8a3c5e293efc56b74a54b7a5 Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Thu, 8 Nov 2012 16:03:14 +1100 Subject: powerpc: Enable relocation on during exceptions at boot We currently do this synchronously at boot from setup_arch. On a large system this could hypothetically take a little while to complete, so currently we will give up if we are asked to wait for more than a second in total. If we actually start hitting that timeout in practice we can always move this code into a kernel thread to take care of it in the background. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/pseries/setup.c | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index e1a5b8a32d2..5d97553e5c2 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -367,6 +367,36 @@ static void pSeries_idle(void) } } +/* + * Enable relocation on during exceptions. This has partition wide scope and + * may take a while to complete, if it takes longer than one second we will + * just give up rather than wasting any more time on this - if that turns out + * to ever be a problem in practice we can move this into a kernel thread to + * finish off the process later in boot. + */ +static int __init pSeries_enable_reloc_on_exc(void) +{ + long rc; + unsigned int delay, total_delay = 0; + + while (1) { + rc = enable_reloc_on_exceptions(); + if (!H_IS_LONG_BUSY(rc)) + return rc; + + delay = get_longbusy_msecs(rc); + total_delay += delay; + if (total_delay > 1000) { + pr_warn("Warning: Giving up waiting to enable " + "relocation on exceptions (%u msec)!\n", + total_delay); + return rc; + } + + mdelay(delay); + } +} + static void __init pSeries_setup_arch(void) { panic_timeout = 10; @@ -402,6 +432,14 @@ static void __init pSeries_setup_arch(void) ppc_md.enable_pmcs = pseries_lpar_enable_pmcs; else ppc_md.enable_pmcs = power4_enable_pmcs; + + if (firmware_has_feature(FW_FEATURE_SET_MODE)) { + long rc; + if ((rc = pSeries_enable_reloc_on_exc()) != H_SUCCESS) { + pr_warn("Unable to enable relocation on exceptions: " + "%ld\n", rc); + } + } } static int __init pSeries_init_panel(void) -- cgit v1.2.3-70-g09d2 From cedddd812a79a4fda3885a15711aee3de78c4a24 Mon Sep 17 00:00:00 2001 From: Ian Munsie Date: Thu, 8 Nov 2012 16:40:28 +1100 Subject: powerpc: Disable relocation on exceptions when kexecing Since we don't know if they new kernel we are kexecing into has been built to support relocation on exceptions, we disable them before we kexec. We do NOT disable them if we are execing a kdump kernel, because we want to change as little state as possible and it is likely that we are execing ourselves and will be able to handle them anyway. Signed-off-by: Ian Munsie Signed-off-by: Michael Neuling Signed-off-by: Benjamin Herrenschmidt --- arch/powerpc/platforms/pseries/setup.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c index 5d97553e5c2..ca55882465d 100644 --- a/arch/powerpc/platforms/pseries/setup.c +++ b/arch/powerpc/platforms/pseries/setup.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -397,6 +398,35 @@ static int __init pSeries_enable_reloc_on_exc(void) } } +#ifdef CONFIG_KEXEC +static long pSeries_disable_reloc_on_exc(void) +{ + long rc; + + while (1) { + rc = disable_reloc_on_exceptions(); + if (!H_IS_LONG_BUSY(rc)) + return rc; + mdelay(get_longbusy_msecs(rc)); + } +} + +static void pSeries_machine_kexec(struct kimage *image) +{ + long rc; + + if (firmware_has_feature(FW_FEATURE_SET_MODE) && + (image->type != KEXEC_TYPE_CRASH)) { + rc = pSeries_disable_reloc_on_exc(); + if (rc != H_SUCCESS) + pr_warning("Warning: Failed to disable relocation on " + "exceptions: %ld\n", rc); + } + + default_machine_kexec(image); +} +#endif + static void __init pSeries_setup_arch(void) { panic_timeout = 10; @@ -697,4 +727,7 @@ define_machine(pseries) { .progress = rtas_progress, .system_reset_exception = pSeries_system_reset_exception, .machine_check_exception = pSeries_machine_check_exception, +#ifdef CONFIG_KEXEC + .machine_kexec = pSeries_machine_kexec, +#endif }; -- cgit v1.2.3-70-g09d2 From 41863f730ff8aad86c038aabee1292d1b04c8876 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 4 Oct 2012 09:28:29 +0200 Subject: ARM: nomadik: switch over to using the FSMC driver The Nomadik NAND driver is really just a subset of the existing FSMC driver, so let's switch over to using that driver instead, since it handles more variants of this chip. The callbacks for setting up the chip is doing stuff now handled by the FSMC driver. Signed-off-by: Linus Walleij Acked-by: Alessandro Rubini Signed-off-by: Artem Bityutskiy --- arch/arm/configs/nhk8815_defconfig | 2 +- arch/arm/mach-nomadik/board-nhk8815.c | 64 ++++++++++++++----------------- arch/arm/mach-nomadik/include/mach/fsmc.h | 29 -------------- drivers/clk/clk-nomadik.c | 1 + 4 files changed, 30 insertions(+), 66 deletions(-) delete mode 100644 arch/arm/mach-nomadik/include/mach/fsmc.h (limited to 'arch') diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index 240b25eea56..86cfd2959c4 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -57,7 +57,7 @@ CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_ECC_SMC=y -CONFIG_MTD_NAND_NOMADIK=y +CONFIG_MTD_NAND_FSMC=y CONFIG_MTD_ONENAND=y CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=y diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index bfa1eab91f4..a105d1b7975 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,7 +37,6 @@ #include #include -#include #include #include "cpu-8815.h" @@ -48,36 +48,18 @@ /* These addresses span 16MB, so use three individual pages */ static struct resource nhk8815_nand_resources[] = { { - .name = "nand_addr", - .start = NAND_IO_ADDR, - .end = NAND_IO_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .name = "nand_cmd", - .start = NAND_IO_CMD, - .end = NAND_IO_CMD + 0xfff, + .name = "nand_data", + .start = 0x40000000, + .end = 0x40000000 + SZ_16K - 1, .flags = IORESOURCE_MEM, }, { - .name = "nand_data", - .start = NAND_IO_DATA, - .end = NAND_IO_DATA + 0xfff, + .name = "fsmc_regs", + .start = NOMADIK_FSMC_BASE, + .end = NOMADIK_FSMC_BASE + SZ_4K - 1, .flags = IORESOURCE_MEM, - } + }, }; -static int nhk8815_nand_init(void) -{ - /* FSMC setup for nand chip select (8-bit nand in 8815NHK) */ - writel(0x0000000E, FSMC_PCR(0)); - writel(0x000D0A00, FSMC_PMEM(0)); - writel(0x00100A00, FSMC_PATT(0)); - - /* enable access to the chip select area */ - writel(readl(FSMC_PCR(0)) | 0x04, FSMC_PCR(0)); - - return 0; -} - /* * These partitions are the same as those used in the 2.6.20 release * shipped by the vendor; the first two partitions are mandated @@ -111,20 +93,30 @@ static struct mtd_partition nhk8815_partitions[] = { } }; -static struct nomadik_nand_platform_data nhk8815_nand_data = { - .parts = nhk8815_partitions, - .nparts = ARRAY_SIZE(nhk8815_partitions), - .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING, - .init = nhk8815_nand_init, +static struct fsmc_nand_timings nhk8815_nand_timings = { + .thiz = 0, + .thold = 0x10, + .twait = 0x0A, + .tset = 0, +}; + +static struct fsmc_nand_platform_data nhk8815_nand_platform_data = { + .nand_timings = &nhk8815_nand_timings, + .partitions = nhk8815_partitions, + .nr_partitions = ARRAY_SIZE(nhk8815_partitions), + .width = FSMC_NAND_BW8, + .ale_off = 0x1000000, + .cle_off = 0x800000, }; static struct platform_device nhk8815_nand_device = { - .name = "nomadik_nand", - .dev = { - .platform_data = &nhk8815_nand_data, + .name = "fsmc-nand", + .id = -1, + .resource = nhk8815_nand_resources, + .num_resources = ARRAY_SIZE(nhk8815_nand_resources), + .dev = { + .platform_data = &nhk8815_nand_platform_data, }, - .resource = nhk8815_nand_resources, - .num_resources = ARRAY_SIZE(nhk8815_nand_resources), }; /* These are the partitions for the OneNand device, different from above */ diff --git a/arch/arm/mach-nomadik/include/mach/fsmc.h b/arch/arm/mach-nomadik/include/mach/fsmc.h deleted file mode 100644 index 8c2c0518368..00000000000 --- a/arch/arm/mach-nomadik/include/mach/fsmc.h +++ /dev/null @@ -1,29 +0,0 @@ - -/* Definitions for the Nomadik FSMC "Flexible Static Memory controller" */ - -#ifndef __ASM_ARCH_FSMC_H -#define __ASM_ARCH_FSMC_H - -#include -/* - * Register list - */ - -/* bus control reg. and bus timing reg. for CS0..CS3 */ -#define FSMC_BCR(x) (NOMADIK_FSMC_VA + (x << 3)) -#define FSMC_BTR(x) (NOMADIK_FSMC_VA + (x << 3) + 0x04) - -/* PC-card and NAND: - * PCR = control register - * PMEM = memory timing - * PATT = attribute timing - * PIO = I/O timing - * PECCR = ECC result - */ -#define FSMC_PCR(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x00) -#define FSMC_PMEM(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x08) -#define FSMC_PATT(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x0c) -#define FSMC_PIO(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x10) -#define FSMC_PECCR(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x14) - -#endif /* __ASM_ARCH_FSMC_H */ diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 517a8ff7121..6b4c70f7d23 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -20,6 +20,7 @@ void __init nomadik_clk_init(void) clk_register_clkdev(clk, NULL, "gpio.2"); clk_register_clkdev(clk, NULL, "gpio.3"); clk_register_clkdev(clk, NULL, "rng"); + clk_register_clkdev(clk, NULL, "fsmc-nand"); /* * The 2.4 MHz TIMCLK reference clock is active at boot time, this is -- cgit v1.2.3-70-g09d2 From 6d7b42a447f92eb3e7e410bbf62042693eb040f7 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 4 Oct 2012 15:14:16 +0200 Subject: mtd: fsmc_nand: pass the ale and cmd resource via resource Do not use the platform_data to pass resource and be smart in the drivers. Just pass it via resource Switch to devm_request_and_ioremap at the sametime Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Linus Walleij Reviewed-By: Vipin Kumar Signed-off-by: Artem Bityutskiy --- .../devicetree/bindings/mtd/fsmc-nand.txt | 12 +++--- arch/arm/boot/dts/spear13xx.dtsi | 10 ++--- arch/arm/boot/dts/spear300.dtsi | 8 ++-- arch/arm/boot/dts/spear310.dtsi | 8 ++-- arch/arm/boot/dts/spear320.dtsi | 8 ++-- arch/arm/boot/dts/spear600.dtsi | 8 ++-- arch/arm/mach-u300/core.c | 14 ++++++- drivers/mtd/nand/fsmc_nand.c | 44 ++++++---------------- include/linux/mtd/fsmc.h | 3 -- 9 files changed, 49 insertions(+), 66 deletions(-) (limited to 'arch') diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt index e2c663b354d..e3ea32e7de3 100644 --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt @@ -3,9 +3,7 @@ Required properties: - compatible : "st,spear600-fsmc-nand" - reg : Address range of the mtd chip -- reg-names: Should contain the reg names "fsmc_regs" and "nand_data" -- st,ale-off : Chip specific offset to ALE -- st,cle-off : Chip specific offset to CLE +- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" Optional properties: - bank-width : Width (in bytes) of the device. If not present, the width @@ -19,10 +17,10 @@ Example: #address-cells = <1>; #size-cells = <1>; reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x4000>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; + 0xd2000000 0x0010 /* NAND Base DATA */ + 0xd2020000 0x0010 /* NAND Base ADDR */ + 0xd2010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; bank-width = <1>; nand-skip-bbtscan; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index f7b84aced65..14a6d15c2a8 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -104,15 +104,15 @@ compatible = "st,spear600-fsmc-nand"; #address-cells = <1>; #size-cells = <1>; - reg = <0xb0000000 0x1000 /* FSMC Register */ - 0xb0800000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; + reg = <0xb0000000 0x1000 /* FSMC Register*/ + 0xb0800000 0x0010 /* NAND Base DATA */ + 0xb0820000 0x0010 /* NAND Base ADDR */ + 0xb0810000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; interrupts = <0 20 0x4 0 21 0x4 0 22 0x4 0 23 0x4>; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi index ed3627c116c..bc436387d7f 100644 --- a/arch/arm/boot/dts/spear300.dtsi +++ b/arch/arm/boot/dts/spear300.dtsi @@ -38,10 +38,10 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x94000000 0x1000 /* FSMC Register */ - 0x80000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; + 0x80000000 0x0010 /* NAND Base DATA */ + 0x80020000 0x0010 /* NAND Base ADDR */ + 0x80010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi index 62fc4fb3e5f..7840e529aba 100644 --- a/arch/arm/boot/dts/spear310.dtsi +++ b/arch/arm/boot/dts/spear310.dtsi @@ -32,10 +32,10 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x44000000 0x1000 /* FSMC Register */ - 0x40000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x10000>; - st,cle-off = <0x20000>; + 0x40000000 0x0010 /* NAND Base DATA */ + 0x40020000 0x0010 /* NAND Base ADDR */ + 0x40010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi index 1f49d69595a..5ad820641ac 100644 --- a/arch/arm/boot/dts/spear320.dtsi +++ b/arch/arm/boot/dts/spear320.dtsi @@ -38,10 +38,10 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x4c000000 0x1000 /* FSMC Register */ - 0x50000000 0x0010>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; + 0x50000000 0x0010 /* NAND Base DATA */ + 0x50020000 0x0010 /* NAND Base ADDR */ + 0x50010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index a3c36e47d7e..4ecc66f5ac8 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -67,10 +67,10 @@ #address-cells = <1>; #size-cells = <1>; reg = <0xd1800000 0x1000 /* FSMC Register */ - 0xd2000000 0x4000>; /* NAND Base */ - reg-names = "fsmc_regs", "nand_data"; - st,ale-off = <0x20000>; - st,cle-off = <0x10000>; + 0xd2000000 0x0010 /* NAND Base DATA */ + 0xd2020000 0x0010 /* NAND Base ADDR */ + 0xd2010000 0x0010>; /* NAND Base CMD */ + reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; status = "disabled"; }; diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index b8efac4daed..f642a155234 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -251,6 +251,18 @@ static struct resource rtc_resources[] = { * but these are not yet used by the driver. */ static struct resource fsmc_resources[] = { + { + .name = "nand_addr", + .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE, + .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "nand_cmd", + .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE, + .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { .name = "nand_data", .start = U300_NAND_CS0_PHYS_BASE, @@ -1496,8 +1508,6 @@ static struct fsmc_nand_platform_data nand_platform_data = { .nr_partitions = ARRAY_SIZE(u300_partitions), .options = NAND_SKIP_BBTSCAN, .width = FSMC_NAND_BW8, - .ale_off = PLAT_NAND_ALE, - .cle_off = PLAT_NAND_CLE, }; static struct platform_device nand_device = { diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 38d26240d8b..cb864508715 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -876,8 +876,6 @@ static int __devinit fsmc_nand_probe_config_dt(struct platform_device *pdev, return -EINVAL; } } - of_property_read_u32(np, "st,ale-off", &pdata->ale_off); - of_property_read_u32(np, "st,cle-off", &pdata->cle_off); if (of_get_property(np, "nand-skip-bbtscan", NULL)) pdata->options = NAND_SKIP_BBTSCAN; @@ -935,41 +933,28 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) if (!res) return -EINVAL; - if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), - pdev->name)) { - dev_err(&pdev->dev, "Failed to get memory data resourse\n"); - return -ENOENT; - } - - host->data_pa = (dma_addr_t)res->start; - host->data_va = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); + host->data_va = devm_request_and_ioremap(&pdev->dev, res); if (!host->data_va) { dev_err(&pdev->dev, "data ioremap failed\n"); return -ENOMEM; } + host->data_pa = (dma_addr_t)res->start; - if (!devm_request_mem_region(&pdev->dev, res->start + pdata->ale_off, - resource_size(res), pdev->name)) { - dev_err(&pdev->dev, "Failed to get memory ale resourse\n"); - return -ENOENT; - } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); + if (!res) + return -EINVAL; - host->addr_va = devm_ioremap(&pdev->dev, res->start + pdata->ale_off, - resource_size(res)); + host->addr_va = devm_request_and_ioremap(&pdev->dev, res); if (!host->addr_va) { dev_err(&pdev->dev, "ale ioremap failed\n"); return -ENOMEM; } - if (!devm_request_mem_region(&pdev->dev, res->start + pdata->cle_off, - resource_size(res), pdev->name)) { - dev_err(&pdev->dev, "Failed to get memory cle resourse\n"); - return -ENOENT; - } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); + if (!res) + return -EINVAL; - host->cmd_va = devm_ioremap(&pdev->dev, res->start + pdata->cle_off, - resource_size(res)); + host->cmd_va = devm_request_and_ioremap(&pdev->dev, res); if (!host->cmd_va) { dev_err(&pdev->dev, "ale ioremap failed\n"); return -ENOMEM; @@ -979,14 +964,7 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) if (!res) return -EINVAL; - if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), - pdev->name)) { - dev_err(&pdev->dev, "Failed to get memory regs resourse\n"); - return -ENOENT; - } - - host->regs_va = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); + host->regs_va = devm_request_and_ioremap(&pdev->dev, res); if (!host->regs_va) { dev_err(&pdev->dev, "regs ioremap failed\n"); return -ENOMEM; diff --git a/include/linux/mtd/fsmc.h b/include/linux/mtd/fsmc.h index b20029221fb..d6ed61ef451 100644 --- a/include/linux/mtd/fsmc.h +++ b/include/linux/mtd/fsmc.h @@ -155,9 +155,6 @@ struct fsmc_nand_platform_data { unsigned int width; unsigned int bank; - /* CLE, ALE offsets */ - unsigned int cle_off; - unsigned int ale_off; enum access_mode mode; void (*select_bank)(uint32_t bank, uint32_t busw); -- cgit v1.2.3-70-g09d2 From db6364a650edcb076786092c7f85f1e1cdae8b20 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 12 Oct 2012 00:23:02 +0200 Subject: ARM: nomadik: fixup some FSMC merge problems Due to a clash between refactoring and due to loss of a header file that remained in my working tree the Nomadik stopped compiling after switching to the FSMC driver. This patch fixes it up. Cc: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Linus Walleij Acked-by: Jean-Christophe PLAGNIOL-VILLARD Signed-off-by: Artem Bityutskiy --- arch/arm/mach-nomadik/board-nhk8815.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index a105d1b7975..3f97ef40ce6 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c @@ -37,14 +37,15 @@ #include #include -#include - #include "cpu-8815.h" /* Initial value for SRC control register: all timers use MXTAL/8 source */ #define SRC_CR_INIT_MASK 0x00007fff #define SRC_CR_INIT_VAL 0x2aaa8000 +#define ALE_OFF 0x1000000 +#define CLE_OFF 0x800000 + /* These addresses span 16MB, so use three individual pages */ static struct resource nhk8815_nand_resources[] = { { @@ -52,6 +53,16 @@ static struct resource nhk8815_nand_resources[] = { .start = 0x40000000, .end = 0x40000000 + SZ_16K - 1, .flags = IORESOURCE_MEM, + }, { + .name = "nand_addr", + .start = 0x40000000 + ALE_OFF, + .end = 0x40000000 +ALE_OFF + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "nand_cmd", + .start = 0x40000000 + CLE_OFF, + .end = 0x40000000 + CLE_OFF + SZ_16K - 1, + .flags = IORESOURCE_MEM, }, { .name = "fsmc_regs", .start = NOMADIK_FSMC_BASE, @@ -105,8 +116,6 @@ static struct fsmc_nand_platform_data nhk8815_nand_platform_data = { .partitions = nhk8815_partitions, .nr_partitions = ARRAY_SIZE(nhk8815_partitions), .width = FSMC_NAND_BW8, - .ale_off = 0x1000000, - .cle_off = 0x800000, }; static struct platform_device nhk8815_nand_device = { @@ -171,6 +180,10 @@ static struct platform_device nhk8815_onenand_device = { .num_resources = ARRAY_SIZE(nhk8815_onenand_resource), }; +/* bus control reg. and bus timing reg. for CS0..CS3 */ +#define FSMC_BCR(x) (NOMADIK_FSMC_VA + (x << 3)) +#define FSMC_BTR(x) (NOMADIK_FSMC_VA + (x << 3) + 0x04) + static void __init nhk8815_onenand_init(void) { #ifdef CONFIG_MTD_ONENAND -- cgit v1.2.3-70-g09d2 From 06e9eff129ec4251e5335ecaebe1aabba78091b6 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 25 Oct 2012 18:23:54 +0200 Subject: ARM: dts: cfa10049: Add the i2c muxer buses to the CFA-10049 This will allow to add the 3 Nuvoton NAU7802 ADCs and the NXP PCA9555 GPIO expander eventually. Signed-off-by: Maxime Ripard Acked-by: Shawn Guo Signed-off-by: Wolfram Sang --- arch/arm/boot/dts/imx28-cfa10049.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 05c892e931e..319a6dbd934 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -70,6 +70,30 @@ status = "okay"; }; + i2cmux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + mux-gpios = <&gpio1 22 0 &gpio1 23 0>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + }; + + i2c@1 { + reg = <1>; + }; + + i2c@2 { + reg = <2>; + }; + + i2c@3 { + reg = <3>; + }; + }; + usbphy1: usbphy@8007e000 { status = "okay"; }; -- cgit v1.2.3-70-g09d2 From 5d346d103355a0ea1ccc40b7ac0659326cb74077 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Thu, 25 Oct 2012 18:31:42 -0600 Subject: sparc: dma-mapping: support debug_dma_mapping_error Add support for debug_dma_mapping_error() call to avoid warning from debug_dma_unmap() interface when it checks for mapping error checked status. Without this patch, device driver failed to check map error warning is generated. Signed-off-by: Shuah Khan Acked-by: David S. Miller Signed-off-by: Joerg Roedel --- arch/sparc/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sparc/include/asm/dma-mapping.h b/arch/sparc/include/asm/dma-mapping.h index 8493fd3c7ba..05fe53f5346 100644 --- a/arch/sparc/include/asm/dma-mapping.h +++ b/arch/sparc/include/asm/dma-mapping.h @@ -59,6 +59,7 @@ static inline void dma_free_attrs(struct device *dev, size_t size, static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { + debug_dma_mapping_error(dev, dma_addr); return (dma_addr == DMA_ERROR_CODE); } -- cgit v1.2.3-70-g09d2 From 0857ba3c24c308f42a242fe8a1894772750230ce Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Sun, 18 Nov 2012 18:36:19 +0200 Subject: i2c: i2c-cbus-gpio: introduce driver Add i2c driver to enable access to devices behind CBUS on Nokia Internet Tablets. The patch also adds CBUS I2C configuration for N8x0 which is one of the users of this driver. Acked-by: Felipe Balbi Acked-by: Tony Lindgren Signed-off-by: Aaro Koskinen Signed-off-by: Wolfram Sang --- .../devicetree/bindings/i2c/i2c-cbus-gpio.txt | 27 ++ arch/arm/mach-omap2/board-n8x0.c | 42 +++ drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-cbus-gpio.c | 300 +++++++++++++++++++++ include/linux/platform_data/i2c-cbus-gpio.h | 27 ++ 6 files changed, 407 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt create mode 100644 drivers/i2c/busses/i2c-cbus-gpio.c create mode 100644 include/linux/platform_data/i2c-cbus-gpio.h (limited to 'arch') diff --git a/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt new file mode 100644 index 00000000000..8ce9cd2855b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-cbus-gpio.txt @@ -0,0 +1,27 @@ +Device tree bindings for i2c-cbus-gpio driver + +Required properties: + - compatible = "i2c-cbus-gpio"; + - gpios: clk, dat, sel + - #address-cells = <1>; + - #size-cells = <0>; + +Optional properties: + - child nodes conforming to i2c bus binding + +Example: + +i2c@0 { + compatible = "i2c-cbus-gpio"; + gpios = <&gpio 66 0 /* clk */ + &gpio 65 0 /* dat */ + &gpio 64 0 /* sel */ + >; + #address-cells = <1>; + #size-cells = <0>; + + retu-mfd: retu@1 { + compatible = "retu-mfd"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c index d95f727ca39..bbfd74263c4 100644 --- a/arch/arm/mach-omap2/board-n8x0.c +++ b/arch/arm/mach-omap2/board-n8x0.c @@ -16,10 +16,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -39,6 +41,45 @@ #define TUSB6010_GPIO_ENABLE 0 #define TUSB6010_DMACHAN 0x3f +#if defined(CONFIG_I2C_CBUS_GPIO) || defined(CONFIG_I2C_CBUS_GPIO_MODULE) +static struct i2c_cbus_platform_data n8x0_cbus_data = { + .clk_gpio = 66, + .dat_gpio = 65, + .sel_gpio = 64, +}; + +static struct platform_device n8x0_cbus_device = { + .name = "i2c-cbus-gpio", + .id = 3, + .dev = { + .platform_data = &n8x0_cbus_data, + }, +}; + +static struct i2c_board_info n8x0_i2c_board_info_3[] __initdata = { + { + I2C_BOARD_INFO("retu-mfd", 0x01), + }, +}; + +static void __init n8x0_cbus_init(void) +{ + const int retu_irq_gpio = 108; + + if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ")) + return; + irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING); + n8x0_i2c_board_info_3[0].irq = gpio_to_irq(retu_irq_gpio); + i2c_register_board_info(3, n8x0_i2c_board_info_3, + ARRAY_SIZE(n8x0_i2c_board_info_3)); + platform_device_register(&n8x0_cbus_device); +} +#else /* CONFIG_I2C_CBUS_GPIO */ +static void __init n8x0_cbus_init(void) +{ +} +#endif /* CONFIG_I2C_CBUS_GPIO */ + #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) /* * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and @@ -677,6 +718,7 @@ static void __init n8x0_init_machine(void) gpmc_onenand_init(board_onenand_data); n8x0_mmc_init(); n8x0_usb_init(); + n8x0_cbus_init(); } MACHINE_START(NOKIA_N800, "Nokia N800") diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index e9df4612b7e..e949edf644d 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -337,6 +337,16 @@ config I2C_BLACKFIN_TWI_CLK_KHZ help The unit of the TWI clock is kHz. +config I2C_CBUS_GPIO + tristate "CBUS I2C driver" + depends on GENERIC_GPIO + help + Support for CBUS access using I2C API. Mostly relevant for Nokia + Internet Tablets (770, N800 and N810). + + This driver can also be built as a module. If so, the module + will be called i2c-cbus-gpio. + config I2C_CPM tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" depends on (CPM1 || CPM2) && OF_I2C diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 395b516ffa0..f9e3e0b5c82 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o obj-$(CONFIG_I2C_AT91) += i2c-at91.o obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o +obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o obj-$(CONFIG_I2C_CPM) += i2c-cpm.o obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c new file mode 100644 index 00000000000..98386d65931 --- /dev/null +++ b/drivers/i2c/busses/i2c-cbus-gpio.c @@ -0,0 +1,300 @@ +/* + * CBUS I2C driver for Nokia Internet Tablets. + * + * Copyright (C) 2004-2010 Nokia Corporation + * + * Based on code written by Juha Yrjölä, David Weinehall, Mikko Ylinen and + * Felipe Balbi. Converted to I2C driver by Aaro Koskinen. + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of this + * archive for more details. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Bit counts are derived from Nokia implementation. These should be checked + * if other CBUS implementations appear. + */ +#define CBUS_ADDR_BITS 3 +#define CBUS_REG_BITS 5 + +struct cbus_host { + spinlock_t lock; /* host lock */ + struct device *dev; + int clk_gpio; + int dat_gpio; + int sel_gpio; +}; + +/** + * cbus_send_bit - sends one bit over the bus + * @host: the host we're using + * @bit: one bit of information to send + */ +static void cbus_send_bit(struct cbus_host *host, unsigned bit) +{ + gpio_set_value(host->dat_gpio, bit ? 1 : 0); + gpio_set_value(host->clk_gpio, 1); + gpio_set_value(host->clk_gpio, 0); +} + +/** + * cbus_send_data - sends @len amount of data over the bus + * @host: the host we're using + * @data: the data to send + * @len: size of the transfer + */ +static void cbus_send_data(struct cbus_host *host, unsigned data, unsigned len) +{ + int i; + + for (i = len; i > 0; i--) + cbus_send_bit(host, data & (1 << (i - 1))); +} + +/** + * cbus_receive_bit - receives one bit from the bus + * @host: the host we're using + */ +static int cbus_receive_bit(struct cbus_host *host) +{ + int ret; + + gpio_set_value(host->clk_gpio, 1); + ret = gpio_get_value(host->dat_gpio); + gpio_set_value(host->clk_gpio, 0); + return ret; +} + +/** + * cbus_receive_word - receives 16-bit word from the bus + * @host: the host we're using + */ +static int cbus_receive_word(struct cbus_host *host) +{ + int ret = 0; + int i; + + for (i = 16; i > 0; i--) { + int bit = cbus_receive_bit(host); + + if (bit < 0) + return bit; + + if (bit) + ret |= 1 << (i - 1); + } + return ret; +} + +/** + * cbus_transfer - transfers data over the bus + * @host: the host we're using + * @rw: read/write flag + * @dev: device address + * @reg: register address + * @data: if @rw == I2C_SBUS_WRITE data to send otherwise 0 + */ +static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev, + unsigned reg, unsigned data) +{ + unsigned long flags; + int ret; + + /* We don't want interrupts disturbing our transfer */ + spin_lock_irqsave(&host->lock, flags); + + /* Reset state and start of transfer, SEL stays down during transfer */ + gpio_set_value(host->sel_gpio, 0); + + /* Set the DAT pin to output */ + gpio_direction_output(host->dat_gpio, 1); + + /* Send the device address */ + cbus_send_data(host, dev, CBUS_ADDR_BITS); + + /* Send the rw flag */ + cbus_send_bit(host, rw == I2C_SMBUS_READ); + + /* Send the register address */ + cbus_send_data(host, reg, CBUS_REG_BITS); + + if (rw == I2C_SMBUS_WRITE) { + cbus_send_data(host, data, 16); + ret = 0; + } else { + ret = gpio_direction_input(host->dat_gpio); + if (ret) { + dev_dbg(host->dev, "failed setting direction\n"); + goto out; + } + gpio_set_value(host->clk_gpio, 1); + + ret = cbus_receive_word(host); + if (ret < 0) { + dev_dbg(host->dev, "failed receiving data\n"); + goto out; + } + } + + /* Indicate end of transfer, SEL goes up until next transfer */ + gpio_set_value(host->sel_gpio, 1); + gpio_set_value(host->clk_gpio, 1); + gpio_set_value(host->clk_gpio, 0); + +out: + spin_unlock_irqrestore(&host->lock, flags); + + return ret; +} + +static int cbus_i2c_smbus_xfer(struct i2c_adapter *adapter, + u16 addr, + unsigned short flags, + char read_write, + u8 command, + int size, + union i2c_smbus_data *data) +{ + struct cbus_host *chost = i2c_get_adapdata(adapter); + int ret; + + if (size != I2C_SMBUS_WORD_DATA) + return -EINVAL; + + ret = cbus_transfer(chost, read_write == I2C_SMBUS_READ, addr, + command, data->word); + if (ret < 0) + return ret; + + if (read_write == I2C_SMBUS_READ) + data->word = ret; + + return 0; +} + +static u32 cbus_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA; +} + +static const struct i2c_algorithm cbus_i2c_algo = { + .smbus_xfer = cbus_i2c_smbus_xfer, + .functionality = cbus_i2c_func, +}; + +static int cbus_i2c_remove(struct platform_device *pdev) +{ + struct i2c_adapter *adapter = platform_get_drvdata(pdev); + + return i2c_del_adapter(adapter); +} + +static int cbus_i2c_probe(struct platform_device *pdev) +{ + struct i2c_adapter *adapter; + struct cbus_host *chost; + int ret; + + adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), + GFP_KERNEL); + if (!adapter) + return -ENOMEM; + + chost = devm_kzalloc(&pdev->dev, sizeof(*chost), GFP_KERNEL); + if (!chost) + return -ENOMEM; + + if (pdev->dev.of_node) { + struct device_node *dnode = pdev->dev.of_node; + if (of_gpio_count(dnode) != 3) + return -ENODEV; + chost->clk_gpio = of_get_gpio(dnode, 0); + chost->dat_gpio = of_get_gpio(dnode, 1); + chost->sel_gpio = of_get_gpio(dnode, 2); + } else if (pdev->dev.platform_data) { + struct i2c_cbus_platform_data *pdata = pdev->dev.platform_data; + chost->clk_gpio = pdata->clk_gpio; + chost->dat_gpio = pdata->dat_gpio; + chost->sel_gpio = pdata->sel_gpio; + } else { + return -ENODEV; + } + + adapter->owner = THIS_MODULE; + adapter->class = I2C_CLASS_HWMON; + adapter->dev.parent = &pdev->dev; + adapter->nr = pdev->id; + adapter->timeout = HZ; + adapter->algo = &cbus_i2c_algo; + strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name)); + + spin_lock_init(&chost->lock); + chost->dev = &pdev->dev; + + ret = devm_gpio_request_one(&pdev->dev, chost->clk_gpio, + GPIOF_OUT_INIT_LOW, "CBUS clk"); + if (ret) + return ret; + + ret = devm_gpio_request_one(&pdev->dev, chost->dat_gpio, GPIOF_IN, + "CBUS data"); + if (ret) + return ret; + + ret = devm_gpio_request_one(&pdev->dev, chost->sel_gpio, + GPIOF_OUT_INIT_HIGH, "CBUS sel"); + if (ret) + return ret; + + i2c_set_adapdata(adapter, chost); + platform_set_drvdata(pdev, adapter); + + return i2c_add_numbered_adapter(adapter); +} + +#if defined(CONFIG_OF) +static const struct of_device_id i2c_cbus_dt_ids[] = { + { .compatible = "i2c-cbus-gpio", }, + { } +}; +MODULE_DEVICE_TABLE(of, i2c_cbus_dt_ids); +#endif + +static struct platform_driver cbus_i2c_driver = { + .probe = cbus_i2c_probe, + .remove = cbus_i2c_remove, + .driver = { + .owner = THIS_MODULE, + .name = "i2c-cbus-gpio", + }, +}; +module_platform_driver(cbus_i2c_driver); + +MODULE_ALIAS("platform:i2c-cbus-gpio"); +MODULE_DESCRIPTION("CBUS I2C driver"); +MODULE_AUTHOR("Juha Yrjölä"); +MODULE_AUTHOR("David Weinehall"); +MODULE_AUTHOR("Mikko Ylinen"); +MODULE_AUTHOR("Felipe Balbi"); +MODULE_AUTHOR("Aaro Koskinen "); +MODULE_LICENSE("GPL"); diff --git a/include/linux/platform_data/i2c-cbus-gpio.h b/include/linux/platform_data/i2c-cbus-gpio.h new file mode 100644 index 00000000000..6faa992a950 --- /dev/null +++ b/include/linux/platform_data/i2c-cbus-gpio.h @@ -0,0 +1,27 @@ +/* + * i2c-cbus-gpio.h - CBUS I2C platform_data definition + * + * Copyright (C) 2004-2009 Nokia Corporation + * + * Written by Felipe Balbi and Aaro Koskinen. + * + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of this + * archive for more details. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __INCLUDE_LINUX_I2C_CBUS_GPIO_H +#define __INCLUDE_LINUX_I2C_CBUS_GPIO_H + +struct i2c_cbus_platform_data { + int dat_gpio; + int clk_gpio; + int sel_gpio; +}; + +#endif /* __INCLUDE_LINUX_I2C_CBUS_GPIO_H */ -- cgit v1.2.3-70-g09d2 From 506ee557b75d4e77f4876ca4189cb855397d617b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Tue, 20 Nov 2012 00:26:17 -0800 Subject: OMAP: nokia770: remove custom implementation of ads7846_get_pendown_state The default implementation matches exactly our custom one so we can switch to using the default one. As a bonus the driver will take care of setting GPIO line for us. Tested-by: Aaro Koskinen Acked-by: Tony Lindgren Signed-off-by: Dmitry Torokhov --- arch/arm/mach-omap1/board-nokia770.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7d5c06d6a52..be6490b5eb2 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c @@ -112,17 +112,6 @@ static void __init mipid_dev_init(void) omapfb_set_lcd_config(&nokia770_lcd_config); } -static void __init ads7846_dev_init(void) -{ - if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0) - printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); -} - -static int ads7846_get_pendown_state(void) -{ - return !gpio_get_value(ADS7846_PENDOWN_GPIO); -} - static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = { .x_max = 0x0fff, .y_max = 0x0fff, @@ -131,7 +120,7 @@ static struct ads7846_platform_data nokia770_ads7846_platform_data __initdata = .debounce_max = 10, .debounce_tol = 3, .debounce_rep = 1, - .get_pendown_state = ads7846_get_pendown_state, + .gpio_pendown = ADS7846_PENDOWN_GPIO, }; static struct spi_board_info nokia770_spi_board_info[] __initdata = { @@ -241,7 +230,6 @@ static void __init omap_nokia770_init(void) omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); hwa742_dev_init(); - ads7846_dev_init(); mipid_dev_init(); omap1_usb_init(&nokia770_usb_config); nokia770_mmc_init(); -- cgit v1.2.3-70-g09d2 From 9c63a650bb100e7553d60c991ba0c5db9c743239 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Wed, 31 Oct 2012 01:29:52 -0400 Subject: tools/power/x86/turbostat: share kernel MSR #defines Now that turbostat is built in the kernel tree, it can share MSR #defines with the kernel. Signed-off-by: Len Brown Cc: x86@kernel.org --- arch/x86/include/asm/msr-index.h | 14 ++++++++++++++ tools/power/x86/turbostat/Makefile | 1 + tools/power/x86/turbostat/turbostat.c | 26 +++++++------------------- 3 files changed, 22 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 7f0edceb756..2639f816628 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -35,11 +35,14 @@ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd +#define MSR_NHM_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) +#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) +#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 @@ -55,6 +58,8 @@ #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 +#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad +#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 @@ -103,6 +108,15 @@ #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +/* C-state Residency Counters */ +#define MSR_PKG_C3_RESIDENCY 0x000003f8 +#define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_PKG_C7_RESIDENCY 0x000003fa +#define MSR_CORE_C3_RESIDENCY 0x000003fc +#define MSR_CORE_C6_RESIDENCY 0x000003fd +#define MSR_CORE_C7_RESIDENCY 0x000003fe +#define MSR_PKG_C2_RESIDENCY 0x0000060d + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) diff --git a/tools/power/x86/turbostat/Makefile b/tools/power/x86/turbostat/Makefile index f8564955419..51880e8467b 100644 --- a/tools/power/x86/turbostat/Makefile +++ b/tools/power/x86/turbostat/Makefile @@ -1,5 +1,6 @@ turbostat : turbostat.c CFLAGS += -Wall +CFLAGS += -I../../../../arch/x86/include/ clean : rm -f turbostat diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index ea095abbe97..3c063a00f3b 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -20,6 +20,7 @@ */ #define _GNU_SOURCE +#include #include #include #include @@ -35,19 +36,6 @@ #include #include -#define MSR_NEHALEM_PLATFORM_INFO 0xCE -#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1AD -#define MSR_IVT_TURBO_RATIO_LIMIT 0x1AE -#define MSR_APERF 0xE8 -#define MSR_MPERF 0xE7 -#define MSR_PKG_C2_RESIDENCY 0x60D /* SNB only */ -#define MSR_PKG_C3_RESIDENCY 0x3F8 -#define MSR_PKG_C6_RESIDENCY 0x3F9 -#define MSR_PKG_C7_RESIDENCY 0x3FA /* SNB only */ -#define MSR_CORE_C3_RESIDENCY 0x3FC -#define MSR_CORE_C6_RESIDENCY 0x3FD -#define MSR_CORE_C7_RESIDENCY 0x3FE /* SNB only */ - char *proc_stat = "/proc/stat"; unsigned int interval_sec = 5; /* set with -i interval_sec */ unsigned int verbose; /* set with -v */ @@ -674,9 +662,9 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) t->tsc = rdtsc(); /* we are running on local CPU of interest */ if (has_aperf) { - if (get_msr(cpu, MSR_APERF, &t->aperf)) + if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) return -3; - if (get_msr(cpu, MSR_MPERF, &t->mperf)) + if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) return -4; } @@ -742,10 +730,10 @@ void print_verbose_header(void) if (!do_nehalem_platform_info) return; - get_msr(0, MSR_NEHALEM_PLATFORM_INFO, &msr); + get_msr(0, MSR_NHM_PLATFORM_INFO, &msr); if (verbose > 1) - fprintf(stderr, "MSR_NEHALEM_PLATFORM_INFO: 0x%llx\n", msr); + fprintf(stderr, "MSR_NHM_PLATFORM_INFO: 0x%llx\n", msr); ratio = (msr >> 40) & 0xFF; fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency\n", @@ -808,10 +796,10 @@ print_nhm_turbo_ratio_limits: if (!do_nehalem_turbo_ratio_limit) return; - get_msr(0, MSR_NEHALEM_TURBO_RATIO_LIMIT, &msr); + get_msr(0, MSR_NHM_TURBO_RATIO_LIMIT, &msr); if (verbose > 1) - fprintf(stderr, "MSR_NEHALEM_TURBO_RATIO_LIMIT: 0x%llx\n", msr); + fprintf(stderr, "MSR_NHM_TURBO_RATIO_LIMIT: 0x%llx\n", msr); ratio = (msr >> 56) & 0xFF; if (ratio) -- cgit v1.2.3-70-g09d2 From 3fc808aaa052dec7b155f3242c6c0eabf0c49127 Mon Sep 17 00:00:00 2001 From: Len Brown Date: Wed, 31 Oct 2012 20:47:40 -0400 Subject: x86 power: define RAPL MSRs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Run Time Average Power Limiting interface is currently model specific, present on Sandy Bridge and Ivy Bridge processors. These #defines correspond to documentation in the latest "Intel® 64 and IA-32 Architectures Software Developer Manual", plus some typos in that document corrected. Signed-off-by: Len Brown Cc: x86@kernel.org --- arch/x86/include/asm/msr-index.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2639f816628..4a4abaea04d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -117,6 +117,29 @@ #define MSR_CORE_C7_RESIDENCY 0x000003fe #define MSR_PKG_C2_RESIDENCY 0x0000060d +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) -- cgit v1.2.3-70-g09d2 From e9c36b0b09f29f4edefa5bfcbc7247bb8419edce Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Tue, 20 Nov 2012 10:01:51 +0530 Subject: powerpc/85xx: p1022ds: Use NULL instead of 0 for pointers The third argument for of_get_property() is a pointer, hence pass NULL instead of 0. Signed-off-by: Tushar Behera Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/p1022_ds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c index 8fb12570b2f..7328b8d7412 100644 --- a/arch/powerpc/platforms/85xx/p1022_ds.c +++ b/arch/powerpc/platforms/85xx/p1022_ds.c @@ -249,7 +249,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) goto exit; } - iprop = of_get_property(law_node, "fsl,num-laws", 0); + iprop = of_get_property(law_node, "fsl,num-laws", NULL); if (!iprop) { pr_err("p1022ds: LAW node is missing fsl,num-laws property\n"); goto exit; -- cgit v1.2.3-70-g09d2 From b567d1c74ecfe4c321bdba251506a95e4c837c86 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 15 Oct 2012 14:52:21 -0500 Subject: powerpc/86xx: fsl_pcibios_fixup_bus requires CONFIG_PCI Function fsl_pcibios_fixup_bus() is available only if PCI is enabled. The MPC8610 HPCD platform file was not protecting the assigned with an #ifdef, which results in a link failure when PCI is disabled. Every other platform already has this #ifdef. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c index a817398a56d..04d9d317f74 100644 --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c @@ -353,5 +353,7 @@ define_machine(mpc86xx_hpcd) { .time_init = mpc86xx_time_init, .calibrate_decr = generic_calibrate_decr, .progress = udbg_progress, +#ifdef CONFIG_PCI .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif }; -- cgit v1.2.3-70-g09d2 From a393d8977acd834520357f951bb28ef46ee7db0a Mon Sep 17 00:00:00 2001 From: Jia Hongtao Date: Thu, 8 Nov 2012 10:11:07 +0800 Subject: powerpc/fsl-pci: Add PCI controller ATMU PM support Power supply for PCI controller ATMU registers is off when system go to deep-sleep state. So ATMU registers should be re-setup during PCI controllers resume from sleep. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- arch/powerpc/sysdev/fsl_pci.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index ffb93ae9379..b96885b4e99 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -89,7 +89,7 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) return 0; } -static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, +static int setup_one_atmu(struct ccsr_pci __iomem *pci, unsigned int index, const struct resource *res, resource_size_t offset) { @@ -126,7 +126,7 @@ static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, } /* atmu setup for fsl pci/pcie controller */ -static void __init setup_pci_atmu(struct pci_controller *hose, +static void setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc) { struct ccsr_pci __iomem *pci; @@ -902,9 +902,42 @@ static int __devinit fsl_pci_probe(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int fsl_pci_resume(struct device *dev) +{ + struct pci_controller *hose; + struct resource pci_rsrc; + + hose = pci_find_hose_for_OF_device(dev->of_node); + if (!hose) + return -ENODEV; + + if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) { + dev_err(dev, "Get pci register base failed."); + return -ENODEV; + } + + setup_pci_atmu(hose, &pci_rsrc); + + return 0; +} + +static const struct dev_pm_ops pci_pm_ops = { + .resume = fsl_pci_resume, +}; + +#define PCI_PM_OPS (&pci_pm_ops) + +#else + +#define PCI_PM_OPS NULL + +#endif + static struct platform_driver fsl_pci_driver = { .driver = { .name = "fsl-pci", + .pm = PCI_PM_OPS, .of_match_table = pci_ids, }, .probe = fsl_pci_probe, -- cgit v1.2.3-70-g09d2 From bc15236fbed1e017b465e38a9d2092393778a2f7 Mon Sep 17 00:00:00 2001 From: York Sun Date: Sat, 29 Sep 2012 16:44:35 -0700 Subject: powerpc/mpc85xx: Change spin table to cached memory ePAPR v1.1 requires the spin table to be in cached memory. So we need to change the call argument of ioremap to enable cache and coherence. We also flush the cache after writing to spin table to keep it compatible with previous cache-inhibit spin table. Flushing before and after accessing spin table is recommended by ePAPR. Signed-off-by: York Sun Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/platforms/85xx/smp.c | 49 ++++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 6fcfa12e5c5..148c2f2d978 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -128,6 +128,19 @@ static void __cpuinit smp_85xx_mach_cpu_die(void) } #endif +static inline void flush_spin_table(void *spin_table) +{ + flush_dcache_range((ulong)spin_table, + (ulong)spin_table + sizeof(struct epapr_spin_table)); +} + +static inline u32 read_spin_table_addr_l(void *spin_table) +{ + flush_dcache_range((ulong)spin_table, + (ulong)spin_table + sizeof(struct epapr_spin_table)); + return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l); +} + static int __cpuinit smp_85xx_kick_cpu(int nr) { unsigned long flags; @@ -161,8 +174,8 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) /* Map the spin table */ if (ioremappable) - spin_table = ioremap(*cpu_rel_addr, - sizeof(struct epapr_spin_table)); + spin_table = ioremap_prot(*cpu_rel_addr, + sizeof(struct epapr_spin_table), _PAGE_COHERENT); else spin_table = phys_to_virt(*cpu_rel_addr); @@ -173,7 +186,16 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) generic_set_cpu_up(nr); if (system_state == SYSTEM_RUNNING) { + /* + * To keep it compatible with old boot program which uses + * cache-inhibit spin table, we need to flush the cache + * before accessing spin table to invalidate any staled data. + * We also need to flush the cache after writing to spin + * table to push data out. + */ + flush_spin_table(spin_table); out_be32(&spin_table->addr_l, 0); + flush_spin_table(spin_table); /* * We don't set the BPTR register here since it already points @@ -181,9 +203,14 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) */ mpic_reset_core(hw_cpu); - /* wait until core is ready... */ - if (!spin_event_timeout(in_be32(&spin_table->addr_l) == 1, - 10000, 100)) { + /* + * wait until core is ready... + * We need to invalidate the stale data, in case the boot + * loader uses a cache-inhibited spin table. + */ + if (!spin_event_timeout( + read_spin_table_addr_l(spin_table) == 1, + 10000, 100)) { pr_err("%s: timeout waiting for core %d to reset\n", __func__, hw_cpu); ret = -ENOENT; @@ -194,12 +221,10 @@ static int __cpuinit smp_85xx_kick_cpu(int nr) __secondary_hold_acknowledge = -1; } #endif + flush_spin_table(spin_table); out_be32(&spin_table->pir, hw_cpu); out_be32(&spin_table->addr_l, __pa(__early_start)); - - if (!ioremappable) - flush_dcache_range((ulong)spin_table, - (ulong)spin_table + sizeof(struct epapr_spin_table)); + flush_spin_table(spin_table); /* Wait a bit for the CPU to ack. */ if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu, @@ -213,13 +238,11 @@ out: #else smp_generic_kick_cpu(nr); + flush_spin_table(spin_table); out_be32(&spin_table->pir, hw_cpu); out_be64((u64 *)(&spin_table->addr_h), __pa((u64)*((unsigned long long *)generic_secondary_smp_init))); - - if (!ioremappable) - flush_dcache_range((ulong)spin_table, - (ulong)spin_table + sizeof(struct epapr_spin_table)); + flush_spin_table(spin_table); #endif local_irq_restore(flags); -- cgit v1.2.3-70-g09d2 From 5320b50797a9a5373f31f5b1c26346357f73e179 Mon Sep 17 00:00:00 2001 From: Varun Sethi Date: Tue, 20 Nov 2012 19:24:55 +0530 Subject: powerpc/iommu/fsl: Add PAMU bypass enable register to ccsr_guts struct PAMU bypass enable register added to the ccsr_guts structure. Signed-off-by: Timur Tabi Signed-off-by: Varun Sethi Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/fsl_guts.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h index dd5ba2c2277..77ced0b3d81 100644 --- a/arch/powerpc/include/asm/fsl_guts.h +++ b/arch/powerpc/include/asm/fsl_guts.h @@ -71,7 +71,9 @@ struct ccsr_guts { u8 res0c4[0x224 - 0xc4]; __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ - u8 res22c[0x800 - 0x22c]; + u8 res22c[0x604 - 0x22c]; + __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ + u8 res608[0x800 - 0x608]; __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ u8 res804[0x900 - 0x804]; __be32 ircr; /* 0x.0900 - Infrared Control Register */ -- cgit v1.2.3-70-g09d2 From 1723d90915d4689fa2e8cd4151d45ea38c96cb99 Mon Sep 17 00:00:00 2001 From: Xuelin Shi Date: Wed, 21 Nov 2012 17:01:20 +0800 Subject: powerpc/dma/raidengine: add raidengine device The RaidEngine is a new Freescale hardware that used for parity computation offloading in RAID5/6. This patch adds the device node in device tree and related binding documentation. Signed-off-by: Harninder Rai Signed-off-by: Naveen Burmi Signed-off-by: Xuelin Shi Signed-off-by: Kumar Gala --- .../devicetree/bindings/powerpc/fsl/raideng.txt | 81 +++++++++++++++++++++ arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 1 + arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 6 ++ arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi | 85 ++++++++++++++++++++++ 4 files changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/raideng.txt create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi (limited to 'arch') diff --git a/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt b/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt new file mode 100644 index 00000000000..4ad29b9ac2a --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/raideng.txt @@ -0,0 +1,81 @@ +* Freescale 85xx RAID Engine nodes + +RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID +Engine should have a separate node. + +Supported chips: +P5020, P5040 + +Required properties: + +- compatible: Should contain "fsl,raideng-v1.0" as the value + This identifies RAID Engine block. 1 in 1.0 represents + major number whereas 0 represents minor number. The + version matches the hardware IP version. +- reg: offset and length of the register set for the device +- ranges: standard ranges property specifying the translation + between child address space and parent address space + +Example: + /* P5020 */ + raideng: raideng@320000 { + compatible = "fsl,raideng-v1.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x320000 0x10000>; + ranges = <0 0x320000 0x10000>; + }; + + +There must be a sub-node for each job queue present in RAID Engine +This node must be a sub-node of the main RAID Engine node + +- compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value + This identifies the job queue interface +- reg: offset and length of the register set for job queue +- ranges: standard ranges property specifying the translation + between child address space and parent address space + +Example: + /* P5020 */ + raideng_jq0@1000 { + compatible = "fsl,raideng-v1.0-job-queue"; + reg = <0x1000 0x1000>; + ranges = <0x0 0x1000 0x1000>; + }; + + +There must be a sub-node for each job ring present in RAID Engine +This node must be a sub-node of job queue node + +- compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value + This identifies job ring. Should contain either + "fsl,raideng-v1.0-hp-ring" or "fsl,raideng-v1.0-lp-ring" + depending upon whether ring has high or low priority +- reg: offset and length of the register set for job ring +- interrupts: interrupt mapping for job ring IRQ + +Optional property: + +- fsl,liodn: Specifies the LIODN to be used for Job Ring. This + property is normally set by firmware. Value + is of 12-bits which is the LIODN number for this JR. + This property is used by the IOMMU (PAMU) to distinquish + transactions from this JR and than be able to do address + translation & protection accordingly. + +Example: + /* P5020 */ + raideng_jq0@1000 { + compatible = "fsl,raideng-v1.0-job-queue"; + reg = <0x1000 0x1000>; + ranges = <0x0 0x1000 0x1000>; + + raideng_jr0: jr@0 { + compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; + reg = <0x0 0x400>; + interrupts = <139 2 0 0>; + interrupt-parent = <&mpic>; + fsl,liodn = <0x41>; + }; + }; diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi index 64b6abea846..5d7205b7bb0 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi @@ -354,4 +354,5 @@ /include/ "qoriq-sata2-0.dtsi" /include/ "qoriq-sata2-1.dtsi" /include/ "qoriq-sec4.2-0.dtsi" +/include/ "qoriq-raid1.0-0.dtsi" }; diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi index 0a198b0a77e..8df47fc45ab 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi @@ -73,6 +73,12 @@ rtic_c = &rtic_c; rtic_d = &rtic_d; sec_mon = &sec_mon; + + raideng = &raideng; + raideng_jr0 = &raideng_jr0; + raideng_jr1 = &raideng_jr1; + raideng_jr2 = &raideng_jr2; + raideng_jr3 = &raideng_jr3; }; cpus { diff --git a/arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi new file mode 100644 index 00000000000..8d2e8aa6cf8 --- /dev/null +++ b/arch/powerpc/boot/dts/fsl/qoriq-raid1.0-0.dtsi @@ -0,0 +1,85 @@ +/* + * QorIQ RAID 1.0 device tree stub [ controller @ offset 0x320000 ] + * + * Copyright 2012 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +raideng: raideng@320000 { + compatible = "fsl,raideng-v1.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x320000 0x10000>; + ranges = <0 0x320000 0x10000>; + + raideng_jq0@1000 { + compatible = "fsl,raideng-v1.0-job-queue"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1000 0x1000>; + ranges = <0x0 0x1000 0x1000>; + + raideng_jr0: jr@0 { + compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; + reg = <0x0 0x400>; + interrupts = <139 2 0 0>; + interrupt-parent = <&mpic>; + }; + + raideng_jr1: jr@400 { + compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; + reg = <0x400 0x400>; + interrupts = <140 2 0 0>; + interrupt-parent = <&mpic>; + }; + }; + + raideng_jq1@2000 { + compatible = "fsl,raideng-v1.0-job-queue"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2000 0x1000>; + ranges = <0x0 0x2000 0x1000>; + + raideng_jr2: jr@0 { + compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring"; + reg = <0x0 0x400>; + interrupts = <141 2 0 0>; + interrupt-parent = <&mpic>; + }; + + raideng_jr3: jr@400 { + compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring"; + reg = <0x400 0x400>; + interrupts = <142 2 0 0>; + interrupt-parent = <&mpic>; + }; + }; +}; -- cgit v1.2.3-70-g09d2 From 6eb583da959cf751eb951cc5ff488dd4e41f1b2f Mon Sep 17 00:00:00 2001 From: Sivaram Nair Date: Tue, 20 Nov 2012 09:29:16 +0200 Subject: ARM: tegra: select correct parent clk for pll_p For Tegra30, pll_p clk's parent is wrongly specified as clk_m instead of pll_ref in the tegra30_clk_init_table and this is resulting in a boot-time warning. This patch fixes this by correcting the clk init table. Signed-off-by: Sivaram Nair Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0b0a5f556d3..988549a77b6 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -102,7 +102,7 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, - { "pll_p", "clk_m", 408000000, true }, + { "pll_p", "pll_ref", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, { NULL, NULL, 0, 0}, }; -- cgit v1.2.3-70-g09d2 From 6e25e1b178ee3caf34f229bacfad5ae6780bcec6 Mon Sep 17 00:00:00 2001 From: Sivaram Nair Date: Wed, 21 Nov 2012 13:42:27 +0200 Subject: ARM: tegra: fix comment in dsib clk set_parent Since the clk framework has already taken necessary locks before calling into the arch clk ops code, no further locks are needed while setting the parent of dsib clk. This patch removes a comment that indicated otherwise, and yet did not take any locks. Signed-off-by: Sivaram Nair Signed-off-by: Stephen Warren --- arch/arm/mach-tegra/tegra30_clocks.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index e9de5dfd94e..c2102a312bc 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = { static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) { struct clk *d = clk_get_sys(NULL, "pll_d"); - /* The DSIB parent selection bit is in PLLD base - register - can not do direct r-m-w, must be - protected by PLLD lock */ + /* The DSIB parent selection bit is in PLLD base register */ tegra_clk_cfg_ex( d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); -- cgit v1.2.3-70-g09d2 From 64db3648e87dceb87ff05d83b1f408f8f691c429 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 27 Sep 2012 11:47:43 +0100 Subject: ARM: ux500: Strip out duplicate touch screen platform information We're currently carrying two 'struct bu21013_platform_device's which are identical for no apparent reason. Here we remove the extra burden and apply the same information to the two different instances of the bu21012_tp driver registration. [Dmitry Torokhov: picked it up to (hopefully) reduce merge conflict with bu21013_ts update that follows.] Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones Signed-off-by: Dmitry Torokhov --- arch/arm/mach-ux500/board-mop500-stuib.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c index 8c979770d87..564f57d5d8a 100644 --- a/arch/arm/mach-ux500/board-mop500-stuib.c +++ b/arch/arm/mach-ux500/board-mop500-stuib.c @@ -162,18 +162,6 @@ static struct bu21013_platform_device tsc_plat_device = { .y_flip = true, }; -static struct bu21013_platform_device tsc_plat2_device = { - .cs_en = bu21013_gpio_board_init, - .cs_dis = bu21013_gpio_board_exit, - .irq_read_val = bu21013_read_pin_val, - .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN), - .touch_x_max = TOUCH_XMAX, - .touch_y_max = TOUCH_YMAX, - .ext_clk = false, - .x_flip = false, - .y_flip = true, -}; - static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { { I2C_BOARD_INFO("bu21013_tp", 0x5C), @@ -181,21 +169,17 @@ static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { }, { I2C_BOARD_INFO("bu21013_tp", 0x5D), - .platform_data = &tsc_plat2_device, + .platform_data = &tsc_plat_device, }, }; void __init mop500_stuib_init(void) { - if (machine_is_hrefv60()) { + if (machine_is_hrefv60()) tsc_plat_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - tsc_plat2_device.cs_pin = HREFV60_TOUCH_RST_GPIO; - } else { + else tsc_plat_device.cs_pin = GPIO_BU21013_CS; - tsc_plat2_device.cs_pin = GPIO_BU21013_CS; - - } mop500_uib_i2c_add(0, mop500_i2c0_devices_stuib, ARRAY_SIZE(mop500_i2c0_devices_stuib)); -- cgit v1.2.3-70-g09d2 From 31fbcda71489d8cbe2b82819eaab4818524e3a49 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Fri, 28 Sep 2012 10:29:07 +0100 Subject: Input: bu21013_ts - move GPIO init and exit functions into the driver These GPIO init and exit functions have no place in platform data, they should be part of the driver instead, Acked-by: Arnd Bergmann Acked-by: Linus Walleij Signed-off-by: Lee Jones Signed-off-by: Dmitry Torokhov --- arch/arm/mach-ux500/board-mop500-stuib.c | 71 +------------------------------- drivers/input/touchscreen/bu21013_ts.c | 69 ++++++++++++++++++++++--------- include/linux/input/bu21013.h | 10 +---- 3 files changed, 53 insertions(+), 97 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ux500/board-mop500-stuib.c b/arch/arm/mach-ux500/board-mop500-stuib.c index 564f57d5d8a..7e1f294f043 100644 --- a/arch/arm/mach-ux500/board-mop500-stuib.c +++ b/arch/arm/mach-ux500/board-mop500-stuib.c @@ -77,9 +77,6 @@ static struct i2c_board_info __initdata mop500_i2c0_devices_stuib[] = { * BU21013 ROHM touchscreen interface on the STUIBs */ -/* tracks number of bu21013 devices being enabled */ -static int bu21013_devices; - #define TOUCH_GPIO_PIN 84 #define TOUCH_XMAX 384 @@ -88,73 +85,8 @@ static int bu21013_devices; #define PRCMU_CLOCK_OCR 0x1CC #define TSC_EXT_CLOCK_9_6MHZ 0x840000 -/** - * bu21013_gpio_board_init : configures the touch panel. - * @reset_pin: reset pin number - * This function can be used to configures - * the voltage and reset the touch panel controller. - */ -static int bu21013_gpio_board_init(int reset_pin) -{ - int retval = 0; - - bu21013_devices++; - if (bu21013_devices == 1) { - retval = gpio_request(reset_pin, "touchp_reset"); - if (retval) { - printk(KERN_ERR "Unable to request gpio reset_pin"); - return retval; - } - retval = gpio_direction_output(reset_pin, 1); - if (retval < 0) { - printk(KERN_ERR "%s: gpio direction failed\n", - __func__); - return retval; - } - } - - return retval; -} - -/** - * bu21013_gpio_board_exit : deconfigures the touch panel controller - * @reset_pin: reset pin number - * This function can be used to deconfigures the chip selection - * for touch panel controller. - */ -static int bu21013_gpio_board_exit(int reset_pin) -{ - int retval = 0; - - if (bu21013_devices == 1) { - retval = gpio_direction_output(reset_pin, 0); - if (retval < 0) { - printk(KERN_ERR "%s: gpio direction failed\n", - __func__); - return retval; - } - gpio_set_value(reset_pin, 0); - } - bu21013_devices--; - - return retval; -} - -/** - * bu21013_read_pin_val : get the interrupt pin value - * This function can be used to get the interrupt pin value for touch panel - * controller. - */ -static int bu21013_read_pin_val(void) -{ - return gpio_get_value(TOUCH_GPIO_PIN); -} - static struct bu21013_platform_device tsc_plat_device = { - .cs_en = bu21013_gpio_board_init, - .cs_dis = bu21013_gpio_board_exit, - .irq_read_val = bu21013_read_pin_val, - .irq = NOMADIK_GPIO_TO_IRQ(TOUCH_GPIO_PIN), + .touch_pin = TOUCH_GPIO_PIN, .touch_x_max = TOUCH_XMAX, .touch_y_max = TOUCH_YMAX, .ext_clk = false, @@ -171,7 +103,6 @@ static struct i2c_board_info __initdata u8500_i2c3_devices_stuib[] = { I2C_BOARD_INFO("bu21013_tp", 0x5D), .platform_data = &tsc_plat_device, }, - }; void __init mop500_stuib_init(void) diff --git a/drivers/input/touchscreen/bu21013_ts.c b/drivers/input/touchscreen/bu21013_ts.c index 1e8cddd06c6..c6f6a04ec67 100644 --- a/drivers/input/touchscreen/bu21013_ts.c +++ b/drivers/input/touchscreen/bu21013_ts.c @@ -14,6 +14,7 @@ #include #include #include +#include #define PEN_DOWN_INTR 0 #define MAX_FINGERS 2 @@ -148,11 +149,12 @@ struct bu21013_ts_data { struct i2c_client *client; wait_queue_head_t wait; - bool touch_stopped; const struct bu21013_platform_device *chip; struct input_dev *in_dev; - unsigned int intr_pin; struct regulator *regulator; + unsigned int irq; + unsigned int intr_pin; + bool touch_stopped; }; /** @@ -262,7 +264,7 @@ static irqreturn_t bu21013_gpio_irq(int irq, void *device_data) return IRQ_NONE; } - data->intr_pin = data->chip->irq_read_val(); + data->intr_pin = gpio_get_value(data->chip->touch_pin); if (data->intr_pin == PEN_DOWN_INTR) wait_event_timeout(data->wait, data->touch_stopped, msecs_to_jiffies(2)); @@ -418,9 +420,32 @@ static void bu21013_free_irq(struct bu21013_ts_data *bu21013_data) { bu21013_data->touch_stopped = true; wake_up(&bu21013_data->wait); - free_irq(bu21013_data->chip->irq, bu21013_data); + free_irq(bu21013_data->irq, bu21013_data); } +/** + * bu21013_cs_disable() - deconfigures the touch panel controller + * @bu21013_data: device structure pointer + * + * This function is used to deconfigure the chip selection + * for touch panel controller. + */ +static void bu21013_cs_disable(struct bu21013_ts_data *bu21013_data) +{ + int error; + + error = gpio_direction_output(bu21013_data->chip->cs_pin, 0); + if (error < 0) + dev_warn(&bu21013_data->client->dev, + "%s: gpio direction failed, error: %d\n", + __func__, error); + else + gpio_set_value(bu21013_data->chip->cs_pin, 0); + + gpio_free(bu21013_data->chip->cs_pin); +} + + /** * bu21013_probe() - initializes the i2c-client touchscreen driver * @client: i2c client structure pointer @@ -430,7 +455,7 @@ static void bu21013_free_irq(struct bu21013_ts_data *bu21013_data) * driver and returns integer. */ static int bu21013_probe(struct i2c_client *client, - const struct i2c_device_id *id) + const struct i2c_device_id *id) { struct bu21013_ts_data *bu21013_data; struct input_dev *in_dev; @@ -449,6 +474,11 @@ static int bu21013_probe(struct i2c_client *client, return -EINVAL; } + if (!gpio_is_valid(pdata->touch_pin)) { + dev_err(&client->dev, "invalid touch_pin supplied\n"); + return -EINVAL; + } + bu21013_data = kzalloc(sizeof(struct bu21013_ts_data), GFP_KERNEL); in_dev = input_allocate_device(); if (!bu21013_data || !in_dev) { @@ -460,6 +490,7 @@ static int bu21013_probe(struct i2c_client *client, bu21013_data->in_dev = in_dev; bu21013_data->chip = pdata; bu21013_data->client = client; + bu21013_data->irq = gpio_to_irq(pdata->touch_pin); bu21013_data->regulator = regulator_get(&client->dev, "avdd"); if (IS_ERR(bu21013_data->regulator)) { @@ -478,12 +509,11 @@ static int bu21013_probe(struct i2c_client *client, init_waitqueue_head(&bu21013_data->wait); /* configure the gpio pins */ - if (pdata->cs_en) { - error = pdata->cs_en(pdata->cs_pin); - if (error < 0) { - dev_err(&client->dev, "chip init failed\n"); - goto err_disable_regulator; - } + error = gpio_request_one(pdata->cs_pin, GPIOF_OUT_INIT_HIGH, + "touchp_reset"); + if (error < 0) { + dev_err(&client->dev, "Unable to request gpio reset_pin\n"); + goto err_disable_regulator; } /* configure the touch panel controller */ @@ -508,12 +538,13 @@ static int bu21013_probe(struct i2c_client *client, pdata->touch_y_max, 0, 0); input_set_drvdata(in_dev, bu21013_data); - error = request_threaded_irq(pdata->irq, NULL, bu21013_gpio_irq, + error = request_threaded_irq(bu21013_data->irq, NULL, bu21013_gpio_irq, IRQF_TRIGGER_FALLING | IRQF_SHARED | IRQF_ONESHOT, DRIVER_TP, bu21013_data); if (error) { - dev_err(&client->dev, "request irq %d failed\n", pdata->irq); + dev_err(&client->dev, "request irq %d failed\n", + bu21013_data->irq); goto err_cs_disable; } @@ -531,7 +562,7 @@ static int bu21013_probe(struct i2c_client *client, err_free_irq: bu21013_free_irq(bu21013_data); err_cs_disable: - pdata->cs_dis(pdata->cs_pin); + bu21013_cs_disable(bu21013_data); err_disable_regulator: regulator_disable(bu21013_data->regulator); err_put_regulator: @@ -555,7 +586,7 @@ static int bu21013_remove(struct i2c_client *client) bu21013_free_irq(bu21013_data); - bu21013_data->chip->cs_dis(bu21013_data->chip->cs_pin); + bu21013_cs_disable(bu21013_data); input_unregister_device(bu21013_data->in_dev); @@ -584,9 +615,9 @@ static int bu21013_suspend(struct device *dev) bu21013_data->touch_stopped = true; if (device_may_wakeup(&client->dev)) - enable_irq_wake(bu21013_data->chip->irq); + enable_irq_wake(bu21013_data->irq); else - disable_irq(bu21013_data->chip->irq); + disable_irq(bu21013_data->irq); regulator_disable(bu21013_data->regulator); @@ -621,9 +652,9 @@ static int bu21013_resume(struct device *dev) bu21013_data->touch_stopped = false; if (device_may_wakeup(&client->dev)) - disable_irq_wake(bu21013_data->chip->irq); + disable_irq_wake(bu21013_data->irq); else - enable_irq(bu21013_data->chip->irq); + enable_irq(bu21013_data->irq); return 0; } diff --git a/include/linux/input/bu21013.h b/include/linux/input/bu21013.h index 05e03284b92..6230d76bde5 100644 --- a/include/linux/input/bu21013.h +++ b/include/linux/input/bu21013.h @@ -9,13 +9,10 @@ /** * struct bu21013_platform_device - Handle the platform data - * @cs_en: pointer to the cs enable function - * @cs_dis: pointer to the cs disable function - * @irq_read_val: pointer to read the pen irq value function * @touch_x_max: touch x max * @touch_y_max: touch y max * @cs_pin: chip select pin - * @irq: irq pin + * @touch_pin: touch gpio pin * @ext_clk: external clock flag * @x_flip: x flip flag * @y_flip: y flip flag @@ -24,13 +21,10 @@ * This is used to handle the platform data */ struct bu21013_platform_device { - int (*cs_en)(int reset_pin); - int (*cs_dis)(int reset_pin); - int (*irq_read_val)(void); int touch_x_max; int touch_y_max; unsigned int cs_pin; - unsigned int irq; + unsigned int touch_pin; bool ext_clk; bool x_flip; bool y_flip; -- cgit v1.2.3-70-g09d2 From 972deb4f49b5b6703d9c6117ba0aeda2180d4447 Mon Sep 17 00:00:00 2001 From: Shubhrajyoti D Date: Mon, 26 Nov 2012 15:25:11 +0530 Subject: i2c: omap: Remove the OMAP_I2C_FLAG_RESET_REGS_POSTIDLE flag The OMAP_I2C_FLAG_RESET_REGS_POSTIDLE is not used anymore in the i2c driver. Remove the flag. Signed-off-by: Shubhrajyoti D Reviewed-by: Felipe Balbi Signed-off-by: Wolfram Sang --- arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 3 +-- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 9 +++------ arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 3 +-- drivers/i2c/busses/i2c-omap.c | 3 +-- include/linux/i2c-omap.h | 1 - 5 files changed, 6 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 59d5c1cd316..c9a186bc6d4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -1103,8 +1103,7 @@ static struct omap_hwmod_class i2c_class = { }; static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, }; /* i2c1 */ diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 943222c4048..36270bb637e 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -791,8 +791,7 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = { /* I2C1 */ static struct omap_i2c_dev_attr i2c1_dev_attr = { .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, }; static struct omap_hwmod omap3xxx_i2c1_hwmod = { @@ -817,8 +816,7 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = { /* I2C2 */ static struct omap_i2c_dev_attr i2c2_dev_attr = { .fifo_depth = 8, /* bytes */ - .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, }; static struct omap_hwmod omap3xxx_i2c2_hwmod = { @@ -843,8 +841,7 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = { /* I2C3 */ static struct omap_i2c_dev_attr i2c3_dev_attr = { .fifo_depth = 64, /* bytes */ - .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, }; static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 652d0285bd6..eb40dbc6688 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -1526,8 +1526,7 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { }; static struct omap_i2c_dev_attr i2c_dev_attr = { - .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE | - OMAP_I2C_FLAG_RESET_REGS_POSTIDLE, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, }; /* i2c1 */ diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 24828013666..7a62acb7d26 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1038,8 +1038,7 @@ static const struct i2c_algorithm omap_i2c_algo = { #ifdef CONFIG_OF static struct omap_i2c_bus_platform_data omap3_pdata = { .rev = OMAP_I2C_IP_VERSION_1, - .flags = OMAP_I2C_FLAG_RESET_REGS_POSTIDLE | - OMAP_I2C_FLAG_BUS_SHIFT_2, + .flags = OMAP_I2C_FLAG_BUS_SHIFT_2, }; static struct omap_i2c_bus_platform_data omap4_pdata = { diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index 1b25c04f82d..babe0cf6d56 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -20,7 +20,6 @@ #define OMAP_I2C_FLAG_NO_FIFO BIT(0) #define OMAP_I2C_FLAG_SIMPLE_CLOCK BIT(1) #define OMAP_I2C_FLAG_16BIT_DATA_REG BIT(2) -#define OMAP_I2C_FLAG_RESET_REGS_POSTIDLE BIT(3) #define OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK BIT(5) #define OMAP_I2C_FLAG_FORCE_19200_INT_CLK BIT(6) /* how the CPU address bus must be translated for I2C unit access */ -- cgit v1.2.3-70-g09d2 From bb7c4deb82c2f0b278cdf45a392a3ed9479cdbbe Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:31:09 -0700 Subject: ARM64: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Acked-by: Catalin Marinas Signed-off-by: Joerg Roedel --- arch/arm64/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h index 538f4b44db5..99477689419 100644 --- a/arch/arm64/include/asm/dma-mapping.h +++ b/arch/arm64/include/asm/dma-mapping.h @@ -50,6 +50,7 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr) static inline int dma_mapping_error(struct device *dev, dma_addr_t dev_addr) { struct dma_map_ops *ops = get_dma_ops(dev); + debug_dma_mapping_error(dev, dev_addr); return ops->mapping_error(dev, dev_addr); } -- cgit v1.2.3-70-g09d2 From ad154880c03daf1f776e502e2c18775eda4280d2 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:32:06 -0700 Subject: c6x: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Acked-by: Mark Salter Signed-off-by: Joerg Roedel --- arch/c6x/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/c6x/include/asm/dma-mapping.h b/arch/c6x/include/asm/dma-mapping.h index 03579fd99db..3c694065030 100644 --- a/arch/c6x/include/asm/dma-mapping.h +++ b/arch/c6x/include/asm/dma-mapping.h @@ -32,6 +32,7 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask) */ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { + debug_dma_mapping_error(dev, dma_addr); return dma_addr == ~0; } -- cgit v1.2.3-70-g09d2 From 27fa0ab66f17e49a59fbca272f8c1cfab7c5fe81 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:32:55 -0700 Subject: ia64: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Joerg Roedel --- arch/ia64/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h index 4f5e8148440..cf3ab7e784b 100644 --- a/arch/ia64/include/asm/dma-mapping.h +++ b/arch/ia64/include/asm/dma-mapping.h @@ -58,6 +58,7 @@ static inline void dma_free_attrs(struct device *dev, size_t size, static inline int dma_mapping_error(struct device *dev, dma_addr_t daddr) { struct dma_map_ops *ops = platform_dma_get_ops(dev); + debug_dma_mapping_error(dev, daddr); return ops->mapping_error(dev, daddr); } -- cgit v1.2.3-70-g09d2 From e728fa18eba8bcbf1f2c4aeb21b6304a16f2f9e4 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:33:42 -0700 Subject: microblaze: dma-mapping: support debug_dma_mapping_error Add support for debug_dma_mapping_error() call to avoid warning from debug_dma_unmap() interface when it checks for mapping error checked status. Without this patch, device driver failed to check map error warning is generated. Signed-off-by: Shuah Khan Acked-by: Michal Simek Signed-off-by: Joerg Roedel --- arch/microblaze/include/asm/dma-mapping.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/microblaze/include/asm/dma-mapping.h b/arch/microblaze/include/asm/dma-mapping.h index 01d228286cb..46460f1c49c 100644 --- a/arch/microblaze/include/asm/dma-mapping.h +++ b/arch/microblaze/include/asm/dma-mapping.h @@ -114,6 +114,8 @@ static inline void __dma_sync(unsigned long paddr, static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { struct dma_map_ops *ops = get_dma_ops(dev); + + debug_dma_mapping_error(dev, dma_addr); if (ops->mapping_error) return ops->mapping_error(dev, dma_addr); -- cgit v1.2.3-70-g09d2 From 9c83b07c042361c429883b3205cbc96fd19598bd Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:34:56 -0700 Subject: mips: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Joerg Roedel --- arch/mips/include/asm/dma-mapping.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index be39a12901c..006b43e38a9 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -40,6 +40,8 @@ static inline int dma_supported(struct device *dev, u64 mask) static inline int dma_mapping_error(struct device *dev, u64 mask) { struct dma_map_ops *ops = get_dma_ops(dev); + + debug_dma_mapping_error(dev, mask); return ops->mapping_error(dev, mask); } -- cgit v1.2.3-70-g09d2 From 34daa88efd7ad46237fd1ac7e162611cc3f88acb Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:35:36 -0700 Subject: powerpc: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Joerg Roedel --- arch/powerpc/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h index 78160874809..e27e9ad6818 100644 --- a/arch/powerpc/include/asm/dma-mapping.h +++ b/arch/powerpc/include/asm/dma-mapping.h @@ -172,6 +172,7 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { struct dma_map_ops *dma_ops = get_dma_ops(dev); + debug_dma_mapping_error(dev, dma_addr); if (dma_ops->mapping_error) return dma_ops->mapping_error(dev, dma_addr); -- cgit v1.2.3-70-g09d2 From 50af1e9df2194991280463541bc89c55ca45164a Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:36:33 -0700 Subject: sh: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Joerg Roedel --- arch/sh/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h index 8bd965e00a1..b437f2c780b 100644 --- a/arch/sh/include/asm/dma-mapping.h +++ b/arch/sh/include/asm/dma-mapping.h @@ -46,6 +46,7 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { struct dma_map_ops *ops = get_dma_ops(dev); + debug_dma_mapping_error(dev, dma_addr); if (ops->mapping_error) return ops->mapping_error(dev, dma_addr); -- cgit v1.2.3-70-g09d2 From fd78a95ac662a18e94509b7314c327475cbeafb4 Mon Sep 17 00:00:00 2001 From: Shuah Khan Date: Fri, 23 Nov 2012 14:37:54 -0700 Subject: tile: dma_debug: add debug_dma_mapping_error support Add dma-debug interface debug_dma_mapping_error() to debug drivers that fail to check dma mapping errors on addresses returned by dma_map_single() and dma_map_page() interfaces. Signed-off-by: Shuah Khan Signed-off-by: Joerg Roedel --- arch/tile/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h index 4b6247d1a31..f2ff191376b 100644 --- a/arch/tile/include/asm/dma-mapping.h +++ b/arch/tile/include/asm/dma-mapping.h @@ -72,6 +72,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { + debug_dma_mapping_error(dev, dma_addr); return get_dma_ops(dev)->mapping_error(dev, dma_addr); } -- cgit v1.2.3-70-g09d2 From 72b15b6ae97796c5fac687addde5dbfab872cf94 Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Mon, 19 Nov 2012 19:05:50 -0600 Subject: iommu/omap: Migrate to hwmod framework Use hwmod data and device attributes to build and register an omap device for iommu driver. - Update the naming convention in isp module. - Remove unneeded check for number of resources, as this is now handled by omap_device and prevents driver from loading. - Now unused, remove platform device and resource data, handling of sysconfig register for softreset purposes, use default latency structure. - Use hwmod API for reset handling. Signed-off-by: Omar Ramirez Luna Tested-by: Ohad Ben-Cohen Signed-off-by: Joerg Roedel --- arch/arm/mach-omap2/devices.c | 2 +- arch/arm/mach-omap2/omap-iommu.c | 168 +++++++------------------------ drivers/iommu/omap-iommu.c | 23 ++++- drivers/iommu/omap-iommu2.c | 19 ---- include/linux/platform_data/iommu-omap.h | 8 +- 5 files changed, 64 insertions(+), 156 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index c15f5a97b51..787a996ec4e 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -214,7 +214,7 @@ static struct platform_device omap3isp_device = { }; static struct omap_iommu_arch_data omap3_isp_iommu = { - .name = "isp", + .name = "mmu_isp", }; int omap3_init_camera(struct isp_platform_data *pdata) diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index a6a4ff8744b..02726a647b1 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -12,153 +12,61 @@ #include #include +#include +#include #include +#include +#include -#include "soc.h" -#include "common.h" - -struct iommu_device { - resource_size_t base; - int irq; - struct iommu_platform_data pdata; - struct resource res[2]; -}; -static struct iommu_device *devices; -static int num_iommu_devices; - -#ifdef CONFIG_ARCH_OMAP3 -static struct iommu_device omap3_devices[] = { - { - .base = 0x480bd400, - .irq = 24 + OMAP_INTC_START, - .pdata = { - .name = "isp", - .nr_tlb_entries = 8, - .clk_name = "cam_ick", - .da_start = 0x0, - .da_end = 0xFFFFF000, - }, - }, -#if defined(CONFIG_OMAP_IOMMU_IVA2) - { - .base = 0x5d000000, - .irq = 28 + OMAP_INTC_START, - .pdata = { - .name = "iva2", - .nr_tlb_entries = 32, - .clk_name = "iva2_ck", - .da_start = 0x11000000, - .da_end = 0xFFFFF000, - }, - }, -#endif -}; -#define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices) -static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES]; -#else -#define omap3_devices NULL -#define NR_OMAP3_IOMMU_DEVICES 0 -#define omap3_iommu_pdev NULL -#endif - -#ifdef CONFIG_ARCH_OMAP4 -static struct iommu_device omap4_devices[] = { - { - .base = OMAP4_MMU1_BASE, - .irq = 100 + OMAP44XX_IRQ_GIC_START, - .pdata = { - .name = "ducati", - .nr_tlb_entries = 32, - .clk_name = "ipu_fck", - .da_start = 0x0, - .da_end = 0xFFFFF000, - }, - }, - { - .base = OMAP4_MMU2_BASE, - .irq = 28 + OMAP44XX_IRQ_GIC_START, - .pdata = { - .name = "tesla", - .nr_tlb_entries = 32, - .clk_name = "dsp_fck", - .da_start = 0x0, - .da_end = 0xFFFFF000, - }, - }, -}; -#define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) -static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; -#else -#define omap4_devices NULL -#define NR_OMAP4_IOMMU_DEVICES 0 -#define omap4_iommu_pdev NULL -#endif - -static struct platform_device **omap_iommu_pdev; - -static int __init omap_iommu_init(void) +static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused) { - int i, err; - struct resource res[] = { - { .flags = IORESOURCE_MEM }, - { .flags = IORESOURCE_IRQ }, - }; + struct platform_device *pdev; + struct iommu_platform_data *pdata; + struct omap_mmu_dev_attr *a = (struct omap_mmu_dev_attr *)oh->dev_attr; + static int i; + + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->name = oh->name; + pdata->clk_name = oh->main_clk; + pdata->nr_tlb_entries = a->nr_tlb_entries; + pdata->da_start = a->da_start; + pdata->da_end = a->da_end; + + if (oh->rst_lines_cnt == 1) { + pdata->reset_name = oh->rst_lines->name; + pdata->assert_reset = omap_device_assert_hardreset; + pdata->deassert_reset = omap_device_deassert_hardreset; + } - if (cpu_is_omap34xx()) { - devices = omap3_devices; - omap_iommu_pdev = omap3_iommu_pdev; - num_iommu_devices = NR_OMAP3_IOMMU_DEVICES; - } else if (cpu_is_omap44xx()) { - devices = omap4_devices; - omap_iommu_pdev = omap4_iommu_pdev; - num_iommu_devices = NR_OMAP4_IOMMU_DEVICES; - } else - return -ENODEV; + pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata), + NULL, 0, 0); - for (i = 0; i < num_iommu_devices; i++) { - struct platform_device *pdev; - const struct iommu_device *d = &devices[i]; + kfree(pdata); - pdev = platform_device_alloc("omap-iommu", i); - if (!pdev) { - err = -ENOMEM; - goto err_out; - } + if (IS_ERR(pdev)) { + pr_err("%s: device build err: %ld\n", __func__, PTR_ERR(pdev)); + return PTR_ERR(pdev); + } - res[0].start = d->base; - res[0].end = d->base + MMU_REG_SIZE - 1; - res[1].start = res[1].end = d->irq; + i++; - err = platform_device_add_resources(pdev, res, - ARRAY_SIZE(res)); - if (err) - goto err_out; - err = platform_device_add_data(pdev, &d->pdata, - sizeof(d->pdata)); - if (err) - goto err_out; - err = platform_device_add(pdev); - if (err) - goto err_out; - omap_iommu_pdev[i] = pdev; - } return 0; +} -err_out: - while (i--) - platform_device_put(omap_iommu_pdev[i]); - return err; +static int __init omap_iommu_init(void) +{ + return omap_hwmod_for_each_by_class("mmu", omap_iommu_dev_init, NULL); } /* must be ready before omap3isp is probed */ subsys_initcall(omap_iommu_init); static void __exit omap_iommu_exit(void) { - int i; - - for (i = 0; i < num_iommu_devices; i++) - platform_device_unregister(omap_iommu_pdev[i]); + /* Do nothing */ } module_exit(omap_iommu_exit); diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index f8082da6179..af9b4f31f59 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -143,13 +143,23 @@ EXPORT_SYMBOL_GPL(omap_iommu_arch_version); static int iommu_enable(struct omap_iommu *obj) { int err; + struct platform_device *pdev = to_platform_device(obj->dev); + struct iommu_platform_data *pdata = pdev->dev.platform_data; - if (!obj) + if (!obj || !pdata) return -EINVAL; if (!arch_iommu) return -ENODEV; + if (pdata->deassert_reset) { + err = pdata->deassert_reset(pdev, pdata->reset_name); + if (err) { + dev_err(obj->dev, "deassert_reset failed: %d\n", err); + return err; + } + } + clk_enable(obj->clk); err = arch_iommu->enable(obj); @@ -159,12 +169,18 @@ static int iommu_enable(struct omap_iommu *obj) static void iommu_disable(struct omap_iommu *obj) { - if (!obj) + struct platform_device *pdev = to_platform_device(obj->dev); + struct iommu_platform_data *pdata = pdev->dev.platform_data; + + if (!obj || !pdata) return; arch_iommu->disable(obj); clk_disable(obj->clk); + + if (pdata->assert_reset) + pdata->assert_reset(pdev, pdata->reset_name); } /* @@ -926,9 +942,6 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) struct resource *res; struct iommu_platform_data *pdata = pdev->dev.platform_data; - if (pdev->num_resources != 2) - return -EINVAL; - obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL); if (!obj) return -ENOMEM; diff --git a/drivers/iommu/omap-iommu2.c b/drivers/iommu/omap-iommu2.c index c0202029237..4a3a1c7a38c 100644 --- a/drivers/iommu/omap-iommu2.c +++ b/drivers/iommu/omap-iommu2.c @@ -35,12 +35,8 @@ #define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) #define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_SOFTRESET (1 << 1) #define MMU_SYS_AUTOIDLE 1 -/* SYSSTATUS */ -#define MMU_SYS_RESETDONE 1 - /* IRQSTATUS & IRQENABLE */ #define MMU_IRQ_MULTIHITFAULT (1 << 4) #define MMU_IRQ_TABLEWALKFAULT (1 << 3) @@ -97,7 +93,6 @@ static void __iommu_set_twl(struct omap_iommu *obj, bool on) static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; - unsigned long timeout; if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; @@ -106,20 +101,6 @@ static int omap2_iommu_enable(struct omap_iommu *obj) if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; - iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); - - timeout = jiffies + msecs_to_jiffies(20); - do { - l = iommu_read_reg(obj, MMU_SYSSTATUS); - if (l & MMU_SYS_RESETDONE) - break; - } while (!time_after(jiffies, timeout)); - - if (!(l & MMU_SYS_RESETDONE)) { - dev_err(obj->dev, "can't take mmu out of reset\n"); - return -ENODEV; - } - l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); diff --git a/include/linux/platform_data/iommu-omap.h b/include/linux/platform_data/iommu-omap.h index c677b9f2fef..ef2060d7eeb 100644 --- a/include/linux/platform_data/iommu-omap.h +++ b/include/linux/platform_data/iommu-omap.h @@ -10,6 +10,8 @@ * published by the Free Software Foundation. */ +#include + #define MMU_REG_SIZE 256 /** @@ -43,7 +45,11 @@ struct omap_mmu_dev_attr { struct iommu_platform_data { const char *name; const char *clk_name; - const int nr_tlb_entries; + const char *reset_name; + int nr_tlb_entries; u32 da_start; u32 da_end; + + int (*assert_reset)(struct platform_device *pdev, const char *name); + int (*deassert_reset)(struct platform_device *pdev, const char *name); }; -- cgit v1.2.3-70-g09d2 From ebf7cda0f92effd8169b831fae81e9437dce1fef Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Mon, 19 Nov 2012 19:05:51 -0600 Subject: iommu/omap: Adapt to runtime pm Use runtime PM functionality interfaced with hwmod enable/idle functions, to replace direct clock operations and sysconfig handling. Due to reset sequence, pm_runtime_[get|put]_sync must be used, to avoid possible operations with the module under reset. Because of this and given that the driver uses spin_locks to protect their critical sections, we must use pm_runtime_irq_safe in order for the runtime ops to be happy, otherwise might_sleep_if checks in runtime framework will complain. The remaining pm_runtime out of iommu_enable and iommu_disable corresponds to paths that can be accessed through debugfs, some of them doesn't work if the module is not enabled first, but in future if the mmu is idled withouth freeing, these are needed to debug. Signed-off-by: Omar Ramirez Luna Tested-by: Ohad Ben-Cohen Acked-by: Tony Lindgren Signed-off-by: Joerg Roedel --- arch/arm/mach-omap2/omap-iommu.c | 1 - drivers/iommu/omap-iommu.c | 40 +++++++++++++++----------------- drivers/iommu/omap-iommu.h | 3 --- drivers/iommu/omap-iommu2.c | 17 -------------- include/linux/platform_data/iommu-omap.h | 1 - 5 files changed, 19 insertions(+), 43 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 02726a647b1..7642fc4672c 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -31,7 +31,6 @@ static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused) return -ENOMEM; pdata->name = oh->name; - pdata->clk_name = oh->main_clk; pdata->nr_tlb_entries = a->nr_tlb_entries; pdata->da_start = a->da_start; pdata->da_end = a->da_end; diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index af9b4f31f59..18108c1405e 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -16,13 +16,13 @@ #include #include #include -#include #include #include #include #include #include #include +#include #include @@ -160,7 +160,7 @@ static int iommu_enable(struct omap_iommu *obj) } } - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); err = arch_iommu->enable(obj); @@ -177,7 +177,7 @@ static void iommu_disable(struct omap_iommu *obj) arch_iommu->disable(obj); - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); if (pdata->assert_reset) pdata->assert_reset(pdev, pdata->reset_name); @@ -303,7 +303,7 @@ static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) if (!obj || !obj->nr_tlb_entries || !e) return -EINVAL; - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); iotlb_lock_get(obj, &l); if (l.base == obj->nr_tlb_entries) { @@ -333,7 +333,7 @@ static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) cr = iotlb_alloc_cr(obj, e); if (IS_ERR(cr)) { - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); return PTR_ERR(cr); } @@ -347,7 +347,7 @@ static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e) l.vict = l.base; iotlb_lock_set(obj, &l); out: - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); return err; } @@ -377,7 +377,7 @@ static void flush_iotlb_page(struct omap_iommu *obj, u32 da) int i; struct cr_regs cr; - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) { u32 start; @@ -396,7 +396,7 @@ static void flush_iotlb_page(struct omap_iommu *obj, u32 da) iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); } } - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); if (i == obj->nr_tlb_entries) dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da); @@ -410,7 +410,7 @@ static void flush_iotlb_all(struct omap_iommu *obj) { struct iotlb_lock l; - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); l.base = 0; l.vict = 0; @@ -418,7 +418,7 @@ static void flush_iotlb_all(struct omap_iommu *obj) iommu_write_reg(obj, 1, MMU_GFLUSH); - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); } #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE) @@ -428,11 +428,11 @@ ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes) if (!obj || !buf) return -EINVAL; - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); bytes = arch_iommu->dump_ctx(obj, buf, bytes); - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); return bytes; } @@ -446,7 +446,7 @@ __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) struct cr_regs tmp; struct cr_regs *p = crs; - clk_enable(obj->clk); + pm_runtime_get_sync(obj->dev); iotlb_lock_get(obj, &saved); for_each_iotlb_cr(obj, num, i, tmp) { @@ -456,7 +456,7 @@ __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num) } iotlb_lock_set(obj, &saved); - clk_disable(obj->clk); + pm_runtime_put_sync(obj->dev); return p - crs; } @@ -946,10 +946,6 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) if (!obj) return -ENOMEM; - obj->clk = clk_get(&pdev->dev, pdata->clk_name); - if (IS_ERR(obj->clk)) - goto err_clk; - obj->nr_tlb_entries = pdata->nr_tlb_entries; obj->name = pdata->name; obj->dev = &pdev->dev; @@ -992,6 +988,9 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev) goto err_irq; platform_set_drvdata(pdev, obj); + pm_runtime_irq_safe(obj->dev); + pm_runtime_enable(obj->dev); + dev_info(&pdev->dev, "%s registered\n", obj->name); return 0; @@ -1000,8 +999,6 @@ err_irq: err_ioremap: release_mem_region(res->start, resource_size(res)); err_mem: - clk_put(obj->clk); -err_clk: kfree(obj); return err; } @@ -1022,7 +1019,8 @@ static int __devexit omap_iommu_remove(struct platform_device *pdev) release_mem_region(res->start, resource_size(res)); iounmap(obj->regbase); - clk_put(obj->clk); + pm_runtime_disable(obj->dev); + dev_info(&pdev->dev, "%s removed\n", obj->name); kfree(obj); return 0; diff --git a/drivers/iommu/omap-iommu.h b/drivers/iommu/omap-iommu.h index 2b5f3c04d16..12008420660 100644 --- a/drivers/iommu/omap-iommu.h +++ b/drivers/iommu/omap-iommu.h @@ -29,7 +29,6 @@ struct iotlb_entry { struct omap_iommu { const char *name; struct module *owner; - struct clk *clk; void __iomem *regbase; struct device *dev; void *isr_priv; @@ -116,8 +115,6 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev) * MMU Register offsets */ #define MMU_REVISION 0x00 -#define MMU_SYSCONFIG 0x10 -#define MMU_SYSSTATUS 0x14 #define MMU_IRQSTATUS 0x18 #define MMU_IRQENABLE 0x1c #define MMU_WALKING_ST 0x40 diff --git a/drivers/iommu/omap-iommu2.c b/drivers/iommu/omap-iommu2.c index 4a3a1c7a38c..d745094a69d 100644 --- a/drivers/iommu/omap-iommu2.c +++ b/drivers/iommu/omap-iommu2.c @@ -28,15 +28,6 @@ */ #define IOMMU_ARCH_VERSION 0x00000011 -/* SYSCONF */ -#define MMU_SYS_IDLE_SHIFT 3 -#define MMU_SYS_IDLE_FORCE (0 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_NONE (1 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_SMART (2 << MMU_SYS_IDLE_SHIFT) -#define MMU_SYS_IDLE_MASK (3 << MMU_SYS_IDLE_SHIFT) - -#define MMU_SYS_AUTOIDLE 1 - /* IRQSTATUS & IRQENABLE */ #define MMU_IRQ_MULTIHITFAULT (1 << 4) #define MMU_IRQ_TABLEWALKFAULT (1 << 3) @@ -105,11 +96,6 @@ static int omap2_iommu_enable(struct omap_iommu *obj) dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); - l = iommu_read_reg(obj, MMU_SYSCONFIG); - l &= ~MMU_SYS_IDLE_MASK; - l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); - iommu_write_reg(obj, l, MMU_SYSCONFIG); - iommu_write_reg(obj, pa, MMU_TTB); __iommu_set_twl(obj, true); @@ -123,7 +109,6 @@ static void omap2_iommu_disable(struct omap_iommu *obj) l &= ~MMU_CNTL_MASK; iommu_write_reg(obj, l, MMU_CNTL); - iommu_write_reg(obj, MMU_SYS_IDLE_FORCE, MMU_SYSCONFIG); dev_dbg(obj->dev, "%s is shutting down\n", obj->name); } @@ -252,8 +237,6 @@ omap2_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len) char *p = buf; pr_reg(REVISION); - pr_reg(SYSCONFIG); - pr_reg(SYSSTATUS); pr_reg(IRQSTATUS); pr_reg(IRQENABLE); pr_reg(WALKING_ST); diff --git a/include/linux/platform_data/iommu-omap.h b/include/linux/platform_data/iommu-omap.h index ef2060d7eeb..5b429c43a29 100644 --- a/include/linux/platform_data/iommu-omap.h +++ b/include/linux/platform_data/iommu-omap.h @@ -44,7 +44,6 @@ struct omap_mmu_dev_attr { struct iommu_platform_data { const char *name; - const char *clk_name; const char *reset_name; int nr_tlb_entries; u32 da_start; -- cgit v1.2.3-70-g09d2 From 298ea44f211de93ce1b30dc4e2bd2d3b23e41556 Mon Sep 17 00:00:00 2001 From: Omar Ramirez Luna Date: Mon, 19 Nov 2012 19:05:52 -0600 Subject: ARM: OMAP4: hwmod data: ipu and dsp to use parent clocks instead of leaf clocks This prevents hwmod _enable_clocks...omap2_dflt_clk_enable path from enabling modulemode inside CLKCTRL using its clk->enable_reg field. Instead is left to _omap4_enable_module though soc_ops, as the one in charge of this setting. According to comments received[1] for related patches the idea is to get rid of leaf clocks in future. So remove these two while at it. [1] http://lkml.org/lkml/2012/8/20/226 Signed-off-by: Omar Ramirez Luna Tested-by: Ohad Ben-Cohen Acked-by: Paul Walmsley Signed-off-by: Joerg Roedel --- arch/arm/mach-omap2/clock44xx_data.c | 22 ---------------------- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 4 ++-- 2 files changed, 2 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 6efc30c961a..067c486fe29 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -1316,16 +1316,6 @@ static struct clk dmic_fck = { .clkdm_name = "abe_clkdm", }; -static struct clk dsp_fck = { - .name = "dsp_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "tesla_clkdm", - .parent = &dpll_iva_m4x2_ck, - .recalc = &followparent_recalc, -}; - static struct clk dss_sys_clk = { .name = "dss_sys_clk", .ops = &clkops_omap2_dflt, @@ -1696,16 +1686,6 @@ static struct clk i2c4_fck = { .recalc = &followparent_recalc, }; -static struct clk ipu_fck = { - .name = "ipu_fck", - .ops = &clkops_omap2_dflt, - .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, - .enable_bit = OMAP4430_MODULEMODE_HWCTRL, - .clkdm_name = "ducati_clkdm", - .parent = &ducati_clk_mux_ck, - .recalc = &followparent_recalc, -}; - static struct clk iss_ctrlclk = { .name = "iss_ctrlclk", .ops = &clkops_omap2_dflt, @@ -3151,7 +3131,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), @@ -3183,7 +3162,6 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X), CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X), CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X), - CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), CLK(NULL, "iss_fck", &iss_fck, CK_443X), CLK(NULL, "iva_fck", &iva_fck, CK_443X), diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 1e00ea8b90e..4b985b9b81d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -651,7 +651,7 @@ static struct omap_hwmod omap44xx_dsp_hwmod = { .mpu_irqs = omap44xx_dsp_irqs, .rst_lines = omap44xx_dsp_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), - .main_clk = "dsp_fck", + .main_clk = "dpll_iva_m4x2_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, @@ -1678,7 +1678,7 @@ static struct omap_hwmod omap44xx_ipu_hwmod = { .mpu_irqs = omap44xx_ipu_irqs, .rst_lines = omap44xx_ipu_resets, .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), - .main_clk = "ipu_fck", + .main_clk = "ducati_clk_mux_ck", .prcm = { .omap4 = { .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, -- cgit v1.2.3-70-g09d2 From a0157573041403e7507a6f3f32279fc14ff5c02e Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Mon, 22 Oct 2012 20:44:03 +0800 Subject: ARM: dma-mapping: support debug_dma_mapping_error Without the patch, kind of below warning will be dumped if DMA-API debug is enabled: [ 11.069763] ------------[ cut here ]------------ [ 11.074645] WARNING: at lib/dma-debug.c:948 check_unmap+0x770/0x860() [ 11.081420] ehci-omap ehci-omap.0: DMA-API: device driver failed to check map error[device address=0x0000000 0adb78e80] [size=8 bytes] [mapped as single] [ 11.095611] Modules linked in: Cc: Russell King Cc: Marek Szyprowski Signed-off-by: Ming Lei Signed-off-by: Joerg Roedel --- arch/arm/include/asm/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch') diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 23004847bb0..78d8e9b5544 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -91,6 +91,7 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) */ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { + debug_dma_mapping_error(dev, dma_addr); return dma_addr == DMA_ERROR_CODE; } -- cgit v1.2.3-70-g09d2 From 6c27b20395d21235b73771a2bcf5325ece94c4c8 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 10 Oct 2012 08:32:24 +0000 Subject: powerpc/mpc52xx: use module_platform_driver macro This patch removes some code duplication by using module_platform_driver. Signed-off-by: Srinivas Kandagatla Signed-off-by: Anatolij Gustschin --- arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c index 2351f9e0fb6..16150fa430f 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_lpbfifo.c @@ -578,18 +578,4 @@ static struct platform_driver mpc52xx_lpbfifo_driver = { .probe = mpc52xx_lpbfifo_probe, .remove = __devexit_p(mpc52xx_lpbfifo_remove), }; - -/*********************************************************************** - * Module init/exit - */ -static int __init mpc52xx_lpbfifo_init(void) -{ - return platform_driver_register(&mpc52xx_lpbfifo_driver); -} -module_init(mpc52xx_lpbfifo_init); - -static void __exit mpc52xx_lpbfifo_exit(void) -{ - platform_driver_unregister(&mpc52xx_lpbfifo_driver); -} -module_exit(mpc52xx_lpbfifo_exit); +module_platform_driver(mpc52xx_lpbfifo_driver); -- cgit v1.2.3-70-g09d2 From 6baf11906e7687ad517567f6b93b94a90f0db3f9 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Mon, 15 Oct 2012 09:52:20 +0000 Subject: powerpc/512x: don't compile any platform DIU code if the DIU is not enabled If the DIU framebuffer driver is not enabled, then there's no point in compiling any platform DIU code, because it will never be used. Most of the platform code was protected in the appropriate #ifdef, but not all. This caused a break in some randconfig builds. This is only a problem on the 512x platforms. The P1022DS and MPC8610HPCD platforms are already correct. This patch reverts commit 12e36309f8774f4ccc769d5e3ff11ef092e524bc ("powerpc: Option FB_FSL_DIU is not really optional for mpc512x") and restores the ability to configure DIU support. Signed-off-by: Timur Tabi Signed-off-by: Anatolij Gustschin --- arch/powerpc/platforms/512x/Kconfig | 1 - arch/powerpc/platforms/512x/mpc5121_ads.c | 3 +++ arch/powerpc/platforms/512x/mpc512x.h | 11 +++++++++-- arch/powerpc/platforms/512x/mpc512x_shared.c | 25 ++++--------------------- 4 files changed, 16 insertions(+), 24 deletions(-) (limited to 'arch') diff --git a/arch/powerpc/platforms/512x/Kconfig b/arch/powerpc/platforms/512x/Kconfig index b62508b113d..c16999802ec 100644 --- a/arch/powerpc/platforms/512x/Kconfig +++ b/arch/powerpc/platforms/512x/Kconfig @@ -2,7 +2,6 @@ config PPC_MPC512x bool "512x-based boards" depends on 6xx select FSL_SOC - select FB_FSL_DIU select IPIC select PPC_CLOCK select PPC_PCI_CHOICE diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c index dcef6ade48e..0a134e0469e 100644 --- a/arch/powerpc/platforms/512x/mpc5121_ads.c +++ b/arch/powerpc/platforms/512x/mpc5121_ads.c @@ -42,7 +42,10 @@ static void __init mpc5121_ads_setup_arch(void) for_each_compatible_node(np, "pci", "fsl,mpc5121-pci") mpc83xx_add_bridge(np); #endif + +#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) mpc512x_setup_diu(); +#endif } static void __init mpc5121_ads_init_IRQ(void) diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h index 1ab6d11d0b1..c32b399eb95 100644 --- a/arch/powerpc/platforms/512x/mpc512x.h +++ b/arch/powerpc/platforms/512x/mpc512x.h @@ -16,6 +16,13 @@ extern void __init mpc512x_init(void); extern int __init mpc5121_clk_init(void); void __init mpc512x_declare_of_platform_devices(void); extern void mpc512x_restart(char *cmd); -extern void mpc512x_init_diu(void); -extern void mpc512x_setup_diu(void); + +#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) +void mpc512x_init_diu(void); +void mpc512x_setup_diu(void); +#else +#define mpc512x_init_diu NULL +#define mpc512x_setup_diu NULL +#endif + #endif /* __MPC512X_H__ */ diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c index 1650e090ef3..35f14fda108 100644 --- a/arch/powerpc/platforms/512x/mpc512x_shared.c +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c @@ -58,6 +58,8 @@ void mpc512x_restart(char *cmd) ; } +#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) + struct fsl_diu_shared_fb { u8 gamma[0x300]; /* 32-bit aligned! */ struct diu_ad ad0; /* 32-bit aligned! */ @@ -66,25 +68,6 @@ struct fsl_diu_shared_fb { bool in_use; }; -u32 mpc512x_get_pixel_format(enum fsl_diu_monitor_port port, - unsigned int bits_per_pixel) -{ - switch (bits_per_pixel) { - case 32: - return 0x88883316; - case 24: - return 0x88082219; - case 16: - return 0x65053118; - } - return 0x00000400; -} - -void mpc512x_set_gamma_table(enum fsl_diu_monitor_port port, - char *gamma_table_base) -{ -} - void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port) { } @@ -320,14 +303,14 @@ void __init mpc512x_setup_diu(void) } } - diu_ops.get_pixel_format = mpc512x_get_pixel_format; - diu_ops.set_gamma_table = mpc512x_set_gamma_table; diu_ops.set_monitor_port = mpc512x_set_monitor_port; diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; diu_ops.release_bootmem = mpc512x_release_bootmem; } +#endif + void __init mpc512x_init_IRQ(void) { struct device_node *np; -- cgit v1.2.3-70-g09d2 From cf66bb93e0f75e0a4ba1ec070692618fa028e994 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Mon, 3 Dec 2012 16:25:40 +0000 Subject: byteorder: allow arch to opt to use GCC intrinsics for byteswapping Since GCC 4.4, there have been __builtin_bswap32() and __builtin_bswap16() intrinsics. A __builtin_bswap16() came a little later (4.6 for PowerPC, 48 for other platforms). By using these instead of the inline assembler that most architectures have in their __arch_swabXX() macros, we let the compiler see what's actually happening. The resulting code should be at least as good, and much *better* in the cases where it can be combined with a nearby load or store, using a load-and-byteswap or store-and-byteswap instruction (e.g. lwbrx/stwbrx on PowerPC, movbe on Atom). When GCC is sufficiently recent *and* the architecture opts in to using the intrinsics by setting CONFIG_ARCH_USE_BUILTIN_BSWAP, they will be used in preference to the __arch_swabXX() macros. An architecture which does not set ARCH_USE_BUILTIN_BSWAP will continue to use its own hand-crafted macros. Signed-off-by: David Woodhouse Acked-by: H. Peter Anvin --- arch/Kconfig | 19 +++++++++++++++++++ include/linux/compiler-gcc4.h | 10 ++++++++++ include/linux/compiler-intel.h | 7 +++++++ include/uapi/linux/swab.h | 12 +++++++++--- 4 files changed, 45 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/Kconfig b/arch/Kconfig index 366ec06a518..c31416b1058 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -112,6 +112,25 @@ config HAVE_EFFICIENT_UNALIGNED_ACCESS See Documentation/unaligned-memory-access.txt for more information on the topic of unaligned memory accesses. +config ARCH_USE_BUILTIN_BSWAP + bool + help + Modern versions of GCC (since 4.4) have builtin functions + for handling byte-swapping. Using these, instead of the old + inline assembler that the architecture code provides in the + __arch_bswapXX() macros, allows the compiler to see what's + happening and offers more opportunity for optimisation. In + particular, the compiler will be able to combine the byteswap + with a nearby load or store and use load-and-swap or + store-and-swap instructions if the architecture has them. It + should almost *never* result in code which is worse than the + hand-coded assembler in . But just in case it + does, the use of the builtins is optional. + + Any architecture with load-and-swap or store-and-swap + instructions should set this. And it shouldn't hurt to set it + on architectures that don't have such instructions. + config HAVE_SYSCALL_WRAPPERS bool diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h index 412bc6c2b02..dc16a858e77 100644 --- a/include/linux/compiler-gcc4.h +++ b/include/linux/compiler-gcc4.h @@ -63,3 +63,13 @@ #define __compiletime_warning(message) __attribute__((warning(message))) #define __compiletime_error(message) __attribute__((error(message))) #endif + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#if __GNUC_MINOR__ >= 4 +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#endif +#if __GNUC_MINOR__ >= 8 || (defined(__powerpc__) && __GNUC_MINOR__ >= 6) +#define __HAVE_BUILTIN_BSWAP16__ +#endif +#endif diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h index d8e636e5607..973ce10c40b 100644 --- a/include/linux/compiler-intel.h +++ b/include/linux/compiler-intel.h @@ -29,3 +29,10 @@ #endif #define uninitialized_var(x) x + +#ifndef __HAVE_BUILTIN_BSWAP16__ +/* icc has this, but it's called _bswap16 */ +#define __HAVE_BUILTIN_BSWAP16__ +#define __builtin_bswap16 _bswap16 +#endif + diff --git a/include/uapi/linux/swab.h b/include/uapi/linux/swab.h index e811474724c..0e011eb91b5 100644 --- a/include/uapi/linux/swab.h +++ b/include/uapi/linux/swab.h @@ -45,7 +45,9 @@ static inline __attribute_const__ __u16 __fswab16(__u16 val) { -#ifdef __arch_swab16 +#ifdef __HAVE_BUILTIN_BSWAP16__ + return __builtin_bswap16(val); +#elif defined (__arch_swab16) return __arch_swab16(val); #else return ___constant_swab16(val); @@ -54,7 +56,9 @@ static inline __attribute_const__ __u16 __fswab16(__u16 val) static inline __attribute_const__ __u32 __fswab32(__u32 val) { -#ifdef __arch_swab32 +#ifdef __HAVE_BUILTIN_BSWAP32__ + return __builtin_bswap32(val); +#elif defined(__arch_swab32) return __arch_swab32(val); #else return ___constant_swab32(val); @@ -63,7 +67,9 @@ static inline __attribute_const__ __u32 __fswab32(__u32 val) static inline __attribute_const__ __u64 __fswab64(__u64 val) { -#ifdef __arch_swab64 +#ifdef __HAVE_BUILTIN_BSWAP64__ + return __builtin_bswap64(val); +#elif defined (__arch_swab64) return __arch_swab64(val); #elif defined(__SWAB_64_THRU_32__) __u32 h = val >> 32; -- cgit v1.2.3-70-g09d2 From 667b504a2c411e4d5915a6e2260a3857ba9f797a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 5 Dec 2012 23:30:10 +0000 Subject: powerpc: mpc5200: Add a3m071 board support This patch adds the MPC5200B based a3m071 board. Signed-off-by: Stefan Roese Cc: Anatolij Gustschin Signed-off-by: Anatolij Gustschin --- arch/powerpc/boot/dts/a3m071.dts | 144 +++++++++++++++++++++++++++ arch/powerpc/platforms/52xx/mpc5200_simple.c | 1 + 2 files changed, 145 insertions(+) create mode 100644 arch/powerpc/boot/dts/a3m071.dts (limited to 'arch') diff --git a/arch/powerpc/boot/dts/a3m071.dts b/arch/powerpc/boot/dts/a3m071.dts new file mode 100644 index 00000000000..877a28cb77e --- /dev/null +++ b/arch/powerpc/boot/dts/a3m071.dts @@ -0,0 +1,144 @@ +/* + * a3m071 board Device Tree Source + * + * Copyright 2012 Stefan Roese + * + * Copyright (C) 2011 DENX Software Engineering GmbH + * Heiko Schocher + * + * Copyright (C) 2007 Semihalf + * Marian Balakowicz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "mpc5200b.dtsi" + +/ { + model = "anonymous,a3m071"; + compatible = "anonymous,a3m071"; + + soc5200@f0000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc5200b-immr"; + ranges = <0 0xf0000000 0x0000c000>; + reg = <0xf0000000 0x00000100>; + bus-frequency = <0>; /* From boot loader */ + system-frequency = <0>; /* From boot loader */ + + timer@600 { + fsl,has-wdt; + }; + + spi@f00 { + status = "disabled"; + }; + + usb: usb@1000 { + status = "disabled"; + }; + + psc@2000 { + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; + reg = <0x2000 0x100>; + interrupts = <2 1 0>; + }; + + psc@2200 { + status = "disabled"; + }; + + psc@2400 { + status = "disabled"; + }; + + psc@2600 { + status = "disabled"; + }; + + psc@2800 { + status = "disabled"; + }; + + psc@2c00 { // PSC6 + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; + reg = <0x2c00 0x100>; + interrupts = <2 4 0>; + }; + + ethernet@3000 { + phy-handle = <&phy0>; + }; + + mdio@3000 { + phy0: ethernet-phy@3 { + reg = <0x03>; + }; + }; + + ata@3a00 { + status = "disabled"; + }; + + i2c@3d00 { + status = "disabled"; + }; + + i2c@3d40 { + status = "disabled"; + }; + }; + + localbus { + compatible = "fsl,mpc5200b-lpb","simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xfc000000 0x02000000 + 3 0 0xe9000000 0x00080000 + 5 0 0xe8000000 0x00010000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x0 0x02000000>; + compatible = "cfi-flash"; + bank-width = <2>; + partition@0x0 { + label = "u-boot"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@0x00040000 { + label = "env"; + reg = <0x00040000 0x00020000>; + }; + partition@0x00060000 { + label = "dtb"; + reg = <0x00060000 0x00020000>; + }; + partition@0x00080000 { + label = "kernel"; + reg = <0x00080000 0x00500000>; + }; + partition@0x00580000 { + label = "root"; + reg = <0x00580000 0x00A80000>; + }; + }; + + fpga@3,0 { + compatible = "anonymous,a3m071-fpga"; + reg = <3 0x0 0x00080000 + 5 0x0 0x00010000>; + interrupts = <0 0 3>; /* level low */ + }; + }; + + pci@f0000d00 { + status = "disabled"; + }; +}; diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c index 9cf36020cf0..792a301a0bf 100644 --- a/arch/powerpc/platforms/52xx/mpc5200_simple.c +++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c @@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void) /* list of the supported boards */ static const char *board[] __initdata = { + "anonymous,a3m071", "anonymous,a4m072", "anon,charon", "ifm,o2d", -- cgit v1.2.3-70-g09d2 From 9ab9da5ee2adc2b98ce7cc13a7f1cc900d2bee5a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 1 Dec 2012 14:24:42 +0100 Subject: c6x: Use generic asm/mmu.h c6x's asm/mmu.h is basically identical to asm-generic/mmu.h, so use it instead of the custom version. Signed-off-by: Lars-Peter Clausen Acked-by: Mark Salter Tested-by: Mark Salter Signed-off-by: Arnd Bergmann --- arch/c6x/include/asm/Kbuild | 1 + arch/c6x/include/asm/mmu.h | 22 ---------------------- 2 files changed, 1 insertion(+), 22 deletions(-) delete mode 100644 arch/c6x/include/asm/mmu.h (limited to 'arch') diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild index 112a496d835..3c8b660e7a9 100644 --- a/arch/c6x/include/asm/Kbuild +++ b/arch/c6x/include/asm/Kbuild @@ -25,6 +25,7 @@ generic-y += kdebug.h generic-y += kmap_types.h generic-y += local.h generic-y += mman.h +generic-y += mmu.h generic-y += mmu_context.h generic-y += msgbuf.h generic-y += param.h diff --git a/arch/c6x/include/asm/mmu.h b/arch/c6x/include/asm/mmu.h deleted file mode 100644 index 4467e770a1c..00000000000 --- a/arch/c6x/include/asm/mmu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Port on Texas Instruments TMS320C6x architecture - * - * Copyright (C) 2004, 2009, 2010 Texas Instruments Incorporated - * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef _ASM_C6X_MMU_H -#define _ASM_C6X_MMU_H - -typedef struct { - unsigned long end_brk; -#ifdef CONFIG_BINFMT_ELF_FDPIC - unsigned long exec_fdpic_loadmap; - unsigned long interp_fdpic_loadmap; -#endif -} mm_context_t; - -#endif /* _ASM_C6X_MMU_H */ -- cgit v1.2.3-70-g09d2 From 0a2f505ee721f0b5480464673ca71520c0ac2eb6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 1 Dec 2012 14:24:43 +0100 Subject: h8300: Use generic asm/mmu.h h8300's asm/mmu.h is basically identical to asm-generic/mmu.h, so use it instead of the custom version. Signed-off-by: Lars-Peter Clausen Signed-off-by: Arnd Bergmann --- arch/h8300/include/asm/Kbuild | 1 + arch/h8300/include/asm/mmu.h | 10 ---------- 2 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 arch/h8300/include/asm/mmu.h (limited to 'arch') diff --git a/arch/h8300/include/asm/Kbuild b/arch/h8300/include/asm/Kbuild index 50bbf387b2f..173de77e593 100644 --- a/arch/h8300/include/asm/Kbuild +++ b/arch/h8300/include/asm/Kbuild @@ -2,4 +2,5 @@ include include/asm-generic/Kbuild.asm generic-y += clkdev.h generic-y += exec.h +generic-y += mmu.h generic-y += module.h diff --git a/arch/h8300/include/asm/mmu.h b/arch/h8300/include/asm/mmu.h deleted file mode 100644 index 31309969df7..00000000000 --- a/arch/h8300/include/asm/mmu.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef __MMU_H -#define __MMU_H - -/* Copyright (C) 2002, David McCullough */ - -typedef struct { - unsigned long end_brk; -} mm_context_t; - -#endif -- cgit v1.2.3-70-g09d2 From fb9de7ebc3a2eb7ddb83c92e288447a0c313bced Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 1 Dec 2012 14:24:44 +0100 Subject: xtensa: Use generic asm/mmu.h for nommu The nommu portion of mmu.h of the extensa platform is basically the same as the asm-generic mmu.h. So use it instead. Signed-off-by: Lars-Peter Clausen Acked-by: Chris Zankel Signed-off-by: Arnd Bergmann --- arch/xtensa/include/asm/mmu.h | 2 +- arch/xtensa/include/asm/nommu.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) delete mode 100644 arch/xtensa/include/asm/nommu.h (limited to 'arch') diff --git a/arch/xtensa/include/asm/mmu.h b/arch/xtensa/include/asm/mmu.h index 04890d6e233..8554b2c8b17 100644 --- a/arch/xtensa/include/asm/mmu.h +++ b/arch/xtensa/include/asm/mmu.h @@ -12,7 +12,7 @@ #define _XTENSA_MMU_H #ifndef CONFIG_MMU -#include +#include #else /* Default "unsigned long" context */ diff --git a/arch/xtensa/include/asm/nommu.h b/arch/xtensa/include/asm/nommu.h deleted file mode 100644 index dce2c438c5b..00000000000 --- a/arch/xtensa/include/asm/nommu.h +++ /dev/null @@ -1,3 +0,0 @@ -typedef struct { - unsigned long end_brk; -} mm_context_t; -- cgit v1.2.3-70-g09d2 From 210dce5faf89c9677ac1a6273bc53f130843539f Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 10 Dec 2012 22:21:19 +0100 Subject: ARM: ep93xx: properly wait for UART FIFO to be empty This patch changes the busy-waiting loop around in the decompressor putc() function on the UART FIFO register. Without a proper wait, the output of the decompressor was corrupted like this: Uncompressing Linx. done, booting th enl To highlight the issue more evidently, looping 100 times instead of 1000 makes the issue appear much faster. This patch takes the approach of using an active while loop until the FIFO is empty (not FULL). This issue happened to me on Sim.One running at 200Mhz. Signed-off-by: Florian Fainelli Signed-off-by: Ryan Mallon --- arch/arm/mach-ep93xx/include/mach/uncompress.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-ep93xx/include/mach/uncompress.h b/arch/arm/mach-ep93xx/include/mach/uncompress.h index 16026c2b1c8..d64274fc576 100644 --- a/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -47,13 +47,9 @@ static void __raw_writel(unsigned int value, unsigned int ptr) static inline void putc(int c) { - int i; - - for (i = 0; i < 1000; i++) { - /* Transmit fifo not full? */ - if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) - break; - } + /* Transmit fifo not full? */ + while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) + ; __raw_writeb(c, PHYS_UART_DATA); } -- cgit v1.2.3-70-g09d2 From 5955a5966632d0f49cb9418ae437db604db295d9 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 25 Oct 2012 16:36:11 -0400 Subject: tilegx: remove __init from pci fixup hook Support having the PCI bus be removed at runtime and rediscovered. gregkh@linuxfoundation.org argued for removing __init rather than converting it to __devinit. Signed-off-by: Chris Metcalf --- arch/tile/kernel/pci_gx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c index 2ba6d052f85..94810d4a633 100644 --- a/arch/tile/kernel/pci_gx.c +++ b/arch/tile/kernel/pci_gx.c @@ -1047,8 +1047,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) } /* Called for each device after PCI setup is done. */ -static void __init -pcibios_fixup_final(struct pci_dev *pdev) +static void pcibios_fixup_final(struct pci_dev *pdev) { set_dma_ops(&pdev->dev, gx_pci_dma_map_ops); set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET); -- cgit v1.2.3-70-g09d2 From 17a263540cebd4c615755300f34c695b15378a58 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Mon, 3 Dec 2012 08:28:36 -0500 Subject: tile/PCI: use for_each_pci_dev to simplify the code Use for_each_pci_dev to simplify the code. Signed-off-by: Wei Yongjun Signed-off-by: Chris Metcalf --- arch/tile/kernel/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c index 759822687e8..aac1cd58696 100644 --- a/arch/tile/kernel/pci.c +++ b/arch/tile/kernel/pci.c @@ -245,7 +245,7 @@ static void __devinit fixup_read_and_payload_sizes(void) u16 new_values; /* Scan for the smallest maximum payload size. */ - while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + for_each_pci_dev(dev) { u32 devcap; int max_payload; @@ -260,7 +260,7 @@ static void __devinit fixup_read_and_payload_sizes(void) /* Now, set the max_payload_size for all devices to that value. */ new_values = (max_read_size << 12) | (smallest_max_payload << 5); - while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) + for_each_pci_dev(dev) pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ, new_values); -- cgit v1.2.3-70-g09d2 From 7056741fd9fc14a65608549a4657cf5178f05f63 Mon Sep 17 00:00:00 2001 From: Jim Kukunas Date: Thu, 8 Nov 2012 13:47:44 -0800 Subject: lib/raid6: Add AVX2 optimized recovery functions Optimize RAID6 recovery functions to take advantage of the 256-bit YMM integer instructions introduced in AVX2. The patch was tested and benchmarked before submission. However hardware is not yet released so benchmark numbers cannot be reported. Acked-by: "H. Peter Anvin" Signed-off-by: Jim Kukunas Signed-off-by: NeilBrown --- arch/x86/Makefile | 5 +- include/linux/raid/pq.h | 1 + lib/raid6/Makefile | 2 +- lib/raid6/algos.c | 3 + lib/raid6/recov_avx2.c | 327 ++++++++++++++++++++++++++++++++++++++++++++++++ lib/raid6/test/Makefile | 2 +- lib/raid6/x86.h | 14 ++- 7 files changed, 345 insertions(+), 9 deletions(-) create mode 100644 lib/raid6/recov_avx2.c (limited to 'arch') diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 58790bd85c1..95477aae9ff 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -123,9 +123,10 @@ cfi-sections := $(call as-instr,.cfi_sections .debug_frame,-DCONFIG_AS_CFI_SECTI # does binutils support specific instructions? asinstr := $(call as-instr,fxsaveq (%rax),-DCONFIG_AS_FXSAVEQ=1) avx_instr := $(call as-instr,vxorps %ymm0$(comma)%ymm1$(comma)%ymm2,-DCONFIG_AS_AVX=1) +avx2_instr :=$(call as-instr,vpbroadcastb %xmm0$(comma)%ymm1,-DCONFIG_AS_AVX2=1) -KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) -KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) +KBUILD_AFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) +KBUILD_CFLAGS += $(cfi) $(cfi-sigframe) $(cfi-sections) $(asinstr) $(avx_instr) $(avx2_instr) LDFLAGS := -m elf_$(UTS_MACHINE) diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h index 640c69ceec9..3156347452b 100644 --- a/include/linux/raid/pq.h +++ b/include/linux/raid/pq.h @@ -109,6 +109,7 @@ struct raid6_recov_calls { extern const struct raid6_recov_calls raid6_recov_intx1; extern const struct raid6_recov_calls raid6_recov_ssse3; +extern const struct raid6_recov_calls raid6_recov_avx2; /* Algorithm list */ extern const struct raid6_calls * const raid6_algos[]; diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile index de06dfe165b..8c2e22bef66 100644 --- a/lib/raid6/Makefile +++ b/lib/raid6/Makefile @@ -1,6 +1,6 @@ obj-$(CONFIG_RAID6_PQ) += raid6_pq.o -raid6_pq-y += algos.o recov.o recov_ssse3.o tables.o int1.o int2.o int4.o \ +raid6_pq-y += algos.o recov.o recov_ssse3.o recov_avx2.o tables.o int1.o int2.o int4.o \ int8.o int16.o int32.o altivec1.o altivec2.o altivec4.o \ altivec8.o mmx.o sse1.o sse2.o hostprogs-y += mktables diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c index 589f5f50ad2..8b7f55cadb4 100644 --- a/lib/raid6/algos.c +++ b/lib/raid6/algos.c @@ -72,6 +72,9 @@ EXPORT_SYMBOL_GPL(raid6_datap_recov); const struct raid6_recov_calls *const raid6_recov_algos[] = { #if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__) +#ifdef CONFIG_AS_AVX2 + &raid6_recov_avx2, +#endif &raid6_recov_ssse3, #endif &raid6_recov_intx1, diff --git a/lib/raid6/recov_avx2.c b/lib/raid6/recov_avx2.c new file mode 100644 index 00000000000..43a9bab9187 --- /dev/null +++ b/lib/raid6/recov_avx2.c @@ -0,0 +1,327 @@ +/* + * Copyright (C) 2012 Intel Corporation + * Author: Jim Kukunas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 + * of the License. + */ + +#if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__) + +#if CONFIG_AS_AVX2 + +#include +#include "x86.h" + +static int raid6_has_avx2(void) +{ + return boot_cpu_has(X86_FEATURE_AVX2) && + boot_cpu_has(X86_FEATURE_AVX); +} + +static void raid6_2data_recov_avx2(int disks, size_t bytes, int faila, + int failb, void **ptrs) +{ + u8 *p, *q, *dp, *dq; + const u8 *pbmul; /* P multiplier table for B data */ + const u8 *qmul; /* Q multiplier table (for both) */ + const u8 x0f = 0x0f; + + p = (u8 *)ptrs[disks-2]; + q = (u8 *)ptrs[disks-1]; + + /* Compute syndrome with zero for the missing data pages + Use the dead data pages as temporary storage for + delta p and delta q */ + dp = (u8 *)ptrs[faila]; + ptrs[faila] = (void *)raid6_empty_zero_page; + ptrs[disks-2] = dp; + dq = (u8 *)ptrs[failb]; + ptrs[failb] = (void *)raid6_empty_zero_page; + ptrs[disks-1] = dq; + + raid6_call.gen_syndrome(disks, bytes, ptrs); + + /* Restore pointer table */ + ptrs[faila] = dp; + ptrs[failb] = dq; + ptrs[disks-2] = p; + ptrs[disks-1] = q; + + /* Now, pick the proper data tables */ + pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]]; + qmul = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila] ^ + raid6_gfexp[failb]]]; + + kernel_fpu_begin(); + + /* ymm0 = x0f[16] */ + asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f)); + + while (bytes) { +#ifdef CONFIG_X86_64 + asm volatile("vmovdqa %0, %%ymm1" : : "m" (q[0])); + asm volatile("vmovdqa %0, %%ymm9" : : "m" (q[32])); + asm volatile("vmovdqa %0, %%ymm0" : : "m" (p[0])); + asm volatile("vmovdqa %0, %%ymm8" : : "m" (p[32])); + asm volatile("vpxor %0, %%ymm1, %%ymm1" : : "m" (dq[0])); + asm volatile("vpxor %0, %%ymm9, %%ymm9" : : "m" (dq[32])); + asm volatile("vpxor %0, %%ymm0, %%ymm0" : : "m" (dp[0])); + asm volatile("vpxor %0, %%ymm8, %%ymm8" : : "m" (dp[32])); + + /* + * 1 = dq[0] ^ q[0] + * 9 = dq[32] ^ q[32] + * 0 = dp[0] ^ p[0] + * 8 = dp[32] ^ p[32] + */ + + asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (qmul[0])); + asm volatile("vbroadcasti128 %0, %%ymm5" : : "m" (qmul[16])); + + asm volatile("vpsraw $4, %ymm1, %ymm3"); + asm volatile("vpsraw $4, %ymm9, %ymm12"); + asm volatile("vpand %ymm7, %ymm1, %ymm1"); + asm volatile("vpand %ymm7, %ymm9, %ymm9"); + asm volatile("vpand %ymm7, %ymm3, %ymm3"); + asm volatile("vpand %ymm7, %ymm12, %ymm12"); + asm volatile("vpshufb %ymm9, %ymm4, %ymm14"); + asm volatile("vpshufb %ymm1, %ymm4, %ymm4"); + asm volatile("vpshufb %ymm12, %ymm5, %ymm15"); + asm volatile("vpshufb %ymm3, %ymm5, %ymm5"); + asm volatile("vpxor %ymm14, %ymm15, %ymm15"); + asm volatile("vpxor %ymm4, %ymm5, %ymm5"); + + /* + * 5 = qx[0] + * 15 = qx[32] + */ + + asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (pbmul[0])); + asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (pbmul[16])); + asm volatile("vpsraw $4, %ymm0, %ymm2"); + asm volatile("vpsraw $4, %ymm8, %ymm6"); + asm volatile("vpand %ymm7, %ymm0, %ymm3"); + asm volatile("vpand %ymm7, %ymm8, %ymm14"); + asm volatile("vpand %ymm7, %ymm2, %ymm2"); + asm volatile("vpand %ymm7, %ymm6, %ymm6"); + asm volatile("vpshufb %ymm14, %ymm4, %ymm12"); + asm volatile("vpshufb %ymm3, %ymm4, %ymm4"); + asm volatile("vpshufb %ymm6, %ymm1, %ymm13"); + asm volatile("vpshufb %ymm2, %ymm1, %ymm1"); + asm volatile("vpxor %ymm4, %ymm1, %ymm1"); + asm volatile("vpxor %ymm12, %ymm13, %ymm13"); + + /* + * 1 = pbmul[px[0]] + * 13 = pbmul[px[32]] + */ + asm volatile("vpxor %ymm5, %ymm1, %ymm1"); + asm volatile("vpxor %ymm15, %ymm13, %ymm13"); + + /* + * 1 = db = DQ + * 13 = db[32] = DQ[32] + */ + asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0])); + asm volatile("vmovdqa %%ymm13,%0" : "=m" (dq[32])); + asm volatile("vpxor %ymm1, %ymm0, %ymm0"); + asm volatile("vpxor %ymm13, %ymm8, %ymm8"); + + asm volatile("vmovdqa %%ymm0, %0" : "=m" (dp[0])); + asm volatile("vmovdqa %%ymm8, %0" : "=m" (dp[32])); + + bytes -= 64; + p += 64; + q += 64; + dp += 64; + dq += 64; +#else + asm volatile("vmovdqa %0, %%ymm1" : : "m" (*q)); + asm volatile("vmovdqa %0, %%ymm0" : : "m" (*p)); + asm volatile("vpxor %0, %%ymm1, %%ymm1" : : "m" (*dq)); + asm volatile("vpxor %0, %%ymm0, %%ymm0" : : "m" (*dp)); + + /* 1 = dq ^ q; 0 = dp ^ p */ + + asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (qmul[0])); + asm volatile("vbroadcasti128 %0, %%ymm5" : : "m" (qmul[16])); + + /* + * 1 = dq ^ q + * 3 = dq ^ p >> 4 + */ + asm volatile("vpsraw $4, %ymm1, %ymm3"); + asm volatile("vpand %ymm7, %ymm1, %ymm1"); + asm volatile("vpand %ymm7, %ymm3, %ymm3"); + asm volatile("vpshufb %ymm1, %ymm4, %ymm4"); + asm volatile("vpshufb %ymm3, %ymm5, %ymm5"); + asm volatile("vpxor %ymm4, %ymm5, %ymm5"); + + /* 5 = qx */ + + asm volatile("vbroadcasti128 %0, %%ymm4" : : "m" (pbmul[0])); + asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (pbmul[16])); + + asm volatile("vpsraw $4, %ymm0, %ymm2"); + asm volatile("vpand %ymm7, %ymm0, %ymm3"); + asm volatile("vpand %ymm7, %ymm2, %ymm2"); + asm volatile("vpshufb %ymm3, %ymm4, %ymm4"); + asm volatile("vpshufb %ymm2, %ymm1, %ymm1"); + asm volatile("vpxor %ymm4, %ymm1, %ymm1"); + + /* 1 = pbmul[px] */ + asm volatile("vpxor %ymm5, %ymm1, %ymm1"); + /* 1 = db = DQ */ + asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0])); + + asm volatile("vpxor %ymm1, %ymm0, %ymm0"); + asm volatile("vmovdqa %%ymm0, %0" : "=m" (dp[0])); + + bytes -= 32; + p += 32; + q += 32; + dp += 32; + dq += 32; +#endif + } + + kernel_fpu_end(); +} + +static void raid6_datap_recov_avx2(int disks, size_t bytes, int faila, + void **ptrs) +{ + u8 *p, *q, *dq; + const u8 *qmul; /* Q multiplier table */ + const u8 x0f = 0x0f; + + p = (u8 *)ptrs[disks-2]; + q = (u8 *)ptrs[disks-1]; + + /* Compute syndrome with zero for the missing data page + Use the dead data page as temporary storage for delta q */ + dq = (u8 *)ptrs[faila]; + ptrs[faila] = (void *)raid6_empty_zero_page; + ptrs[disks-1] = dq; + + raid6_call.gen_syndrome(disks, bytes, ptrs); + + /* Restore pointer table */ + ptrs[faila] = dq; + ptrs[disks-1] = q; + + /* Now, pick the proper data tables */ + qmul = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila]]]; + + kernel_fpu_begin(); + + asm volatile("vpbroadcastb %0, %%ymm7" : : "m" (x0f)); + + while (bytes) { +#ifdef CONFIG_X86_64 + asm volatile("vmovdqa %0, %%ymm3" : : "m" (dq[0])); + asm volatile("vmovdqa %0, %%ymm8" : : "m" (dq[32])); + asm volatile("vpxor %0, %%ymm3, %%ymm3" : : "m" (q[0])); + asm volatile("vpxor %0, %%ymm8, %%ymm8" : : "m" (q[32])); + + /* + * 3 = q[0] ^ dq[0] + * 8 = q[32] ^ dq[32] + */ + asm volatile("vbroadcasti128 %0, %%ymm0" : : "m" (qmul[0])); + asm volatile("vmovapd %ymm0, %ymm13"); + asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (qmul[16])); + asm volatile("vmovapd %ymm1, %ymm14"); + + asm volatile("vpsraw $4, %ymm3, %ymm6"); + asm volatile("vpsraw $4, %ymm8, %ymm12"); + asm volatile("vpand %ymm7, %ymm3, %ymm3"); + asm volatile("vpand %ymm7, %ymm8, %ymm8"); + asm volatile("vpand %ymm7, %ymm6, %ymm6"); + asm volatile("vpand %ymm7, %ymm12, %ymm12"); + asm volatile("vpshufb %ymm3, %ymm0, %ymm0"); + asm volatile("vpshufb %ymm8, %ymm13, %ymm13"); + asm volatile("vpshufb %ymm6, %ymm1, %ymm1"); + asm volatile("vpshufb %ymm12, %ymm14, %ymm14"); + asm volatile("vpxor %ymm0, %ymm1, %ymm1"); + asm volatile("vpxor %ymm13, %ymm14, %ymm14"); + + /* + * 1 = qmul[q[0] ^ dq[0]] + * 14 = qmul[q[32] ^ dq[32]] + */ + asm volatile("vmovdqa %0, %%ymm2" : : "m" (p[0])); + asm volatile("vmovdqa %0, %%ymm12" : : "m" (p[32])); + asm volatile("vpxor %ymm1, %ymm2, %ymm2"); + asm volatile("vpxor %ymm14, %ymm12, %ymm12"); + + /* + * 2 = p[0] ^ qmul[q[0] ^ dq[0]] + * 12 = p[32] ^ qmul[q[32] ^ dq[32]] + */ + + asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0])); + asm volatile("vmovdqa %%ymm14, %0" : "=m" (dq[32])); + asm volatile("vmovdqa %%ymm2, %0" : "=m" (p[0])); + asm volatile("vmovdqa %%ymm12,%0" : "=m" (p[32])); + + bytes -= 64; + p += 64; + q += 64; + dq += 64; +#else + asm volatile("vmovdqa %0, %%ymm3" : : "m" (dq[0])); + asm volatile("vpxor %0, %%ymm3, %%ymm3" : : "m" (q[0])); + + /* 3 = q ^ dq */ + + asm volatile("vbroadcasti128 %0, %%ymm0" : : "m" (qmul[0])); + asm volatile("vbroadcasti128 %0, %%ymm1" : : "m" (qmul[16])); + + asm volatile("vpsraw $4, %ymm3, %ymm6"); + asm volatile("vpand %ymm7, %ymm3, %ymm3"); + asm volatile("vpand %ymm7, %ymm6, %ymm6"); + asm volatile("vpshufb %ymm3, %ymm0, %ymm0"); + asm volatile("vpshufb %ymm6, %ymm1, %ymm1"); + asm volatile("vpxor %ymm0, %ymm1, %ymm1"); + + /* 1 = qmul[q ^ dq] */ + + asm volatile("vmovdqa %0, %%ymm2" : : "m" (p[0])); + asm volatile("vpxor %ymm1, %ymm2, %ymm2"); + + /* 2 = p ^ qmul[q ^ dq] */ + + asm volatile("vmovdqa %%ymm1, %0" : "=m" (dq[0])); + asm volatile("vmovdqa %%ymm2, %0" : "=m" (p[0])); + + bytes -= 32; + p += 32; + q += 32; + dq += 32; +#endif + } + + kernel_fpu_end(); +} + +const struct raid6_recov_calls raid6_recov_avx2 = { + .data2 = raid6_2data_recov_avx2, + .datap = raid6_datap_recov_avx2, + .valid = raid6_has_avx2, +#ifdef CONFIG_X86_64 + .name = "avx2x2", +#else + .name = "avx2x1", +#endif + .priority = 2, +}; + +#else +#warning "your version of binutils lacks AVX2 support" +#endif + +#endif diff --git a/lib/raid6/test/Makefile b/lib/raid6/test/Makefile index c76151d9476..d919c98ce26 100644 --- a/lib/raid6/test/Makefile +++ b/lib/raid6/test/Makefile @@ -23,7 +23,7 @@ RANLIB = ranlib all: raid6.a raid6test raid6.a: int1.o int2.o int4.o int8.o int16.o int32.o mmx.o sse1.o sse2.o \ - altivec1.o altivec2.o altivec4.o altivec8.o recov.o recov_ssse3.o algos.o \ + altivec1.o altivec2.o altivec4.o altivec8.o recov.o recov_ssse3.o recov_avx2.o algos.o \ tables.o rm -f $@ $(AR) cq $@ $^ diff --git a/lib/raid6/x86.h b/lib/raid6/x86.h index d55d63232c5..b7595484a81 100644 --- a/lib/raid6/x86.h +++ b/lib/raid6/x86.h @@ -45,19 +45,23 @@ static inline void kernel_fpu_end(void) #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ +#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ /* Should work well enough on modern CPUs for testing */ static inline int boot_cpu_has(int flag) { - u32 eax = (flag & 0x20) ? 0x80000001 : 1; - u32 ecx, edx; + u32 eax, ebx, ecx, edx; + + eax = (flag & 0x100) ? 7 : + (flag & 0x20) ? 0x80000001 : 1; + ecx = 0; asm volatile("cpuid" - : "+a" (eax), "=d" (edx), "=c" (ecx) - : : "ebx"); + : "+a" (eax), "=b" (ebx), "=d" (edx), "+c" (ecx)); - return ((flag & 0x80 ? ecx : edx) >> (flag & 31)) & 1; + return ((flag & 0x100 ? ebx : + (flag & 0x80) ? ecx : edx) >> (flag & 31)) & 1; } #endif /* ndef __KERNEL__ */ -- cgit v1.2.3-70-g09d2 From 2ba364504f2c31665007330dec23e89e44f5864e Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 9 Oct 2012 09:46:39 +0100 Subject: UAPI: (Scripted) Disintegrate arch/blackfin/include/asm Signed-off-by: David Howells Acked-by: Arnd Bergmann Acked-by: Thomas Gleixner Acked-by: Michael Kerrisk Acked-by: Paul E. McKenney Acked-by: Dave Jones --- arch/blackfin/include/asm/Kbuild | 5 - arch/blackfin/include/asm/bfin_sport.h | 128 +------- arch/blackfin/include/asm/byteorder.h | 1 - arch/blackfin/include/asm/cachectl.h | 20 -- arch/blackfin/include/asm/fcntl.h | 17 -- arch/blackfin/include/asm/fixed_code.h | 30 +- arch/blackfin/include/asm/ioctls.h | 7 - arch/blackfin/include/asm/kvm_para.h | 1 - arch/blackfin/include/asm/poll.h | 16 - arch/blackfin/include/asm/posix_types.h | 30 -- arch/blackfin/include/asm/ptrace.h | 161 +--------- arch/blackfin/include/asm/sigcontext.h | 61 ---- arch/blackfin/include/asm/siginfo.h | 41 --- arch/blackfin/include/asm/signal.h | 7 - arch/blackfin/include/asm/stat.h | 69 ----- arch/blackfin/include/asm/swab.h | 50 --- arch/blackfin/include/asm/unistd.h | 430 +------------------------- arch/blackfin/include/uapi/asm/Kbuild | 16 + arch/blackfin/include/uapi/asm/bfin_sport.h | 136 +++++++++ arch/blackfin/include/uapi/asm/byteorder.h | 1 + arch/blackfin/include/uapi/asm/cachectl.h | 20 ++ arch/blackfin/include/uapi/asm/fcntl.h | 17 ++ arch/blackfin/include/uapi/asm/fixed_code.h | 38 +++ arch/blackfin/include/uapi/asm/ioctls.h | 7 + arch/blackfin/include/uapi/asm/kvm_para.h | 1 + arch/blackfin/include/uapi/asm/poll.h | 16 + arch/blackfin/include/uapi/asm/posix_types.h | 30 ++ arch/blackfin/include/uapi/asm/ptrace.h | 170 +++++++++++ arch/blackfin/include/uapi/asm/sigcontext.h | 61 ++++ arch/blackfin/include/uapi/asm/siginfo.h | 41 +++ arch/blackfin/include/uapi/asm/signal.h | 7 + arch/blackfin/include/uapi/asm/stat.h | 69 +++++ arch/blackfin/include/uapi/asm/swab.h | 50 +++ arch/blackfin/include/uapi/asm/unistd.h | 437 +++++++++++++++++++++++++++ 34 files changed, 1122 insertions(+), 1069 deletions(-) delete mode 100644 arch/blackfin/include/asm/byteorder.h delete mode 100644 arch/blackfin/include/asm/cachectl.h delete mode 100644 arch/blackfin/include/asm/fcntl.h delete mode 100644 arch/blackfin/include/asm/ioctls.h delete mode 100644 arch/blackfin/include/asm/kvm_para.h delete mode 100644 arch/blackfin/include/asm/poll.h delete mode 100644 arch/blackfin/include/asm/posix_types.h delete mode 100644 arch/blackfin/include/asm/sigcontext.h delete mode 100644 arch/blackfin/include/asm/siginfo.h delete mode 100644 arch/blackfin/include/asm/signal.h delete mode 100644 arch/blackfin/include/asm/stat.h delete mode 100644 arch/blackfin/include/asm/swab.h create mode 100644 arch/blackfin/include/uapi/asm/bfin_sport.h create mode 100644 arch/blackfin/include/uapi/asm/byteorder.h create mode 100644 arch/blackfin/include/uapi/asm/cachectl.h create mode 100644 arch/blackfin/include/uapi/asm/fcntl.h create mode 100644 arch/blackfin/include/uapi/asm/fixed_code.h create mode 100644 arch/blackfin/include/uapi/asm/ioctls.h create mode 100644 arch/blackfin/include/uapi/asm/kvm_para.h create mode 100644 arch/blackfin/include/uapi/asm/poll.h create mode 100644 arch/blackfin/include/uapi/asm/posix_types.h create mode 100644 arch/blackfin/include/uapi/asm/ptrace.h create mode 100644 arch/blackfin/include/uapi/asm/sigcontext.h create mode 100644 arch/blackfin/include/uapi/asm/siginfo.h create mode 100644 arch/blackfin/include/uapi/asm/signal.h create mode 100644 arch/blackfin/include/uapi/asm/stat.h create mode 100644 arch/blackfin/include/uapi/asm/swab.h create mode 100644 arch/blackfin/include/uapi/asm/unistd.h (limited to 'arch') diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index 5a0625aad6a..7ce56f5f6dd 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -1,4 +1,3 @@ -include include/asm-generic/Kbuild.asm generic-y += auxvec.h generic-y += bitsperlong.h @@ -43,7 +42,3 @@ generic-y += ucontext.h generic-y += unaligned.h generic-y += user.h generic-y += xor.h - -header-y += bfin_sport.h -header-y += cachectl.h -header-y += fixed_code.h diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index f8907ea6b5b..50b9dfd4839 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h @@ -5,65 +5,12 @@ * * Licensed under the GPL-2 or later. */ - #ifndef __BFIN_SPORT_H__ #define __BFIN_SPORT_H__ -/* Sport mode: it can be set to TDM, i2s or others */ -#define NORM_MODE 0x0 -#define TDM_MODE 0x1 -#define I2S_MODE 0x2 -#define NDSO_MODE 0x3 - -/* Data format, normal, a-law or u-law */ -#define NORM_FORMAT 0x0 -#define ALAW_FORMAT 0x2 -#define ULAW_FORMAT 0x3 - -/* Function driver which use sport must initialize the structure */ -struct sport_config { - /* TDM (multichannels), I2S or other mode */ - unsigned int mode:3; - unsigned int polled; /* use poll instead of irq when set */ - - /* if TDM mode is selected, channels must be set */ - int channels; /* Must be in 8 units */ - unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ - - /* I2S mode */ - unsigned int right_first:1; /* Right stereo channel first */ - - /* In mormal mode, the following item need to be set */ - unsigned int lsb_first:1; /* order of transmit or receive data */ - unsigned int fsync:1; /* Frame sync required */ - unsigned int data_indep:1; /* data independent frame sync generated */ - unsigned int act_low:1; /* Active low TFS */ - unsigned int late_fsync:1; /* Late frame sync */ - unsigned int tckfe:1; - unsigned int sec_en:1; /* Secondary side enabled */ - - /* Choose clock source */ - unsigned int int_clk:1; /* Internal or external clock */ - - /* If external clock is used, the following fields are ignored */ - int serial_clk; - int fsync_clk; - - unsigned int data_format:2; /* Normal, u-law or a-law */ - - int word_len; /* How length of the word in bits, 3-32 bits */ - int dma_enabled; -}; - -/* Userspace interface */ -#define SPORT_IOC_MAGIC 'P' -#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) -#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) -#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) - -#ifdef __KERNEL__ #include +#include /* * All Blackfin system MMRs are padded to 32bits even if the register @@ -122,76 +69,3 @@ struct bfin_snd_platform_data { }) #endif - -/* SPORT_TCR1 Masks */ -#define TSPEN 0x0001 /* TX enable */ -#define ITCLK 0x0002 /* Internal TX Clock Select */ -#define TDTYPE 0x000C /* TX Data Formatting Select */ -#define DTYPE_NORM 0x0000 /* Data Format Normal */ -#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ -#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ -#define TLSBIT 0x0010 /* TX Bit Order */ -#define ITFS 0x0200 /* Internal TX Frame Sync Select */ -#define TFSR 0x0400 /* TX Frame Sync Required Select */ -#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ -#define LTFS 0x1000 /* Low TX Frame Sync Select */ -#define LATFS 0x2000 /* Late TX Frame Sync Select */ -#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ - -/* SPORT_TCR2 Masks */ -#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ -#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) -#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) -#define TXSE 0x0100 /* TX Secondary Enable */ -#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ -#define TRFST 0x0400 /* TX Right-First Data Order */ - -/* SPORT_RCR1 Masks */ -#define RSPEN 0x0001 /* RX enable */ -#define IRCLK 0x0002 /* Internal RX Clock Select */ -#define RDTYPE 0x000C /* RX Data Formatting Select */ -/* DTYPE_* defined above */ -#define RLSBIT 0x0010 /* RX Bit Order */ -#define IRFS 0x0200 /* Internal RX Frame Sync Select */ -#define RFSR 0x0400 /* RX Frame Sync Required Select */ -#define LRFS 0x1000 /* Low RX Frame Sync Select */ -#define LARFS 0x2000 /* Late RX Frame Sync Select */ -#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ - -/* SPORT_RCR2 Masks */ -/* SLEN defined above */ -#define RXSE 0x0100 /* RX Secondary Enable */ -#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ -#define RRFST 0x0400 /* Right-First Data Order */ - -/* SPORT_STAT Masks */ -#define RXNE 0x0001 /* RX FIFO Not Empty Status */ -#define RUVF 0x0002 /* RX Underflow Status */ -#define ROVF 0x0004 /* RX Overflow Status */ -#define TXF 0x0008 /* TX FIFO Full Status */ -#define TUVF 0x0010 /* TX Underflow Status */ -#define TOVF 0x0020 /* TX Overflow Status */ -#define TXHRE 0x0040 /* TX Hold Register Empty */ - -/* SPORT_MCMC1 Masks */ -#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ -#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) -#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) -#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ -#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) -#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) - -/* SPORT_MCMC2 Masks */ -#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ -#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ -#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ -#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ -#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ -#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ -#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ -#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ -#define MFD 0xF000 /* Multichannel Frame Delay */ -#define DP_MFD(x) BFIN_DEPOSIT(MFD, x) -#define EX_MFD(x) BFIN_EXTRACT(MFD, x) - -#endif diff --git a/arch/blackfin/include/asm/byteorder.h b/arch/blackfin/include/asm/byteorder.h deleted file mode 100644 index 9558416d578..00000000000 --- a/arch/blackfin/include/asm/byteorder.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/include/asm/cachectl.h b/arch/blackfin/include/asm/cachectl.h deleted file mode 100644 index 03255df6c1e..00000000000 --- a/arch/blackfin/include/asm/cachectl.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * based on the mips/cachectl.h - * - * Copyright 2010 Analog Devices Inc. - * Copyright (C) 1994, 1995, 1996 by Ralf Baechle - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL - -/* - * Options for cacheflush system call - */ -#define ICACHE (1<<0) /* flush instruction cache */ -#define DCACHE (1<<1) /* writeback and flush data cache */ -#define BCACHE (ICACHE|DCACHE) /* flush both caches */ - -#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/asm/fcntl.h b/arch/blackfin/include/asm/fcntl.h deleted file mode 100644 index 251c911d59c..00000000000 --- a/arch/blackfin/include/asm/fcntl.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_FCNTL_H -#define _BFIN_FCNTL_H - -#define O_DIRECTORY 040000 /* must be a directory */ -#define O_NOFOLLOW 0100000 /* don't follow links */ -#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ -#define O_LARGEFILE 0400000 - -#include - -#endif diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h index 5395088b2d0..bc330f06207 100644 --- a/arch/blackfin/include/asm/fixed_code.h +++ b/arch/blackfin/include/asm/fixed_code.h @@ -6,11 +6,11 @@ * * Licensed under the GPL-2 or later. */ - #ifndef __BFIN_ASM_FIXED_CODE_H__ #define __BFIN_ASM_FIXED_CODE_H__ -#ifdef __KERNEL__ +#include + #ifndef __ASSEMBLY__ #include #include @@ -28,29 +28,3 @@ extern void safe_user_instruction(void); extern void sigreturn_stub(void); #endif #endif - -#ifndef CONFIG_PHY_RAM_BASE_ADDRESS -#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0 -#endif - -#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) - -#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) - -#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) - -#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) -#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420) -#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430) -#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440) -#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450) -#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460) -#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470) - -#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) - -#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) - -#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490) - -#endif diff --git a/arch/blackfin/include/asm/ioctls.h b/arch/blackfin/include/asm/ioctls.h deleted file mode 100644 index eca8d75b0a8..00000000000 --- a/arch/blackfin/include/asm/ioctls.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef __ARCH_BFIN_IOCTLS_H__ -#define __ARCH_BFIN_IOCTLS_H__ - -#define FIOQSIZE 0x545E -#include - -#endif diff --git a/arch/blackfin/include/asm/kvm_para.h b/arch/blackfin/include/asm/kvm_para.h deleted file mode 100644 index 14fab8f0b95..00000000000 --- a/arch/blackfin/include/asm/kvm_para.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/arch/blackfin/include/asm/poll.h b/arch/blackfin/include/asm/poll.h deleted file mode 100644 index 072d8966c5c..00000000000 --- a/arch/blackfin/include/asm/poll.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - * - */ - -#ifndef __BFIN_POLL_H -#define __BFIN_POLL_H - -#define POLLWRNORM 4 /* POLLOUT */ -#define POLLWRBAND 256 - -#include - -#endif diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h deleted file mode 100644 index 1bd3436db6a..00000000000 --- a/arch/blackfin/include/asm/posix_types.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2004-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ARCH_BFIN_POSIX_TYPES_H -#define __ARCH_BFIN_POSIX_TYPES_H - -typedef unsigned short __kernel_mode_t; -#define __kernel_mode_t __kernel_mode_t - -typedef unsigned int __kernel_ipc_pid_t; -#define __kernel_ipc_pid_t __kernel_ipc_pid_t - -typedef unsigned long __kernel_size_t; -typedef long __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -#define __kernel_size_t __kernel_size_t - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -#define __kernel_old_uid_t __kernel_old_uid_t - -typedef unsigned short __kernel_old_dev_t; -#define __kernel_old_dev_t __kernel_old_dev_t - -#include - -#endif diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h index 10d8641180f..14ea93388c0 100644 --- a/arch/blackfin/include/asm/ptrace.h +++ b/arch/blackfin/include/asm/ptrace.h @@ -3,102 +3,13 @@ * * Licensed under the GPL-2 or later. */ - #ifndef _BFIN_PTRACE_H #define _BFIN_PTRACE_H -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 7 are data registers R0-R7 - * 8 - 15 are address registers P0-P7 - * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 - * 32 - 33 A registers A0 & A1 - * 34 - status register - * ----------------------------- - * - * We follows above, except: - * 32-33 --- Low 32-bit of A0&1 - * 34-35 --- High 8-bit of A0&1 - */ +#include #ifndef __ASSEMBLY__ -struct task_struct; - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long orig_pc; - long ipend; - long seqstat; - long rete; - long retn; - long retx; - long pc; /* PC == RETI */ - long rets; - long reserved; /* Used as scratch during system calls */ - long astat; - long lb1; - long lb0; - long lt1; - long lt0; - long lc1; - long lc0; - long a1w; - long a1x; - long a0w; - long a0x; - long b3; - long b2; - long b1; - long b0; - long l3; - long l2; - long l1; - long l0; - long m3; - long m2; - long m1; - long m0; - long i3; - long i2; - long i1; - long i0; - long usp; - long fp; - long p5; - long p4; - long p3; - long p2; - long p1; - long p0; - long r7; - long r6; - long r5; - long r4; - long r3; - long r2; - long r1; - long r0; - long orig_r0; - long orig_p0; - long syscfg; -}; - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 /* ptrace signal */ - -#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ -#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ -#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ - -#define PS_S (0x0002) - -#ifdef __KERNEL__ - /* user_mode returns true if only one bit is set in IPEND, other than the master interrupt enable. */ #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1))) @@ -126,75 +37,5 @@ extern int is_user_addr_valid(struct task_struct *child, #include -#endif /* __KERNEL__ */ - #endif /* __ASSEMBLY__ */ - -/* - * Offsets used by 'ptrace' system call interface. - */ - -#define PT_R0 204 -#define PT_R1 200 -#define PT_R2 196 -#define PT_R3 192 -#define PT_R4 188 -#define PT_R5 184 -#define PT_R6 180 -#define PT_R7 176 -#define PT_P0 172 -#define PT_P1 168 -#define PT_P2 164 -#define PT_P3 160 -#define PT_P4 156 -#define PT_P5 152 -#define PT_FP 148 -#define PT_USP 144 -#define PT_I0 140 -#define PT_I1 136 -#define PT_I2 132 -#define PT_I3 128 -#define PT_M0 124 -#define PT_M1 120 -#define PT_M2 116 -#define PT_M3 112 -#define PT_L0 108 -#define PT_L1 104 -#define PT_L2 100 -#define PT_L3 96 -#define PT_B0 92 -#define PT_B1 88 -#define PT_B2 84 -#define PT_B3 80 -#define PT_A0X 76 -#define PT_A0W 72 -#define PT_A1X 68 -#define PT_A1W 64 -#define PT_LC0 60 -#define PT_LC1 56 -#define PT_LT0 52 -#define PT_LT1 48 -#define PT_LB0 44 -#define PT_LB1 40 -#define PT_ASTAT 36 -#define PT_RESERVED 32 -#define PT_RETS 28 -#define PT_PC 24 -#define PT_RETX 20 -#define PT_RETN 16 -#define PT_RETE 12 -#define PT_SEQSTAT 8 -#define PT_IPEND 4 - -#define PT_ORIG_R0 208 -#define PT_ORIG_P0 212 -#define PT_SYSCFG 216 -#define PT_TEXT_ADDR 220 -#define PT_TEXT_END_ADDR 224 -#define PT_DATA_ADDR 228 -#define PT_FDPIC_EXEC 232 -#define PT_FDPIC_INTERP 236 - -#define PT_LAST_PSEUDO PT_FDPIC_INTERP - #endif /* _BFIN_PTRACE_H */ diff --git a/arch/blackfin/include/asm/sigcontext.h b/arch/blackfin/include/asm/sigcontext.h deleted file mode 100644 index 906bdc1f5fd..00000000000 --- a/arch/blackfin/include/asm/sigcontext.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _ASM_BLACKFIN_SIGCONTEXT_H -#define _ASM_BLACKFIN_SIGCONTEXT_H - -/* Add new entries at the end of the structure only. */ -struct sigcontext { - unsigned long sc_r0; - unsigned long sc_r1; - unsigned long sc_r2; - unsigned long sc_r3; - unsigned long sc_r4; - unsigned long sc_r5; - unsigned long sc_r6; - unsigned long sc_r7; - unsigned long sc_p0; - unsigned long sc_p1; - unsigned long sc_p2; - unsigned long sc_p3; - unsigned long sc_p4; - unsigned long sc_p5; - unsigned long sc_usp; - unsigned long sc_a0w; - unsigned long sc_a1w; - unsigned long sc_a0x; - unsigned long sc_a1x; - unsigned long sc_astat; - unsigned long sc_rets; - unsigned long sc_pc; - unsigned long sc_retx; - unsigned long sc_fp; - unsigned long sc_i0; - unsigned long sc_i1; - unsigned long sc_i2; - unsigned long sc_i3; - unsigned long sc_m0; - unsigned long sc_m1; - unsigned long sc_m2; - unsigned long sc_m3; - unsigned long sc_l0; - unsigned long sc_l1; - unsigned long sc_l2; - unsigned long sc_l3; - unsigned long sc_b0; - unsigned long sc_b1; - unsigned long sc_b2; - unsigned long sc_b3; - unsigned long sc_lc0; - unsigned long sc_lc1; - unsigned long sc_lt0; - unsigned long sc_lt1; - unsigned long sc_lb0; - unsigned long sc_lb1; - unsigned long sc_seqstat; -}; - -#endif diff --git a/arch/blackfin/include/asm/siginfo.h b/arch/blackfin/include/asm/siginfo.h deleted file mode 100644 index 3e81306394e..00000000000 --- a/arch/blackfin/include/asm/siginfo.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2004-2008 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BFIN_SIGINFO_H -#define _BFIN_SIGINFO_H - -#include -#include - -#define UID16_SIGINFO_COMPAT_NEEDED - -#define si_uid16 _sifields._kill._uid - -#define ILL_ILLPARAOP (__SI_FAULT|2) /* illegal opcode combine ********** */ -#define ILL_ILLEXCPT (__SI_FAULT|4) /* unrecoverable exception ********** */ -#define ILL_CPLB_VI (__SI_FAULT|9) /* D/I CPLB protect violation ******** */ -#define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */ -#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */ - -/* - * SIGBUS si_codes - */ -#define BUS_OPFETCH (__SI_FAULT|4) /* error from instruction fetch ******** */ - -/* - * SIGTRAP si_codes - */ -#define TRAP_STEP (__SI_FAULT|1) /* single-step breakpoint************* */ -#define TRAP_TRACEFLOW (__SI_FAULT|2) /* trace buffer overflow ************* */ -#define TRAP_WATCHPT (__SI_FAULT|3) /* watchpoint match ************* */ -#define TRAP_ILLTRAP (__SI_FAULT|4) /* illegal trap ************* */ - -/* - * SIGSEGV si_codes - */ -#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */ - -#endif diff --git a/arch/blackfin/include/asm/signal.h b/arch/blackfin/include/asm/signal.h deleted file mode 100644 index 77a3bf37b69..00000000000 --- a/arch/blackfin/include/asm/signal.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _BLACKFIN_SIGNAL_H -#define _BLACKFIN_SIGNAL_H - -#define SA_RESTORER 0x04000000 -#include - -#endif diff --git a/arch/blackfin/include/asm/stat.h b/arch/blackfin/include/asm/stat.h deleted file mode 100644 index 2e27665c4e9..00000000000 --- a/arch/blackfin/include/asm/stat.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2004-2006 Analog Devices Inc. - * - * Licensed under the GPL-2. - */ - -#ifndef _BFIN_STAT_H -#define _BFIN_STAT_H - -struct stat { - unsigned short st_dev; - unsigned short __pad1; - unsigned long st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned long st_size; - unsigned long st_blksize; - unsigned long st_blocks; - unsigned long st_atime; - unsigned long __unused1; - unsigned long st_mtime; - unsigned long __unused2; - unsigned long st_ctime; - unsigned long __unused3; - unsigned long __unused4; - unsigned long __unused5; -}; - -/* This matches struct stat64 in glibc2.1, hence the absolutely - * insane amounts of padding around dev_t's. - */ -struct stat64 { - unsigned long long st_dev; - unsigned char __pad1[4]; - -#define STAT64_HAS_BROKEN_ST_INO 1 - unsigned long __st_ino; - - unsigned int st_mode; - unsigned int st_nlink; - - unsigned long st_uid; - unsigned long st_gid; - - unsigned long long st_rdev; - unsigned char __pad2[4]; - - long long st_size; - unsigned long st_blksize; - - long long st_blocks; /* Number 512-byte blocks allocated. */ - - unsigned long st_atime; - unsigned long st_atime_nsec; - - unsigned long st_mtime; - unsigned long st_mtime_nsec; - - unsigned long st_ctime; - unsigned long st_ctime_nsec; - - unsigned long long st_ino; -}; - -#endif /* _BFIN_STAT_H */ diff --git a/arch/blackfin/include/asm/swab.h b/arch/blackfin/include/asm/swab.h deleted file mode 100644 index 89de6507ca2..00000000000 --- a/arch/blackfin/include/asm/swab.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef _BLACKFIN_SWAB_H -#define _BLACKFIN_SWAB_H - -#include -#include - -#ifdef __GNUC__ - -static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx) -{ - __u32 tmp; - __asm__("%1 = %0 >> 8 (V);\n\t" - "%0 = %0 << 8 (V);\n\t" - "%0 = %0 | %1;\n\t" - : "+d"(xx), "=&d"(tmp)); - return xx; -} -#define __arch_swahb32 __arch_swahb32 - -static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx) -{ - __u32 rv; - __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx)); - return rv; -} -#define __arch_swahw32 __arch_swahw32 - -static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx) -{ - return __arch_swahb32(__arch_swahw32(xx)); -} -#define __arch_swab32 __arch_swab32 - -static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx) -{ - __u32 xw = xx; - __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw)); - return (__u16)xw; -} -#define __arch_swab16 __arch_swab16 - -#endif /* __GNUC__ */ - -#endif /* _BLACKFIN_SWAB_H */ diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h index 5b2a0748d7d..a5aa9bd5fed 100644 --- a/arch/blackfin/include/asm/unistd.h +++ b/arch/blackfin/include/asm/unistd.h @@ -3,437 +3,11 @@ * * Licensed under the GPL-2 or later. */ - #ifndef __ASM_BFIN_UNISTD_H #define __ASM_BFIN_UNISTD_H -/* - * This file contains the system call numbers. - */ -#define __NR_restart_syscall 0 -#define __NR_exit 1 - /* 2 __NR_fork not supported on nommu */ -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 - /* 7 __NR_waitpid obsolete */ -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_chown 16 - /* 17 __NR_break obsolete */ - /* 18 __NR_oldstat obsolete */ -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 - /* 22 __NR_umount obsolete */ -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 - /* 28 __NR_oldfstat obsolete */ -#define __NR_pause 29 - /* 30 __NR_utime obsolete */ - /* 31 __NR_stty obsolete */ - /* 32 __NR_gtty obsolete */ -#define __NR_access 33 -#define __NR_nice 34 - /* 35 __NR_ftime obsolete */ -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 - /* 44 __NR_prof obsolete */ -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 - /* 48 __NR_signal obsolete */ -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 - /* 53 __NR_lock obsolete */ -#define __NR_ioctl 54 -#define __NR_fcntl 55 - /* 56 __NR_mpx obsolete */ -#define __NR_setpgid 57 - /* 58 __NR_ulimit obsolete */ - /* 59 __NR_oldolduname obsolete */ -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 - /* 67 __NR_sigaction obsolete */ -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 - /* 72 __NR_sigsuspend obsolete */ - /* 73 __NR_sigpending obsolete */ -#define __NR_sethostname 74 -#define __NR_setrlimit 75 - /* 76 __NR_old_getrlimit obsolete */ -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 - /* 82 __NR_select obsolete */ -#define __NR_symlink 83 - /* 84 __NR_oldlstat obsolete */ -#define __NR_readlink 85 - /* 86 __NR_uselib obsolete */ - /* 87 __NR_swapon obsolete */ -#define __NR_reboot 88 - /* 89 __NR_readdir obsolete */ - /* 90 __NR_mmap obsolete */ -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 - /* 98 __NR_profil obsolete */ -#define __NR_statfs 99 -#define __NR_fstatfs 100 - /* 101 __NR_ioperm */ - /* 102 __NR_socketcall obsolete */ -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 - /* 109 __NR_olduname obsolete */ - /* 110 __NR_iopl obsolete */ -#define __NR_vhangup 111 - /* 112 __NR_idle obsolete */ - /* 113 __NR_vm86old */ -#define __NR_wait4 114 - /* 115 __NR_swapoff obsolete */ -#define __NR_sysinfo 116 - /* 117 __NR_ipc oboslete */ -#define __NR_fsync 118 - /* 119 __NR_sigreturn obsolete */ -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 - /* 123 __NR_modify_ldt obsolete */ -#define __NR_adjtimex 124 -#define __NR_mprotect 125 - /* 126 __NR_sigprocmask obsolete */ - /* 127 __NR_create_module obsolete */ -#define __NR_init_module 128 -#define __NR_delete_module 129 - /* 130 __NR_get_kernel_syms obsolete */ -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 - /* 135 was sysfs */ -#define __NR_personality 136 - /* 137 __NR_afs_syscall */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 - /* 142 __NR__newselect obsolete */ -#define __NR_flock 143 - /* 144 __NR_msync obsolete */ -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 - /* 150 __NR_mlock */ - /* 151 __NR_munlock */ - /* 152 __NR_mlockall */ - /* 153 __NR_munlockall */ -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 - /* 166 __NR_vm86 */ - /* 167 __NR_query_module */ - /* 168 __NR_poll */ -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread 180 -#define __NR_pwrite 181 -#define __NR_lchown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 - /* 188 __NR_getpmsg */ - /* 189 __NR_putpmsg */ -#define __NR_vfork 190 -#define __NR_getrlimit 191 -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_chown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_lchown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 - /* 218 __NR_mincore */ - /* 219 __NR_madvise */ -#define __NR_getdents64 220 -#define __NR_fcntl64 221 - /* 222 reserved for TUX */ - /* 223 reserved for TUX */ -#define __NR_gettid 224 -#define __NR_readahead 225 -#define __NR_setxattr 226 -#define __NR_lsetxattr 227 -#define __NR_fsetxattr 228 -#define __NR_getxattr 229 -#define __NR_lgetxattr 230 -#define __NR_fgetxattr 231 -#define __NR_listxattr 232 -#define __NR_llistxattr 233 -#define __NR_flistxattr 234 -#define __NR_removexattr 235 -#define __NR_lremovexattr 236 -#define __NR_fremovexattr 237 -#define __NR_tkill 238 -#define __NR_sendfile64 239 -#define __NR_futex 240 -#define __NR_sched_setaffinity 241 -#define __NR_sched_getaffinity 242 - /* 243 __NR_set_thread_area */ - /* 244 __NR_get_thread_area */ -#define __NR_io_setup 245 -#define __NR_io_destroy 246 -#define __NR_io_getevents 247 -#define __NR_io_submit 248 -#define __NR_io_cancel 249 - /* 250 __NR_alloc_hugepages */ - /* 251 __NR_free_hugepages */ -#define __NR_exit_group 252 -#define __NR_lookup_dcookie 253 -#define __NR_bfin_spinlock 254 - -#define __NR_epoll_create 255 -#define __NR_epoll_ctl 256 -#define __NR_epoll_wait 257 - /* 258 __NR_remap_file_pages */ -#define __NR_set_tid_address 259 -#define __NR_timer_create 260 -#define __NR_timer_settime 261 -#define __NR_timer_gettime 262 -#define __NR_timer_getoverrun 263 -#define __NR_timer_delete 264 -#define __NR_clock_settime 265 -#define __NR_clock_gettime 266 -#define __NR_clock_getres 267 -#define __NR_clock_nanosleep 268 -#define __NR_statfs64 269 -#define __NR_fstatfs64 270 -#define __NR_tgkill 271 -#define __NR_utimes 272 -#define __NR_fadvise64_64 273 - /* 274 __NR_vserver */ - /* 275 __NR_mbind */ - /* 276 __NR_get_mempolicy */ - /* 277 __NR_set_mempolicy */ -#define __NR_mq_open 278 -#define __NR_mq_unlink 279 -#define __NR_mq_timedsend 280 -#define __NR_mq_timedreceive 281 -#define __NR_mq_notify 282 -#define __NR_mq_getsetattr 283 -#define __NR_kexec_load 284 -#define __NR_waitid 285 -#define __NR_add_key 286 -#define __NR_request_key 287 -#define __NR_keyctl 288 -#define __NR_ioprio_set 289 -#define __NR_ioprio_get 290 -#define __NR_inotify_init 291 -#define __NR_inotify_add_watch 292 -#define __NR_inotify_rm_watch 293 - /* 294 __NR_migrate_pages */ -#define __NR_openat 295 -#define __NR_mkdirat 296 -#define __NR_mknodat 297 -#define __NR_fchownat 298 -#define __NR_futimesat 299 -#define __NR_fstatat64 300 -#define __NR_unlinkat 301 -#define __NR_renameat 302 -#define __NR_linkat 303 -#define __NR_symlinkat 304 -#define __NR_readlinkat 305 -#define __NR_fchmodat 306 -#define __NR_faccessat 307 -#define __NR_pselect6 308 -#define __NR_ppoll 309 -#define __NR_unshare 310 - -/* Blackfin private syscalls */ -#define __NR_sram_alloc 311 -#define __NR_sram_free 312 -#define __NR_dma_memcpy 313 - -/* socket syscalls */ -#define __NR_accept 314 -#define __NR_bind 315 -#define __NR_connect 316 -#define __NR_getpeername 317 -#define __NR_getsockname 318 -#define __NR_getsockopt 319 -#define __NR_listen 320 -#define __NR_recv 321 -#define __NR_recvfrom 322 -#define __NR_recvmsg 323 -#define __NR_send 324 -#define __NR_sendmsg 325 -#define __NR_sendto 326 -#define __NR_setsockopt 327 -#define __NR_shutdown 328 -#define __NR_socket 329 -#define __NR_socketpair 330 - -/* sysv ipc syscalls */ -#define __NR_semctl 331 -#define __NR_semget 332 -#define __NR_semop 333 -#define __NR_msgctl 334 -#define __NR_msgget 335 -#define __NR_msgrcv 336 -#define __NR_msgsnd 337 -#define __NR_shmat 338 -#define __NR_shmctl 339 -#define __NR_shmdt 340 -#define __NR_shmget 341 -#define __NR_splice 342 -#define __NR_sync_file_range 343 -#define __NR_tee 344 -#define __NR_vmsplice 345 +#include -#define __NR_epoll_pwait 346 -#define __NR_utimensat 347 -#define __NR_signalfd 348 -#define __NR_timerfd_create 349 -#define __NR_eventfd 350 -#define __NR_pread64 351 -#define __NR_pwrite64 352 -#define __NR_fadvise64 353 -#define __NR_set_robust_list 354 -#define __NR_get_robust_list 355 -#define __NR_fallocate 356 -#define __NR_semtimedop 357 -#define __NR_timerfd_settime 358 -#define __NR_timerfd_gettime 359 -#define __NR_signalfd4 360 -#define __NR_eventfd2 361 -#define __NR_epoll_create1 362 -#define __NR_dup3 363 -#define __NR_pipe2 364 -#define __NR_inotify_init1 365 -#define __NR_preadv 366 -#define __NR_pwritev 367 -#define __NR_rt_tgsigqueueinfo 368 -#define __NR_perf_event_open 369 -#define __NR_recvmmsg 370 -#define __NR_fanotify_init 371 -#define __NR_fanotify_mark 372 -#define __NR_prlimit64 373 -#define __NR_cacheflush 374 -#define __NR_name_to_handle_at 375 -#define __NR_open_by_handle_at 376 -#define __NR_clock_adjtime 377 -#define __NR_syncfs 378 -#define __NR_setns 379 -#define __NR_sendmmsg 380 -#define __NR_process_vm_readv 381 -#define __NR_process_vm_writev 382 - -#define __NR_syscall 383 -#define NR_syscalls __NR_syscall - -/* Old optional stuff no one actually uses */ -#define __IGNORE_sysfs -#define __IGNORE_uselib - -/* Implement the newer interfaces */ -#define __IGNORE_mmap -#define __IGNORE_poll -#define __IGNORE_select -#define __IGNORE_utime - -/* Not relevant on no-mmu */ -#define __IGNORE_swapon -#define __IGNORE_swapoff -#define __IGNORE_msync -#define __IGNORE_mlock -#define __IGNORE_munlock -#define __IGNORE_mlockall -#define __IGNORE_munlockall -#define __IGNORE_mincore -#define __IGNORE_madvise -#define __IGNORE_remap_file_pages -#define __IGNORE_mbind -#define __IGNORE_get_mempolicy -#define __IGNORE_set_mempolicy -#define __IGNORE_migrate_pages -#define __IGNORE_move_pages -#define __IGNORE_getcpu - -#ifdef __KERNEL__ #define __ARCH_WANT_STAT64 #define __ARCH_WANT_SYS_ALARM #define __ARCH_WANT_SYS_GETHOSTNAME @@ -455,6 +29,4 @@ */ #define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall"); -#endif /* __KERNEL__ */ - #endif /* __ASM_BFIN_UNISTD_H */ diff --git a/arch/blackfin/include/uapi/asm/Kbuild b/arch/blackfin/include/uapi/asm/Kbuild index baebb3da1d4..0bd28f77abc 100644 --- a/arch/blackfin/include/uapi/asm/Kbuild +++ b/arch/blackfin/include/uapi/asm/Kbuild @@ -1,3 +1,19 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm +header-y += bfin_sport.h +header-y += byteorder.h +header-y += cachectl.h +header-y += fcntl.h +header-y += fixed_code.h +header-y += ioctls.h +header-y += kvm_para.h +header-y += poll.h +header-y += posix_types.h +header-y += ptrace.h +header-y += sigcontext.h +header-y += siginfo.h +header-y += signal.h +header-y += stat.h +header-y += swab.h +header-y += unistd.h diff --git a/arch/blackfin/include/uapi/asm/bfin_sport.h b/arch/blackfin/include/uapi/asm/bfin_sport.h new file mode 100644 index 00000000000..c086de87ee6 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/bfin_sport.h @@ -0,0 +1,136 @@ +/* + * bfin_sport.h - interface to Blackfin SPORTs + * + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _UAPI__BFIN_SPORT_H__ +#define _UAPI__BFIN_SPORT_H__ + +/* Sport mode: it can be set to TDM, i2s or others */ +#define NORM_MODE 0x0 +#define TDM_MODE 0x1 +#define I2S_MODE 0x2 +#define NDSO_MODE 0x3 + +/* Data format, normal, a-law or u-law */ +#define NORM_FORMAT 0x0 +#define ALAW_FORMAT 0x2 +#define ULAW_FORMAT 0x3 + +/* Function driver which use sport must initialize the structure */ +struct sport_config { + /* TDM (multichannels), I2S or other mode */ + unsigned int mode:3; + unsigned int polled; /* use poll instead of irq when set */ + + /* if TDM mode is selected, channels must be set */ + int channels; /* Must be in 8 units */ + unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */ + + /* I2S mode */ + unsigned int right_first:1; /* Right stereo channel first */ + + /* In mormal mode, the following item need to be set */ + unsigned int lsb_first:1; /* order of transmit or receive data */ + unsigned int fsync:1; /* Frame sync required */ + unsigned int data_indep:1; /* data independent frame sync generated */ + unsigned int act_low:1; /* Active low TFS */ + unsigned int late_fsync:1; /* Late frame sync */ + unsigned int tckfe:1; + unsigned int sec_en:1; /* Secondary side enabled */ + + /* Choose clock source */ + unsigned int int_clk:1; /* Internal or external clock */ + + /* If external clock is used, the following fields are ignored */ + int serial_clk; + int fsync_clk; + + unsigned int data_format:2; /* Normal, u-law or a-law */ + + int word_len; /* How length of the word in bits, 3-32 bits */ + int dma_enabled; +}; + +/* Userspace interface */ +#define SPORT_IOC_MAGIC 'P' +#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) +#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long) +#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long) + + +/* SPORT_TCR1 Masks */ +#define TSPEN 0x0001 /* TX enable */ +#define ITCLK 0x0002 /* Internal TX Clock Select */ +#define TDTYPE 0x000C /* TX Data Formatting Select */ +#define DTYPE_NORM 0x0000 /* Data Format Normal */ +#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ +#define DTYPE_ALAW 0x000C /* Compand Using A-Law */ +#define TLSBIT 0x0010 /* TX Bit Order */ +#define ITFS 0x0200 /* Internal TX Frame Sync Select */ +#define TFSR 0x0400 /* TX Frame Sync Required Select */ +#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */ +#define LTFS 0x1000 /* Low TX Frame Sync Select */ +#define LATFS 0x2000 /* Late TX Frame Sync Select */ +#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ + +/* SPORT_TCR2 Masks */ +#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */ +#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x) +#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x) +#define TXSE 0x0100 /* TX Secondary Enable */ +#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */ +#define TRFST 0x0400 /* TX Right-First Data Order */ + +/* SPORT_RCR1 Masks */ +#define RSPEN 0x0001 /* RX enable */ +#define IRCLK 0x0002 /* Internal RX Clock Select */ +#define RDTYPE 0x000C /* RX Data Formatting Select */ +/* DTYPE_* defined above */ +#define RLSBIT 0x0010 /* RX Bit Order */ +#define IRFS 0x0200 /* Internal RX Frame Sync Select */ +#define RFSR 0x0400 /* RX Frame Sync Required Select */ +#define LRFS 0x1000 /* Low RX Frame Sync Select */ +#define LARFS 0x2000 /* Late RX Frame Sync Select */ +#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ + +/* SPORT_RCR2 Masks */ +/* SLEN defined above */ +#define RXSE 0x0100 /* RX Secondary Enable */ +#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ +#define RRFST 0x0400 /* Right-First Data Order */ + +/* SPORT_STAT Masks */ +#define RXNE 0x0001 /* RX FIFO Not Empty Status */ +#define RUVF 0x0002 /* RX Underflow Status */ +#define ROVF 0x0004 /* RX Overflow Status */ +#define TXF 0x0008 /* TX FIFO Full Status */ +#define TUVF 0x0010 /* TX Underflow Status */ +#define TOVF 0x0020 /* TX Overflow Status */ +#define TXHRE 0x0040 /* TX Hold Register Empty */ + +/* SPORT_MCMC1 Masks */ +#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */ +#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x) +#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x) +#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */ +#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x) +#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x) + +/* SPORT_MCMC2 Masks */ +#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */ +#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ +#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ +#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ +#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ +#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ +#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ +#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ +#define MFD 0xF000 /* Multichannel Frame Delay */ +#define DP_MFD(x) BFIN_DEPOSIT(MFD, x) +#define EX_MFD(x) BFIN_EXTRACT(MFD, x) + +#endif /* _UAPI__BFIN_SPORT_H__ */ diff --git a/arch/blackfin/include/uapi/asm/byteorder.h b/arch/blackfin/include/uapi/asm/byteorder.h new file mode 100644 index 00000000000..9558416d578 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/byteorder.h @@ -0,0 +1 @@ +#include diff --git a/arch/blackfin/include/uapi/asm/cachectl.h b/arch/blackfin/include/uapi/asm/cachectl.h new file mode 100644 index 00000000000..03255df6c1e --- /dev/null +++ b/arch/blackfin/include/uapi/asm/cachectl.h @@ -0,0 +1,20 @@ +/* + * based on the mips/cachectl.h + * + * Copyright 2010 Analog Devices Inc. + * Copyright (C) 1994, 1995, 1996 by Ralf Baechle + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE (1<<0) /* flush instruction cache */ +#define DCACHE (1<<1) /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _ASM_CACHECTL */ diff --git a/arch/blackfin/include/uapi/asm/fcntl.h b/arch/blackfin/include/uapi/asm/fcntl.h new file mode 100644 index 00000000000..251c911d59c --- /dev/null +++ b/arch/blackfin/include/uapi/asm/fcntl.h @@ -0,0 +1,17 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_FCNTL_H +#define _BFIN_FCNTL_H + +#define O_DIRECTORY 040000 /* must be a directory */ +#define O_NOFOLLOW 0100000 /* don't follow links */ +#define O_DIRECT 0200000 /* direct disk access hint - currently ignored */ +#define O_LARGEFILE 0400000 + +#include + +#endif diff --git a/arch/blackfin/include/uapi/asm/fixed_code.h b/arch/blackfin/include/uapi/asm/fixed_code.h new file mode 100644 index 00000000000..3bef1dca379 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/fixed_code.h @@ -0,0 +1,38 @@ +/* + * This file defines the fixed addresses where userspace programs + * can find atomic code sequences. + * + * Copyright 2007-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _UAPI__BFIN_ASM_FIXED_CODE_H__ +#define _UAPI__BFIN_ASM_FIXED_CODE_H__ + + +#ifndef CONFIG_PHY_RAM_BASE_ADDRESS +#define CONFIG_PHY_RAM_BASE_ADDRESS 0x0 +#endif + +#define FIXED_CODE_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) + +#define SIGRETURN_STUB (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400) + +#define ATOMIC_SEQS_START (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) + +#define ATOMIC_XCHG32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410) +#define ATOMIC_CAS32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420) +#define ATOMIC_ADD32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430) +#define ATOMIC_SUB32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440) +#define ATOMIC_IOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450) +#define ATOMIC_AND32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460) +#define ATOMIC_XOR32 (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470) + +#define ATOMIC_SEQS_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) + +#define SAFE_USER_INSTRUCTION (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480) + +#define FIXED_CODE_END (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490) + +#endif /* _UAPI__BFIN_ASM_FIXED_CODE_H__ */ diff --git a/arch/blackfin/include/uapi/asm/ioctls.h b/arch/blackfin/include/uapi/asm/ioctls.h new file mode 100644 index 00000000000..eca8d75b0a8 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/ioctls.h @@ -0,0 +1,7 @@ +#ifndef __ARCH_BFIN_IOCTLS_H__ +#define __ARCH_BFIN_IOCTLS_H__ + +#define FIOQSIZE 0x545E +#include + +#endif diff --git a/arch/blackfin/include/uapi/asm/kvm_para.h b/arch/blackfin/include/uapi/asm/kvm_para.h new file mode 100644 index 00000000000..14fab8f0b95 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/kvm_para.h @@ -0,0 +1 @@ +#include diff --git a/arch/blackfin/include/uapi/asm/poll.h b/arch/blackfin/include/uapi/asm/poll.h new file mode 100644 index 00000000000..072d8966c5c --- /dev/null +++ b/arch/blackfin/include/uapi/asm/poll.h @@ -0,0 +1,16 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + * + */ + +#ifndef __BFIN_POLL_H +#define __BFIN_POLL_H + +#define POLLWRNORM 4 /* POLLOUT */ +#define POLLWRBAND 256 + +#include + +#endif diff --git a/arch/blackfin/include/uapi/asm/posix_types.h b/arch/blackfin/include/uapi/asm/posix_types.h new file mode 100644 index 00000000000..1bd3436db6a --- /dev/null +++ b/arch/blackfin/include/uapi/asm/posix_types.h @@ -0,0 +1,30 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_BFIN_POSIX_TYPES_H +#define __ARCH_BFIN_POSIX_TYPES_H + +typedef unsigned short __kernel_mode_t; +#define __kernel_mode_t __kernel_mode_t + +typedef unsigned int __kernel_ipc_pid_t; +#define __kernel_ipc_pid_t __kernel_ipc_pid_t + +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +#define __kernel_size_t __kernel_size_t + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +#define __kernel_old_uid_t __kernel_old_uid_t + +typedef unsigned short __kernel_old_dev_t; +#define __kernel_old_dev_t __kernel_old_dev_t + +#include + +#endif diff --git a/arch/blackfin/include/uapi/asm/ptrace.h b/arch/blackfin/include/uapi/asm/ptrace.h new file mode 100644 index 00000000000..fd48bd0739d --- /dev/null +++ b/arch/blackfin/include/uapi/asm/ptrace.h @@ -0,0 +1,170 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _UAPI_BFIN_PTRACE_H +#define _UAPI_BFIN_PTRACE_H + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 7 are data registers R0-R7 + * 8 - 15 are address registers P0-P7 + * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3 + * 32 - 33 A registers A0 & A1 + * 34 - status register + * ----------------------------- + * + * We follows above, except: + * 32-33 --- Low 32-bit of A0&1 + * 34-35 --- High 8-bit of A0&1 + */ + +#ifndef __ASSEMBLY__ + +struct task_struct; + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long orig_pc; + long ipend; + long seqstat; + long rete; + long retn; + long retx; + long pc; /* PC == RETI */ + long rets; + long reserved; /* Used as scratch during system calls */ + long astat; + long lb1; + long lb0; + long lt1; + long lt0; + long lc1; + long lc0; + long a1w; + long a1x; + long a0w; + long a0x; + long b3; + long b2; + long b1; + long b0; + long l3; + long l2; + long l1; + long l0; + long m3; + long m2; + long m1; + long m0; + long i3; + long i2; + long i1; + long i0; + long usp; + long fp; + long p5; + long p4; + long p3; + long p2; + long p1; + long p0; + long r7; + long r6; + long r5; + long r4; + long r3; + long r2; + long r1; + long r0; + long orig_r0; + long orig_p0; + long syscfg; +}; + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 /* ptrace signal */ + +#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ +#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ +#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ + +#define PS_S (0x0002) + + +#endif /* __ASSEMBLY__ */ + +/* + * Offsets used by 'ptrace' system call interface. + */ + +#define PT_R0 204 +#define PT_R1 200 +#define PT_R2 196 +#define PT_R3 192 +#define PT_R4 188 +#define PT_R5 184 +#define PT_R6 180 +#define PT_R7 176 +#define PT_P0 172 +#define PT_P1 168 +#define PT_P2 164 +#define PT_P3 160 +#define PT_P4 156 +#define PT_P5 152 +#define PT_FP 148 +#define PT_USP 144 +#define PT_I0 140 +#define PT_I1 136 +#define PT_I2 132 +#define PT_I3 128 +#define PT_M0 124 +#define PT_M1 120 +#define PT_M2 116 +#define PT_M3 112 +#define PT_L0 108 +#define PT_L1 104 +#define PT_L2 100 +#define PT_L3 96 +#define PT_B0 92 +#define PT_B1 88 +#define PT_B2 84 +#define PT_B3 80 +#define PT_A0X 76 +#define PT_A0W 72 +#define PT_A1X 68 +#define PT_A1W 64 +#define PT_LC0 60 +#define PT_LC1 56 +#define PT_LT0 52 +#define PT_LT1 48 +#define PT_LB0 44 +#define PT_LB1 40 +#define PT_ASTAT 36 +#define PT_RESERVED 32 +#define PT_RETS 28 +#define PT_PC 24 +#define PT_RETX 20 +#define PT_RETN 16 +#define PT_RETE 12 +#define PT_SEQSTAT 8 +#define PT_IPEND 4 + +#define PT_ORIG_R0 208 +#define PT_ORIG_P0 212 +#define PT_SYSCFG 216 +#define PT_TEXT_ADDR 220 +#define PT_TEXT_END_ADDR 224 +#define PT_DATA_ADDR 228 +#define PT_FDPIC_EXEC 232 +#define PT_FDPIC_INTERP 236 + +#define PT_LAST_PSEUDO PT_FDPIC_INTERP + +#endif /* _UAPI_BFIN_PTRACE_H */ diff --git a/arch/blackfin/include/uapi/asm/sigcontext.h b/arch/blackfin/include/uapi/asm/sigcontext.h new file mode 100644 index 00000000000..906bdc1f5fd --- /dev/null +++ b/arch/blackfin/include/uapi/asm/sigcontext.h @@ -0,0 +1,61 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _ASM_BLACKFIN_SIGCONTEXT_H +#define _ASM_BLACKFIN_SIGCONTEXT_H + +/* Add new entries at the end of the structure only. */ +struct sigcontext { + unsigned long sc_r0; + unsigned long sc_r1; + unsigned long sc_r2; + unsigned long sc_r3; + unsigned long sc_r4; + unsigned long sc_r5; + unsigned long sc_r6; + unsigned long sc_r7; + unsigned long sc_p0; + unsigned long sc_p1; + unsigned long sc_p2; + unsigned long sc_p3; + unsigned long sc_p4; + unsigned long sc_p5; + unsigned long sc_usp; + unsigned long sc_a0w; + unsigned long sc_a1w; + unsigned long sc_a0x; + unsigned long sc_a1x; + unsigned long sc_astat; + unsigned long sc_rets; + unsigned long sc_pc; + unsigned long sc_retx; + unsigned long sc_fp; + unsigned long sc_i0; + unsigned long sc_i1; + unsigned long sc_i2; + unsigned long sc_i3; + unsigned long sc_m0; + unsigned long sc_m1; + unsigned long sc_m2; + unsigned long sc_m3; + unsigned long sc_l0; + unsigned long sc_l1; + unsigned long sc_l2; + unsigned long sc_l3; + unsigned long sc_b0; + unsigned long sc_b1; + unsigned long sc_b2; + unsigned long sc_b3; + unsigned long sc_lc0; + unsigned long sc_lc1; + unsigned long sc_lt0; + unsigned long sc_lt1; + unsigned long sc_lb0; + unsigned long sc_lb1; + unsigned long sc_seqstat; +}; + +#endif diff --git a/arch/blackfin/include/uapi/asm/siginfo.h b/arch/blackfin/include/uapi/asm/siginfo.h new file mode 100644 index 00000000000..3e81306394e --- /dev/null +++ b/arch/blackfin/include/uapi/asm/siginfo.h @@ -0,0 +1,41 @@ +/* + * Copyright 2004-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BFIN_SIGINFO_H +#define _BFIN_SIGINFO_H + +#include +#include + +#define UID16_SIGINFO_COMPAT_NEEDED + +#define si_uid16 _sifields._kill._uid + +#define ILL_ILLPARAOP (__SI_FAULT|2) /* illegal opcode combine ********** */ +#define ILL_ILLEXCPT (__SI_FAULT|4) /* unrecoverable exception ********** */ +#define ILL_CPLB_VI (__SI_FAULT|9) /* D/I CPLB protect violation ******** */ +#define ILL_CPLB_MISS (__SI_FAULT|10) /* D/I CPLB miss ******** */ +#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */ + +/* + * SIGBUS si_codes + */ +#define BUS_OPFETCH (__SI_FAULT|4) /* error from instruction fetch ******** */ + +/* + * SIGTRAP si_codes + */ +#define TRAP_STEP (__SI_FAULT|1) /* single-step breakpoint************* */ +#define TRAP_TRACEFLOW (__SI_FAULT|2) /* trace buffer overflow ************* */ +#define TRAP_WATCHPT (__SI_FAULT|3) /* watchpoint match ************* */ +#define TRAP_ILLTRAP (__SI_FAULT|4) /* illegal trap ************* */ + +/* + * SIGSEGV si_codes + */ +#define SEGV_STACKFLOW (__SI_FAULT|3) /* stack overflow */ + +#endif diff --git a/arch/blackfin/include/uapi/asm/signal.h b/arch/blackfin/include/uapi/asm/signal.h new file mode 100644 index 00000000000..77a3bf37b69 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/signal.h @@ -0,0 +1,7 @@ +#ifndef _BLACKFIN_SIGNAL_H +#define _BLACKFIN_SIGNAL_H + +#define SA_RESTORER 0x04000000 +#include + +#endif diff --git a/arch/blackfin/include/uapi/asm/stat.h b/arch/blackfin/include/uapi/asm/stat.h new file mode 100644 index 00000000000..2e27665c4e9 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/stat.h @@ -0,0 +1,69 @@ +/* + * Copyright 2004-2006 Analog Devices Inc. + * + * Licensed under the GPL-2. + */ + +#ifndef _BFIN_STAT_H +#define _BFIN_STAT_H + +struct stat { + unsigned short st_dev; + unsigned short __pad1; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned short __pad2; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long __unused1; + unsigned long st_mtime; + unsigned long __unused2; + unsigned long st_ctime; + unsigned long __unused3; + unsigned long __unused4; + unsigned long __unused5; +}; + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad1[4]; + +#define STAT64_HAS_BROKEN_ST_INO 1 + unsigned long __st_ino; + + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad2[4]; + + long long st_size; + unsigned long st_blksize; + + long long st_blocks; /* Number 512-byte blocks allocated. */ + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned long st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; + + unsigned long long st_ino; +}; + +#endif /* _BFIN_STAT_H */ diff --git a/arch/blackfin/include/uapi/asm/swab.h b/arch/blackfin/include/uapi/asm/swab.h new file mode 100644 index 00000000000..89de6507ca2 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/swab.h @@ -0,0 +1,50 @@ +/* + * Copyright 2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _BLACKFIN_SWAB_H +#define _BLACKFIN_SWAB_H + +#include +#include + +#ifdef __GNUC__ + +static __inline__ __attribute_const__ __u32 __arch_swahb32(__u32 xx) +{ + __u32 tmp; + __asm__("%1 = %0 >> 8 (V);\n\t" + "%0 = %0 << 8 (V);\n\t" + "%0 = %0 | %1;\n\t" + : "+d"(xx), "=&d"(tmp)); + return xx; +} +#define __arch_swahb32 __arch_swahb32 + +static __inline__ __attribute_const__ __u32 __arch_swahw32(__u32 xx) +{ + __u32 rv; + __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx)); + return rv; +} +#define __arch_swahw32 __arch_swahw32 + +static __inline__ __attribute_const__ __u32 __arch_swab32(__u32 xx) +{ + return __arch_swahb32(__arch_swahw32(xx)); +} +#define __arch_swab32 __arch_swab32 + +static __inline__ __attribute_const__ __u16 __arch_swab16(__u16 xx) +{ + __u32 xw = xx; + __asm__("%0 <<= 8;\n %0.L = %0.L + %0.H (NS);\n": "+d"(xw)); + return (__u16)xw; +} +#define __arch_swab16 __arch_swab16 + +#endif /* __GNUC__ */ + +#endif /* _BLACKFIN_SWAB_H */ diff --git a/arch/blackfin/include/uapi/asm/unistd.h b/arch/blackfin/include/uapi/asm/unistd.h new file mode 100644 index 00000000000..a4511649a86 --- /dev/null +++ b/arch/blackfin/include/uapi/asm/unistd.h @@ -0,0 +1,437 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef _UAPI__ASM_BFIN_UNISTD_H +#define _UAPI__ASM_BFIN_UNISTD_H +/* + * This file contains the system call numbers. + */ +#define __NR_restart_syscall 0 +#define __NR_exit 1 + /* 2 __NR_fork not supported on nommu */ +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 + /* 7 __NR_waitpid obsolete */ +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_chown 16 + /* 17 __NR_break obsolete */ + /* 18 __NR_oldstat obsolete */ +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 + /* 22 __NR_umount obsolete */ +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 + /* 28 __NR_oldfstat obsolete */ +#define __NR_pause 29 + /* 30 __NR_utime obsolete */ + /* 31 __NR_stty obsolete */ + /* 32 __NR_gtty obsolete */ +#define __NR_access 33 +#define __NR_nice 34 + /* 35 __NR_ftime obsolete */ +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 + /* 44 __NR_prof obsolete */ +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 + /* 48 __NR_signal obsolete */ +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 + /* 53 __NR_lock obsolete */ +#define __NR_ioctl 54 +#define __NR_fcntl 55 + /* 56 __NR_mpx obsolete */ +#define __NR_setpgid 57 + /* 58 __NR_ulimit obsolete */ + /* 59 __NR_oldolduname obsolete */ +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 + /* 67 __NR_sigaction obsolete */ +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 + /* 72 __NR_sigsuspend obsolete */ + /* 73 __NR_sigpending obsolete */ +#define __NR_sethostname 74 +#define __NR_setrlimit 75 + /* 76 __NR_old_getrlimit obsolete */ +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 + /* 82 __NR_select obsolete */ +#define __NR_symlink 83 + /* 84 __NR_oldlstat obsolete */ +#define __NR_readlink 85 + /* 86 __NR_uselib obsolete */ + /* 87 __NR_swapon obsolete */ +#define __NR_reboot 88 + /* 89 __NR_readdir obsolete */ + /* 90 __NR_mmap obsolete */ +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 + /* 98 __NR_profil obsolete */ +#define __NR_statfs 99 +#define __NR_fstatfs 100 + /* 101 __NR_ioperm */ + /* 102 __NR_socketcall obsolete */ +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 + /* 109 __NR_olduname obsolete */ + /* 110 __NR_iopl obsolete */ +#define __NR_vhangup 111 + /* 112 __NR_idle obsolete */ + /* 113 __NR_vm86old */ +#define __NR_wait4 114 + /* 115 __NR_swapoff obsolete */ +#define __NR_sysinfo 116 + /* 117 __NR_ipc oboslete */ +#define __NR_fsync 118 + /* 119 __NR_sigreturn obsolete */ +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 + /* 123 __NR_modify_ldt obsolete */ +#define __NR_adjtimex 124 +#define __NR_mprotect 125 + /* 126 __NR_sigprocmask obsolete */ + /* 127 __NR_create_module obsolete */ +#define __NR_init_module 128 +#define __NR_delete_module 129 + /* 130 __NR_get_kernel_syms obsolete */ +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 + /* 135 was sysfs */ +#define __NR_personality 136 + /* 137 __NR_afs_syscall */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 + /* 142 __NR__newselect obsolete */ +#define __NR_flock 143 + /* 144 __NR_msync obsolete */ +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 + /* 150 __NR_mlock */ + /* 151 __NR_munlock */ + /* 152 __NR_mlockall */ + /* 153 __NR_munlockall */ +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 + /* 166 __NR_vm86 */ + /* 167 __NR_query_module */ + /* 168 __NR_poll */ +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread 180 +#define __NR_pwrite 181 +#define __NR_lchown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 + /* 188 __NR_getpmsg */ + /* 189 __NR_putpmsg */ +#define __NR_vfork 190 +#define __NR_getrlimit 191 +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_chown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_lchown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 + /* 218 __NR_mincore */ + /* 219 __NR_madvise */ +#define __NR_getdents64 220 +#define __NR_fcntl64 221 + /* 222 reserved for TUX */ + /* 223 reserved for TUX */ +#define __NR_gettid 224 +#define __NR_readahead 225 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 + /* 243 __NR_set_thread_area */ + /* 244 __NR_get_thread_area */ +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 + /* 250 __NR_alloc_hugepages */ + /* 251 __NR_free_hugepages */ +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_bfin_spinlock 254 + +#define __NR_epoll_create 255 +#define __NR_epoll_ctl 256 +#define __NR_epoll_wait 257 + /* 258 __NR_remap_file_pages */ +#define __NR_set_tid_address 259 +#define __NR_timer_create 260 +#define __NR_timer_settime 261 +#define __NR_timer_gettime 262 +#define __NR_timer_getoverrun 263 +#define __NR_timer_delete 264 +#define __NR_clock_settime 265 +#define __NR_clock_gettime 266 +#define __NR_clock_getres 267 +#define __NR_clock_nanosleep 268 +#define __NR_statfs64 269 +#define __NR_fstatfs64 270 +#define __NR_tgkill 271 +#define __NR_utimes 272 +#define __NR_fadvise64_64 273 + /* 274 __NR_vserver */ + /* 275 __NR_mbind */ + /* 276 __NR_get_mempolicy */ + /* 277 __NR_set_mempolicy */ +#define __NR_mq_open 278 +#define __NR_mq_unlink 279 +#define __NR_mq_timedsend 280 +#define __NR_mq_timedreceive 281 +#define __NR_mq_notify 282 +#define __NR_mq_getsetattr 283 +#define __NR_kexec_load 284 +#define __NR_waitid 285 +#define __NR_add_key 286 +#define __NR_request_key 287 +#define __NR_keyctl 288 +#define __NR_ioprio_set 289 +#define __NR_ioprio_get 290 +#define __NR_inotify_init 291 +#define __NR_inotify_add_watch 292 +#define __NR_inotify_rm_watch 293 + /* 294 __NR_migrate_pages */ +#define __NR_openat 295 +#define __NR_mkdirat 296 +#define __NR_mknodat 297 +#define __NR_fchownat 298 +#define __NR_futimesat 299 +#define __NR_fstatat64 300 +#define __NR_unlinkat 301 +#define __NR_renameat 302 +#define __NR_linkat 303 +#define __NR_symlinkat 304 +#define __NR_readlinkat 305 +#define __NR_fchmodat 306 +#define __NR_faccessat 307 +#define __NR_pselect6 308 +#define __NR_ppoll 309 +#define __NR_unshare 310 + +/* Blackfin private syscalls */ +#define __NR_sram_alloc 311 +#define __NR_sram_free 312 +#define __NR_dma_memcpy 313 + +/* socket syscalls */ +#define __NR_accept 314 +#define __NR_bind 315 +#define __NR_connect 316 +#define __NR_getpeername 317 +#define __NR_getsockname 318 +#define __NR_getsockopt 319 +#define __NR_listen 320 +#define __NR_recv 321 +#define __NR_recvfrom 322 +#define __NR_recvmsg 323 +#define __NR_send 324 +#define __NR_sendmsg 325 +#define __NR_sendto 326 +#define __NR_setsockopt 327 +#define __NR_shutdown 328 +#define __NR_socket 329 +#define __NR_socketpair 330 + +/* sysv ipc syscalls */ +#define __NR_semctl 331 +#define __NR_semget 332 +#define __NR_semop 333 +#define __NR_msgctl 334 +#define __NR_msgget 335 +#define __NR_msgrcv 336 +#define __NR_msgsnd 337 +#define __NR_shmat 338 +#define __NR_shmctl 339 +#define __NR_shmdt 340 +#define __NR_shmget 341 + +#define __NR_splice 342 +#define __NR_sync_file_range 343 +#define __NR_tee 344 +#define __NR_vmsplice 345 + +#define __NR_epoll_pwait 346 +#define __NR_utimensat 347 +#define __NR_signalfd 348 +#define __NR_timerfd_create 349 +#define __NR_eventfd 350 +#define __NR_pread64 351 +#define __NR_pwrite64 352 +#define __NR_fadvise64 353 +#define __NR_set_robust_list 354 +#define __NR_get_robust_list 355 +#define __NR_fallocate 356 +#define __NR_semtimedop 357 +#define __NR_timerfd_settime 358 +#define __NR_timerfd_gettime 359 +#define __NR_signalfd4 360 +#define __NR_eventfd2 361 +#define __NR_epoll_create1 362 +#define __NR_dup3 363 +#define __NR_pipe2 364 +#define __NR_inotify_init1 365 +#define __NR_preadv 366 +#define __NR_pwritev 367 +#define __NR_rt_tgsigqueueinfo 368 +#define __NR_perf_event_open 369 +#define __NR_recvmmsg 370 +#define __NR_fanotify_init 371 +#define __NR_fanotify_mark 372 +#define __NR_prlimit64 373 +#define __NR_cacheflush 374 +#define __NR_name_to_handle_at 375 +#define __NR_open_by_handle_at 376 +#define __NR_clock_adjtime 377 +#define __NR_syncfs 378 +#define __NR_setns 379 +#define __NR_sendmmsg 380 +#define __NR_process_vm_readv 381 +#define __NR_process_vm_writev 382 + +#define __NR_syscall 383 +#define NR_syscalls __NR_syscall + +/* Old optional stuff no one actually uses */ +#define __IGNORE_sysfs +#define __IGNORE_uselib + +/* Implement the newer interfaces */ +#define __IGNORE_mmap +#define __IGNORE_poll +#define __IGNORE_select +#define __IGNORE_utime + +/* Not relevant on no-mmu */ +#define __IGNORE_swapon +#define __IGNORE_swapoff +#define __IGNORE_msync +#define __IGNORE_mlock +#define __IGNORE_munlock +#define __IGNORE_mlockall +#define __IGNORE_munlockall +#define __IGNORE_mincore +#define __IGNORE_madvise +#define __IGNORE_remap_file_pages +#define __IGNORE_mbind +#define __IGNORE_get_mempolicy +#define __IGNORE_set_mempolicy +#define __IGNORE_migrate_pages +#define __IGNORE_move_pages +#define __IGNORE_getcpu + + +#endif /* _UAPI__ASM_BFIN_UNISTD_H */ -- cgit v1.2.3-70-g09d2 From e9dfcdbd76b14a24e751d6e0bfb29dc262c69b0c Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Fri, 12 Oct 2012 22:26:36 -0400 Subject: blackfin: Use Kbuild infrastructure for kvm_para.h All the headers but kvm_para.h use the Kbuild infrastructure to get to the asm-generic headers. Cc: linux-kbuild@vger.kernel.org Cc: uclinux-dist-devel@blackfin.uclinux.org Cc: Mike Frysinger Signed-off-by: Steven Rostedt Signed-off-by: Bob Liu --- arch/blackfin/include/asm/Kbuild | 1 + arch/blackfin/include/uapi/asm/kvm_para.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) delete mode 100644 arch/blackfin/include/uapi/asm/kvm_para.h (limited to 'arch') diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index 7ce56f5f6dd..9d1f5b381b8 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild @@ -16,6 +16,7 @@ generic-y += ipcbuf.h generic-y += irq_regs.h generic-y += kdebug.h generic-y += kmap_types.h +generic-y += kvm_para.h generic-y += local64.h generic-y += local.h generic-y += mman.h diff --git a/arch/blackfin/include/uapi/asm/kvm_para.h b/arch/blackfin/include/uapi/asm/kvm_para.h deleted file mode 100644 index 14fab8f0b95..00000000000 --- a/arch/blackfin/include/uapi/asm/kvm_para.h +++ /dev/null @@ -1 +0,0 @@ -#include -- cgit v1.2.3-70-g09d2 From d95dcaa06ba895ec379d80b35c25ddba3a71943a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 17 Oct 2012 16:28:02 +0200 Subject: Blackfin: Annotate strncpy_from_user src parameter with __user The src parameter of strncpy_from_user is supposed to take a string from userspace, so it should be annotated with __user. Doing so fixes the following and similar warnings from sparse: kernel/sys.c:491:51: warning: incorrect type in argument 2 (different address spaces) kernel/sys.c:491:51: expected char const *src kernel/sys.c:491:51: got void [noderef] *arg kernel/sys.c:2061:54: warning: incorrect type in argument 2 (different address spaces) kernel/sys.c:2061:54: expected char const *src kernel/sys.c:2061:54: got char [noderef] * Signed-off-by: Lars-Peter Clausen Signed-off-by: Bob Liu --- arch/blackfin/include/asm/uaccess.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 5cc11150282..3edb4afa305 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -216,12 +216,12 @@ copy_to_user(void __user *to, const void *from, unsigned long n) */ static inline long __must_check -strncpy_from_user(char *dst, const char *src, long count) +strncpy_from_user(char *dst, const char __user *src, long count) { char *tmp; if (!access_ok(VERIFY_READ, src, 1)) return -EFAULT; - strncpy(dst, src, count); + strncpy(dst, (const char __force *)src, count); for (tmp = dst; *tmp && count > 0; tmp++, count--) ; return (tmp - dst); } -- cgit v1.2.3-70-g09d2 From aff06631da3c8349149fe4214091735b35294151 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 22 Oct 2012 16:09:03 +0200 Subject: Blackfin: Add missing __user annotations to put_user typeof() will not inherit the __user annotation so we have to explicitly specify this for '_p'. This fixes the following and quite a few similar warnings from spatch: kernel/sys.c:884:26: warning: incorrect type in initializer (different address spaces) kernel/sys.c:884:26: expected unsigned int *_p kernel/sys.c:884:26: got unsigned int [noderef] [usertype] *ruidp kernel/sys.c:885:26: warning: incorrect type in initializer (different address spaces) kernel/sys.c:885:26: expected unsigned int *_p kernel/sys.c:885:26: got unsigned int [noderef] [usertype] *euidp kernel/sys.c:886:26: warning: incorrect type in initializer (different address spaces) kernel/sys.c:886:26: expected unsigned int *_p kernel/sys.c:886:26: got unsigned int [noderef] [usertype] *suidp Signed-off-by: Lars-Peter Clausen Signed-off-by: Bob Liu --- arch/blackfin/include/asm/uaccess.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 3edb4afa305..90f32c2a65b 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -89,7 +89,7 @@ struct exception_table_entry { ({ \ int _err = 0; \ typeof(*(p)) _x = (x); \ - typeof(*(p)) *_p = (p); \ + typeof(*(p)) __user *_p = (p); \ if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\ _err = -EFAULT; \ } \ @@ -108,8 +108,8 @@ struct exception_table_entry { long _xl, _xh; \ _xl = ((long *)&_x)[0]; \ _xh = ((long *)&_x)[1]; \ - __put_user_asm(_xl, ((long *)_p)+0, ); \ - __put_user_asm(_xh, ((long *)_p)+1, ); \ + __put_user_asm(_xl, ((long __user *)_p)+0, ); \ + __put_user_asm(_xh, ((long __user *)_p)+1, ); \ } break; \ default: \ _err = __put_user_bad(); \ @@ -136,7 +136,7 @@ static inline int bad_user_access_length(void) * aliasing issues. */ -#define __ptr(x) ((unsigned long *)(x)) +#define __ptr(x) ((unsigned long __force *)(x)) #define __put_user_asm(x,p,bhw) \ __asm__ (#bhw"[%1] = %0;\n\t" \ -- cgit v1.2.3-70-g09d2 From 10dc42b5b262f3bb2e4532759e4e1147ebf6a22f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 22 Oct 2012 16:09:04 +0200 Subject: Blackfin: Annotate clear_user 'to' parameter with __user The 'to' parameter of clear_user is supposed to take a userspace pointer, so annotate it with __user. This fixes the following and similar sparse warnings: fs/binfmt_elf_fdpic.c:714:35: warning: incorrect type in argument 1 (different address spaces) fs/binfmt_elf_fdpic.c:714:35: expected void [noderef] *to fs/binfmt_elf_fdpic.c:714:35: got void * fs/binfmt_elf_fdpic.c:1119:29: warning: incorrect type in argument 1 (different address spaces) fs/binfmt_elf_fdpic.c:1119:29: expected void *to fs/binfmt_elf_fdpic.c:1119:29: got void [noderef] * Signed-off-by: Lars-Peter Clausen Signed-off-by: Bob Liu --- arch/blackfin/include/asm/uaccess.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 90f32c2a65b..ded2d05847f 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -256,11 +256,11 @@ static inline long __must_check strlen_user(const char *src) */ static inline unsigned long __must_check -__clear_user(void *to, unsigned long n) +__clear_user(void __user *to, unsigned long n) { if (!access_ok(VERIFY_WRITE, to, n)) return n; - memset(to, 0, n); + memset((void __force *)to, 0, n); return 0; } -- cgit v1.2.3-70-g09d2 From 2a7e0775d0b0dfc083f97c72dc885f6dab8dd27b Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 22 Oct 2012 16:09:05 +0200 Subject: Blackfin: Annotate strnlen_user and strlen_user 'src' parameter with __user The 'src' parameter of strnlen_user and strlen_user is supposed to take a userspace pointer, so annotate it with __user. This fixes the following and similar sparse warnings: fs/binfmt_elf_fdpic.c:671:36: warning: incorrect type in argument 1 (different address spaces) fs/binfmt_elf_fdpic.c:671:36: expected char const *src fs/binfmt_elf_fdpic.c:671:36: got char [noderef] *[assigned] p fs/binfmt_elf_fdpic.c:683:36: warning: incorrect type in argument 1 (different address spaces) fs/binfmt_elf_fdpic.c:683:36: expected char const *src fs/binfmt_elf_fdpic.c:683:36: got char [noderef] *[assigned] p Signed-off-by: Lars-Peter Clausen Signed-off-by: Bob Liu --- arch/blackfin/include/asm/uaccess.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index ded2d05847f..3ee7b421615 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -237,18 +237,18 @@ strncpy_from_user(char *dst, const char __user *src, long count) * On exception, returns 0. * If the string is too long, returns a value greater than n. */ -static inline long __must_check strnlen_user(const char *src, long n) +static inline long __must_check strnlen_user(const char __user *src, long n) { if (!access_ok(VERIFY_READ, src, 1)) return 0; - return strnlen(src, n) + 1; + return strnlen((const char __force *)src, n) + 1; } -static inline long __must_check strlen_user(const char *src) +static inline long __must_check strlen_user(const char __user *src) { if (!access_ok(VERIFY_READ, src, 1)) return 0; - return strlen(src) + 1; + return strlen((const char __force *)src) + 1; } /* -- cgit v1.2.3-70-g09d2 From 594fa5c96d6432c292c6baebc56a6500de6b7bc2 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 22 Oct 2012 16:09:06 +0200 Subject: Blackfin: twi: Add missing __iomem annotation Add a missing __iomem to the bfin_twi_iface struct's regs_base field. This fixes the following sparse warnings: Fixes the following sparse warnings: drivers/i2c/busses/i2c-bfin-twi.c:641:26: warning: incorrect type in assignment (different address spaces) drivers/i2c/busses/i2c-bfin-twi.c:641:26: expected struct bfin_twi_regs *regs_base drivers/i2c/busses/i2c-bfin-twi.c:641:26: got void [noderef] * drivers/i2c/busses/i2c-bfin-twi.c:715:22: warning: incorrect type in argument 1 (different address spaces) drivers/i2c/busses/i2c-bfin-twi.c:715:22: expected void [noderef] *addr drivers/i2c/busses/i2c-bfin-twi.c:715:22: got struct bfin_twi_regs *regs_base drivers/i2c/busses/i2c-bfin-twi.c:732:22: warning: incorrect type in argument 1 (different address spaces) drivers/i2c/busses/i2c-bfin-twi.c:732:22: expected void [noderef] *addr drivers/i2c/busses/i2c-bfin-twi.c:732:22: got struct bfin_twi_regs *regs_base Signed-off-by: Lars-Peter Clausen Signed-off-by: Bob Liu --- arch/blackfin/include/asm/bfin_twi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h index f4a07278743..90c3c006557 100644 --- a/arch/blackfin/include/asm/bfin_twi.h +++ b/arch/blackfin/include/asm/bfin_twi.h @@ -61,7 +61,7 @@ struct bfin_twi_iface { int cur_msg; u16 saved_clkdiv; u16 saved_control; - struct bfin_twi_regs *regs_base; + struct bfin_twi_regs __iomem *regs_base; }; #define DEFINE_TWI_REG(reg_name, reg) \ -- cgit v1.2.3-70-g09d2 From d69367b1fb63be6f47da974bb3a97fb7c06c6062 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 26 Oct 2012 16:31:02 +0200 Subject: Blackfin: remove unnecessary prototype for kobjsize() The prototype for kobjsize() is already defined in linux/mm.h which is included where kobjsize() is used. Signed-off-by: Tobias Klauser Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu --- arch/blackfin/include/asm/pgtable.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h index dcca3e6d6e8..b8663921d3c 100644 --- a/arch/blackfin/include/asm/pgtable.h +++ b/arch/blackfin/include/asm/pgtable.h @@ -83,8 +83,6 @@ PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED); #define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page) extern char empty_zero_page[]; -extern unsigned int kobjsize(const void *objp); - #define swapper_pg_dir ((pgd_t *) 0) /* * No page table caches to initialise. -- cgit v1.2.3-70-g09d2 From 00e9584c765043d6f4385244f03eed0e7fe18287 Mon Sep 17 00:00:00 2001 From: Tobias Klauser Date: Fri, 26 Oct 2012 16:31:03 +0200 Subject: Blackfin: remove unused is_in_rom() The function is not used anywhere in the whole tree (anymore), so remove it. Signed-off-by: Tobias Klauser Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu --- arch/blackfin/include/asm/uaccess.h | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/asm/uaccess.h b/arch/blackfin/include/asm/uaccess.h index 3ee7b421615..461bb542e2e 100644 --- a/arch/blackfin/include/asm/uaccess.h +++ b/arch/blackfin/include/asm/uaccess.h @@ -34,23 +34,6 @@ static inline void set_fs(mm_segment_t fs) #define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size)) -static inline int is_in_rom(unsigned long addr) -{ - /* - * What we are really trying to do is determine if addr is - * in an allocated kernel memory region. If not then assume - * we cannot free it or otherwise de-allocate it. Ideally - * we could restrict this to really being in a ROM or flash, - * but that would need to be done on a board by board basis, - * not globally. - */ - if ((addr < _ramstart) || (addr >= _ramend)) - return (1); - - /* Default case, not in ROM */ - return (0); -} - /* * The fs value determines whether argument validity checking should be * performed or not. If get_fs() == USER_DS, checking is performed, with -- cgit v1.2.3-70-g09d2 From 4452fec6af8d5ed1dc3ac37f31d7da1bd62733b8 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 10 Oct 2012 19:40:19 +0100 Subject: Blackfin: dpmc: use module_platform_driver macro This patch removes some code duplication by using module_platform_driver. Signed-off-by: Srinivas Kandagatla Signed-off-by: Mike Frysinger Signed-off-by: Bob Liu --- arch/blackfin/mach-common/dpmc.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c index f5685a496c5..978bb400be0 100644 --- a/arch/blackfin/mach-common/dpmc.c +++ b/arch/blackfin/mach-common/dpmc.c @@ -157,24 +157,7 @@ struct platform_driver bfin_dpmc_device_driver = { .name = DRIVER_NAME, } }; - -/** - * bfin_dpmc_init - Init driver - */ -static int __init bfin_dpmc_init(void) -{ - return platform_driver_register(&bfin_dpmc_device_driver); -} -module_init(bfin_dpmc_init); - -/** - * bfin_dpmc_exit - break down driver - */ -static void __exit bfin_dpmc_exit(void) -{ - platform_driver_unregister(&bfin_dpmc_device_driver); -} -module_exit(bfin_dpmc_exit); +module_platform_driver(bfin_dpmc_device_driver); MODULE_AUTHOR("Michael Hennerich "); MODULE_DESCRIPTION("cpu power management driver for Blackfin"); -- cgit v1.2.3-70-g09d2 From f1a1d52508bd29c68a7f77412c0a9cf5e1b51154 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Mon, 29 Oct 2012 13:50:05 +0800 Subject: blackfin: anomaly: add anomaly 16000030 for bf5xx Drivers common to both bf5xx and bf60x chip families may use this anomaly id. So add it to bf5xx header files also. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu --- arch/blackfin/mach-bf518/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf527/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf533/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf537/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf538/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf548/include/mach/anomaly.h | 1 + arch/blackfin/mach-bf561/include/mach/anomaly.h | 1 + 7 files changed, 7 insertions(+) (limited to 'arch') diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index 845e6bc8d63..46cb88231d6 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h @@ -165,5 +165,6 @@ #define ANOMALY_05000474 (0) #define ANOMALY_05000475 (0) #define ANOMALY_05000480 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index aa14110be4c..2f9cc33deec 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h @@ -285,5 +285,6 @@ #define ANOMALY_05000448 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000480 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 3a8f73a669f..0e754efc3cf 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h @@ -378,5 +378,6 @@ #define ANOMALY_05000474 (0) #define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index df921269639..2bc70c5b941 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h @@ -236,5 +236,6 @@ #define ANOMALY_05000467 (0) #define ANOMALY_05000474 (0) #define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index 318d922d11d..eaac26973f6 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h @@ -210,5 +210,6 @@ #define ANOMALY_05000474 (0) #define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 5b711d85b90..098fad63e03 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h @@ -296,5 +296,6 @@ #define ANOMALY_05000440 (0) #define ANOMALY_05000475 (0) #define ANOMALY_05000480 (0) +#define ANOMALY_16000030 (0) #endif diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 72476ff5033..038249c1d0d 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -348,5 +348,6 @@ #define ANOMALY_05000474 (0) #define ANOMALY_05000480 (0) #define ANOMALY_05000485 (0) +#define ANOMALY_16000030 (0) #endif -- cgit v1.2.3-70-g09d2 From 1439d030b9032261f1111a2dd16b9a8ca11112ef Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Thu, 1 Nov 2012 17:07:09 +0800 Subject: blackfin: kgdb: call generic_exec_single() directly Current generic API smp_call_function_single() is changed to avoid raise IPI and call function in IPI handler on the same core which is necessary to support KGDB switch master core in SMP case, so call generic_exec_single() directly instead of smp_call_function_single(). Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu --- arch/blackfin/kernel/kgdb.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c index 9b80b152435..b882ce22c34 100644 --- a/arch/blackfin/kernel/kgdb.c +++ b/arch/blackfin/kernel/kgdb.c @@ -329,6 +329,9 @@ static void bfin_disable_hw_debug(struct pt_regs *regs) } #ifdef CONFIG_SMP +extern void generic_exec_single(int cpu, struct call_single_data *data, int wait); +static struct call_single_data kgdb_smp_ipi_data[NR_CPUS]; + void kgdb_passive_cpu_callback(void *info) { kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs()); @@ -336,12 +339,18 @@ void kgdb_passive_cpu_callback(void *info) void kgdb_roundup_cpus(unsigned long flags) { - smp_call_function(kgdb_passive_cpu_callback, NULL, 0); + unsigned int cpu; + + for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids; + cpu = cpumask_next(cpu, cpu_online_mask)) { + kgdb_smp_ipi_data[cpu].func = kgdb_passive_cpu_callback; + generic_exec_single(cpu, &kgdb_smp_ipi_data[cpu], 0); + } } void kgdb_roundup_cpu(int cpu, unsigned long flags) { - smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0); + generic_exec_single(cpu, &kgdb_smp_ipi_data[cpu], 0); } #endif -- cgit v1.2.3-70-g09d2 From cb67e161bc947ab467657dda38168c2b2266f5bc Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Wed, 12 Dec 2012 17:24:39 -0500 Subject: arch/tile: provide PT_FLAGS_COMPAT value in pt_regs This flag is set for ptrace GETREGS or PEEKUSER for processes that are COMPAT, i.e. 32-bit. This allows things like strace to easily discover what personality to use, for example. Acked-by: Oleg Nesterov Signed-off-by: Chris Metcalf --- arch/tile/include/uapi/asm/ptrace.h | 6 ++++ arch/tile/kernel/ptrace.c | 57 ++++++++++++++++++++++++++----------- 2 files changed, 46 insertions(+), 17 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/uapi/asm/ptrace.h b/arch/tile/include/uapi/asm/ptrace.h index c717d0fec72..0d2208803b2 100644 --- a/arch/tile/include/uapi/asm/ptrace.h +++ b/arch/tile/include/uapi/asm/ptrace.h @@ -84,5 +84,11 @@ struct pt_regs { #define PTRACE_O_TRACEMIGRATE 0x00010000 #define PTRACE_EVENT_MIGRATE 16 +/* + * Flag bits in pt_regs.flags that are part of the ptrace API. + * We start our numbering higher up to avoid confusion with the + * non-ABI kernel-internal values that use the low 16 bits. + */ +#define PT_FLAGS_COMPAT 0x10000 /* process is an -m32 compat process */ #endif /* _UAPI_ASM_TILE_PTRACE_H */ diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c index e92e40527d6..64ba102c596 100644 --- a/arch/tile/kernel/ptrace.c +++ b/arch/tile/kernel/ptrace.c @@ -45,6 +45,41 @@ void ptrace_disable(struct task_struct *child) clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); } +/* + * Get registers from task and ready the result for userspace. + * Note that we localize the API issues to getregs() and putregs() at + * some cost in performance, e.g. we need a full pt_regs copy for + * PEEKUSR, and two copies for POKEUSR. But in general we expect + * GETREGS/PUTREGS to be the API of choice anyway. + */ +static char *getregs(struct task_struct *child, struct pt_regs *uregs) +{ + *uregs = *task_pt_regs(child); + + /* Set up flags ABI bits. */ + uregs->flags = 0; +#ifdef CONFIG_COMPAT + if (task_thread_info(child)->status & TS_COMPAT) + uregs->flags |= PT_FLAGS_COMPAT; +#endif + + return (char *)uregs; +} + +/* Put registers back to task. */ +static void putregs(struct task_struct *child, struct pt_regs *uregs) +{ + struct pt_regs *regs = task_pt_regs(child); + + /* Don't allow overwriting the kernel-internal flags word. */ + uregs->flags = regs->flags; + + /* Only allow setting the ICS bit in the ex1 word. */ + uregs->ex1 = PL_ICS_EX1(USER_PL, EX1_ICS(uregs->ex1)); + + *regs = *uregs; +} + long arch_ptrace(struct task_struct *child, long request, unsigned long addr, unsigned long data) { @@ -53,14 +88,13 @@ long arch_ptrace(struct task_struct *child, long request, long ret = -EIO; char *childreg; struct pt_regs copyregs; - int ex1_offset; switch (request) { case PTRACE_PEEKUSR: /* Read register from pt_regs. */ if (addr >= PTREGS_SIZE) break; - childreg = (char *)task_pt_regs(child) + addr; + childreg = getregs(child, ©regs) + addr; #ifdef CONFIG_COMPAT if (is_compat_task()) { if (addr & (sizeof(compat_long_t)-1)) @@ -79,17 +113,7 @@ long arch_ptrace(struct task_struct *child, long request, case PTRACE_POKEUSR: /* Write register in pt_regs. */ if (addr >= PTREGS_SIZE) break; - childreg = (char *)task_pt_regs(child) + addr; - - /* Guard against overwrites of the privilege level. */ - ex1_offset = PTREGS_OFFSET_EX1; -#if defined(CONFIG_COMPAT) && defined(__BIG_ENDIAN) - if (is_compat_task()) /* point at low word */ - ex1_offset += sizeof(compat_long_t); -#endif - if (addr == ex1_offset) - data = PL_ICS_EX1(USER_PL, EX1_ICS(data)); - + childreg = getregs(child, ©regs) + addr; #ifdef CONFIG_COMPAT if (is_compat_task()) { if (addr & (sizeof(compat_long_t)-1)) @@ -102,11 +126,12 @@ long arch_ptrace(struct task_struct *child, long request, break; *(long *)childreg = data; } + putregs(child, ©regs); ret = 0; break; case PTRACE_GETREGS: /* Get all registers from the child. */ - if (copy_to_user(datap, task_pt_regs(child), + if (copy_to_user(datap, getregs(child, ©regs), sizeof(struct pt_regs)) == 0) { ret = 0; } @@ -115,9 +140,7 @@ long arch_ptrace(struct task_struct *child, long request, case PTRACE_SETREGS: /* Set all registers in the child. */ if (copy_from_user(©regs, datap, sizeof(struct pt_regs)) == 0) { - copyregs.ex1 = - PL_ICS_EX1(USER_PL, EX1_ICS(copyregs.ex1)); - *task_pt_regs(child) = copyregs; + putregs(child, ©regs); ret = 0; } break; -- cgit v1.2.3-70-g09d2 From 34e1169d996ab148490c01b65b4ee371cf8ffba2 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 16 Oct 2012 07:31:07 +1030 Subject: module: add syscall to load module from fd As part of the effort to create a stronger boundary between root and kernel, Chrome OS wants to be able to enforce that kernel modules are being loaded only from our read-only crypto-hash verified (dm_verity) root filesystem. Since the init_module syscall hands the kernel a module as a memory blob, no reasoning about the origin of the blob can be made. Earlier proposals for appending signatures to kernel modules would not be useful in Chrome OS, since it would involve adding an additional set of keys to our kernel and builds for no good reason: we already trust the contents of our root filesystem. We don't need to verify those kernel modules a second time. Having to do signature checking on module loading would slow us down and be redundant. All we need to know is where a module is coming from so we can say yes/no to loading it. If a file descriptor is used as the source of a kernel module, many more things can be reasoned about. In Chrome OS's case, we could enforce that the module lives on the filesystem we expect it to live on. In the case of IMA (or other LSMs), it would be possible, for example, to examine extended attributes that may contain signatures over the contents of the module. This introduces a new syscall (on x86), similar to init_module, that has only two arguments. The first argument is used as a file descriptor to the module and the second argument is a pointer to the NULL terminated string of module arguments. Signed-off-by: Kees Cook Cc: Andrew Morton Signed-off-by: Rusty Russell (merge fixes) --- arch/x86/syscalls/syscall_32.tbl | 1 + arch/x86/syscalls/syscall_64.tbl | 1 + include/linux/syscalls.h | 1 + kernel/module.c | 367 +++++++++++++++++++++++---------------- kernel/sys_ni.c | 1 + 5 files changed, 223 insertions(+), 148 deletions(-) (limited to 'arch') diff --git a/arch/x86/syscalls/syscall_32.tbl b/arch/x86/syscalls/syscall_32.tbl index a47103fbc69..83b3838417e 100644 --- a/arch/x86/syscalls/syscall_32.tbl +++ b/arch/x86/syscalls/syscall_32.tbl @@ -356,3 +356,4 @@ 347 i386 process_vm_readv sys_process_vm_readv compat_sys_process_vm_readv 348 i386 process_vm_writev sys_process_vm_writev compat_sys_process_vm_writev 349 i386 kcmp sys_kcmp +350 i386 finit_module sys_finit_module diff --git a/arch/x86/syscalls/syscall_64.tbl b/arch/x86/syscalls/syscall_64.tbl index a582bfed95b..7c58c84b7bc 100644 --- a/arch/x86/syscalls/syscall_64.tbl +++ b/arch/x86/syscalls/syscall_64.tbl @@ -319,6 +319,7 @@ 310 64 process_vm_readv sys_process_vm_readv 311 64 process_vm_writev sys_process_vm_writev 312 common kcmp sys_kcmp +313 common finit_module sys_finit_module # # x32-specific system call numbers start at 512 to avoid cache impact diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 727f0cd7392..32bc035bcd6 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -868,4 +868,5 @@ asmlinkage long sys_process_vm_writev(pid_t pid, asmlinkage long sys_kcmp(pid_t pid1, pid_t pid2, int type, unsigned long idx1, unsigned long idx2); +asmlinkage long sys_finit_module(int fd, const char __user *uargs); #endif diff --git a/kernel/module.c b/kernel/module.c index 6e48c3a4359..6d2c4e4ca1f 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -2425,18 +2426,17 @@ static inline void kmemleak_load_module(const struct module *mod, #endif #ifdef CONFIG_MODULE_SIG -static int module_sig_check(struct load_info *info, - const void *mod, unsigned long *_len) +static int module_sig_check(struct load_info *info) { int err = -ENOKEY; - unsigned long markerlen = sizeof(MODULE_SIG_STRING) - 1; - unsigned long len = *_len; + const unsigned long markerlen = sizeof(MODULE_SIG_STRING) - 1; + const void *mod = info->hdr; - if (len > markerlen && - memcmp(mod + len - markerlen, MODULE_SIG_STRING, markerlen) == 0) { + if (info->len > markerlen && + memcmp(mod + info->len - markerlen, MODULE_SIG_STRING, markerlen) == 0) { /* We truncate the module to discard the signature */ - *_len -= markerlen; - err = mod_verify_sig(mod, _len); + info->len -= markerlen; + err = mod_verify_sig(mod, &info->len); } if (!err) { @@ -2454,59 +2454,97 @@ static int module_sig_check(struct load_info *info, return err; } #else /* !CONFIG_MODULE_SIG */ -static int module_sig_check(struct load_info *info, - void *mod, unsigned long *len) +static int module_sig_check(struct load_info *info) { return 0; } #endif /* !CONFIG_MODULE_SIG */ -/* Sets info->hdr, info->len and info->sig_ok. */ -static int copy_and_check(struct load_info *info, - const void __user *umod, unsigned long len, - const char __user *uargs) +/* Sanity checks against invalid binaries, wrong arch, weird elf version. */ +static int elf_header_check(struct load_info *info) { - int err; - Elf_Ehdr *hdr; + if (info->len < sizeof(*(info->hdr))) + return -ENOEXEC; + + if (memcmp(info->hdr->e_ident, ELFMAG, SELFMAG) != 0 + || info->hdr->e_type != ET_REL + || !elf_check_arch(info->hdr) + || info->hdr->e_shentsize != sizeof(Elf_Shdr)) + return -ENOEXEC; + + if (info->hdr->e_shoff >= info->len + || (info->hdr->e_shnum * sizeof(Elf_Shdr) > + info->len - info->hdr->e_shoff)) + return -ENOEXEC; - if (len < sizeof(*hdr)) + return 0; +} + +/* Sets info->hdr and info->len. */ +static int copy_module_from_user(const void __user *umod, unsigned long len, + struct load_info *info) +{ + info->len = len; + if (info->len < sizeof(*(info->hdr))) return -ENOEXEC; /* Suck in entire file: we'll want most of it. */ - if ((hdr = vmalloc(len)) == NULL) + info->hdr = vmalloc(info->len); + if (!info->hdr) return -ENOMEM; - if (copy_from_user(hdr, umod, len) != 0) { - err = -EFAULT; - goto free_hdr; + if (copy_from_user(info->hdr, umod, info->len) != 0) { + vfree(info->hdr); + return -EFAULT; } - err = module_sig_check(info, hdr, &len); + return 0; +} + +/* Sets info->hdr and info->len. */ +static int copy_module_from_fd(int fd, struct load_info *info) +{ + struct file *file; + int err; + struct kstat stat; + loff_t pos; + ssize_t bytes = 0; + + file = fget(fd); + if (!file) + return -ENOEXEC; + + err = vfs_getattr(file->f_vfsmnt, file->f_dentry, &stat); if (err) - goto free_hdr; + goto out; - /* Sanity checks against insmoding binaries or wrong arch, - weird elf version */ - if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) != 0 - || hdr->e_type != ET_REL - || !elf_check_arch(hdr) - || hdr->e_shentsize != sizeof(Elf_Shdr)) { - err = -ENOEXEC; - goto free_hdr; + if (stat.size > INT_MAX) { + err = -EFBIG; + goto out; } - - if (hdr->e_shoff >= len || - hdr->e_shnum * sizeof(Elf_Shdr) > len - hdr->e_shoff) { - err = -ENOEXEC; - goto free_hdr; + info->hdr = vmalloc(stat.size); + if (!info->hdr) { + err = -ENOMEM; + goto out; } - info->hdr = hdr; - info->len = len; - return 0; + pos = 0; + while (pos < stat.size) { + bytes = kernel_read(file, pos, (char *)(info->hdr) + pos, + stat.size - pos); + if (bytes < 0) { + vfree(info->hdr); + err = bytes; + goto out; + } + if (bytes == 0) + break; + pos += bytes; + } + info->len = pos; -free_hdr: - vfree(hdr); +out: + fput(file); return err; } @@ -2945,33 +2983,123 @@ static bool finished_loading(const char *name) return ret; } +/* Call module constructors. */ +static void do_mod_ctors(struct module *mod) +{ +#ifdef CONFIG_CONSTRUCTORS + unsigned long i; + + for (i = 0; i < mod->num_ctors; i++) + mod->ctors[i](); +#endif +} + +/* This is where the real work happens */ +static int do_init_module(struct module *mod) +{ + int ret = 0; + + blocking_notifier_call_chain(&module_notify_list, + MODULE_STATE_COMING, mod); + + /* Set RO and NX regions for core */ + set_section_ro_nx(mod->module_core, + mod->core_text_size, + mod->core_ro_size, + mod->core_size); + + /* Set RO and NX regions for init */ + set_section_ro_nx(mod->module_init, + mod->init_text_size, + mod->init_ro_size, + mod->init_size); + + do_mod_ctors(mod); + /* Start the module */ + if (mod->init != NULL) + ret = do_one_initcall(mod->init); + if (ret < 0) { + /* Init routine failed: abort. Try to protect us from + buggy refcounters. */ + mod->state = MODULE_STATE_GOING; + synchronize_sched(); + module_put(mod); + blocking_notifier_call_chain(&module_notify_list, + MODULE_STATE_GOING, mod); + free_module(mod); + wake_up_all(&module_wq); + return ret; + } + if (ret > 0) { + printk(KERN_WARNING +"%s: '%s'->init suspiciously returned %d, it should follow 0/-E convention\n" +"%s: loading module anyway...\n", + __func__, mod->name, ret, + __func__); + dump_stack(); + } + + /* Now it's a first class citizen! */ + mod->state = MODULE_STATE_LIVE; + blocking_notifier_call_chain(&module_notify_list, + MODULE_STATE_LIVE, mod); + + /* We need to finish all async code before the module init sequence is done */ + async_synchronize_full(); + + mutex_lock(&module_mutex); + /* Drop initial reference. */ + module_put(mod); + trim_init_extable(mod); +#ifdef CONFIG_KALLSYMS + mod->num_symtab = mod->core_num_syms; + mod->symtab = mod->core_symtab; + mod->strtab = mod->core_strtab; +#endif + unset_module_init_ro_nx(mod); + module_free(mod, mod->module_init); + mod->module_init = NULL; + mod->init_size = 0; + mod->init_ro_size = 0; + mod->init_text_size = 0; + mutex_unlock(&module_mutex); + wake_up_all(&module_wq); + + return 0; +} + +static int may_init_module(void) +{ + if (!capable(CAP_SYS_MODULE) || modules_disabled) + return -EPERM; + + return 0; +} + /* Allocate and load the module: note that size of section 0 is always zero, and we rely on this for optional sections. */ -static struct module *load_module(void __user *umod, - unsigned long len, - const char __user *uargs) +static int load_module(struct load_info *info, const char __user *uargs) { - struct load_info info = { NULL, }; struct module *mod, *old; long err; - pr_debug("load_module: umod=%p, len=%lu, uargs=%p\n", - umod, len, uargs); + err = module_sig_check(info); + if (err) + goto free_copy; - /* Copy in the blobs from userspace, check they are vaguely sane. */ - err = copy_and_check(&info, umod, len, uargs); + err = elf_header_check(info); if (err) - return ERR_PTR(err); + goto free_copy; /* Figure out module layout, and allocate all the memory. */ - mod = layout_and_allocate(&info); + mod = layout_and_allocate(info); if (IS_ERR(mod)) { err = PTR_ERR(mod); goto free_copy; } #ifdef CONFIG_MODULE_SIG - mod->sig_ok = info.sig_ok; + mod->sig_ok = info->sig_ok; if (!mod->sig_ok) add_taint_module(mod, TAINT_FORCED_MODULE); #endif @@ -2983,25 +3111,25 @@ static struct module *load_module(void __user *umod, /* Now we've got everything in the final locations, we can * find optional sections. */ - find_module_sections(mod, &info); + find_module_sections(mod, info); err = check_module_license_and_versions(mod); if (err) goto free_unload; /* Set up MODINFO_ATTR fields */ - setup_modinfo(mod, &info); + setup_modinfo(mod, info); /* Fix up syms, so that st_value is a pointer to location. */ - err = simplify_symbols(mod, &info); + err = simplify_symbols(mod, info); if (err < 0) goto free_modinfo; - err = apply_relocations(mod, &info); + err = apply_relocations(mod, info); if (err < 0) goto free_modinfo; - err = post_relocation(mod, &info); + err = post_relocation(mod, info); if (err < 0) goto free_modinfo; @@ -3041,14 +3169,14 @@ again: } /* This has to be done once we're sure module name is unique. */ - dynamic_debug_setup(info.debug, info.num_debug); + dynamic_debug_setup(info->debug, info->num_debug); /* Find duplicate symbols */ err = verify_export_symbols(mod); if (err < 0) goto ddebug; - module_bug_finalize(info.hdr, info.sechdrs, mod); + module_bug_finalize(info->hdr, info->sechdrs, mod); list_add_rcu(&mod->list, &modules); mutex_unlock(&module_mutex); @@ -3059,16 +3187,17 @@ again: goto unlink; /* Link in to syfs. */ - err = mod_sysfs_setup(mod, &info, mod->kp, mod->num_kp); + err = mod_sysfs_setup(mod, info, mod->kp, mod->num_kp); if (err < 0) goto unlink; /* Get rid of temporary copy. */ - free_copy(&info); + free_copy(info); /* Done! */ trace_module_load(mod); - return mod; + + return do_init_module(mod); unlink: mutex_lock(&module_mutex); @@ -3077,7 +3206,7 @@ again: module_bug_cleanup(mod); wake_up_all(&module_wq); ddebug: - dynamic_debug_remove(info.debug); + dynamic_debug_remove(info->debug); unlock: mutex_unlock(&module_mutex); synchronize_sched(); @@ -3089,106 +3218,48 @@ again: free_unload: module_unload_free(mod); free_module: - module_deallocate(mod, &info); + module_deallocate(mod, info); free_copy: - free_copy(&info); - return ERR_PTR(err); -} - -/* Call module constructors. */ -static void do_mod_ctors(struct module *mod) -{ -#ifdef CONFIG_CONSTRUCTORS - unsigned long i; - - for (i = 0; i < mod->num_ctors; i++) - mod->ctors[i](); -#endif + free_copy(info); + return err; } -/* This is where the real work happens */ SYSCALL_DEFINE3(init_module, void __user *, umod, unsigned long, len, const char __user *, uargs) { - struct module *mod; - int ret = 0; - - /* Must have permission */ - if (!capable(CAP_SYS_MODULE) || modules_disabled) - return -EPERM; + int err; + struct load_info info = { }; - /* Do all the hard work */ - mod = load_module(umod, len, uargs); - if (IS_ERR(mod)) - return PTR_ERR(mod); + err = may_init_module(); + if (err) + return err; - blocking_notifier_call_chain(&module_notify_list, - MODULE_STATE_COMING, mod); + pr_debug("init_module: umod=%p, len=%lu, uargs=%p\n", + umod, len, uargs); - /* Set RO and NX regions for core */ - set_section_ro_nx(mod->module_core, - mod->core_text_size, - mod->core_ro_size, - mod->core_size); + err = copy_module_from_user(umod, len, &info); + if (err) + return err; - /* Set RO and NX regions for init */ - set_section_ro_nx(mod->module_init, - mod->init_text_size, - mod->init_ro_size, - mod->init_size); + return load_module(&info, uargs); +} - do_mod_ctors(mod); - /* Start the module */ - if (mod->init != NULL) - ret = do_one_initcall(mod->init); - if (ret < 0) { - /* Init routine failed: abort. Try to protect us from - buggy refcounters. */ - mod->state = MODULE_STATE_GOING; - synchronize_sched(); - module_put(mod); - blocking_notifier_call_chain(&module_notify_list, - MODULE_STATE_GOING, mod); - free_module(mod); - wake_up_all(&module_wq); - return ret; - } - if (ret > 0) { - printk(KERN_WARNING -"%s: '%s'->init suspiciously returned %d, it should follow 0/-E convention\n" -"%s: loading module anyway...\n", - __func__, mod->name, ret, - __func__); - dump_stack(); - } +SYSCALL_DEFINE2(finit_module, int, fd, const char __user *, uargs) +{ + int err; + struct load_info info = { }; - /* Now it's a first class citizen! */ - mod->state = MODULE_STATE_LIVE; - blocking_notifier_call_chain(&module_notify_list, - MODULE_STATE_LIVE, mod); + err = may_init_module(); + if (err) + return err; - /* We need to finish all async code before the module init sequence is done */ - async_synchronize_full(); + pr_debug("finit_module: fd=%d, uargs=%p\n", fd, uargs); - mutex_lock(&module_mutex); - /* Drop initial reference. */ - module_put(mod); - trim_init_extable(mod); -#ifdef CONFIG_KALLSYMS - mod->num_symtab = mod->core_num_syms; - mod->symtab = mod->core_symtab; - mod->strtab = mod->core_strtab; -#endif - unset_module_init_ro_nx(mod); - module_free(mod, mod->module_init); - mod->module_init = NULL; - mod->init_size = 0; - mod->init_ro_size = 0; - mod->init_text_size = 0; - mutex_unlock(&module_mutex); - wake_up_all(&module_wq); + err = copy_module_from_fd(fd, &info); + if (err) + return err; - return 0; + return load_module(&info, uargs); } static inline int within(unsigned long addr, void *start, unsigned long size) diff --git a/kernel/sys_ni.c b/kernel/sys_ni.c index dbff751e408..395084d4ce1 100644 --- a/kernel/sys_ni.c +++ b/kernel/sys_ni.c @@ -25,6 +25,7 @@ cond_syscall(sys_swapoff); cond_syscall(sys_kexec_load); cond_syscall(compat_sys_kexec_load); cond_syscall(sys_init_module); +cond_syscall(sys_finit_module); cond_syscall(sys_delete_module); cond_syscall(sys_socketpair); cond_syscall(sys_bind); -- cgit v1.2.3-70-g09d2 From 4926f65224e49f253feb0320b03814ea630b7541 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Tue, 16 Oct 2012 12:38:47 +1030 Subject: ARM: add finit_module syscall to ARM Add finit_module syscall to the ARM syscall list. Signed-off-by: Kees Cook Cc: Russell King Signed-off-by: Rusty Russell --- arch/arm/include/uapi/asm/unistd.h | 1 + arch/arm/kernel/calls.S | 1 + 2 files changed, 2 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h index ac03bdb4ae4..4da7cde70b5 100644 --- a/arch/arm/include/uapi/asm/unistd.h +++ b/arch/arm/include/uapi/asm/unistd.h @@ -405,6 +405,7 @@ #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) /* 378 for kcmp */ +#define __NR_finit_module (__NR_SYSCALL_BASE+379) /* * This may need to be greater than __NR_last_syscall+1 in order to diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index 831cd38c8d9..36e27df01b4 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S @@ -388,6 +388,7 @@ CALL(sys_process_vm_readv) CALL(sys_process_vm_writev) CALL(sys_ni_syscall) /* reserved for sys_kcmp */ + CALL(sys_finit_module) #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted -- cgit v1.2.3-70-g09d2 From 71eac70257b469bd43737232bce0fd960caebee1 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Fri, 2 Nov 2012 14:57:20 +1030 Subject: powerpc: add finit_module syscall. (This is just for Acks: this won't work without the actual syscall patches, sitting in my tree for -next at the moment). Acked-by: Benjamin Herrenschmidt Signed-off-by: Rusty Russell --- arch/powerpc/include/asm/systbl.h | 1 + arch/powerpc/include/asm/unistd.h | 2 +- arch/powerpc/include/uapi/asm/unistd.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h index 84083876985..d0b27f8b47f 100644 --- a/arch/powerpc/include/asm/systbl.h +++ b/arch/powerpc/include/asm/systbl.h @@ -356,3 +356,4 @@ COMPAT_SYS_SPU(sendmmsg) SYSCALL_SPU(setns) COMPAT_SYS(process_vm_readv) COMPAT_SYS(process_vm_writev) +SYSCALL(finit_module) diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h index 921dce6d844..8d219a014c3 100644 --- a/arch/powerpc/include/asm/unistd.h +++ b/arch/powerpc/include/asm/unistd.h @@ -12,7 +12,7 @@ #include -#define __NR_syscalls 353 +#define __NR_syscalls 354 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h index 380b5d37a90..8c478c6c6b1 100644 --- a/arch/powerpc/include/uapi/asm/unistd.h +++ b/arch/powerpc/include/uapi/asm/unistd.h @@ -375,6 +375,7 @@ #define __NR_setns 350 #define __NR_process_vm_readv 351 #define __NR_process_vm_writev 352 +#define __NR_finit_module 353 #endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */ -- cgit v1.2.3-70-g09d2 From 82fab442f5322b016f72891c0db2436c6a6c20b7 Mon Sep 17 00:00:00 2001 From: Rusty Russell Date: Tue, 11 Dec 2012 09:38:33 +1030 Subject: modules: don't hand 0 to vmalloc. In commit d0a21265dfb5fa8a David Rientjes unified various archs' module_alloc implementation (including x86) and removed the graduitous shortcut for size == 0. Then, in commit de7d2b567d040e3b, Joe Perches added a warning for zero-length vmallocs, which can happen without kallsyms on modules with no init sections (eg. zlib_deflate). Fix this once and for all; the module code has to handle zero length anyway, so get it right at the caller and remove the now-gratuitous checks within the arch-specific module_alloc implementations. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=42608 Reported-by: Conrad Kostecki Cc: David Rientjes Cc: Joe Perches Signed-off-by: Rusty Russell --- arch/cris/kernel/module.c | 2 -- arch/parisc/kernel/module.c | 2 -- arch/sparc/kernel/module.c | 4 ---- arch/tile/kernel/module.c | 2 -- arch/unicore32/kernel/module.c | 3 --- kernel/module.c | 33 ++++++++++++++++++--------------- 6 files changed, 18 insertions(+), 28 deletions(-) (limited to 'arch') diff --git a/arch/cris/kernel/module.c b/arch/cris/kernel/module.c index 37400f5869e..51123f985eb 100644 --- a/arch/cris/kernel/module.c +++ b/arch/cris/kernel/module.c @@ -32,8 +32,6 @@ #ifdef CONFIG_ETRAX_KMALLOCED_MODULES void *module_alloc(unsigned long size) { - if (size == 0) - return NULL; return kmalloc(size, GFP_KERNEL); } diff --git a/arch/parisc/kernel/module.c b/arch/parisc/kernel/module.c index 5e34ccf39a4..2a625fb063e 100644 --- a/arch/parisc/kernel/module.c +++ b/arch/parisc/kernel/module.c @@ -214,8 +214,6 @@ static inline int reassemble_22(int as22) void *module_alloc(unsigned long size) { - if (size == 0) - return NULL; /* using RWX means less protection for modules, but it's * easier than trying to map the text, data, init_text and * init_data correctly */ diff --git a/arch/sparc/kernel/module.c b/arch/sparc/kernel/module.c index f1ddc0d2367..4435488ebe2 100644 --- a/arch/sparc/kernel/module.c +++ b/arch/sparc/kernel/module.c @@ -43,10 +43,6 @@ void *module_alloc(unsigned long size) { void *ret; - /* We handle the zero case fine, unlike vmalloc */ - if (size == 0) - return NULL; - ret = module_map(size); if (ret) memset(ret, 0, size); diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c index 243ffebe38d..4918d91bc3a 100644 --- a/arch/tile/kernel/module.c +++ b/arch/tile/kernel/module.c @@ -42,8 +42,6 @@ void *module_alloc(unsigned long size) int i = 0; int npages; - if (size == 0) - return NULL; npages = (size + PAGE_SIZE - 1) / PAGE_SIZE; pages = kmalloc(npages * sizeof(struct page *), GFP_KERNEL); if (pages == NULL) diff --git a/arch/unicore32/kernel/module.c b/arch/unicore32/kernel/module.c index 8fbe8577f5e..16bd1495b93 100644 --- a/arch/unicore32/kernel/module.c +++ b/arch/unicore32/kernel/module.c @@ -27,9 +27,6 @@ void *module_alloc(unsigned long size) struct vm_struct *area; size = PAGE_ALIGN(size); - if (!size) - return NULL; - area = __get_vm_area(size, VM_ALLOC, MODULES_VADDR, MODULES_END); if (!area) return NULL; diff --git a/kernel/module.c b/kernel/module.c index 79a526dd1b1..4542ff3f7ef 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -2377,7 +2377,7 @@ static void dynamic_debug_remove(struct _ddebug *debug) void * __weak module_alloc(unsigned long size) { - return size == 0 ? NULL : vmalloc_exec(size); + return vmalloc_exec(size); } static void *module_alloc_update_bounds(unsigned long size) @@ -2793,20 +2793,23 @@ static int move_module(struct module *mod, struct load_info *info) memset(ptr, 0, mod->core_size); mod->module_core = ptr; - ptr = module_alloc_update_bounds(mod->init_size); - /* - * The pointer to this block is stored in the module structure - * which is inside the block. This block doesn't need to be - * scanned as it contains data and code that will be freed - * after the module is initialized. - */ - kmemleak_ignore(ptr); - if (!ptr && mod->init_size) { - module_free(mod, mod->module_core); - return -ENOMEM; - } - memset(ptr, 0, mod->init_size); - mod->module_init = ptr; + if (mod->init_size) { + ptr = module_alloc_update_bounds(mod->init_size); + /* + * The pointer to this block is stored in the module structure + * which is inside the block. This block doesn't need to be + * scanned as it contains data and code that will be freed + * after the module is initialized. + */ + kmemleak_ignore(ptr); + if (!ptr) { + module_free(mod, mod->module_core); + return -ENOMEM; + } + memset(ptr, 0, mod->init_size); + mod->module_init = ptr; + } else + mod->module_init = NULL; /* Transfer each section which specifies SHF_ALLOC */ pr_debug("final section addresses:\n"); -- cgit v1.2.3-70-g09d2 From 86794b43569c9b8936dff2e8eed503393379af6e Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Fri, 14 Dec 2012 11:19:24 +0800 Subject: blackfin: SEC: clean up SEC interrupt initialization Append the SEC IRQ after the IVG6, which is consistent to BF5xx SIC. Exclude SIC irqchip fucntions from SEC code. Call handle_fasteoi_irq in SEC error and fault handler. Signed-off-by: Sonic Zhang Signed-off-by: Bob Liu --- arch/blackfin/include/mach-common/irq.h | 5 +- arch/blackfin/mach-bf609/include/mach/irq.h | 3 - arch/blackfin/mach-bf609/pm.c | 3 +- arch/blackfin/mach-common/ints-priority.c | 272 ++++++++++++++-------------- 4 files changed, 137 insertions(+), 146 deletions(-) (limited to 'arch') diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h index cab14e911dc..af9fc8171eb 100644 --- a/arch/blackfin/include/mach-common/irq.h +++ b/arch/blackfin/include/mach-common/irq.h @@ -40,8 +40,6 @@ #define IRQ_HWERR 5 /* Hardware Error */ #define IRQ_CORETMR 6 /* Core timer */ -#define BFIN_IRQ(x) ((x) + 7) - #define IVG7 7 #define IVG8 8 #define IVG9 9 @@ -52,6 +50,9 @@ #define IVG14 14 #define IVG15 15 +#define BFIN_IRQ(x) ((x) + IVG7) +#define BFIN_SYSIRQ(x) ((x) - IVG7) + #define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS) #endif diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h index 23e74cdeeee..fa0843d5d77 100644 --- a/arch/blackfin/mach-bf609/include/mach/irq.h +++ b/arch/blackfin/mach-bf609/include/mach/irq.h @@ -9,9 +9,6 @@ #include -#undef BFIN_IRQ -#define BFIN_IRQ(x) ((x) + IVG15) - #define NR_PERI_INTS (5 * 32) #define IRQ_SEC_ERR BFIN_IRQ(0) /* SEC Error */ diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c index dacafc163f7..ad505d9db4a 100644 --- a/arch/blackfin/mach-bf609/pm.c +++ b/arch/blackfin/mach-bf609/pm.c @@ -174,7 +174,6 @@ void bfin_hibernate_syscontrol(void) bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4); } -#define IRQ_SID(irq) ((irq) - IVG15) asmlinkage void enter_deepsleep(void); __attribute__((l1_text)) @@ -311,7 +310,7 @@ static irqreturn_t test_isr(int irq, void *dev_id) { printk(KERN_DEBUG "gpio irq %d\n", irq); if (irq == 231) - bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1)); + bfin_sec_raise_irq(BFIN_SYSIRQ(IRQ_SOFT1)); return IRQ_HANDLED; } diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 902bebc434c..83ff311fd6e 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c @@ -28,12 +28,6 @@ #include #include -#ifndef SEC_GCTL -# define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) -#else -# define SIC_SYSIRQ(irq) ((irq) - IVG15) -#endif - /* * NOTES: * - we have separated the physical Hardware interrupt from the @@ -141,13 +135,13 @@ static void bfin_core_unmask_irq(struct irq_data *d) return; } +#ifndef SEC_GCTL void bfin_internal_mask_irq(unsigned int irq) { unsigned long flags = hard_local_irq_save(); -#ifndef SEC_GCTL #ifdef SIC_IMASK0 - unsigned mask_bank = SIC_SYSIRQ(irq) / 32; - unsigned mask_bit = SIC_SYSIRQ(irq) % 32; + unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; + unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & ~(1 << mask_bit)); # if defined(CONFIG_SMP) || defined(CONFIG_ICC) @@ -156,9 +150,8 @@ void bfin_internal_mask_irq(unsigned int irq) # endif #else bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & - ~(1 << SIC_SYSIRQ(irq))); + ~(1 << BFIN_SYSIRQ(irq))); #endif /* end of SIC_IMASK0 */ -#endif hard_local_irq_restore(flags); } @@ -176,10 +169,9 @@ void bfin_internal_unmask_irq(unsigned int irq) { unsigned long flags = hard_local_irq_save(); -#ifndef SEC_GCTL #ifdef SIC_IMASK0 - unsigned mask_bank = SIC_SYSIRQ(irq) / 32; - unsigned mask_bit = SIC_SYSIRQ(irq) % 32; + unsigned mask_bank = BFIN_SYSIRQ(irq) / 32; + unsigned mask_bit = BFIN_SYSIRQ(irq) % 32; # ifdef CONFIG_SMP if (cpumask_test_cpu(0, affinity)) # endif @@ -194,17 +186,103 @@ void bfin_internal_unmask_irq(unsigned int irq) # endif #else bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | - (1 << SIC_SYSIRQ(irq))); + (1 << BFIN_SYSIRQ(irq))); +#endif + hard_local_irq_restore(flags); +} + +#ifdef CONFIG_SMP +static void bfin_internal_unmask_irq_chip(struct irq_data *d) +{ + bfin_internal_unmask_irq_affinity(d->irq, d->affinity); +} + +static int bfin_internal_set_affinity(struct irq_data *d, + const struct cpumask *mask, bool force) +{ + bfin_internal_mask_irq(d->irq); + bfin_internal_unmask_irq_affinity(d->irq, mask); + + return 0; +} +#else +static void bfin_internal_unmask_irq_chip(struct irq_data *d) +{ + bfin_internal_unmask_irq(d->irq); +} #endif + +#if defined(CONFIG_PM) +int bfin_internal_set_wake(unsigned int irq, unsigned int state) +{ + u32 bank, bit, wakeup = 0; + unsigned long flags; + bank = BFIN_SYSIRQ(irq) / 32; + bit = BFIN_SYSIRQ(irq) % 32; + + switch (irq) { +#ifdef IRQ_RTC + case IRQ_RTC: + wakeup |= WAKE; + break; +#endif +#ifdef IRQ_CAN0_RX + case IRQ_CAN0_RX: + wakeup |= CANWE; + break; #endif +#ifdef IRQ_CAN1_RX + case IRQ_CAN1_RX: + wakeup |= CANWE; + break; +#endif +#ifdef IRQ_USB_INT0 + case IRQ_USB_INT0: + wakeup |= USBWE; + break; +#endif +#ifdef CONFIG_BF54x + case IRQ_CNT: + wakeup |= ROTWE; + break; +#endif + default: + break; + } + + flags = hard_local_irq_save(); + + if (state) { + bfin_sic_iwr[bank] |= (1 << bit); + vr_wakeup |= wakeup; + + } else { + bfin_sic_iwr[bank] &= ~(1 << bit); + vr_wakeup &= ~wakeup; + } + hard_local_irq_restore(flags); + + return 0; } -#ifdef SEC_GCTL +static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) +{ + return bfin_internal_set_wake(d->irq, state); +} +#else +inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) +{ + return 0; +} +# define bfin_internal_set_wake_chip NULL +#endif + +#else /* SEC_GCTL */ static void bfin_sec_preflow_handler(struct irq_data *d) { unsigned long flags = hard_local_irq_save(); - unsigned int sid = SIC_SYSIRQ(d->irq); + unsigned int sid = BFIN_SYSIRQ(d->irq); bfin_write_SEC_SCI(0, SEC_CSID, sid); @@ -214,7 +292,7 @@ static void bfin_sec_preflow_handler(struct irq_data *d) static void bfin_sec_mask_ack_irq(struct irq_data *d) { unsigned long flags = hard_local_irq_save(); - unsigned int sid = SIC_SYSIRQ(d->irq); + unsigned int sid = BFIN_SYSIRQ(d->irq); bfin_write_SEC_SCI(0, SEC_CSID, sid); @@ -224,7 +302,7 @@ static void bfin_sec_mask_ack_irq(struct irq_data *d) static void bfin_sec_unmask_irq(struct irq_data *d) { unsigned long flags = hard_local_irq_save(); - unsigned int sid = SIC_SYSIRQ(d->irq); + unsigned int sid = BFIN_SYSIRQ(d->irq); bfin_write32(SEC_END, sid); @@ -269,7 +347,7 @@ static void bfin_sec_enable_sci(unsigned int sid) unsigned long flags = hard_local_irq_save(); uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); - if (sid == SIC_SYSIRQ(IRQ_WATCH0)) + if (sid == BFIN_SYSIRQ(IRQ_WATCH0)) reg_sctl |= SEC_SCTL_FAULT_EN; else reg_sctl |= SEC_SCTL_INT_EN; @@ -292,7 +370,7 @@ static void bfin_sec_disable_sci(unsigned int sid) static void bfin_sec_enable(struct irq_data *d) { unsigned long flags = hard_local_irq_save(); - unsigned int sid = SIC_SYSIRQ(d->irq); + unsigned int sid = BFIN_SYSIRQ(d->irq); bfin_sec_enable_sci(sid); bfin_sec_enable_ssi(sid); @@ -303,7 +381,7 @@ static void bfin_sec_enable(struct irq_data *d) static void bfin_sec_disable(struct irq_data *d) { unsigned long flags = hard_local_irq_save(); - unsigned int sid = SIC_SYSIRQ(d->irq); + unsigned int sid = BFIN_SYSIRQ(d->irq); bfin_sec_disable_sci(sid); bfin_sec_disable_ssi(sid); @@ -328,9 +406,10 @@ static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_prior hard_local_irq_restore(flags); } -void bfin_sec_raise_irq(unsigned int sid) +void bfin_sec_raise_irq(unsigned int irq) { unsigned long flags = hard_local_irq_save(); + unsigned int sid = BFIN_SYSIRQ(irq); bfin_write32(SEC_RAISE, sid); @@ -341,8 +420,13 @@ static void init_software_driven_irq(void) { bfin_sec_set_ssi_coreid(34, 0); bfin_sec_set_ssi_coreid(35, 1); + + bfin_sec_enable_sci(35); + bfin_sec_enable_ssi(35); bfin_sec_set_ssi_coreid(36, 0); bfin_sec_set_ssi_coreid(37, 1); + bfin_sec_enable_sci(37); + bfin_sec_enable_ssi(37); } void bfin_sec_resume(void) @@ -412,6 +496,8 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc) } raw_spin_unlock(&desc->lock); + + handle_fasteoi_irq(irq, desc); } void handle_core_fault(unsigned int irq, struct irq_desc *desc) @@ -431,105 +517,18 @@ void handle_core_fault(unsigned int irq, struct irq_desc *desc) printk(KERN_NOTICE "Kernel Stack\n"); show_stack(current, NULL); print_modules(); - panic("Kernel core hardware error"); + panic("Core 0 hardware error"); break; case IRQ_C0_NMI_L1_PARITY_ERR: - panic("NMI occurs unexpectedly"); + panic("Core 0 NMI L1 parity error"); break; default: - panic("Core 1 fault occurs unexpectedly"); + panic("Core 1 fault %d occurs unexpectedly", irq); } raw_spin_unlock(&desc->lock); } -#endif - -#ifdef CONFIG_SMP -static void bfin_internal_unmask_irq_chip(struct irq_data *d) -{ - bfin_internal_unmask_irq_affinity(d->irq, d->affinity); -} - -static int bfin_internal_set_affinity(struct irq_data *d, - const struct cpumask *mask, bool force) -{ - bfin_internal_mask_irq(d->irq); - bfin_internal_unmask_irq_affinity(d->irq, mask); - - return 0; -} -#else -static void bfin_internal_unmask_irq_chip(struct irq_data *d) -{ - bfin_internal_unmask_irq(d->irq); -} -#endif - -#if defined(CONFIG_PM) && !defined(SEC_GCTL) -int bfin_internal_set_wake(unsigned int irq, unsigned int state) -{ - u32 bank, bit, wakeup = 0; - unsigned long flags; - bank = SIC_SYSIRQ(irq) / 32; - bit = SIC_SYSIRQ(irq) % 32; - - switch (irq) { -#ifdef IRQ_RTC - case IRQ_RTC: - wakeup |= WAKE; - break; -#endif -#ifdef IRQ_CAN0_RX - case IRQ_CAN0_RX: - wakeup |= CANWE; - break; -#endif -#ifdef IRQ_CAN1_RX - case IRQ_CAN1_RX: - wakeup |= CANWE; - break; -#endif -#ifdef IRQ_USB_INT0 - case IRQ_USB_INT0: - wakeup |= USBWE; - break; -#endif -#ifdef CONFIG_BF54x - case IRQ_CNT: - wakeup |= ROTWE; - break; -#endif - default: - break; - } - - flags = hard_local_irq_save(); - - if (state) { - bfin_sic_iwr[bank] |= (1 << bit); - vr_wakeup |= wakeup; - - } else { - bfin_sic_iwr[bank] &= ~(1 << bit); - vr_wakeup &= ~wakeup; - } - - hard_local_irq_restore(flags); - - return 0; -} - -static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) -{ - return bfin_internal_set_wake(d->irq, state); -} -#else -inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) -{ - return 0; -} -# define bfin_internal_set_wake_chip NULL -#endif +#endif /* SEC_GCTL */ static struct irq_chip bfin_core_irqchip = { .name = "CORE", @@ -537,6 +536,7 @@ static struct irq_chip bfin_core_irqchip = { .irq_unmask = bfin_core_unmask_irq, }; +#ifndef SEC_GCTL static struct irq_chip bfin_internal_irqchip = { .name = "INTN", .irq_mask = bfin_internal_mask_irq_chip, @@ -548,8 +548,7 @@ static struct irq_chip bfin_internal_irqchip = { #endif .irq_set_wake = bfin_internal_set_wake_chip, }; - -#ifdef SEC_GCTL +#else static struct irq_chip bfin_sec_irqchip = { .name = "SEC", .irq_mask_ack = bfin_sec_mask_ack_irq, @@ -1138,7 +1137,9 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) return -EINVAL; } +#ifndef SEC_GCTL bfin_internal_set_wake(pint_irq, state); +#endif return 0; } @@ -1173,7 +1174,7 @@ static int sec_suspend(void) u32 bank; for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) - save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0)); + save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0)); return 0; } @@ -1187,7 +1188,7 @@ static void sec_resume(void) bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) - bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); + bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); } static struct syscore_ops sec_pm_syscore_ops = { @@ -1538,33 +1539,26 @@ int __init init_arch_irq(void) for (irq = 0; irq <= SYS_IRQS; irq++) { if (irq <= IRQ_CORETMR) { - irq_set_chip(irq, &bfin_core_irqchip); -#ifdef CONFIG_TICKSOURCE_CORETMR + irq_set_chip_and_handler(irq, &bfin_core_irqchip, + handle_simple_irq); +#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP) if (irq == IRQ_CORETMR) -# ifdef CONFIG_SMP irq_set_handler(irq, handle_percpu_irq); -# else - irq_set_handler(irq, handle_simple_irq); -# endif #endif - } else if (irq < BFIN_IRQ(0)) { - irq_set_chip_and_handler(irq, &bfin_internal_irqchip, - handle_simple_irq); - } else if (irq == IRQ_SEC_ERR) { - irq_set_chip_and_handler(irq, &bfin_sec_irqchip, - handle_sec_fault); - } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) { - irq_set_chip_and_handler(irq, &bfin_sec_irqchip, - handle_core_fault); } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { irq_set_chip(irq, &bfin_sec_irqchip); irq_set_chained_handler(irq, bfin_demux_gpio_irq); } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { - irq_set_chip(irq, &bfin_sec_irqchip); - irq_set_handler(irq, handle_percpu_irq); - } else { irq_set_chip_and_handler(irq, &bfin_sec_irqchip, - handle_fasteoi_irq); + handle_percpu_irq); + } else { + irq_set_chip(irq, &bfin_sec_irqchip); + if (irq == IRQ_SEC_ERR) + irq_set_handler(irq, handle_sec_fault); + else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS) + irq_set_handler(irq, handle_core_fault); + else + irq_set_handler(irq, handle_fasteoi_irq); __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); } } @@ -1593,8 +1587,8 @@ int __init init_arch_irq(void) bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); - bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0)); - bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0)); + bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0)); + bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0)); bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); udelay(100); bfin_write_SEC_GCTL(SEC_GCTL_EN); -- cgit v1.2.3-70-g09d2 From d0b0885316ab7a97cc8a19027905de3ff7bd1e79 Mon Sep 17 00:00:00 2001 From: Jan Glauber Date: Tue, 11 Dec 2012 14:53:35 +0100 Subject: s390/pci: performance statistics and debug infrastructure Add support for reading the PCI function measurement block counters provided by the hypervisor. Add two s390 debug features, one for critical errors and one for tracing and provide wrappers to log data. Signed-off-by: Jan Glauber Signed-off-by: Martin Schwidefsky --- arch/s390/include/asm/pci.h | 39 ++++++++ arch/s390/include/asm/pci_debug.h | 36 +++++++ arch/s390/pci/Makefile | 2 +- arch/s390/pci/pci.c | 73 +++++++++++++- arch/s390/pci/pci_clp.c | 1 + arch/s390/pci/pci_debug.c | 193 ++++++++++++++++++++++++++++++++++++++ arch/s390/pci/pci_dma.c | 8 +- arch/s390/pci/pci_event.c | 2 + 8 files changed, 349 insertions(+), 5 deletions(-) create mode 100644 arch/s390/include/asm/pci_debug.h create mode 100644 arch/s390/pci/pci_debug.c (limited to 'arch') diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h index a6175ad0c42..b1fa93c606a 100644 --- a/arch/s390/include/asm/pci.h +++ b/arch/s390/include/asm/pci.h @@ -9,6 +9,7 @@ #include #include #include +#include #define PCIBIOS_MIN_IO 0x1000 #define PCIBIOS_MIN_MEM 0x10000000 @@ -33,6 +34,25 @@ int pci_proc_domain(struct pci_bus *); #define ZPCI_FC_BLOCKED 0x20 #define ZPCI_FC_DMA_ENABLED 0x10 +struct zpci_fmb { + u32 format : 8; + u32 dma_valid : 1; + u32 : 23; + u32 samples; + u64 last_update; + /* hardware counters */ + u64 ld_ops; + u64 st_ops; + u64 stb_ops; + u64 rpcit_ops; + u64 dma_rbytes; + u64 dma_wbytes; + /* software counters */ + atomic64_t allocated_pages; + atomic64_t mapped_pages; + atomic64_t unmapped_pages; +} __packed __aligned(16); + struct msi_map { unsigned long irq; struct msi_desc *msi; @@ -92,7 +112,15 @@ struct zpci_dev { u64 end_dma; /* End of available DMA addresses */ u64 dma_mask; /* DMA address space mask */ + /* Function measurement block */ + struct zpci_fmb *fmb; + u16 fmb_update; /* update interval */ + enum pci_bus_speed max_bus_speed; + + struct dentry *debugfs_dev; + struct dentry *debugfs_perf; + struct dentry *debugfs_debug; }; struct pci_hp_callback_ops { @@ -155,4 +183,15 @@ extern struct list_head zpci_list; extern struct pci_hp_callback_ops hotplug_ops; extern unsigned int pci_probe; +/* FMB */ +int zpci_fmb_enable_device(struct zpci_dev *); +int zpci_fmb_disable_device(struct zpci_dev *); + +/* Debug */ +int zpci_debug_init(void); +void zpci_debug_exit(void); +void zpci_debug_init_device(struct zpci_dev *); +void zpci_debug_exit_device(struct zpci_dev *); +void zpci_debug_info(struct zpci_dev *, struct seq_file *); + #endif diff --git a/arch/s390/include/asm/pci_debug.h b/arch/s390/include/asm/pci_debug.h new file mode 100644 index 00000000000..6bbec4265b6 --- /dev/null +++ b/arch/s390/include/asm/pci_debug.h @@ -0,0 +1,36 @@ +#ifndef _S390_ASM_PCI_DEBUG_H +#define _S390_ASM_PCI_DEBUG_H + +#include + +extern debug_info_t *pci_debug_msg_id; +extern debug_info_t *pci_debug_err_id; + +#ifdef CONFIG_PCI_DEBUG +#define zpci_dbg(fmt, args...) \ + do { \ + if (pci_debug_msg_id->level >= 2) \ + debug_sprintf_event(pci_debug_msg_id, 2, fmt , ## args);\ + } while (0) + +#else /* !CONFIG_PCI_DEBUG */ +#define zpci_dbg(fmt, args...) do { } while (0) +#endif + +#define zpci_err(text...) \ + do { \ + char debug_buffer[16]; \ + snprintf(debug_buffer, 16, text); \ + debug_text_event(pci_debug_err_id, 0, debug_buffer); \ + } while (0) + +static inline void zpci_err_hex(void *addr, int len) +{ + while (len > 0) { + debug_event(pci_debug_err_id, 0, (void *) addr, len); + len -= pci_debug_err_id->buf_size; + addr += pci_debug_err_id->buf_size; + } +} + +#endif diff --git a/arch/s390/pci/Makefile b/arch/s390/pci/Makefile index ab0827b6bc4..f0f426a113c 100644 --- a/arch/s390/pci/Makefile +++ b/arch/s390/pci/Makefile @@ -3,4 +3,4 @@ # obj-$(CONFIG_PCI) += pci.o pci_dma.o pci_clp.o pci_msi.o \ - pci_sysfs.o pci_event.o + pci_sysfs.o pci_event.o pci_debug.o diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c index 7ed38e5e302..8fa416b8775 100644 --- a/arch/s390/pci/pci.c +++ b/arch/s390/pci/pci.c @@ -98,6 +98,10 @@ EXPORT_SYMBOL_GPL(zpci_iomap_start); static int __read_mostly aisb_max; static struct kmem_cache *zdev_irq_cache; +static struct kmem_cache *zdev_fmb_cache; + +debug_info_t *pci_debug_msg_id; +debug_info_t *pci_debug_err_id; static inline int irq_to_msi_nr(unsigned int irq) { @@ -216,6 +220,7 @@ struct mod_pci_args { u64 base; u64 limit; u64 iota; + u64 fmb_addr; }; static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args *args) @@ -232,6 +237,7 @@ static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args fib->pba = args->base; fib->pal = args->limit; fib->iota = args->iota; + fib->fmb_addr = args->fmb_addr; rc = mpcifc_instr(req, fib); free_page((unsigned long) fib); @@ -242,7 +248,7 @@ static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args int zpci_register_ioat(struct zpci_dev *zdev, u8 dmaas, u64 base, u64 limit, u64 iota) { - struct mod_pci_args args = { base, limit, iota }; + struct mod_pci_args args = { base, limit, iota, 0 }; WARN_ON_ONCE(iota & 0x3fff); args.iota |= ZPCI_IOTA_RTTO_FLAG; @@ -252,7 +258,7 @@ int zpci_register_ioat(struct zpci_dev *zdev, u8 dmaas, /* Modify PCI: Unregister I/O address translation parameters */ int zpci_unregister_ioat(struct zpci_dev *zdev, u8 dmaas) { - struct mod_pci_args args = { 0, 0, 0 }; + struct mod_pci_args args = { 0, 0, 0, 0 }; return mod_pci(zdev, ZPCI_MOD_FC_DEREG_IOAT, dmaas, &args); } @@ -260,11 +266,46 @@ int zpci_unregister_ioat(struct zpci_dev *zdev, u8 dmaas) /* Modify PCI: Unregister adapter interruptions */ static int zpci_unregister_airq(struct zpci_dev *zdev) { - struct mod_pci_args args = { 0, 0, 0 }; + struct mod_pci_args args = { 0, 0, 0, 0 }; return mod_pci(zdev, ZPCI_MOD_FC_DEREG_INT, 0, &args); } +/* Modify PCI: Set PCI function measurement parameters */ +int zpci_fmb_enable_device(struct zpci_dev *zdev) +{ + struct mod_pci_args args = { 0, 0, 0, 0 }; + + if (zdev->fmb) + return -EINVAL; + + zdev->fmb = kmem_cache_alloc(zdev_fmb_cache, GFP_KERNEL); + if (!zdev->fmb) + return -ENOMEM; + memset(zdev->fmb, 0, sizeof(*zdev->fmb)); + WARN_ON((u64) zdev->fmb & 0xf); + + args.fmb_addr = virt_to_phys(zdev->fmb); + return mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args); +} + +/* Modify PCI: Disable PCI function measurement */ +int zpci_fmb_disable_device(struct zpci_dev *zdev) +{ + struct mod_pci_args args = { 0, 0, 0, 0 }; + int rc; + + if (!zdev->fmb) + return -EINVAL; + + /* Function measurement is disabled if fmb address is zero */ + rc = mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args); + + kmem_cache_free(zdev_fmb_cache, zdev->fmb); + zdev->fmb = NULL; + return rc; +} + #define ZPCI_PCIAS_CFGSPC 15 static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len) @@ -633,6 +674,7 @@ static void zpci_remove_device(struct pci_dev *pdev) dev_info(&pdev->dev, "Removing device %u\n", zdev->domain); zdev->state = ZPCI_FN_STATE_CONFIGURED; zpci_dma_exit_device(zdev); + zpci_fmb_disable_device(zdev); zpci_sysfs_remove_device(&pdev->dev); zpci_unmap_resources(pdev); list_del(&zdev->entry); /* can be called from init */ @@ -799,6 +841,16 @@ static void zpci_irq_exit(void) kfree(bucket); } +void zpci_debug_info(struct zpci_dev *zdev, struct seq_file *m) +{ + if (!zdev) + return; + + seq_printf(m, "global irq retries: %u\n", atomic_read(&irq_retries)); + seq_printf(m, "aibv[0]:%016lx aibv[1]:%016lx aisb:%016lx\n", + get_imap(0)->aibv, get_imap(1)->aibv, *bucket->aisb); +} + static struct resource *zpci_alloc_bus_resource(unsigned long start, unsigned long size, unsigned long flags, int domain) { @@ -994,6 +1046,8 @@ int zpci_scan_device(struct zpci_dev *zdev) goto out; } + zpci_debug_init_device(zdev); + zpci_fmb_enable_device(zdev); zpci_map_resources(zdev); pci_bus_add_devices(zdev->bus); @@ -1020,6 +1074,11 @@ static int zpci_mem_init(void) if (!zdev_irq_cache) goto error_zdev; + zdev_fmb_cache = kmem_cache_create("PCI_FMB_cache", sizeof(struct zpci_fmb), + 16, 0, NULL); + if (!zdev_fmb_cache) + goto error_fmb; + /* TODO: use realloc */ zpci_iomap_start = kzalloc(ZPCI_IOMAP_MAX_ENTRIES * sizeof(*zpci_iomap_start), GFP_KERNEL); @@ -1028,6 +1087,8 @@ static int zpci_mem_init(void) return 0; error_iomap: + kmem_cache_destroy(zdev_fmb_cache); +error_fmb: kmem_cache_destroy(zdev_irq_cache); error_zdev: return -ENOMEM; @@ -1037,6 +1098,7 @@ static void zpci_mem_exit(void) { kfree(zpci_iomap_start); kmem_cache_destroy(zdev_irq_cache); + kmem_cache_destroy(zdev_fmb_cache); } unsigned int pci_probe = 1; @@ -1066,6 +1128,10 @@ static int __init pci_base_init(void) test_facility(69), test_facility(70), test_facility(71)); + rc = zpci_debug_init(); + if (rc) + return rc; + rc = zpci_mem_init(); if (rc) goto out_mem; @@ -1098,6 +1164,7 @@ out_irq: out_hash: zpci_mem_exit(); out_mem: + zpci_debug_exit(); return rc; } subsys_initcall(pci_base_init); diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c index 7f4ce8d874a..2c847143cbd 100644 --- a/arch/s390/pci/pci_clp.c +++ b/arch/s390/pci/pci_clp.c @@ -51,6 +51,7 @@ static void clp_store_query_pci_fngrp(struct zpci_dev *zdev, zdev->tlb_refresh = response->refresh; zdev->dma_mask = response->dasm; zdev->msi_addr = response->msia; + zdev->fmb_update = response->mui; pr_debug("Supported number of MSI vectors: %u\n", response->noi); switch (response->version) { diff --git a/arch/s390/pci/pci_debug.c b/arch/s390/pci/pci_debug.c new file mode 100644 index 00000000000..a303c95346c --- /dev/null +++ b/arch/s390/pci/pci_debug.c @@ -0,0 +1,193 @@ +/* + * Copyright IBM Corp. 2012 + * + * Author(s): + * Jan Glauber + */ + +#define COMPONENT "zPCI" +#define pr_fmt(fmt) COMPONENT ": " fmt + +#include +#include +#include +#include +#include + +#include + +static struct dentry *debugfs_root; + +static char *pci_perf_names[] = { + /* hardware counters */ + "Load operations", + "Store operations", + "Store block operations", + "Refresh operations", + "DMA read bytes", + "DMA write bytes", + /* software counters */ + "Allocated pages", + "Mapped pages", + "Unmapped pages", +}; + +static int pci_perf_show(struct seq_file *m, void *v) +{ + struct zpci_dev *zdev = m->private; + u64 *stat; + int i; + + if (!zdev) + return 0; + if (!zdev->fmb) + return seq_printf(m, "FMB statistics disabled\n"); + + /* header */ + seq_printf(m, "FMB @ %p\n", zdev->fmb); + seq_printf(m, "Update interval: %u ms\n", zdev->fmb_update); + seq_printf(m, "Samples: %u\n", zdev->fmb->samples); + seq_printf(m, "Last update TOD: %Lx\n", zdev->fmb->last_update); + + /* hardware counters */ + stat = (u64 *) &zdev->fmb->ld_ops; + for (i = 0; i < 4; i++) + seq_printf(m, "%26s:\t%llu\n", + pci_perf_names[i], *(stat + i)); + if (zdev->fmb->dma_valid) + for (i = 4; i < 6; i++) + seq_printf(m, "%26s:\t%llu\n", + pci_perf_names[i], *(stat + i)); + /* software counters */ + for (i = 6; i < ARRAY_SIZE(pci_perf_names); i++) + seq_printf(m, "%26s:\t%llu\n", + pci_perf_names[i], + atomic64_read((atomic64_t *) (stat + i))); + + return 0; +} + +static ssize_t pci_perf_seq_write(struct file *file, const char __user *ubuf, + size_t count, loff_t *off) +{ + struct zpci_dev *zdev = ((struct seq_file *) file->private_data)->private; + unsigned long val; + int rc; + + if (!zdev) + return 0; + + rc = kstrtoul_from_user(ubuf, count, 10, &val); + if (rc) + return rc; + + switch (val) { + case 0: + rc = zpci_fmb_disable_device(zdev); + if (rc) + return rc; + break; + case 1: + rc = zpci_fmb_enable_device(zdev); + if (rc) + return rc; + break; + } + return count; +} + +static int pci_perf_seq_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, pci_perf_show, + filp->f_path.dentry->d_inode->i_private); +} + +static const struct file_operations debugfs_pci_perf_fops = { + .open = pci_perf_seq_open, + .read = seq_read, + .write = pci_perf_seq_write, + .llseek = seq_lseek, + .release = single_release, +}; + +static int pci_debug_show(struct seq_file *m, void *v) +{ + struct zpci_dev *zdev = m->private; + + zpci_debug_info(zdev, m); + return 0; +} + +static int pci_debug_seq_open(struct inode *inode, struct file *filp) +{ + return single_open(filp, pci_debug_show, + filp->f_path.dentry->d_inode->i_private); +} + +static const struct file_operations debugfs_pci_debug_fops = { + .open = pci_debug_seq_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void zpci_debug_init_device(struct zpci_dev *zdev) +{ + zdev->debugfs_dev = debugfs_create_dir(dev_name(&zdev->pdev->dev), + debugfs_root); + if (IS_ERR(zdev->debugfs_dev)) + zdev->debugfs_dev = NULL; + + zdev->debugfs_perf = debugfs_create_file("statistics", + S_IFREG | S_IRUGO | S_IWUSR, + zdev->debugfs_dev, zdev, + &debugfs_pci_perf_fops); + if (IS_ERR(zdev->debugfs_perf)) + zdev->debugfs_perf = NULL; + + zdev->debugfs_debug = debugfs_create_file("debug", + S_IFREG | S_IRUGO | S_IWUSR, + zdev->debugfs_dev, zdev, + &debugfs_pci_debug_fops); + if (IS_ERR(zdev->debugfs_debug)) + zdev->debugfs_debug = NULL; +} + +void zpci_debug_exit_device(struct zpci_dev *zdev) +{ + debugfs_remove(zdev->debugfs_perf); + debugfs_remove(zdev->debugfs_debug); + debugfs_remove(zdev->debugfs_dev); +} + +int __init zpci_debug_init(void) +{ + /* event trace buffer */ + pci_debug_msg_id = debug_register("pci_msg", 16, 1, 16 * sizeof(long)); + if (!pci_debug_msg_id) + return -EINVAL; + debug_register_view(pci_debug_msg_id, &debug_sprintf_view); + debug_set_level(pci_debug_msg_id, 3); + zpci_dbg("Debug view initialized\n"); + + /* error log */ + pci_debug_err_id = debug_register("pci_error", 2, 1, 16); + if (!pci_debug_err_id) + return -EINVAL; + debug_register_view(pci_debug_err_id, &debug_hex_ascii_view); + debug_set_level(pci_debug_err_id, 6); + zpci_err("Debug view initialized\n"); + + debugfs_root = debugfs_create_dir("pci", NULL); + return 0; +} + +void zpci_debug_exit(void) +{ + if (pci_debug_msg_id) + debug_unregister(pci_debug_msg_id); + if (pci_debug_err_id) + debug_unregister(pci_debug_err_id); + + debugfs_remove(debugfs_root); +} diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index c64b4b294b0..6138468b420 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -291,8 +291,10 @@ static dma_addr_t s390_dma_map_pages(struct device *dev, struct page *page, if (direction == DMA_NONE || direction == DMA_TO_DEVICE) flags |= ZPCI_TABLE_PROTECTED; - if (!dma_update_trans(zdev, pa, dma_addr, size, flags)) + if (!dma_update_trans(zdev, pa, dma_addr, size, flags)) { + atomic64_add(nr_pages, (atomic64_t *) &zdev->fmb->mapped_pages); return dma_addr + offset; + } out_free: dma_free_iommu(zdev, iommu_page_index, nr_pages); @@ -315,6 +317,7 @@ static void s390_dma_unmap_pages(struct device *dev, dma_addr_t dma_addr, ZPCI_TABLE_PROTECTED | ZPCI_PTE_INVALID)) dev_err(dev, "Failed to unmap addr: %Lx\n", dma_addr); + atomic64_add(npages, (atomic64_t *) &zdev->fmb->unmapped_pages); iommu_page_index = (dma_addr - zdev->start_dma) >> PAGE_SHIFT; dma_free_iommu(zdev, iommu_page_index, npages); } @@ -323,6 +326,7 @@ static void *s390_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag, struct dma_attrs *attrs) { + struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev)); struct page *page; unsigned long pa; dma_addr_t map; @@ -331,6 +335,8 @@ static void *s390_dma_alloc(struct device *dev, size_t size, page = alloc_pages(flag, get_order(size)); if (!page) return NULL; + + atomic64_add(size / PAGE_SIZE, (atomic64_t *) &zdev->fmb->allocated_pages); pa = page_to_phys(page); memset((void *) pa, 0, size); diff --git a/arch/s390/pci/pci_event.c b/arch/s390/pci/pci_event.c index dbed8cd3370..ec62e3a0dc0 100644 --- a/arch/s390/pci/pci_event.c +++ b/arch/s390/pci/pci_event.c @@ -45,6 +45,8 @@ static void zpci_event_log_err(struct zpci_ccdf_err *ccdf) { struct zpci_dev *zdev = get_zdev_by_fid(ccdf->fid); + zpci_err("SEI error CCD:\n"); + zpci_err_hex(ccdf, sizeof(*ccdf)); dev_err(&zdev->pdev->dev, "event code: 0x%x\n", ccdf->pec); } -- cgit v1.2.3-70-g09d2 From 34cceb7464f2db0da4da900afa82a210f4470b89 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 27 Nov 2012 11:22:39 -0600 Subject: ARM: OMAP2+: Fix realtime_counter_init warning in timer.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In commit fa6d79d (ARM: OMAP: Add initialisation for the real-time counter), the function realtime_counter_init() was added. However, if the kernel configuration option CONFIG_SOC_OMAP5 is not selected then the following compiler warning is observed. CC arch/arm/mach-omap2/timer.o arch/arm/mach-omap2/timer.c:489:20: warning: ‘realtime_counter_init’ defined but not used [-Wunused-function] Commit fa6d79d also introduced the kernel configuration option CONFIG_SOC_HAS_REALTIME_COUNTER. If this option is not selected then the a stub function for realtime_counter_init() is defined. For non-OMAP5 devices, there is no realtime counter and so realtime_counter_init() function and stub function are not used for these devices. Therefore, fix this warning by only allowing the kernel configuration option CONFIG_SOC_HAS_REALTIME_COUNTER to be enabled for OMAP5 devices. Cc: Santosh Shilimkar Reported-by: Tony Lindgren Signed-off-by: Jon Hunter Acked-by Santosh Shilimkar --- arch/arm/mach-omap2/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index be0f62bf903..41b581fd021 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -26,6 +26,8 @@ config SOC_HAS_OMAP2_SDRC config SOC_HAS_REALTIME_COUNTER bool "Real time free running counter" + depends on SOC_OMAP5 + default y config ARCH_OMAP2 bool "TI OMAP2" @@ -79,7 +81,6 @@ config SOC_OMAP5 select ARM_GIC select CPU_V7 select HAVE_SMP - select SOC_HAS_REALTIME_COUNTER select COMMON_CLK comment "OMAP Core Type" -- cgit v1.2.3-70-g09d2 From e0c3e27ce19fcc81156ba49c91d83a676144a103 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 27 Nov 2012 15:24:12 -0600 Subject: ARM: AM335x: Fix warning in timer.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When compiling the kernel with configuration options ... # CONFIG_ARCH_OMAP2 is not set # CONFIG_ARCH_OMAP3 is not set # CONFIG_ARCH_OMAP4 is not set # CONFIG_SOC_OMAP5 is not set CONFIG_SOC_AM33XX=y ... the following build warning is seen. CC arch/arm/mach-omap2/timer.o arch/arm/mach-omap2/timer.c:395:19: warning: ‘omap2_sync32k_clocksource_init’ defined but not used [-Wunused-function] This issue was introduced by commit 6f80b3b (ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER) where the omap2_sync32k_clocksource_init() is no longer referenced by the timer initialisation function for the AM335x device as it has no 32k-sync timer. Fix this by adding the "__maybe_unused" compiler directive to the omap2_sync32k_clocksource_init() function to indicate that this function may be used for certain configurations. Cc: Igor Grinberg Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 7016637b531..e2ffe0adc28 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -392,7 +392,7 @@ static struct of_device_id omap_counter_match[] __initdata = { }; /* Setup free-running counter for clocksource */ -static int __init omap2_sync32k_clocksource_init(void) +static int __init __maybe_unused omap2_sync32k_clocksource_init(void) { int ret; struct device_node *np = NULL; -- cgit v1.2.3-70-g09d2 From bf85f205d95eb223e849914101e0db1a5a576a3c Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 28 Nov 2012 15:56:41 -0600 Subject: ARM: OMAP2+: Fix sparse warnings in timer.c Sparse generates the following warnings when compiling mach-omap2/timer.c. CHECK arch/arm/mach-omap2/timer.c arch/arm/mach-omap2/timer.c:193:13: warning: symbol 'omap_dmtimer_init' was not declared. Should it be static? arch/arm/mach-omap2/timer.c:213:12: warning: symbol 'omap_dm_timer_get_errata' was not declared. Should it be static? Add static to function declaration to fix warnings. Signed-off-by: Vaibhav Hiremath Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index e2ffe0adc28..06e14154362 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -190,7 +190,7 @@ static struct device_node * __init omap_get_timer_dt(struct of_device_id *match, * kernel registering these devices remove them dynamically from the device * tree on boot. */ -void __init omap_dmtimer_init(void) +static void __init omap_dmtimer_init(void) { struct device_node *np; @@ -210,7 +210,7 @@ void __init omap_dmtimer_init(void) * * Get the timer errata flags that are specific to the OMAP device being used. */ -u32 __init omap_dm_timer_get_errata(void) +static u32 __init omap_dm_timer_get_errata(void) { if (cpu_is_omap24xx()) return 0; -- cgit v1.2.3-70-g09d2 From 395e095ed92b1ccfe74c90fee4cc637cff468ea7 Mon Sep 17 00:00:00 2001 From: Chris Metcalf Date: Thu, 13 Dec 2012 11:34:45 -0500 Subject: arch/tile: clean up tile-specific PTRACE_SETOPTIONS Use the newer idioms for setting PTRACE_O_xxx and PT_TRACE_xxx flags. Only set/clear tile-specific flags if the generic routine returns success, since otherwise we want to avoid setting any flags at all. Atomically update the ptrace flags with the new values. Eliminate the PT_TRACE_MASK_TILE bitmask and just shift PTRACE_O_MASK_TILE. Add a BUILD_BUG_ON to avoid overlapping with generic bits. Acked-by: Oleg Nesterov Signed-off-by: Chris Metcalf --- arch/tile/include/asm/ptrace.h | 3 +-- arch/tile/include/uapi/asm/ptrace.h | 2 +- arch/tile/kernel/ptrace.c | 10 +++++++--- 3 files changed, 9 insertions(+), 6 deletions(-) (limited to 'arch') diff --git a/arch/tile/include/asm/ptrace.h b/arch/tile/include/asm/ptrace.h index 1a4fd9ab0ee..5ce052e16b7 100644 --- a/arch/tile/include/asm/ptrace.h +++ b/arch/tile/include/asm/ptrace.h @@ -24,8 +24,7 @@ typedef unsigned long pt_reg_t; #include #define PTRACE_O_MASK_TILE (PTRACE_O_TRACEMIGRATE) -#define PT_TRACE_MIGRATE 0x00080000 -#define PT_TRACE_MASK_TILE (PT_TRACE_MIGRATE) +#define PT_TRACE_MIGRATE PT_EVENT_FLAG(PTRACE_EVENT_MIGRATE) /* Flag bits in pt_regs.flags */ #define PT_FLAGS_DISABLE_IRQ 1 /* on return to kernel, disable irqs */ diff --git a/arch/tile/include/uapi/asm/ptrace.h b/arch/tile/include/uapi/asm/ptrace.h index 0d2208803b2..7757e1985fb 100644 --- a/arch/tile/include/uapi/asm/ptrace.h +++ b/arch/tile/include/uapi/asm/ptrace.h @@ -81,8 +81,8 @@ struct pt_regs { #define PTRACE_SETFPREGS 15 /* Support TILE-specific ptrace options, with events starting at 16. */ -#define PTRACE_O_TRACEMIGRATE 0x00010000 #define PTRACE_EVENT_MIGRATE 16 +#define PTRACE_O_TRACEMIGRATE (1 << PTRACE_EVENT_MIGRATE) /* * Flag bits in pt_regs.flags that are part of the ptrace API. diff --git a/arch/tile/kernel/ptrace.c b/arch/tile/kernel/ptrace.c index 64ba102c596..b32bc3f9d63 100644 --- a/arch/tile/kernel/ptrace.c +++ b/arch/tile/kernel/ptrace.c @@ -151,12 +151,16 @@ long arch_ptrace(struct task_struct *child, long request, case PTRACE_SETOPTIONS: /* Support TILE-specific ptrace options. */ - child->ptrace &= ~PT_TRACE_MASK_TILE; + BUILD_BUG_ON(PTRACE_O_MASK_TILE & PTRACE_O_MASK); tmp = data & PTRACE_O_MASK_TILE; data &= ~PTRACE_O_MASK_TILE; ret = ptrace_request(child, request, addr, data); - if (tmp & PTRACE_O_TRACEMIGRATE) - child->ptrace |= PT_TRACE_MIGRATE; + if (ret == 0) { + unsigned int flags = child->ptrace; + flags &= ~(PTRACE_O_MASK_TILE << PT_OPT_FLAG_SHIFT); + flags |= (tmp << PT_OPT_FLAG_SHIFT); + child->ptrace = flags; + } break; default: -- cgit v1.2.3-70-g09d2 From ca2e16faa7378878c1522a7c1b6c38211de3331d Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Thu, 22 Nov 2012 10:39:56 +0200 Subject: OMAP: board-files: fix i2c_bus for tfp410 The i2c handling in tfp410 driver, which handles converting parallel RGB to DVI, was changed in 958f2717b84e88bf833d996997fda8f73276f2af (OMAPDSS: TFP410: pdata rewrite). The patch changed what value the driver considers as invalid/undefined. Before the patch, 0 was the invalid value, but as 0 is a valid bus number, the patch changed this to -1. However, the fact was missed that many board files do not define the bus number at all, thus it's left to 0. This causes the driver to fail to get the i2c bus, exiting from the driver's probe with an error, meaning that the DVI output does not work for those boards. This patch fixes the issue by changing the i2c_bus number field in the driver's platform data from u16 to int, and setting the bus number to -1 in the board files for the boards that did not define the bus. The exception is devkit8000, for which the bus is set to 1, which is the correct bus for that board. The bug exists in v3.5+ kernels. Signed-off-by: Tomi Valkeinen Reported-by: Thomas Weber Cc: Thomas Weber Cc: # v3.5+ Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-3430sdp.c | 1 + arch/arm/mach-omap2/board-am3517evm.c | 1 + arch/arm/mach-omap2/board-cm-t35.c | 1 + arch/arm/mach-omap2/board-devkit8000.c | 1 + arch/arm/mach-omap2/board-omap3evm.c | 1 + arch/arm/mach-omap2/board-omap3stalker.c | 1 + include/video/omap-panel-tfp410.h | 2 +- 7 files changed, 7 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 7b201546834..bb73afc9ac1 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -157,6 +157,7 @@ static struct omap_dss_device sdp3430_lcd_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = -1, + .i2c_bus_num = -1, }; static struct omap_dss_device sdp3430_dvi_device = { diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index 4be58fd071f..f81a303b87f 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -208,6 +208,7 @@ static struct omap_dss_device am3517_evm_tv_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = -1, + .i2c_bus_num = -1, }; static struct omap_dss_device am3517_evm_dvi_device = { diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index c8e37dc0089..b3102c2f4a3 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -241,6 +241,7 @@ static struct omap_dss_device cm_t35_lcd_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = CM_T35_DVI_EN_GPIO, + .i2c_bus_num = -1, }; static struct omap_dss_device cm_t35_dvi_device = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index 7667eb74952..12865af25d3 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -141,6 +141,7 @@ static struct omap_dss_device devkit8000_lcd_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = -1, + .i2c_bus_num = 1, }; static struct omap_dss_device devkit8000_dvi_device = { diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 54647d6286b..3985f35aee0 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -240,6 +240,7 @@ static struct omap_dss_device omap3_evm_tv_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, + .i2c_bus_num = -1, }; static struct omap_dss_device omap3_evm_dvi_device = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index d8638b3b4f9..53a6cbcf974 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -118,6 +118,7 @@ static struct omap_dss_device omap3_stalker_tv_device = { static struct tfp410_platform_data dvi_panel = { .power_down_gpio = DSS_ENABLE_GPIO, + .i2c_bus_num = -1, }; static struct omap_dss_device omap3_stalker_dvi_device = { diff --git a/include/video/omap-panel-tfp410.h b/include/video/omap-panel-tfp410.h index 68c31d79c57..aef35e48bc7 100644 --- a/include/video/omap-panel-tfp410.h +++ b/include/video/omap-panel-tfp410.h @@ -28,7 +28,7 @@ struct omap_dss_device; * @power_down_gpio: gpio number for PD pin (or -1 if not available) */ struct tfp410_platform_data { - u16 i2c_bus_num; + int i2c_bus_num; int power_down_gpio; }; -- cgit v1.2.3-70-g09d2 From 421e84509980206fb3b3bc039bc05bae1dd41c7b Mon Sep 17 00:00:00 2001 From: Oleg Matcovschi Date: Mon, 26 Nov 2012 17:02:03 -0800 Subject: OMAP2+: mux: Fixed gpio mux mode analysis OMAP_MODE_GPIO() macro verified only OMAP_MUX_MODE4. It is not correct for following platforms: 2430 - gpio mux mode 3 44xx - gpio mux mode 3 54xx - gpio mux mode 6 Patch reserves first 3 bits in partition flags for storing gpio mux mode in same format as stored in control pad register. Modified OMAP_MODE_GPIO() macro to handle all possible cases of gpio mux mode. Modified omap_mux_init() flags of omap34xx to include OMAP_MUX_GPIO_IN_MODE4. Signed-off-by: Oleg Matcovschi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/mux.c | 10 ++++------ arch/arm/mach-omap2/mux.h | 20 +++++++++++++++----- arch/arm/mach-omap2/mux34xx.c | 2 +- 3 files changed, 20 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 26126343d6a..6a217c98db5 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -135,10 +135,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, old_mode = omap_mux_read(partition, gpio_mux->reg_offset); mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - if (partition->flags & OMAP_MUX_GPIO_IN_MODE3) - mux_mode |= OMAP_MUX_MODE3; - else - mux_mode |= OMAP_MUX_MODE4; + mux_mode |= partition->gpio; pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__, gpio_mux->muxnames[0], gpio, old_mode, mux_mode); omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); @@ -800,7 +797,7 @@ int __init omap_mux_late_init(void) struct omap_mux *m = &e->mux; u16 mode = omap_mux_read(partition, m->reg_offset); - if (OMAP_MODE_GPIO(mode)) + if (OMAP_MODE_GPIO(partition, mode)) continue; #ifndef CONFIG_DEBUG_FS @@ -1065,7 +1062,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition, } #else /* Skip pins that are not muxed as GPIO by bootloader */ - if (!OMAP_MODE_GPIO(omap_mux_read(partition, + if (!OMAP_MODE_GPIO(partition, omap_mux_read(partition, superset->reg_offset))) { superset++; continue; @@ -1132,6 +1129,7 @@ int __init omap_mux_init(const char *name, u32 flags, partition->name = name; partition->flags = flags; + partition->gpio = flags & OMAP_MUX_MODE7; partition->size = mux_size; partition->phys = mux_pbase; partition->base = ioremap(mux_pbase, mux_size); diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 76f9b3c2f58..fdb22f14021 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -58,7 +58,8 @@ #define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN) #define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN -#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) +#define OMAP_MODE_GPIO(partition, x) (((x) & OMAP_MUX_MODE7) == \ + partition->gpio) #define OMAP_MODE_UART(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE0) /* Flags for omapX_mux_init */ @@ -79,13 +80,20 @@ /* * omap_mux_init flags definition: * + * OMAP_GPIO_MUX_MODE, bits 0-2: gpio muxing mode, same like pad control + * register which includes values from 0-7. * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits. * The default value is 16 bits. - * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3. - * The default is mode4. */ -#define OMAP_MUX_REG_8BIT (1 << 0) -#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1) +#define OMAP_MUX_GPIO_IN_MODE0 OMAP_MUX_MODE0 +#define OMAP_MUX_GPIO_IN_MODE1 OMAP_MUX_MODE1 +#define OMAP_MUX_GPIO_IN_MODE2 OMAP_MUX_MODE2 +#define OMAP_MUX_GPIO_IN_MODE3 OMAP_MUX_MODE3 +#define OMAP_MUX_GPIO_IN_MODE4 OMAP_MUX_MODE4 +#define OMAP_MUX_GPIO_IN_MODE5 OMAP_MUX_MODE5 +#define OMAP_MUX_GPIO_IN_MODE6 OMAP_MUX_MODE6 +#define OMAP_MUX_GPIO_IN_MODE7 OMAP_MUX_MODE7 +#define OMAP_MUX_REG_8BIT (1 << 3) /** * struct omap_board_data - board specific device data @@ -105,6 +113,7 @@ struct omap_board_data { * struct mux_partition - contain partition related information * @name: name of the current partition * @flags: flags specific to this partition + * @gpio: gpio mux mode * @phys: physical address * @size: partition size * @base: virtual address after ioremap @@ -114,6 +123,7 @@ struct omap_board_data { struct omap_mux_partition { const char *name; u32 flags; + u32 gpio; u32 phys; u32 size; void __iomem *base; diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index c47140bbbec..c53609f4629 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2053,7 +2053,7 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) return -EINVAL; } - return omap_mux_init("core", 0, + return omap_mux_init("core", OMAP_MUX_GPIO_IN_MODE4, OMAP3_CONTROL_PADCONF_MUX_PBASE, OMAP3_CONTROL_PADCONF_MUX_SIZE, omap3_muxmodes, package_subset, board_subset, -- cgit v1.2.3-70-g09d2 From 86c35960852b726a1d773ae65302dcfb24267180 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 13 Nov 2012 16:02:19 -0600 Subject: ARM: OMAP2420: Fix ethernet support for OMAP2420 H4 Ethernet is not currently working on the OMAP2420 H4 board. In commit f604931 (ARM: OMAP: abstract debug card setup (smc, leds)) the function h4_init_smc91x() that initialised the ethernet controller was renamed to h4_init_debug() but was never called when initialising the board. Adding a call to h4_init_debug() fixes ethernet support, however, instead of using the legacy H4 code migrate the H4 to use the gpmc_smc91x_init() function instead and remove the legacy H4 code. Signed-off-by: Jon Hunter Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-h4.c | 83 ++++++++++-------------------------------- 1 file changed, 20 insertions(+), 63 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 9a3878ec225..3be1311f9e3 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -27,14 +27,12 @@ #include #include #include +#include #include #include #include -#include -#include - #include