From cded80f869aef94853e056ab9c21e305b0c26138 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 19 Dec 2013 16:51:02 +0100 Subject: ARM: shmobile: r8a7791: Add MSIOF clocks in device tree Signed-off-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0a821925814..6a29341462c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -394,6 +394,14 @@ }; /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "msiof0"; + }; mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; @@ -413,15 +421,16 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_SCIFB2 + R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 + R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 >; clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", - "scifb2"; + "scifa2", "scifa1", "scifa0", "misof2", "scifb0", + "scifb1", "msiof1", "scifb2"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3-70-g09d2