From c4eee283e004751143fb81dbf4f8cfe7b8dcc970 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Mon, 12 Nov 2007 01:05:16 +0900 Subject: [MIPS] Move inclusing of kernel/time/Kconfig menu to appropriate place CONFIG_NO_HZ, CONFIG_HIGH_RES_TIMERS should be selected in "Kernel type" menu, not in "CPU selection" menu. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c6fc405a6c8..291d368ffd2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -992,8 +992,6 @@ config BOOT_ELF64 menu "CPU selection" -source "kernel/time/Kconfig" - choice prompt "CPU type" default CPU_R4X00 @@ -1768,6 +1766,8 @@ config NR_CPUS performance should round up your number of processors to the next power of two. +source "kernel/time/Kconfig" + # # Timer Interrupt Frequency Configuration # -- cgit v1.2.3-70-g09d2 From 9cfacb790f581000a7ec8455785d131aca923ded Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 25 Dec 2007 21:00:45 +0300 Subject: [MIPS] Alchemy: Fix use of __init code bug exposed by modpost warning WARNING: vmlinux.o(.text+0x1ca608): Section mismatch: reference to .init.text: add_wired_entry (between 'config_access' and 'config_read') by refactoring the code calling add_wired_entry() from config_access() to a separate function which is called from aau1x_pci_setup(). While at it: - make some unnecassarily global variables 'static'; - fix the letter case, whitespace, etc. in the comments... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- arch/mips/au1000/common/pci.c | 8 +++++-- arch/mips/pci/ops-au1000.c | 53 +++++++++++++++++++++---------------------- 2 files changed, 32 insertions(+), 29 deletions(-) (limited to 'arch') diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 6fa70a36a25..ce771487567 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -1,8 +1,8 @@ /* * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 pci support. + * Alchemy/AMD Au1x00 PCI support. * - * Copyright 2001,2002,2003 MontaVista Software Inc. + * Copyright 2001-2003, 2007 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * @@ -66,6 +66,8 @@ static unsigned long virt_io_addr; static int __init au1x_pci_setup(void) { + extern void au1x_pci_cfg_init(void); + #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); @@ -94,6 +96,8 @@ static int __init au1x_pci_setup(void) set_io_port_base(virt_io_addr); #endif + au1x_pci_cfg_init(); + register_pci_controller(&au1x_controller); return 0; } diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c index 6b29904acf4..1314bd58f03 100644 --- a/arch/mips/pci/ops-au1000.c +++ b/arch/mips/pci/ops-au1000.c @@ -1,8 +1,8 @@ /* * BRIEF MODULE DESCRIPTION - * Alchemy/AMD Au1x00 pci support. + * Alchemy/AMD Au1x00 PCI support. * - * Copyright 2001,2002,2003 MontaVista Software Inc. + * Copyright 2001-2003, 2007 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * @@ -69,10 +69,27 @@ void mod_wired_entry(int entry, unsigned long entrylo0, write_c0_pagemask(old_pagemask); } -struct vm_struct *pci_cfg_vm; +static struct vm_struct *pci_cfg_vm; static int pci_cfg_wired_entry; -static int first_cfg = 1; -unsigned long last_entryLo0, last_entryLo1; +static unsigned long last_entryLo0, last_entryLo1; + +/* + * We can't ioremap the entire pci config space because it's too large. + * Nor can we call ioremap dynamically because some device drivers use + * the PCI config routines from within interrupt handlers and that + * becomes a problem in get_vm_area(). We use one wired TLB to handle + * all config accesses for all busses. + */ +void __init au1x_pci_cfg_init(void) +{ + /* Reserve a wired entry for PCI config accesses */ + pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); + if (!pci_cfg_vm) + panic(KERN_ERR "PCI unable to get vm area\n"); + pci_cfg_wired_entry = read_c0_wired(); + add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); + last_entryLo0 = last_entryLo1 = 0xffffffff; +} static int config_access(unsigned char access_type, struct pci_bus *bus, unsigned int dev_fn, unsigned char where, @@ -97,27 +114,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, Au1500_PCI_STATCMD); au_sync_udelay(1); - /* - * We can't ioremap the entire pci config space because it's - * too large. Nor can we call ioremap dynamically because some - * device drivers use the pci config routines from within - * interrupt handlers and that becomes a problem in get_vm_area(). - * We use one wired tlb to handle all config accesses for all - * busses. To improve performance, if the current device - * is the same as the last device accessed, we don't touch the - * tlb. - */ - if (first_cfg) { - /* reserve a wired entry for pci config accesses */ - first_cfg = 0; - pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); - if (!pci_cfg_vm) - panic(KERN_ERR "PCI unable to get vm area\n"); - pci_cfg_wired_entry = read_c0_wired(); - add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); - last_entryLo0 = last_entryLo1 = 0xffffffff; - } - /* Allow board vendors to implement their own off-chip idsel. * If it doesn't succeed, may as well bail out at this point. */ @@ -144,9 +140,12 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, /* page boundary */ cfg_base = cfg_base & PAGE_MASK; + /* + * To improve performance, if the current device is the same as + * the last device accessed, we don't touch the TLB. + */ entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; - if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, (unsigned long)pci_cfg_vm->addr, PM_4K); -- cgit v1.2.3-70-g09d2 From c990081bf87bf5afcd6d39d8bfce9c6d60b1f2eb Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Sat, 5 Jan 2008 12:13:11 +0100 Subject: [MIPS] Fix IP32 breakage - suppress master aborts during config read - set io_map_base - only fixup end of iomem resource to avoid failing request_resource in serial driver - killed useless setting of crime_int bit, which caused wrong interrupts - use physcial address for serial port platform device and let 8250 driver do the ioremap Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/pci/ops-mace.c | 7 +++++++ arch/mips/pci/pci-ip32.c | 4 +++- arch/mips/sgi-ip32/ip32-irq.c | 1 - arch/mips/sgi-ip32/ip32-platform.c | 20 +++++++++----------- 4 files changed, 19 insertions(+), 13 deletions(-) (limited to 'arch') diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c index fe545144930..e95881897ec 100644 --- a/arch/mips/pci/ops-mace.c +++ b/arch/mips/pci/ops-mace.c @@ -42,6 +42,10 @@ static int mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) { + u32 control = mace->pci.control; + + /* disable master aborts interrupts during config read */ + mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT; mace->pci.config_addr = mkaddr(bus, devfn, reg); switch (size) { case 1: @@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, *val = mace->pci.config_data.l; break; } + /* ack possible master abort */ + mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT; + mace->pci.control = control; DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c index 618ea7dbc47..532b561b444 100644 --- a/arch/mips/pci/pci-ip32.c +++ b/arch/mips/pci/pci-ip32.c @@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = { .iommu = 0, .mem_offset = MACE_PCI_MEM_OFFSET, .io_offset = 0, + .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO), }; static int __init mace_init(void) @@ -135,7 +136,8 @@ static int __init mace_init(void) BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0, "MACE PCI error", NULL)); - iomem_resource = mace_pci_mem_resource; + /* extend memory resources */ + iomem_resource.end = mace_pci_mem_resource.end; ioport_resource = mace_pci_io_resource; register_pci_controller(&mace_pci_controller); diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index cab7cc22ab6..b0ea0e43ba4 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c @@ -426,7 +426,6 @@ static void ip32_irq0(void) crime_int = crime->istat & crime_mask; irq = MACE_VID_IN1_IRQ + __ffs(crime_int); - crime_int = 1 << irq; if (crime_int & CRIME_MACEISA_INT_MASK) { unsigned long mace_int = mace->perif.ctrl.istat; diff --git a/arch/mips/sgi-ip32/ip32-platform.c b/arch/mips/sgi-ip32/ip32-platform.c index 77febd68fcd..89a71f49b69 100644 --- a/arch/mips/sgi-ip32/ip32-platform.c +++ b/arch/mips/sgi-ip32/ip32-platform.c @@ -13,21 +13,22 @@ #include #include -/* - * .iobase isn't a constant (in the sense of C) so we fill it in at runtime. - */ -#define MACE_PORT(int) \ +#define MACEISA_SERIAL1_OFFS offsetof(struct sgi_mace, isa.serial1) +#define MACEISA_SERIAL2_OFFS offsetof(struct sgi_mace, isa.serial2) + +#define MACE_PORT(offset,_irq) \ { \ - .irq = int, \ + .mapbase = MACE_BASE + offset, \ + .irq = _irq, \ .uartclk = 1843200, \ .iotype = UPIO_MEM, \ - .flags = UPF_SKIP_TEST, \ + .flags = UPF_SKIP_TEST|UPF_IOREMAP, \ .regshift = 8, \ } static struct plat_serial8250_port uart8250_data[] = { - MACE_PORT(MACEISA_SERIAL1_IRQ), - MACE_PORT(MACEISA_SERIAL2_IRQ), + MACE_PORT(MACEISA_SERIAL1_OFFS, MACEISA_SERIAL1_IRQ), + MACE_PORT(MACEISA_SERIAL2_OFFS, MACEISA_SERIAL2_IRQ), { }, }; @@ -41,9 +42,6 @@ static struct platform_device uart8250_device = { static int __init uart8250_init(void) { - uart8250_data[0].membase = (void __iomem *) &mace->isa.serial1; - uart8250_data[1].membase = (void __iomem *) &mace->isa.serial2; - return platform_device_register(&uart8250_device); } -- cgit v1.2.3-70-g09d2 From ce202cbb9e0b623671e8ecb3d53afdd42b8e458f Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Fri, 4 Jan 2008 23:38:31 +0100 Subject: [MIPS] Assume R4000/R4400 newer than 3.0 don't have the mfc0 count bug This seems as reasonable assumption and gets some SNI machines to work which currently must rely on the cp0 counter as clocksource. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/kernel/time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 1ecfbb7eba6..2995be1ab3c 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -147,9 +147,9 @@ static __init int cpu_has_mfc0_count_bug(void) return 1; /* - * I don't have erratas for newer R4400 so be paranoid. + * we assume newer revisions are ok */ - return 1; + return 0; } return 0; -- cgit v1.2.3-70-g09d2 From ba820c5c51296343be202c9afb072b7b943099cb Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 7 Jan 2008 15:09:50 +0000 Subject: [MIPS] Fix CONFIG_BOOT_RAW. This was broken by 017e3a492683b32d17dcd1b13b279745cc656073 (lmo) / 396a2ae08e5080b140330645743ab2567f6bc426 (kernel.org). Signed-off-by: Ralf Baechle --- arch/mips/kernel/head.S | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 23676873106..50be56c9e9e 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -136,7 +136,8 @@ EXPORT(_stext) * kernel load address. This is needed because this platform does * not have a ELF loader yet. */ - __INIT +FEXPORT(__kernel_entry) + j kernel_entry #endif __INIT_REFOK -- cgit v1.2.3-70-g09d2