From 270b9f421e66ee5d135c99ba1c2b883c7750ab6c Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Wed, 11 Apr 2012 18:04:23 +0530 Subject: SPEAr: clk: Add Fractional Synthesizer clock All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from following equations: Fout = Fin / (2 * div) (division factor) div is 17 bits:- 0-13 (fractional part) 14-16 (integer part) div is (16-14 bits).(13-0 bits) (in binary) Fout = Fin/(2 * div) Fout = ((Fin / 10000)/(2 * div)) * 10000 Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 div << 14 is simply 17 bit value written at register. This patch adds in support for this type of clock. Signed-off-by: Viresh Kumar Reviewed-by: Mike Turquette --- drivers/clk/spear/clk.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/clk/spear/clk.h') diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h index c2290800503..ac9030bbd6c 100644 --- a/drivers/clk/spear/clk.h +++ b/drivers/clk/spear/clk.h @@ -55,6 +55,19 @@ struct clk_aux { spinlock_t *lock; }; +/* Fractional Synth clk */ +struct frac_rate_tbl { + u32 div; +}; + +struct clk_frac { + struct clk_hw hw; + void __iomem *reg; + struct frac_rate_tbl *rtbl; + u8 rtbl_cnt; + spinlock_t *lock; +}; + /* VCO-PLL clk */ struct pll_rate_tbl { u8 mode; @@ -87,6 +100,9 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name, const char *parent_name, unsigned long flags, void __iomem *reg, struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); +struct clk *clk_register_frac(const char *name, const char *parent_name, + unsigned long flags, void __iomem *reg, + struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock); struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name, const char *vco_gate_name, const char *parent_name, unsigned long flags, void __iomem *mode_reg, void __iomem -- cgit v1.2.3-70-g09d2