From b0504e39c27b00101c9c1fa2c58fd896ae0f64f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 18 Nov 2013 16:48:19 +0100 Subject: ARM: zynq: Map I/O memory on clkc init The clkc has its registers in the range of the slcr. Instead of passing around the slcr base address pointer, let the clkc get the address from the DT. This prepares the slcr to be a real driver with multiple memory ranges (slcr, clocks, pinctrl,...) Signed-off-by: Steffen Trumtrar Signed-off-by: Michal Simek --- drivers/clk/zynq/clkc.c | 89 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 63 insertions(+), 26 deletions(-) (limited to 'drivers/clk') diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 09dd0173ea0..03052d67b19 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -21,34 +21,35 @@ #include #include #include +#include #include #include #include -static void __iomem *zynq_slcr_base_priv; - -#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) -#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) -#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) -#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) -#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) -#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) -#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) -#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) -#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) -#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) -#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) -#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) -#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) -#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) -#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) -#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) -#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) -#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) -#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) -#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) -#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) -#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) +static void __iomem *zynq_clkc_base; + +#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00) +#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04) +#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08) +#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c) +#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20) +#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24) +#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28) +#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c) +#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40) +#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44) +#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48) +#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c) +#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50) +#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54) +#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58) +#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c) +#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60) +#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64) +#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68) +#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70) +#define SLCR_621_TRUE (zynq_clkc_base + 0xc4) +#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204) #define NUM_MIO_PINS 54 @@ -569,8 +570,44 @@ static void __init zynq_clk_setup(struct device_node *np) CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); -void __init zynq_clock_init(void __iomem *slcr_base) +void __init zynq_clock_init(void) { - zynq_slcr_base_priv = slcr_base; + struct device_node *np; + struct device_node *slcr; + struct resource res; + + np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc"); + if (!np) { + pr_err("%s: clkc node not found\n", __func__); + goto np_err; + } + + if (of_address_to_resource(np, 0, &res)) { + pr_err("%s: failed to get resource\n", np->name); + goto np_err; + } + + slcr = of_get_parent(np); + + if (slcr->data) { + zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; + } else { + pr_err("%s: Unable to get I/O memory\n", np->name); + of_node_put(slcr); + goto np_err; + } + + pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base); + + of_node_put(slcr); + of_node_put(np); + of_clk_init(NULL); + + return; + +np_err: + of_node_put(np); + BUG(); + return; } -- cgit v1.2.3-70-g09d2 From cc0cc4ca093f3df9e554af8dae39a126987bccf7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 13 Feb 2014 20:07:26 +0100 Subject: ARM: integrator: localize the impd1.h header As we move toward multiplatform support for the Integrator family we need to localize all headers. This moves the impd1.h header down to the machine folder, copying the the three defines only used by the clock driver down into the clock driver. Cc: Will Deacon Cc: Jonathan Austin Cc: Russell King Cc: Mike Turquette Signed-off-by: Linus Walleij --- arch/arm/mach-integrator/impd1.c | 2 +- arch/arm/mach-integrator/impd1.h | 14 ++++++++++++++ arch/arm/mach-integrator/include/mach/impd1.h | 18 ------------------ drivers/clk/versatile/clk-impd1.c | 6 ++++-- 4 files changed, 19 insertions(+), 21 deletions(-) create mode 100644 arch/arm/mach-integrator/impd1.h delete mode 100644 arch/arm/mach-integrator/include/mach/impd1.h (limited to 'drivers/clk') diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index a90e83fe877..0e870ea818c 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -25,9 +25,9 @@ #include #include -#include #include #include "lm.h" +#include "impd1.h" static int module_id; diff --git a/arch/arm/mach-integrator/impd1.h b/arch/arm/mach-integrator/impd1.h new file mode 100644 index 00000000000..76de4dc9bee --- /dev/null +++ b/arch/arm/mach-integrator/impd1.h @@ -0,0 +1,14 @@ +#define IMPD1_LEDS 0x0c +#define IMPD1_INT 0x10 +#define IMPD1_SW 0x14 +#define IMPD1_CTRL 0x18 + +#define IMPD1_CTRL_DISP_LCD (0 << 0) +#define IMPD1_CTRL_DISP_VGA (1 << 0) +#define IMPD1_CTRL_DISP_LCD1 (2 << 0) +#define IMPD1_CTRL_DISP_ENABLE (1 << 2) +#define IMPD1_CTRL_DISP_MASK (7 << 0) + +struct device; + +void impd1_tweak_control(struct device *dev, u32 mask, u32 val); diff --git a/arch/arm/mach-integrator/include/mach/impd1.h b/arch/arm/mach-integrator/include/mach/impd1.h deleted file mode 100644 index d75de4b1423..00000000000 --- a/arch/arm/mach-integrator/include/mach/impd1.h +++ /dev/null @@ -1,18 +0,0 @@ -#define IMPD1_OSC1 0x00 -#define IMPD1_OSC2 0x04 -#define IMPD1_LOCK 0x08 -#define IMPD1_LEDS 0x0c -#define IMPD1_INT 0x10 -#define IMPD1_SW 0x14 -#define IMPD1_CTRL 0x18 - -#define IMPD1_CTRL_DISP_LCD (0 << 0) -#define IMPD1_CTRL_DISP_VGA (1 << 0) -#define IMPD1_CTRL_DISP_LCD1 (2 << 0) -#define IMPD1_CTRL_DISP_ENABLE (1 << 2) -#define IMPD1_CTRL_DISP_MASK (7 << 0) - -struct device; - -void impd1_tweak_control(struct device *dev, u32 mask, u32 val); - diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c index 6d8b8e1a080..31b44f025f9 100644 --- a/drivers/clk/versatile/clk-impd1.c +++ b/drivers/clk/versatile/clk-impd1.c @@ -13,10 +13,12 @@ #include #include -#include - #include "clk-icst.h" +#define IMPD1_OSC1 0x00 +#define IMPD1_OSC2 0x04 +#define IMPD1_LOCK 0x08 + struct impd1_clk { char *vco1name; struct clk *vco1clk; -- cgit v1.2.3-70-g09d2 From 4a32c74e762236a53627536b9b9c1693d3073359 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 5 Feb 2014 15:41:51 +0100 Subject: ARM: zynq: Move of_clk_init from clock driver Move of_clk_init() from clock driver to enable options not to use zynq clock driver. Use for example fixed clock setting. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/common.c | 2 ++ drivers/clk/zynq/clkc.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/clk') diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 93ea19b13e6..5755129a6e4 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -68,6 +69,7 @@ static void __init zynq_timer_init(void) zynq_early_slcr_init(); zynq_clock_init(); + of_clk_init(NULL); clocksource_of_init(); } diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 03052d67b19..c812b93a52b 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -602,8 +602,6 @@ void __init zynq_clock_init(void) of_node_put(slcr); of_node_put(np); - of_clk_init(NULL); - return; np_err: -- cgit v1.2.3-70-g09d2 From 602408e3de70d132c115670a366f4c5ae657080c Mon Sep 17 00:00:00 2001 From: Tushar Behera Date: Fri, 21 Mar 2014 04:31:30 +0900 Subject: dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. Signed-off-by: Tushar Behera Reviewed-by: Sachin Kamat Acked-by: Tomasz Figa Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 2 +- drivers/clk/samsung/clk-exynos-audss.c | 2 +- include/dt-bindings/clk/exynos-audss-clk.h | 26 -------------------------- include/dt-bindings/clock/exynos-audss-clk.h | 26 ++++++++++++++++++++++++++ 5 files changed, 29 insertions(+), 29 deletions(-) delete mode 100644 include/dt-bindings/clk/exynos-audss-clk.h create mode 100644 include/dt-bindings/clock/exynos-audss-clk.h (limited to 'drivers/clk') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index affb393755c..d1a46d6f944 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -20,7 +20,7 @@ #include "exynos5.dtsi" #include "exynos5250-pinctrl.dtsi" -#include +#include / { compatible = "samsung,exynos5250", "samsung,exynos5"; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index bbc8ed829b0..51d1475ca88 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -16,7 +16,7 @@ #include "exynos5.dtsi" #include "exynos5420-pinctrl.dtsi" -#include +#include / { compatible = "samsung,exynos5420", "samsung,exynos5"; diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 884187fbfe0..13eae14c2cc 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -17,7 +17,7 @@ #include #include -#include +#include enum exynos_audss_clk_type { TYPE_EXYNOS4210, diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h deleted file mode 100644 index 0ae6f5a75d2..00000000000 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This header provides constants for Samsung audio subsystem - * clock controller. - * - * The constants defined in this header are being used in dts - * and exynos audss driver. - */ - -#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H -#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H - -#define EXYNOS_MOUT_AUDSS 0 -#define EXYNOS_MOUT_I2S 1 -#define EXYNOS_DOUT_SRP 2 -#define EXYNOS_DOUT_AUD_BUS 3 -#define EXYNOS_DOUT_I2S 4 -#define EXYNOS_SRP_CLK 5 -#define EXYNOS_I2S_BUS 6 -#define EXYNOS_SCLK_I2S 7 -#define EXYNOS_PCM_BUS 8 -#define EXYNOS_SCLK_PCM 9 -#define EXYNOS_ADMA 10 - -#define EXYNOS_AUDSS_MAX_CLKS 11 - -#endif diff --git a/include/dt-bindings/clock/exynos-audss-clk.h b/include/dt-bindings/clock/exynos-audss-clk.h new file mode 100644 index 00000000000..0ae6f5a75d2 --- /dev/null +++ b/include/dt-bindings/clock/exynos-audss-clk.h @@ -0,0 +1,26 @@ +/* + * This header provides constants for Samsung audio subsystem + * clock controller. + * + * The constants defined in this header are being used in dts + * and exynos audss driver. + */ + +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H + +#define EXYNOS_MOUT_AUDSS 0 +#define EXYNOS_MOUT_I2S 1 +#define EXYNOS_DOUT_SRP 2 +#define EXYNOS_DOUT_AUD_BUS 3 +#define EXYNOS_DOUT_I2S 4 +#define EXYNOS_SRP_CLK 5 +#define EXYNOS_I2S_BUS 6 +#define EXYNOS_SCLK_I2S 7 +#define EXYNOS_PCM_BUS 8 +#define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 + +#define EXYNOS_AUDSS_MAX_CLKS 11 + +#endif -- cgit v1.2.3-70-g09d2