From 85a8885bd0e00569108aa7b5e26b89c752e3cd51 Mon Sep 17 00:00:00 2001 From: Aravind Gopalakrishnan Date: Thu, 20 Feb 2014 10:28:46 -0600 Subject: amd64_edac: Add support for newer F16h models Extend ECC decoding support for F16h M30h. Tested on F16h M30h with ECC turned on using mce_amd_inj module and the patch works fine. Signed-off-by: Aravind Gopalakrishnan Link: http://lkml.kernel.org/r/1392913726-16961-1-git-send-email-Aravind.Gopalakrishnan@amd.com Tested-by: Arindam Nath Acked-by: H. Peter Anvin Signed-off-by: Borislav Petkov --- drivers/edac/amd64_edac.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/edac/amd64_edac.c') diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 34380ccc3dd..f8bf00010d4 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1807,6 +1807,17 @@ static struct amd64_family_type family_types[] = { .read_dct_pci_cfg = f10_read_dct_pci_cfg, } }, + [F16_M30H_CPUS] = { + .ctl_name = "F16h_M30h", + .f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1, + .f3_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F3, + .ops = { + .early_channel_count = f1x_early_channel_count, + .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, + .dbam_to_cs = f16_dbam_to_chip_select, + .read_dct_pci_cfg = f10_read_dct_pci_cfg, + } + }, }; /* @@ -2586,6 +2597,11 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) break; case 0x16: + if (pvt->model == 0x30) { + fam_type = &family_types[F16_M30H_CPUS]; + pvt->ops = &family_types[F16_M30H_CPUS].ops; + break; + } fam_type = &family_types[F16_CPUS]; pvt->ops = &family_types[F16_CPUS].ops; break; @@ -2838,6 +2854,14 @@ static const struct pci_device_id amd64_pci_table[] = { .class = 0, .class_mask = 0, }, + { + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .class = 0, + .class_mask = 0, + }, {0, } }; -- cgit v1.2.3-70-g09d2