From 4efec6272e8e61fc77132b4d2bae56d61b289956 Mon Sep 17 00:00:00 2001 From: Roel Kluin Date: Tue, 15 Dec 2009 16:46:18 -0800 Subject: gpio: fix test on unsigned in lnw_irq_type() The wrong test was used, gpio is unsigned and it had an off-by-one. Signed-off-by: Roel Kluin Cc: Alek Du Cc: David Brownell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/langwell_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c index 4baf3d7d0f8..6c0ebbdc659 100644 --- a/drivers/gpio/langwell_gpio.c +++ b/drivers/gpio/langwell_gpio.c @@ -123,7 +123,7 @@ static int lnw_irq_type(unsigned irq, unsigned type) void __iomem *grer = (void __iomem *)(&lnw->reg_base->GRER[reg]); void __iomem *gfer = (void __iomem *)(&lnw->reg_base->GFER[reg]); - if (gpio < 0 || gpio > lnw->chip.ngpio) + if (gpio >= lnw->chip.ngpio) return -EINVAL; spin_lock_irqsave(&lnw->lock, flags); if (type & IRQ_TYPE_EDGE_RISING) -- cgit v1.2.3-70-g09d2 From 35570ac6039ef490b9c5abde1fee4803a39bf4e1 Mon Sep 17 00:00:00 2001 From: Richard Röjfors Date: Tue, 15 Dec 2009 16:46:18 -0800 Subject: gpio: add GPIO driver for the Timberdale FPGA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A GPIO driver for the Timberdale FPGA found on the Intel Atom board Russellville. The GPIO driver also has an IRQ-chip to support interrupts on the pins. Signed-off-by: Richard Röjfors Cc: David Brownell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/timbgpio.c | 342 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/timb_gpio.h | 37 +++++ 4 files changed, 386 insertions(+) create mode 100644 drivers/gpio/timbgpio.c create mode 100644 include/linux/timb_gpio.h (limited to 'drivers/gpio') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 57ca339924e..a019b49ecc9 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -206,6 +206,12 @@ config GPIO_LANGWELL help Say Y here to support Intel Moorestown platform GPIO. +config GPIO_TIMBERDALE + bool "Support for timberdale GPIO IP" + depends on MFD_TIMBERDALE && GPIOLIB && HAS_IOMEM + ---help--- + Add support for the GPIO IP in the timberdale FPGA. + comment "SPI GPIO expanders:" config GPIO_MAX7301 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 270b6d7839f..52fe4cf734c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o obj-$(CONFIG_GPIO_PCA953X) += pca953x.o obj-$(CONFIG_GPIO_PCF857X) += pcf857x.o obj-$(CONFIG_GPIO_PL061) += pl061.o +obj-$(CONFIG_GPIO_TIMBERDALE) += timbgpio.o obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o obj-$(CONFIG_GPIO_UCB1400) += ucb1400_gpio.o obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c new file mode 100644 index 00000000000..a4d344ba8e5 --- /dev/null +++ b/drivers/gpio/timbgpio.c @@ -0,0 +1,342 @@ +/* + * timbgpio.c timberdale FPGA GPIO driver + * Copyright (c) 2009 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* Supports: + * Timberdale FPGA GPIO + */ + +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "timb-gpio" + +#define TGPIOVAL 0x00 +#define TGPIODIR 0x04 +#define TGPIO_IER 0x08 +#define TGPIO_ISR 0x0c +#define TGPIO_IPR 0x10 +#define TGPIO_ICR 0x14 +#define TGPIO_FLR 0x18 +#define TGPIO_LVR 0x1c + +struct timbgpio { + void __iomem *membase; + spinlock_t lock; /* mutual exclusion */ + struct gpio_chip gpio; + int irq_base; +}; + +static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, + unsigned offset, bool enabled) +{ + struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); + u32 reg; + + spin_lock(&tgpio->lock); + reg = ioread32(tgpio->membase + offset); + + if (enabled) + reg |= (1 << index); + else + reg &= ~(1 << index); + + iowrite32(reg, tgpio->membase + offset); + spin_unlock(&tgpio->lock); + + return 0; +} + +static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) +{ + return timbgpio_update_bit(gpio, nr, TGPIODIR, true); +} + +static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr) +{ + struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); + u32 value; + + value = ioread32(tgpio->membase + TGPIOVAL); + return (value & (1 << nr)) ? 1 : 0; +} + +static int timbgpio_gpio_direction_output(struct gpio_chip *gpio, + unsigned nr, int val) +{ + return timbgpio_update_bit(gpio, nr, TGPIODIR, false); +} + +static void timbgpio_gpio_set(struct gpio_chip *gpio, + unsigned nr, int val) +{ + timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0); +} + +static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset) +{ + struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio); + + if (tgpio->irq_base <= 0) + return -EINVAL; + + return tgpio->irq_base + offset; +} + +/* + * GPIO IRQ + */ +static void timbgpio_irq_disable(unsigned irq) +{ + struct timbgpio *tgpio = get_irq_chip_data(irq); + int offset = irq - tgpio->irq_base; + + timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0); +} + +static void timbgpio_irq_enable(unsigned irq) +{ + struct timbgpio *tgpio = get_irq_chip_data(irq); + int offset = irq - tgpio->irq_base; + + timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1); +} + +static int timbgpio_irq_type(unsigned irq, unsigned trigger) +{ + struct timbgpio *tgpio = get_irq_chip_data(irq); + int offset = irq - tgpio->irq_base; + unsigned long flags; + u32 lvr, flr; + + if (offset < 0 || offset > tgpio->gpio.ngpio) + return -EINVAL; + + spin_lock_irqsave(&tgpio->lock, flags); + + lvr = ioread32(tgpio->membase + TGPIO_LVR); + flr = ioread32(tgpio->membase + TGPIO_FLR); + + if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { + flr &= ~(1 << offset); + if (trigger & IRQ_TYPE_LEVEL_HIGH) + lvr |= 1 << offset; + else + lvr &= ~(1 << offset); + } + + if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) + return -EINVAL; + else { + flr |= 1 << offset; + /* opposite compared to the datasheet, but it mirrors the + * reality + */ + if (trigger & IRQ_TYPE_EDGE_FALLING) + lvr |= 1 << offset; + else + lvr &= ~(1 << offset); + } + + iowrite32(lvr, tgpio->membase + TGPIO_LVR); + iowrite32(flr, tgpio->membase + TGPIO_FLR); + iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); + spin_unlock_irqrestore(&tgpio->lock, flags); + + return 0; +} + +static void timbgpio_irq(unsigned int irq, struct irq_desc *desc) +{ + struct timbgpio *tgpio = get_irq_data(irq); + unsigned long ipr; + int offset; + + desc->chip->ack(irq); + ipr = ioread32(tgpio->membase + TGPIO_IPR); + iowrite32(ipr, tgpio->membase + TGPIO_ICR); + + for_each_bit(offset, &ipr, tgpio->gpio.ngpio) + generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset)); +} + +static struct irq_chip timbgpio_irqchip = { + .name = "GPIO", + .enable = timbgpio_irq_enable, + .disable = timbgpio_irq_disable, + .set_type = timbgpio_irq_type, +}; + +static int __devinit timbgpio_probe(struct platform_device *pdev) +{ + int err, i; + struct gpio_chip *gc; + struct timbgpio *tgpio; + struct resource *iomem; + struct timbgpio_platform_data *pdata = pdev->dev.platform_data; + int irq = platform_get_irq(pdev, 0); + + if (!pdata || pdata->nr_pins > 32) { + err = -EINVAL; + goto err_mem; + } + + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!iomem) { + err = -EINVAL; + goto err_mem; + } + + tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL); + if (!tgpio) { + err = -EINVAL; + goto err_mem; + } + tgpio->irq_base = pdata->irq_base; + + spin_lock_init(&tgpio->lock); + + if (!request_mem_region(iomem->start, resource_size(iomem), + DRIVER_NAME)) { + err = -EBUSY; + goto err_request; + } + + tgpio->membase = ioremap(iomem->start, resource_size(iomem)); + if (!tgpio->membase) { + err = -ENOMEM; + goto err_ioremap; + } + + gc = &tgpio->gpio; + + gc->label = dev_name(&pdev->dev); + gc->owner = THIS_MODULE; + gc->dev = &pdev->dev; + gc->direction_input = timbgpio_gpio_direction_input; + gc->get = timbgpio_gpio_get; + gc->direction_output = timbgpio_gpio_direction_output; + gc->set = timbgpio_gpio_set; + gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL; + gc->dbg_show = NULL; + gc->base = pdata->gpio_base; + gc->ngpio = pdata->nr_pins; + gc->can_sleep = 0; + + err = gpiochip_add(gc); + if (err) + goto err_chipadd; + + platform_set_drvdata(pdev, tgpio); + + /* make sure to disable interrupts */ + iowrite32(0x0, tgpio->membase + TGPIO_IER); + + if (irq < 0 || tgpio->irq_base <= 0) + return 0; + + for (i = 0; i < pdata->nr_pins; i++) { + set_irq_chip_and_handler_name(tgpio->irq_base + i, + &timbgpio_irqchip, handle_simple_irq, "mux"); + set_irq_chip_data(tgpio->irq_base + i, tgpio); +#ifdef CONFIG_ARM + set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE); +#endif + } + + set_irq_data(irq, tgpio); + set_irq_chained_handler(irq, timbgpio_irq); + + return 0; + +err_chipadd: + iounmap(tgpio->membase); +err_ioremap: + release_mem_region(iomem->start, resource_size(iomem)); +err_request: + kfree(tgpio); +err_mem: + printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err); + + return err; +} + +static int __devexit timbgpio_remove(struct platform_device *pdev) +{ + int err; + struct timbgpio_platform_data *pdata = pdev->dev.platform_data; + struct timbgpio *tgpio = platform_get_drvdata(pdev); + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + int irq = platform_get_irq(pdev, 0); + + if (irq >= 0 && tgpio->irq_base > 0) { + int i; + for (i = 0; i < pdata->nr_pins; i++) { + set_irq_chip(tgpio->irq_base + i, NULL); + set_irq_chip_data(tgpio->irq_base + i, NULL); + } + + set_irq_handler(irq, NULL); + set_irq_data(irq, NULL); + } + + err = gpiochip_remove(&tgpio->gpio); + if (err) + printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n"); + + iounmap(tgpio->membase); + release_mem_region(iomem->start, resource_size(iomem)); + kfree(tgpio); + + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver timbgpio_platform_driver = { + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, + .probe = timbgpio_probe, + .remove = timbgpio_remove, +}; + +/*--------------------------------------------------------------------------*/ + +static int __init timbgpio_init(void) +{ + return platform_driver_register(&timbgpio_platform_driver); +} + +static void __exit timbgpio_exit(void) +{ + platform_driver_unregister(&timbgpio_platform_driver); +} + +module_init(timbgpio_init); +module_exit(timbgpio_exit); + +MODULE_DESCRIPTION("Timberdale GPIO driver"); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Mocean Laboratories"); +MODULE_ALIAS("platform:"DRIVER_NAME); + diff --git a/include/linux/timb_gpio.h b/include/linux/timb_gpio.h new file mode 100644 index 00000000000..ce456eaae86 --- /dev/null +++ b/include/linux/timb_gpio.h @@ -0,0 +1,37 @@ +/* + * timb_gpio.h timberdale FPGA GPIO driver, platform data definition + * Copyright (c) 2009 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _LINUX_TIMB_GPIO_H +#define _LINUX_TIMB_GPIO_H + +/** + * struct timbgpio_platform_data - Platform data of the Timberdale GPIO driver + * @gpio_base The number of the first GPIO pin, set to -1 for + * dynamic number allocation. + * @nr_pins Number of pins that is supported by the hardware (1-32) + * @irq_base If IRQ is supported by the hardware, this is the base + * number of IRQ:s. One IRQ per pin will be used. Set to + * -1 if IRQ:s is not supported. + */ +struct timbgpio_platform_data { + int gpio_base; + int nr_pins; + int irq_base; +}; + +#endif -- cgit v1.2.3-70-g09d2 From 0769746183caff9d4334be48c7b0e7d2ec8716c4 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 15 Dec 2009 16:46:20 -0800 Subject: gpiolib: add support for changing value polarity in sysfs Drivers may use gpiolib sysfs as part of their public user space interface. The GPIO number and polarity might change from board to board. The gpio_export_link() call can be used to hide the GPIO number from user space. Add support for also hiding the GPIO line polarity changes from user space. Signed-off-by: Jani Nikula Cc: David Brownell Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- Documentation/gpio.txt | 15 +++++ drivers/gpio/gpiolib.c | 161 +++++++++++++++++++++++++++++++++++++++++---- include/asm-generic/gpio.h | 6 ++ include/linux/gpio.h | 6 ++ 4 files changed, 176 insertions(+), 12 deletions(-) (limited to 'drivers/gpio') diff --git a/Documentation/gpio.txt b/Documentation/gpio.txt index e4e7daed2ba..1866c27eec6 100644 --- a/Documentation/gpio.txt +++ b/Documentation/gpio.txt @@ -531,6 +531,13 @@ and have the following read/write attributes: This file exists only if the pin can be configured as an interrupt generating input pin. + "active_low" ... reads as either 0 (false) or 1 (true). Write + any nonzero value to invert the value attribute both + for reading and writing. Existing and subsequent + poll(2) support configuration via the edge attribute + for "rising" and "falling" edges will follow this + setting. + GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the controller implementing GPIOs starting at #42) and have the following read-only attributes: @@ -566,6 +573,8 @@ requested using gpio_request(): int gpio_export_link(struct device *dev, const char *name, unsigned gpio) + /* change the polarity of a GPIO node in sysfs */ + int gpio_sysfs_set_active_low(unsigned gpio, int value); After a kernel driver requests a GPIO, it may only be made available in the sysfs interface by gpio_export(). The driver can control whether the @@ -580,3 +589,9 @@ After the GPIO has been exported, gpio_export_link() allows creating symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can use this to provide the interface under their own device in sysfs with a descriptive name. + +Drivers can use gpio_sysfs_set_active_low() to hide GPIO line polarity +differences between boards from user space. This only affects the +sysfs interface. Polarity change can be done both before and after +gpio_export(), and previously enabled poll(2) support for either +rising or falling edge will be reconfigured to follow this setting. diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 50de0f5750d..a25ad284a27 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -53,6 +53,7 @@ struct gpio_desc { #define FLAG_SYSFS 4 /* exported via /sys/class/gpio/control */ #define FLAG_TRIG_FALL 5 /* trigger on falling edge */ #define FLAG_TRIG_RISE 6 /* trigger on rising edge */ +#define FLAG_ACTIVE_LOW 7 /* sysfs value has active low */ #define PDESC_ID_SHIFT 16 /* add new flags before this one */ @@ -210,6 +211,11 @@ static DEFINE_MUTEX(sysfs_lock); * * configures behavior of poll(2) on /value * * available only if pin can generate IRQs on input * * is read/write as "none", "falling", "rising", or "both" + * /active_low + * * configures polarity of /value + * * is read/write as zero/nonzero + * * also affects existing and subsequent "falling" and "rising" + * /edge configuration */ static ssize_t gpio_direction_show(struct device *dev, @@ -255,7 +261,7 @@ static ssize_t gpio_direction_store(struct device *dev, return status ? : size; } -static const DEVICE_ATTR(direction, 0644, +static /* const */ DEVICE_ATTR(direction, 0644, gpio_direction_show, gpio_direction_store); static ssize_t gpio_value_show(struct device *dev, @@ -267,10 +273,17 @@ static ssize_t gpio_value_show(struct device *dev, mutex_lock(&sysfs_lock); - if (!test_bit(FLAG_EXPORT, &desc->flags)) + if (!test_bit(FLAG_EXPORT, &desc->flags)) { status = -EIO; - else - status = sprintf(buf, "%d\n", !!gpio_get_value_cansleep(gpio)); + } else { + int value; + + value = !!gpio_get_value_cansleep(gpio); + if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) + value = !value; + + status = sprintf(buf, "%d\n", value); + } mutex_unlock(&sysfs_lock); return status; @@ -294,6 +307,8 @@ static ssize_t gpio_value_store(struct device *dev, status = strict_strtol(buf, 0, &value); if (status == 0) { + if (test_bit(FLAG_ACTIVE_LOW, &desc->flags)) + value = !value; gpio_set_value_cansleep(gpio, value != 0); status = size; } @@ -303,7 +318,7 @@ static ssize_t gpio_value_store(struct device *dev, return status; } -static /*const*/ DEVICE_ATTR(value, 0644, +static const DEVICE_ATTR(value, 0644, gpio_value_show, gpio_value_store); static irqreturn_t gpio_sysfs_irq(int irq, void *priv) @@ -352,9 +367,11 @@ static int gpio_setup_irq(struct gpio_desc *desc, struct device *dev, irq_flags = IRQF_SHARED; if (test_bit(FLAG_TRIG_FALL, &gpio_flags)) - irq_flags |= IRQF_TRIGGER_FALLING; + irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? + IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING; if (test_bit(FLAG_TRIG_RISE, &gpio_flags)) - irq_flags |= IRQF_TRIGGER_RISING; + irq_flags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ? + IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING; if (!pdesc) { pdesc = kmalloc(sizeof(*pdesc), GFP_KERNEL); @@ -475,9 +492,79 @@ found: static DEVICE_ATTR(edge, 0644, gpio_edge_show, gpio_edge_store); +static int sysfs_set_active_low(struct gpio_desc *desc, struct device *dev, + int value) +{ + int status = 0; + + if (!!test_bit(FLAG_ACTIVE_LOW, &desc->flags) == !!value) + return 0; + + if (value) + set_bit(FLAG_ACTIVE_LOW, &desc->flags); + else + clear_bit(FLAG_ACTIVE_LOW, &desc->flags); + + /* reconfigure poll(2) support if enabled on one edge only */ + if (dev != NULL && (!!test_bit(FLAG_TRIG_RISE, &desc->flags) ^ + !!test_bit(FLAG_TRIG_FALL, &desc->flags))) { + unsigned long trigger_flags = desc->flags & GPIO_TRIGGER_MASK; + + gpio_setup_irq(desc, dev, 0); + status = gpio_setup_irq(desc, dev, trigger_flags); + } + + return status; +} + +static ssize_t gpio_active_low_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct gpio_desc *desc = dev_get_drvdata(dev); + ssize_t status; + + mutex_lock(&sysfs_lock); + + if (!test_bit(FLAG_EXPORT, &desc->flags)) + status = -EIO; + else + status = sprintf(buf, "%d\n", + !!test_bit(FLAG_ACTIVE_LOW, &desc->flags)); + + mutex_unlock(&sysfs_lock); + + return status; +} + +static ssize_t gpio_active_low_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct gpio_desc *desc = dev_get_drvdata(dev); + ssize_t status; + + mutex_lock(&sysfs_lock); + + if (!test_bit(FLAG_EXPORT, &desc->flags)) { + status = -EIO; + } else { + long value; + + status = strict_strtol(buf, 0, &value); + if (status == 0) + status = sysfs_set_active_low(desc, dev, value != 0); + } + + mutex_unlock(&sysfs_lock); + + return status ? : size; +} + +static const DEVICE_ATTR(active_low, 0644, + gpio_active_low_show, gpio_active_low_store); + static const struct attribute *gpio_attrs[] = { - &dev_attr_direction.attr, &dev_attr_value.attr, + &dev_attr_active_low.attr, NULL, }; @@ -662,12 +749,12 @@ int gpio_export(unsigned gpio, bool direction_may_change) dev = device_create(&gpio_class, desc->chip->dev, MKDEV(0, 0), desc, ioname ? ioname : "gpio%d", gpio); if (!IS_ERR(dev)) { - if (direction_may_change) - status = sysfs_create_group(&dev->kobj, + status = sysfs_create_group(&dev->kobj, &gpio_attr_group); - else + + if (!status && direction_may_change) status = device_create_file(dev, - &dev_attr_value); + &dev_attr_direction); if (!status && gpio_to_irq(gpio) >= 0 && (direction_may_change @@ -744,6 +831,55 @@ done: } EXPORT_SYMBOL_GPL(gpio_export_link); + +/** + * gpio_sysfs_set_active_low - set the polarity of gpio sysfs value + * @gpio: gpio to change + * @value: non-zero to use active low, i.e. inverted values + * + * Set the polarity of /sys/class/gpio/gpioN/value sysfs attribute. + * The GPIO does not have to be exported yet. If poll(2) support has + * been enabled for either rising or falling edge, it will be + * reconfigured to follow the new polarity. + * + * Returns zero on success, else an error. + */ +int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + struct gpio_desc *desc; + struct device *dev = NULL; + int status = -EINVAL; + + if (!gpio_is_valid(gpio)) + goto done; + + mutex_lock(&sysfs_lock); + + desc = &gpio_desc[gpio]; + + if (test_bit(FLAG_EXPORT, &desc->flags)) { + struct device *dev; + + dev = class_find_device(&gpio_class, NULL, desc, match_export); + if (dev == NULL) { + status = -ENODEV; + goto unlock; + } + } + + status = sysfs_set_active_low(desc, dev, value); + +unlock: + mutex_unlock(&sysfs_lock); + +done: + if (status) + pr_debug("%s: gpio%d status %d\n", __func__, gpio, status); + + return status; +} +EXPORT_SYMBOL_GPL(gpio_sysfs_set_active_low); + /** * gpio_unexport - reverse effect of gpio_export() * @gpio: gpio to make unavailable @@ -1094,6 +1230,7 @@ void gpio_free(unsigned gpio) } desc_set_label(desc, NULL); module_put(desc->chip->owner); + clear_bit(FLAG_ACTIVE_LOW, &desc->flags); clear_bit(FLAG_REQUESTED, &desc->flags); } else WARN_ON(extra_checks); diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 204bed37e82..485eeb6c4ef 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -145,6 +145,7 @@ extern int __gpio_to_irq(unsigned gpio); extern int gpio_export(unsigned gpio, bool direction_may_change); extern int gpio_export_link(struct device *dev, const char *name, unsigned gpio); +extern int gpio_sysfs_set_active_low(unsigned gpio, int value); extern void gpio_unexport(unsigned gpio); #endif /* CONFIG_GPIO_SYSFS */ @@ -197,6 +198,11 @@ static inline int gpio_export_link(struct device *dev, const char *name, return -ENOSYS; } +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + return -ENOSYS; +} + static inline void gpio_unexport(unsigned gpio) { } diff --git a/include/linux/gpio.h b/include/linux/gpio.h index 059bd189d35..4e949a5b5b8 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -99,6 +99,12 @@ static inline int gpio_export_link(struct device *dev, const char *name, return -EINVAL; } +static inline int gpio_sysfs_set_active_low(unsigned gpio, int value) +{ + /* GPIO can never have been requested */ + WARN_ON(1); + return -EINVAL; +} static inline void gpio_unexport(unsigned gpio) { -- cgit v1.2.3-70-g09d2