From 4e646495c6153f304fe45b6564ee08d4df935bb1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 27 Aug 2013 15:12:20 +0300 Subject: drm/i915: add basic MIPI DSI output support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This does not include any panel specific sub-encoders yet. v2: Fix fixed mode handling (Daniel) v3: Mostly based on Ville's review comments. - Fix MIPI_HS_TX_TIMEOUT. - DPI_ENABLE only for video mode. - Drop ULPS usage for now, use DEVICE_READY only. - Set MIPI_INIT_COUNT based on txclkesc. Signed-off-by: Jani Nikula Signed-off-by: Shobhit Kumar Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.c | 566 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 566 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi.c (limited to 'drivers/gpu/drm/i915/intel_dsi.c') diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c new file mode 100644 index 00000000000..0dfb28fba47 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -0,0 +1,566 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Author: Jani Nikula + */ + +#include +#include +#include +#include +#include +#include "i915_drv.h" +#include "intel_drv.h" +#include "intel_dsi.h" +#include "intel_dsi_cmd.h" + +/* the sub-encoders aka panel drivers */ +static const struct intel_dsi_device intel_dsi_devices[] = { +}; + +static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) +{ + return container_of(intel_attached_encoder(connector), + struct intel_dsi, base); +} + +static inline bool is_vid_mode(struct intel_dsi *intel_dsi) +{ + return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE; +} + +static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) +{ + return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE; +} + +static void intel_dsi_hot_plug(struct intel_encoder *encoder) +{ + DRM_DEBUG_KMS("\n"); +} + +static bool intel_dsi_compute_config(struct intel_encoder *encoder, + struct intel_crtc_config *config) +{ + struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, + base); + struct intel_connector *intel_connector = intel_dsi->attached_connector; + struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; + struct drm_display_mode *adjusted_mode = &config->adjusted_mode; + struct drm_display_mode *mode = &config->requested_mode; + + DRM_DEBUG_KMS("\n"); + + if (fixed_mode) + intel_fixed_panel_mode(fixed_mode, adjusted_mode); + + if (intel_dsi->dev.dev_ops->mode_fixup) + return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, + mode, adjusted_mode); + + return true; +} + +static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) +{ + DRM_DEBUG_KMS("\n"); +} + +static void intel_dsi_pre_enable(struct intel_encoder *encoder) +{ + DRM_DEBUG_KMS("\n"); +} + +static void intel_dsi_enable(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + int pipe = intel_crtc->pipe; + u32 temp; + + DRM_DEBUG_KMS("\n"); + + temp = I915_READ(MIPI_DEVICE_READY(pipe)); + if ((temp & DEVICE_READY) == 0) { + temp &= ~ULPS_STATE_MASK; + I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY); + } else if (temp & ULPS_STATE_MASK) { + temp &= ~ULPS_STATE_MASK; + I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT); + /* + * We need to ensure that there is a minimum of 1 ms time + * available before clearing the UPLS exit state. + */ + msleep(2); + I915_WRITE(MIPI_DEVICE_READY(pipe), temp); + } + + if (is_cmd_mode(intel_dsi)) + I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); + + if (is_vid_mode(intel_dsi)) { + msleep(20); /* XXX */ + dpi_send_cmd(intel_dsi, TURN_ON); + msleep(100); + + /* assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(pipe)); + I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(pipe)); + } + + intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); +} + +static void intel_dsi_disable(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + int pipe = intel_crtc->pipe; + u32 temp; + + DRM_DEBUG_KMS("\n"); + + intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); + + if (is_vid_mode(intel_dsi)) { + dpi_send_cmd(intel_dsi, SHUTDOWN); + msleep(10); + + /* de-assert ip_tg_enable signal */ + temp = I915_READ(MIPI_PORT_CTRL(pipe)); + I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); + POSTING_READ(MIPI_PORT_CTRL(pipe)); + + msleep(2); + } + + temp = I915_READ(MIPI_DEVICE_READY(pipe)); + if (temp & DEVICE_READY) { + temp &= ~DEVICE_READY; + temp &= ~ULPS_STATE_MASK; + I915_WRITE(MIPI_DEVICE_READY(pipe), temp); + } +} + +static void intel_dsi_post_disable(struct intel_encoder *encoder) +{ + DRM_DEBUG_KMS("\n"); +} + +static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, + enum pipe *pipe) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + u32 port, func; + enum pipe p; + + DRM_DEBUG_KMS("\n"); + + /* XXX: this only works for one DSI output */ + for (p = PIPE_A; p <= PIPE_B; p++) { + port = I915_READ(MIPI_PORT_CTRL(p)); + func = I915_READ(MIPI_DSI_FUNC_PRG(p)); + + if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { + if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { + *pipe = p; + return true; + } + } + } + + return false; +} + +static void intel_dsi_get_config(struct intel_encoder *encoder, + struct intel_crtc_config *pipe_config) +{ + DRM_DEBUG_KMS("\n"); + + /* XXX: read flags, set to adjusted_mode */ +} + +static int intel_dsi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; + struct intel_dsi *intel_dsi = intel_attached_dsi(connector); + + DRM_DEBUG_KMS("\n"); + + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { + DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); + return MODE_NO_DBLESCAN; + } + + if (fixed_mode) { + if (mode->hdisplay > fixed_mode->hdisplay) + return MODE_PANEL; + if (mode->vdisplay > fixed_mode->vdisplay) + return MODE_PANEL; + } + + return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); +} + +/* return txclkesc cycles in terms of divider and duration in us */ +static u16 txclkesc(u32 divider, unsigned int us) +{ + switch (divider) { + case ESCAPE_CLOCK_DIVIDER_1: + default: + return 20 * us; + case ESCAPE_CLOCK_DIVIDER_2: + return 10 * us; + case ESCAPE_CLOCK_DIVIDER_4: + return 5 * us; + } +} + +/* return pixels in terms of txbyteclkhs */ +static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) +{ + return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); +} + +static void set_dsi_timings(struct drm_encoder *encoder, + const struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + int pipe = intel_crtc->pipe; + unsigned int bpp = intel_crtc->config.pipe_bpp; + unsigned int lane_count = intel_dsi->lane_count; + + u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; + + hactive = mode->hdisplay; + hfp = mode->hsync_start - mode->hdisplay; + hsync = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsync = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + /* horizontal values are in terms of high speed byte clock */ + hactive = txbyteclkhs(hactive, bpp, lane_count); + hfp = txbyteclkhs(hfp, bpp, lane_count); + hsync = txbyteclkhs(hsync, bpp, lane_count); + hbp = txbyteclkhs(hbp, bpp, lane_count); + + I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); + I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); + + /* meaningful for video mode non-burst sync pulse mode only, can be zero + * for non-burst sync events and burst modes */ + I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); + I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); + + /* vertical values are in terms of lines */ + I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); + I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); + I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); +} + +static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) +{ + struct drm_encoder *encoder = &intel_encoder->base; + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + struct drm_display_mode *adjusted_mode = + &intel_crtc->config.adjusted_mode; + int pipe = intel_crtc->pipe; + unsigned int bpp = intel_crtc->config.pipe_bpp; + u32 val, tmp; + + DRM_DEBUG_KMS("pipe %d\n", pipe); + + /* escape clock divider, 20MHz, shared for A and C. device ready must be + * off when doing this! txclkesc? */ + tmp = I915_READ(MIPI_CTRL(0)); + tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; + I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); + + /* read request priority is per pipe */ + tmp = I915_READ(MIPI_CTRL(pipe)); + tmp &= ~READ_REQUEST_PRIORITY_MASK; + I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); + + /* XXX: why here, why like this? handling in irq handler?! */ + I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); + I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); + + I915_WRITE(MIPI_DPHY_PARAM(pipe), + 0x3c << EXIT_ZERO_COUNT_SHIFT | + 0x1f << TRAIL_COUNT_SHIFT | + 0xc5 << CLK_ZERO_COUNT_SHIFT | + 0x1f << PREPARE_COUNT_SHIFT); + + I915_WRITE(MIPI_DPI_RESOLUTION(pipe), + adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | + adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); + + set_dsi_timings(encoder, adjusted_mode); + + val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; + if (is_cmd_mode(intel_dsi)) { + val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; + val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ + } else { + val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; + + /* XXX: cross-check bpp vs. pixel format? */ + val |= intel_dsi->pixel_format; + } + I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); + + /* timeouts for recovery. one frame IIUC. if counter expires, EOT and + * stop state. */ + + /* + * In burst mode, value greater than one DPI line Time in byte clock + * (txbyteclkhs) To timeout this timer 1+ of the above said value is + * recommended. + * + * In non-burst mode, Value greater than one DPI frame time in byte + * clock(txbyteclkhs) To timeout this timer 1+ of the above said value + * is recommended. + * + * In DBI only mode, value greater than one DBI frame time in byte + * clock(txbyteclkhs) To timeout this timer 1+ of the above said value + * is recommended. + */ + + if (is_vid_mode(intel_dsi) && + intel_dsi->video_mode_format == VIDEO_MODE_BURST) { + I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + txbyteclkhs(adjusted_mode->htotal, bpp, + intel_dsi->lane_count) + 1); + } else { + I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), + txbyteclkhs(adjusted_mode->vtotal * + adjusted_mode->htotal, + bpp, intel_dsi->lane_count) + 1); + } + I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */ + I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */ + I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */ + + /* dphy stuff */ + + /* in terms of low power clock */ + I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100)); + + /* recovery disables */ + I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable); + + /* in terms of txbyteclkhs. actual high to low switch + + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. + * + * XXX: write MIPI_STOP_STATE_STALL? + */ + I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46); + + /* XXX: low power clock equivalence in terms of byte clock. the number + * of byte clocks occupied in one low power clock. based on txbyteclkhs + * and txclkesc. txclkesc time / txbyteclk time * (105 + + * MIPI_STOP_STATE_STALL) / 105.??? + */ + I915_WRITE(MIPI_LP_BYTECLK(pipe), 4); + + /* the bw essential for transmitting 16 long packets containing 252 + * bytes meant for dcs write memory command is programmed in this + * register in terms of byte clocks. based on dsi transfer rate and the + * number of lanes configured the time taken to transmit 16 long packets + * in a dsi stream varies. */ + I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820); + + I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), + 0xa << LP_HS_SSW_CNT_SHIFT | + 0x14 << HS_LP_PWR_SW_CNT_SHIFT); + + if (is_vid_mode(intel_dsi)) + I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), + intel_dsi->video_mode_format); +} + +static enum drm_connector_status +intel_dsi_detect(struct drm_connector *connector, bool force) +{ + struct intel_dsi *intel_dsi = intel_attached_dsi(connector); + DRM_DEBUG_KMS("\n"); + return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); +} + +static int intel_dsi_get_modes(struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + struct drm_display_mode *mode; + + DRM_DEBUG_KMS("\n"); + + if (!intel_connector->panel.fixed_mode) { + DRM_DEBUG_KMS("no fixed mode\n"); + return 0; + } + + mode = drm_mode_duplicate(connector->dev, + intel_connector->panel.fixed_mode); + if (!mode) { + DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); + return 0; + } + + drm_mode_probed_add(connector, mode); + return 1; +} + +static void intel_dsi_destroy(struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + + DRM_DEBUG_KMS("\n"); + intel_panel_fini(&intel_connector->panel); + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + kfree(connector); +} + +static const struct drm_encoder_funcs intel_dsi_funcs = { + .destroy = intel_encoder_destroy, +}; + +static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { + .get_modes = intel_dsi_get_modes, + .mode_valid = intel_dsi_mode_valid, + .best_encoder = intel_best_encoder, +}; + +static const struct drm_connector_funcs intel_dsi_connector_funcs = { + .dpms = intel_connector_dpms, + .detect = intel_dsi_detect, + .destroy = intel_dsi_destroy, + .fill_modes = drm_helper_probe_single_connector_modes, +}; + +bool intel_dsi_init(struct drm_device *dev) +{ + struct intel_dsi *intel_dsi; + struct intel_encoder *intel_encoder; + struct drm_encoder *encoder; + struct intel_connector *intel_connector; + struct drm_connector *connector; + struct drm_display_mode *fixed_mode = NULL; + const struct intel_dsi_device *dsi; + unsigned int i; + + DRM_DEBUG_KMS("\n"); + + intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); + if (!intel_dsi) + return false; + + intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); + if (!intel_connector) { + kfree(intel_dsi); + return false; + } + + intel_encoder = &intel_dsi->base; + encoder = &intel_encoder->base; + intel_dsi->attached_connector = intel_connector; + + connector = &intel_connector->base; + + drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); + + /* XXX: very likely not all of these are needed */ + intel_encoder->hot_plug = intel_dsi_hot_plug; + intel_encoder->compute_config = intel_dsi_compute_config; + intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; + intel_encoder->pre_enable = intel_dsi_pre_enable; + intel_encoder->enable = intel_dsi_enable; + intel_encoder->mode_set = intel_dsi_mode_set; + intel_encoder->disable = intel_dsi_disable; + intel_encoder->post_disable = intel_dsi_post_disable; + intel_encoder->get_hw_state = intel_dsi_get_hw_state; + intel_encoder->get_config = intel_dsi_get_config; + + intel_connector->get_hw_state = intel_connector_get_hw_state; + + for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { + dsi = &intel_dsi_devices[i]; + intel_dsi->dev = *dsi; + + if (dsi->dev_ops->init(&intel_dsi->dev)) + break; + } + + if (i == ARRAY_SIZE(intel_dsi_devices)) { + DRM_DEBUG_KMS("no device found\n"); + goto err; + } + + intel_encoder->type = INTEL_OUTPUT_DSI; + intel_encoder->crtc_mask = (1 << 0); /* XXX */ + + intel_encoder->cloneable = false; + drm_connector_init(dev, connector, &intel_dsi_connector_funcs, + DRM_MODE_CONNECTOR_DSI); + + drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); + + connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + + intel_connector_attach_encoder(intel_connector, intel_encoder); + + drm_sysfs_connector_add(connector); + + fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); + if (!fixed_mode) { + DRM_DEBUG_KMS("no fixed mode\n"); + goto err; + } + + fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; + intel_panel_init(&intel_connector->panel, fixed_mode); + + return true; + +err: + drm_encoder_cleanup(&intel_encoder->base); + kfree(intel_dsi); + kfree(intel_connector); + + return false; +} -- cgit v1.2.3-70-g09d2 From be4fc046bed35f7a50c8d5751abf555933d864ae Mon Sep 17 00:00:00 2001 From: ymohanma Date: Tue, 27 Aug 2013 23:40:56 +0300 Subject: drm/i915: add VLV DSI PLL Calculations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: - Grab dpio_lock mutex in vlv_enable_dsi_pll(). - Add and call vlv_disable_dsi_pll(). v3: Mostly based on Ville's review comments. - Only pipe A has DSI PLL lock bit. - Add more of CCK REG bit definitions for DSI PLL. - Make tables static. - Move clock gating out of the clock calculation functions. - DSI PLL LDO power gating. - Put alternative MNP from table calc behind #ifdef. v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville). Signed-off-by: ymohanma Signed-off-by: Shobhit Kumar Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/i915_reg.h | 32 ++++ drivers/gpu/drm/i915/intel_dsi.c | 7 + drivers/gpu/drm/i915/intel_dsi.h | 3 + drivers/gpu/drm/i915/intel_dsi_pll.c | 317 +++++++++++++++++++++++++++++++++++ 5 files changed, 360 insertions(+) create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c (limited to 'drivers/gpu/drm/i915/intel_dsi.c') diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5864c5ba44b..65e60d26891 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -23,6 +23,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ intel_lvds.o \ intel_dsi.o \ intel_dsi_cmd.o \ + intel_dsi_pll.o \ intel_bios.o \ intel_ddi.o \ intel_dp.o \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b26cf9b5b1e..f626a16a14f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -376,6 +376,38 @@ #define FB_FMAX_VMIN_FREQ_LO_SHIFT 27 #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 +/* vlv2 north clock has */ +#define CCK_REG_DSI_PLL_FUSE 0x44 +#define CCK_REG_DSI_PLL_CONTROL 0x48 +#define DSI_PLL_VCO_EN (1 << 31) +#define DSI_PLL_LDO_GATE (1 << 30) +#define DSI_PLL_P1_POST_DIV_SHIFT 17 +#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17) +#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13) +#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12) +#define DSI_PLL_MUX_MASK (3 << 9) +#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10) +#define DSI_PLL_MUX_DSI0_CCK (1 << 10) +#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9) +#define DSI_PLL_MUX_DSI1_CCK (1 << 9) +#define DSI_PLL_CLK_GATE_MASK (0xf << 5) +#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8) +#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7) +#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6) +#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5) +#define DSI_PLL_LOCK (1 << 0) +#define CCK_REG_DSI_PLL_DIVIDER 0x4c +#define DSI_PLL_LFSR (1 << 31) +#define DSI_PLL_FRACTION_EN (1 << 30) +#define DSI_PLL_FRAC_COUNTER_SHIFT 27 +#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27) +#define DSI_PLL_USYNC_CNT_SHIFT 18 +#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18) +#define DSI_PLL_N1_DIV_SHIFT 16 +#define DSI_PLL_N1_DIV_MASK (3 << 16) +#define DSI_PLL_M1_DIV_SHIFT 0 +#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) + /* * DPIO - a special bus for various display related registers to hide behind * diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 0dfb28fba47..263c8d2603b 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) { DRM_DEBUG_KMS("\n"); + + vlv_enable_dsi_pll(encoder); } static void intel_dsi_pre_enable(struct intel_encoder *encoder) @@ -167,6 +169,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder) static void intel_dsi_post_disable(struct intel_encoder *encoder) { DRM_DEBUG_KMS("\n"); + + vlv_disable_dsi_pll(encoder); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, @@ -303,6 +307,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) DRM_DEBUG_KMS("pipe %d\n", pipe); + /* Update the DSI PLL */ + vlv_enable_dsi_pll(intel_encoder); + /* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp = I915_READ(MIPI_CTRL(0)); diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index f308269cd87..c7765f33d52 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -96,4 +96,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) return container_of(encoder, struct intel_dsi, base.base); } +extern void vlv_enable_dsi_pll(struct intel_encoder *encoder); +extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); + #endif /* _INTEL_DSI_H */ diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c new file mode 100644 index 00000000000..582f626a99f --- /dev/null +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -0,0 +1,317 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Shobhit Kumar + * Yogesh Mohan Marimuthu + */ + +#include +#include "intel_drv.h" +#include "i915_drv.h" +#include "intel_dsi.h" + +#define DSI_HSS_PACKET_SIZE 4 +#define DSI_HSE_PACKET_SIZE 4 +#define DSI_HSA_PACKET_EXTRA_SIZE 6 +#define DSI_HBP_PACKET_EXTRA_SIZE 6 +#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 +#define DSI_HFP_PACKET_EXTRA_SIZE 6 +#define DSI_EOTP_PACKET_SIZE 4 + +struct dsi_mnp { + u32 dsi_pll_ctrl; + u32 dsi_pll_div; +}; + +static const u32 lfsr_converts[] = { + 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ + 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ + 106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */ + 71, 35 /* 91 - 92 */ +}; + +static u32 dsi_rr_formula(struct drm_display_mode *mode, + int pixel_format, int video_mode_format, + int lane_count, bool eotp) +{ + u32 bpp; + u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; + u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; + u32 bytes_per_line, bytes_per_frame; + u32 num_frames; + u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; + u32 dsi_bit_clock_hz; + u32 dsi_clk; + + switch (pixel_format) { + default: + case VID_MODE_FORMAT_RGB888: + case VID_MODE_FORMAT_RGB666_LOOSE: + bpp = 24; + break; + case VID_MODE_FORMAT_RGB666: + bpp = 18; + break; + case VID_MODE_FORMAT_RGB565: + bpp = 16; + break; + } + + hactive = mode->hdisplay; + vactive = mode->vdisplay; + hfp = mode->hsync_start - mode->hdisplay; + hsync = mode->hsync_end - mode->hsync_start; + hbp = mode->htotal - mode->hsync_end; + + vfp = mode->vsync_start - mode->vdisplay; + vsync = mode->vsync_end - mode->vsync_start; + vbp = mode->vtotal - mode->vsync_end; + + hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); + hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); + hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); + hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); + + bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + + DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + + hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + + hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + + hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; + + /* + * XXX: Need to accurately calculate LP to HS transition timeout and add + * it to bytes_per_line/bytes_per_frame. + */ + + if (eotp && video_mode_format == VIDEO_MODE_BURST) + bytes_per_line += DSI_EOTP_PACKET_SIZE; + + bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + + vactive * bytes_per_line + vfp * bytes_per_line; + + if (eotp && + (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || + video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) + bytes_per_frame += DSI_EOTP_PACKET_SIZE; + + num_frames = drm_mode_vrefresh(mode); + bytes_per_x_frames = num_frames * bytes_per_frame; + + bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; + + /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ + dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; + dsi_clk = dsi_bit_clock_hz / (1000 * 1000); + + if (eotp && video_mode_format == VIDEO_MODE_BURST) + dsi_clk *= 2; + + return dsi_clk; +} + +#ifdef MNP_FROM_TABLE + +struct dsi_clock_table { + u32 freq; + u8 m; + u8 p; +}; + +static const struct dsi_clock_table dsi_clk_tbl[] = { + {300, 72, 6}, {313, 75, 6}, {323, 78, 6}, {333, 80, 6}, + {343, 82, 6}, {353, 85, 6}, {363, 87, 6}, {373, 90, 6}, + {383, 92, 6}, {390, 78, 5}, {393, 79, 5}, {400, 80, 5}, + {401, 80, 5}, {402, 80, 5}, {403, 81, 5}, {404, 81, 5}, + {405, 81, 5}, {406, 81, 5}, {407, 81, 5}, {408, 82, 5}, + {409, 82, 5}, {410, 82, 5}, {411, 82, 5}, {412, 82, 5}, + {413, 83, 5}, {414, 83, 5}, {415, 83, 5}, {416, 83, 5}, + {417, 83, 5}, {418, 84, 5}, {419, 84, 5}, {420, 84, 5}, + {430, 86, 5}, {440, 88, 5}, {450, 90, 5}, {460, 92, 5}, + {470, 75, 4}, {480, 77, 4}, {490, 78, 4}, {500, 80, 4}, + {510, 82, 4}, {520, 83, 4}, {530, 85, 4}, {540, 86, 4}, + {550, 88, 4}, {560, 90, 4}, {570, 91, 4}, {580, 70, 3}, + {590, 71, 3}, {600, 72, 3}, {610, 73, 3}, {620, 74, 3}, + {630, 76, 3}, {640, 77, 3}, {650, 78, 3}, {660, 79, 3}, + {670, 80, 3}, {680, 82, 3}, {690, 83, 3}, {700, 84, 3}, + {710, 85, 3}, {720, 86, 3}, {730, 88, 3}, {740, 89, 3}, + {750, 90, 3}, {760, 91, 3}, {770, 92, 3}, {780, 62, 2}, + {790, 63, 2}, {800, 64, 2}, {880, 70, 2}, {900, 72, 2}, + {1000, 80, 2}, /* dsi clock frequency in Mhz*/ +}; + +static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) +{ + unsigned int i; + u8 m; + u8 n; + u8 p; + u32 m_seed; + + if (dsi_clk < 300 || dsi_clk > 1000) + return -ECHRNG; + + for (i = 0; i <= ARRAY_SIZE(dsi_clk_tbl); i++) { + if (dsi_clk_tbl[i].freq > dsi_clk) + break; + } + + m = dsi_clk_tbl[i].m; + p = dsi_clk_tbl[i].p; + m_seed = lfsr_converts[m - 62]; + n = 1; + dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + p - 2); + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | + m_seed << DSI_PLL_M1_DIV_SHIFT; + + return 0; +} + +#else + +static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) +{ + u32 m, n, p; + u32 ref_clk; + u32 error; + u32 tmp_error; + u32 target_dsi_clk; + u32 calc_dsi_clk; + u32 calc_m; + u32 calc_p; + u32 m_seed; + + if (dsi_clk < 300 || dsi_clk > 1150) { + DRM_ERROR("DSI CLK Out of Range\n"); + return -ECHRNG; + } + + ref_clk = 25000; + target_dsi_clk = dsi_clk * 1000; + error = 0xFFFFFFFF; + calc_m = 0; + calc_p = 0; + + for (m = 62; m <= 92; m++) { + for (p = 2; p <= 6; p++) { + + calc_dsi_clk = (m * ref_clk) / p; + if (calc_dsi_clk >= target_dsi_clk) { + tmp_error = calc_dsi_clk - target_dsi_clk; + if (tmp_error < error) { + error = tmp_error; + calc_m = m; + calc_p = p; + } + } + } + } + + m_seed = lfsr_converts[calc_m - 62]; + n = 1; + dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | + m_seed << DSI_PLL_M1_DIV_SHIFT; + + return 0; +} + +#endif + +/* + * XXX: The muxing and gating is hard coded for now. Need to add support for + * sharing PLLs with two DSI outputs. + */ +static void vlv_configure_dsi_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); + struct drm_display_mode *mode = &intel_crtc->config.requested_mode; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + int ret; + struct dsi_mnp dsi_mnp; + u32 dsi_clk; + + dsi_clk = dsi_rr_formula(mode, intel_dsi->pixel_format, + intel_dsi->video_mode_format, + intel_dsi->lane_count, !intel_dsi->eot_disable); + + ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); + if (ret) { + DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); + return; + } + + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; + + DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", + dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); + + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); +} + +void vlv_enable_dsi_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + u32 tmp; + + DRM_DEBUG_KMS("\n"); + + mutex_lock(&dev_priv->dpio_lock); + + vlv_configure_dsi_pll(encoder); + + /* wait at least 0.5 us after ungating before enabling VCO */ + usleep_range(1, 10); + + tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); + tmp |= DSI_PLL_VCO_EN; + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); + + mutex_unlock(&dev_priv->dpio_lock); + + if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) { + DRM_ERROR("DSI PLL lock failed\n"); + return; + } + + DRM_DEBUG_KMS("DSI PLL locked\n"); +} + +void vlv_disable_dsi_pll(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + u32 tmp; + + DRM_DEBUG_KMS("\n"); + + mutex_lock(&dev_priv->dpio_lock); + + tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); + tmp &= ~DSI_PLL_VCO_EN; + tmp |= DSI_PLL_LDO_GATE; + vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); + + mutex_unlock(&dev_priv->dpio_lock); +} -- cgit v1.2.3-70-g09d2 From 4ce8c9a720c566a4ce7b782ddd5df90d66f0ba85 Mon Sep 17 00:00:00 2001 From: Shobhit Kumar Date: Tue, 27 Aug 2013 15:12:24 +0300 Subject: drm/i915: Band Gap WA Note: No one seems to have docs for this, so this patch here is just unreviewed black magic :( Signed-off-by: Shobhit Kumar Signed-off-by: ymohanma Signed-off-by: Jani Nikula [danvet: Add note about the doc situation.] Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dsi.c | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'drivers/gpu/drm/i915/intel_dsi.c') diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 263c8d2603b..674fd4989b4 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -37,6 +37,51 @@ static const struct intel_dsi_device intel_dsi_devices[] = { }; + +static void vlv_cck_modify(struct drm_i915_private *dev_priv, u32 reg, u32 val, + u32 mask) +{ + u32 tmp = vlv_cck_read(dev_priv, reg); + tmp &= ~mask; + tmp |= val; + vlv_cck_write(dev_priv, reg, tmp); +} + +static void band_gap_wa(struct drm_i915_private *dev_priv) +{ + mutex_lock(&dev_priv->dpio_lock); + + /* Enable bandgap fix in GOP driver */ + vlv_cck_modify(dev_priv, 0x6D, 0x00010000, 0x00030000); + msleep(20); + vlv_cck_modify(dev_priv, 0x6E, 0x00010000, 0x00030000); + msleep(20); + vlv_cck_modify(dev_priv, 0x6F, 0x00010000, 0x00030000); + msleep(20); + vlv_cck_modify(dev_priv, 0x00, 0x00008000, 0x00008000); + msleep(20); + vlv_cck_modify(dev_priv, 0x00, 0x00000000, 0x00008000); + msleep(20); + + /* Turn Display Trunk on */ + vlv_cck_modify(dev_priv, 0x6B, 0x00020000, 0x00030000); + msleep(20); + + vlv_cck_modify(dev_priv, 0x6C, 0x00020000, 0x00030000); + msleep(20); + + vlv_cck_modify(dev_priv, 0x6D, 0x00020000, 0x00030000); + msleep(20); + vlv_cck_modify(dev_priv, 0x6E, 0x00020000, 0x00030000); + msleep(20); + vlv_cck_modify(dev_priv, 0x6F, 0x00020000, 0x00030000); + + mutex_unlock(&dev_priv->dpio_lock); + + /* Need huge delay, otherwise clock is not stable */ + msleep(100); +} + static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) { return container_of(intel_attached_encoder(connector), @@ -310,6 +355,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) /* Update the DSI PLL */ vlv_enable_dsi_pll(intel_encoder); + /* XXX: Location of the call */ + band_gap_wa(dev_priv); + /* escape clock divider, 20MHz, shared for A and C. device ready must be * off when doing this! txclkesc? */ tmp = I915_READ(MIPI_CTRL(0)); -- cgit v1.2.3-70-g09d2 From d9255d57147e1dbcebdf6670409c2fa0ac3609e6 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Thu, 26 Sep 2013 20:05:59 -0300 Subject: drm/i915: destroy connector sysfs files earlier For some reason, every single time I try to run module_reload something tries to read the connector sysfs files. This happens after we destroy the encoders and before we destroy the connectors, so when the sysfs read triggers the connector detect() function, intel_conector->encoder points to memory that was already freed. The bad backtrace is just: [] dump_stack+0x54/0x74 [] intel_dp_detect+0x1e/0x4b0 [i915] [] status_show+0x3d/0x80 [drm] [] dev_attr_show+0x20/0x60 [] ? sysfs_read_file+0x80/0x1b0 [] sysfs_read_file+0xa9/0x1b0 [] vfs_read+0x9e/0x170 [] SyS_read+0x4c/0xa0 [] system_call_fastpath+0x16/0x1b But if you add tons of memory checking debug options to your Kernel you'll also see: - general protection fault: 0000 - BUG kmalloc-4096 (Tainted: G D W ): Poison overwritten - INFO: Allocated in intel_ddi_init+0x65/0x270 [i915] - INFO: Freed in intel_dp_encoder_destroy+0x69/0xb0 [i915] Among a bunch of other error messages. So this commit just destroys the sysfs files before both the encoder and connectors are freed. Signed-off-by: Paulo Zanoni Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_crt.c | 1 - drivers/gpu/drm/i915/intel_display.c | 5 +++++ drivers/gpu/drm/i915/intel_dp.c | 1 - drivers/gpu/drm/i915/intel_dsi.c | 1 - drivers/gpu/drm/i915/intel_dvo.c | 1 - drivers/gpu/drm/i915/intel_hdmi.c | 1 - drivers/gpu/drm/i915/intel_lvds.c | 1 - drivers/gpu/drm/i915/intel_sdvo.c | 7 +++++-- drivers/gpu/drm/i915/intel_tv.c | 1 - 9 files changed, 10 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.c') diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 0263629332d..942b9acb0d8 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -677,7 +677,6 @@ intel_crt_detect(struct drm_connector *connector, bool force) static void intel_crt_destroy(struct drm_connector *connector) { - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 76870f0ffa7..29b93877981 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10727,6 +10727,7 @@ void intel_modeset_cleanup(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_crtc *crtc; + struct drm_connector *connector; /* * Interrupts and polling as the first thing to avoid creating havoc. @@ -10769,6 +10770,10 @@ void intel_modeset_cleanup(struct drm_device *dev) /* destroy backlight, if any, before the connectors */ intel_panel_destroy_backlight(dev); + /* destroy the sysfs files before encoders/connectors */ + list_for_each_entry(connector, &dev->mode_config.connector_list, head) + drm_sysfs_connector_remove(connector); + drm_mode_config_cleanup(dev); intel_cleanup_overlay(dev); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2d790d01972..5614365465c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3189,7 +3189,6 @@ intel_dp_connector_destroy(struct drm_connector *connector) if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) intel_panel_fini(&intel_connector->panel); - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 674fd4989b4..9a2fdd2a7e3 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -504,7 +504,6 @@ static void intel_dsi_destroy(struct drm_connector *connector) DRM_DEBUG_KMS("\n"); intel_panel_fini(&intel_connector->panel); - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c index 91287d1d305..1b64145c669 100644 --- a/drivers/gpu/drm/i915/intel_dvo.c +++ b/drivers/gpu/drm/i915/intel_dvo.c @@ -367,7 +367,6 @@ static int intel_dvo_get_modes(struct drm_connector *connector) static void intel_dvo_destroy(struct drm_connector *connector) { - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 6004f9c549a..4f4d346db8f 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1181,7 +1181,6 @@ static void intel_hdmi_post_disable(struct intel_encoder *encoder) static void intel_hdmi_destroy(struct drm_connector *connector) { - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index fb3f8efcc6e..ae0c843dd26 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -474,7 +474,6 @@ static void intel_lvds_destroy(struct drm_connector *connector) intel_panel_fini(&lvds_connector->base.panel); - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 5e59d64cfd9..a583e8f718a 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -2009,7 +2009,6 @@ static void intel_sdvo_destroy(struct drm_connector *connector) intel_sdvo_connector->tv_format); intel_sdvo_destroy_enhance_property(connector); - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(intel_sdvo_connector); } @@ -2482,6 +2481,7 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) return true; err: + drm_sysfs_connector_remove(connector); intel_sdvo_destroy(connector); return false; } @@ -2553,6 +2553,7 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) return true; err: + drm_sysfs_connector_remove(connector); intel_sdvo_destroy(connector); return false; } @@ -2624,8 +2625,10 @@ static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { - if (intel_attached_encoder(connector) == &intel_sdvo->base) + if (intel_attached_encoder(connector) == &intel_sdvo->base) { + drm_sysfs_connector_remove(connector); intel_sdvo_destroy(connector); + } } } diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 75925a1ab35..92895f92a73 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1433,7 +1433,6 @@ intel_tv_get_modes(struct drm_connector *connector) static void intel_tv_destroy(struct drm_connector *connector) { - drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); } -- cgit v1.2.3-70-g09d2 From 6f2bcceb27b6120af6b76a865a72eafa50323d41 Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Wed, 16 Oct 2013 12:29:54 +0100 Subject: drm/i915: Use pipe_name() instead of the pipe number MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Yet other direct usages of the pipe number instead of pipe_name(). We've been tracking them lately but managed to miss these last ones. v2: Catch them all! (Ville) Reviewed-by: Ville Syrjälä (v1) Signed-off-by: Damien Lespiau Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/i915/intel_dsi.c') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 53ad5cb9e80..d3d5adc4379 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10762,11 +10762,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) } encoder->connectors_active = false; - DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", + DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", encoder->base.base.id, drm_get_encoder_name(&encoder->base), encoder->base.crtc ? "enabled" : "disabled", - pipe); + pipe_name(pipe)); } list_for_each_entry(connector, &dev->mode_config.connector_list, diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 9a2fdd2a7e3..d257b093ca6 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -350,7 +350,7 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder) unsigned int bpp = intel_crtc->config.pipe_bpp; u32 val, tmp; - DRM_DEBUG_KMS("pipe %d\n", pipe); + DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); /* Update the DSI PLL */ vlv_enable_dsi_pll(intel_encoder); diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 1f2996031ad..de151861482 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -574,7 +574,7 @@ void intel_panel_enable_backlight(struct drm_device *dev, intel_pipe_to_cpu_transcoder(dev_priv, pipe); unsigned long flags; - DRM_DEBUG_KMS("pipe=%d\n", pipe); + DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); spin_lock_irqsave(&dev_priv->backlight.lock, flags); -- cgit v1.2.3-70-g09d2