From b3d254955fb5797232ec329b136c363aa4fdaa05 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Wed, 24 Jun 2009 23:09:15 -0700 Subject: drm/i915: Adjust DisplayPort clocks to use 96MHz reference For some reason, the DP clocks were based off a 100MHz reference instead of the standard 96MHz reference. This caused some DP monitors to fail to lock to the signal. Signed-off-by: Keith Packard Signed-off-by: Eric Anholt --- drivers/gpu/drm/i915/intel_display.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/i915') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 59de4951b6e..508838ee31e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -816,24 +816,21 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, { intel_clock_t clock; if (target < 200000) { - clock.dot = 161670; - clock.p = 20; clock.p1 = 2; clock.p2 = 10; - clock.n = 0x01; - clock.m = 97; - clock.m1 = 0x10; - clock.m2 = 0x05; + clock.n = 2; + clock.m1 = 23; + clock.m2 = 8; } else { - clock.dot = 270000; - clock.p = 10; clock.p1 = 1; clock.p2 = 10; - clock.n = 0x02; - clock.m = 108; - clock.m1 = 0x12; - clock.m2 = 0x06; + clock.n = 1; + clock.m1 = 14; + clock.m2 = 2; } + clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); + clock.p = (clock.p1 * clock.p2); + clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; memcpy(best_clock, &clock, sizeof(intel_clock_t)); return true; } -- cgit v1.2.3-70-g09d2