From 7c856522069755ab9d163a24ac332cd3cb35fe30 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 14 Jan 2013 08:28:28 +1000 Subject: drm/nouveau/clk: implement power state and engine clock control in core User control of this has been hard-coded as disabled for now. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/core/subdev/clock/seq.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/core/subdev/clock/seq.h (limited to 'drivers/gpu/drm/nouveau/core/subdev/clock/seq.h') diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h new file mode 100644 index 00000000000..fb33f06ebd5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h @@ -0,0 +1,17 @@ +#ifndef __NVKM_CLK_SEQ_H__ +#define __NVKM_CLK_SEQ_H__ + +#include +#include + +#define clk_init(s,p) hwsq_init(&(s)->base, (p)) +#define clk_exec(s,e) hwsq_exec(&(s)->base, (e)) +#define clk_have(s,r) ((s)->r_##r.addr != 0x000000) +#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) +#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) +#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) +#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) +#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) +#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) + +#endif -- cgit v1.2.3-70-g09d2