From a879e9c34b93ee43f5caa7f94eb17e7af4f6ef50 Mon Sep 17 00:00:00 2001 From: Nikolaus Voss Date: Tue, 8 Nov 2011 11:49:24 +0100 Subject: i2c: at91: remove old polling driver It will get replaced by a superior one. Safe to remove since this one depends on BROKEN anyhow. Signed-off-by: Nikolaus Voss Tested-by: Ludovic Desroches Reviewed-by: Nicolas Ferre [wsa: added commit message] Signed-off-by: Wolfram Sang --- drivers/i2c/busses/Makefile | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/i2c/busses/Makefile') diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index ce3c2be7fb4..4f46873282b 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -28,7 +28,6 @@ obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o # Embedded system I2C/SMBus host controller drivers -obj-$(CONFIG_I2C_AT91) += i2c-at91.o obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o obj-$(CONFIG_I2C_CPM) += i2c-cpm.o -- cgit v1.2.3-70-g09d2 From fac368a040484293006bb488e67972aafcf88ec7 Mon Sep 17 00:00:00 2001 From: Nikolaus Voss Date: Tue, 8 Nov 2011 11:49:46 +0100 Subject: i2c: at91: add new driver This driver has the following properties compared to the old driver: 1. Support for multiple interfaces. 2. Interrupt driven I/O as opposed to polling/busy waiting. 3. Support for _one_ repeated start (Sr) condition, which is enough for most real-world applications including all SMBus transfer types. (The hardware does not support issuing arbitrary Sr conditions on the bus.) testing: SoC: at91sam9g45 - BQ20Z80 battery SMBus client. - on a 2.6.38 kernel with several i2c clients (temp-sensor, audio-codec, touchscreen-controller, w1-bridge, io-expanders) Signed-off-by: Nikolaus Voss Reviewed-by: Felipe Balbi Tested-by: Hubert Feurstein Tested-by: Ludovic Desroches Reviewed-by: Nicolas Ferre [wsa: squashed with the following patches from Ludovic to have some flaws fixed: i2c: at91: use managed resources i2c: at91: add warning about transmission issues for some devices i2c: at91: use an id table for SoC dependent parameters ] Signed-off-by: Ludovic Desroches Signed-off-by: Wolfram Sang --- arch/arm/mach-at91/at91rm9200.c | 2 +- arch/arm/mach-at91/at91rm9200_devices.c | 2 +- arch/arm/mach-at91/at91sam9260.c | 3 +- arch/arm/mach-at91/at91sam9260_devices.c | 8 +- arch/arm/mach-at91/at91sam9261.c | 3 +- arch/arm/mach-at91/at91sam9261_devices.c | 8 +- arch/arm/mach-at91/at91sam9263.c | 2 +- arch/arm/mach-at91/at91sam9263_devices.c | 2 +- arch/arm/mach-at91/at91sam9g45.c | 4 +- arch/arm/mach-at91/at91sam9g45_devices.c | 4 +- arch/arm/mach-at91/at91sam9rl.c | 4 +- arch/arm/mach-at91/at91sam9rl_devices.c | 2 +- drivers/i2c/busses/Kconfig | 17 +- drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-at91.c | 505 +++++++++++++++++++++++++++++++ 15 files changed, 545 insertions(+), 22 deletions(-) create mode 100644 drivers/i2c/busses/i2c-at91.c (limited to 'drivers/i2c/busses/Makefile') diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index f2112f9c180..b4f0565aff6 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -187,7 +187,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index 01fb7325fec..0b972f2e57e 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c @@ -495,7 +495,7 @@ static struct resource twi_resources[] = { }; static struct platform_device at91rm9200_twi_device = { - .name = "at91_i2c", + .name = "i2c-at91rm9200", .id = -1, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 57c79eed5fd..5bd19a44236 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -211,7 +211,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20", &twi_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index bce572a530e..95fc23aab43 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -503,7 +503,6 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9260_twi_device = { - .name = "at91_i2c", .id = -1, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), @@ -511,6 +510,13 @@ static struct platform_device at91sam9260_twi_device = { void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) { + /* IP version is not the same on 9260 and g20 */ + if (cpu_is_at91sam9g20()) { + at91sam9260_twi_device.name = "i2c-at91sam9g20"; + } else { + at91sam9260_twi_device.name = "i2c-at91sam9260"; + } + /* pins used for TWI interface */ at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */ at91_set_multi_drive(AT91_PIN_PA23, 1); diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 71ca1e06a16..8d999eb1a13 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -178,7 +178,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index bc2590d712d..29188ef7422 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c @@ -317,7 +317,6 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9261_twi_device = { - .name = "at91_i2c", .id = -1, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), @@ -325,6 +324,13 @@ static struct platform_device at91sam9261_twi_device = { void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) { + /* IP version is not the same on 9261 and g10 */ + if (cpu_is_at91sam9g10()) { + at91sam9261_twi_device.name = "i2c-at91sam9g10"; + } else { + at91sam9261_twi_device.name = "i2c-at91sam9261"; + } + /* pins used for TWI interface */ at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ at91_set_multi_drive(AT91_PIN_PA7, 1); diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 2a08305b657..e6b595658e7 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -193,7 +193,7 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c", &twi_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 9b6ca734f1a..3f5288ea64b 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -574,7 +574,7 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9263_twi_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9260", .id = -1, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index ddf3d3707c5..858f032e510 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -237,8 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c.0", &twi0_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c.1", &twi1_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 1b47319ca00..ac1b0f8c3b3 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c @@ -653,7 +653,7 @@ static struct resource twi0_resources[] = { }; static struct platform_device at91sam9g45_twi0_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9g10", .id = 0, .resource = twi0_resources, .num_resources = ARRAY_SIZE(twi0_resources), @@ -673,7 +673,7 @@ static struct resource twi1_resources[] = { }; static struct platform_device at91sam9g45_twi1_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9g10", .id = 1, .resource = twi1_resources, .num_resources = ARRAY_SIZE(twi1_resources), diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index bf79c1fd593..72e90841222 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -186,8 +186,8 @@ static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c.0", &twi0_clk), - CLKDEV_CON_DEV_ID(NULL, "at91_i2c.1", &twi1_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index b3d365dadef..0794954953e 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c @@ -346,7 +346,7 @@ static struct resource twi_resources[] = { }; static struct platform_device at91sam9rl_twi_device = { - .name = "at91_i2c", + .name = "i2c-at91sam9g20", .id = -1, .resource = twi_resources, .num_resources = ARRAY_SIZE(twi_resources), diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index b4aaa1bd672..da77c37caf1 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -290,18 +290,21 @@ comment "I2C system bus drivers (mostly embedded / system-on-chip)" config I2C_AT91 tristate "Atmel AT91 I2C Two-Wire interface (TWI)" - depends on ARCH_AT91 && EXPERIMENTAL && BROKEN + depends on ARCH_AT91 && EXPERIMENTAL help This supports the use of the I2C interface on Atmel AT91 processors. - This driver is BROKEN because the controller which it uses - will easily trigger RX overrun and TX underrun errors. Using - low I2C clock rates may partially work around those issues - on some systems. Another serious problem is that there is no - documented way to issue repeated START conditions, as needed + A serious problem is that there is no documented way to issue + repeated START conditions for more than two messages, as needed to support combined I2C messages. Use the i2c-gpio driver - unless your system can cope with those limitations. + unless your system can cope with this limitation. + + Caution! at91rm9200, at91sam9261, at91sam9260, at91sam9263 devices + don't have clock stretching in transmission mode. For that reason, + you can encounter underrun issues causing premature stop sendings if + the latency to fill the transmission register is too long. If you + are facing this situation, use the i2c-gpio driver. config I2C_AU1550 tristate "Au1550/Au1200/Au1300 SMBus interface" diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 4f46873282b..ce3c2be7fb4 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_I2C_HYDRA) += i2c-hydra.o obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o # Embedded system I2C/SMBus host controller drivers +obj-$(CONFIG_I2C_AT91) += i2c-at91.o obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o obj-$(CONFIG_I2C_CPM) += i2c-cpm.o diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c new file mode 100644 index 00000000000..78bcad031d6 --- /dev/null +++ b/drivers/i2c/busses/i2c-at91.c @@ -0,0 +1,505 @@ +/* + * i2c Support for Atmel's AT91 Two-Wire Interface (TWI) + * + * Copyright (C) 2011 Weinmann Medical GmbH + * Author: Nikolaus Voss + * + * Evolved from original work by: + * Copyright (C) 2004 Rick Bronson + * Converted to 2.6 by Andrew Victor + * + * Borrowed heavily from original work by: + * Copyright (C) 2000 Philip Edelbrock + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TWI_CLK_HZ 100000 /* max 400 Kbits/s */ +#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ + +/* AT91 TWI register definitions */ +#define AT91_TWI_CR 0x0000 /* Control Register */ +#define AT91_TWI_START 0x0001 /* Send a Start Condition */ +#define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */ +#define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */ +#define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */ +#define AT91_TWI_SWRST 0x0080 /* Software Reset */ + +#define AT91_TWI_MMR 0x0004 /* Master Mode Register */ +#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ +#define AT91_TWI_MREAD 0x1000 /* Master Read Direction */ + +#define AT91_TWI_IADR 0x000c /* Internal Address Register */ + +#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ + +#define AT91_TWI_SR 0x0020 /* Status Register */ +#define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */ +#define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */ +#define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */ + +#define AT91_TWI_OVRE 0x0040 /* Overrun Error */ +#define AT91_TWI_UNRE 0x0080 /* Underrun Error */ +#define AT91_TWI_NACK 0x0100 /* Not Acknowledged */ + +#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ +#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ +#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ +#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ +#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ + +struct at91_twi_pdata { + unsigned clk_max_div; + unsigned clk_offset; + bool has_unre_flag; +}; + +struct at91_twi_dev { + struct device *dev; + void __iomem *base; + struct completion cmd_complete; + struct clk *clk; + u8 *buf; + size_t buf_len; + struct i2c_msg *msg; + int irq; + unsigned transfer_status; + struct i2c_adapter adapter; + unsigned twi_cwgr_reg; + struct at91_twi_pdata *pdata; +}; + +static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) +{ + return readl_relaxed(dev->base + reg); +} + +static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val) +{ + writel_relaxed(val, dev->base + reg); +} + +static void at91_disable_twi_interrupts(struct at91_twi_dev *dev) +{ + at91_twi_write(dev, AT91_TWI_IDR, + AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY); +} + +static void at91_init_twi_bus(struct at91_twi_dev *dev) +{ + at91_disable_twi_interrupts(dev); + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST); + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN); + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS); + at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); +} + +/* + * Calculate symmetric clock as stated in datasheet: + * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) + */ +static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk) +{ + int ckdiv, cdiv, div; + struct at91_twi_pdata *pdata = dev->pdata; + int offset = pdata->clk_offset; + int max_ckdiv = pdata->clk_max_div; + + div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk), + 2 * twi_clk) - offset); + ckdiv = fls(div >> 8); + cdiv = div >> ckdiv; + + if (ckdiv > max_ckdiv) { + dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n", + ckdiv, max_ckdiv); + ckdiv = max_ckdiv; + cdiv = 255; + } + + dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv; + dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); +} + +static void at91_twi_write_next_byte(struct at91_twi_dev *dev) +{ + if (dev->buf_len <= 0) + return; + + at91_twi_write(dev, AT91_TWI_THR, *dev->buf); + + /* send stop when last byte has been written */ + if (--dev->buf_len == 0) + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); + + dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len); + + ++dev->buf; +} + +static void at91_twi_read_next_byte(struct at91_twi_dev *dev) +{ + if (dev->buf_len <= 0) + return; + + *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff; + --dev->buf_len; + + /* handle I2C_SMBUS_BLOCK_DATA */ + if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) { + dev->msg->flags &= ~I2C_M_RECV_LEN; + dev->buf_len += *dev->buf; + dev->msg->len = dev->buf_len + 1; + dev_dbg(dev->dev, "received block length %d\n", dev->buf_len); + } + + /* send stop if second but last byte has been read */ + if (dev->buf_len == 1) + at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP); + + dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len); + + ++dev->buf; +} + +static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) +{ + struct at91_twi_dev *dev = dev_id; + const unsigned status = at91_twi_read(dev, AT91_TWI_SR); + const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR); + + if (!irqstatus) + return IRQ_NONE; + else if (irqstatus & AT91_TWI_RXRDY) + at91_twi_read_next_byte(dev); + else if (irqstatus & AT91_TWI_TXRDY) + at91_twi_write_next_byte(dev); + + /* catch error flags */ + dev->transfer_status |= status; + + if (irqstatus & AT91_TWI_TXCOMP) { + at91_disable_twi_interrupts(dev); + complete(&dev->cmd_complete); + } + + return IRQ_HANDLED; +} + +static int at91_do_twi_transfer(struct at91_twi_dev *dev) +{ + int ret; + bool has_unre_flag = dev->pdata->has_unre_flag; + + dev_dbg(dev->dev, "transfer: %s %d bytes.\n", + (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len); + + INIT_COMPLETION(dev->cmd_complete); + dev->transfer_status = 0; + if (dev->msg->flags & I2C_M_RD) { + unsigned start_flags = AT91_TWI_START; + + if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) { + dev_err(dev->dev, "RXRDY still set!"); + at91_twi_read(dev, AT91_TWI_RHR); + } + + /* if only one byte is to be read, immediately stop transfer */ + if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) + start_flags |= AT91_TWI_STOP; + at91_twi_write(dev, AT91_TWI_CR, start_flags); + at91_twi_write(dev, AT91_TWI_IER, + AT91_TWI_TXCOMP | AT91_TWI_RXRDY); + } else { + at91_twi_write_next_byte(dev); + at91_twi_write(dev, AT91_TWI_IER, + AT91_TWI_TXCOMP | AT91_TWI_TXRDY); + } + + ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, + dev->adapter.timeout); + if (ret == 0) { + dev_err(dev->dev, "controller timed out\n"); + at91_init_twi_bus(dev); + return -ETIMEDOUT; + } + if (dev->transfer_status & AT91_TWI_NACK) { + dev_dbg(dev->dev, "received nack\n"); + return -EREMOTEIO; + } + if (dev->transfer_status & AT91_TWI_OVRE) { + dev_err(dev->dev, "overrun while reading\n"); + return -EIO; + } + if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { + dev_err(dev->dev, "underrun while writing\n"); + return -EIO; + } + dev_dbg(dev->dev, "transfer complete\n"); + + return 0; +} + +static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) +{ + struct at91_twi_dev *dev = i2c_get_adapdata(adap); + int ret; + unsigned int_addr_flag = 0; + struct i2c_msg *m_start = msg; + + dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); + + /* + * The hardware can handle at most two messages concatenated by a + * repeated start via it's internal address feature. + */ + if (num > 2) { + dev_err(dev->dev, + "cannot handle more than two concatenated messages.\n"); + return 0; + } else if (num == 2) { + int internal_address = 0; + int i; + + if (msg->flags & I2C_M_RD) { + dev_err(dev->dev, "first transfer must be write.\n"); + return -EINVAL; + } + if (msg->len > 3) { + dev_err(dev->dev, "first message size must be <= 3.\n"); + return -EINVAL; + } + + /* 1st msg is put into the internal address, start with 2nd */ + m_start = &msg[1]; + for (i = 0; i < msg->len; ++i) { + const unsigned addr = msg->buf[msg->len - 1 - i]; + + internal_address |= addr << (8 * i); + int_addr_flag += AT91_TWI_IADRSZ_1; + } + at91_twi_write(dev, AT91_TWI_IADR, internal_address); + } + + at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag + | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0)); + + dev->buf_len = m_start->len; + dev->buf = m_start->buf; + dev->msg = m_start; + + ret = at91_do_twi_transfer(dev); + + return (ret < 0) ? ret : num; +} + +static u32 at91_twi_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL + | I2C_FUNC_SMBUS_READ_BLOCK_DATA; +} + +static struct i2c_algorithm at91_twi_algorithm = { + .master_xfer = at91_twi_xfer, + .functionality = at91_twi_func, +}; + +static struct at91_twi_pdata at91rm9200_config = { + .clk_max_div = 5, + .clk_offset = 3, + .has_unre_flag = true, +}; + +static struct at91_twi_pdata at91sam9261_config = { + .clk_max_div = 5, + .clk_offset = 4, + .has_unre_flag = false, +}; + +static struct at91_twi_pdata at91sam9260_config = { + .clk_max_div = 7, + .clk_offset = 4, + .has_unre_flag = false, +}; + +static struct at91_twi_pdata at91sam9g20_config = { + .clk_max_div = 7, + .clk_offset = 4, + .has_unre_flag = false, +}; + +static struct at91_twi_pdata at91sam9g10_config = { + .clk_max_div = 7, + .clk_offset = 4, + .has_unre_flag = false, +}; + +static const struct platform_device_id at91_twi_devtypes[] = { + { + .name = "i2c-at91rm9200", + .driver_data = (unsigned long) &at91rm9200_config, + }, { + .name = "i2c-at91sam9261", + .driver_data = (unsigned long) &at91sam9261_config, + }, { + .name = "i2c-at91sam9260", + .driver_data = (unsigned long) &at91sam9260_config, + }, { + .name = "i2c-at91sam9g20", + .driver_data = (unsigned long) &at91sam9g20_config, + }, { + .name = "i2c-at91sam9g10", + .driver_data = (unsigned long) &at91sam9g10_config, + }, { + /* sentinel */ + } +}; + +static int __devinit at91_twi_probe(struct platform_device *pdev) +{ + struct at91_twi_dev *dev; + struct resource *mem; + int rc; + + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) + return -ENOMEM; + init_completion(&dev->cmd_complete); + dev->dev = &pdev->dev; + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) + return -ENODEV; + + dev->pdata = at91_twi_get_driver_data(pdev); + if (!dev->pdata) + return -ENODEV; + + dev->base = devm_request_and_ioremap(&pdev->dev, mem); + if (!dev->base) + return -EBUSY; + + dev->irq = platform_get_irq(pdev, 0); + if (dev->irq < 0) + return dev->irq; + + rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0, + dev_name(dev->dev), dev); + if (rc) { + dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc); + return rc; + } + + platform_set_drvdata(pdev, dev); + + dev->clk = devm_clk_get(dev->dev, NULL); + if (IS_ERR(dev->clk)) { + dev_err(dev->dev, "no clock defined\n"); + return -ENODEV; + } + clk_prepare_enable(dev->clk); + + at91_calc_twi_clock(dev, TWI_CLK_HZ); + at91_init_twi_bus(dev); + + snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91"); + i2c_set_adapdata(&dev->adapter, dev); + dev->adapter.owner = THIS_MODULE; + dev->adapter.class = I2C_CLASS_HWMON; + dev->adapter.algo = &at91_twi_algorithm; + dev->adapter.dev.parent = dev->dev; + dev->adapter.nr = pdev->id; + dev->adapter.timeout = AT91_I2C_TIMEOUT; + + rc = i2c_add_numbered_adapter(&dev->adapter); + if (rc) { + dev_err(dev->dev, "Adapter %s registration failed\n", + dev->adapter.name); + clk_disable_unprepare(dev->clk); + return rc; + } + + dev_info(dev->dev, "AT91 i2c bus driver.\n"); + return 0; +} + +static int __devexit at91_twi_remove(struct platform_device *pdev) +{ + struct at91_twi_dev *dev = platform_get_drvdata(pdev); + int rc; + + rc = i2c_del_adapter(&dev->adapter); + clk_disable_unprepare(dev->clk); + + return rc; +} + +#ifdef CONFIG_PM + +static int at91_twi_runtime_suspend(struct device *dev) +{ + struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); + + clk_disable(twi_dev->clk); + + return 0; +} + +static int at91_twi_runtime_resume(struct device *dev) +{ + struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); + + return clk_enable(twi_dev->clk); +} + +static const struct dev_pm_ops at91_twi_pm = { + .runtime_suspend = at91_twi_runtime_suspend, + .runtime_resume = at91_twi_runtime_resume, +}; + +#define at91_twi_pm_ops (&at91_twi_pm) +#else +#define at91_twi_pm_ops NULL +#endif + +static struct platform_driver at91_twi_driver = { + .probe = at91_twi_probe, + .remove = __devexit_p(at91_twi_remove), + .id_table = at91_twi_devtypes, + .driver = { + .name = "at91_i2c", + .owner = THIS_MODULE, + .pm = at91_twi_pm_ops, + }, +}; + +static int __init at91_twi_init(void) +{ + return platform_driver_register(&at91_twi_driver); +} + +static void __exit at91_twi_exit(void) +{ + platform_driver_unregister(&at91_twi_driver); +} + +subsys_initcall(at91_twi_init); +module_exit(at91_twi_exit); + +MODULE_AUTHOR("Nikolaus Voss "); +MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:at91_i2c"); -- cgit v1.2.3-70-g09d2 From 6ccbe607132bd823abbad8d32b13af89161707da Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 27 Sep 2012 23:44:25 -0700 Subject: i2c: add Renesas R-Car I2C driver R-Car I2C is similar with SH7760 I2C. But the SH7760 I2C driver had many workaround operations, since H/W had bugs. Thus, it was pointless to keep compatible between SH7760 and R-Car I2C drivers. This patch creates new Renesas R-Car I2C driver. Signed-off-by: Kuninori Morimoto Signed-off-by: Wolfram Sang --- drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-rcar.c | 709 ++++++++++++++++++++++++++++++++++++++++++ include/linux/i2c/i2c-rcar.h | 10 + 4 files changed, 730 insertions(+) create mode 100644 drivers/i2c/busses/i2c-rcar.c create mode 100644 include/linux/i2c/i2c-rcar.h (limited to 'drivers/i2c/busses/Makefile') diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index da77c37caf1..c8c11b21778 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -712,6 +712,16 @@ config I2C_XLR This driver can also be built as a module. If so, the module will be called i2c-xlr. +config I2C_RCAR + tristate "Renesas R-Car I2C Controller" + depends on ARCH_SHMOBILE && I2C + help + If you say yes to this option, support will be included for the + R-Car I2C controller. + + This driver can also be built as a module. If so, the module + will be called i2c-rcar. + comment "External I2C/SMBus adapter drivers" config I2C_DIOLAN_U2C diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index ce3c2be7fb4..e98ff51e9d9 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o obj-$(CONFIG_I2C_XLR) += i2c-xlr.o +obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c new file mode 100644 index 00000000000..f9399d163af --- /dev/null +++ b/drivers/i2c/busses/i2c-rcar.c @@ -0,0 +1,709 @@ +/* + * drivers/i2c/busses/i2c-rcar.c + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Kuninori Morimoto + * + * This file is based on the drivers/i2c/busses/i2c-sh7760.c + * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss + * + * This file used out-of-tree driver i2c-rcar.c + * Copyright (C) 2011-2012 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define ICSCR 0x00 /* slave ctrl */ +#define ICMCR 0x04 /* master ctrl */ +#define ICSSR 0x08 /* slave status */ +#define ICMSR 0x0C /* master status */ +#define ICSIER 0x10 /* slave irq enable */ +#define ICMIER 0x14 /* master irq enable */ +#define ICCCR 0x18 /* clock dividers */ +#define ICSAR 0x1C /* slave address */ +#define ICMAR 0x20 /* master address */ +#define ICRXTX 0x24 /* data port */ + +/* ICMCR */ +#define MDBS (1 << 7) /* non-fifo mode switch */ +#define FSCL (1 << 6) /* override SCL pin */ +#define FSDA (1 << 5) /* override SDA pin */ +#define OBPC (1 << 4) /* override pins */ +#define MIE (1 << 3) /* master if enable */ +#define TSBE (1 << 2) +#define FSB (1 << 1) /* force stop bit */ +#define ESG (1 << 0) /* en startbit gen */ + +/* ICMSR */ +#define MNR (1 << 6) /* nack received */ +#define MAL (1 << 5) /* arbitration lost */ +#define MST (1 << 4) /* sent a stop */ +#define MDE (1 << 3) +#define MDT (1 << 2) +#define MDR (1 << 1) +#define MAT (1 << 0) /* slave addr xfer done */ + +/* ICMIE */ +#define MNRE (1 << 6) /* nack irq en */ +#define MALE (1 << 5) /* arblos irq en */ +#define MSTE (1 << 4) /* stop irq en */ +#define MDEE (1 << 3) +#define MDTE (1 << 2) +#define MDRE (1 << 1) +#define MATE (1 << 0) /* address sent irq en */ + + +enum { + RCAR_BUS_PHASE_ADDR, + RCAR_BUS_PHASE_DATA, + RCAR_BUS_PHASE_STOP, +}; + +enum { + RCAR_IRQ_CLOSE, + RCAR_IRQ_OPEN_FOR_SEND, + RCAR_IRQ_OPEN_FOR_RECV, + RCAR_IRQ_OPEN_FOR_STOP, +}; + +/* + * flags + */ +#define ID_LAST_MSG (1 << 0) +#define ID_IOERROR (1 << 1) +#define ID_DONE (1 << 2) +#define ID_ARBLOST (1 << 3) +#define ID_NACK (1 << 4) + +struct rcar_i2c_priv { + void __iomem *io; + struct i2c_adapter adap; + struct i2c_msg *msg; + + spinlock_t lock; + wait_queue_head_t wait; + + int pos; + int irq; + u32 icccr; + u32 flags; +}; + +#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) +#define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD) + +#define rcar_i2c_flags_set(p, f) ((p)->flags |= (f)) +#define rcar_i2c_flags_has(p, f) ((p)->flags & (f)) + +#define LOOP_TIMEOUT 1024 + +/* + * basic functions + */ +static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val) +{ + writel(val, priv->io + reg); +} + +static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg) +{ + return readl(priv->io + reg); +} + +static void rcar_i2c_init(struct rcar_i2c_priv *priv) +{ + /* + * reset slave mode. + * slave mode is not used on this driver + */ + rcar_i2c_write(priv, ICSIER, 0); + rcar_i2c_write(priv, ICSAR, 0); + rcar_i2c_write(priv, ICSCR, 0); + rcar_i2c_write(priv, ICSSR, 0); + + /* reset master mode */ + rcar_i2c_write(priv, ICMIER, 0); + rcar_i2c_write(priv, ICMCR, 0); + rcar_i2c_write(priv, ICMSR, 0); + rcar_i2c_write(priv, ICMAR, 0); +} + +static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open) +{ + u32 val = MNRE | MALE | MSTE | MATE; /* default */ + + switch (open) { + case RCAR_IRQ_OPEN_FOR_SEND: + val |= MDEE; /* default + send */ + break; + case RCAR_IRQ_OPEN_FOR_RECV: + val |= MDRE; /* default + read */ + break; + case RCAR_IRQ_OPEN_FOR_STOP: + val = MSTE; /* stop irq only */ + break; + case RCAR_IRQ_CLOSE: + default: + val = 0; /* all close */ + break; + } + rcar_i2c_write(priv, ICMIER, val); +} + +static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) +{ + rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); +} + +/* + * bus control functions + */ +static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv) +{ + int i; + + for (i = 0; i < LOOP_TIMEOUT; i++) { + /* make sure that bus is not busy */ + if (!(rcar_i2c_read(priv, ICMCR) & FSDA)) + return 0; + udelay(1); + } + + return -EBUSY; +} + +static void rcar_i2c_bus_phase(struct rcar_i2c_priv *priv, int phase) +{ + switch (phase) { + case RCAR_BUS_PHASE_ADDR: + rcar_i2c_write(priv, ICMCR, MDBS | MIE | ESG); + break; + case RCAR_BUS_PHASE_DATA: + rcar_i2c_write(priv, ICMCR, MDBS | MIE); + break; + case RCAR_BUS_PHASE_STOP: + rcar_i2c_write(priv, ICMCR, MDBS | MIE | FSB); + break; + } +} + +/* + * clock function + */ +static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, + u32 bus_speed, + struct device *dev) +{ + struct clk *clkp = clk_get(NULL, "peripheral_clk"); + u32 scgd, cdf; + u32 round, ick; + u32 scl; + + if (!clkp) { + dev_err(dev, "there is no peripheral_clk\n"); + return -EIO; + } + + /* + * calculate SCL clock + * see + * ICCCR + * + * ick = clkp / (1 + CDF) + * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) + * + * ick : I2C internal clock < 20 MHz + * ticf : I2C SCL falling time = 35 ns here + * tr : I2C SCL rising time = 200 ns here + * intd : LSI internal delay = 50 ns here + * clkp : peripheral_clk + * F[] : integer up-valuation + */ + for (cdf = 0; cdf < 4; cdf++) { + ick = clk_get_rate(clkp) / (1 + cdf); + if (ick < 20000000) + goto ick_find; + } + dev_err(dev, "there is no best CDF\n"); + return -EIO; + +ick_find: + /* + * it is impossible to calculate large scale + * number on u32. separate it + * + * F[(ticf + tr + intd) * ick] + * = F[(35 + 200 + 50)ns * ick] + * = F[285 * ick / 1000000000] + * = F[(ick / 1000000) * 285 / 1000] + */ + round = (ick + 500000) / 1000000 * 285; + round = (round + 500) / 1000; + + /* + * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) + * + * Calculation result (= SCL) should be less than + * bus_speed for hardware safety + */ + for (scgd = 0; scgd < 0x40; scgd++) { + scl = ick / (20 + (scgd * 8) + round); + if (scl <= bus_speed) + goto scgd_find; + } + dev_err(dev, "it is impossible to calculate best SCL\n"); + return -EIO; + +scgd_find: + dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n", + scl, bus_speed, clk_get_rate(clkp), round, cdf, scgd); + + /* + * keep icccr value + */ + priv->icccr = (scgd << 2 | cdf); + + return 0; +} + +static void rcar_i2c_clock_start(struct rcar_i2c_priv *priv) +{ + rcar_i2c_write(priv, ICCCR, priv->icccr); +} + +/* + * status functions + */ +static u32 rcar_i2c_status_get(struct rcar_i2c_priv *priv) +{ + return rcar_i2c_read(priv, ICMSR); +} + +#define rcar_i2c_status_clear(priv) rcar_i2c_status_bit_clear(priv, 0xffffffff) +static void rcar_i2c_status_bit_clear(struct rcar_i2c_priv *priv, u32 bit) +{ + rcar_i2c_write(priv, ICMSR, ~bit); +} + +/* + * recv/send functions + */ +static int rcar_i2c_recv(struct rcar_i2c_priv *priv) +{ + rcar_i2c_set_addr(priv, 1); + rcar_i2c_status_clear(priv); + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); + rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); + + return 0; +} + +static int rcar_i2c_send(struct rcar_i2c_priv *priv) +{ + int ret; + + /* + * It should check bus status when send case + */ + ret = rcar_i2c_bus_barrier(priv); + if (ret < 0) + return ret; + + rcar_i2c_set_addr(priv, 0); + rcar_i2c_status_clear(priv); + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_ADDR); + rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); + + return 0; +} + +#define rcar_i2c_send_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDE)) +#define rcar_i2c_recv_restart(priv) rcar_i2c_status_bit_clear(priv, (MAT | MDR)) + +/* + * interrupt functions + */ +static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr) +{ + struct i2c_msg *msg = priv->msg; + + /* + * FIXME + * sometimes, unknown interrupt happened. + * Do nothing + */ + if (!(msr & MDE)) + return 0; + + /* + * If address transfer phase finished, + * goto data phase. + */ + if (msr & MAT) + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); + + if (priv->pos < msg->len) { + /* + * Prepare next data to ICRXTX register. + * This data will go to _SHIFT_ register. + * + * * + * [ICRXTX] -> [SHIFT] -> [I2C bus] + */ + rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]); + priv->pos++; + + } else { + /* + * The last data was pushed to ICRXTX on _PREV_ empty irq. + * It is on _SHIFT_ register, and will sent to I2C bus. + * + * * + * [ICRXTX] -> [SHIFT] -> [I2C bus] + */ + + if (priv->flags & ID_LAST_MSG) + /* + * If current msg is the _LAST_ msg, + * prepare stop condition here. + * ID_DONE will be set on STOP irq. + */ + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); + else + /* + * If current msg is _NOT_ last msg, + * it doesn't call stop phase. + * thus, there is no STOP irq. + * return ID_DONE here. + */ + return ID_DONE; + } + + rcar_i2c_send_restart(priv); + + return 0; +} + +static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr) +{ + struct i2c_msg *msg = priv->msg; + + /* + * FIXME + * sometimes, unknown interrupt happened. + * Do nothing + */ + if (!(msr & MDR)) + return 0; + + if (msr & MAT) { + /* + * Address transfer phase finished, + * but, there is no data at this point. + * Do nothing. + */ + } else if (priv->pos < msg->len) { + /* + * get received data + */ + msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX); + priv->pos++; + } + + /* + * If next received data is the _LAST_, + * go to STOP phase, + * otherwise, go to DATA phase. + */ + if (priv->pos + 1 >= msg->len) + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); + else + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_DATA); + + rcar_i2c_recv_restart(priv); + + return 0; +} + +static irqreturn_t rcar_i2c_irq(int irq, void *ptr) +{ + struct rcar_i2c_priv *priv = ptr; + struct device *dev = rcar_i2c_priv_to_dev(priv); + u32 msr; + + /*-------------- spin lock -----------------*/ + spin_lock(&priv->lock); + + msr = rcar_i2c_status_get(priv); + + /* + * Arbitration lost + */ + if (msr & MAL) { + /* + * CAUTION + * + * When arbitration lost, device become _slave_ mode. + */ + dev_dbg(dev, "Arbitration Lost\n"); + rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST)); + goto out; + } + + /* + * Stop + */ + if (msr & MST) { + dev_dbg(dev, "Stop\n"); + rcar_i2c_flags_set(priv, ID_DONE); + goto out; + } + + /* + * Nack + */ + if (msr & MNR) { + dev_dbg(dev, "Nack\n"); + + /* go to stop phase */ + rcar_i2c_bus_phase(priv, RCAR_BUS_PHASE_STOP); + rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); + rcar_i2c_flags_set(priv, ID_NACK); + goto out; + } + + /* + * recv/send + */ + if (rcar_i2c_is_recv(priv)) + rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr)); + else + rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr)); + +out: + if (rcar_i2c_flags_has(priv, ID_DONE)) { + rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); + rcar_i2c_status_clear(priv); + wake_up(&priv->wait); + } + + spin_unlock(&priv->lock); + /*-------------- spin unlock -----------------*/ + + return IRQ_HANDLED; +} + +static int rcar_i2c_master_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, + int num) +{ + struct rcar_i2c_priv *priv = i2c_get_adapdata(adap); + struct device *dev = rcar_i2c_priv_to_dev(priv); + unsigned long flags; + int i, ret, timeout; + + pm_runtime_get_sync(dev); + + /*-------------- spin lock -----------------*/ + spin_lock_irqsave(&priv->lock, flags); + + rcar_i2c_init(priv); + rcar_i2c_clock_start(priv); + + spin_unlock_irqrestore(&priv->lock, flags); + /*-------------- spin unlock -----------------*/ + + ret = -EINVAL; + for (i = 0; i < num; i++) { + /*-------------- spin lock -----------------*/ + spin_lock_irqsave(&priv->lock, flags); + + /* init each data */ + priv->msg = &msgs[i]; + priv->pos = 0; + priv->flags = 0; + if (priv->msg == &msgs[num - 1]) + rcar_i2c_flags_set(priv, ID_LAST_MSG); + + /* start send/recv */ + if (rcar_i2c_is_recv(priv)) + ret = rcar_i2c_recv(priv); + else + ret = rcar_i2c_send(priv); + + spin_unlock_irqrestore(&priv->lock, flags); + /*-------------- spin unlock -----------------*/ + + if (ret < 0) + break; + + /* + * wait result + */ + timeout = wait_event_timeout(priv->wait, + rcar_i2c_flags_has(priv, ID_DONE), + 5 * HZ); + if (!timeout) { + ret = -ETIMEDOUT; + break; + } + + /* + * error handling + */ + if (rcar_i2c_flags_has(priv, ID_NACK)) { + ret = -EREMOTEIO; + break; + } + + if (rcar_i2c_flags_has(priv, ID_ARBLOST)) { + ret = -EAGAIN; + break; + } + + if (rcar_i2c_flags_has(priv, ID_IOERROR)) { + ret = -EIO; + break; + } + + ret = i + 1; /* The number of transfer */ + } + + pm_runtime_put(dev); + + if (ret < 0) + dev_err(dev, "error %d : %x\n", ret, priv->flags); + + return ret; +} + +static u32 rcar_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm rcar_i2c_algo = { + .master_xfer = rcar_i2c_master_xfer, + .functionality = rcar_i2c_func, +}; + +static int __devinit rcar_i2c_probe(struct platform_device *pdev) +{ + struct i2c_rcar_platform_data *pdata = pdev->dev.platform_data; + struct rcar_i2c_priv *priv; + struct i2c_adapter *adap; + struct resource *res; + struct device *dev = &pdev->dev; + u32 bus_speed; + int ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "no mmio resources\n"); + return -ENODEV; + } + + priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); + if (!priv) { + dev_err(dev, "no mem for private data\n"); + return -ENOMEM; + } + + bus_speed = 100000; /* default 100 kHz */ + if (pdata && pdata->bus_speed) + bus_speed = pdata->bus_speed; + ret = rcar_i2c_clock_calculate(priv, bus_speed, dev); + if (ret < 0) + return ret; + + priv->io = devm_ioremap(dev, res->start, resource_size(res)); + if (!priv->io) { + dev_err(dev, "cannot ioremap\n"); + return -ENODEV; + } + + priv->irq = platform_get_irq(pdev, 0); + init_waitqueue_head(&priv->wait); + spin_lock_init(&priv->lock); + + adap = &priv->adap; + adap->nr = pdev->id; + adap->algo = &rcar_i2c_algo; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->retries = 3; + adap->dev.parent = dev; + i2c_set_adapdata(adap, priv); + strlcpy(adap->name, pdev->name, sizeof(adap->name)); + + ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, + dev_name(dev), priv); + if (ret < 0) { + dev_err(dev, "cannot get irq %d\n", priv->irq); + return ret; + } + + ret = i2c_add_numbered_adapter(adap); + if (ret < 0) { + dev_err(dev, "reg adap failed: %d\n", ret); + return ret; + } + + pm_runtime_enable(dev); + platform_set_drvdata(pdev, priv); + + dev_info(dev, "probed\n"); + + return 0; +} + +static int __devexit rcar_i2c_remove(struct platform_device *pdev) +{ + struct rcar_i2c_priv *priv = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + i2c_del_adapter(&priv->adap); + pm_runtime_disable(dev); + + return 0; +} + +static struct platform_driver rcar_i2c_drv = { + .driver = { + .name = "i2c-rcar", + .owner = THIS_MODULE, + }, + .probe = rcar_i2c_probe, + .remove = __devexit_p(rcar_i2c_remove), +}; + +module_platform_driver(rcar_i2c_drv); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); +MODULE_AUTHOR("Kuninori Morimoto "); diff --git a/include/linux/i2c/i2c-rcar.h b/include/linux/i2c/i2c-rcar.h new file mode 100644 index 00000000000..496f5c2b23c --- /dev/null +++ b/include/linux/i2c/i2c-rcar.h @@ -0,0 +1,10 @@ +#ifndef __I2C_R_CAR_H__ +#define __I2C_R_CAR_H__ + +#include + +struct i2c_rcar_platform_data { + u32 bus_speed; +}; + +#endif /* __I2C_R_CAR_H__ */ -- cgit v1.2.3-70-g09d2