From 903bfeac50ecc7725db606c19edbbc93966772c2 Mon Sep 17 00:00:00 2001 From: Andy Walls Date: Thu, 1 Jan 2009 11:09:24 -0300 Subject: V4L/DVB (10274): cx18: Fix a PLL divisor update for the I2S master clock A redundant PLL divisior update for the I2S master clock after AV core firmware load was missed in earlier PLL parameter changes. This one really doesn't matter because it's redundant and gets overwritten, but the driver should be self consistent in the values used. Signed-off-by: Andy Walls Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/cx18/cx18-av-firmware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/video/cx18') diff --git a/drivers/media/video/cx18/cx18-av-firmware.c b/drivers/media/video/cx18/cx18-av-firmware.c index c64fd0a05a9..d1fa0289b06 100644 --- a/drivers/media/video/cx18/cx18-av-firmware.c +++ b/drivers/media/video/cx18/cx18-av-firmware.c @@ -115,9 +115,9 @@ int cx18_av_loadfw(struct cx18 *cx) are generated) */ cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0); - /* set alt I2s master clock to /16 and enable alt divider i2s + /* set alt I2s master clock to /0x16 and enable alt divider i2s passthrough */ - cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687); + cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687); cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6, 0x3F00FFFF); -- cgit v1.2.3-70-g09d2