From 945a51517cc0bd9e461f2018624dfc1faef9ddee Mon Sep 17 00:00:00 2001 From: Jesse Brandeburg Date: Wed, 20 Jul 2011 00:56:21 +0000 Subject: intel drivers: repair missing flush operations after review of all intel drivers, found several instances where drivers had the incorrect pattern of: memory mapped write(); delay(); which should always be: memory mapped write(); write flush(); /* aka memory mapped read */ delay(); explanation: The reason for including the flush is that writes can be held (posted) in PCI/PCIe bridges, but the read always has to complete synchronously and therefore has to flush all pending writes to a device. If a write is held and followed by a delay, the delay means nothing because the write may not have reached hardware (maybe even not until the next read) Signed-off-by: Jesse Brandeburg Tested-by: Aaron Brown Signed-off-by: Jeff Kirsher --- drivers/net/e1000e/lib.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net/e1000e/lib.c') diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index 65580b40594..7898a67d650 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c @@ -1986,6 +1986,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) /* Clear SK and CS */ eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); ew32(EECD, eecd); + e1e_flush(); udelay(1); /* -- cgit v1.2.3-70-g09d2