From 423e38e8079f8f4fe0bf66d4f9a7d61beb232aca Mon Sep 17 00:00:00 2001 From: Rajkumar Manoharan Date: Thu, 13 Oct 2011 11:00:44 +0530 Subject: ath9k: Rename AR9480 into AR9462 Renamed to be in sync with Marketing term and to avoid confusion with other chip names. Signed-off-by: Rajkumar Manoharan Signed-off-by: John W. Linville --- .../net/wireless/ath/ath9k/ar9462_1p0_initvals.h | 62 +++++++++++----------- 1 file changed, 31 insertions(+), 31 deletions(-) (limited to 'drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h') diff --git a/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h index 4071bd2bd03..5c55ae389ad 100644 --- a/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h @@ -14,12 +14,12 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -#ifndef INITVALS_9480_1P0_H -#define INITVALS_9480_1P0_H +#ifndef INITVALS_9462_1P0_H +#define INITVALS_9462_1P0_H -/* AR9480 1.0 */ +/* AR9462 1.0 */ -static const u32 ar9480_1p0_mac_core[][2] = { +static const u32 ar9462_1p0_mac_core[][2] = { /* Addr allmodes */ {0x00000008, 0x00000000}, {0x00000030, 0x00060085}, @@ -183,27 +183,27 @@ static const u32 ar9480_1p0_mac_core[][2] = { {0x000083d0, 0x000301ff}, }; -static const u32 ar9480_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { +static const u32 ar9462_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { /* Addr allmodes */ {0x0000a398, 0x00000000}, {0x0000a39c, 0x6f7f0301}, {0x0000a3a0, 0xca9228ee}, }; -static const u32 ar9480_1p0_sys3ant[][2] = { +static const u32 ar9462_1p0_sys3ant[][2] = { /* Addr allmodes */ {0x00063280, 0x00040807}, {0x00063284, 0x104ccccc}, }; -static const u32 ar9480_pcie_phy_clkreq_enable_L1_1p0[][2] = { +static const u32 ar9462_pcie_phy_clkreq_enable_L1_1p0[][2] = { /* Addr allmodes */ {0x00018c00, 0x10053e5e}, {0x00018c04, 0x000801d8}, {0x00018c08, 0x0000580c}, }; -static const u32 ar9480_1p0_mac_core_emulation[][2] = { +static const u32 ar9462_1p0_mac_core_emulation[][2] = { /* Addr allmodes */ {0x00000030, 0x00060085}, {0x00000044, 0x00000008}, @@ -211,7 +211,7 @@ static const u32 ar9480_1p0_mac_core_emulation[][2] = { {0x00008344, 0xaa4a105b}, }; -static const u32 ar9480_common_rx_gain_table_ar9280_2p0_1p0[][2] = { +static const u32 ar9462_common_rx_gain_table_ar9280_2p0_1p0[][2] = { /* Addr allmodes */ {0x0000a000, 0x02000101}, {0x0000a004, 0x02000102}, @@ -513,7 +513,7 @@ static const u32 ar9200_ar9280_2p0_radio_core_1p0[][2] = { {0x00007894, 0x5a108000}, }; -static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = { +static const u32 ar9462_1p0_baseband_postamble_emulation[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, @@ -535,14 +535,14 @@ static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = { {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, }; -static const u32 ar9480_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = { +static const u32 ar9462_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = { /* Addr allmodes */ {0x00018c00, 0x10012e5e}, {0x00018c04, 0x000801d8}, {0x00018c08, 0x0000580c}, }; -static const u32 ar9480_common_rx_gain_table_1p0[][2] = { +static const u32 ar9462_common_rx_gain_table_1p0[][2] = { /* Addr allmodes */ {0x0000a000, 0x00010000}, {0x0000a004, 0x00030002}, @@ -802,7 +802,7 @@ static const u32 ar9480_common_rx_gain_table_1p0[][2] = { {0x0000b1fc, 0x00000196}, }; -static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = { +static const u32 ar9462_modes_high_ob_db_tx_gain_table_1p0[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, @@ -867,7 +867,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = { {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, }; -static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = { +static const u32 ar9462_common_wo_xlna_rx_gain_table_1p0[][2] = { /* Addr allmodes */ {0x0000a000, 0x00010000}, {0x0000a004, 0x00030002}, @@ -1127,7 +1127,7 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = { {0x0000b1fc, 0x00000196}, }; -static const u32 ar9480_1p0_mac_postamble[][5] = { +static const u32 ar9462_1p0_mac_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, @@ -1139,13 +1139,13 @@ static const u32 ar9480_1p0_mac_postamble[][5] = { {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, }; -static const u32 ar9480_1p0_mac_postamble_emulation[][5] = { +static const u32 ar9462_1p0_mac_postamble_emulation[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, }; -static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { +static const u32 ar9462_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, @@ -1163,7 +1163,7 @@ static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, }; -static const u32 ar9480_1p0_radio_postamble[][5] = { +static const u32 ar9462_1p0_radio_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08}, @@ -1174,12 +1174,12 @@ static const u32 ar9480_1p0_radio_postamble[][5] = { {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, }; -static const u32 ar9480_1p0_soc_postamble_emulation[][5] = { +static const u32 ar9462_1p0_soc_postamble_emulation[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133}, }; -static const u32 ar9480_1p0_baseband_core[][2] = { +static const u32 ar9462_1p0_baseband_core[][2] = { /* Addr allmodes */ {0x00009800, 0xafe68e30}, {0x00009804, 0xfd14e000}, @@ -1336,7 +1336,7 @@ static const u32 ar9480_1p0_baseband_core[][2] = { {0x0000b6b4, 0x00c00001}, }; -static const u32 ar9480_1p0_baseband_postamble[][5] = { +static const u32 ar9462_1p0_baseband_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, @@ -1386,7 +1386,7 @@ static const u32 ar9480_1p0_baseband_postamble[][5] = { {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, }; -static const u32 ar9480_modes_fast_clock_1p0[][3] = { +static const u32 ar9462_modes_fast_clock_1p0[][3] = { /* Addr 5G_HT20 5G_HT40 */ {0x00001030, 0x00000268, 0x000004d0}, {0x00001070, 0x0000018c, 0x00000318}, @@ -1399,7 +1399,7 @@ static const u32 ar9480_modes_fast_clock_1p0[][3] = { {0x0000a254, 0x00000898, 0x00001130}, }; -static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = { +static const u32 ar9462_modes_low_ob_db_tx_gain_table_1p0[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, @@ -1464,12 +1464,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = { {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, }; -static const u32 ar9480_1p0_soc_postamble[][5] = { +static const u32 ar9462_1p0_soc_postamble[][5] = { /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, }; -static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = { +static const u32 ar9462_common_mixed_rx_gain_table_1p0[][2] = { /* Addr allmodes */ {0x0000a000, 0x00010000}, {0x0000a004, 0x00030002}, @@ -1729,14 +1729,14 @@ static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = { {0x0000b1fc, 0x00000196}, }; -static const u32 ar9480_pcie_phy_clkreq_disable_L1_1p0[][2] = { +static const u32 ar9462_pcie_phy_clkreq_disable_L1_1p0[][2] = { /* Addr allmodes */ {0x00018c00, 0x10013e5e}, {0x00018c04, 0x000801d8}, {0x00018c08, 0x0000580c}, }; -static const u32 ar9480_1p0_baseband_core_emulation[][2] = { +static const u32 ar9462_1p0_baseband_core_emulation[][2] = { /* Addr allmodes */ {0x00009800, 0xafa68e30}, {0x00009884, 0x00002842}, @@ -1758,7 +1758,7 @@ static const u32 ar9480_1p0_baseband_core_emulation[][2] = { {0x0000a690, 0x00000038}, }; -static const u32 ar9480_1p0_radio_core[][2] = { +static const u32 ar9462_1p0_radio_core[][2] = { /* Addr allmodes */ {0x00016000, 0x36db6db6}, {0x00016004, 0x6db6db40}, @@ -1818,16 +1818,16 @@ static const u32 ar9480_1p0_radio_core[][2] = { {0x00016548, 0x000080c0}, }; -static const u32 ar9480_1p0_soc_preamble[][2] = { +static const u32 ar9462_1p0_soc_preamble[][2] = { /* Addr allmodes */ {0x00007020, 0x00000000}, {0x00007034, 0x00000002}, {0x00007038, 0x000004c2}, }; -static const u32 ar9480_1p0_sys2ant[][2] = { +static const u32 ar9462_1p0_sys2ant[][2] = { /* Addr allmodes */ {0x00063120, 0x00801980}, }; -#endif /* INITVALS_9480_1P0_H */ +#endif /* INITVALS_9462_1P0_H */ -- cgit v1.2.3-70-g09d2