From a778005589918c8051c496d8b7c96037776ed239 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Sat, 27 Oct 2012 14:47:47 +0530 Subject: pinctrl: SPEAr3xx: correct register space to configure pwm To have pwm on pad no. 34 we also need to select between pwm and SD_LED functions. Add this to pwm pin mux register configuration. Signed-off-by: Shiraz Hashim Signed-off-by: Viresh Kumar Reviewed-by: Vipin Kumar Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear320.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/pinctrl/spear/pinctrl-spear320.c') diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index 020b1e0bdb3..4fccf952954 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -2239,6 +2239,10 @@ static struct spear_muxreg pwm2_pin_34_muxreg[] = { .reg = PMX_CONFIG_REG, .mask = PMX_SSP_CS_MASK, .val = 0, + }, { + .reg = MODE_CONFIG_REG, + .mask = PMX_PWM_MASK, + .val = PMX_PWM_MASK, }, { .reg = IP_SEL_PAD_30_39_REG, .mask = PMX_PL_34_MASK, -- cgit v1.2.3-70-g09d2 From b06bf9a905e1d9ebb7326fa4110cf5eb105c872f Mon Sep 17 00:00:00 2001 From: Deepak Sikri Date: Sat, 27 Oct 2012 14:47:48 +0530 Subject: pinctrl: SPEAr320: Correct pad mux entries for rmii/smii pin entries of rmii and smii are interchanged by mistake. Fix it. Signed-off-by: Deepak Sikri Signed-off-by: Viresh Kumar Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear320.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pinctrl/spear/pinctrl-spear320.c') diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index 4fccf952954..ca47b0e5078 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -2960,9 +2960,9 @@ static struct spear_function mii2_function = { }; /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ -static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, +static const unsigned rmii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 }; -static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; +static const unsigned smii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; static struct spear_muxreg mii0_1_muxreg[] = { { .reg = PMX_CONFIG_REG, -- cgit v1.2.3-70-g09d2