From 6ae705b23be8da52d3163be9d81e9b767876aaf9 Mon Sep 17 00:00:00 2001 From: Denis Turischev Date: Thu, 10 Mar 2011 15:14:00 +0200 Subject: pch_uart: reference clock on CM-iTC Default clock source for UARTs on Topcliff is external UART_CLK. On CM-iTC USB_48MHz is used instead. After VCO2PLL and DIV manipulations UARTs will receive 192 MHz. Clock manipulations on Topcliff are controlled in pch_phub.c v2: redone against the linux-next tree v3: redone against linux/kernel/git/next/linux-next.git snapshot Signed-off-by: Denis Turischev Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/pch_uart.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/tty/serial') diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c index a5ce9a5c018..a9ad7f33526 100644 --- a/drivers/tty/serial/pch_uart.c +++ b/drivers/tty/serial/pch_uart.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -1404,14 +1405,18 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, if (!rxbuf) goto init_port_free_txbuf; + base_baud = 1843200; /* 1.8432MHz */ + + /* quirk for CM-iTC board */ + if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC")) + base_baud = 192000000; /* 192.0MHz */ + switch (port_type) { case PORT_UNKNOWN: fifosize = 256; /* EG20T/ML7213: UART0 */ - base_baud = 1843200; /* 1.8432MHz */ break; case PORT_8250: fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ - base_baud = 1843200; /* 1.8432MHz */ break; default: dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); -- cgit v1.2.3-70-g09d2