From 690c70bab1ebab0782cf9c316b726e2dddebc411 Mon Sep 17 00:00:00 2001 From: Ruchika Kharwar Date: Thu, 4 Jul 2013 00:21:19 -0500 Subject: usb: phy: omap-usb3: fix dpll clock index Correction of the omap_usb3_dpll_params array when the sys_clk_rate is 20MHz. Signed-off-by: Nikhil Devshatwar Signed-off-by: Ruchika Kharwar Signed-off-by: Felipe Balbi --- drivers/usb/phy/phy-omap-usb3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/usb/phy/phy-omap-usb3.c') diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/usb/phy/phy-omap-usb3.c index efe6e1464f4..a2fb30bbb97 100644 --- a/drivers/usb/phy/phy-omap-usb3.c +++ b/drivers/usb/phy/phy-omap-usb3.c @@ -71,9 +71,9 @@ static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = { {1250, 5, 4, 20, 0}, /* 12 MHz */ {3125, 20, 4, 20, 0}, /* 16.8 MHz */ {1172, 8, 4, 20, 65537}, /* 19.2 MHz */ + {1000, 7, 4, 10, 0}, /* 20 MHz */ {1250, 12, 4, 20, 0}, /* 26 MHz */ {3125, 47, 4, 20, 92843}, /* 38.4 MHz */ - {1000, 7, 4, 10, 0}, /* 20 MHz */ }; -- cgit v1.2.3-70-g09d2