From 70dfcfea4b728ab26af1a3e0f331cc63a7e3554b Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 11 Sep 2005 19:37:29 +1000 Subject: drm: missing drm_vm.c changes for consistent maps This adds a missing change from CVS for consistent maps. Signed-off-by: Dave Airlie --- drivers/char/drm/drm_vm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c index ced4215e227..a13d07f4420 100644 --- a/drivers/char/drm/drm_vm.c +++ b/drivers/char/drm/drm_vm.c @@ -148,7 +148,8 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, offset = address - vma->vm_start; i = (unsigned long)map->handle + offset; - page = vmalloc_to_page((void *)i); + page = (map->type == _DRM_CONSISTENT) ? + virt_to_page((void *)i) : vmalloc_to_page((void *)i); if (!page) return NOPAGE_OOM; get_page(page); -- cgit v1.2.3-70-g09d2 From 9d17601c4e132eee9fe450191f6866fb9fb5a762 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 11 Sep 2005 19:55:53 +1000 Subject: drm: update radeon driver to 1.18 Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) From: Roland Scheidegger, David Airlie Signed-off-by: David Airlie --- drivers/char/drm/radeon_drm.h | 11 ++++++++++- drivers/char/drm/radeon_drv.h | 11 +++++++++-- drivers/char/drm/radeon_state.c | 18 ++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h index 3792798270a..67a8bf04970 100644 --- a/drivers/char/drm/radeon_drm.h +++ b/drivers/char/drm/radeon_drm.h @@ -153,7 +153,16 @@ #define RADEON_EMIT_PP_CUBIC_FACES_2 82 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 #define R200_EMIT_PP_TRI_PERF_CNTL 84 -#define RADEON_MAX_STATE_PACKETS 85 +#define R200_EMIT_PP_AFS_0 85 +#define R200_EMIT_PP_AFS_1 86 +#define R200_EMIT_ATF_TFACTOR 87 +#define R200_EMIT_PP_TXCTLALL_0 88 +#define R200_EMIT_PP_TXCTLALL_1 89 +#define R200_EMIT_PP_TXCTLALL_2 90 +#define R200_EMIT_PP_TXCTLALL_3 91 +#define R200_EMIT_PP_TXCTLALL_4 92 +#define R200_EMIT_PP_TXCTLALL_5 93 +#define RADEON_MAX_STATE_PACKETS 94 /* Commands understood by cmd_buffer ioctl. More can be added but * obviously these can't be removed or changed: diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index f12a963ede1..430598e1fa6 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -38,7 +38,7 @@ #define DRIVER_NAME "radeon" #define DRIVER_DESC "ATI Radeon" -#define DRIVER_DATE "20050311" +#define DRIVER_DATE "20050720" /* Interface history: * @@ -83,9 +83,13 @@ * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear * texture filtering on r200 * 1.17- Add initial support for R300 (3D). + * 1.18- Add support for GL_ATI_fragment_shader, new packets + * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces + * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR + * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 17 +#define DRIVER_MINOR 18 #define DRIVER_PATCHLEVEL 0 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) @@ -857,6 +861,9 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define R200_PP_TRI_PERF 0x2cf8 +#define R200_PP_AFS_0 0x2f80 +#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ + /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 64a3e3a406e..c4325f1e229 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -207,6 +207,15 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case RADEON_EMIT_PP_CUBIC_FACES_1: case RADEON_EMIT_PP_CUBIC_FACES_2: case R200_EMIT_PP_TRI_PERF_CNTL: + case R200_EMIT_PP_AFS_0: + case R200_EMIT_PP_AFS_1: + case R200_EMIT_ATF_TFACTOR: + case R200_EMIT_PP_TXCTLALL_0: + case R200_EMIT_PP_TXCTLALL_1: + case R200_EMIT_PP_TXCTLALL_2: + case R200_EMIT_PP_TXCTLALL_3: + case R200_EMIT_PP_TXCTLALL_4: + case R200_EMIT_PP_TXCTLALL_5: /* These packets don't contain memory offsets */ break; @@ -568,6 +577,15 @@ static struct { { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ + { R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, + { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, }; -- cgit v1.2.3-70-g09d2 From ea98a92ff18c03bf7f4d21536986cbbcb4c10cd9 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 11 Sep 2005 20:28:11 +1000 Subject: drm: add radeon PCI express support Add support for Radeon PCI Express cards (needs a new X.org DDX) Also allows PCI GART table to be stored in VRAM for non PCIE cards Signed-off-by: Dave Airlie --- drivers/char/drm/ati_pcigart.c | 82 ++++++++++++++++++++++++----------------- drivers/char/drm/drmP.h | 24 +++++++++--- drivers/char/drm/r128_cce.c | 16 ++++---- drivers/char/drm/r128_drv.h | 3 +- drivers/char/drm/radeon_cp.c | 77 ++++++++++++++++++++++++++++++++++---- drivers/char/drm/radeon_drm.h | 1 + drivers/char/drm/radeon_drv.h | 39 ++++++++++++++++++-- drivers/char/drm/radeon_state.c | 3 ++ 8 files changed, 186 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c index 0aec5ef481b..957596c6393 100644 --- a/drivers/char/drm/ati_pcigart.c +++ b/drivers/char/drm/ati_pcigart.c @@ -91,9 +91,7 @@ static void drm_ati_free_pcigart_table( unsigned long address ) free_pages( address, ATI_PCIGART_TABLE_ORDER ); } -int drm_ati_pcigart_cleanup( drm_device_t *dev, - unsigned long addr, - dma_addr_t bus_addr) +int drm_ati_pcigart_cleanup(drm_device_t *dev, drm_ati_pcigart_info *gart_info) { drm_sg_mem_t *entry = dev->sg; unsigned long pages; @@ -105,10 +103,12 @@ int drm_ati_pcigart_cleanup( drm_device_t *dev, return 0; } - if ( bus_addr ) { - pci_unmap_single(dev->pdev, bus_addr, - ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, - PCI_DMA_TODEVICE); + if (gart_info->bus_addr) { + if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) { + pci_unmap_single(dev->pdev, gart_info->bus_addr, + ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, + PCI_DMA_TODEVICE); + } pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) ? entry->pages : ATI_MAX_PCIGART_PAGES; @@ -118,19 +118,21 @@ int drm_ati_pcigart_cleanup( drm_device_t *dev, pci_unmap_single(dev->pdev, entry->busaddr[i], PAGE_SIZE, PCI_DMA_TODEVICE); } + + if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) + gart_info->bus_addr=0; } - if ( addr ) { - drm_ati_free_pcigart_table( addr ); + if (gart_info->gart_table_location==DRM_ATI_GART_MAIN && gart_info->addr) { + drm_ati_free_pcigart_table(gart_info->addr); + gart_info->addr=0; } return 1; } EXPORT_SYMBOL(drm_ati_pcigart_cleanup); -int drm_ati_pcigart_init( drm_device_t *dev, - unsigned long *addr, - dma_addr_t *bus_addr) +int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) { drm_sg_mem_t *entry = dev->sg; unsigned long address = 0; @@ -143,25 +145,36 @@ int drm_ati_pcigart_init( drm_device_t *dev, goto done; } - address = drm_ati_alloc_pcigart_table(); - if ( !address ) { - DRM_ERROR( "cannot allocate PCI GART page!\n" ); - goto done; - } + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) + { + DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); + + address = drm_ati_alloc_pcigart_table(); + if ( !address ) { + DRM_ERROR( "cannot allocate PCI GART page!\n" ); + goto done; + } + + if ( !dev->pdev ) { + DRM_ERROR( "PCI device unknown!\n" ); + goto done; + } - if ( !dev->pdev ) { - DRM_ERROR( "PCI device unknown!\n" ); - goto done; + bus_address = pci_map_single(dev->pdev, (void *)address, + ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, + PCI_DMA_TODEVICE); + if (bus_address == 0) { + DRM_ERROR( "unable to map PCIGART pages!\n" ); + drm_ati_free_pcigart_table( address ); + address = 0; + goto done; + } } - - bus_address = pci_map_single(dev->pdev, (void *)address, - ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, - PCI_DMA_TODEVICE); - if (bus_address == 0) { - DRM_ERROR( "unable to map PCIGART pages!\n" ); - drm_ati_free_pcigart_table( address ); - address = 0; - goto done; + else + { + address = gart_info->addr; + bus_address = gart_info->bus_addr; + DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", bus_address, address); } pci_gart = (u32 *)address; @@ -179,7 +192,7 @@ int drm_ati_pcigart_init( drm_device_t *dev, PCI_DMA_TODEVICE); if (entry->busaddr[i] == 0) { DRM_ERROR( "unable to map PCIGART pages!\n" ); - drm_ati_pcigart_cleanup( dev, address, bus_address ); + drm_ati_pcigart_cleanup(dev, gart_info); address = 0; bus_address = 0; goto done; @@ -187,7 +200,10 @@ int drm_ati_pcigart_init( drm_device_t *dev, page_base = (u32) entry->busaddr[i]; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { - *pci_gart++ = cpu_to_le32( page_base ); + if (gart_info->is_pcie) + *pci_gart = (cpu_to_le32(page_base)>>8) | 0xc; + else + *pci_gart++ = cpu_to_le32( page_base ); page_base += ATI_PCIGART_PAGE_SIZE; } } @@ -201,8 +217,8 @@ int drm_ati_pcigart_init( drm_device_t *dev, #endif done: - *addr = address; - *bus_addr = bus_address; + gart_info->addr = address; + gart_info->bus_addr = bus_address; return ret; } EXPORT_SYMBOL(drm_ati_pcigart_init); diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h index 6f98701dfe1..c164c76e33f 100644 --- a/drivers/char/drm/drmP.h +++ b/drivers/char/drm/drmP.h @@ -532,6 +532,17 @@ typedef struct drm_vbl_sig { } drm_vbl_sig_t; +/* location of GART table */ +#define DRM_ATI_GART_MAIN 1 +#define DRM_ATI_GART_FB 2 + +typedef struct ati_pcigart_info { + int gart_table_location; + int is_pcie; + unsigned long addr; + dma_addr_t bus_addr; +} drm_ati_pcigart_info; + /** * DRM driver structure. This structure represent the common code for * a family of cards. There will one drm_device for each card present @@ -975,12 +986,8 @@ extern int drm_sg_free(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /* ATI PCIGART support (ati_pcigart.h) */ -extern int drm_ati_pcigart_init(drm_device_t *dev, - unsigned long *addr, - dma_addr_t *bus_addr); -extern int drm_ati_pcigart_cleanup(drm_device_t *dev, - unsigned long addr, - dma_addr_t bus_addr); +extern int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info *gart_info); +extern int drm_ati_pcigart_cleanup(drm_device_t * dev, drm_ati_pcigart_info *gart_info); extern drm_dma_handle_t *drm_pci_alloc(drm_device_t *dev, size_t size, size_t align, dma_addr_t maxaddr); @@ -1038,6 +1045,11 @@ static __inline__ int drm_device_is_agp(drm_device_t *dev) return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP); } +static __inline__ int drm_device_is_pcie(drm_device_t *dev) +{ + return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); +} + static __inline__ void drm_core_dropmap(struct drm_map *map) { } diff --git a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c index 895152206b3..ac3ea2bc9b2 100644 --- a/drivers/char/drm/r128_cce.c +++ b/drivers/char/drm/r128_cce.c @@ -562,14 +562,16 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) #if __OS_HAS_AGP if ( dev_priv->is_pci ) { #endif - if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart) ) { + dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; + dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr = 0; + dev_priv->gart_info.is_pcie = 0; + if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { DRM_ERROR( "failed to init PCI GART!\n" ); dev->dev_private = (void *)dev_priv; r128_do_cleanup_cce( dev ); return DRM_ERR(ENOMEM); } - R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); + R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); #if __OS_HAS_AGP } #endif @@ -607,10 +609,10 @@ int r128_do_cleanup_cce( drm_device_t *dev ) } else #endif { - if (!drm_ati_pcigart_cleanup( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); + if (dev_priv->gart_info.bus_addr) + if (!drm_ati_pcigart_cleanup( dev, + &dev_priv->gart_info)) + DRM_ERROR( "failed to cleanup PCI GART!\n" ); } drm_free( dev->dev_private, sizeof(drm_r128_private_t), diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h index 0fb687c9505..938dfaea553 100644 --- a/drivers/char/drm/r128_drv.h +++ b/drivers/char/drm/r128_drv.h @@ -88,8 +88,6 @@ typedef struct drm_r128_private { int usec_timeout; int is_pci; - unsigned long phys_pci_gart; - dma_addr_t bus_pci_gart; unsigned long cce_buffers_offset; atomic_t idle_count; @@ -120,6 +118,7 @@ typedef struct drm_r128_private { drm_local_map_t *cce_ring; drm_local_map_t *ring_rptr; drm_local_map_t *agp_textures; + drm_ati_pcigart_info gart_info; } drm_r128_private_t; typedef struct drm_r128_buf_priv { diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 6d9080a3ca7..6dff5e43f71 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c @@ -825,6 +825,12 @@ static int RADEON_READ_PLL(drm_device_t *dev, int addr) return RADEON_READ(RADEON_CLOCK_CNTL_DATA); } +static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) +{ + RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); + return RADEON_READ(RADEON_PCIE_DATA); +} + #if RADEON_FIFO_DEBUG static void radeon_status( drm_radeon_private_t *dev_priv ) { @@ -1241,17 +1247,46 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); } +/* Enable or disable PCI-E GART on the chip */ +static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) +{ + u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); + if (on) { + + DRM_DEBUG("programming pcie %08X %08lX %08X\n", + dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr, + dev_priv->gart_size); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start + + dev_priv->gart_size - 1); + + RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ + + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN); + } else { + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); + } +} + /* Enable or disable PCI GART on the chip */ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) { u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); + if (dev_priv->flags & CHIP_IS_PCIE) + { + radeon_set_pciegart(dev_priv, on); + return; + } + if ( on ) { RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); /* set PCI GART page-table base address */ - RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); + RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); /* set address range for PCI address translate */ @@ -1519,8 +1554,28 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } else #endif { - if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart, - &dev_priv->bus_pci_gart)) { + /* if we have an offset set from userspace */ + if (dev_priv->pcigart_offset) { + dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; + dev_priv->gart_info.addr = (unsigned long)drm_ioremap(dev_priv->gart_info.bus_addr, RADEON_PCIGART_TABLE_SIZE, dev); + + dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE); + dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; + + DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset); + } + else { + dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; + dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr= 0; + if (dev_priv->flags & CHIP_IS_PCIE) + { + DRM_ERROR("Cannot use PCI Express without GART in FB memory\n"); + radeon_do_cleanup_cp(dev); + return DRM_ERR(EINVAL); + } + } + + if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { DRM_ERROR( "failed to init PCI GART!\n" ); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); @@ -1568,10 +1623,15 @@ static int radeon_do_cleanup_cp( drm_device_t *dev ) } else #endif { - if (!drm_ati_pcigart_cleanup( dev, - dev_priv->phys_pci_gart, - dev_priv->bus_pci_gart )) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); + if (dev_priv->gart_info.bus_addr) + if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) + DRM_ERROR("failed to cleanup PCI GART!\n"); + + if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) + { + drm_ioremapfree((void *)dev_priv->gart_info.addr, RADEON_PCIGART_TABLE_SIZE, dev); + dev_priv->gart_info.addr = 0; + } } /* only clear to the start of flags */ @@ -2057,6 +2117,9 @@ int radeon_driver_preinit(struct drm_device *dev, unsigned long flags) if (drm_device_is_agp(dev)) dev_priv->flags |= CHIP_IS_AGP; + if (drm_device_is_pcie(dev)) + dev_priv->flags |= CHIP_IS_PCIE; + DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI")); return ret; diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h index 67a8bf04970..dd526617fae 100644 --- a/drivers/char/drm/radeon_drm.h +++ b/drivers/char/drm/radeon_drm.h @@ -698,6 +698,7 @@ typedef struct drm_radeon_setparam { #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ +#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ /* 1.14: Clients can allocate/free a surface */ diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 430598e1fa6..9c10141845e 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -38,7 +38,7 @@ #define DRIVER_NAME "radeon" #define DRIVER_DESC "ATI Radeon" -#define DRIVER_DATE "20050720" +#define DRIVER_DATE "20050911" /* Interface history: * @@ -87,9 +87,10 @@ * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) + * 1.19- Add support for gart table in FB memory and PCIE r300 */ #define DRIVER_MAJOR 1 -#define DRIVER_MINOR 18 +#define DRIVER_MINOR 19 #define DRIVER_PATCHLEVEL 0 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) @@ -134,6 +135,7 @@ enum radeon_chip_flags { CHIP_SINGLE_CRTC = 0x00040000UL, CHIP_IS_AGP = 0x00080000UL, CHIP_HAS_HIERZ = 0x00100000UL, + CHIP_IS_PCIE = 0x00200000UL, }; typedef struct drm_radeon_freelist { @@ -213,8 +215,6 @@ typedef struct drm_radeon_private { int microcode_version; int is_pci; - unsigned long phys_pci_gart; - dma_addr_t bus_pci_gart; struct { u32 boxes; @@ -270,6 +270,9 @@ typedef struct drm_radeon_private { struct radeon_surface surfaces[RADEON_MAX_SURFACES]; struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; + unsigned long pcigart_offset; + drm_ati_pcigart_info gart_info; + /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ } drm_radeon_private_t; @@ -373,6 +376,25 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define RADEON_CRTC2_OFFSET 0x0324 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 +#define RADEON_PCIE_INDEX 0x0030 +#define RADEON_PCIE_DATA 0x0034 +#define RADEON_PCIE_TX_GART_CNTL 0x10 +# define RADEON_PCIE_TX_GART_EN (1 << 0) +# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) +# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) +# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) +# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) +# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) +# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) +# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) +#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 +#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 +#define RADEON_PCIE_TX_GART_BASE 0x13 +#define RADEON_PCIE_TX_GART_START_LO 0x14 +#define RADEON_PCIE_TX_GART_START_HI 0x15 +#define RADEON_PCIE_TX_GART_END_LO 0x16 +#define RADEON_PCIE_TX_GART_END_HI 0x17 + #define RADEON_MPP_TB_CONFIG 0x01c0 #define RADEON_MEM_CNTL 0x0140 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 @@ -878,6 +900,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define RADEON_RING_HIGH_MARK 128 +#define RADEON_PCIGART_TABLE_SIZE (32*1024) + #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) @@ -890,6 +914,13 @@ do { \ RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ } while (0) +#define RADEON_WRITE_PCIE( addr, val ) \ +do { \ + RADEON_WRITE8( RADEON_PCIE_INDEX, \ + ((addr) & 0xff)); \ + RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ +} while (0) + #define CP_PACKET0( reg, n ) \ (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) #define CP_PACKET0_TABLE( reg, n ) \ diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index c4325f1e229..74c2fe8033c 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -3034,6 +3034,9 @@ static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { dev_priv->sarea_priv->tiling_enabled = 1; } break; + case RADEON_SETPARAM_PCIGART_LOCATION: + dev_priv->pcigart_offset = sp.value; + break; default: DRM_DEBUG( "Invalid parameter %d\n", sp.param ); return DRM_ERR( EINVAL ); -- cgit v1.2.3-70-g09d2 From aacaf9bd9646f6f611a08fca976411b6e5ddefe2 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sat, 17 Sep 2005 10:36:54 -0500 Subject: [PATCH] powerpc: Remove sections use from ppc64 and drivers Here is a new patch that removes all notion of the pmac, prep, chrp and openfirmware initialization sections, and then unifies the sections.h files without those __pmac, etc, sections identifiers cluttering things up. Signed-off-by: Jon Loeliger Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/ppc64/kernel/pmac_feature.c | 60 +++++++++--------- arch/ppc64/kernel/pmac_nvram.c | 30 ++++----- arch/ppc64/kernel/pmac_pci.c | 12 ++-- arch/ppc64/kernel/pmac_setup.c | 10 +-- arch/ppc64/kernel/pmac_smp.c | 2 +- arch/ppc64/kernel/pmac_time.c | 4 +- drivers/ide/ppc/pmac.c | 80 ++++++++++++------------ drivers/macintosh/ans-lcd.c | 10 +-- drivers/macintosh/mediabay.c | 56 ++++++++--------- drivers/macintosh/via-cuda.c | 1 - drivers/macintosh/via-pmu.c | 129 +++++++++++++++++++-------------------- drivers/macintosh/via-pmu68k.c | 15 +++-- 12 files changed, 203 insertions(+), 206 deletions(-) (limited to 'drivers') diff --git a/arch/ppc64/kernel/pmac_feature.c b/arch/ppc64/kernel/pmac_feature.c index eb4e6c3f694..26075f11db7 100644 --- a/arch/ppc64/kernel/pmac_feature.c +++ b/arch/ppc64/kernel/pmac_feature.c @@ -53,7 +53,7 @@ * We use a single global lock to protect accesses. Each driver has * to take care of its own locking */ -static DEFINE_SPINLOCK(feature_lock __pmacdata); +static DEFINE_SPINLOCK(feature_lock); #define LOCK(flags) spin_lock_irqsave(&feature_lock, flags); #define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags); @@ -62,9 +62,9 @@ static DEFINE_SPINLOCK(feature_lock __pmacdata); /* * Instance of some macio stuffs */ -struct macio_chip macio_chips[MAX_MACIO_CHIPS] __pmacdata; +struct macio_chip macio_chips[MAX_MACIO_CHIPS] ; -struct macio_chip* __pmac macio_find(struct device_node* child, int type) +struct macio_chip* macio_find(struct device_node* child, int type) { while(child) { int i; @@ -79,7 +79,7 @@ struct macio_chip* __pmac macio_find(struct device_node* child, int type) } EXPORT_SYMBOL_GPL(macio_find); -static const char* macio_names[] __pmacdata = +static const char* macio_names[] = { "Unknown", "Grand Central", @@ -106,9 +106,9 @@ static const char* macio_names[] __pmacdata = #define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v))) #define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v))) -static struct device_node* uninorth_node __pmacdata; -static u32* uninorth_base __pmacdata; -static u32 uninorth_rev __pmacdata; +static struct device_node* uninorth_node; +static u32* uninorth_base; +static u32 uninorth_rev; static void *u3_ht; extern struct device_node *k2_skiplist[2]; @@ -133,14 +133,14 @@ struct pmac_mb_def struct feature_table_entry* features; unsigned long board_flags; }; -static struct pmac_mb_def pmac_mb __pmacdata; +static struct pmac_mb_def pmac_mb; /* * Here are the chip specific feature functions */ -static long __pmac g5_read_gpio(struct device_node* node, long param, long value) +static long g5_read_gpio(struct device_node* node, long param, long value) { struct macio_chip* macio = &macio_chips[0]; @@ -148,7 +148,7 @@ static long __pmac g5_read_gpio(struct device_node* node, long param, long value } -static long __pmac g5_write_gpio(struct device_node* node, long param, long value) +static long g5_write_gpio(struct device_node* node, long param, long value) { struct macio_chip* macio = &macio_chips[0]; @@ -156,7 +156,7 @@ static long __pmac g5_write_gpio(struct device_node* node, long param, long valu return 0; } -static long __pmac g5_gmac_enable(struct device_node* node, long param, long value) +static long g5_gmac_enable(struct device_node* node, long param, long value) { struct macio_chip* macio = &macio_chips[0]; unsigned long flags; @@ -181,7 +181,7 @@ static long __pmac g5_gmac_enable(struct device_node* node, long param, long val return 0; } -static long __pmac g5_fw_enable(struct device_node* node, long param, long value) +static long g5_fw_enable(struct device_node* node, long param, long value) { struct macio_chip* macio = &macio_chips[0]; unsigned long flags; @@ -206,7 +206,7 @@ static long __pmac g5_fw_enable(struct device_node* node, long param, long value return 0; } -static long __pmac g5_mpic_enable(struct device_node* node, long param, long value) +static long g5_mpic_enable(struct device_node* node, long param, long value) { unsigned long flags; @@ -220,7 +220,7 @@ static long __pmac g5_mpic_enable(struct device_node* node, long param, long val return 0; } -static long __pmac g5_eth_phy_reset(struct device_node* node, long param, long value) +static long g5_eth_phy_reset(struct device_node* node, long param, long value) { struct macio_chip* macio = &macio_chips[0]; struct device_node *phy; @@ -250,7 +250,7 @@ static long __pmac g5_eth_phy_reset(struct device_node* node, long param, long v return 0; } -static long __pmac g5_i2s_enable(struct device_node *node, long param, long value) +static long g5_i2s_enable(struct device_node *node, long param, long value) { /* Very crude implementation for now */ struct macio_chip* macio = &macio_chips[0]; @@ -275,7 +275,7 @@ static long __pmac g5_i2s_enable(struct device_node *node, long param, long valu #ifdef CONFIG_SMP -static long __pmac g5_reset_cpu(struct device_node* node, long param, long value) +static long g5_reset_cpu(struct device_node* node, long param, long value) { unsigned int reset_io = 0; unsigned long flags; @@ -320,12 +320,12 @@ static long __pmac g5_reset_cpu(struct device_node* node, long param, long value * This takes the second CPU off the bus on dual CPU machines * running UP */ -void __pmac g5_phy_disable_cpu1(void) +void g5_phy_disable_cpu1(void) { UN_OUT(U3_API_PHY_CONFIG_1, 0); } -static long __pmac generic_get_mb_info(struct device_node* node, long param, long value) +static long generic_get_mb_info(struct device_node* node, long param, long value) { switch(param) { case PMAC_MB_INFO_MODEL: @@ -347,14 +347,14 @@ static long __pmac generic_get_mb_info(struct device_node* node, long param, lon /* Used on any machine */ -static struct feature_table_entry any_features[] __pmacdata = { +static struct feature_table_entry any_features[] = { { PMAC_FTR_GET_MB_INFO, generic_get_mb_info }, { 0, NULL } }; /* G5 features */ -static struct feature_table_entry g5_features[] __pmacdata = { +static struct feature_table_entry g5_features[] = { { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable }, { PMAC_FTR_1394_ENABLE, g5_fw_enable }, { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable }, @@ -368,7 +368,7 @@ static struct feature_table_entry g5_features[] __pmacdata = { { 0, NULL } }; -static struct pmac_mb_def pmac_mb_defs[] __pmacdata = { +static struct pmac_mb_def pmac_mb_defs[] = { { "PowerMac7,2", "PowerMac G5", PMAC_TYPE_POWERMAC_G5, g5_features, 0, @@ -394,7 +394,7 @@ static struct pmac_mb_def pmac_mb_defs[] __pmacdata = { /* * The toplevel feature_call callback */ -long __pmac pmac_do_feature_call(unsigned int selector, ...) +long pmac_do_feature_call(unsigned int selector, ...) { struct device_node* node; long param, value; @@ -706,8 +706,8 @@ void __init pmac_check_ht_link(void) * Early video resume hook */ -static void (*pmac_early_vresume_proc)(void *data) __pmacdata; -static void *pmac_early_vresume_data __pmacdata; +static void (*pmac_early_vresume_proc)(void *data); +static void *pmac_early_vresume_data; void pmac_set_early_video_resume(void (*proc)(void *data), void *data) { @@ -725,11 +725,11 @@ EXPORT_SYMBOL(pmac_set_early_video_resume); * AGP related suspend/resume code */ -static struct pci_dev *pmac_agp_bridge __pmacdata; -static int (*pmac_agp_suspend)(struct pci_dev *bridge) __pmacdata; -static int (*pmac_agp_resume)(struct pci_dev *bridge) __pmacdata; +static struct pci_dev *pmac_agp_bridge; +static int (*pmac_agp_suspend)(struct pci_dev *bridge); +static int (*pmac_agp_resume)(struct pci_dev *bridge); -void __pmac pmac_register_agp_pm(struct pci_dev *bridge, +void pmac_register_agp_pm(struct pci_dev *bridge, int (*suspend)(struct pci_dev *bridge), int (*resume)(struct pci_dev *bridge)) { @@ -746,7 +746,7 @@ void __pmac pmac_register_agp_pm(struct pci_dev *bridge, } EXPORT_SYMBOL(pmac_register_agp_pm); -void __pmac pmac_suspend_agp_for_card(struct pci_dev *dev) +void pmac_suspend_agp_for_card(struct pci_dev *dev) { if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) return; @@ -756,7 +756,7 @@ void __pmac pmac_suspend_agp_for_card(struct pci_dev *dev) } EXPORT_SYMBOL(pmac_suspend_agp_for_card); -void __pmac pmac_resume_agp_for_card(struct pci_dev *dev) +void pmac_resume_agp_for_card(struct pci_dev *dev) { if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) return; diff --git a/arch/ppc64/kernel/pmac_nvram.c b/arch/ppc64/kernel/pmac_nvram.c index e32a902236e..11586d535f8 100644 --- a/arch/ppc64/kernel/pmac_nvram.c +++ b/arch/ppc64/kernel/pmac_nvram.c @@ -82,10 +82,10 @@ extern int system_running; static int (*core99_write_bank)(int bank, u8* datas); static int (*core99_erase_bank)(int bank); -static char *nvram_image __pmacdata; +static char *nvram_image; -static ssize_t __pmac core99_nvram_read(char *buf, size_t count, loff_t *index) +static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index) { int i; @@ -103,7 +103,7 @@ static ssize_t __pmac core99_nvram_read(char *buf, size_t count, loff_t *index) return count; } -static ssize_t __pmac core99_nvram_write(char *buf, size_t count, loff_t *index) +static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index) { int i; @@ -121,14 +121,14 @@ static ssize_t __pmac core99_nvram_write(char *buf, size_t count, loff_t *index) return count; } -static ssize_t __pmac core99_nvram_size(void) +static ssize_t core99_nvram_size(void) { if (nvram_image == NULL) return -ENODEV; return NVRAM_SIZE; } -static u8 __pmac chrp_checksum(struct chrp_header* hdr) +static u8 chrp_checksum(struct chrp_header* hdr) { u8 *ptr; u16 sum = hdr->signature; @@ -139,7 +139,7 @@ static u8 __pmac chrp_checksum(struct chrp_header* hdr) return sum; } -static u32 __pmac core99_calc_adler(u8 *buffer) +static u32 core99_calc_adler(u8 *buffer) { int cnt; u32 low, high; @@ -161,7 +161,7 @@ static u32 __pmac core99_calc_adler(u8 *buffer) return (high << 16) | low; } -static u32 __pmac core99_check(u8* datas) +static u32 core99_check(u8* datas) { struct core99_header* hdr99 = (struct core99_header*)datas; @@ -180,7 +180,7 @@ static u32 __pmac core99_check(u8* datas) return hdr99->generation; } -static int __pmac sm_erase_bank(int bank) +static int sm_erase_bank(int bank) { int stat, i; unsigned long timeout; @@ -212,7 +212,7 @@ static int __pmac sm_erase_bank(int bank) return 0; } -static int __pmac sm_write_bank(int bank, u8* datas) +static int sm_write_bank(int bank, u8* datas) { int i, stat = 0; unsigned long timeout; @@ -247,7 +247,7 @@ static int __pmac sm_write_bank(int bank, u8* datas) return 0; } -static int __pmac amd_erase_bank(int bank) +static int amd_erase_bank(int bank) { int i, stat = 0; unsigned long timeout; @@ -294,7 +294,7 @@ static int __pmac amd_erase_bank(int bank) return 0; } -static int __pmac amd_write_bank(int bank, u8* datas) +static int amd_write_bank(int bank, u8* datas) { int i, stat = 0; unsigned long timeout; @@ -341,7 +341,7 @@ static int __pmac amd_write_bank(int bank, u8* datas) } -static int __pmac core99_nvram_sync(void) +static int core99_nvram_sync(void) { struct core99_header* hdr99; unsigned long flags; @@ -431,7 +431,7 @@ int __init pmac_nvram_init(void) return 0; } -int __pmac pmac_get_partition(int partition) +int pmac_get_partition(int partition) { struct nvram_partition *part; const char *name; @@ -459,7 +459,7 @@ int __pmac pmac_get_partition(int partition) return part->index; } -u8 __pmac pmac_xpram_read(int xpaddr) +u8 pmac_xpram_read(int xpaddr) { int offset = pmac_get_partition(pmac_nvram_XPRAM); loff_t index; @@ -476,7 +476,7 @@ u8 __pmac pmac_xpram_read(int xpaddr) return buf; } -void __pmac pmac_xpram_write(int xpaddr, u8 data) +void pmac_xpram_write(int xpaddr, u8 data) { int offset = pmac_get_partition(pmac_nvram_XPRAM); loff_t index; diff --git a/arch/ppc64/kernel/pmac_pci.c b/arch/ppc64/kernel/pmac_pci.c index dc40a0cad0b..1f61aa4746e 100644 --- a/arch/ppc64/kernel/pmac_pci.c +++ b/arch/ppc64/kernel/pmac_pci.c @@ -121,7 +121,7 @@ static void __init fixup_bus_range(struct device_node *bridge) |(((unsigned long)(off)) & 0xFCUL) \ |1UL) -static unsigned long __pmac macrisc_cfg_access(struct pci_controller* hose, +static unsigned long macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) { unsigned int caddr; @@ -142,7 +142,7 @@ static unsigned long __pmac macrisc_cfg_access(struct pci_controller* hose, return ((unsigned long)hose->cfg_data) + offset; } -static int __pmac macrisc_read_config(struct pci_bus *bus, unsigned int devfn, +static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; @@ -173,7 +173,7 @@ static int __pmac macrisc_read_config(struct pci_bus *bus, unsigned int devfn, return PCIBIOS_SUCCESSFUL; } -static int __pmac macrisc_write_config(struct pci_bus *bus, unsigned int devfn, +static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; @@ -265,7 +265,7 @@ static int u3_ht_skip_device(struct pci_controller *hose, + (((unsigned long)bus) << 16) \ + 0x01000000UL) -static unsigned long __pmac u3_ht_cfg_access(struct pci_controller* hose, +static unsigned long u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) { if (bus == hose->first_busno) { @@ -277,7 +277,7 @@ static unsigned long __pmac u3_ht_cfg_access(struct pci_controller* hose, return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); } -static int __pmac u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, +static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose; @@ -327,7 +327,7 @@ static int __pmac u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, return PCIBIOS_SUCCESSFUL; } -static int __pmac u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, +static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) { struct pci_controller *hose; diff --git a/arch/ppc64/kernel/pmac_setup.c b/arch/ppc64/kernel/pmac_setup.c index 325426c7bed..1f5118078f7 100644 --- a/arch/ppc64/kernel/pmac_setup.c +++ b/arch/ppc64/kernel/pmac_setup.c @@ -98,7 +98,7 @@ EXPORT_SYMBOL(smu_cmdbuf_abs); extern void udbg_init_scc(struct device_node *np); -static void __pmac pmac_show_cpuinfo(struct seq_file *m) +static void pmac_show_cpuinfo(struct seq_file *m) { struct device_node *np; char *pp; @@ -210,7 +210,7 @@ static int pmac_late_init(void) late_initcall(pmac_late_init); /* can't be __init - can be called whenever a disk is first accessed */ -void __pmac note_bootable_part(dev_t dev, int part, int goodness) +void note_bootable_part(dev_t dev, int part, int goodness) { extern dev_t boot_dev; char *p; @@ -231,7 +231,7 @@ void __pmac note_bootable_part(dev_t dev, int part, int goodness) } } -static void __pmac pmac_restart(char *cmd) +static void pmac_restart(char *cmd) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU @@ -250,7 +250,7 @@ static void __pmac pmac_restart(char *cmd) } } -static void __pmac pmac_power_off(void) +static void pmac_power_off(void) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU @@ -268,7 +268,7 @@ static void __pmac pmac_power_off(void) } } -static void __pmac pmac_halt(void) +static void pmac_halt(void) { pmac_power_off(); } diff --git a/arch/ppc64/kernel/pmac_smp.c b/arch/ppc64/kernel/pmac_smp.c index a23de37227b..9fd23ea55bc 100644 --- a/arch/ppc64/kernel/pmac_smp.c +++ b/arch/ppc64/kernel/pmac_smp.c @@ -310,7 +310,7 @@ static void __init smp_core99_setup_cpu(int cpu_nr) } } -struct smp_ops_t core99_smp_ops __pmacdata = { +struct smp_ops_t core99_smp_ops = { .message_pass = smp_mpic_message_pass, .probe = smp_core99_probe, .kick_cpu = smp_core99_kick_cpu, diff --git a/arch/ppc64/kernel/pmac_time.c b/arch/ppc64/kernel/pmac_time.c index 3059edb09cc..6c8c99295e7 100644 --- a/arch/ppc64/kernel/pmac_time.c +++ b/arch/ppc64/kernel/pmac_time.c @@ -51,7 +51,7 @@ extern struct timezone sys_tz; extern void to_tm(int tim, struct rtc_time * tm); -void __pmac pmac_get_rtc_time(struct rtc_time *tm) +void pmac_get_rtc_time(struct rtc_time *tm) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU @@ -92,7 +92,7 @@ void __pmac pmac_get_rtc_time(struct rtc_time *tm) } } -int __pmac pmac_set_rtc_time(struct rtc_time *tm) +int pmac_set_rtc_time(struct rtc_time *tm) { switch(sys_ctrler) { #ifdef CONFIG_ADB_PMU diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c index 87d1f8a1f41..d8c3d8ebad3 100644 --- a/drivers/ide/ppc/pmac.c +++ b/drivers/ide/ppc/pmac.c @@ -81,7 +81,7 @@ typedef struct pmac_ide_hwif { } pmac_ide_hwif_t; -static pmac_ide_hwif_t pmac_ide[MAX_HWIFS] __pmacdata; +static pmac_ide_hwif_t pmac_ide[MAX_HWIFS]; static int pmac_ide_count; enum { @@ -242,7 +242,7 @@ struct mdma_timings_t { int cycleTime; }; -struct mdma_timings_t mdma_timings_33[] __pmacdata = +struct mdma_timings_t mdma_timings_33[] = { { 240, 240, 480 }, { 180, 180, 360 }, @@ -255,7 +255,7 @@ struct mdma_timings_t mdma_timings_33[] __pmacdata = { 0, 0, 0 } }; -struct mdma_timings_t mdma_timings_33k[] __pmacdata = +struct mdma_timings_t mdma_timings_33k[] = { { 240, 240, 480 }, { 180, 180, 360 }, @@ -268,7 +268,7 @@ struct mdma_timings_t mdma_timings_33k[] __pmacdata = { 0, 0, 0 } }; -struct mdma_timings_t mdma_timings_66[] __pmacdata = +struct mdma_timings_t mdma_timings_66[] = { { 240, 240, 480 }, { 180, 180, 360 }, @@ -286,7 +286,7 @@ struct { int addrSetup; /* ??? */ int rdy2pause; int wrDataSetup; -} kl66_udma_timings[] __pmacdata = +} kl66_udma_timings[] = { { 0, 180, 120 }, /* Mode 0 */ { 0, 150, 90 }, /* 1 */ @@ -301,7 +301,7 @@ struct kauai_timing { u32 timing_reg; }; -static struct kauai_timing kauai_pio_timings[] __pmacdata = +static struct kauai_timing kauai_pio_timings[] = { { 930 , 0x08000fff }, { 600 , 0x08000a92 }, @@ -316,7 +316,7 @@ static struct kauai_timing kauai_pio_timings[] __pmacdata = { 120 , 0x04000148 } }; -static struct kauai_timing kauai_mdma_timings[] __pmacdata = +static struct kauai_timing kauai_mdma_timings[] = { { 1260 , 0x00fff000 }, { 480 , 0x00618000 }, @@ -330,7 +330,7 @@ static struct kauai_timing kauai_mdma_timings[] __pmacdata = { 0 , 0 }, }; -static struct kauai_timing kauai_udma_timings[] __pmacdata = +static struct kauai_timing kauai_udma_timings[] = { { 120 , 0x000070c0 }, { 90 , 0x00005d80 }, @@ -341,7 +341,7 @@ static struct kauai_timing kauai_udma_timings[] __pmacdata = { 0 , 0 }, }; -static struct kauai_timing shasta_pio_timings[] __pmacdata = +static struct kauai_timing shasta_pio_timings[] = { { 930 , 0x08000fff }, { 600 , 0x0A000c97 }, @@ -356,7 +356,7 @@ static struct kauai_timing shasta_pio_timings[] __pmacdata = { 120 , 0x0400010a } }; -static struct kauai_timing shasta_mdma_timings[] __pmacdata = +static struct kauai_timing shasta_mdma_timings[] = { { 1260 , 0x00fff000 }, { 480 , 0x00820800 }, @@ -370,7 +370,7 @@ static struct kauai_timing shasta_mdma_timings[] __pmacdata = { 0 , 0 }, }; -static struct kauai_timing shasta_udma133_timings[] __pmacdata = +static struct kauai_timing shasta_udma133_timings[] = { { 120 , 0x00035901, }, { 90 , 0x000348b1, }, @@ -522,7 +522,7 @@ pmu_hd_blink_init(void) * N.B. this can't be an initfunc, because the media-bay task can * call ide_[un]register at any time. */ -void __pmac +void pmac_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, unsigned long ctrl_port, int *irq) @@ -559,7 +559,7 @@ pmac_ide_init_hwif_ports(hw_regs_t *hw, * timing register when selecting that unit. This version is for * ASICs with a single timing register */ -static void __pmac +static void pmac_ide_selectproc(ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -579,7 +579,7 @@ pmac_ide_selectproc(ide_drive_t *drive) * timing register when selecting that unit. This version is for * ASICs with a dual timing register (Kauai) */ -static void __pmac +static void pmac_ide_kauai_selectproc(ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -600,7 +600,7 @@ pmac_ide_kauai_selectproc(ide_drive_t *drive) /* * Force an update of controller timing values for a given drive */ -static void __pmac +static void pmac_ide_do_update_timings(ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -633,7 +633,7 @@ pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port) * to sort that out sooner or later and see if I can finally get the * common version to work properly in all cases */ -static int __pmac +static int pmac_ide_do_setfeature(ide_drive_t *drive, u8 command) { ide_hwif_t *hwif = HWIF(drive); @@ -710,7 +710,7 @@ out: /* * Old tuning functions (called on hdparm -p), sets up drive PIO timings */ -static void __pmac +static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio) { ide_pio_data_t d; @@ -801,7 +801,7 @@ pmac_ide_tuneproc(ide_drive_t *drive, u8 pio) /* * Calculate KeyLargo ATA/66 UDMA timings */ -static int __pmac +static int set_timings_udma_ata4(u32 *timings, u8 speed) { unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks; @@ -829,7 +829,7 @@ set_timings_udma_ata4(u32 *timings, u8 speed) /* * Calculate Kauai ATA/100 UDMA timings */ -static int __pmac +static int set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) { struct ide_timing *t = ide_timing_find_mode(speed); @@ -849,7 +849,7 @@ set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed) /* * Calculate Shasta ATA/133 UDMA timings */ -static int __pmac +static int set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) { struct ide_timing *t = ide_timing_find_mode(speed); @@ -869,7 +869,7 @@ set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed) /* * Calculate MDMA timings for all cells */ -static int __pmac +static int set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, u8 speed, int drive_cycle_time) { @@ -1014,7 +1014,7 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, * our dedicated function is more precise as it uses the drive provided * cycle time value. We should probably fix this one to deal with that too... */ -static int __pmac +static int pmac_ide_tune_chipset (ide_drive_t *drive, byte speed) { int unit = (drive->select.b.unit & 0x01); @@ -1092,7 +1092,7 @@ pmac_ide_tune_chipset (ide_drive_t *drive, byte speed) * Blast some well known "safe" values to the timing registers at init or * wakeup from sleep time, before we do real calculation */ -static void __pmac +static void sanitize_timings(pmac_ide_hwif_t *pmif) { unsigned int value, value2 = 0; @@ -1123,13 +1123,13 @@ sanitize_timings(pmac_ide_hwif_t *pmif) pmif->timings[2] = pmif->timings[3] = value2; } -unsigned long __pmac +unsigned long pmac_ide_get_base(int index) { return pmac_ide[index].regbase; } -int __pmac +int pmac_ide_check_base(unsigned long base) { int ix; @@ -1140,7 +1140,7 @@ pmac_ide_check_base(unsigned long base) return -1; } -int __pmac +int pmac_ide_get_irq(unsigned long base) { int ix; @@ -1151,7 +1151,7 @@ pmac_ide_get_irq(unsigned long base) return 0; } -static int ide_majors[] __pmacdata = { 3, 22, 33, 34, 56, 57 }; +static int ide_majors[] = { 3, 22, 33, 34, 56, 57 }; dev_t __init pmac_find_ide_boot(char *bootdevice, int n) @@ -1701,7 +1701,7 @@ pmac_ide_probe(void) * pmac_ide_build_dmatable builds the DBDMA command list * for a transfer and sets the DBDMA channel to point to it. */ -static int __pmac +static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) { struct dbdma_cmd *table; @@ -1785,7 +1785,7 @@ pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq) } /* Teardown mappings after DMA has completed. */ -static void __pmac +static void pmac_ide_destroy_dmatable (ide_drive_t *drive) { ide_hwif_t *hwif = drive->hwif; @@ -1802,7 +1802,7 @@ pmac_ide_destroy_dmatable (ide_drive_t *drive) /* * Pick up best MDMA timing for the drive and apply it */ -static int __pmac +static int pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode) { ide_hwif_t *hwif = HWIF(drive); @@ -1859,7 +1859,7 @@ pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode) /* * Pick up best UDMA timing for the drive and apply it */ -static int __pmac +static int pmac_ide_udma_enable(ide_drive_t *drive, u16 mode) { ide_hwif_t *hwif = HWIF(drive); @@ -1915,7 +1915,7 @@ pmac_ide_udma_enable(ide_drive_t *drive, u16 mode) * Check what is the best DMA timing setting for the drive and * call appropriate functions to apply it. */ -static int __pmac +static int pmac_ide_dma_check(ide_drive_t *drive) { struct hd_driveid *id = drive->id; @@ -1967,7 +1967,7 @@ pmac_ide_dma_check(ide_drive_t *drive) * Prepare a DMA transfer. We build the DMA table, adjust the timings for * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion */ -static int __pmac +static int pmac_ide_dma_setup(ide_drive_t *drive) { ide_hwif_t *hwif = HWIF(drive); @@ -1997,7 +1997,7 @@ pmac_ide_dma_setup(ide_drive_t *drive) return 0; } -static void __pmac +static void pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) { /* issue cmd to drive */ @@ -2008,7 +2008,7 @@ pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command) * Kick the DMA controller into life after the DMA command has been issued * to the drive. */ -static void __pmac +static void pmac_ide_dma_start(ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -2024,7 +2024,7 @@ pmac_ide_dma_start(ide_drive_t *drive) /* * After a DMA transfer, make sure the controller is stopped */ -static int __pmac +static int pmac_ide_dma_end (ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -2052,7 +2052,7 @@ pmac_ide_dma_end (ide_drive_t *drive) * that's not implemented yet), on the other hand, we don't have shared interrupts * so it's not really a problem */ -static int __pmac +static int pmac_ide_dma_test_irq (ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; @@ -2108,19 +2108,19 @@ pmac_ide_dma_test_irq (ide_drive_t *drive) return 1; } -static int __pmac +static int pmac_ide_dma_host_off (ide_drive_t *drive) { return 0; } -static int __pmac +static int pmac_ide_dma_host_on (ide_drive_t *drive) { return 0; } -static int __pmac +static int pmac_ide_dma_lostirq (ide_drive_t *drive) { pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data; diff --git a/drivers/macintosh/ans-lcd.c b/drivers/macintosh/ans-lcd.c index 5e0811dc653..2b8a6e821d4 100644 --- a/drivers/macintosh/ans-lcd.c +++ b/drivers/macintosh/ans-lcd.c @@ -27,7 +27,7 @@ static volatile unsigned char __iomem *anslcd_ptr; #undef DEBUG -static void __pmac +static void anslcd_write_byte_ctrl ( unsigned char c ) { #ifdef DEBUG @@ -43,14 +43,14 @@ anslcd_write_byte_ctrl ( unsigned char c ) } } -static void __pmac +static void anslcd_write_byte_data ( unsigned char c ) { out_8(anslcd_ptr + ANSLCD_DATA_IX, c); udelay(anslcd_short_delay); } -static ssize_t __pmac +static ssize_t anslcd_write( struct file * file, const char __user * buf, size_t count, loff_t *ppos ) { @@ -73,7 +73,7 @@ anslcd_write( struct file * file, const char __user * buf, return p - buf; } -static int __pmac +static int anslcd_ioctl( struct inode * inode, struct file * file, unsigned int cmd, unsigned long arg ) { @@ -115,7 +115,7 @@ anslcd_ioctl( struct inode * inode, struct file * file, } } -static int __pmac +static int anslcd_open( struct inode * inode, struct file * file ) { return 0; diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c index c0712a1ea5a..b856bb67169 100644 --- a/drivers/macintosh/mediabay.c +++ b/drivers/macintosh/mediabay.c @@ -167,19 +167,19 @@ enum { * Functions for polling content of media bay */ -static u8 __pmac +static u8 ohare_mb_content(struct media_bay_info *bay) { return (MB_IN32(bay, OHARE_MBCR) >> 12) & 7; } -static u8 __pmac +static u8 heathrow_mb_content(struct media_bay_info *bay) { return (MB_IN32(bay, HEATHROW_MBCR) >> 12) & 7; } -static u8 __pmac +static u8 keylargo_mb_content(struct media_bay_info *bay) { int new_gpio; @@ -205,7 +205,7 @@ keylargo_mb_content(struct media_bay_info *bay) * into reset state as well */ -static void __pmac +static void ohare_mb_power(struct media_bay_info* bay, int on_off) { if (on_off) { @@ -224,7 +224,7 @@ ohare_mb_power(struct media_bay_info* bay, int on_off) MB_BIC(bay, OHARE_MBCR, 0x00000F00); } -static void __pmac +static void heathrow_mb_power(struct media_bay_info* bay, int on_off) { if (on_off) { @@ -243,7 +243,7 @@ heathrow_mb_power(struct media_bay_info* bay, int on_off) MB_BIC(bay, HEATHROW_MBCR, 0x00000F00); } -static void __pmac +static void keylargo_mb_power(struct media_bay_info* bay, int on_off) { if (on_off) { @@ -267,7 +267,7 @@ keylargo_mb_power(struct media_bay_info* bay, int on_off) * enable the related busses */ -static int __pmac +static int ohare_mb_setup_bus(struct media_bay_info* bay, u8 device_id) { switch(device_id) { @@ -287,7 +287,7 @@ ohare_mb_setup_bus(struct media_bay_info* bay, u8 device_id) return -ENODEV; } -static int __pmac +static int heathrow_mb_setup_bus(struct media_bay_info* bay, u8 device_id) { switch(device_id) { @@ -307,7 +307,7 @@ heathrow_mb_setup_bus(struct media_bay_info* bay, u8 device_id) return -ENODEV; } -static int __pmac +static int keylargo_mb_setup_bus(struct media_bay_info* bay, u8 device_id) { switch(device_id) { @@ -330,43 +330,43 @@ keylargo_mb_setup_bus(struct media_bay_info* bay, u8 device_id) * Functions for tweaking resets */ -static void __pmac +static void ohare_mb_un_reset(struct media_bay_info* bay) { MB_BIS(bay, OHARE_FCR, OH_BAY_RESET_N); } -static void __pmac keylargo_mb_init(struct media_bay_info *bay) +static void keylargo_mb_init(struct media_bay_info *bay) { MB_BIS(bay, KEYLARGO_MBCR, KL_MBCR_MB0_ENABLE); } -static void __pmac heathrow_mb_un_reset(struct media_bay_info* bay) +static void heathrow_mb_un_reset(struct media_bay_info* bay) { MB_BIS(bay, HEATHROW_FCR, HRW_BAY_RESET_N); } -static void __pmac keylargo_mb_un_reset(struct media_bay_info* bay) +static void keylargo_mb_un_reset(struct media_bay_info* bay) { MB_BIS(bay, KEYLARGO_MBCR, KL_MBCR_MB0_DEV_RESET); } -static void __pmac ohare_mb_un_reset_ide(struct media_bay_info* bay) +static void ohare_mb_un_reset_ide(struct media_bay_info* bay) { MB_BIS(bay, OHARE_FCR, OH_IDE1_RESET_N); } -static void __pmac heathrow_mb_un_reset_ide(struct media_bay_info* bay) +static void heathrow_mb_un_reset_ide(struct media_bay_info* bay) { MB_BIS(bay, HEATHROW_FCR, HRW_IDE1_RESET_N); } -static void __pmac keylargo_mb_un_reset_ide(struct media_bay_info* bay) +static void keylargo_mb_un_reset_ide(struct media_bay_info* bay) { MB_BIS(bay, KEYLARGO_FCR1, KL1_EIDE0_RESET_N); } -static inline void __pmac set_mb_power(struct media_bay_info* bay, int onoff) +static inline void set_mb_power(struct media_bay_info* bay, int onoff) { /* Power up up and assert the bay reset line */ if (onoff) { @@ -382,7 +382,7 @@ static inline void __pmac set_mb_power(struct media_bay_info* bay, int onoff) bay->timer = msecs_to_jiffies(MB_POWER_DELAY); } -static void __pmac poll_media_bay(struct media_bay_info* bay) +static void poll_media_bay(struct media_bay_info* bay) { int id = bay->ops->content(bay); @@ -415,7 +415,7 @@ static void __pmac poll_media_bay(struct media_bay_info* bay) } } -int __pmac check_media_bay(struct device_node *which_bay, int what) +int check_media_bay(struct device_node *which_bay, int what) { #ifdef CONFIG_BLK_DEV_IDE int i; @@ -432,7 +432,7 @@ int __pmac check_media_bay(struct device_node *which_bay, int what) } EXPORT_SYMBOL(check_media_bay); -int __pmac check_media_bay_by_base(unsigned long base, int what) +int check_media_bay_by_base(unsigned long base, int what) { #ifdef CONFIG_BLK_DEV_IDE int i; @@ -449,7 +449,7 @@ int __pmac check_media_bay_by_base(unsigned long base, int what) return -ENODEV; } -int __pmac media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base, +int media_bay_set_ide_infos(struct device_node* which_bay, unsigned long base, int irq, int index) { #ifdef CONFIG_BLK_DEV_IDE @@ -489,7 +489,7 @@ int __pmac media_bay_set_ide_infos(struct device_node* which_bay, unsigned long return -ENODEV; } -static void __pmac media_bay_step(int i) +static void media_bay_step(int i) { struct media_bay_info* bay = &media_bays[i]; @@ -619,7 +619,7 @@ static void __pmac media_bay_step(int i) * with the IDE driver. It needs to be a thread because * ide_register can't be called from interrupt context. */ -static int __pmac media_bay_task(void *x) +static int media_bay_task(void *x) { int i; @@ -704,7 +704,7 @@ static int __devinit media_bay_attach(struct macio_dev *mdev, const struct of_de } -static int __pmac media_bay_suspend(struct macio_dev *mdev, pm_message_t state) +static int media_bay_suspend(struct macio_dev *mdev, pm_message_t state) { struct media_bay_info *bay = macio_get_drvdata(mdev); @@ -719,7 +719,7 @@ static int __pmac media_bay_suspend(struct macio_dev *mdev, pm_message_t state) return 0; } -static int __pmac media_bay_resume(struct macio_dev *mdev) +static int media_bay_resume(struct macio_dev *mdev) { struct media_bay_info *bay = macio_get_drvdata(mdev); @@ -760,7 +760,7 @@ static int __pmac media_bay_resume(struct macio_dev *mdev) /* Definitions of "ops" structures. */ -static struct mb_ops ohare_mb_ops __pmacdata = { +static struct mb_ops ohare_mb_ops = { .name = "Ohare", .content = ohare_mb_content, .power = ohare_mb_power, @@ -769,7 +769,7 @@ static struct mb_ops ohare_mb_ops __pmacdata = { .un_reset_ide = ohare_mb_un_reset_ide, }; -static struct mb_ops heathrow_mb_ops __pmacdata = { +static struct mb_ops heathrow_mb_ops = { .name = "Heathrow", .content = heathrow_mb_content, .power = heathrow_mb_power, @@ -778,7 +778,7 @@ static struct mb_ops heathrow_mb_ops __pmacdata = { .un_reset_ide = heathrow_mb_un_reset_ide, }; -static struct mb_ops keylargo_mb_ops __pmacdata = { +static struct mb_ops keylargo_mb_ops = { .name = "KeyLargo", .init = keylargo_mb_init, .content = keylargo_mb_content, diff --git a/drivers/macintosh/via-cuda.c b/drivers/macintosh/via-cuda.c index 417deb5de10..d843a6c9c6d 100644 --- a/drivers/macintosh/via-cuda.c +++ b/drivers/macintosh/via-cuda.c @@ -37,7 +37,6 @@ static DEFINE_SPINLOCK(cuda_lock); #ifdef CONFIG_MAC #define CUDA_IRQ IRQ_MAC_ADB -#define __openfirmware #define eieio() #else #define CUDA_IRQ vias->intrs[0].line diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c index 645a2e5c70a..76719451e38 100644 --- a/drivers/macintosh/via-pmu.c +++ b/drivers/macintosh/via-pmu.c @@ -244,7 +244,7 @@ int pmu_wink(struct adb_request *req); * - the number of response bytes which the PMU will return, or * -1 if it will send a length byte. */ -static const s8 pmu_data_len[256][2] __openfirmwaredata = { +static const s8 pmu_data_len[256][2] = { /* 0 1 2 3 4 5 6 7 */ /*00*/ {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0}, /*08*/ {-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1},{-1,-1}, @@ -295,7 +295,7 @@ static struct backlight_controller pmu_backlight_controller = { }; #endif /* CONFIG_PMAC_BACKLIGHT */ -int __openfirmware +int find_via_pmu(void) { if (via != 0) @@ -374,7 +374,7 @@ find_via_pmu(void) } #ifdef CONFIG_ADB -static int __openfirmware +static int pmu_probe(void) { return vias == NULL? -ENODEV: 0; @@ -520,7 +520,7 @@ static int __init via_pmu_dev_init(void) device_initcall(via_pmu_dev_init); -static int __openfirmware +static int init_pmu(void) { int timeout; @@ -625,7 +625,7 @@ static void pmu_set_server_mode(int server_mode) /* This new version of the code for 2400/3400/3500 powerbooks * is inspired from the implementation in gkrellm-pmu */ -static void __pmac +static void done_battery_state_ohare(struct adb_request* req) { /* format: @@ -713,7 +713,7 @@ done_battery_state_ohare(struct adb_request* req) clear_bit(0, &async_req_locks); } -static void __pmac +static void done_battery_state_smart(struct adb_request* req) { /* format: @@ -791,7 +791,7 @@ done_battery_state_smart(struct adb_request* req) clear_bit(0, &async_req_locks); } -static void __pmac +static void query_battery_state(void) { if (test_and_set_bit(0, &async_req_locks)) @@ -804,7 +804,7 @@ query_battery_state(void) 2, PMU_SMART_BATTERY_STATE, pmu_cur_battery+1); } -static int __pmac +static int proc_get_info(char *page, char **start, off_t off, int count, int *eof, void *data) { @@ -819,7 +819,7 @@ proc_get_info(char *page, char **start, off_t off, return p - page; } -static int __pmac +static int proc_get_irqstats(char *page, char **start, off_t off, int count, int *eof, void *data) { @@ -846,7 +846,7 @@ proc_get_irqstats(char *page, char **start, off_t off, return p - page; } -static int __pmac +static int proc_get_batt(char *page, char **start, off_t off, int count, int *eof, void *data) { @@ -870,7 +870,7 @@ proc_get_batt(char *page, char **start, off_t off, return p - page; } -static int __pmac +static int proc_read_options(char *page, char **start, off_t off, int count, int *eof, void *data) { @@ -887,7 +887,7 @@ proc_read_options(char *page, char **start, off_t off, return p - page; } -static int __pmac +static int proc_write_options(struct file *file, const char __user *buffer, unsigned long count, void *data) { @@ -934,7 +934,7 @@ proc_write_options(struct file *file, const char __user *buffer, #ifdef CONFIG_ADB /* Send an ADB command */ -static int __pmac +static int pmu_send_request(struct adb_request *req, int sync) { int i, ret; @@ -1014,7 +1014,7 @@ pmu_send_request(struct adb_request *req, int sync) } /* Enable/disable autopolling */ -static int __pmac +static int pmu_adb_autopoll(int devs) { struct adb_request req; @@ -1037,7 +1037,7 @@ pmu_adb_autopoll(int devs) } /* Reset the ADB bus */ -static int __pmac +static int pmu_adb_reset_bus(void) { struct adb_request req; @@ -1072,7 +1072,7 @@ pmu_adb_reset_bus(void) #endif /* CONFIG_ADB */ /* Construct and send a pmu request */ -int __openfirmware +int pmu_request(struct adb_request *req, void (*done)(struct adb_request *), int nbytes, ...) { @@ -1098,7 +1098,7 @@ pmu_request(struct adb_request *req, void (*done)(struct adb_request *), return pmu_queue_request(req); } -int __pmac +int pmu_queue_request(struct adb_request *req) { unsigned long flags; @@ -1190,7 +1190,7 @@ pmu_done(struct adb_request *req) (*done)(req); } -static void __pmac +static void pmu_start(void) { struct adb_request *req; @@ -1214,7 +1214,7 @@ pmu_start(void) send_byte(req->data[0]); } -void __openfirmware +void pmu_poll(void) { if (!via) @@ -1224,7 +1224,7 @@ pmu_poll(void) via_pmu_interrupt(0, NULL, NULL); } -void __openfirmware +void pmu_poll_adb(void) { if (!via) @@ -1239,7 +1239,7 @@ pmu_poll_adb(void) || req_awaiting_reply)); } -void __openfirmware +void pmu_wait_complete(struct adb_request *req) { if (!via) @@ -1253,7 +1253,7 @@ pmu_wait_complete(struct adb_request *req) * This is done to avoid spurrious shutdowns when we know we'll have * interrupts switched off for a long time */ -void __openfirmware +void pmu_suspend(void) { unsigned long flags; @@ -1293,7 +1293,7 @@ pmu_suspend(void) } while (1); } -void __openfirmware +void pmu_resume(void) { unsigned long flags; @@ -1323,7 +1323,7 @@ pmu_resume(void) } /* Interrupt data could be the result data from an ADB cmd */ -static void __pmac +static void pmu_handle_data(unsigned char *data, int len, struct pt_regs *regs) { unsigned char ints, pirq; @@ -1435,7 +1435,7 @@ next: goto next; } -static struct adb_request* __pmac +static struct adb_request* pmu_sr_intr(struct pt_regs *regs) { struct adb_request *req; @@ -1541,7 +1541,7 @@ pmu_sr_intr(struct pt_regs *regs) return NULL; } -static irqreturn_t __pmac +static irqreturn_t via_pmu_interrupt(int irq, void *arg, struct pt_regs *regs) { unsigned long flags; @@ -1629,7 +1629,7 @@ no_free_slot: return IRQ_RETVAL(handled); } -void __pmac +void pmu_unlock(void) { unsigned long flags; @@ -1642,7 +1642,7 @@ pmu_unlock(void) } -static irqreturn_t __pmac +static irqreturn_t gpio1_interrupt(int irq, void *arg, struct pt_regs *regs) { unsigned long flags; @@ -1663,12 +1663,12 @@ gpio1_interrupt(int irq, void *arg, struct pt_regs *regs) } #ifdef CONFIG_PMAC_BACKLIGHT -static int backlight_to_bright[] __pmacdata = { +static int backlight_to_bright[] = { 0x7f, 0x46, 0x42, 0x3e, 0x3a, 0x36, 0x32, 0x2e, 0x2a, 0x26, 0x22, 0x1e, 0x1a, 0x16, 0x12, 0x0e }; -static int __openfirmware +static int pmu_set_backlight_enable(int on, int level, void* data) { struct adb_request req; @@ -1688,7 +1688,7 @@ pmu_set_backlight_enable(int on, int level, void* data) return 0; } -static void __openfirmware +static void pmu_bright_complete(struct adb_request *req) { if (req == &bright_req_1) @@ -1697,7 +1697,7 @@ pmu_bright_complete(struct adb_request *req) clear_bit(2, &async_req_locks); } -static int __openfirmware +static int pmu_set_backlight_level(int level, void* data) { if (vias == NULL) @@ -1717,7 +1717,7 @@ pmu_set_backlight_level(int level, void* data) } #endif /* CONFIG_PMAC_BACKLIGHT */ -void __pmac +void pmu_enable_irled(int on) { struct adb_request req; @@ -1732,7 +1732,7 @@ pmu_enable_irled(int on) pmu_wait_complete(&req); } -void __pmac +void pmu_restart(void) { struct adb_request req; @@ -1757,7 +1757,7 @@ pmu_restart(void) ; } -void __pmac +void pmu_shutdown(void) { struct adb_request req; @@ -2076,7 +2076,7 @@ pmu_unregister_sleep_notifier(struct pmu_sleep_notifier* n) } /* Sleep is broadcast last-to-first */ -static int __pmac +static int broadcast_sleep(int when, int fallback) { int ret = PBOOK_SLEEP_OK; @@ -2101,7 +2101,7 @@ broadcast_sleep(int when, int fallback) } /* Wake is broadcast first-to-last */ -static int __pmac +static int broadcast_wake(void) { int ret = PBOOK_SLEEP_OK; @@ -2132,7 +2132,7 @@ static struct pci_save { } *pbook_pci_saves; static int pbook_npci_saves; -static void __pmac +static void pbook_alloc_pci_save(void) { int npci; @@ -2149,7 +2149,7 @@ pbook_alloc_pci_save(void) pbook_npci_saves = npci; } -static void __pmac +static void pbook_free_pci_save(void) { if (pbook_pci_saves == NULL) @@ -2159,7 +2159,7 @@ pbook_free_pci_save(void) pbook_npci_saves = 0; } -static void __pmac +static void pbook_pci_save(void) { struct pci_save *ps = pbook_pci_saves; @@ -2190,7 +2190,7 @@ pbook_pci_save(void) * during boot, it will be in the pci dev list. If it's disabled at this point * (and it will probably be), then you can't access it's config space. */ -static void __pmac +static void pbook_pci_restore(void) { u16 cmd; @@ -2238,7 +2238,7 @@ pbook_pci_restore(void) #ifdef DEBUG_SLEEP /* N.B. This doesn't work on the 3400 */ -void __pmac +void pmu_blink(int n) { struct adb_request req; @@ -2277,9 +2277,9 @@ pmu_blink(int n) * Put the powerbook to sleep. */ -static u32 save_via[8] __pmacdata; +static u32 save_via[8]; -static void __pmac +static void save_via_state(void) { save_via[0] = in_8(&via[ANH]); @@ -2291,7 +2291,7 @@ save_via_state(void) save_via[6] = in_8(&via[T1CL]); save_via[7] = in_8(&via[T1CH]); } -static void __pmac +static void restore_via_state(void) { out_8(&via[ANH], save_via[0]); @@ -2307,7 +2307,7 @@ restore_via_state(void) out_8(&via[IER], IER_SET | SR_INT | CB1_INT); } -static int __pmac +static int pmac_suspend_devices(void) { int ret; @@ -2397,7 +2397,7 @@ pmac_suspend_devices(void) return 0; } -static int __pmac +static int pmac_wakeup_devices(void) { mdelay(100); @@ -2436,7 +2436,7 @@ pmac_wakeup_devices(void) #define GRACKLE_NAP (1<<4) #define GRACKLE_SLEEP (1<<3) -int __pmac +int powerbook_sleep_grackle(void) { unsigned long save_l2cr; @@ -2520,7 +2520,7 @@ powerbook_sleep_grackle(void) return 0; } -static int __pmac +static int powerbook_sleep_Core99(void) { unsigned long save_l2cr; @@ -2620,7 +2620,7 @@ powerbook_sleep_Core99(void) #define PB3400_MEM_CTRL 0xf8000000 #define PB3400_MEM_CTRL_SLEEP 0x70 -static int __pmac +static int powerbook_sleep_3400(void) { int ret, i, x; @@ -2720,9 +2720,9 @@ struct pmu_private { }; static LIST_HEAD(all_pmu_pvt); -static DEFINE_SPINLOCK(all_pvt_lock __pmacdata); +static DEFINE_SPINLOCK(all_pvt_lock); -static void __pmac +static void pmu_pass_intr(unsigned char *data, int len) { struct pmu_private *pp; @@ -2751,7 +2751,7 @@ pmu_pass_intr(unsigned char *data, int len) spin_unlock_irqrestore(&all_pvt_lock, flags); } -static int __pmac +static int pmu_open(struct inode *inode, struct file *file) { struct pmu_private *pp; @@ -2773,7 +2773,7 @@ pmu_open(struct inode *inode, struct file *file) return 0; } -static ssize_t __pmac +static ssize_t pmu_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { @@ -2825,14 +2825,14 @@ pmu_read(struct file *file, char __user *buf, return ret; } -static ssize_t __pmac +static ssize_t pmu_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { return 0; } -static unsigned int __pmac +static unsigned int pmu_fpoll(struct file *filp, poll_table *wait) { struct pmu_private *pp = filp->private_data; @@ -2849,7 +2849,7 @@ pmu_fpoll(struct file *filp, poll_table *wait) return mask; } -static int __pmac +static int pmu_release(struct inode *inode, struct file *file) { struct pmu_private *pp = file->private_data; @@ -2874,8 +2874,7 @@ pmu_release(struct inode *inode, struct file *file) return 0; } -/* Note: removed __openfirmware here since it causes link errors */ -static int __pmac +static int pmu_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) { @@ -2957,7 +2956,7 @@ pmu_ioctl(struct inode * inode, struct file *filp, return error; } -static struct file_operations pmu_device_fops __pmacdata = { +static struct file_operations pmu_device_fops = { .read = pmu_read, .write = pmu_write, .poll = pmu_fpoll, @@ -2966,7 +2965,7 @@ static struct file_operations pmu_device_fops __pmacdata = { .release = pmu_release, }; -static struct miscdevice pmu_device __pmacdata = { +static struct miscdevice pmu_device = { PMU_MINOR, "pmu", &pmu_device_fops }; @@ -2982,7 +2981,7 @@ device_initcall(pmu_device_init); #ifdef DEBUG_SLEEP -static inline void __pmac +static inline void polled_handshake(volatile unsigned char __iomem *via) { via[B] &= ~TREQ; eieio(); @@ -2993,7 +2992,7 @@ polled_handshake(volatile unsigned char __iomem *via) ; } -static inline void __pmac +static inline void polled_send_byte(volatile unsigned char __iomem *via, int x) { via[ACR] |= SR_OUT | SR_EXT; eieio(); @@ -3001,7 +3000,7 @@ polled_send_byte(volatile unsigned char __iomem *via, int x) polled_handshake(via); } -static inline int __pmac +static inline int polled_recv_byte(volatile unsigned char __iomem *via) { int x; @@ -3013,7 +3012,7 @@ polled_recv_byte(volatile unsigned char __iomem *via) return x; } -int __pmac +int pmu_polled_request(struct adb_request *req) { unsigned long flags; diff --git a/drivers/macintosh/via-pmu68k.c b/drivers/macintosh/via-pmu68k.c index 820dc52e30b..6f80d76ac17 100644 --- a/drivers/macintosh/via-pmu68k.c +++ b/drivers/macintosh/via-pmu68k.c @@ -835,7 +835,7 @@ static struct pci_save { } *pbook_pci_saves; static int n_pbook_pci_saves; -static inline void __openfirmware +static inline void pbook_pci_save(void) { int npci; @@ -863,7 +863,7 @@ pbook_pci_save(void) } } -static inline void __openfirmware +static inline void pbook_pci_restore(void) { u16 cmd; @@ -902,7 +902,7 @@ pbook_pci_restore(void) #define IRQ_ENABLE ((unsigned int *)0xf3000024) #define MEM_CTRL ((unsigned int *)0xf8000070) -int __openfirmware powerbook_sleep(void) +int powerbook_sleep(void) { int ret, i, x; static int save_backlight; @@ -1001,25 +1001,24 @@ int __openfirmware powerbook_sleep(void) /* * Support for /dev/pmu device */ -static int __openfirmware pmu_open(struct inode *inode, struct file *file) +static int pmu_open(struct inode *inode, struct file *file) { return 0; } -static ssize_t __openfirmware pmu_read(struct file *file, char *buf, +static ssize_t pmu_read(struct file *file, char *buf, size_t count, loff_t *ppos) { return 0; } -static ssize_t __openfirmware pmu_write(struct file *file, const char *buf, +static ssize_t pmu_write(struct file *file, const char *buf, size_t count, loff_t *ppos) { return 0; } -/* Note: removed __openfirmware here since it causes link errors */ -static int /*__openfirmware*/ pmu_ioctl(struct inode * inode, struct file *filp, +static int pmu_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) { int error; -- cgit v1.2.3-70-g09d2 From 99a2657a29e2d623c3568cd86b27cac13fb63140 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 25 Sep 2005 13:25:41 +1000 Subject: drm: use kernel macros Make some of the DRM_ macros use the real kernel macros. Signed-off-by: Dave Airlie --- drivers/char/drm/drmP.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h index cf58a526a03..79221783a14 100644 --- a/drivers/char/drm/drmP.h +++ b/drivers/char/drm/drmP.h @@ -228,9 +228,9 @@ /** \name Internal types and structures */ /*@{*/ -#define DRM_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) -#define DRM_MIN(a,b) ((a)<(b)?(a):(b)) -#define DRM_MAX(a,b) ((a)>(b)?(a):(b)) +#define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x) +#define DRM_MIN(a,b) min(a,b) +#define DRM_MAX(a,b) max(a,b) #define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1)) #define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x)) -- cgit v1.2.3-70-g09d2 From b5e89ed53ed8d24f83ba1941c07382af00ed238e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 25 Sep 2005 14:28:13 +1000 Subject: drm: lindent the drm directory. I've been threatening this for a while, so no point hanging around. This lindents the DRM code which was always really bad in tabbing department. I've also fixed some misnamed files in comments and removed some trailing whitespace. Signed-off-by: Dave Airlie --- drivers/char/drm/ati_pcigart.c | 123 +- drivers/char/drm/drm.h | 295 +- drivers/char/drm/drmP.h | 863 +- drivers/char/drm/drm_agpsupport.c | 150 +- drivers/char/drm/drm_auth.c | 68 +- drivers/char/drm/drm_bufs.c | 883 +- drivers/char/drm/drm_context.c | 304 +- drivers/char/drm/drm_dma.c | 87 +- drivers/char/drm/drm_drawable.c | 8 +- drivers/char/drm/drm_drv.c | 361 +- drivers/char/drm/drm_fops.c | 293 +- drivers/char/drm/drm_init.c | 7 +- drivers/char/drm/drm_ioc32.c | 225 +- drivers/char/drm/drm_ioctl.c | 168 +- drivers/char/drm/drm_irq.c | 169 +- drivers/char/drm/drm_lock.c | 177 +- drivers/char/drm/drm_memory.c | 54 +- drivers/char/drm/drm_memory.h | 73 +- drivers/char/drm/drm_memory_debug.h | 224 +- drivers/char/drm/drm_os_linux.h | 17 +- drivers/char/drm/drm_pci.c | 10 +- drivers/char/drm/drm_pciids.h | 1 - drivers/char/drm/drm_proc.c | 272 +- drivers/char/drm/drm_sarea.h | 30 +- drivers/char/drm/drm_scatter.c | 183 +- drivers/char/drm/drm_stub.c | 112 +- drivers/char/drm/drm_vm.c | 369 +- drivers/char/drm/ffb_context.c | 230 +- drivers/char/drm/ffb_drv.c | 139 +- drivers/char/drm/ffb_drv.h | 433 +- drivers/char/drm/i810_dma.c | 1101 ++- drivers/char/drm/i810_drm.h | 75 +- drivers/char/drm/i810_drv.c | 60 +- drivers/char/drm/i810_drv.h | 38 +- drivers/char/drm/i830_dma.c | 1328 ++- drivers/char/drm/i830_drm.h | 90 +- drivers/char/drm/i830_drv.c | 59 +- drivers/char/drm/i830_drv.h | 67 +- drivers/char/drm/i830_irq.c | 137 +- drivers/char/drm/i915_dma.c | 65 +- drivers/char/drm/i915_drv.c | 61 +- drivers/char/drm/i915_drv.h | 13 +- drivers/char/drm/i915_ioc32.c | 64 +- drivers/char/drm/i915_mem.c | 8 +- drivers/char/drm/mga_dma.c | 511 +- drivers/char/drm/mga_drm.h | 142 +- drivers/char/drm/mga_drv.c | 75 +- drivers/char/drm/mga_drv.h | 42 +- drivers/char/drm/mga_ioc32.c | 60 +- drivers/char/drm/mga_irq.c | 42 +- drivers/char/drm/mga_state.c | 894 +- drivers/char/drm/mga_ucode.h | 16070 +++++++++++++++++----------------- drivers/char/drm/mga_warp.c | 120 +- drivers/char/drm/r128_cce.c | 590 +- drivers/char/drm/r128_drm.h | 32 +- drivers/char/drm/r128_drv.c | 60 +- drivers/char/drm/r128_drv.h | 67 +- drivers/char/drm/r128_ioc32.c | 35 +- drivers/char/drm/r128_irq.c | 53 +- drivers/char/drm/r128_state.c | 1386 ++- drivers/char/drm/r300_cmdbuf.c | 502 +- drivers/char/drm/r300_reg.h | 192 +- drivers/char/drm/radeon_cp.c | 2480 +++--- drivers/char/drm/radeon_drm.h | 276 +- drivers/char/drm/radeon_drv.c | 61 +- drivers/char/drm/radeon_drv.h | 149 +- drivers/char/drm/radeon_ioc32.c | 51 +- drivers/char/drm/radeon_irq.c | 127 +- drivers/char/drm/radeon_mem.c | 148 +- drivers/char/drm/radeon_state.c | 2493 +++--- drivers/char/drm/savage_bci.c | 201 +- drivers/char/drm/savage_drm.h | 53 +- drivers/char/drm/savage_drv.c | 56 +- drivers/char/drm/savage_drv.h | 58 +- drivers/char/drm/savage_state.c | 483 +- drivers/char/drm/sis_drm.h | 2 +- drivers/char/drm/sis_drv.c | 58 +- drivers/char/drm/sis_drv.h | 10 +- drivers/char/drm/sis_ds.c | 82 +- drivers/char/drm/sis_ds.h | 40 +- drivers/char/drm/sis_mm.c | 132 +- drivers/char/drm/tdfx_drv.c | 52 +- drivers/char/drm/via_3d_reg.h | 1 - drivers/char/drm/via_dma.c | 259 +- drivers/char/drm/via_drm.h | 4 +- drivers/char/drm/via_drv.c | 22 +- drivers/char/drm/via_drv.h | 21 +- drivers/char/drm/via_irq.c | 106 +- drivers/char/drm/via_map.c | 4 +- drivers/char/drm/via_mm.c | 17 +- drivers/char/drm/via_verifier.c | 483 +- drivers/char/drm/via_verifier.h | 22 +- drivers/char/drm/via_video.c | 30 +- 93 files changed, 19197 insertions(+), 19151 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c index 957596c6393..d07ce96e9f4 100644 --- a/drivers/char/drm/ati_pcigart.c +++ b/drivers/char/drm/ati_pcigart.c @@ -1,5 +1,5 @@ /** - * \file ati_pcigart.h + * \file ati_pcigart.c * ATI PCI GART support * * \author Gareth Hughes @@ -52,87 +52,91 @@ # define ATI_MAX_PCIGART_PAGES 8192 /**< 32 MB aperture, 4K pages */ # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ -static unsigned long drm_ati_alloc_pcigart_table( void ) +static unsigned long drm_ati_alloc_pcigart_table(void) { unsigned long address; struct page *page; int i; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - address = __get_free_pages( GFP_KERNEL, ATI_PCIGART_TABLE_ORDER ); - if ( address == 0UL ) { + address = __get_free_pages(GFP_KERNEL, ATI_PCIGART_TABLE_ORDER); + if (address == 0UL) { return 0; } - page = virt_to_page( address ); + page = virt_to_page(address); - for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) { get_page(page); - SetPageReserved( page ); + SetPageReserved(page); } - DRM_DEBUG( "%s: returning 0x%08lx\n", __FUNCTION__, address ); + DRM_DEBUG("%s: returning 0x%08lx\n", __FUNCTION__, address); return address; } -static void drm_ati_free_pcigart_table( unsigned long address ) +static void drm_ati_free_pcigart_table(unsigned long address) { struct page *page; int i; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - page = virt_to_page( address ); + page = virt_to_page(address); - for ( i = 0 ; i < ATI_PCIGART_TABLE_PAGES ; i++, page++ ) { + for (i = 0; i < ATI_PCIGART_TABLE_PAGES; i++, page++) { __put_page(page); - ClearPageReserved( page ); + ClearPageReserved(page); } - free_pages( address, ATI_PCIGART_TABLE_ORDER ); + free_pages(address, ATI_PCIGART_TABLE_ORDER); } -int drm_ati_pcigart_cleanup(drm_device_t *dev, drm_ati_pcigart_info *gart_info) +int drm_ati_pcigart_cleanup(drm_device_t * dev, + drm_ati_pcigart_info * gart_info) { drm_sg_mem_t *entry = dev->sg; unsigned long pages; int i; /* we need to support large memory configurations */ - if ( !entry ) { - DRM_ERROR( "no scatter/gather memory!\n" ); + if (!entry) { + DRM_ERROR("no scatter/gather memory!\n"); return 0; } if (gart_info->bus_addr) { - if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) { + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { pci_unmap_single(dev->pdev, gart_info->bus_addr, ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, PCI_DMA_TODEVICE); } - pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) - ? entry->pages : ATI_MAX_PCIGART_PAGES; + pages = (entry->pages <= ATI_MAX_PCIGART_PAGES) + ? entry->pages : ATI_MAX_PCIGART_PAGES; - for ( i = 0 ; i < pages ; i++ ) { - if ( !entry->busaddr[i] ) break; + for (i = 0; i < pages; i++) { + if (!entry->busaddr[i]) + break; pci_unmap_single(dev->pdev, entry->busaddr[i], PAGE_SIZE, PCI_DMA_TODEVICE); } - - if (gart_info->gart_table_location==DRM_ATI_GART_MAIN) - gart_info->bus_addr=0; + + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) + gart_info->bus_addr = 0; } - if (gart_info->gart_table_location==DRM_ATI_GART_MAIN && gart_info->addr) { + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN + && gart_info->addr) { drm_ati_free_pcigart_table(gart_info->addr); - gart_info->addr=0; + gart_info->addr = 0; } return 1; } + EXPORT_SYMBOL(drm_ati_pcigart_cleanup); -int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) +int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info * gart_info) { drm_sg_mem_t *entry = dev->sg; unsigned long address = 0; @@ -140,58 +144,56 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) u32 *pci_gart, page_base, bus_address = 0; int i, j, ret = 0; - if ( !entry ) { - DRM_ERROR( "no scatter/gather memory!\n" ); + if (!entry) { + DRM_ERROR("no scatter/gather memory!\n"); goto done; } - if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) - { + if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); - + address = drm_ati_alloc_pcigart_table(); - if ( !address ) { - DRM_ERROR( "cannot allocate PCI GART page!\n" ); + if (!address) { + DRM_ERROR("cannot allocate PCI GART page!\n"); goto done; } - - if ( !dev->pdev ) { - DRM_ERROR( "PCI device unknown!\n" ); + + if (!dev->pdev) { + DRM_ERROR("PCI device unknown!\n"); goto done; } bus_address = pci_map_single(dev->pdev, (void *)address, - ATI_PCIGART_TABLE_PAGES * PAGE_SIZE, - PCI_DMA_TODEVICE); + ATI_PCIGART_TABLE_PAGES * + PAGE_SIZE, PCI_DMA_TODEVICE); if (bus_address == 0) { - DRM_ERROR( "unable to map PCIGART pages!\n" ); - drm_ati_free_pcigart_table( address ); + DRM_ERROR("unable to map PCIGART pages!\n"); + drm_ati_free_pcigart_table(address); address = 0; goto done; } - } - else - { + } else { address = gart_info->addr; bus_address = gart_info->bus_addr; - DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", bus_address, address); + DRM_DEBUG("PCI: Gart Table: VRAM %08X mapped at %08lX\n", + bus_address, address); } - pci_gart = (u32 *)address; + pci_gart = (u32 *) address; - pages = ( entry->pages <= ATI_MAX_PCIGART_PAGES ) - ? entry->pages : ATI_MAX_PCIGART_PAGES; + pages = (entry->pages <= ATI_MAX_PCIGART_PAGES) + ? entry->pages : ATI_MAX_PCIGART_PAGES; - memset( pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32) ); + memset(pci_gart, 0, ATI_MAX_PCIGART_PAGES * sizeof(u32)); - for ( i = 0 ; i < pages ; i++ ) { + for (i = 0; i < pages; i++) { /* we need to support large memory configurations */ entry->busaddr[i] = pci_map_single(dev->pdev, - page_address( entry->pagelist[i] ), - PAGE_SIZE, - PCI_DMA_TODEVICE); + page_address(entry-> + pagelist[i]), + PAGE_SIZE, PCI_DMA_TODEVICE); if (entry->busaddr[i] == 0) { - DRM_ERROR( "unable to map PCIGART pages!\n" ); + DRM_ERROR("unable to map PCIGART pages!\n"); drm_ati_pcigart_cleanup(dev, gart_info); address = 0; bus_address = 0; @@ -201,9 +203,9 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { if (gart_info->is_pcie) - *pci_gart = (cpu_to_le32(page_base)>>8) | 0xc; + *pci_gart = (cpu_to_le32(page_base) >> 8) | 0xc; else - *pci_gart++ = cpu_to_le32( page_base ); + *pci_gart++ = cpu_to_le32(page_base); page_base += ATI_PCIGART_PAGE_SIZE; } } @@ -216,9 +218,10 @@ int drm_ati_pcigart_init(drm_device_t *dev, drm_ati_pcigart_info *gart_info) mb(); #endif -done: + done: gart_info->addr = address; - gart_info->bus_addr = bus_address; + gart_info->bus_addr = bus_address; return ret; } + EXPORT_SYMBOL(drm_ati_pcigart_init); diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h index fc6598a81ac..64d6237fdd0 100644 --- a/drivers/char/drm/drm.h +++ b/drivers/char/drm/drm.h @@ -1,7 +1,7 @@ /** - * \file drm.h + * \file drm.h * Header for the Direct Rendering Manager - * + * * \author Rickard E. (Rik) Faith * * \par Acknowledgments: @@ -33,7 +33,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ - #ifndef _DRM_H_ #define _DRM_H_ @@ -56,7 +55,7 @@ #define ioctl(a,b,c) xf86ioctl(a,b,c) #else #include -#endif /* __FreeBSD__ && xf86ioctl */ +#endif /* __FreeBSD__ && xf86ioctl */ #define DRM_IOCTL_NR(n) ((n) & 0xff) #define DRM_IOC_VOID IOC_VOID #define DRM_IOC_READ IOC_OUT @@ -97,16 +96,14 @@ #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) - -typedef unsigned int drm_handle_t; -typedef unsigned int drm_context_t; -typedef unsigned int drm_drawable_t; -typedef unsigned int drm_magic_t; - +typedef unsigned int drm_handle_t; +typedef unsigned int drm_context_t; +typedef unsigned int drm_drawable_t; +typedef unsigned int drm_magic_t; /** * Cliprect. - * + * * \warning: If you change this structure, make sure you change * XF86DRIClipRectRec in the server as well * @@ -114,22 +111,21 @@ typedef unsigned int drm_magic_t; * backwards-compatibility reasons. */ typedef struct drm_clip_rect { - unsigned short x1; - unsigned short y1; - unsigned short x2; - unsigned short y2; + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; } drm_clip_rect_t; - /** * Texture region, */ typedef struct drm_tex_region { - unsigned char next; - unsigned char prev; - unsigned char in_use; - unsigned char padding; - unsigned int age; + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; + unsigned int age; } drm_tex_region_t; /** @@ -141,28 +137,26 @@ typedef struct drm_tex_region { */ typedef struct drm_hw_lock { __volatile__ unsigned int lock; /**< lock variable */ - char padding[60]; /**< Pad to cache line */ + char padding[60]; /**< Pad to cache line */ } drm_hw_lock_t; - /** * DRM_IOCTL_VERSION ioctl argument type. - * + * * \sa drmGetVersion(). */ typedef struct drm_version { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel;/**< Patch level */ + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ size_t name_len; /**< Length of name buffer */ - char __user *name; /**< Name of driver */ + char __user *name; /**< Name of driver */ size_t date_len; /**< Length of date buffer */ - char __user *date; /**< User-space buffer to hold date */ + char __user *date; /**< User-space buffer to hold date */ size_t desc_len; /**< Length of desc buffer */ - char __user *desc; /**< User-space buffer to hold desc */ + char __user *desc; /**< User-space buffer to hold desc */ } drm_version_t; - /** * DRM_IOCTL_GET_UNIQUE ioctl argument type. * @@ -170,21 +164,18 @@ typedef struct drm_version { */ typedef struct drm_unique { size_t unique_len; /**< Length of unique */ - char __user *unique; /**< Unique name for driver instantiation */ + char __user *unique; /**< Unique name for driver instantiation */ } drm_unique_t; - typedef struct drm_list { - int count; /**< Length of user-space structures */ - drm_version_t __user *version; + int count; /**< Length of user-space structures */ + drm_version_t __user *version; } drm_list_t; - typedef struct drm_block { - int unused; + int unused; } drm_block_t; - /** * DRM_IOCTL_CONTROL ioctl argument type. * @@ -196,44 +187,40 @@ typedef struct drm_control { DRM_RM_COMMAND, DRM_INST_HANDLER, DRM_UNINST_HANDLER - } func; - int irq; + } func; + int irq; } drm_control_t; - /** * Type of memory to map. */ typedef enum drm_map_type { - _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ - _DRM_REGISTERS = 1, /**< no caching, no core dump */ - _DRM_SHM = 2, /**< shared, cached */ - _DRM_AGP = 3, /**< AGP/GART */ + _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ + _DRM_REGISTERS = 1, /**< no caching, no core dump */ + _DRM_SHM = 2, /**< shared, cached */ + _DRM_AGP = 3, /**< AGP/GART */ _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ - _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ + _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ } drm_map_type_t; - /** * Memory mapping flags. */ typedef enum drm_map_flags { - _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ - _DRM_READ_ONLY = 0x02, - _DRM_LOCKED = 0x04, /**< shared, cached, locked */ - _DRM_KERNEL = 0x08, /**< kernel requires access */ + _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ + _DRM_READ_ONLY = 0x02, + _DRM_LOCKED = 0x04, /**< shared, cached, locked */ + _DRM_KERNEL = 0x08, /**< kernel requires access */ _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ - _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ - _DRM_REMOVABLE = 0x40 /**< Removable mapping */ + _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ + _DRM_REMOVABLE = 0x40 /**< Removable mapping */ } drm_map_flags_t; - typedef struct drm_ctx_priv_map { - unsigned int ctx_id; /**< Context requesting private mapping */ - void *handle; /**< Handle of map */ + unsigned int ctx_id; /**< Context requesting private mapping */ + void *handle; /**< Handle of map */ } drm_ctx_priv_map_t; - /** * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls * argument type. @@ -241,30 +228,28 @@ typedef struct drm_ctx_priv_map { * \sa drmAddMap(). */ typedef struct drm_map { - unsigned long offset; /**< Requested physical address (0 for SAREA)*/ - unsigned long size; /**< Requested physical size (bytes) */ - drm_map_type_t type; /**< Type of memory to map */ + unsigned long offset; /**< Requested physical address (0 for SAREA)*/ + unsigned long size; /**< Requested physical size (bytes) */ + drm_map_type_t type; /**< Type of memory to map */ drm_map_flags_t flags; /**< Flags */ - void *handle; /**< User-space: "Handle" to pass to mmap() */ + void *handle; /**< User-space: "Handle" to pass to mmap() */ /**< Kernel-space: kernel-virtual address */ - int mtrr; /**< MTRR slot used */ - /* Private data */ + int mtrr; /**< MTRR slot used */ + /* Private data */ } drm_map_t; - /** * DRM_IOCTL_GET_CLIENT ioctl argument type. */ typedef struct drm_client { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - unsigned long pid; /**< Process ID */ - unsigned long uid; /**< User ID */ - unsigned long magic; /**< Magic */ - unsigned long iocs; /**< Ioctl count */ + int idx; /**< Which client desired? */ + int auth; /**< Is client authenticated? */ + unsigned long pid; /**< Process ID */ + unsigned long uid; /**< User ID */ + unsigned long magic; /**< Magic */ + unsigned long iocs; /**< Ioctl count */ } drm_client_t; - typedef enum { _DRM_STAT_LOCK, _DRM_STAT_OPENS, @@ -282,63 +267,58 @@ typedef enum { _DRM_STAT_DMA, /**< DMA */ _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ _DRM_STAT_MISSED /**< Missed DMA opportunity */ - - /* Add to the *END* of the list */ + /* Add to the *END* of the list */ } drm_stat_type_t; - /** * DRM_IOCTL_GET_STATS ioctl argument type. */ typedef struct drm_stats { unsigned long count; struct { - unsigned long value; + unsigned long value; drm_stat_type_t type; } data[15]; } drm_stats_t; - /** * Hardware locking flags. */ typedef enum drm_lock_flags { - _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ - _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ - _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ - _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ - /* These *HALT* flags aren't supported yet - -- they will be used to support the - full-screen DGA-like mode. */ + _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ } drm_lock_flags_t; - /** * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. - * + * * \sa drmGetLock() and drmUnlock(). */ typedef struct drm_lock { - int context; + int context; drm_lock_flags_t flags; } drm_lock_t; - /** * DMA flags * - * \warning + * \warning * These values \e must match xf86drm.h. * * \sa drm_dma. */ -typedef enum drm_dma_flags { - /* Flags for DMA buffer dispatch */ - _DRM_DMA_BLOCK = 0x01, /**< +typedef enum drm_dma_flags { + /* Flags for DMA buffer dispatch */ + _DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. - * + * * \note The buffer may not yet have * been processed by the hardware -- * getting a hardware lock with the @@ -347,79 +327,73 @@ typedef enum drm_dma_flags { * processed. */ _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ - _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ - /* Flags for DMA buffer request */ - _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ - _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ - _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ + /* Flags for DMA buffer request */ + _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ } drm_dma_flags_t; - /** * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. * * \sa drmAddBufs(). */ typedef struct drm_buf_desc { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ enum { - _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ - _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ - _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ - _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ - } flags; - unsigned long agp_start; /**< + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ + _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ + _DRM_FB_BUFFER = 0x08 /**< Buffer is in frame buffer */ + } flags; + unsigned long agp_start; /**< * Start address of where the AGP buffers are * in the AGP aperture */ } drm_buf_desc_t; - /** * DRM_IOCTL_INFO_BUFS ioctl argument type. */ typedef struct drm_buf_info { - int count; /**< Entries in list */ + int count; /**< Entries in list */ drm_buf_desc_t __user *list; } drm_buf_info_t; - /** * DRM_IOCTL_FREE_BUFS ioctl argument type. */ typedef struct drm_buf_free { - int count; - int __user *list; + int count; + int __user *list; } drm_buf_free_t; - /** * Buffer information * * \sa drm_buf_map. */ typedef struct drm_buf_pub { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - void __user *address; /**< Address of buffer */ + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + void __user *address; /**< Address of buffer */ } drm_buf_pub_t; - /** * DRM_IOCTL_MAP_BUFS ioctl argument type. */ typedef struct drm_buf_map { - int count; /**< Length of the buffer list */ - void __user *virtual; /**< Mmap'd area in user-virtual */ + int count; /**< Length of the buffer list */ + void __user *virtual; /**< Mmap'd area in user-virtual */ drm_buf_pub_t __user *list; /**< Buffer information */ } drm_buf_map_t; - /** * DRM_IOCTL_DMA ioctl argument type. * @@ -428,61 +402,55 @@ typedef struct drm_buf_map { * \sa drmDMA(). */ typedef struct drm_dma { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - int __user *send_indices; /**< List of handles to buffers */ - int __user *send_sizes; /**< Lengths of data to send */ + int context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int __user *send_indices; /**< List of handles to buffers */ + int __user *send_sizes; /**< Lengths of data to send */ drm_dma_flags_t flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - int __user *request_indices; /**< Buffer information */ - int __user *request_sizes; - int granted_count; /**< Number of buffers granted */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size for buffers */ + int __user *request_indices; /**< Buffer information */ + int __user *request_sizes; + int granted_count; /**< Number of buffers granted */ } drm_dma_t; - typedef enum { _DRM_CONTEXT_PRESERVED = 0x01, - _DRM_CONTEXT_2DONLY = 0x02 + _DRM_CONTEXT_2DONLY = 0x02 } drm_ctx_flags_t; - /** * DRM_IOCTL_ADD_CTX ioctl argument type. * * \sa drmCreateContext() and drmDestroyContext(). */ typedef struct drm_ctx { - drm_context_t handle; + drm_context_t handle; drm_ctx_flags_t flags; } drm_ctx_t; - /** * DRM_IOCTL_RES_CTX ioctl argument type. */ typedef struct drm_ctx_res { - int count; - drm_ctx_t __user *contexts; + int count; + drm_ctx_t __user *contexts; } drm_ctx_res_t; - /** * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. */ typedef struct drm_draw { - drm_drawable_t handle; + drm_drawable_t handle; } drm_draw_t; - /** * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. */ typedef struct drm_auth { - drm_magic_t magic; + drm_magic_t magic; } drm_auth_t; - /** * DRM_IOCTL_IRQ_BUSID ioctl argument type. * @@ -495,24 +463,20 @@ typedef struct drm_irq_busid { int funcnum; /**< function number */ } drm_irq_busid_t; - typedef enum { - _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ - _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ - _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ + _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ } drm_vblank_seq_type_t; - #define _DRM_VBLANK_FLAGS_MASK _DRM_VBLANK_SIGNAL - struct drm_wait_vblank_request { drm_vblank_seq_type_t type; unsigned int sequence; unsigned long signal; }; - struct drm_wait_vblank_reply { drm_vblank_seq_type_t type; unsigned int sequence; @@ -520,7 +484,6 @@ struct drm_wait_vblank_reply { long tval_usec; }; - /** * DRM_IOCTL_WAIT_VBLANK ioctl argument type. * @@ -531,7 +494,6 @@ typedef union drm_wait_vblank { struct drm_wait_vblank_reply reply; } drm_wait_vblank_t; - /** * DRM_IOCTL_AGP_ENABLE ioctl argument type. * @@ -541,7 +503,6 @@ typedef struct drm_agp_mode { unsigned long mode; /**< AGP mode */ } drm_agp_mode_t; - /** * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. * @@ -550,22 +511,20 @@ typedef struct drm_agp_mode { typedef struct drm_agp_buffer { unsigned long size; /**< In bytes -- will round to page boundary */ unsigned long handle; /**< Used for binding / unbinding */ - unsigned long type; /**< Type of memory to allocate */ - unsigned long physical; /**< Physical used by i810 */ + unsigned long type; /**< Type of memory to allocate */ + unsigned long physical; /**< Physical used by i810 */ } drm_agp_buffer_t; - /** * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. * * \sa drmAgpBind() and drmAgpUnbind(). */ typedef struct drm_agp_binding { - unsigned long handle; /**< From drm_agp_buffer */ + unsigned long handle; /**< From drm_agp_buffer */ unsigned long offset; /**< In bytes -- will round to page boundary */ } drm_agp_binding_t; - /** * DRM_IOCTL_AGP_INFO ioctl argument type. * @@ -574,20 +533,19 @@ typedef struct drm_agp_binding { * drmAgpVendorId() and drmAgpDeviceId(). */ typedef struct drm_agp_info { - int agp_version_major; - int agp_version_minor; - unsigned long mode; - unsigned long aperture_base; /* physical address */ - unsigned long aperture_size; /* bytes */ - unsigned long memory_allowed; /* bytes */ - unsigned long memory_used; - - /* PCI information */ + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ unsigned short id_vendor; unsigned short id_device; } drm_agp_info_t; - /** * DRM_IOCTL_SG_ALLOC ioctl argument type. */ @@ -606,7 +564,6 @@ typedef struct drm_set_version { int drm_dd_minor; } drm_set_version_t; - #define DRM_IOCTL_BASE 'd' #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h index 79221783a14..255a21783d1 100644 --- a/drivers/char/drm/drmP.h +++ b/drivers/char/drm/drmP.h @@ -1,7 +1,7 @@ /** - * \file drmP.h + * \file drmP.h * Private header for Direct Rendering Manager - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -43,7 +43,7 @@ * before static inline funcs in wait.h. Doing this so we * can build the DRM (part of PI DRI). 4/21/2000 S + B */ #include -#endif /* __alpha__ */ +#endif /* __alpha__ */ #include #include #include @@ -58,7 +58,7 @@ #include #include #if defined(__alpha__) || defined(__powerpc__) -#include /* For pte_wrprotect */ +#include /* For pte_wrprotect */ #endif #include #include @@ -138,16 +138,15 @@ #define DRM_MEM_CTXLIST 21 #define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8) - -/*@}*/ +/*@}*/ /***********************************************************************/ /** \name Backward compatibility section */ /*@{*/ #ifndef MODULE_LICENSE -#define MODULE_LICENSE(x) +#define MODULE_LICENSE(x) #endif #ifndef preempt_disable @@ -155,7 +154,7 @@ #define preempt_enable() #endif -#ifndef pte_offset_map +#ifndef pte_offset_map #define pte_offset_map pte_offset #define pte_unmap(pte) #endif @@ -166,7 +165,6 @@ /*@}*/ - /***********************************************************************/ /** \name Macros to make printk easier */ /*@{*/ @@ -195,7 +193,7 @@ /** * Debug output. - * + * * \param fmt printf() like format string. * \param arg arguments */ @@ -223,7 +221,6 @@ /*@}*/ - /***********************************************************************/ /** \name Internal types and structures */ /*@{*/ @@ -275,7 +272,7 @@ do { \ if ( copy_to_user( name, value, len ) ) \ return -EFAULT; \ } - + /** * Ioctl function type. * @@ -284,25 +281,25 @@ do { \ * \param cmd command. * \param arg argument. */ -typedef int drm_ioctl_t( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +typedef int drm_ioctl_t(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd, unsigned long arg); typedef struct drm_ioctl_desc { - drm_ioctl_t *func; - int auth_needed; - int root_only; + drm_ioctl_t *func; + int auth_needed; + int root_only; } drm_ioctl_desc_t; typedef struct drm_devstate { - pid_t owner; /**< X server pid holding x_lock */ + pid_t owner; /**< X server pid holding x_lock */ } drm_devstate_t; typedef struct drm_magic_entry { - drm_magic_t magic; - struct drm_file *priv; + drm_magic_t magic; + struct drm_file *priv; struct drm_magic_entry *next; } drm_magic_entry_t; @@ -313,111 +310,110 @@ typedef struct drm_magic_head { typedef struct drm_vma_entry { struct vm_area_struct *vma; - struct drm_vma_entry *next; - pid_t pid; + struct drm_vma_entry *next; + pid_t pid; } drm_vma_entry_t; /** * DMA buffer. */ typedef struct drm_buf { - int idx; /**< Index into master buflist */ - int total; /**< Buffer size */ - int order; /**< log-base-2(total) */ - int used; /**< Amount of buffer in use (for DMA) */ - unsigned long offset; /**< Byte offset (used internally) */ - void *address; /**< Address of buffer */ - unsigned long bus_address; /**< Bus address of buffer */ - struct drm_buf *next; /**< Kernel-only: used for free list */ - __volatile__ int waiting; /**< On kernel DMA queue */ - __volatile__ int pending; /**< On hardware DMA queue */ + int idx; /**< Index into master buflist */ + int total; /**< Buffer size */ + int order; /**< log-base-2(total) */ + int used; /**< Amount of buffer in use (for DMA) */ + unsigned long offset; /**< Byte offset (used internally) */ + void *address; /**< Address of buffer */ + unsigned long bus_address; /**< Bus address of buffer */ + struct drm_buf *next; /**< Kernel-only: used for free list */ + __volatile__ int waiting; /**< On kernel DMA queue */ + __volatile__ int pending; /**< On hardware DMA queue */ wait_queue_head_t dma_wait; /**< Processes waiting */ - struct file *filp; /**< Pointer to holding file descr */ - int context; /**< Kernel queue for this buffer */ - int while_locked;/**< Dispatch this buffer while locked */ + struct file *filp; /**< Pointer to holding file descr */ + int context; /**< Kernel queue for this buffer */ + int while_locked; /**< Dispatch this buffer while locked */ enum { - DRM_LIST_NONE = 0, - DRM_LIST_FREE = 1, - DRM_LIST_WAIT = 2, - DRM_LIST_PEND = 3, - DRM_LIST_PRIO = 4, + DRM_LIST_NONE = 0, + DRM_LIST_FREE = 1, + DRM_LIST_WAIT = 2, + DRM_LIST_PEND = 3, + DRM_LIST_PRIO = 4, DRM_LIST_RECLAIM = 5 - } list; /**< Which list we're on */ + } list; /**< Which list we're on */ - int dev_priv_size; /**< Size of buffer private storage */ - void *dev_private; /**< Per-buffer private storage */ + int dev_priv_size; /**< Size of buffer private storage */ + void *dev_private; /**< Per-buffer private storage */ } drm_buf_t; - /** bufs is one longer than it has to be */ typedef struct drm_waitlist { - int count; /**< Number of possible buffers */ - drm_buf_t **bufs; /**< List of pointers to buffers */ - drm_buf_t **rp; /**< Read pointer */ - drm_buf_t **wp; /**< Write pointer */ - drm_buf_t **end; /**< End pointer */ - spinlock_t read_lock; - spinlock_t write_lock; + int count; /**< Number of possible buffers */ + drm_buf_t **bufs; /**< List of pointers to buffers */ + drm_buf_t **rp; /**< Read pointer */ + drm_buf_t **wp; /**< Write pointer */ + drm_buf_t **end; /**< End pointer */ + spinlock_t read_lock; + spinlock_t write_lock; } drm_waitlist_t; typedef struct drm_freelist { - int initialized; /**< Freelist in use */ - atomic_t count; /**< Number of free buffers */ - drm_buf_t *next; /**< End pointer */ + int initialized; /**< Freelist in use */ + atomic_t count; /**< Number of free buffers */ + drm_buf_t *next; /**< End pointer */ wait_queue_head_t waiting; /**< Processes waiting on free bufs */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - atomic_t wfh; /**< If waiting for high mark */ - spinlock_t lock; + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + atomic_t wfh; /**< If waiting for high mark */ + spinlock_t lock; } drm_freelist_t; /** * Buffer entry. There is one of this for each buffer size order. */ typedef struct drm_buf_entry { - int buf_size; /**< size */ - int buf_count; /**< number of buffers */ - drm_buf_t *buflist; /**< buffer list */ - int seg_count; - int page_order; - unsigned long *seglist; - - drm_freelist_t freelist; + int buf_size; /**< size */ + int buf_count; /**< number of buffers */ + drm_buf_t *buflist; /**< buffer list */ + int seg_count; + int page_order; + unsigned long *seglist; + + drm_freelist_t freelist; } drm_buf_entry_t; /** File private data */ typedef struct drm_file { - int authenticated; - int minor; - pid_t pid; - uid_t uid; - drm_magic_t magic; - unsigned long ioctl_count; - struct drm_file *next; - struct drm_file *prev; - struct drm_head *head; - int remove_auth_on_close; - unsigned long lock_count; - void *driver_priv; + int authenticated; + int minor; + pid_t pid; + uid_t uid; + drm_magic_t magic; + unsigned long ioctl_count; + struct drm_file *next; + struct drm_file *prev; + struct drm_head *head; + int remove_auth_on_close; + unsigned long lock_count; + void *driver_priv; } drm_file_t; /** Wait queue */ typedef struct drm_queue { - atomic_t use_count; /**< Outstanding uses (+1) */ - atomic_t finalization; /**< Finalization in progress */ - atomic_t block_count; /**< Count of processes waiting */ - atomic_t block_read; /**< Queue blocked for reads */ + atomic_t use_count; /**< Outstanding uses (+1) */ + atomic_t finalization; /**< Finalization in progress */ + atomic_t block_count; /**< Count of processes waiting */ + atomic_t block_read; /**< Queue blocked for reads */ wait_queue_head_t read_queue; /**< Processes waiting on block_read */ - atomic_t block_write; /**< Queue blocked for writes */ + atomic_t block_write; /**< Queue blocked for writes */ wait_queue_head_t write_queue; /**< Processes waiting on block_write */ #if 1 - atomic_t total_queued; /**< Total queued statistic */ - atomic_t total_flushed;/**< Total flushes statistic */ - atomic_t total_locks; /**< Total locks statistics */ + atomic_t total_queued; /**< Total queued statistic */ + atomic_t total_flushed; /**< Total flushes statistic */ + atomic_t total_locks; /**< Total locks statistics */ #endif - drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ - drm_waitlist_t waitlist; /**< Pending buffers */ + drm_ctx_flags_t flags; /**< Context preserving and 2D-only */ + drm_waitlist_t waitlist; /**< Pending buffers */ wait_queue_head_t flush_queue; /**< Processes waiting until flush */ } drm_queue_t; @@ -425,10 +421,10 @@ typedef struct drm_queue { * Lock data. */ typedef struct drm_lock_data { - drm_hw_lock_t *hw_lock; /**< Hardware lock */ - struct file *filp; /**< File descr of lock holder (0=kernel) */ + drm_hw_lock_t *hw_lock; /**< Hardware lock */ + struct file *filp; /**< File descr of lock holder (0=kernel) */ wait_queue_head_t lock_queue; /**< Queue of blocked processes */ - unsigned long lock_time; /**< Time of last lock in jiffies */ + unsigned long lock_time; /**< Time of last lock in jiffies */ } drm_lock_data_t; /** @@ -436,29 +432,29 @@ typedef struct drm_lock_data { */ typedef struct drm_device_dma { - drm_buf_entry_t bufs[DRM_MAX_ORDER+1]; /**< buffers, grouped by their size order */ - int buf_count; /**< total number of buffers */ - drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ - int seg_count; - int page_count; /**< number of pages */ - unsigned long *pagelist; /**< page list */ - unsigned long byte_count; + drm_buf_entry_t bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */ + int buf_count; /**< total number of buffers */ + drm_buf_t **buflist; /**< Vector of pointers into drm_device_dma::bufs */ + int seg_count; + int page_count; /**< number of pages */ + unsigned long *pagelist; /**< page list */ + unsigned long byte_count; enum { _DRM_DMA_USE_AGP = 0x01, - _DRM_DMA_USE_SG = 0x02, - _DRM_DMA_USE_FB = 0x04 + _DRM_DMA_USE_SG = 0x02, + _DRM_DMA_USE_FB = 0x04 } flags; } drm_device_dma_t; -/** +/** * AGP memory entry. Stored as a doubly linked list. */ typedef struct drm_agp_mem { - unsigned long handle; /**< handle */ - DRM_AGP_MEM *memory; - unsigned long bound; /**< address */ - int pages; + unsigned long handle; /**< handle */ + DRM_AGP_MEM *memory; + unsigned long bound; /**< address */ + int pages; struct drm_agp_mem *prev; /**< previous entry */ struct drm_agp_mem *next; /**< next entry */ } drm_agp_mem_t; @@ -469,31 +465,31 @@ typedef struct drm_agp_mem { * \sa drm_agp_init() and drm_device::agp. */ typedef struct drm_agp_head { - DRM_AGP_KERN agp_info; /**< AGP device information */ - drm_agp_mem_t *memory; /**< memory entries */ - unsigned long mode; /**< AGP mode */ - struct agp_bridge_data *bridge; - int enabled; /**< whether the AGP bus as been enabled */ - int acquired; /**< whether the AGP device has been acquired */ - unsigned long base; - int agp_mtrr; - int cant_use_aperture; - unsigned long page_mask; + DRM_AGP_KERN agp_info; /**< AGP device information */ + drm_agp_mem_t *memory; /**< memory entries */ + unsigned long mode; /**< AGP mode */ + struct agp_bridge_data *bridge; + int enabled; /**< whether the AGP bus as been enabled */ + int acquired; /**< whether the AGP device has been acquired */ + unsigned long base; + int agp_mtrr; + int cant_use_aperture; + unsigned long page_mask; } drm_agp_head_t; /** * Scatter-gather memory. */ typedef struct drm_sg_mem { - unsigned long handle; - void *virtual; - int pages; - struct page **pagelist; - dma_addr_t *busaddr; + unsigned long handle; + void *virtual; + int pages; + struct page **pagelist; + dma_addr_t *busaddr; } drm_sg_mem_t; typedef struct drm_sigdata { - int context; + int context; drm_hw_lock_t *lock; } drm_sigdata_t; @@ -507,8 +503,8 @@ typedef struct drm_dma_handle { * Mappings list */ typedef struct drm_map_list { - struct list_head head; /**< list head */ - drm_map_t *map; /**< mapping */ + struct list_head head; /**< list head */ + drm_map_t *map; /**< mapping */ unsigned int user_token; } drm_map_list_t; @@ -518,20 +514,18 @@ typedef drm_map_t drm_local_map_t; * Context handle list */ typedef struct drm_ctx_list { - struct list_head head; /**< list head */ - drm_context_t handle; /**< context handle */ - drm_file_t *tag; /**< associated fd private data */ + struct list_head head; /**< list head */ + drm_context_t handle; /**< context handle */ + drm_file_t *tag; /**< associated fd private data */ } drm_ctx_list_t; - typedef struct drm_vbl_sig { - struct list_head head; - unsigned int sequence; - struct siginfo info; - struct task_struct *task; + struct list_head head; + unsigned int sequence; + struct siginfo info; + struct task_struct *task; } drm_vbl_sig_t; - /* location of GART table */ #define DRM_ATI_GART_MAIN 1 #define DRM_ATI_GART_FB 2 @@ -551,24 +545,26 @@ typedef struct ati_pcigart_info { struct drm_device; struct drm_driver { - int (*preinit)(struct drm_device *, unsigned long flags); - void (*prerelease)(struct drm_device *, struct file *filp); - void (*pretakedown)(struct drm_device *); - int (*postcleanup)(struct drm_device *); - int (*presetup)(struct drm_device *); - int (*postsetup)(struct drm_device *); - int (*dma_ioctl)( DRM_IOCTL_ARGS ); - int (*open_helper)(struct drm_device *, drm_file_t *); - void (*free_filp_priv)(struct drm_device *, drm_file_t *); - void (*release)(struct drm_device *, struct file *filp); - void (*dma_ready)(struct drm_device *); - int (*dma_quiescent)(struct drm_device *); - int (*context_ctor)(struct drm_device *dev, int context); - int (*context_dtor)(struct drm_device *dev, int context); - int (*kernel_context_switch)(struct drm_device *dev, int old, int new); - void (*kernel_context_switch_unlock)(struct drm_device *dev, drm_lock_t *lock); - int (*vblank_wait)(struct drm_device *dev, unsigned int *sequence); - + int (*preinit) (struct drm_device *, unsigned long flags); + void (*prerelease) (struct drm_device *, struct file * filp); + void (*pretakedown) (struct drm_device *); + int (*postcleanup) (struct drm_device *); + int (*presetup) (struct drm_device *); + int (*postsetup) (struct drm_device *); + int (*dma_ioctl) (DRM_IOCTL_ARGS); + int (*open_helper) (struct drm_device *, drm_file_t *); + void (*free_filp_priv) (struct drm_device *, drm_file_t *); + void (*release) (struct drm_device *, struct file * filp); + void (*dma_ready) (struct drm_device *); + int (*dma_quiescent) (struct drm_device *); + int (*context_ctor) (struct drm_device * dev, int context); + int (*context_dtor) (struct drm_device * dev, int context); + int (*kernel_context_switch) (struct drm_device * dev, int old, + int new); + void (*kernel_context_switch_unlock) (struct drm_device * dev, + drm_lock_t * lock); + int (*vblank_wait) (struct drm_device * dev, unsigned int *sequence); + /** * Called by \c drm_device_is_agp. Typically used to determine if a * card is really attached to AGP or not. @@ -583,17 +579,17 @@ struct drm_driver { int (*device_is_agp) (struct drm_device * dev); /* these have to be filled in */ - - int (*postinit)(struct drm_device *, unsigned long flags); - irqreturn_t (*irq_handler)( DRM_IRQ_ARGS ); - void (*irq_preinstall)(struct drm_device *dev); - void (*irq_postinstall)(struct drm_device *dev); - void (*irq_uninstall)(struct drm_device *dev); - void (*reclaim_buffers)(struct drm_device *dev, struct file *filp); - unsigned long (*get_map_ofs)(drm_map_t *map); - unsigned long (*get_reg_ofs)(struct drm_device *dev); - void (*set_version)(struct drm_device *dev, drm_set_version_t *sv); - int (*version)(drm_version_t *version); + + int (*postinit) (struct drm_device *, unsigned long flags); + irqreturn_t(*irq_handler) (DRM_IRQ_ARGS); + void (*irq_preinstall) (struct drm_device * dev); + void (*irq_postinstall) (struct drm_device * dev); + void (*irq_uninstall) (struct drm_device * dev); + void (*reclaim_buffers) (struct drm_device * dev, struct file * filp); + unsigned long (*get_map_ofs) (drm_map_t * map); + unsigned long (*get_reg_ofs) (struct drm_device * dev); + void (*set_version) (struct drm_device * dev, drm_set_version_t * sv); + int (*version) (drm_version_t * version); u32 driver_features; int dev_priv_size; drm_ioctl_desc_t *ioctls; @@ -620,128 +616,129 @@ typedef struct drm_head { * may contain multiple heads. */ typedef struct drm_device { - char *unique; /**< Unique identifier: e.g., busid */ - int unique_len; /**< Length of unique field */ - char *devname; /**< For /proc/interrupts */ - int if_version; /**< Highest interface version set */ + char *unique; /**< Unique identifier: e.g., busid */ + int unique_len; /**< Length of unique field */ + char *devname; /**< For /proc/interrupts */ + int if_version; /**< Highest interface version set */ - int blocked; /**< Blocked due to VC switch? */ + int blocked; /**< Blocked due to VC switch? */ /** \name Locks */ - /*@{*/ - spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ - struct semaphore struct_sem; /**< For others */ - /*@}*/ + /*@{ */ + spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */ + struct semaphore struct_sem; /**< For others */ + /*@} */ /** \name Usage Counters */ - /*@{*/ - int open_count; /**< Outstanding files open */ - atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ - atomic_t vma_count; /**< Outstanding vma areas open */ - int buf_use; /**< Buffers in use -- cannot alloc */ - atomic_t buf_alloc; /**< Buffer allocation in progress */ - /*@}*/ + /*@{ */ + int open_count; /**< Outstanding files open */ + atomic_t ioctl_count; /**< Outstanding IOCTLs pending */ + atomic_t vma_count; /**< Outstanding vma areas open */ + int buf_use; /**< Buffers in use -- cannot alloc */ + atomic_t buf_alloc; /**< Buffer allocation in progress */ + /*@} */ /** \name Performance counters */ - /*@{*/ - unsigned long counters; - drm_stat_type_t types[15]; - atomic_t counts[15]; - /*@}*/ + /*@{ */ + unsigned long counters; + drm_stat_type_t types[15]; + atomic_t counts[15]; + /*@} */ /** \name Authentication */ - /*@{*/ - drm_file_t *file_first; /**< file list head */ - drm_file_t *file_last; /**< file list tail */ - drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ - /*@}*/ + /*@{ */ + drm_file_t *file_first; /**< file list head */ + drm_file_t *file_last; /**< file list tail */ + drm_magic_head_t magiclist[DRM_HASH_SIZE]; /**< magic hash table */ + /*@} */ /** \name Memory management */ - /*@{*/ - drm_map_list_t *maplist; /**< Linked list of regions */ - int map_count; /**< Number of mappable regions */ + /*@{ */ + drm_map_list_t *maplist; /**< Linked list of regions */ + int map_count; /**< Number of mappable regions */ /** \name Context handle management */ - /*@{*/ - drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ - int ctx_count; /**< Number of context handles */ - struct semaphore ctxlist_sem; /**< For ctxlist */ + /*@{ */ + drm_ctx_list_t *ctxlist; /**< Linked list of context handles */ + int ctx_count; /**< Number of context handles */ + struct semaphore ctxlist_sem; /**< For ctxlist */ - drm_map_t **context_sareas; /**< per-context SAREA's */ - int max_context; + drm_map_t **context_sareas; /**< per-context SAREA's */ + int max_context; - drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ - drm_lock_data_t lock; /**< Information on hardware lock */ - /*@}*/ + drm_vma_entry_t *vmalist; /**< List of vmas (for debugging) */ + drm_lock_data_t lock; /**< Information on hardware lock */ + /*@} */ /** \name DMA queues (contexts) */ - /*@{*/ - int queue_count; /**< Number of active DMA queues */ - int queue_reserved; /**< Number of reserved DMA queues */ - int queue_slots; /**< Actual length of queuelist */ - drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ - drm_device_dma_t *dma; /**< Optional pointer for DMA support */ - /*@}*/ + /*@{ */ + int queue_count; /**< Number of active DMA queues */ + int queue_reserved; /**< Number of reserved DMA queues */ + int queue_slots; /**< Actual length of queuelist */ + drm_queue_t **queuelist; /**< Vector of pointers to DMA queues */ + drm_device_dma_t *dma; /**< Optional pointer for DMA support */ + /*@} */ /** \name Context support */ - /*@{*/ - int irq; /**< Interrupt used by board */ - int irq_enabled; /**< True if irq handler is enabled */ + /*@{ */ + int irq; /**< Interrupt used by board */ + int irq_enabled; /**< True if irq handler is enabled */ __volatile__ long context_flag; /**< Context swapping flag */ __volatile__ long interrupt_flag; /**< Interruption handler flag */ __volatile__ long dma_flag; /**< DMA dispatch flag */ struct timer_list timer; /**< Timer for delaying ctx switch */ - wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ - int last_checked; /**< Last context checked for DMA */ - int last_context; /**< Last current context */ - unsigned long last_switch; /**< jiffies at last context switch */ - /*@}*/ - - struct work_struct work; + wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */ + int last_checked; /**< Last context checked for DMA */ + int last_context; /**< Last current context */ + unsigned long last_switch; /**< jiffies at last context switch */ + /*@} */ + + struct work_struct work; /** \name VBLANK IRQ support */ - /*@{*/ - - wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ - atomic_t vbl_received; - spinlock_t vbl_lock; - drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ - unsigned int vbl_pending; - - /*@}*/ - cycles_t ctx_start; - cycles_t lck_start; - - char buf[DRM_BSZ]; /**< Output buffer */ - char *buf_rp; /**< Read pointer */ - char *buf_wp; /**< Write pointer */ - char *buf_end; /**< End pointer */ + /*@{ */ + + wait_queue_head_t vbl_queue; /**< VBLANK wait queue */ + atomic_t vbl_received; + spinlock_t vbl_lock; + drm_vbl_sig_t vbl_sigs; /**< signal list to send on VBLANK */ + unsigned int vbl_pending; + + /*@} */ + cycles_t ctx_start; + cycles_t lck_start; + + char buf[DRM_BSZ]; /**< Output buffer */ + char *buf_rp; /**< Read pointer */ + char *buf_wp; /**< Write pointer */ + char *buf_end; /**< End pointer */ struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ wait_queue_head_t buf_readers; /**< Processes waiting to read */ wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ - drm_agp_head_t *agp; /**< AGP data */ + drm_agp_head_t *agp; /**< AGP data */ - struct pci_dev *pdev; /**< PCI device structure */ - int pci_domain; /**< PCI bus domain number */ - int pci_bus; /**< PCI bus number */ - int pci_slot; /**< PCI slot number */ - int pci_func; /**< PCI function number */ + struct pci_dev *pdev; /**< PCI device structure */ + int pci_domain; /**< PCI bus domain number */ + int pci_bus; /**< PCI bus number */ + int pci_slot; /**< PCI slot number */ + int pci_func; /**< PCI function number */ #ifdef __alpha__ struct pci_controller *hose; #endif - drm_sg_mem_t *sg; /**< Scatter gather memory */ - unsigned long *ctx_bitmap; /**< context bitmap */ - void *dev_private; /**< device private data */ - drm_sigdata_t sigdata; /**< For block_all_signals */ - sigset_t sigmask; - - struct drm_driver *driver; - drm_local_map_t *agp_buffer_map; + drm_sg_mem_t *sg; /**< Scatter gather memory */ + unsigned long *ctx_bitmap; /**< context bitmap */ + void *dev_private; /**< device private data */ + drm_sigdata_t sigdata; /**< For block_all_signals */ + sigset_t sigmask; + + struct drm_driver *driver; + drm_local_map_t *agp_buffer_map; unsigned int agp_buffer_token; drm_head_t primary; /**< primary screen head */ } drm_device_t; -static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature) +static __inline__ int drm_core_check_feature(struct drm_device *dev, + int feature) { return ((dev->driver->driver_features & feature) ? 1 : 0); } @@ -749,7 +746,7 @@ static __inline__ int drm_core_check_feature(struct drm_device *dev, int feature #if __OS_HAS_AGP static inline int drm_core_has_AGP(struct drm_device *dev) { - return drm_core_check_feature(dev, DRIVER_USE_AGP); + return drm_core_check_feature(dev, DRIVER_USE_AGP); } #else #define drm_core_has_AGP(dev) (0) @@ -758,7 +755,7 @@ static inline int drm_core_has_AGP(struct drm_device *dev) #if __OS_HAS_MTRR static inline int drm_core_has_MTRR(struct drm_device *dev) { - return drm_core_check_feature(dev, DRIVER_USE_MTRR); + return drm_core_check_feature(dev, DRIVER_USE_MTRR); } #else #define drm_core_has_MTRR(dev) (0) @@ -769,230 +766,229 @@ static inline int drm_core_has_MTRR(struct drm_device *dev) /*@{*/ /* Misc. support (drm_init.h) */ -extern int drm_flags; -extern void drm_parse_options( char *s ); -extern int drm_cpu_valid( void ); +extern int drm_flags; +extern void drm_parse_options(char *s); +extern int drm_cpu_valid(void); /* Driver support (drm_drv.h) */ -extern int drm_init(struct drm_driver *driver); -extern void drm_exit(struct drm_driver *driver); -extern int drm_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern long drm_compat_ioctl(struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_takedown(drm_device_t * dev); +extern int drm_init(struct drm_driver *driver); +extern void drm_exit(struct drm_driver *driver); +extern int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern long drm_compat_ioctl(struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_takedown(drm_device_t * dev); /* Device support (drm_fops.h) */ -extern int drm_open(struct inode *inode, struct file *filp); -extern int drm_stub_open(struct inode *inode, struct file *filp); -extern int drm_flush(struct file *filp); -extern int drm_fasync(int fd, struct file *filp, int on); -extern int drm_release(struct inode *inode, struct file *filp); +extern int drm_open(struct inode *inode, struct file *filp); +extern int drm_stub_open(struct inode *inode, struct file *filp); +extern int drm_flush(struct file *filp); +extern int drm_fasync(int fd, struct file *filp, int on); +extern int drm_release(struct inode *inode, struct file *filp); /* Mapping support (drm_vm.h) */ -extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); -extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); +extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); +extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); /* Memory management support (drm_memory.h) */ #include "drm_memory.h" -extern void drm_mem_init(void); -extern int drm_mem_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, - int area); +extern void drm_mem_init(void); +extern int drm_mem_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area); extern unsigned long drm_alloc_pages(int order, int area); -extern void drm_free_pages(unsigned long address, int order, - int area); -extern void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev); -extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size, - drm_device_t *dev); -extern void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev); - -extern DRM_AGP_MEM *drm_alloc_agp(drm_device_t *dev, int pages, u32 type); -extern int drm_free_agp(DRM_AGP_MEM *handle, int pages); -extern int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start); -extern int drm_unbind_agp(DRM_AGP_MEM *handle); +extern void drm_free_pages(unsigned long address, int order, int area); +extern void *drm_ioremap(unsigned long offset, unsigned long size, + drm_device_t * dev); +extern void *drm_ioremap_nocache(unsigned long offset, unsigned long size, + drm_device_t * dev); +extern void drm_ioremapfree(void *pt, unsigned long size, drm_device_t * dev); + +extern DRM_AGP_MEM *drm_alloc_agp(drm_device_t * dev, int pages, u32 type); +extern int drm_free_agp(DRM_AGP_MEM * handle, int pages); +extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); +extern int drm_unbind_agp(DRM_AGP_MEM * handle); /* Misc. IOCTL support (drm_ioctl.h) */ -extern int drm_irq_by_busid(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_setunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getmap(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getclient(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_getstats(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_setversion(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int drm_irq_by_busid(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setunique(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getclient(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getstats(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_setversion(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Context IOCTL support (drm_context.h) */ -extern int drm_resctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_addctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_modctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_getctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_switchctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_newctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_rmctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); - -extern int drm_ctxbitmap_init( drm_device_t *dev ); -extern void drm_ctxbitmap_cleanup( drm_device_t *dev ); -extern void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ); - -extern int drm_setsareactx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_getsareactx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); +extern int drm_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern int drm_ctxbitmap_init(drm_device_t * dev); +extern void drm_ctxbitmap_cleanup(drm_device_t * dev); +extern void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle); + +extern int drm_setsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_getsareactx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Drawable IOCTL support (drm_drawable.h) */ -extern int drm_adddraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_rmdraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); - +extern int drm_adddraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_rmdraw(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Authentication IOCTL support (drm_auth.h) */ -extern int drm_getmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_authmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern int drm_getmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_authmagic(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); - /* Placeholder for ioctls past */ -extern int drm_noop(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); + /* Placeholder for ioctls past */ +extern int drm_noop(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); /* Locking IOCTL support (drm_lock.h) */ -extern int drm_lock(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_unlock(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_lock_take(__volatile__ unsigned int *lock, - unsigned int context); -extern int drm_lock_free(drm_device_t *dev, - __volatile__ unsigned int *lock, - unsigned int context); +extern int drm_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context); +extern int drm_lock_free(drm_device_t * dev, + __volatile__ unsigned int *lock, unsigned int context); /* Buffer management support (drm_bufs.h) */ -extern int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request); -extern int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request); -extern int drm_addmap(drm_device_t *dev, unsigned int offset, +extern int drm_addbufs_agp(drm_device_t * dev, drm_buf_desc_t * request); +extern int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request); +extern int drm_addmap(drm_device_t * dev, unsigned int offset, unsigned int size, drm_map_type_t type, - drm_map_flags_t flags, drm_local_map_t **map_ptr); + drm_map_flags_t flags, drm_local_map_t ** map_ptr); extern int drm_addmap_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern int drm_rmmap(drm_device_t *dev, drm_local_map_t *map); -extern int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map); +extern int drm_rmmap(drm_device_t * dev, drm_local_map_t * map); +extern int drm_rmmap_locked(drm_device_t * dev, drm_local_map_t * map); extern int drm_rmmap_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern int drm_order( unsigned long size ); -extern int drm_addbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_infobufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_markbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_freebufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_mapbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern unsigned long drm_get_resource_start(drm_device_t *dev, +extern int drm_order(unsigned long size); +extern int drm_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern unsigned long drm_get_resource_start(drm_device_t * dev, unsigned int resource); -extern unsigned long drm_get_resource_len(drm_device_t *dev, +extern unsigned long drm_get_resource_len(drm_device_t * dev, unsigned int resource); /* DMA support (drm_dma.h) */ -extern int drm_dma_setup(drm_device_t *dev); -extern void drm_dma_takedown(drm_device_t *dev); -extern void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf); -extern void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp); +extern int drm_dma_setup(drm_device_t * dev); +extern void drm_dma_takedown(drm_device_t * dev); +extern void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf); +extern void drm_core_reclaim_buffers(drm_device_t * dev, struct file *filp); /* IRQ support (drm_irq.h) */ -extern int drm_control( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int drm_irq_uninstall( drm_device_t *dev ); -extern irqreturn_t drm_irq_handler( DRM_IRQ_ARGS ); -extern void drm_driver_irq_preinstall( drm_device_t *dev ); -extern void drm_driver_irq_postinstall( drm_device_t *dev ); -extern void drm_driver_irq_uninstall( drm_device_t *dev ); - -extern int drm_wait_vblank(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_vblank_wait(drm_device_t *dev, unsigned int *vbl_seq); -extern void drm_vbl_send_signals( drm_device_t *dev ); +extern int drm_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_irq_uninstall(drm_device_t * dev); +extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS); +extern void drm_driver_irq_preinstall(drm_device_t * dev); +extern void drm_driver_irq_postinstall(drm_device_t * dev); +extern void drm_driver_irq_uninstall(drm_device_t * dev); + +extern int drm_wait_vblank(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_vblank_wait(drm_device_t * dev, unsigned int *vbl_seq); +extern void drm_vbl_send_signals(drm_device_t * dev); /* AGP/GART support (drm_agpsupport.h) */ -extern drm_agp_head_t *drm_agp_init(drm_device_t *dev); +extern drm_agp_head_t *drm_agp_init(drm_device_t * dev); extern int drm_agp_acquire(drm_device_t * dev); extern int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_release(drm_device_t *dev); + unsigned int cmd, unsigned long arg); +extern int drm_agp_release(drm_device_t * dev); extern int drm_agp_release_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode); + unsigned int cmd, unsigned long arg); +extern int drm_agp_enable(drm_device_t * dev, drm_agp_mode_t mode); extern int drm_agp_enable_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_info(drm_device_t * dev, drm_agp_info_t *info); + unsigned int cmd, unsigned long arg); +extern int drm_agp_info(drm_device_t * dev, drm_agp_info_t * info); extern int drm_agp_info_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_free(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); -extern int drm_agp_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_unbind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_agp_bind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type); -extern int drm_agp_free_memory(DRM_AGP_MEM *handle); -extern int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start); -extern int drm_agp_unbind_memory(DRM_AGP_MEM *handle); +extern int drm_agp_unbind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_agp_bind(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, + size_t pages, u32 type); +extern int drm_agp_free_memory(DRM_AGP_MEM * handle); +extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start); +extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle); /* Stub support (drm_stub.h) */ extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, - struct drm_driver *driver); + struct drm_driver *driver); extern int drm_put_dev(drm_device_t * dev); extern int drm_put_head(drm_head_t * head); -extern unsigned int drm_debug; -extern unsigned int drm_cards_limit; +extern unsigned int drm_debug; +extern unsigned int drm_cards_limit; extern drm_head_t **drm_heads; extern struct drm_sysfs_class *drm_class; extern struct proc_dir_entry *drm_proc_root; /* Proc support (drm_proc.h) */ -extern int drm_proc_init(drm_device_t *dev, - int minor, - struct proc_dir_entry *root, - struct proc_dir_entry **dev_root); -extern int drm_proc_cleanup(int minor, - struct proc_dir_entry *root, - struct proc_dir_entry *dev_root); +extern int drm_proc_init(drm_device_t * dev, + int minor, + struct proc_dir_entry *root, + struct proc_dir_entry **dev_root); +extern int drm_proc_cleanup(int minor, + struct proc_dir_entry *root, + struct proc_dir_entry *dev_root); /* Scatter Gather Support (drm_scatter.h) */ -extern void drm_sg_cleanup(drm_sg_mem_t *entry); -extern int drm_sg_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); -extern int drm_sg_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg); +extern void drm_sg_cleanup(drm_sg_mem_t * entry); +extern int drm_sg_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int drm_sg_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); - /* ATI PCIGART support (ati_pcigart.h) */ -extern int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info *gart_info); -extern int drm_ati_pcigart_cleanup(drm_device_t * dev, drm_ati_pcigart_info *gart_info); + /* ATI PCIGART support (ati_pcigart.h) */ +extern int drm_ati_pcigart_init(drm_device_t * dev, + drm_ati_pcigart_info * gart_info); +extern int drm_ati_pcigart_cleanup(drm_device_t * dev, + drm_ati_pcigart_info * gart_info); -extern drm_dma_handle_t *drm_pci_alloc(drm_device_t *dev, size_t size, +extern drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align, dma_addr_t maxaddr); -extern void __drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah); -extern void drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah); +extern void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah); +extern void drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah); /* sysfs support (drm_sysfs.c) */ struct drm_sysfs_class; @@ -1005,38 +1001,41 @@ extern struct class_device *drm_sysfs_device_add(struct drm_sysfs_class *cs, const char *fmt, ...); extern void drm_sysfs_device_remove(dev_t dev); - /* Inline replacements for DRM_IOREMAP macros */ -static __inline__ void drm_core_ioremap(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremap(struct drm_map *map, + struct drm_device *dev) { - map->handle = drm_ioremap( map->offset, map->size, dev ); + map->handle = drm_ioremap(map->offset, map->size, dev); } -static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremap_nocache(struct drm_map *map, + struct drm_device *dev) { map->handle = drm_ioremap_nocache(map->offset, map->size, dev); } -static __inline__ void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev) +static __inline__ void drm_core_ioremapfree(struct drm_map *map, + struct drm_device *dev) { - if ( map->handle && map->size ) - drm_ioremapfree( map->handle, map->size, dev ); + if (map->handle && map->size) + drm_ioremapfree(map->handle, map->size, dev); } -static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, unsigned int token) +static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev, + unsigned int token) { drm_map_list_t *_entry; list_for_each_entry(_entry, &dev->maplist->head, head) - if (_entry->user_token == token) - return _entry->map; + if (_entry->user_token == token) + return _entry->map; return NULL; } -static __inline__ int drm_device_is_agp(drm_device_t *dev) +static __inline__ int drm_device_is_agp(drm_device_t * dev) { - if ( dev->driver->device_is_agp != NULL ) { - int err = (*dev->driver->device_is_agp)( dev ); - + if (dev->driver->device_is_agp != NULL) { + int err = (*dev->driver->device_is_agp) (dev); + if (err != 2) { return err; } @@ -1045,7 +1044,7 @@ static __inline__ int drm_device_is_agp(drm_device_t *dev) return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP); } -static __inline__ int drm_device_is_pcie(drm_device_t *dev) +static __inline__ int drm_device_is_pcie(drm_device_t * dev) { return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); } @@ -1080,12 +1079,12 @@ extern void *drm_calloc(size_t nmemb, size_t size, int area); /*@}*/ -extern unsigned long drm_core_get_map_ofs(drm_map_t *map); +extern unsigned long drm_core_get_map_ofs(drm_map_t * map); extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev); #ifndef pci_pretty_name #define pci_pretty_name(dev) "" #endif -#endif /* __KERNEL__ */ +#endif /* __KERNEL__ */ #endif diff --git a/drivers/char/drm/drm_agpsupport.c b/drivers/char/drm/drm_agpsupport.c index 8c215adcb4b..2b6453a9ffc 100644 --- a/drivers/char/drm/drm_agpsupport.c +++ b/drivers/char/drm/drm_agpsupport.c @@ -1,7 +1,7 @@ /** - * \file drm_agpsupport.h + * \file drm_agpsupport.h * DRM support for AGP/GART backend - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -48,30 +48,31 @@ * Verifies the AGP device has been initialized and acquired and fills in the * drm_agp_info structure with the information in drm_agp_head::agp_info. */ -int drm_agp_info(drm_device_t *dev, drm_agp_info_t *info) +int drm_agp_info(drm_device_t * dev, drm_agp_info_t * info) { - DRM_AGP_KERN *kern; + DRM_AGP_KERN *kern; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - kern = &dev->agp->agp_info; + kern = &dev->agp->agp_info; info->agp_version_major = kern->version.major; info->agp_version_minor = kern->version.minor; - info->mode = kern->mode; - info->aperture_base = kern->aper_base; - info->aperture_size = kern->aper_size * 1024 * 1024; - info->memory_allowed = kern->max_memory << PAGE_SHIFT; - info->memory_used = kern->current_memory << PAGE_SHIFT; - info->id_vendor = kern->device->vendor; - info->id_device = kern->device->device; + info->mode = kern->mode; + info->aperture_base = kern->aper_base; + info->aperture_size = kern->aper_size * 1024 * 1024; + info->memory_allowed = kern->max_memory << PAGE_SHIFT; + info->memory_used = kern->current_memory << PAGE_SHIFT; + info->id_vendor = kern->device->vendor; + info->id_device = kern->device->device; return 0; } + EXPORT_SYMBOL(drm_agp_info); int drm_agp_info_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -81,7 +82,7 @@ int drm_agp_info_ioctl(struct inode *inode, struct file *filp, err = drm_agp_info(dev, &info); if (err) return err; - + if (copy_to_user((drm_agp_info_t __user *) arg, &info, sizeof(info))) return -EFAULT; return 0; @@ -91,12 +92,12 @@ int drm_agp_info_ioctl(struct inode *inode, struct file *filp, * Acquire the AGP device. * * \param dev DRM device that is to acquire AGP - * \return zero on success or a negative number on failure. + * \return zero on success or a negative number on failure. * * Verifies the AGP device hasn't been acquired before and calls * \c agp_backend_acquire. */ -int drm_agp_acquire(drm_device_t *dev) +int drm_agp_acquire(drm_device_t * dev) { if (!dev->agp) return -ENODEV; @@ -107,6 +108,7 @@ int drm_agp_acquire(drm_device_t *dev) dev->agp->acquired = 1; return 0; } + EXPORT_SYMBOL(drm_agp_acquire); /** @@ -125,8 +127,8 @@ int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; - - return drm_agp_acquire( (drm_device_t *) priv->head->dev ); + + return drm_agp_acquire((drm_device_t *) priv->head->dev); } /** @@ -137,7 +139,7 @@ int drm_agp_acquire_ioctl(struct inode *inode, struct file *filp, * * Verifies the AGP device has been acquired and calls \c agp_backend_release. */ -int drm_agp_release(drm_device_t *dev) +int drm_agp_release(drm_device_t * dev) { if (!dev->agp || !dev->agp->acquired) return -EINVAL; @@ -145,6 +147,7 @@ int drm_agp_release(drm_device_t *dev) dev->agp->acquired = 0; return 0; } + EXPORT_SYMBOL(drm_agp_release); int drm_agp_release_ioctl(struct inode *inode, struct file *filp, @@ -152,13 +155,13 @@ int drm_agp_release_ioctl(struct inode *inode, struct file *filp, { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - + return drm_agp_release(dev); } /** * Enable the AGP bus. - * + * * \param dev DRM device that has previously acquired AGP. * \param mode Requested AGP mode. * \return zero on success or a negative number on failure. @@ -166,27 +169,27 @@ int drm_agp_release_ioctl(struct inode *inode, struct file *filp, * Verifies the AGP device has been acquired but not enabled, and calls * \c agp_enable. */ -int drm_agp_enable(drm_device_t *dev, drm_agp_mode_t mode) +int drm_agp_enable(drm_device_t * dev, drm_agp_mode_t mode) { if (!dev->agp || !dev->agp->acquired) return -EINVAL; - dev->agp->mode = mode.mode; + dev->agp->mode = mode.mode; agp_enable(dev->agp->bridge, mode.mode); - dev->agp->base = dev->agp->agp_info.aper_base; + dev->agp->base = dev->agp->agp_info.aper_base; dev->agp->enabled = 1; return 0; } + EXPORT_SYMBOL(drm_agp_enable); int drm_agp_enable_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_agp_mode_t mode; - if (copy_from_user(&mode, (drm_agp_mode_t __user *) arg, sizeof(mode))) return -EFAULT; @@ -201,20 +204,20 @@ int drm_agp_enable_ioctl(struct inode *inode, struct file *filp, * \param cmd command. * \param arg pointer to a drm_agp_buffer structure. * \return zero on success or a negative number on failure. - * + * * Verifies the AGP device is present and has been acquired, allocates the * memory via alloc_agp() and creates a drm_agp_mem entry for it. */ int drm_agp_alloc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_agp_buffer_t request; - drm_agp_mem_t *entry; - DRM_AGP_MEM *memory; - unsigned long pages; - u32 type; + drm_agp_mem_t *entry; + DRM_AGP_MEM *memory; + unsigned long pages; + u32 type; drm_agp_buffer_t __user *argp = (void __user *)arg; if (!dev->agp || !dev->agp->acquired) @@ -224,7 +227,7 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, if (!(entry = drm_alloc(sizeof(*entry), DRM_MEM_AGPLISTS))) return -ENOMEM; - memset(entry, 0, sizeof(*entry)); + memset(entry, 0, sizeof(*entry)); pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; type = (u32) request.type; @@ -234,21 +237,21 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, return -ENOMEM; } - entry->handle = (unsigned long)memory->key + 1; - entry->memory = memory; - entry->bound = 0; - entry->pages = pages; - entry->prev = NULL; - entry->next = dev->agp->memory; + entry->handle = (unsigned long)memory->key + 1; + entry->memory = memory; + entry->bound = 0; + entry->pages = pages; + entry->prev = NULL; + entry->next = dev->agp->memory; if (dev->agp->memory) dev->agp->memory->prev = entry; dev->agp->memory = entry; - request.handle = entry->handle; + request.handle = entry->handle; request.physical = memory->physical; if (copy_to_user(argp, &request, sizeof(request))) { - dev->agp->memory = entry->next; + dev->agp->memory = entry->next; dev->agp->memory->prev = NULL; drm_free_agp(memory, pages); drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); @@ -263,11 +266,11 @@ int drm_agp_alloc(struct inode *inode, struct file *filp, * \param dev DRM device structure. * \param handle AGP memory handle. * \return pointer to the drm_agp_mem structure associated with \p handle. - * + * * Walks through drm_agp_head::memory until finding a matching handle. */ -static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, - unsigned long handle) +static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t * dev, + unsigned long handle) { drm_agp_mem_t *entry; @@ -291,17 +294,18 @@ static drm_agp_mem_t *drm_agp_lookup_entry(drm_device_t *dev, * entry and passes it to the unbind_agp() function. */ int drm_agp_unbind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_agp_binding_t request; - drm_agp_mem_t *entry; + drm_agp_mem_t *entry; int ret; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_binding_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -309,7 +313,7 @@ int drm_agp_unbind(struct inode *inode, struct file *filp, return -EINVAL; ret = drm_unbind_agp(entry->memory); if (ret == 0) - entry->bound = 0; + entry->bound = 0; return ret; } @@ -327,18 +331,19 @@ int drm_agp_unbind(struct inode *inode, struct file *filp, * it to bind_agp() function. */ int drm_agp_bind(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_agp_binding_t request; - drm_agp_mem_t *entry; - int retcode; - int page; + drm_agp_mem_t *entry; + int retcode; + int page; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - if (copy_from_user(&request, (drm_agp_binding_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_binding_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -368,16 +373,17 @@ int drm_agp_bind(struct inode *inode, struct file *filp, * and unlinks from the doubly linked list it's inserted in. */ int drm_agp_free(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_agp_buffer_t request; - drm_agp_mem_t *entry; + drm_agp_mem_t *entry; if (!dev->agp || !dev->agp->acquired) return -EINVAL; - if (copy_from_user(&request, (drm_agp_buffer_t __user *)arg, sizeof(request))) + if (copy_from_user + (&request, (drm_agp_buffer_t __user *) arg, sizeof(request))) return -EFAULT; if (!(entry = drm_agp_lookup_entry(dev, request.handle))) return -EINVAL; @@ -403,9 +409,9 @@ int drm_agp_free(struct inode *inode, struct file *filp, * \return pointer to a drm_agp_head structure. * */ -drm_agp_head_t *drm_agp_init(drm_device_t *dev) +drm_agp_head_t *drm_agp_init(drm_device_t * dev) { - drm_agp_head_t *head = NULL; + drm_agp_head_t *head = NULL; if (!(head = drm_alloc(sizeof(*head), DRM_MEM_AGPLISTS))) return NULL; @@ -433,13 +439,14 @@ drm_agp_head_t *drm_agp_init(drm_device_t *dev) } /** Calls agp_allocate_memory() */ -DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type) +DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data * bridge, + size_t pages, u32 type) { return agp_allocate_memory(bridge, pages, type); } /** Calls agp_free_memory() */ -int drm_agp_free_memory(DRM_AGP_MEM *handle) +int drm_agp_free_memory(DRM_AGP_MEM * handle) { if (!handle) return 0; @@ -448,20 +455,21 @@ int drm_agp_free_memory(DRM_AGP_MEM *handle) } /** Calls agp_bind_memory() */ -int drm_agp_bind_memory(DRM_AGP_MEM *handle, off_t start) +int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start) { if (!handle) return -EINVAL; return agp_bind_memory(handle, start); } + EXPORT_SYMBOL(drm_agp_bind_memory); /** Calls agp_unbind_memory() */ -int drm_agp_unbind_memory(DRM_AGP_MEM *handle) +int drm_agp_unbind_memory(DRM_AGP_MEM * handle) { if (!handle) return -EINVAL; return agp_unbind_memory(handle); } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ diff --git a/drivers/char/drm/drm_auth.c b/drivers/char/drm/drm_auth.c index dd140bca8f7..a47b502bc7c 100644 --- a/drivers/char/drm/drm_auth.c +++ b/drivers/char/drm/drm_auth.c @@ -1,5 +1,5 @@ /** - * \file drm_auth.h + * \file drm_auth.c * IOCTLs for authentication * * \author Rickard E. (Rik) Faith @@ -46,7 +46,7 @@ */ static int drm_hash_magic(drm_magic_t magic) { - return magic & (DRM_HASH_SIZE-1); + return magic & (DRM_HASH_SIZE - 1); } /** @@ -59,11 +59,11 @@ static int drm_hash_magic(drm_magic_t magic) * the one with matching magic number, while holding the drm_device::struct_sem * lock. */ -static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) +static drm_file_t *drm_find_file(drm_device_t * dev, drm_magic_t magic) { - drm_file_t *retval = NULL; + drm_file_t *retval = NULL; drm_magic_entry_t *pt; - int hash = drm_hash_magic(magic); + int hash = drm_hash_magic(magic); down(&dev->struct_sem); for (pt = dev->magiclist[hash].head; pt; pt = pt->next) { @@ -78,7 +78,7 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) /** * Adds a magic number. - * + * * \param dev DRM device. * \param priv file private data. * \param magic magic number. @@ -87,28 +87,30 @@ static drm_file_t *drm_find_file(drm_device_t *dev, drm_magic_t magic) * associated the magic number hash key in drm_device::magiclist, while holding * the drm_device::struct_sem lock. */ -static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) +static int drm_add_magic(drm_device_t * dev, drm_file_t * priv, + drm_magic_t magic) { - int hash; + int hash; drm_magic_entry_t *entry; DRM_DEBUG("%d\n", magic); - hash = drm_hash_magic(magic); - entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); - if (!entry) return -ENOMEM; + hash = drm_hash_magic(magic); + entry = drm_alloc(sizeof(*entry), DRM_MEM_MAGIC); + if (!entry) + return -ENOMEM; memset(entry, 0, sizeof(*entry)); entry->magic = magic; - entry->priv = priv; - entry->next = NULL; + entry->priv = priv; + entry->next = NULL; down(&dev->struct_sem); if (dev->magiclist[hash].tail) { dev->magiclist[hash].tail->next = entry; - dev->magiclist[hash].tail = entry; + dev->magiclist[hash].tail = entry; } else { - dev->magiclist[hash].head = entry; - dev->magiclist[hash].tail = entry; + dev->magiclist[hash].head = entry; + dev->magiclist[hash].tail = entry; } up(&dev->struct_sem); @@ -117,19 +119,18 @@ static int drm_add_magic(drm_device_t *dev, drm_file_t *priv, drm_magic_t magic) /** * Remove a magic number. - * + * * \param dev DRM device. * \param magic magic number. * * Searches and unlinks the entry in drm_device::magiclist with the magic * number hash key, while holding the drm_device::struct_sem lock. */ -static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) +static int drm_remove_magic(drm_device_t * dev, drm_magic_t magic) { drm_magic_entry_t *prev = NULL; drm_magic_entry_t *pt; - int hash; - + int hash; DRM_DEBUG("%d\n", magic); hash = drm_hash_magic(magic); @@ -171,21 +172,22 @@ static int drm_remove_magic(drm_device_t *dev, drm_magic_t magic) * filp. */ int drm_getmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { static drm_magic_t sequence = 0; static DEFINE_SPINLOCK(lock); - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_auth_t auth; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_auth_t auth; - /* Find unique magic */ + /* Find unique magic */ if (priv->magic) { auth.magic = priv->magic; } else { do { spin_lock(&lock); - if (!sequence) ++sequence; /* reserve 0 */ + if (!sequence) + ++sequence; /* reserve 0 */ auth.magic = sequence++; spin_unlock(&lock); } while (drm_find_file(dev, auth.magic)); @@ -194,7 +196,7 @@ int drm_getmagic(struct inode *inode, struct file *filp, } DRM_DEBUG("%u\n", auth.magic); - if (copy_to_user((drm_auth_t __user *)arg, &auth, sizeof(auth))) + if (copy_to_user((drm_auth_t __user *) arg, &auth, sizeof(auth))) return -EFAULT; return 0; } @@ -211,14 +213,14 @@ int drm_getmagic(struct inode *inode, struct file *filp, * Checks if \p filp is associated with the magic number passed in \arg. */ int drm_authmagic(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_auth_t auth; - drm_file_t *file; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_auth_t auth; + drm_file_t *file; - if (copy_from_user(&auth, (drm_auth_t __user *)arg, sizeof(auth))) + if (copy_from_user(&auth, (drm_auth_t __user *) arg, sizeof(auth))) return -EFAULT; DRM_DEBUG("%u\n", auth.magic); if ((file = drm_find_file(dev, auth.magic))) { diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c index f28e70ae660..bb989ccea5a 100644 --- a/drivers/char/drm/drm_bufs.c +++ b/drivers/char/drm/drm_bufs.c @@ -1,7 +1,7 @@ /** - * \file drm_bufs.h + * \file drm_bufs.c * Generic buffer template - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -36,20 +36,22 @@ #include #include "drmP.h" -unsigned long drm_get_resource_start(drm_device_t *dev, unsigned int resource) +unsigned long drm_get_resource_start(drm_device_t * dev, unsigned int resource) { return pci_resource_start(dev->pdev, resource); } + EXPORT_SYMBOL(drm_get_resource_start); -unsigned long drm_get_resource_len(drm_device_t *dev, unsigned int resource) +unsigned long drm_get_resource_len(drm_device_t * dev, unsigned int resource) { return pci_resource_len(dev->pdev, resource); } + EXPORT_SYMBOL(drm_get_resource_len); -static drm_map_list_t *drm_find_matching_map(drm_device_t *dev, - drm_local_map_t *map) +static drm_map_list_t *drm_find_matching_map(drm_device_t * dev, + drm_local_map_t * map) { struct list_head *list; @@ -71,7 +73,8 @@ static drm_map_list_t *drm_find_matching_map(drm_device_t *dev, #define END_RANGE 0x40000000 #ifdef _LP64 -static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev) +static __inline__ unsigned int HandleID(unsigned long lhandle, + drm_device_t * dev) { static unsigned int map32_handle = START_RANGE; unsigned int hash; @@ -81,12 +84,12 @@ static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev map32_handle += PAGE_SIZE; if (map32_handle > END_RANGE) map32_handle = START_RANGE; - } else + } else hash = lhandle; while (1) { drm_map_list_t *_entry; - list_for_each_entry(_entry, &dev->maplist->head,head) { + list_for_each_entry(_entry, &dev->maplist->head, head) { if (_entry->user_token == hash) break; } @@ -116,14 +119,14 @@ static __inline__ unsigned int HandleID(unsigned long lhandle, drm_device_t *dev */ int drm_addmap_core(drm_device_t * dev, unsigned int offset, unsigned int size, drm_map_type_t type, - drm_map_flags_t flags, drm_map_list_t **maplist) + drm_map_flags_t flags, drm_map_list_t ** maplist) { drm_map_t *map; drm_map_list_t *list; drm_dma_handle_t *dmah; - map = drm_alloc( sizeof(*map), DRM_MEM_MAPS ); - if ( !map ) + map = drm_alloc(sizeof(*map), DRM_MEM_MAPS); + if (!map) return -ENOMEM; map->offset = offset; @@ -135,26 +138,26 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, * book keeping information about shared memory to allow for removal * when processes fork. */ - if ( (map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + if ((map->flags & _DRM_REMOVABLE) && map->type != _DRM_SHM) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } - DRM_DEBUG( "offset = 0x%08lx, size = 0x%08lx, type = %d\n", - map->offset, map->size, map->type ); - if ( (map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK)) ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + DRM_DEBUG("offset = 0x%08lx, size = 0x%08lx, type = %d\n", + map->offset, map->size, map->type); + if ((map->offset & (~PAGE_MASK)) || (map->size & (~PAGE_MASK))) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } - map->mtrr = -1; + map->mtrr = -1; map->handle = NULL; - switch ( map->type ) { + switch (map->type) { case _DRM_REGISTERS: case _DRM_FRAME_BUFFER: #if !defined(__sparc__) && !defined(__alpha__) && !defined(__ia64__) && !defined(__powerpc64__) && !defined(__x86_64__) - if ( map->offset + map->size < map->offset || - map->offset < virt_to_phys(high_memory) ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + if (map->offset + map->size < map->offset || + map->offset < virt_to_phys(high_memory)) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } #endif @@ -169,8 +172,9 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, if (list != NULL) { if (list->map->size != map->size) { DRM_DEBUG("Matching maps of type %d with " - "mismatched sizes, (%ld vs %ld)\n", - map->type, map->size, list->map->size); + "mismatched sizes, (%ld vs %ld)\n", + map->type, map->size, + list->map->size); list->map->size = map->size; } @@ -180,35 +184,33 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, } if (drm_core_has_MTRR(dev)) { - if ( map->type == _DRM_FRAME_BUFFER || - (map->flags & _DRM_WRITE_COMBINING) ) { - map->mtrr = mtrr_add( map->offset, map->size, - MTRR_TYPE_WRCOMB, 1 ); + if (map->type == _DRM_FRAME_BUFFER || + (map->flags & _DRM_WRITE_COMBINING)) { + map->mtrr = mtrr_add(map->offset, map->size, + MTRR_TYPE_WRCOMB, 1); } } if (map->type == _DRM_REGISTERS) - map->handle = drm_ioremap( map->offset, map->size, - dev ); + map->handle = drm_ioremap(map->offset, map->size, dev); break; case _DRM_SHM: map->handle = vmalloc_32(map->size); - DRM_DEBUG( "%lu %d %p\n", - map->size, drm_order( map->size ), map->handle ); - if ( !map->handle ) { - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + DRM_DEBUG("%lu %d %p\n", + map->size, drm_order(map->size), map->handle); + if (!map->handle) { + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -ENOMEM; } map->offset = (unsigned long)map->handle; - if ( map->flags & _DRM_CONTAINS_LOCK ) { + if (map->flags & _DRM_CONTAINS_LOCK) { /* Prevent a 2nd X Server from creating a 2nd lock */ if (dev->lock.hw_lock != NULL) { - vfree( map->handle ); - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + vfree(map->handle); + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EBUSY; } - dev->sigdata.lock = - dev->lock.hw_lock = map->handle; /* Pointer to lock */ + dev->sigdata.lock = dev->lock.hw_lock = map->handle; /* Pointer to lock */ } break; case _DRM_AGP: @@ -217,7 +219,7 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, map->offset += dev->hose->mem_space->start; #endif map->offset += dev->agp->base; - map->mtrr = dev->agp->agp_mtrr; /* for getmap */ + map->mtrr = dev->agp->agp_mtrr; /* for getmap */ } break; case _DRM_SCATTER_GATHER: @@ -227,7 +229,7 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, } map->offset += (unsigned long)dev->sg->virtual; break; - case _DRM_CONSISTENT: + case _DRM_CONSISTENT: /* dma_addr_t is 64bit on i386 with CONFIG_HIGHMEM64G, * As we're limiting the address to 2^32-1 (or less), * casting it down to 32 bits is no problem, but we @@ -242,12 +244,12 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, kfree(dmah); break; default: - drm_free( map, sizeof(*map), DRM_MEM_MAPS ); + drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } list = drm_alloc(sizeof(*list), DRM_MEM_MAPS); - if(!list) { + if (!list) { drm_free(map, sizeof(*map), DRM_MEM_MAPS); return -EINVAL; } @@ -258,18 +260,18 @@ int drm_addmap_core(drm_device_t * dev, unsigned int offset, list_add(&list->head, &dev->maplist->head); /* Assign a 32-bit handle */ /* We do it here so that dev->struct_sem protects the increment */ - list->user_token = HandleID(map->type==_DRM_SHM + list->user_token = HandleID(map->type == _DRM_SHM ? (unsigned long)map->handle : map->offset, dev); - up(&dev->struct_sem); + up(&dev->struct_sem); *maplist = list; return 0; } -int drm_addmap(drm_device_t *dev, unsigned int offset, +int drm_addmap(drm_device_t * dev, unsigned int offset, unsigned int size, drm_map_type_t type, - drm_map_flags_t flags, drm_local_map_t **map_ptr) + drm_map_flags_t flags, drm_local_map_t ** map_ptr) { drm_map_list_t *list; int rc; @@ -279,6 +281,7 @@ int drm_addmap(drm_device_t *dev, unsigned int offset, *map_ptr = list->map; return rc; } + EXPORT_SYMBOL(drm_addmap); int drm_addmap_ioctl(struct inode *inode, struct file *filp, @@ -294,14 +297,14 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp, if (!(filp->f_mode & 3)) return -EACCES; /* Require read/write */ - if (copy_from_user(& map, argp, sizeof(map))) { + if (copy_from_user(&map, argp, sizeof(map))) { return -EFAULT; } err = drm_addmap_core(dev, map.offset, map.size, map.type, map.flags, &maplist); - if (err) + if (err) return err; if (copy_to_user(argp, maplist->map, sizeof(drm_map_t))) @@ -311,7 +314,6 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp, return 0; } - /** * Remove a map private from list and deallocate resources if the mapping * isn't in use. @@ -328,7 +330,7 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp, * * \sa drm_addmap */ -int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map) +int drm_rmmap_locked(drm_device_t * dev, drm_local_map_t * map) { struct list_head *list; drm_map_list_t *r_list = NULL; @@ -359,9 +361,8 @@ int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map) case _DRM_FRAME_BUFFER: if (drm_core_has_MTRR(dev) && map->mtrr >= 0) { int retcode; - retcode = mtrr_del(map->mtrr, map->offset, - map->size); - DRM_DEBUG ("mtrr_del=%d\n", retcode); + retcode = mtrr_del(map->mtrr, map->offset, map->size); + DRM_DEBUG("mtrr_del=%d\n", retcode); } break; case _DRM_SHM: @@ -381,9 +382,10 @@ int drm_rmmap_locked(drm_device_t *dev, drm_local_map_t *map) return 0; } + EXPORT_SYMBOL(drm_rmmap_locked); -int drm_rmmap(drm_device_t *dev, drm_local_map_t *map) +int drm_rmmap(drm_device_t * dev, drm_local_map_t * map) { int ret; @@ -393,6 +395,7 @@ int drm_rmmap(drm_device_t *dev, drm_local_map_t *map) return ret; } + EXPORT_SYMBOL(drm_rmmap); /* The rmmap ioctl appears to be unnecessary. All mappings are torn down on @@ -414,7 +417,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp, struct list_head *list; int ret; - if (copy_from_user(&request, (drm_map_t __user *)arg, sizeof(request))) { + if (copy_from_user(&request, (drm_map_t __user *) arg, sizeof(request))) { return -EFAULT; } @@ -423,7 +426,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp, drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); if (r_list->map && - r_list->user_token == (unsigned long) request.handle && + r_list->user_token == (unsigned long)request.handle && r_list->map->flags & _DRM_REMOVABLE) { map = r_list->map; break; @@ -462,7 +465,7 @@ int drm_rmmap_ioctl(struct inode *inode, struct file *filp, * * Frees any pages and buffers associated with the given entry. */ -static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) +static void drm_cleanup_buf_error(drm_device_t * dev, drm_buf_entry_t * entry) { int i; @@ -470,30 +473,27 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) for (i = 0; i < entry->seg_count; i++) { if (entry->seglist[i]) { drm_free_pages(entry->seglist[i], - entry->page_order, - DRM_MEM_DMA); + entry->page_order, DRM_MEM_DMA); } } drm_free(entry->seglist, - entry->seg_count * - sizeof(*entry->seglist), - DRM_MEM_SEGS); + entry->seg_count * + sizeof(*entry->seglist), DRM_MEM_SEGS); entry->seg_count = 0; } - if (entry->buf_count) { - for (i = 0; i < entry->buf_count; i++) { + if (entry->buf_count) { + for (i = 0; i < entry->buf_count; i++) { if (entry->buflist[i].dev_private) { drm_free(entry->buflist[i].dev_private, - entry->buflist[i].dev_priv_size, - DRM_MEM_BUFS); + entry->buflist[i].dev_priv_size, + DRM_MEM_BUFS); } } drm_free(entry->buflist, - entry->buf_count * - sizeof(*entry->buflist), - DRM_MEM_BUFS); + entry->buf_count * + sizeof(*entry->buflist), DRM_MEM_BUFS); entry->buf_count = 0; } @@ -506,12 +506,12 @@ static void drm_cleanup_buf_error(drm_device_t *dev, drm_buf_entry_t *entry) * \param dev drm_device_t to which the buffers are to be added. * \param request pointer to a drm_buf_desc_t describing the request. * \return zero on success or a negative number on failure. - * + * * After some sanity checks creates a drm_buf structure for each buffer and * reallocates the buffer list of the same size order to accommodate the new * buffers. */ -int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request) +int drm_addbufs_agp(drm_device_t * dev, drm_buf_desc_t * request) { drm_device_dma_t *dma = dev->dma; drm_buf_entry_t *entry; @@ -528,144 +528,145 @@ int drm_addbufs_agp(drm_device_t *dev, drm_buf_desc_t *request) int i; drm_buf_t **temp_buflist; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; count = request->count; order = drm_order(request->size); size = 1 << order; - alignment = (request->flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + alignment = (request->flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; byte_count = 0; agp_offset = dev->agp->base + request->agp_start; - DRM_DEBUG( "count: %d\n", count ); - DRM_DEBUG( "order: %d\n", order ); - DRM_DEBUG( "size: %d\n", size ); - DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); - DRM_DEBUG( "alignment: %d\n", alignment ); - DRM_DEBUG( "page_order: %d\n", page_order ); - DRM_DEBUG( "total: %d\n", total ); + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %lu\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); - return -ENOMEM; /* May only call once for each order */ + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); entry->buf_size = size; entry->page_order = page_order; offset = 0; - while ( entry->buf_count < count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; + while (entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; - buf->offset = (dma->byte_count + offset); + buf->offset = (dma->byte_count + offset); buf->bus_address = agp_offset + offset; buf->address = (void *)(agp_offset + offset); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->driver->dev_priv_size; - buf->dev_private = drm_alloc( buf->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); offset += alignment; entry->buf_count++; byte_count += PAGE_SIZE << page_order; } - DRM_DEBUG( "byte_count: %d\n", byte_count ); + DRM_DEBUG("byte_count: %d\n", byte_count); - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); - if(!temp_buflist) { + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); + if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } dma->buf_count += entry->buf_count; dma->byte_count += byte_count; - DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); - DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); + DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); - up( &dev->struct_sem ); + up(&dev->struct_sem); request->count = entry->buf_count; request->size = size; dma->flags = _DRM_DMA_USE_AGP; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } + EXPORT_SYMBOL(drm_addbufs_agp); -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ -int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request) +int drm_addbufs_pci(drm_device_t * dev, drm_buf_desc_t * request) { drm_device_dma_t *dma = dev->dma; int count; @@ -684,178 +685,174 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request) unsigned long *temp_pagelist; drm_buf_t **temp_buflist; - if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_PCI_DMA)) + return -EINVAL; + if (!dma) + return -EINVAL; count = request->count; order = drm_order(request->size); size = 1 << order; - DRM_DEBUG( "count=%d, size=%d (%d), order=%d, queue_count=%d\n", - request->count, request->size, size, - order, dev->queue_count ); + DRM_DEBUG("count=%d, size=%d (%d), order=%d, queue_count=%d\n", + request->count, request->size, size, order, dev->queue_count); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ alignment = (request->flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); - - entry->seglist = drm_alloc( count * sizeof(*entry->seglist), - DRM_MEM_SEGS ); - if ( !entry->seglist ) { - drm_free( entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); + + entry->seglist = drm_alloc(count * sizeof(*entry->seglist), + DRM_MEM_SEGS); + if (!entry->seglist) { + drm_free(entry->buflist, + count * sizeof(*entry->buflist), DRM_MEM_BUFS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->seglist, 0, count * sizeof(*entry->seglist) ); + memset(entry->seglist, 0, count * sizeof(*entry->seglist)); /* Keep the original pagelist until we know all the allocations * have succeeded */ - temp_pagelist = drm_alloc( (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); + temp_pagelist = drm_alloc((dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); if (!temp_pagelist) { - drm_free( entry->buflist, - count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - drm_free( entry->seglist, - count * sizeof(*entry->seglist), - DRM_MEM_SEGS ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_free(entry->buflist, + count * sizeof(*entry->buflist), DRM_MEM_BUFS); + drm_free(entry->seglist, + count * sizeof(*entry->seglist), DRM_MEM_SEGS); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } memcpy(temp_pagelist, - dma->pagelist, - dma->page_count * sizeof(*dma->pagelist)); - DRM_DEBUG( "pagelist: %d entries\n", - dma->page_count + (count << page_order) ); + dma->pagelist, dma->page_count * sizeof(*dma->pagelist)); + DRM_DEBUG("pagelist: %d entries\n", + dma->page_count + (count << page_order)); - entry->buf_size = size; + entry->buf_size = size; entry->page_order = page_order; byte_count = 0; page_count = 0; - while ( entry->buf_count < count ) { - page = drm_alloc_pages( page_order, DRM_MEM_DMA ); - if ( !page ) { + while (entry->buf_count < count) { + page = drm_alloc_pages(page_order, DRM_MEM_DMA); + if (!page) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; entry->seg_count = count; drm_cleanup_buf_error(dev, entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_free(temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } entry->seglist[entry->seg_count++] = page; - for ( i = 0 ; i < (1 << page_order) ; i++ ) { - DRM_DEBUG( "page %d @ 0x%08lx\n", - dma->page_count + page_count, - page + PAGE_SIZE * i ); + for (i = 0; i < (1 << page_order); i++) { + DRM_DEBUG("page %d @ 0x%08lx\n", + dma->page_count + page_count, + page + PAGE_SIZE * i); temp_pagelist[dma->page_count + page_count++] - = page + PAGE_SIZE * i; + = page + PAGE_SIZE * i; } - for ( offset = 0 ; - offset + size <= total && entry->buf_count < count ; - offset += alignment, ++entry->buf_count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; - buf->offset = (dma->byte_count + byte_count + offset); + for (offset = 0; + offset + size <= total && entry->buf_count < count; + offset += alignment, ++entry->buf_count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; + buf->offset = (dma->byte_count + byte_count + offset); buf->address = (void *)(page + offset); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->driver->dev_priv_size; - buf->dev_private = drm_alloc( buf->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(buf->dev_priv_size, + DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; entry->seg_count = count; - drm_cleanup_buf_error(dev,entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + drm_free(temp_pagelist, + (dma->page_count + + (count << page_order)) + * sizeof(*dma->pagelist), + DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", + entry->buf_count, buf->address); } byte_count += PAGE_SIZE << page_order; } - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - drm_free( temp_pagelist, - (dma->page_count + (count << page_order)) - * sizeof(*dma->pagelist), - DRM_MEM_PAGES ); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + drm_free(temp_pagelist, + (dma->page_count + (count << page_order)) + * sizeof(*dma->pagelist), DRM_MEM_PAGES); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } @@ -864,8 +861,8 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request) */ if (dma->page_count) { drm_free(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - DRM_MEM_PAGES); + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); } dma->pagelist = temp_pagelist; @@ -874,18 +871,19 @@ int drm_addbufs_pci(drm_device_t *dev, drm_buf_desc_t *request) dma->page_count += entry->seg_count << page_order; dma->byte_count += PAGE_SIZE * (entry->seg_count << page_order); - up( &dev->struct_sem ); + up(&dev->struct_sem); request->count = entry->buf_count; request->size = size; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } + EXPORT_SYMBOL(drm_addbufs_pci); -static int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request) +static int drm_addbufs_sg(drm_device_t * dev, drm_buf_desc_t * request) { drm_device_dma_t *dma = dev->dma; drm_buf_entry_t *entry; @@ -902,146 +900,147 @@ static int drm_addbufs_sg(drm_device_t *dev, drm_buf_desc_t *request) int i; drm_buf_t **temp_buflist; - if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - - if ( !dma ) return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_SG)) + return -EINVAL; + + if (!dma) + return -EINVAL; count = request->count; order = drm_order(request->size); size = 1 << order; - alignment = (request->flags & _DRM_PAGE_ALIGN) - ? PAGE_ALIGN(size) : size; + alignment = (request->flags & _DRM_PAGE_ALIGN) + ? PAGE_ALIGN(size) : size; page_order = order - PAGE_SHIFT > 0 ? order - PAGE_SHIFT : 0; total = PAGE_SIZE << page_order; byte_count = 0; agp_offset = request->agp_start; - DRM_DEBUG( "count: %d\n", count ); - DRM_DEBUG( "order: %d\n", order ); - DRM_DEBUG( "size: %d\n", size ); - DRM_DEBUG( "agp_offset: %lu\n", agp_offset ); - DRM_DEBUG( "alignment: %d\n", alignment ); - DRM_DEBUG( "page_order: %d\n", page_order ); - DRM_DEBUG( "total: %d\n", total ); + DRM_DEBUG("count: %d\n", count); + DRM_DEBUG("order: %d\n", order); + DRM_DEBUG("size: %d\n", size); + DRM_DEBUG("agp_offset: %lu\n", agp_offset); + DRM_DEBUG("alignment: %d\n", alignment); + DRM_DEBUG("page_order: %d\n", page_order); + DRM_DEBUG("total: %d\n", total); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; - if ( dev->queue_count ) return -EBUSY; /* Not while in use */ + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; + if (dev->queue_count) + return -EBUSY; /* Not while in use */ - spin_lock( &dev->count_lock ); - if ( dev->buf_use ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (dev->buf_use) { + spin_unlock(&dev->count_lock); return -EBUSY; } - atomic_inc( &dev->buf_alloc ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->buf_alloc); + spin_unlock(&dev->count_lock); - down( &dev->struct_sem ); + down(&dev->struct_sem); entry = &dma->bufs[order]; - if ( entry->buf_count ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); - return -ENOMEM; /* May only call once for each order */ + if (entry->buf_count) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); + return -ENOMEM; /* May only call once for each order */ } if (count < 0 || count > 4096) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -EINVAL; } - entry->buflist = drm_alloc( count * sizeof(*entry->buflist), - DRM_MEM_BUFS ); - if ( !entry->buflist ) { - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + entry->buflist = drm_alloc(count * sizeof(*entry->buflist), + DRM_MEM_BUFS); + if (!entry->buflist) { + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( entry->buflist, 0, count * sizeof(*entry->buflist) ); + memset(entry->buflist, 0, count * sizeof(*entry->buflist)); entry->buf_size = size; entry->page_order = page_order; offset = 0; - while ( entry->buf_count < count ) { - buf = &entry->buflist[entry->buf_count]; - buf->idx = dma->buf_count + entry->buf_count; - buf->total = alignment; - buf->order = order; - buf->used = 0; + while (entry->buf_count < count) { + buf = &entry->buflist[entry->buf_count]; + buf->idx = dma->buf_count + entry->buf_count; + buf->total = alignment; + buf->order = order; + buf->used = 0; - buf->offset = (dma->byte_count + offset); + buf->offset = (dma->byte_count + offset); buf->bus_address = agp_offset + offset; - buf->address = (void *)(agp_offset + offset + buf->address = (void *)(agp_offset + offset + (unsigned long)dev->sg->virtual); - buf->next = NULL; + buf->next = NULL; buf->waiting = 0; buf->pending = 0; - init_waitqueue_head( &buf->dma_wait ); - buf->filp = NULL; + init_waitqueue_head(&buf->dma_wait); + buf->filp = NULL; buf->dev_priv_size = dev->driver->dev_priv_size; - buf->dev_private = drm_alloc( buf->dev_priv_size, - DRM_MEM_BUFS ); - if(!buf->dev_private) { + buf->dev_private = drm_alloc(buf->dev_priv_size, DRM_MEM_BUFS); + if (!buf->dev_private) { /* Set count correctly so we free the proper amount. */ entry->buf_count = count; - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } - memset( buf->dev_private, 0, buf->dev_priv_size ); + memset(buf->dev_private, 0, buf->dev_priv_size); - DRM_DEBUG( "buffer %d @ %p\n", - entry->buf_count, buf->address ); + DRM_DEBUG("buffer %d @ %p\n", entry->buf_count, buf->address); offset += alignment; entry->buf_count++; byte_count += PAGE_SIZE << page_order; } - DRM_DEBUG( "byte_count: %d\n", byte_count ); + DRM_DEBUG("byte_count: %d\n", byte_count); - temp_buflist = drm_realloc( dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - (dma->buf_count + entry->buf_count) - * sizeof(*dma->buflist), - DRM_MEM_BUFS ); - if(!temp_buflist) { + temp_buflist = drm_realloc(dma->buflist, + dma->buf_count * sizeof(*dma->buflist), + (dma->buf_count + entry->buf_count) + * sizeof(*dma->buflist), DRM_MEM_BUFS); + if (!temp_buflist) { /* Free the entry because it isn't valid */ - drm_cleanup_buf_error(dev,entry); - up( &dev->struct_sem ); - atomic_dec( &dev->buf_alloc ); + drm_cleanup_buf_error(dev, entry); + up(&dev->struct_sem); + atomic_dec(&dev->buf_alloc); return -ENOMEM; } dma->buflist = temp_buflist; - for ( i = 0 ; i < entry->buf_count ; i++ ) { + for (i = 0; i < entry->buf_count; i++) { dma->buflist[i + dma->buf_count] = &entry->buflist[i]; } dma->buf_count += entry->buf_count; dma->byte_count += byte_count; - DRM_DEBUG( "dma->buf_count : %d\n", dma->buf_count ); - DRM_DEBUG( "entry->buf_count : %d\n", entry->buf_count ); + DRM_DEBUG("dma->buf_count : %d\n", dma->buf_count); + DRM_DEBUG("entry->buf_count : %d\n", entry->buf_count); - up( &dev->struct_sem ); + up(&dev->struct_sem); request->count = entry->buf_count; request->size = size; dma->flags = _DRM_DMA_USE_SG; - atomic_dec( &dev->buf_alloc ); + atomic_dec(&dev->buf_alloc); return 0; } -static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request) +static int drm_addbufs_fb(drm_device_t * dev, drm_buf_desc_t * request) { drm_device_dma_t *dma = dev->dma; drm_buf_entry_t *entry; @@ -1060,7 +1059,7 @@ static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request) if (!drm_core_check_feature(dev, DRIVER_FB_DMA)) return -EINVAL; - + if (!dma) return -EINVAL; @@ -1210,43 +1209,41 @@ static int drm_addbufs_fb(drm_device_t *dev, drm_buf_desc_t *request) * addbufs_sg() or addbufs_pci() for AGP, scatter-gather or consistent * PCI memory respectively. */ -int drm_addbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_buf_desc_t request; drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; int ret; - + if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( copy_from_user( &request, (drm_buf_desc_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, (drm_buf_desc_t __user *) arg, + sizeof(request))) return -EFAULT; #if __OS_HAS_AGP - if ( request.flags & _DRM_AGP_BUFFER ) - ret=drm_addbufs_agp(dev, &request); + if (request.flags & _DRM_AGP_BUFFER) + ret = drm_addbufs_agp(dev, &request); else #endif - if ( request.flags & _DRM_SG_BUFFER ) - ret=drm_addbufs_sg(dev, &request); - else if ( request.flags & _DRM_FB_BUFFER) - ret=drm_addbufs_fb(dev, &request); + if (request.flags & _DRM_SG_BUFFER) + ret = drm_addbufs_sg(dev, &request); + else if (request.flags & _DRM_FB_BUFFER) + ret = drm_addbufs_fb(dev, &request); else - ret=drm_addbufs_pci(dev, &request); + ret = drm_addbufs_pci(dev, &request); - if (ret==0) { - if (copy_to_user((void __user *)arg, &request, - sizeof(request))) { + if (ret == 0) { + if (copy_to_user((void __user *)arg, &request, sizeof(request))) { ret = -EFAULT; } } return ret; } - /** * Get information about the buffer mappings. * @@ -1264,8 +1261,8 @@ int drm_addbufs( struct inode *inode, struct file *filp, * lock, preventing of allocating more buffers after this call. Information * about each requested buffer is then copied into user space. */ -int drm_infobufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_infobufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1278,58 +1275,61 @@ int drm_infobufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - spin_lock( &dev->count_lock ); - if ( atomic_read( &dev->buf_alloc ) ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); return -EBUSY; } ++dev->buf_use; /* Can't allocate more after this call */ - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { - if ( dma->bufs[i].buf_count ) ++count; + for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { + if (dma->bufs[i].buf_count) + ++count; } - DRM_DEBUG( "count = %d\n", count ); + DRM_DEBUG("count = %d\n", count); - if ( request.count >= count ) { - for ( i = 0, count = 0 ; i < DRM_MAX_ORDER + 1 ; i++ ) { - if ( dma->bufs[i].buf_count ) { - drm_buf_desc_t __user *to = &request.list[count]; + if (request.count >= count) { + for (i = 0, count = 0; i < DRM_MAX_ORDER + 1; i++) { + if (dma->bufs[i].buf_count) { + drm_buf_desc_t __user *to = + &request.list[count]; drm_buf_entry_t *from = &dma->bufs[i]; drm_freelist_t *list = &dma->bufs[i].freelist; - if ( copy_to_user( &to->count, - &from->buf_count, - sizeof(from->buf_count) ) || - copy_to_user( &to->size, - &from->buf_size, - sizeof(from->buf_size) ) || - copy_to_user( &to->low_mark, - &list->low_mark, - sizeof(list->low_mark) ) || - copy_to_user( &to->high_mark, - &list->high_mark, - sizeof(list->high_mark) ) ) + if (copy_to_user(&to->count, + &from->buf_count, + sizeof(from->buf_count)) || + copy_to_user(&to->size, + &from->buf_size, + sizeof(from->buf_size)) || + copy_to_user(&to->low_mark, + &list->low_mark, + sizeof(list->low_mark)) || + copy_to_user(&to->high_mark, + &list->high_mark, + sizeof(list->high_mark))) return -EFAULT; - DRM_DEBUG( "%d %d %d %d %d\n", - i, - dma->bufs[i].buf_count, - dma->bufs[i].buf_size, - dma->bufs[i].freelist.low_mark, - dma->bufs[i].freelist.high_mark ); + DRM_DEBUG("%d %d %d %d %d\n", + i, + dma->bufs[i].buf_count, + dma->bufs[i].buf_size, + dma->bufs[i].freelist.low_mark, + dma->bufs[i].freelist.high_mark); ++count; } } } request.count = count; - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; return 0; @@ -1349,8 +1349,8 @@ int drm_infobufs( struct inode *inode, struct file *filp, * * \note This ioctl is deprecated and mostly never used. */ -int drm_markbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_markbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1362,44 +1362,45 @@ int drm_markbufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, - (drm_buf_desc_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_buf_desc_t __user *) arg, sizeof(request))) return -EFAULT; - DRM_DEBUG( "%d, %d, %d\n", - request.size, request.low_mark, request.high_mark ); - order = drm_order( request.size ); - if ( order < DRM_MIN_ORDER || order > DRM_MAX_ORDER ) return -EINVAL; + DRM_DEBUG("%d, %d, %d\n", + request.size, request.low_mark, request.high_mark); + order = drm_order(request.size); + if (order < DRM_MIN_ORDER || order > DRM_MAX_ORDER) + return -EINVAL; entry = &dma->bufs[order]; - if ( request.low_mark < 0 || request.low_mark > entry->buf_count ) + if (request.low_mark < 0 || request.low_mark > entry->buf_count) return -EINVAL; - if ( request.high_mark < 0 || request.high_mark > entry->buf_count ) + if (request.high_mark < 0 || request.high_mark > entry->buf_count) return -EINVAL; - entry->freelist.low_mark = request.low_mark; + entry->freelist.low_mark = request.low_mark; entry->freelist.high_mark = request.high_mark; return 0; } /** - * Unreserve the buffers in list, previously reserved using drmDMA. + * Unreserve the buffers in list, previously reserved using drmDMA. * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg pointer to a drm_buf_free structure. * \return zero on success or a negative number on failure. - * + * * Calls free_buffer() for each used buffer. * This function is primarily used for debugging. */ -int drm_freebufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_freebufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1412,31 +1413,29 @@ int drm_freebufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - if ( copy_from_user( &request, - (drm_buf_free_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_buf_free_t __user *) arg, sizeof(request))) return -EFAULT; - DRM_DEBUG( "%d\n", request.count ); - for ( i = 0 ; i < request.count ; i++ ) { - if ( copy_from_user( &idx, - &request.list[i], - sizeof(idx) ) ) + DRM_DEBUG("%d\n", request.count); + for (i = 0; i < request.count; i++) { + if (copy_from_user(&idx, &request.list[i], sizeof(idx))) return -EFAULT; - if ( idx < 0 || idx >= dma->buf_count ) { - DRM_ERROR( "Index %d (of %d max)\n", - idx, dma->buf_count - 1 ); + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("Index %d (of %d max)\n", + idx, dma->buf_count - 1); return -EINVAL; } buf = dma->buflist[idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "Process %d freeing buffer not owned\n", - current->pid ); + if (buf->filp != filp) { + DRM_ERROR("Process %d freeing buffer not owned\n", + current->pid); return -EINVAL; } - drm_free_buffer( dev, buf ); + drm_free_buffer(dev, buf); } return 0; @@ -1455,8 +1454,8 @@ int drm_freebufs( struct inode *inode, struct file *filp, * about each buffer into user space. The PCI buffers are already mapped on the * addbufs_pci() call. */ -int drm_mapbufs( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_mapbufs(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1472,86 +1471,84 @@ int drm_mapbufs( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; - if ( !dma ) return -EINVAL; + if (!dma) + return -EINVAL; - spin_lock( &dev->count_lock ); - if ( atomic_read( &dev->buf_alloc ) ) { - spin_unlock( &dev->count_lock ); + spin_lock(&dev->count_lock); + if (atomic_read(&dev->buf_alloc)) { + spin_unlock(&dev->count_lock); return -EBUSY; } dev->buf_use++; /* Can't allocate more after this call */ - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - if ( request.count >= dma->buf_count ) { + if (request.count >= dma->buf_count) { if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP)) - || (drm_core_check_feature(dev, DRIVER_SG) + || (drm_core_check_feature(dev, DRIVER_SG) && (dma->flags & _DRM_DMA_USE_SG)) || (drm_core_check_feature(dev, DRIVER_FB_DMA) && (dma->flags & _DRM_DMA_USE_FB))) { drm_map_t *map = dev->agp_buffer_map; unsigned long token = dev->agp_buffer_token; - if ( !map ) { + if (!map) { retcode = -EINVAL; goto done; } - down_write( ¤t->mm->mmap_sem ); - virtual = do_mmap( filp, 0, map->size, - PROT_READ | PROT_WRITE, - MAP_SHARED, - token ); - up_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, map->size, + PROT_READ | PROT_WRITE, + MAP_SHARED, token); + up_write(¤t->mm->mmap_sem); } else { - down_write( ¤t->mm->mmap_sem ); - virtual = do_mmap( filp, 0, dma->byte_count, - PROT_READ | PROT_WRITE, - MAP_SHARED, 0 ); - up_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); + virtual = do_mmap(filp, 0, dma->byte_count, + PROT_READ | PROT_WRITE, + MAP_SHARED, 0); + up_write(¤t->mm->mmap_sem); } - if ( virtual > -1024UL ) { + if (virtual > -1024UL) { /* Real error */ retcode = (signed long)virtual; goto done; } request.virtual = (void __user *)virtual; - for ( i = 0 ; i < dma->buf_count ; i++ ) { - if ( copy_to_user( &request.list[i].idx, - &dma->buflist[i]->idx, - sizeof(request.list[0].idx) ) ) { + for (i = 0; i < dma->buf_count; i++) { + if (copy_to_user(&request.list[i].idx, + &dma->buflist[i]->idx, + sizeof(request.list[0].idx))) { retcode = -EFAULT; goto done; } - if ( copy_to_user( &request.list[i].total, - &dma->buflist[i]->total, - sizeof(request.list[0].total) ) ) { + if (copy_to_user(&request.list[i].total, + &dma->buflist[i]->total, + sizeof(request.list[0].total))) { retcode = -EFAULT; goto done; } - if ( copy_to_user( &request.list[i].used, - &zero, - sizeof(zero) ) ) { + if (copy_to_user(&request.list[i].used, + &zero, sizeof(zero))) { retcode = -EFAULT; goto done; } - address = virtual + dma->buflist[i]->offset; /* *** */ - if ( copy_to_user( &request.list[i].address, - &address, - sizeof(address) ) ) { + address = virtual + dma->buflist[i]->offset; /* *** */ + if (copy_to_user(&request.list[i].address, + &address, sizeof(address))) { retcode = -EFAULT; goto done; } } } - done: + done: request.count = dma->buf_count; - DRM_DEBUG( "%d buffers, retcode = %d\n", request.count, retcode ); + DRM_DEBUG("%d buffers, retcode = %d\n", request.count, retcode); - if ( copy_to_user( argp, &request, sizeof(request) ) ) + if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; return retcode; @@ -1560,23 +1557,23 @@ int drm_mapbufs( struct inode *inode, struct file *filp, /** * Compute size order. Returns the exponent of the smaller power of two which * is greater or equal to given number. - * + * * \param size size. * \return order. * * \todo Can be made faster. */ -int drm_order( unsigned long size ) +int drm_order(unsigned long size) { int order; unsigned long tmp; - for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) - ; + for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ; if (size & (size - 1)) ++order; return order; } + EXPORT_SYMBOL(drm_order); diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c index 502892794c1..6380127be28 100644 --- a/drivers/char/drm/drm_context.c +++ b/drivers/char/drm/drm_context.c @@ -1,7 +1,7 @@ /** - * \file drm_context.h + * \file drm_context.c * IOCTLs for generic contexts - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -56,25 +56,26 @@ * in drm_device::context_sareas, while holding the drm_device::struct_sem * lock. */ -void drm_ctxbitmap_free( drm_device_t *dev, int ctx_handle ) +void drm_ctxbitmap_free(drm_device_t * dev, int ctx_handle) { - if ( ctx_handle < 0 ) goto failed; - if ( !dev->ctx_bitmap ) goto failed; + if (ctx_handle < 0) + goto failed; + if (!dev->ctx_bitmap) + goto failed; - if ( ctx_handle < DRM_MAX_CTXBITMAP ) { + if (ctx_handle < DRM_MAX_CTXBITMAP) { down(&dev->struct_sem); - clear_bit( ctx_handle, dev->ctx_bitmap ); + clear_bit(ctx_handle, dev->ctx_bitmap); dev->context_sareas[ctx_handle] = NULL; up(&dev->struct_sem); return; } -failed: - DRM_ERROR( "Attempt to free invalid context handle: %d\n", - ctx_handle ); - return; + failed: + DRM_ERROR("Attempt to free invalid context handle: %d\n", ctx_handle); + return; } -/** +/** * Context bitmap allocation. * * \param dev DRM device. @@ -84,29 +85,33 @@ failed: * drm_device::context_sareas to accommodate the new entry while holding the * drm_device::struct_sem lock. */ -static int drm_ctxbitmap_next( drm_device_t *dev ) +static int drm_ctxbitmap_next(drm_device_t * dev) { int bit; - if(!dev->ctx_bitmap) return -1; + if (!dev->ctx_bitmap) + return -1; down(&dev->struct_sem); - bit = find_first_zero_bit( dev->ctx_bitmap, DRM_MAX_CTXBITMAP ); - if ( bit < DRM_MAX_CTXBITMAP ) { - set_bit( bit, dev->ctx_bitmap ); - DRM_DEBUG( "drm_ctxbitmap_next bit : %d\n", bit ); - if((bit+1) > dev->max_context) { - dev->max_context = (bit+1); - if(dev->context_sareas) { + bit = find_first_zero_bit(dev->ctx_bitmap, DRM_MAX_CTXBITMAP); + if (bit < DRM_MAX_CTXBITMAP) { + set_bit(bit, dev->ctx_bitmap); + DRM_DEBUG("drm_ctxbitmap_next bit : %d\n", bit); + if ((bit + 1) > dev->max_context) { + dev->max_context = (bit + 1); + if (dev->context_sareas) { drm_map_t **ctx_sareas; ctx_sareas = drm_realloc(dev->context_sareas, - (dev->max_context - 1) * - sizeof(*dev->context_sareas), - dev->max_context * - sizeof(*dev->context_sareas), - DRM_MEM_MAPS); - if(!ctx_sareas) { + (dev->max_context - + 1) * + sizeof(*dev-> + context_sareas), + dev->max_context * + sizeof(*dev-> + context_sareas), + DRM_MEM_MAPS); + if (!ctx_sareas) { clear_bit(bit, dev->ctx_bitmap); up(&dev->struct_sem); return -1; @@ -115,11 +120,11 @@ static int drm_ctxbitmap_next( drm_device_t *dev ) dev->context_sareas[bit] = NULL; } else { /* max_context == 1 at this point */ - dev->context_sareas = drm_alloc( - dev->max_context * - sizeof(*dev->context_sareas), - DRM_MEM_MAPS); - if(!dev->context_sareas) { + dev->context_sareas = + drm_alloc(dev->max_context * + sizeof(*dev->context_sareas), + DRM_MEM_MAPS); + if (!dev->context_sareas) { clear_bit(bit, dev->ctx_bitmap); up(&dev->struct_sem); return -1; @@ -142,26 +147,26 @@ static int drm_ctxbitmap_next( drm_device_t *dev ) * Allocates and initialize drm_device::ctx_bitmap and drm_device::context_sareas, while holding * the drm_device::struct_sem lock. */ -int drm_ctxbitmap_init( drm_device_t *dev ) +int drm_ctxbitmap_init(drm_device_t * dev) { int i; - int temp; + int temp; down(&dev->struct_sem); - dev->ctx_bitmap = (unsigned long *) drm_alloc( PAGE_SIZE, - DRM_MEM_CTXBITMAP ); - if ( dev->ctx_bitmap == NULL ) { + dev->ctx_bitmap = (unsigned long *)drm_alloc(PAGE_SIZE, + DRM_MEM_CTXBITMAP); + if (dev->ctx_bitmap == NULL) { up(&dev->struct_sem); return -ENOMEM; } - memset( (void *)dev->ctx_bitmap, 0, PAGE_SIZE ); + memset((void *)dev->ctx_bitmap, 0, PAGE_SIZE); dev->context_sareas = NULL; dev->max_context = -1; up(&dev->struct_sem); - for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { - temp = drm_ctxbitmap_next( dev ); - DRM_DEBUG( "drm_ctxbitmap_init : %d\n", temp ); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { + temp = drm_ctxbitmap_next(dev); + DRM_DEBUG("drm_ctxbitmap_init : %d\n", temp); } return 0; @@ -175,14 +180,14 @@ int drm_ctxbitmap_init( drm_device_t *dev ) * Frees drm_device::ctx_bitmap and drm_device::context_sareas, while holding * the drm_device::struct_sem lock. */ -void drm_ctxbitmap_cleanup( drm_device_t *dev ) +void drm_ctxbitmap_cleanup(drm_device_t * dev) { down(&dev->struct_sem); - if( dev->context_sareas ) drm_free( dev->context_sareas, - sizeof(*dev->context_sareas) * - dev->max_context, - DRM_MEM_MAPS ); - drm_free( (void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP ); + if (dev->context_sareas) + drm_free(dev->context_sareas, + sizeof(*dev->context_sareas) * + dev->max_context, DRM_MEM_MAPS); + drm_free((void *)dev->ctx_bitmap, PAGE_SIZE, DRM_MEM_CTXBITMAP); up(&dev->struct_sem); } @@ -194,7 +199,7 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev ) /** * Get per-context SAREA. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -205,10 +210,10 @@ void drm_ctxbitmap_cleanup( drm_device_t *dev ) * returns its handle. */ int drm_getsareactx(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_ctx_priv_map_t __user *argp = (void __user *)arg; drm_ctx_priv_map_t request; drm_map_t *map; @@ -218,7 +223,8 @@ int drm_getsareactx(struct inode *inode, struct file *filp, return -EFAULT; down(&dev->struct_sem); - if (dev->max_context < 0 || request.ctx_id >= (unsigned) dev->max_context) { + if (dev->max_context < 0 + || request.ctx_id >= (unsigned)dev->max_context) { up(&dev->struct_sem); return -EINVAL; } @@ -227,16 +233,16 @@ int drm_getsareactx(struct inode *inode, struct file *filp, up(&dev->struct_sem); request.handle = 0; - list_for_each_entry(_entry, &dev->maplist->head,head) { + list_for_each_entry(_entry, &dev->maplist->head, head) { if (_entry->map == map) { - request.handle = (void *)(unsigned long)_entry->user_token; + request.handle = + (void *)(unsigned long)_entry->user_token; break; } } if (request.handle == 0) return -EINVAL; - if (copy_to_user(argp, &request, sizeof(request))) return -EFAULT; return 0; @@ -244,7 +250,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp, /** * Set per-context SAREA. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -255,37 +261,37 @@ int drm_getsareactx(struct inode *inode, struct file *filp, * drm_device::context_sareas with it. */ int drm_setsareactx(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_ctx_priv_map_t request; drm_map_t *map = NULL; drm_map_list_t *r_list = NULL; struct list_head *list; if (copy_from_user(&request, - (drm_ctx_priv_map_t __user *)arg, - sizeof(request))) + (drm_ctx_priv_map_t __user *) arg, sizeof(request))) return -EFAULT; down(&dev->struct_sem); list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); if (r_list->map - && r_list->user_token == (unsigned long) request.handle) + && r_list->user_token == (unsigned long)request.handle) goto found; } -bad: + bad: up(&dev->struct_sem); return -EINVAL; -found: + found: map = r_list->map; - if (!map) goto bad; + if (!map) + goto bad; if (dev->max_context < 0) goto bad; - if (request.ctx_id >= (unsigned) dev->max_context) + if (request.ctx_id >= (unsigned)dev->max_context) goto bad; dev->context_sareas[request.ctx_id] = map; up(&dev->struct_sem); @@ -308,22 +314,21 @@ found: * * Attempt to set drm_device::context_flag. */ -static int drm_context_switch( drm_device_t *dev, int old, int new ) +static int drm_context_switch(drm_device_t * dev, int old, int new) { - if ( test_and_set_bit( 0, &dev->context_flag ) ) { - DRM_ERROR( "Reentering -- FIXME\n" ); - return -EBUSY; - } - + if (test_and_set_bit(0, &dev->context_flag)) { + DRM_ERROR("Reentering -- FIXME\n"); + return -EBUSY; + } - DRM_DEBUG( "Context switch from %d to %d\n", old, new ); + DRM_DEBUG("Context switch from %d to %d\n", old, new); - if ( new == dev->last_context ) { - clear_bit( 0, &dev->context_flag ); - return 0; - } + if (new == dev->last_context) { + clear_bit(0, &dev->context_flag); + return 0; + } - return 0; + return 0; } /** @@ -337,22 +342,22 @@ static int drm_context_switch( drm_device_t *dev, int old, int new ) * hardware lock is held, clears the drm_device::context_flag and wakes up * drm_device::context_wait. */ -static int drm_context_switch_complete( drm_device_t *dev, int new ) +static int drm_context_switch_complete(drm_device_t * dev, int new) { - dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ - dev->last_switch = jiffies; + dev->last_context = new; /* PRE/POST: This is the _only_ writer. */ + dev->last_switch = jiffies; - if ( !_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) ) { - DRM_ERROR( "Lock isn't held after context switch\n" ); - } + if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) { + DRM_ERROR("Lock isn't held after context switch\n"); + } - /* If a context switch is ever initiated - when the kernel holds the lock, release - that lock here. */ - clear_bit( 0, &dev->context_flag ); - wake_up( &dev->context_wait ); + /* If a context switch is ever initiated + when the kernel holds the lock, release + that lock here. */ + clear_bit(0, &dev->context_flag); + wake_up(&dev->context_wait); - return 0; + return 0; } /** @@ -364,29 +369,28 @@ static int drm_context_switch_complete( drm_device_t *dev, int new ) * \param arg user argument pointing to a drm_ctx_res structure. * \return zero on success or a negative number on failure. */ -int drm_resctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_resctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_ctx_res_t res; drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; int i; - if ( copy_from_user( &res, argp, sizeof(res) ) ) + if (copy_from_user(&res, argp, sizeof(res))) return -EFAULT; - if ( res.count >= DRM_RESERVED_CONTEXTS ) { - memset( &ctx, 0, sizeof(ctx) ); - for ( i = 0 ; i < DRM_RESERVED_CONTEXTS ; i++ ) { + if (res.count >= DRM_RESERVED_CONTEXTS) { + memset(&ctx, 0, sizeof(ctx)); + for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; - if ( copy_to_user( &res.contexts[i], - &ctx, sizeof(ctx) ) ) + if (copy_to_user(&res.contexts[i], &ctx, sizeof(ctx))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; - if ( copy_to_user( argp, &res, sizeof(res) ) ) + if (copy_to_user(argp, &res, sizeof(res))) return -EFAULT; return 0; } @@ -402,58 +406,57 @@ int drm_resctx( struct inode *inode, struct file *filp, * * Get a new handle for the context and copy to userspace. */ -int drm_addctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_addctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - drm_ctx_list_t * ctx_entry; + drm_ctx_list_t *ctx_entry; drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; - if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + if (copy_from_user(&ctx, argp, sizeof(ctx))) return -EFAULT; - ctx.handle = drm_ctxbitmap_next( dev ); - if ( ctx.handle == DRM_KERNEL_CONTEXT ) { - /* Skip kernel's context and get a new one. */ - ctx.handle = drm_ctxbitmap_next( dev ); + ctx.handle = drm_ctxbitmap_next(dev); + if (ctx.handle == DRM_KERNEL_CONTEXT) { + /* Skip kernel's context and get a new one. */ + ctx.handle = drm_ctxbitmap_next(dev); } - DRM_DEBUG( "%d\n", ctx.handle ); - if ( ctx.handle == -1 ) { - DRM_DEBUG( "Not enough free contexts.\n" ); - /* Should this return -EBUSY instead? */ + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == -1) { + DRM_DEBUG("Not enough free contexts.\n"); + /* Should this return -EBUSY instead? */ return -ENOMEM; } - if ( ctx.handle != DRM_KERNEL_CONTEXT ) - { + if (ctx.handle != DRM_KERNEL_CONTEXT) { if (dev->driver->context_ctor) dev->driver->context_ctor(dev, ctx.handle); } - ctx_entry = drm_alloc( sizeof(*ctx_entry), DRM_MEM_CTXLIST ); - if ( !ctx_entry ) { + ctx_entry = drm_alloc(sizeof(*ctx_entry), DRM_MEM_CTXLIST); + if (!ctx_entry) { DRM_DEBUG("out of memory\n"); return -ENOMEM; } - INIT_LIST_HEAD( &ctx_entry->head ); + INIT_LIST_HEAD(&ctx_entry->head); ctx_entry->handle = ctx.handle; ctx_entry->tag = priv; - down( &dev->ctxlist_sem ); - list_add( &ctx_entry->head, &dev->ctxlist->head ); + down(&dev->ctxlist_sem); + list_add(&ctx_entry->head, &dev->ctxlist->head); ++dev->ctx_count; - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); - if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + if (copy_to_user(argp, &ctx, sizeof(ctx))) return -EFAULT; return 0; } -int drm_modctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_modctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { /* This does nothing */ return 0; @@ -468,19 +471,19 @@ int drm_modctx( struct inode *inode, struct file *filp, * \param arg user argument pointing to a drm_ctx structure. * \return zero on success or a negative number on failure. */ -int drm_getctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_ctx_t __user *argp = (void __user *)arg; drm_ctx_t ctx; - if ( copy_from_user( &ctx, argp, sizeof(ctx) ) ) + if (copy_from_user(&ctx, argp, sizeof(ctx))) return -EFAULT; /* This is 0, because we don't handle any context flags */ ctx.flags = 0; - if ( copy_to_user( argp, &ctx, sizeof(ctx) ) ) + if (copy_to_user(argp, &ctx, sizeof(ctx))) return -EFAULT; return 0; } @@ -496,18 +499,18 @@ int drm_getctx( struct inode *inode, struct file *filp, * * Calls context_switch(). */ -int drm_switchctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - return drm_context_switch( dev, dev->last_context, ctx.handle ); + DRM_DEBUG("%d\n", ctx.handle); + return drm_context_switch(dev, dev->last_context, ctx.handle); } /** @@ -521,18 +524,18 @@ int drm_switchctx( struct inode *inode, struct file *filp, * * Calls context_switch_complete(). */ -int drm_newctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_newctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - drm_context_switch_complete( dev, ctx.handle ); + DRM_DEBUG("%d\n", ctx.handle); + drm_context_switch_complete(dev, ctx.handle); return 0; } @@ -548,42 +551,41 @@ int drm_newctx( struct inode *inode, struct file *filp, * * If not the special kernel context, calls ctxbitmap_free() to free the specified context. */ -int drm_rmctx( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_rmctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_ctx_t ctx; - if ( copy_from_user( &ctx, (drm_ctx_t __user *)arg, sizeof(ctx) ) ) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - DRM_DEBUG( "%d\n", ctx.handle ); - if ( ctx.handle == DRM_KERNEL_CONTEXT + 1 ) { + DRM_DEBUG("%d\n", ctx.handle); + if (ctx.handle == DRM_KERNEL_CONTEXT + 1) { priv->remove_auth_on_close = 1; } - if ( ctx.handle != DRM_KERNEL_CONTEXT ) { + if (ctx.handle != DRM_KERNEL_CONTEXT) { if (dev->driver->context_dtor) dev->driver->context_dtor(dev, ctx.handle); - drm_ctxbitmap_free( dev, ctx.handle ); + drm_ctxbitmap_free(dev, ctx.handle); } - down( &dev->ctxlist_sem ); - if ( !list_empty( &dev->ctxlist->head ) ) { + down(&dev->ctxlist_sem); + if (!list_empty(&dev->ctxlist->head)) { drm_ctx_list_t *pos, *n; - list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { - if ( pos->handle == ctx.handle ) { - list_del( &pos->head ); - drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) { + if (pos->handle == ctx.handle) { + list_del(&pos->head); + drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST); --dev->ctx_count; } } } - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); return 0; } /*@}*/ - diff --git a/drivers/char/drm/drm_dma.c b/drivers/char/drm/drm_dma.c index 4a28c053c98..2afab95ca03 100644 --- a/drivers/char/drm/drm_dma.c +++ b/drivers/char/drm/drm_dma.c @@ -1,5 +1,5 @@ /** - * \file drm_dma.h + * \file drm_dma.c * DMA IOCTL and function support * * \author Rickard E. (Rik) Faith @@ -37,23 +37,23 @@ /** * Initialize the DMA data. - * + * * \param dev DRM device. * \return zero on success or a negative value on failure. * * Allocate and initialize a drm_device_dma structure. */ -int drm_dma_setup( drm_device_t *dev ) +int drm_dma_setup(drm_device_t * dev) { int i; - dev->dma = drm_alloc( sizeof(*dev->dma), DRM_MEM_DRIVER ); - if ( !dev->dma ) + dev->dma = drm_alloc(sizeof(*dev->dma), DRM_MEM_DRIVER); + if (!dev->dma) return -ENOMEM; - memset( dev->dma, 0, sizeof(*dev->dma) ); + memset(dev->dma, 0, sizeof(*dev->dma)); - for ( i = 0 ; i <= DRM_MAX_ORDER ; i++ ) + for (i = 0; i <= DRM_MAX_ORDER; i++) memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); return 0; @@ -67,14 +67,15 @@ int drm_dma_setup( drm_device_t *dev ) * Free all pages associated with DMA buffers, the buffers and pages lists, and * finally the the drm_device::dma structure itself. */ -void drm_dma_takedown(drm_device_t *dev) +void drm_dma_takedown(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i, j; + drm_device_dma_t *dma = dev->dma; + int i, j; - if (!dma) return; + if (!dma) + return; - /* Clear dma buffers */ + /* Clear dma buffers */ for (i = 0; i <= DRM_MAX_ORDER; i++) { if (dma->bufs[i].seg_count) { DRM_DEBUG("order %d: buf_count = %d," @@ -85,64 +86,63 @@ void drm_dma_takedown(drm_device_t *dev) for (j = 0; j < dma->bufs[i].seg_count; j++) { if (dma->bufs[i].seglist[j]) { drm_free_pages(dma->bufs[i].seglist[j], - dma->bufs[i].page_order, - DRM_MEM_DMA); + dma->bufs[i].page_order, + DRM_MEM_DMA); } } drm_free(dma->bufs[i].seglist, - dma->bufs[i].seg_count - * sizeof(*dma->bufs[0].seglist), - DRM_MEM_SEGS); + dma->bufs[i].seg_count + * sizeof(*dma->bufs[0].seglist), DRM_MEM_SEGS); } - if (dma->bufs[i].buf_count) { - for (j = 0; j < dma->bufs[i].buf_count; j++) { + if (dma->bufs[i].buf_count) { + for (j = 0; j < dma->bufs[i].buf_count; j++) { if (dma->bufs[i].buflist[j].dev_private) { - drm_free(dma->bufs[i].buflist[j].dev_private, - dma->bufs[i].buflist[j].dev_priv_size, - DRM_MEM_BUFS); + drm_free(dma->bufs[i].buflist[j]. + dev_private, + dma->bufs[i].buflist[j]. + dev_priv_size, DRM_MEM_BUFS); } } - drm_free(dma->bufs[i].buflist, - dma->bufs[i].buf_count * - sizeof(*dma->bufs[0].buflist), - DRM_MEM_BUFS); + drm_free(dma->bufs[i].buflist, + dma->bufs[i].buf_count * + sizeof(*dma->bufs[0].buflist), DRM_MEM_BUFS); } } if (dma->buflist) { drm_free(dma->buflist, - dma->buf_count * sizeof(*dma->buflist), - DRM_MEM_BUFS); + dma->buf_count * sizeof(*dma->buflist), DRM_MEM_BUFS); } if (dma->pagelist) { drm_free(dma->pagelist, - dma->page_count * sizeof(*dma->pagelist), - DRM_MEM_PAGES); + dma->page_count * sizeof(*dma->pagelist), + DRM_MEM_PAGES); } drm_free(dev->dma, sizeof(*dev->dma), DRM_MEM_DRIVER); dev->dma = NULL; } - /** * Free a buffer. * * \param dev DRM device. * \param buf buffer to free. - * + * * Resets the fields of \p buf. */ -void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) +void drm_free_buffer(drm_device_t * dev, drm_buf_t * buf) { - if (!buf) return; + if (!buf) + return; - buf->waiting = 0; - buf->pending = 0; - buf->filp = NULL; - buf->used = 0; + buf->waiting = 0; + buf->pending = 0; + buf->filp = NULL; + buf->used = 0; - if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && waitqueue_active(&buf->dma_wait)) { + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) + && waitqueue_active(&buf->dma_wait)) { wake_up_interruptible(&buf->dma_wait); } } @@ -154,12 +154,13 @@ void drm_free_buffer(drm_device_t *dev, drm_buf_t *buf) * * Frees each buffer associated with \p filp not already on the hardware. */ -void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp) +void drm_core_reclaim_buffers(drm_device_t * dev, struct file *filp) { drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; + if (!dma) + return; for (i = 0; i < dma->buf_count; i++) { if (dma->buflist[i]->filp == filp) { switch (dma->buflist[i]->list) { @@ -176,5 +177,5 @@ void drm_core_reclaim_buffers(drm_device_t *dev, struct file *filp) } } } -EXPORT_SYMBOL(drm_core_reclaim_buffers); +EXPORT_SYMBOL(drm_core_reclaim_buffers); diff --git a/drivers/char/drm/drm_drawable.c b/drivers/char/drm/drm_drawable.c index e8e8e42be4c..7857453c4f4 100644 --- a/drivers/char/drm/drm_drawable.c +++ b/drivers/char/drm/drm_drawable.c @@ -1,5 +1,5 @@ /** - * \file drm_drawable.h + * \file drm_drawable.c * IOCTLs for drawables * * \author Rickard E. (Rik) Faith @@ -37,20 +37,20 @@ /** No-op. */ int drm_adddraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_draw_t draw; draw.handle = 0; /* NOOP */ DRM_DEBUG("%d\n", draw.handle); - if (copy_to_user((drm_draw_t __user *)arg, &draw, sizeof(draw))) + if (copy_to_user((drm_draw_t __user *) arg, &draw, sizeof(draw))) return -EFAULT; return 0; } /** No-op. */ int drm_rmdraw(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { return 0; /* NOOP */ } diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c index 6ba48f346fc..26733248ff4 100644 --- a/drivers/char/drm/drm_drv.c +++ b/drivers/char/drm/drm_drv.c @@ -1,5 +1,5 @@ /** - * \file drm_drv.h + * \file drm_drv.c * Generic driver template * * \author Rickard E. (Rik) Faith @@ -55,67 +55,67 @@ static int drm_version(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg); /** Ioctl table */ -static drm_ioctl_desc_t drm_ioctls[] = { - [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = { drm_version, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = { drm_getunique, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = { drm_getmagic, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = { drm_irq_by_busid, 0, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = { drm_getmap, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = { drm_getclient, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = { drm_getstats, 0, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = { drm_setversion, 0, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = { drm_setunique, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = { drm_noop, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = { drm_noop, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = { drm_authmagic, 1, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = { drm_addmap_ioctl,1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = { drm_rmmap_ioctl, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = { drm_setsareactx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = { drm_getsareactx, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = { drm_addctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = { drm_rmctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = { drm_modctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = { drm_getctx, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = { drm_switchctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = { drm_newctx, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = { drm_resctx, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = { drm_adddraw, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = { drm_rmdraw, 1, 1 }, - - [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = { drm_lock, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = { drm_unlock, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = { drm_noop, 1, 0 }, - - [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = { drm_addbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = { drm_markbufs, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = { drm_infobufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = { drm_mapbufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = { drm_freebufs, 1, 0 }, +static drm_ioctl_desc_t drm_ioctls[] = { + [DRM_IOCTL_NR(DRM_IOCTL_VERSION)] = {drm_version, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_UNIQUE)] = {drm_getunique, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAGIC)] = {drm_getmagic, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_IRQ_BUSID)] = {drm_irq_by_busid, 0, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_MAP)] = {drm_getmap, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CLIENT)] = {drm_getclient, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_STATS)] = {drm_getstats, 0, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_SET_VERSION)] = {drm_setversion, 0, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_UNIQUE)] = {drm_setunique, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_BLOCK)] = {drm_noop, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_UNBLOCK)] = {drm_noop, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AUTH_MAGIC)] = {drm_authmagic, 1, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_MAP)] = {drm_addmap_ioctl, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_MAP)] = {drm_rmmap_ioctl, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_SET_SAREA_CTX)] = {drm_setsareactx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX)] = {drm_getsareactx, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_CTX)] = {drm_addctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)] = {drm_rmctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)] = {drm_modctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)] = {drm_getctx, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)] = {drm_switchctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)] = {drm_newctx, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)] = {drm_resctx, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_DRAW)] = {drm_adddraw, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_RM_DRAW)] = {drm_rmdraw, 1, 1}, + + [DRM_IOCTL_NR(DRM_IOCTL_LOCK)] = {drm_lock, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_UNLOCK)] = {drm_unlock, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_FINISH)] = {drm_noop, 1, 0}, + + [DRM_IOCTL_NR(DRM_IOCTL_ADD_BUFS)] = {drm_addbufs, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_MARK_BUFS)] = {drm_markbufs, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_INFO_BUFS)] = {drm_infobufs, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_MAP_BUFS)] = {drm_mapbufs, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_FREE_BUFS)] = {drm_freebufs, 1, 0}, /* The DRM_IOCTL_DMA ioctl should be defined by the driver. */ - [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = { drm_control, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_CONTROL)] = {drm_control, 1, 1}, #if __OS_HAS_AGP - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = { drm_agp_acquire_ioctl, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = { drm_agp_release_ioctl, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = { drm_agp_enable_ioctl, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = { drm_agp_info_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = { drm_agp_alloc, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = { drm_agp_free, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = { drm_agp_bind, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = { drm_agp_unbind, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ACQUIRE)] = {drm_agp_acquire_ioctl, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_RELEASE)] = {drm_agp_release_ioctl, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE)] = {drm_agp_enable_ioctl, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO)] = {drm_agp_info_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC)] = {drm_agp_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_FREE)] = {drm_agp_free, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_BIND)] = {drm_agp_bind, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_AGP_UNBIND)] = {drm_agp_unbind, 1, 1}, #endif - [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = { drm_sg_alloc, 1, 1 }, - [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = { drm_sg_free, 1, 1 }, + [DRM_IOCTL_NR(DRM_IOCTL_SG_ALLOC)] = {drm_sg_alloc, 1, 1}, + [DRM_IOCTL_NR(DRM_IOCTL_SG_FREE)] = {drm_sg_free, 1, 1}, - [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = { drm_wait_vblank, 0, 0 }, + [DRM_IOCTL_NR(DRM_IOCTL_WAIT_VBLANK)] = {drm_wait_vblank, 0, 0}, }; #define DRIVER_IOCTL_COUNT DRM_ARRAY_SIZE( drm_ioctls ) @@ -129,17 +129,17 @@ static drm_ioctl_desc_t drm_ioctls[] = { * * \sa drm_device */ -int drm_takedown( drm_device_t *dev ) +int drm_takedown(drm_device_t * dev) { drm_magic_entry_t *pt, *next; drm_map_list_t *r_list; drm_vma_entry_t *vma, *vma_next; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); if (dev->driver->pretakedown) - dev->driver->pretakedown(dev); + dev->driver->pretakedown(dev); DRM_DEBUG("driver pretakedown completed\n"); if (dev->unique) { @@ -148,95 +148,95 @@ int drm_takedown( drm_device_t *dev ) dev->unique_len = 0; } - if ( dev->irq_enabled ) drm_irq_uninstall( dev ); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - down( &dev->struct_sem ); - del_timer( &dev->timer ); + down(&dev->struct_sem); + del_timer(&dev->timer); - /* Clear pid list */ - for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { - for ( pt = dev->magiclist[i].head ; pt ; pt = next ) { + /* Clear pid list */ + for (i = 0; i < DRM_HASH_SIZE; i++) { + for (pt = dev->magiclist[i].head; pt; pt = next) { next = pt->next; - drm_free( pt, sizeof(*pt), DRM_MEM_MAGIC ); + drm_free(pt, sizeof(*pt), DRM_MEM_MAGIC); } dev->magiclist[i].head = dev->magiclist[i].tail = NULL; } - /* Clear AGP information */ + /* Clear AGP information */ if (drm_core_has_AGP(dev) && dev->agp) { drm_agp_mem_t *entry; drm_agp_mem_t *nexte; - /* Remove AGP resources, but leave dev->agp - intact until drv_cleanup is called. */ - for ( entry = dev->agp->memory ; entry ; entry = nexte ) { + /* Remove AGP resources, but leave dev->agp + intact until drv_cleanup is called. */ + for (entry = dev->agp->memory; entry; entry = nexte) { nexte = entry->next; - if ( entry->bound ) drm_unbind_agp( entry->memory ); - drm_free_agp( entry->memory, entry->pages ); - drm_free( entry, sizeof(*entry), DRM_MEM_AGPLISTS ); + if (entry->bound) + drm_unbind_agp(entry->memory); + drm_free_agp(entry->memory, entry->pages); + drm_free(entry, sizeof(*entry), DRM_MEM_AGPLISTS); } dev->agp->memory = NULL; if (dev->agp->acquired) - drm_agp_release(dev); + drm_agp_release(dev); dev->agp->acquired = 0; - dev->agp->enabled = 0; + dev->agp->enabled = 0; } if (drm_core_check_feature(dev, DRIVER_SG) && dev->sg) { drm_sg_cleanup(dev->sg); dev->sg = NULL; } - /* Clear vma list (only built for debugging) */ - if ( dev->vmalist ) { - for ( vma = dev->vmalist ; vma ; vma = vma_next ) { + /* Clear vma list (only built for debugging) */ + if (dev->vmalist) { + for (vma = dev->vmalist; vma; vma = vma_next) { vma_next = vma->next; - drm_free( vma, sizeof(*vma), DRM_MEM_VMAS ); + drm_free(vma, sizeof(*vma), DRM_MEM_VMAS); } dev->vmalist = NULL; } - if( dev->maplist ) { + if (dev->maplist) { while (!list_empty(&dev->maplist->head)) { struct list_head *list = dev->maplist->head.next; r_list = list_entry(list, drm_map_list_t, head); drm_rmmap_locked(dev, r_list->map); } - } - - if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist ) { - for ( i = 0 ; i < dev->queue_count ; i++ ) { - if ( dev->queuelist[i] ) { - drm_free( dev->queuelist[i], - sizeof(*dev->queuelist[0]), - DRM_MEM_QUEUES ); + } + + if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE) && dev->queuelist) { + for (i = 0; i < dev->queue_count; i++) { + if (dev->queuelist[i]) { + drm_free(dev->queuelist[i], + sizeof(*dev->queuelist[0]), + DRM_MEM_QUEUES); dev->queuelist[i] = NULL; } } - drm_free( dev->queuelist, - dev->queue_slots * sizeof(*dev->queuelist), - DRM_MEM_QUEUES ); + drm_free(dev->queuelist, + dev->queue_slots * sizeof(*dev->queuelist), + DRM_MEM_QUEUES); dev->queuelist = NULL; } dev->queue_count = 0; if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) - drm_dma_takedown( dev ); + drm_dma_takedown(dev); - if ( dev->lock.hw_lock ) { - dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ + if (dev->lock.hw_lock) { + dev->sigdata.lock = dev->lock.hw_lock = NULL; /* SHM removed */ dev->lock.filp = NULL; - wake_up_interruptible( &dev->lock.lock_queue ); + wake_up_interruptible(&dev->lock.lock_queue); } - up( &dev->struct_sem ); + up(&dev->struct_sem); DRM_DEBUG("takedown completed\n"); return 0; } - - /** * Module initialization. Called via init_module at module load time, or via * linux/init/main.c (this is not currently supported). @@ -246,26 +246,28 @@ int drm_takedown( drm_device_t *dev ) * Initializes an array of drm_device structures, and attempts to * initialize all available devices, using consecutive minors, registering the * stubs and initializing the AGP device. - * + * * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and * after the initialization for driver customization. */ -int drm_init( struct drm_driver *driver ) +int drm_init(struct drm_driver *driver) { struct pci_dev *pdev = NULL; struct pci_device_id *pid; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); drm_mem_init(); - for (i=0; driver->pci_driver.id_table[i].vendor != 0; i++) { + for (i = 0; driver->pci_driver.id_table[i].vendor != 0; i++) { pid = (struct pci_device_id *)&driver->pci_driver.id_table[i]; - - pdev=NULL; - /* pass back in pdev to account for multiple identical cards */ - while ((pdev = pci_get_subsys(pid->vendor, pid->device, pid->subvendor, pid->subdevice, pdev)) != NULL) { + + pdev = NULL; + /* pass back in pdev to account for multiple identical cards */ + while ((pdev = + pci_get_subsys(pid->vendor, pid->device, pid->subvendor, + pid->subdevice, pdev)) != NULL) { /* stealth mode requires a manual probe */ pci_dev_get(pdev); drm_get_dev(pdev, pid, driver); @@ -273,62 +275,63 @@ int drm_init( struct drm_driver *driver ) } return 0; } + EXPORT_SYMBOL(drm_init); /** * Called via cleanup_module() at module unload time. * * Cleans up all DRM device, calling takedown(). - * + * * \sa drm_init */ -static void drm_cleanup( drm_device_t *dev ) +static void drm_cleanup(drm_device_t * dev) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); if (!dev) { DRM_ERROR("cleanup called no dev\n"); return; } - drm_takedown( dev ); + drm_takedown(dev); if (dev->maplist) { drm_free(dev->maplist, sizeof(*dev->maplist), DRM_MEM_MAPS); dev->maplist = NULL; } - drm_ctxbitmap_cleanup( dev ); - + drm_ctxbitmap_cleanup(dev); + if (drm_core_has_MTRR(dev) && drm_core_has_AGP(dev) && dev->agp && dev->agp->agp_mtrr >= 0) { int retval; - retval = mtrr_del( dev->agp->agp_mtrr, - dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size*1024*1024 ); - DRM_DEBUG( "mtrr_del=%d\n", retval ); + retval = mtrr_del(dev->agp->agp_mtrr, + dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * 1024 * 1024); + DRM_DEBUG("mtrr_del=%d\n", retval); } - - if (drm_core_has_AGP(dev) && dev->agp ) { - drm_free( dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS ); + + if (drm_core_has_AGP(dev) && dev->agp) { + drm_free(dev->agp, sizeof(*dev->agp), DRM_MEM_AGPLISTS); dev->agp = NULL; } if (dev->driver->postcleanup) dev->driver->postcleanup(dev); - + drm_put_head(&dev->primary); - if ( drm_put_dev(dev) ) - DRM_ERROR( "Cannot unload module\n" ); + if (drm_put_dev(dev)) + DRM_ERROR("Cannot unload module\n"); } -void drm_exit (struct drm_driver *driver) +void drm_exit(struct drm_driver *driver) { int i; drm_device_t *dev = NULL; drm_head_t *head; - - DRM_DEBUG( "\n" ); + + DRM_DEBUG("\n"); for (i = 0; i < drm_cards_limit; i++) { head = drm_heads[i]; @@ -336,9 +339,9 @@ void drm_exit (struct drm_driver *driver) continue; if (!head->dev) continue; - if (head->dev->driver!=driver) + if (head->dev->driver != driver) continue; - dev=head->dev; + dev = head->dev; } if (dev) { /* release the pci driver */ @@ -346,32 +349,35 @@ void drm_exit (struct drm_driver *driver) pci_dev_put(dev->pdev); drm_cleanup(dev); } - DRM_INFO( "Module unloaded\n" ); + DRM_INFO("Module unloaded\n"); } + EXPORT_SYMBOL(drm_exit); /** File operations structure */ static struct file_operations drm_stub_fops = { .owner = THIS_MODULE, - .open = drm_stub_open + .open = drm_stub_open }; static int __init drm_core_init(void) { int ret = -ENOMEM; - - drm_cards_limit = (drm_cards_limit < DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1); - drm_heads = drm_calloc(drm_cards_limit, - sizeof(*drm_heads), DRM_MEM_STUB); - if(!drm_heads) + + drm_cards_limit = + (drm_cards_limit < + DRM_MAX_MINOR + 1 ? drm_cards_limit : DRM_MAX_MINOR + 1); + drm_heads = + drm_calloc(drm_cards_limit, sizeof(*drm_heads), DRM_MEM_STUB); + if (!drm_heads) goto err_p1; - + if (register_chrdev(DRM_MAJOR, "drm", &drm_stub_fops)) goto err_p1; - + drm_class = drm_sysfs_create(THIS_MODULE, "drm"); if (IS_ERR(drm_class)) { - printk (KERN_ERR "DRM: Error creating drm class.\n"); + printk(KERN_ERR "DRM: Error creating drm class.\n"); ret = PTR_ERR(drm_class); goto err_p2; } @@ -382,35 +388,31 @@ static int __init drm_core_init(void) ret = -1; goto err_p3; } - - DRM_INFO( "Initialized %s %d.%d.%d %s\n", - CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, - CORE_DATE); + + DRM_INFO("Initialized %s %d.%d.%d %s\n", + CORE_NAME, CORE_MAJOR, CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE); return 0; -err_p3: + err_p3: drm_sysfs_destroy(drm_class); -err_p2: + err_p2: unregister_chrdev(DRM_MAJOR, "drm"); drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB); -err_p1: + err_p1: return ret; } -static void __exit drm_core_exit (void) +static void __exit drm_core_exit(void) { remove_proc_entry("dri", NULL); drm_sysfs_destroy(drm_class); unregister_chrdev(DRM_MAJOR, "drm"); - drm_free(drm_heads, sizeof(*drm_heads) * - drm_cards_limit, DRM_MEM_STUB); + drm_free(drm_heads, sizeof(*drm_heads) * drm_cards_limit, DRM_MEM_STUB); } - -module_init( drm_core_init ); -module_exit( drm_core_exit ); - +module_init(drm_core_init); +module_exit(drm_core_exit); /** * Get version information @@ -423,8 +425,8 @@ module_exit( drm_core_exit ); * * Fills in the version information in \p arg. */ -static int drm_version( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +static int drm_version(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -432,21 +434,19 @@ static int drm_version( struct inode *inode, struct file *filp, drm_version_t version; int ret; - if ( copy_from_user( &version, argp, sizeof(version) ) ) + if (copy_from_user(&version, argp, sizeof(version))) return -EFAULT; /* version is a required function to return the personality module version */ if ((ret = dev->driver->version(&version))) return ret; - - if ( copy_to_user( argp, &version, sizeof(version) ) ) + + if (copy_to_user(argp, &version, sizeof(version))) return -EFAULT; return 0; } - - -/** +/** * Called whenever a process performs an ioctl on /dev/drm. * * \param inode device inode. @@ -458,8 +458,8 @@ static int drm_version( struct inode *inode, struct file *filp, * Looks up the ioctl function in the ::ioctls table, checking for root * previleges if so required, and dispatches to the respective function. */ -int drm_ioctl( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -468,40 +468,43 @@ int drm_ioctl( struct inode *inode, struct file *filp, unsigned int nr = DRM_IOCTL_NR(cmd); int retcode = -EINVAL; - atomic_inc( &dev->ioctl_count ); - atomic_inc( &dev->counts[_DRM_STAT_IOCTLS] ); + atomic_inc(&dev->ioctl_count); + atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]); ++priv->ioctl_count; - DRM_DEBUG( "pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", - current->pid, cmd, nr, (long)old_encode_dev(priv->head->device), - priv->authenticated ); - + DRM_DEBUG("pid=%d, cmd=0x%02x, nr=0x%02x, dev 0x%lx, auth=%d\n", + current->pid, cmd, nr, + (long)old_encode_dev(priv->head->device), + priv->authenticated); + if (nr < DRIVER_IOCTL_COUNT) ioctl = &drm_ioctls[nr]; - else if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) + else if ((nr >= DRM_COMMAND_BASE) + && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; else goto err_i1; - + func = ioctl->func; /* is there a local override? */ if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) func = dev->driver->dma_ioctl; - - if ( !func ) { - DRM_DEBUG( "no function\n" ); + + if (!func) { + DRM_DEBUG("no function\n"); retcode = -EINVAL; - } else if ( ( ioctl->root_only && !capable( CAP_SYS_ADMIN ) )|| - ( ioctl->auth_needed && !priv->authenticated ) ) { + } else if ((ioctl->root_only && !capable(CAP_SYS_ADMIN)) || + (ioctl->auth_needed && !priv->authenticated)) { retcode = -EACCES; } else { - retcode = func( inode, filp, cmd, arg ); + retcode = func(inode, filp, cmd, arg); } - -err_i1: - atomic_dec( &dev->ioctl_count ); - if (retcode) DRM_DEBUG( "ret = %x\n", retcode); + + err_i1: + atomic_dec(&dev->ioctl_count); + if (retcode) + DRM_DEBUG("ret = %x\n", retcode); return retcode; } -EXPORT_SYMBOL(drm_ioctl); +EXPORT_SYMBOL(drm_ioctl); diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c index a1f4e9cd64e..e0124a9ba14 100644 --- a/drivers/char/drm/drm_fops.c +++ b/drivers/char/drm/drm_fops.c @@ -1,7 +1,7 @@ /** - * \file drm_fops.h + * \file drm_fops.c * File operations for DRM - * + * * \author Rickard E. (Rik) Faith * \author Daryll Strauss * \author Gareth Hughes @@ -37,49 +37,48 @@ #include "drmP.h" #include -static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev); +static int drm_open_helper(struct inode *inode, struct file *filp, + drm_device_t * dev); -static int drm_setup( drm_device_t *dev ) +static int drm_setup(drm_device_t * dev) { int i; int ret; - if (dev->driver->presetup) - { - ret=dev->driver->presetup(dev); - if (ret!=0) + if (dev->driver->presetup) { + ret = dev->driver->presetup(dev); + if (ret != 0) return ret; } - atomic_set( &dev->ioctl_count, 0 ); - atomic_set( &dev->vma_count, 0 ); + atomic_set(&dev->ioctl_count, 0); + atomic_set(&dev->vma_count, 0); dev->buf_use = 0; - atomic_set( &dev->buf_alloc, 0 ); + atomic_set(&dev->buf_alloc, 0); - if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) - { - i = drm_dma_setup( dev ); - if ( i < 0 ) + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA)) { + i = drm_dma_setup(dev); + if (i < 0) return i; } - for ( i = 0 ; i < DRM_ARRAY_SIZE(dev->counts) ; i++ ) - atomic_set( &dev->counts[i], 0 ); + for (i = 0; i < DRM_ARRAY_SIZE(dev->counts); i++) + atomic_set(&dev->counts[i], 0); - for ( i = 0 ; i < DRM_HASH_SIZE ; i++ ) { + for (i = 0; i < DRM_HASH_SIZE; i++) { dev->magiclist[i].head = NULL; dev->magiclist[i].tail = NULL; } - dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), - DRM_MEM_CTXLIST); - if(dev->ctxlist == NULL) return -ENOMEM; + dev->ctxlist = drm_alloc(sizeof(*dev->ctxlist), DRM_MEM_CTXLIST); + if (dev->ctxlist == NULL) + return -ENOMEM; memset(dev->ctxlist, 0, sizeof(*dev->ctxlist)); INIT_LIST_HEAD(&dev->ctxlist->head); dev->vmalist = NULL; dev->sigdata.lock = dev->lock.hw_lock = NULL; - init_waitqueue_head( &dev->lock.lock_queue ); + init_waitqueue_head(&dev->lock.lock_queue); dev->queue_count = 0; dev->queue_reserved = 0; dev->queue_slots = 0; @@ -91,7 +90,7 @@ static int drm_setup( drm_device_t *dev ) dev->last_context = 0; dev->last_switch = 0; dev->last_checked = 0; - init_waitqueue_head( &dev->context_wait ); + init_waitqueue_head(&dev->context_wait); dev->if_version = 0; dev->ctx_start = 0; @@ -101,14 +100,14 @@ static int drm_setup( drm_device_t *dev ) dev->buf_wp = dev->buf; dev->buf_end = dev->buf + DRM_BSZ; dev->buf_async = NULL; - init_waitqueue_head( &dev->buf_readers ); - init_waitqueue_head( &dev->buf_writers ); + init_waitqueue_head(&dev->buf_readers); + init_waitqueue_head(&dev->buf_writers); - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* * The kernel's context could be created here, but is now created - * in drm_dma_enqueue. This is more resource-efficient for + * in drm_dma_enqueue. This is more resource-efficient for * hardware that does not do DMA, but may mean that * drm_select_queue fails between the time the interrupt is * initialized and the time the queues are initialized. @@ -121,7 +120,7 @@ static int drm_setup( drm_device_t *dev ) /** * Open file. - * + * * \param inode device inode * \param filp file pointer. * \return zero on success or a negative number on failure. @@ -130,7 +129,7 @@ static int drm_setup( drm_device_t *dev ) * increments the device open count. If the open count was previous at zero, * i.e., it's the first that the device is open, then calls setup(). */ -int drm_open( struct inode *inode, struct file *filp ) +int drm_open(struct inode *inode, struct file *filp) { drm_device_t *dev = NULL; int minor = iminor(inode); @@ -138,26 +137,27 @@ int drm_open( struct inode *inode, struct file *filp ) if (!((minor >= 0) && (minor < drm_cards_limit))) return -ENODEV; - + if (!drm_heads[minor]) return -ENODEV; if (!(dev = drm_heads[minor]->dev)) return -ENODEV; - - retcode = drm_open_helper( inode, filp, dev ); - if ( !retcode ) { - atomic_inc( &dev->counts[_DRM_STAT_OPENS] ); - spin_lock( &dev->count_lock ); - if ( !dev->open_count++ ) { - spin_unlock( &dev->count_lock ); - return drm_setup( dev ); + + retcode = drm_open_helper(inode, filp, dev); + if (!retcode) { + atomic_inc(&dev->counts[_DRM_STAT_OPENS]); + spin_lock(&dev->count_lock); + if (!dev->open_count++) { + spin_unlock(&dev->count_lock); + return drm_setup(dev); } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); } return retcode; } + EXPORT_SYMBOL(drm_open); /** @@ -172,7 +172,7 @@ EXPORT_SYMBOL(drm_open); * data from its list and free it. Decreases the open count and if it reaches * zero calls takedown(). */ -int drm_release( struct inode *inode, struct file *filp ) +int drm_release(struct inode *inode, struct file *filp) { drm_file_t *priv = filp->private_data; drm_device_t *dev; @@ -181,7 +181,7 @@ int drm_release( struct inode *inode, struct file *filp ) lock_kernel(); dev = priv->head->dev; - DRM_DEBUG( "open_count = %d\n", dev->open_count ); + DRM_DEBUG("open_count = %d\n", dev->open_count); if (dev->driver->prerelease) dev->driver->prerelease(dev, filp); @@ -190,194 +190,199 @@ int drm_release( struct inode *inode, struct file *filp ) * Begin inline drm_release */ - DRM_DEBUG( "pid = %d, device = 0x%lx, open_count = %d\n", - current->pid, (long)old_encode_dev(priv->head->device), dev->open_count ); + DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", + current->pid, (long)old_encode_dev(priv->head->device), + dev->open_count); + + if (priv->lock_count && dev->lock.hw_lock && + _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && + dev->lock.filp == filp) { + DRM_DEBUG("File %p released, freeing lock for context %d\n", + filp, _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - if ( priv->lock_count && dev->lock.hw_lock && - _DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock) && - dev->lock.filp == filp ) { - DRM_DEBUG( "File %p released, freeing lock for context %d\n", - filp, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); - if (dev->driver->release) dev->driver->release(dev, filp); - drm_lock_free( dev, &dev->lock.hw_lock->lock, - _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock) ); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock)); - /* FIXME: may require heavy-handed reset of - hardware at this point, possibly - processed via a callback to the X - server. */ - } - else if ( dev->driver->release && priv->lock_count && dev->lock.hw_lock ) { + /* FIXME: may require heavy-handed reset of + hardware at this point, possibly + processed via a callback to the X + server. */ + } else if (dev->driver->release && priv->lock_count + && dev->lock.hw_lock) { /* The lock is required to reclaim buffers */ - DECLARE_WAITQUEUE( entry, current ); + DECLARE_WAITQUEUE(entry, current); - add_wait_queue( &dev->lock.lock_queue, &entry ); + add_wait_queue(&dev->lock.lock_queue, &entry); for (;;) { __set_current_state(TASK_INTERRUPTIBLE); - if ( !dev->lock.hw_lock ) { + if (!dev->lock.hw_lock) { /* Device has been unregistered */ retcode = -EINTR; break; } - if ( drm_lock_take( &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ) ) { - dev->lock.filp = filp; + if (drm_lock_take(&dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + dev->lock.filp = filp; dev->lock.lock_time = jiffies; - atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); + atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); break; /* Got lock */ } - /* Contention */ + /* Contention */ schedule(); - if ( signal_pending( current ) ) { + if (signal_pending(current)) { retcode = -ERESTARTSYS; break; } } __set_current_state(TASK_RUNNING); - remove_wait_queue( &dev->lock.lock_queue, &entry ); - if( !retcode ) { + remove_wait_queue(&dev->lock.lock_queue, &entry); + if (!retcode) { if (dev->driver->release) dev->driver->release(dev, filp); - drm_lock_free( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ); + drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); } } - - if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) && !dev->driver->release) - { + + if (drm_core_check_feature(dev, DRIVER_HAVE_DMA) + && !dev->driver->release) { dev->driver->reclaim_buffers(dev, filp); } - drm_fasync( -1, filp, 0 ); + drm_fasync(-1, filp, 0); - down( &dev->ctxlist_sem ); - if ( dev->ctxlist && (!list_empty(&dev->ctxlist->head))) { + down(&dev->ctxlist_sem); + if (dev->ctxlist && (!list_empty(&dev->ctxlist->head))) { drm_ctx_list_t *pos, *n; - list_for_each_entry_safe( pos, n, &dev->ctxlist->head, head ) { - if ( pos->tag == priv && - pos->handle != DRM_KERNEL_CONTEXT ) { + list_for_each_entry_safe(pos, n, &dev->ctxlist->head, head) { + if (pos->tag == priv && + pos->handle != DRM_KERNEL_CONTEXT) { if (dev->driver->context_dtor) - dev->driver->context_dtor(dev, pos->handle); + dev->driver->context_dtor(dev, + pos->handle); - drm_ctxbitmap_free( dev, pos->handle ); + drm_ctxbitmap_free(dev, pos->handle); - list_del( &pos->head ); - drm_free( pos, sizeof(*pos), DRM_MEM_CTXLIST ); + list_del(&pos->head); + drm_free(pos, sizeof(*pos), DRM_MEM_CTXLIST); --dev->ctx_count; } } } - up( &dev->ctxlist_sem ); + up(&dev->ctxlist_sem); - down( &dev->struct_sem ); - if ( priv->remove_auth_on_close == 1 ) { + down(&dev->struct_sem); + if (priv->remove_auth_on_close == 1) { drm_file_t *temp = dev->file_first; - while ( temp ) { + while (temp) { temp->authenticated = 0; temp = temp->next; } } - if ( priv->prev ) { + if (priv->prev) { priv->prev->next = priv->next; } else { - dev->file_first = priv->next; + dev->file_first = priv->next; } - if ( priv->next ) { + if (priv->next) { priv->next->prev = priv->prev; } else { - dev->file_last = priv->prev; + dev->file_last = priv->prev; } - up( &dev->struct_sem ); - + up(&dev->struct_sem); + if (dev->driver->free_filp_priv) dev->driver->free_filp_priv(dev, priv); - drm_free( priv, sizeof(*priv), DRM_MEM_FILES ); + drm_free(priv, sizeof(*priv), DRM_MEM_FILES); /* ======================================================== * End inline drm_release */ - atomic_inc( &dev->counts[_DRM_STAT_CLOSES] ); - spin_lock( &dev->count_lock ); - if ( !--dev->open_count ) { - if ( atomic_read( &dev->ioctl_count ) || dev->blocked ) { - DRM_ERROR( "Device busy: %d %d\n", - atomic_read( &dev->ioctl_count ), - dev->blocked ); - spin_unlock( &dev->count_lock ); + atomic_inc(&dev->counts[_DRM_STAT_CLOSES]); + spin_lock(&dev->count_lock); + if (!--dev->open_count) { + if (atomic_read(&dev->ioctl_count) || dev->blocked) { + DRM_ERROR("Device busy: %d %d\n", + atomic_read(&dev->ioctl_count), dev->blocked); + spin_unlock(&dev->count_lock); unlock_kernel(); return -EBUSY; } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); unlock_kernel(); - return drm_takedown( dev ); + return drm_takedown(dev); } - spin_unlock( &dev->count_lock ); + spin_unlock(&dev->count_lock); unlock_kernel(); return retcode; } + EXPORT_SYMBOL(drm_release); /** - * Called whenever a process opens /dev/drm. + * Called whenever a process opens /dev/drm. * * \param inode device inode. * \param filp file pointer. * \param dev device. * \return zero on success or a negative number on failure. - * + * * Creates and initializes a drm_file structure for the file private data in \p * filp and add it into the double linked list in \p dev. */ -static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t *dev) +static int drm_open_helper(struct inode *inode, struct file *filp, + drm_device_t * dev) { - int minor = iminor(inode); - drm_file_t *priv; + int minor = iminor(inode); + drm_file_t *priv; int ret; - if (filp->f_flags & O_EXCL) return -EBUSY; /* No exclusive opens */ - if (!drm_cpu_valid()) return -EINVAL; + if (filp->f_flags & O_EXCL) + return -EBUSY; /* No exclusive opens */ + if (!drm_cpu_valid()) + return -EINVAL; DRM_DEBUG("pid = %d, minor = %d\n", current->pid, minor); - priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); - if(!priv) return -ENOMEM; + priv = drm_alloc(sizeof(*priv), DRM_MEM_FILES); + if (!priv) + return -ENOMEM; memset(priv, 0, sizeof(*priv)); - filp->private_data = priv; - priv->uid = current->euid; - priv->pid = current->pid; - priv->minor = minor; - priv->head = drm_heads[minor]; - priv->ioctl_count = 0; + filp->private_data = priv; + priv->uid = current->euid; + priv->pid = current->pid; + priv->minor = minor; + priv->head = drm_heads[minor]; + priv->ioctl_count = 0; priv->authenticated = capable(CAP_SYS_ADMIN); - priv->lock_count = 0; + priv->lock_count = 0; if (dev->driver->open_helper) { - ret=dev->driver->open_helper(dev, priv); + ret = dev->driver->open_helper(dev, priv); if (ret < 0) goto out_free; } down(&dev->struct_sem); if (!dev->file_last) { - priv->next = NULL; - priv->prev = NULL; + priv->next = NULL; + priv->prev = NULL; dev->file_first = priv; - dev->file_last = priv; + dev->file_last = priv; } else { - priv->next = NULL; - priv->prev = dev->file_last; + priv->next = NULL; + priv->prev = dev->file_last; dev->file_last->next = priv; - dev->file_last = priv; + dev->file_last = priv; } up(&dev->struct_sem); @@ -394,42 +399,48 @@ static int drm_open_helper(struct inode *inode, struct file *filp, drm_device_t } if (!dev->hose) { struct pci_bus *b = pci_bus_b(pci_root_buses.next); - if (b) dev->hose = b->sysdata; + if (b) + dev->hose = b->sysdata; } } #endif return 0; -out_free: + out_free: drm_free(priv, sizeof(*priv), DRM_MEM_FILES); - filp->private_data=NULL; + filp->private_data = NULL; return ret; } /** No-op. */ int drm_flush(struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; DRM_DEBUG("pid = %d, device = 0x%lx, open_count = %d\n", - current->pid, (long)old_encode_dev(priv->head->device), dev->open_count); + current->pid, (long)old_encode_dev(priv->head->device), + dev->open_count); return 0; } + EXPORT_SYMBOL(drm_flush); /** No-op. */ int drm_fasync(int fd, struct file *filp, int on) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - int retcode; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode; - DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, (long)old_encode_dev(priv->head->device)); + DRM_DEBUG("fd = %d, device = 0x%lx\n", fd, + (long)old_encode_dev(priv->head->device)); retcode = fasync_helper(fd, filp, on, &dev->buf_async); - if (retcode < 0) return retcode; + if (retcode < 0) + return retcode; return 0; } + EXPORT_SYMBOL(drm_fasync); /** No-op. */ @@ -437,5 +448,5 @@ unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait) { return 0; } -EXPORT_SYMBOL(drm_poll); +EXPORT_SYMBOL(drm_poll); diff --git a/drivers/char/drm/drm_init.c b/drivers/char/drm/drm_init.c index 62883b749e9..754b934715c 100644 --- a/drivers/char/drm/drm_init.c +++ b/drivers/char/drm/drm_init.c @@ -1,5 +1,5 @@ /** - * \file drm_init.h + * \file drm_init.c * Setup/Cleanup for DRM * * \author Rickard E. (Rik) Faith @@ -43,10 +43,11 @@ int drm_cpu_valid(void) { #if defined(__i386__) - if (boot_cpu_data.x86 == 3) return 0; /* No cmpxchg on a 386 */ + if (boot_cpu_data.x86 == 3) + return 0; /* No cmpxchg on a 386 */ #endif #if defined(__sparc__) && !defined(__sparc_v9__) - return 0; /* No cmpxchg before v9 sparc. */ + return 0; /* No cmpxchg before v9 sparc. */ #endif return 1; } diff --git a/drivers/char/drm/drm_ioc32.c b/drivers/char/drm/drm_ioc32.c index 8087a963639..dd91ff6b474 100644 --- a/drivers/char/drm/drm_ioc32.c +++ b/drivers/char/drm/drm_ioc32.c @@ -68,15 +68,15 @@ #define DRM_IOCTL_WAIT_VBLANK32 DRM_IOWR(0x3a, drm_wait_vblank32_t) typedef struct drm_version_32 { - int version_major; /**< Major version */ - int version_minor; /**< Minor version */ - int version_patchlevel;/**< Patch level */ - u32 name_len; /**< Length of name buffer */ - u32 name; /**< Name of driver */ - u32 date_len; /**< Length of date buffer */ - u32 date; /**< User-space buffer to hold date */ - u32 desc_len; /**< Length of desc buffer */ - u32 desc; /**< User-space buffer to hold desc */ + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ + u32 name_len; /**< Length of name buffer */ + u32 name; /**< Name of driver */ + u32 date_len; /**< Length of date buffer */ + u32 date; /**< User-space buffer to hold date */ + u32 desc_len; /**< Length of desc buffer */ + u32 desc; /**< User-space buffer to hold desc */ } drm_version32_t; static int compat_drm_version(struct file *file, unsigned int cmd, @@ -86,7 +86,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd, drm_version_t __user *version; int err; - if (copy_from_user(&v32, (void __user *) arg, sizeof(v32))) + if (copy_from_user(&v32, (void __user *)arg, sizeof(v32))) return -EFAULT; version = compat_alloc_user_space(sizeof(*version)); @@ -104,7 +104,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_VERSION, (unsigned long) version); + DRM_IOCTL_VERSION, (unsigned long)version); if (err) return err; @@ -116,7 +116,7 @@ static int compat_drm_version(struct file *file, unsigned int cmd, || __get_user(v32.desc_len, &version->desc_len)) return -EFAULT; - if (copy_to_user((void __user *) arg, &v32, sizeof(v32))) + if (copy_to_user((void __user *)arg, &v32, sizeof(v32))) return -EFAULT; return 0; } @@ -133,25 +133,25 @@ static int compat_drm_getunique(struct file *file, unsigned int cmd, drm_unique_t __user *u; int err; - if (copy_from_user(&uq32, (void __user *) arg, sizeof(uq32))) + if (copy_from_user(&uq32, (void __user *)arg, sizeof(uq32))) return -EFAULT; u = compat_alloc_user_space(sizeof(*u)); if (!access_ok(VERIFY_WRITE, u, sizeof(*u))) return -EFAULT; if (__put_user(uq32.unique_len, &u->unique_len) - || __put_user((void __user *)(unsigned long) uq32.unique, + || __put_user((void __user *)(unsigned long)uq32.unique, &u->unique)) return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_GET_UNIQUE, (unsigned long) u); + DRM_IOCTL_GET_UNIQUE, (unsigned long)u); if (err) return err; if (__get_user(uq32.unique_len, &u->unique_len)) return -EFAULT; - if (copy_to_user((void __user *) arg, &uq32, sizeof(uq32))) + if (copy_to_user((void __user *)arg, &uq32, sizeof(uq32))) return -EFAULT; return 0; } @@ -162,28 +162,28 @@ static int compat_drm_setunique(struct file *file, unsigned int cmd, drm_unique32_t uq32; drm_unique_t __user *u; - if (copy_from_user(&uq32, (void __user *) arg, sizeof(uq32))) + if (copy_from_user(&uq32, (void __user *)arg, sizeof(uq32))) return -EFAULT; u = compat_alloc_user_space(sizeof(*u)); if (!access_ok(VERIFY_WRITE, u, sizeof(*u))) return -EFAULT; if (__put_user(uq32.unique_len, &u->unique_len) - || __put_user((void __user *)(unsigned long) uq32.unique, + || __put_user((void __user *)(unsigned long)uq32.unique, &u->unique)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_SET_UNIQUE, (unsigned long) u); + DRM_IOCTL_SET_UNIQUE, (unsigned long)u); } typedef struct drm_map32 { - u32 offset; /**< Requested physical address (0 for SAREA)*/ - u32 size; /**< Requested physical size (bytes) */ - drm_map_type_t type; /**< Type of memory to map */ + u32 offset; /**< Requested physical address (0 for SAREA)*/ + u32 size; /**< Requested physical size (bytes) */ + drm_map_type_t type; /**< Type of memory to map */ drm_map_flags_t flags; /**< Flags */ - u32 handle; /**< User-space: "Handle" to pass to mmap() */ - int mtrr; /**< MTRR slot used */ + u32 handle; /**< User-space: "Handle" to pass to mmap() */ + int mtrr; /**< MTRR slot used */ } drm_map32_t; static int compat_drm_getmap(struct file *file, unsigned int cmd, @@ -205,7 +205,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_GET_MAP, (unsigned long) map); + DRM_IOCTL_GET_MAP, (unsigned long)map); if (err) return err; @@ -217,7 +217,7 @@ static int compat_drm_getmap(struct file *file, unsigned int cmd, || __get_user(m32.mtrr, &map->mtrr)) return -EFAULT; - m32.handle = (unsigned long) handle; + m32.handle = (unsigned long)handle; if (copy_to_user(argp, &m32, sizeof(m32))) return -EFAULT; return 0; @@ -246,7 +246,7 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_ADD_MAP, (unsigned long) map); + DRM_IOCTL_ADD_MAP, (unsigned long)map); if (err) return err; @@ -255,8 +255,8 @@ static int compat_drm_addmap(struct file *file, unsigned int cmd, || __get_user(handle, &map->handle)) return -EFAULT; - m32.handle = (unsigned long) handle; - if (m32.handle != (unsigned long) handle && printk_ratelimit()) + m32.handle = (unsigned long)handle; + if (m32.handle != (unsigned long)handle && printk_ratelimit()) printk(KERN_ERR "compat_drm_addmap truncated handle" " %p for type %d offset %x\n", handle, m32.type, m32.offset); @@ -280,20 +280,20 @@ static int compat_drm_rmmap(struct file *file, unsigned int cmd, map = compat_alloc_user_space(sizeof(*map)); if (!access_ok(VERIFY_WRITE, map, sizeof(*map))) return -EFAULT; - if (__put_user((void *)(unsigned long) handle, &map->handle)) + if (__put_user((void *)(unsigned long)handle, &map->handle)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RM_MAP, (unsigned long) map); + DRM_IOCTL_RM_MAP, (unsigned long)map); } typedef struct drm_client32 { - int idx; /**< Which client desired? */ - int auth; /**< Is client authenticated? */ - u32 pid; /**< Process ID */ - u32 uid; /**< User ID */ - u32 magic; /**< Magic */ - u32 iocs; /**< Ioctl count */ + int idx; /**< Which client desired? */ + int auth; /**< Is client authenticated? */ + u32 pid; /**< Process ID */ + u32 uid; /**< User ID */ + u32 magic; /**< Magic */ + u32 iocs; /**< Ioctl count */ } drm_client32_t; static int compat_drm_getclient(struct file *file, unsigned int cmd, @@ -314,7 +314,7 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_GET_CLIENT, (unsigned long) client); + DRM_IOCTL_GET_CLIENT, (unsigned long)client); if (err) return err; @@ -351,7 +351,7 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_GET_STATS, (unsigned long) stats); + DRM_IOCTL_GET_STATS, (unsigned long)stats); if (err) return err; @@ -368,12 +368,12 @@ static int compat_drm_getstats(struct file *file, unsigned int cmd, } typedef struct drm_buf_desc32 { - int count; /**< Number of buffers of this size */ - int size; /**< Size in bytes */ - int low_mark; /**< Low water mark */ - int high_mark; /**< High water mark */ - int flags; - u32 agp_start; /**< Start address in the AGP aperture */ + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + int flags; + u32 agp_start; /**< Start address in the AGP aperture */ } drm_buf_desc32_t; static int compat_drm_addbufs(struct file *file, unsigned int cmd, @@ -395,7 +395,7 @@ static int compat_drm_addbufs(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_ADD_BUFS, (unsigned long) buf); + DRM_IOCTL_ADD_BUFS, (unsigned long)buf); if (err) return err; @@ -427,12 +427,12 @@ static int compat_drm_markbufs(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_MARK_BUFS, (unsigned long) buf); + DRM_IOCTL_MARK_BUFS, (unsigned long)buf); } typedef struct drm_buf_info32 { - int count; /**< Entries in list */ - u32 list; + int count; /**< Entries in list */ + u32 list; } drm_buf_info32_t; static int compat_drm_infobufs(struct file *file, unsigned int cmd, @@ -451,7 +451,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd, return -EFAULT; count = req32.count; - to = (drm_buf_desc32_t __user *)(unsigned long) req32.list; + to = (drm_buf_desc32_t __user *) (unsigned long)req32.list; if (count < 0) count = 0; if (count > 0 @@ -469,7 +469,7 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_INFO_BUFS, (unsigned long) request); + DRM_IOCTL_INFO_BUFS, (unsigned long)request); if (err) return err; @@ -488,16 +488,16 @@ static int compat_drm_infobufs(struct file *file, unsigned int cmd, } typedef struct drm_buf_pub32 { - int idx; /**< Index into the master buffer list */ - int total; /**< Buffer size */ - int used; /**< Amount of buffer in use (for DMA) */ - u32 address; /**< Address of buffer */ + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + u32 address; /**< Address of buffer */ } drm_buf_pub32_t; typedef struct drm_buf_map32 { - int count; /**< Length of the buffer list */ - u32 virtual; /**< Mmap'd area in user-virtual */ - u32 list; /**< Buffer information */ + int count; /**< Length of the buffer list */ + u32 virtual; /**< Mmap'd area in user-virtual */ + u32 list; /**< Buffer information */ } drm_buf_map32_t; static int compat_drm_mapbufs(struct file *file, unsigned int cmd, @@ -531,7 +531,7 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_MAP_BUFS, (unsigned long) request); + DRM_IOCTL_MAP_BUFS, (unsigned long)request); if (err) return err; @@ -542,21 +542,21 @@ static int compat_drm_mapbufs(struct file *file, unsigned int cmd, if (__copy_in_user(&list32[i], &list[i], offsetof(drm_buf_pub_t, address)) || __get_user(addr, &list[i].address) - || __put_user((unsigned long) addr, + || __put_user((unsigned long)addr, &list32[i].address)) return -EFAULT; if (__put_user(actual, &argp->count) || __get_user(addr, &request->virtual) - || __put_user((unsigned long) addr, &argp->virtual)) + || __put_user((unsigned long)addr, &argp->virtual)) return -EFAULT; return 0; } typedef struct drm_buf_free32 { - int count; - u32 list; + int count; + u32 list; } drm_buf_free32_t; static int compat_drm_freebufs(struct file *file, unsigned int cmd, @@ -573,17 +573,17 @@ static int compat_drm_freebufs(struct file *file, unsigned int cmd, if (!access_ok(VERIFY_WRITE, request, sizeof(*request))) return -EFAULT; if (__put_user(req32.count, &request->count) - || __put_user((int __user *)(unsigned long) req32.list, + || __put_user((int __user *)(unsigned long)req32.list, &request->list)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_FREE_BUFS, (unsigned long) request); + DRM_IOCTL_FREE_BUFS, (unsigned long)request); } typedef struct drm_ctx_priv_map32 { - unsigned int ctx_id; /**< Context requesting private mapping */ - u32 handle; /**< Handle of map */ + unsigned int ctx_id; /**< Context requesting private mapping */ + u32 handle; /**< Handle of map */ } drm_ctx_priv_map32_t; static int compat_drm_setsareactx(struct file *file, unsigned int cmd, @@ -600,12 +600,12 @@ static int compat_drm_setsareactx(struct file *file, unsigned int cmd, if (!access_ok(VERIFY_WRITE, request, sizeof(*request))) return -EFAULT; if (__put_user(req32.ctx_id, &request->ctx_id) - || __put_user((void *)(unsigned long) req32.handle, + || __put_user((void *)(unsigned long)req32.handle, &request->handle)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_SET_SAREA_CTX, (unsigned long) request); + DRM_IOCTL_SET_SAREA_CTX, (unsigned long)request); } static int compat_drm_getsareactx(struct file *file, unsigned int cmd, @@ -628,20 +628,20 @@ static int compat_drm_getsareactx(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_GET_SAREA_CTX, (unsigned long) request); + DRM_IOCTL_GET_SAREA_CTX, (unsigned long)request); if (err) return err; if (__get_user(handle, &request->handle) - || __put_user((unsigned long) handle, &argp->handle)) + || __put_user((unsigned long)handle, &argp->handle)) return -EFAULT; return 0; } typedef struct drm_ctx_res32 { - int count; - u32 contexts; + int count; + u32 contexts; } drm_ctx_res32_t; static int compat_drm_resctx(struct file *file, unsigned int cmd, @@ -659,12 +659,12 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd, if (!access_ok(VERIFY_WRITE, res, sizeof(*res))) return -EFAULT; if (__put_user(res32.count, &res->count) - || __put_user((drm_ctx_t __user *)(unsigned long) res32.contexts, + || __put_user((drm_ctx_t __user *) (unsigned long)res32.contexts, &res->contexts)) return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RES_CTX, (unsigned long) res); + DRM_IOCTL_RES_CTX, (unsigned long)res); if (err) return err; @@ -676,23 +676,23 @@ static int compat_drm_resctx(struct file *file, unsigned int cmd, } typedef struct drm_dma32 { - int context; /**< Context handle */ - int send_count; /**< Number of buffers to send */ - u32 send_indices; /**< List of handles to buffers */ - u32 send_sizes; /**< Lengths of data to send */ + int context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + u32 send_indices; /**< List of handles to buffers */ + u32 send_sizes; /**< Lengths of data to send */ drm_dma_flags_t flags; /**< Flags */ - int request_count; /**< Number of buffers requested */ - int request_size; /**< Desired size for buffers */ - u32 request_indices; /**< Buffer information */ - u32 request_sizes; - int granted_count; /**< Number of buffers granted */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size for buffers */ + u32 request_indices; /**< Buffer information */ + u32 request_sizes; + int granted_count; /**< Number of buffers granted */ } drm_dma32_t; static int compat_drm_dma(struct file *file, unsigned int cmd, unsigned long arg) { drm_dma32_t d32; - drm_dma32_t __user *argp = (void __user *) arg; + drm_dma32_t __user *argp = (void __user *)arg; drm_dma_t __user *d; int err; @@ -705,20 +705,20 @@ static int compat_drm_dma(struct file *file, unsigned int cmd, if (__put_user(d32.context, &d->context) || __put_user(d32.send_count, &d->send_count) - || __put_user((int __user *)(unsigned long) d32.send_indices, + || __put_user((int __user *)(unsigned long)d32.send_indices, &d->send_indices) - || __put_user((int __user *)(unsigned long) d32.send_sizes, + || __put_user((int __user *)(unsigned long)d32.send_sizes, &d->send_sizes) || __put_user(d32.flags, &d->flags) || __put_user(d32.request_count, &d->request_count) - || __put_user((int __user *)(unsigned long) d32.request_indices, + || __put_user((int __user *)(unsigned long)d32.request_indices, &d->request_indices) - || __put_user((int __user *)(unsigned long) d32.request_sizes, + || __put_user((int __user *)(unsigned long)d32.request_sizes, &d->request_sizes)) return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_DMA, (unsigned long) d); + DRM_IOCTL_DMA, (unsigned long)d); if (err) return err; @@ -751,19 +751,19 @@ static int compat_drm_agp_enable(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_ENABLE, (unsigned long) mode); + DRM_IOCTL_AGP_ENABLE, (unsigned long)mode); } typedef struct drm_agp_info32 { - int agp_version_major; - int agp_version_minor; - u32 mode; - u32 aperture_base; /* physical address */ - u32 aperture_size; /* bytes */ - u32 memory_allowed; /* bytes */ - u32 memory_used; - - /* PCI information */ + int agp_version_major; + int agp_version_minor; + u32 mode; + u32 aperture_base; /* physical address */ + u32 aperture_size; /* bytes */ + u32 memory_allowed; /* bytes */ + u32 memory_used; + + /* PCI information */ unsigned short id_vendor; unsigned short id_device; } drm_agp_info32_t; @@ -781,7 +781,7 @@ static int compat_drm_agp_info(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_INFO, (unsigned long) info); + DRM_IOCTL_AGP_INFO, (unsigned long)info); if (err) return err; @@ -806,7 +806,7 @@ typedef struct drm_agp_buffer32 { u32 size; /**< In bytes -- will round to page boundary */ u32 handle; /**< Used for binding / unbinding */ u32 type; /**< Type of memory to allocate */ - u32 physical; /**< Physical used by i810 */ + u32 physical; /**< Physical used by i810 */ } drm_agp_buffer32_t; static int compat_drm_agp_alloc(struct file *file, unsigned int cmd, @@ -827,7 +827,7 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_ALLOC, (unsigned long) request); + DRM_IOCTL_AGP_ALLOC, (unsigned long)request); if (err) return err; @@ -835,7 +835,7 @@ static int compat_drm_agp_alloc(struct file *file, unsigned int cmd, || __get_user(req32.physical, &request->physical) || copy_to_user(argp, &req32, sizeof(req32))) { drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_FREE, (unsigned long) request); + DRM_IOCTL_AGP_FREE, (unsigned long)request); return -EFAULT; } @@ -856,7 +856,7 @@ static int compat_drm_agp_free(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_FREE, (unsigned long) request); + DRM_IOCTL_AGP_FREE, (unsigned long)request); } typedef struct drm_agp_binding32 { @@ -881,7 +881,7 @@ static int compat_drm_agp_bind(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_BIND, (unsigned long) request); + DRM_IOCTL_AGP_BIND, (unsigned long)request); } static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, @@ -898,9 +898,9 @@ static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_AGP_UNBIND, (unsigned long) request); + DRM_IOCTL_AGP_UNBIND, (unsigned long)request); } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ typedef struct drm_scatter_gather32 { u32 size; /**< In bytes -- will round to page boundary */ @@ -923,7 +923,7 @@ static int compat_drm_sg_alloc(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_SG_ALLOC, (unsigned long) request); + DRM_IOCTL_SG_ALLOC, (unsigned long)request); if (err) return err; @@ -950,7 +950,7 @@ static int compat_drm_sg_free(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_SG_FREE, (unsigned long) request); + DRM_IOCTL_SG_FREE, (unsigned long)request); } struct drm_wait_vblank_request32 { @@ -990,7 +990,7 @@ static int compat_drm_wait_vblank(struct file *file, unsigned int cmd, return -EFAULT; err = drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_WAIT_VBLANK, (unsigned long) request); + DRM_IOCTL_WAIT_VBLANK, (unsigned long)request); if (err) return err; @@ -1059,11 +1059,12 @@ long drm_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) lock_kernel(); /* XXX for now */ if (fn != NULL) - ret = (*fn)(filp, cmd, arg); + ret = (*fn) (filp, cmd, arg); else ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); unlock_kernel(); return ret; } + EXPORT_SYMBOL(drm_compat_ioctl); diff --git a/drivers/char/drm/drm_ioctl.c b/drivers/char/drm/drm_ioctl.c index d2ed3ba5aca..9b0feba6b06 100644 --- a/drivers/char/drm/drm_ioctl.c +++ b/drivers/char/drm/drm_ioctl.c @@ -1,5 +1,5 @@ /** - * \file drm_ioctl.h + * \file drm_ioctl.c * IOCTL processing for DRM * * \author Rickard E. (Rik) Faith @@ -40,7 +40,7 @@ /** * Get the bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -50,12 +50,12 @@ * Copies the bus id from drm_device::unique into user space. */ int drm_getunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_unique_t __user *argp = (void __user *)arg; - drm_unique_t u; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_unique_t __user *argp = (void __user *)arg; + drm_unique_t u; if (copy_from_user(&u, argp, sizeof(u))) return -EFAULT; @@ -71,7 +71,7 @@ int drm_getunique(struct inode *inode, struct file *filp, /** * Set the bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. @@ -84,34 +84,39 @@ int drm_getunique(struct inode *inode, struct file *filp, * version 1.1 or greater. */ int drm_setunique(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_unique_t u; - int domain, bus, slot, func, ret; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_unique_t u; + int domain, bus, slot, func, ret; - if (dev->unique_len || dev->unique) return -EBUSY; + if (dev->unique_len || dev->unique) + return -EBUSY; - if (copy_from_user(&u, (drm_unique_t __user *)arg, sizeof(u))) + if (copy_from_user(&u, (drm_unique_t __user *) arg, sizeof(u))) return -EFAULT; - if (!u.unique_len || u.unique_len > 1024) return -EINVAL; + if (!u.unique_len || u.unique_len > 1024) + return -EINVAL; dev->unique_len = u.unique_len; - dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); - if(!dev->unique) return -ENOMEM; + dev->unique = drm_alloc(u.unique_len + 1, DRM_MEM_DRIVER); + if (!dev->unique) + return -ENOMEM; if (copy_from_user(dev->unique, u.unique, dev->unique_len)) return -EFAULT; dev->unique[dev->unique_len] = '\0'; - dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + strlen(dev->unique) + 2, - DRM_MEM_DRIVER); + dev->devname = + drm_alloc(strlen(dev->driver->pci_driver.name) + + strlen(dev->unique) + 2, DRM_MEM_DRIVER); if (!dev->devname) return -ENOMEM; - sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); + sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, + dev->unique); /* Return error if the busid submitted doesn't match the device's actual * busid. @@ -121,18 +126,16 @@ int drm_setunique(struct inode *inode, struct file *filp, return DRM_ERR(EINVAL); domain = bus >> 8; bus &= 0xff; - + if ((domain != dev->pci_domain) || (bus != dev->pci_bus) || - (slot != dev->pci_slot) || - (func != dev->pci_func)) + (slot != dev->pci_slot) || (func != dev->pci_func)) return -EINVAL; return 0; } -static int -drm_set_busid(drm_device_t *dev) +static int drm_set_busid(drm_device_t * dev) { if (dev->unique != NULL) return EBUSY; @@ -143,19 +146,20 @@ drm_set_busid(drm_device_t *dev) return ENOMEM; snprintf(dev->unique, dev->unique_len, "pci:%04x:%02x:%02x.%d", - dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); + dev->pci_domain, dev->pci_bus, dev->pci_slot, dev->pci_func); - dev->devname = drm_alloc(strlen(dev->driver->pci_driver.name) + dev->unique_len + 2, - DRM_MEM_DRIVER); + dev->devname = + drm_alloc(strlen(dev->driver->pci_driver.name) + dev->unique_len + + 2, DRM_MEM_DRIVER); if (dev->devname == NULL) return ENOMEM; - sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, dev->unique); + sprintf(dev->devname, "%s@%s", dev->driver->pci_driver.name, + dev->unique); return 0; } - /** * Get a mapping information. * @@ -163,23 +167,23 @@ drm_set_busid(drm_device_t *dev) * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_map structure. - * + * * \return zero on success or a negative number on failure. * * Searches for the mapping with the specified offset and copies its information * into userspace */ -int drm_getmap( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getmap(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_map_t __user *argp = (void __user *)arg; - drm_map_t map; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t __user *argp = (void __user *)arg; + drm_map_t map; drm_map_list_t *r_list = NULL; struct list_head *list; - int idx; - int i; + int idx; + int i; if (copy_from_user(&map, argp, sizeof(map))) return -EFAULT; @@ -193,26 +197,27 @@ int drm_getmap( struct inode *inode, struct file *filp, i = 0; list_for_each(list, &dev->maplist->head) { - if(i == idx) { + if (i == idx) { r_list = list_entry(list, drm_map_list_t, head); break; } i++; } - if(!r_list || !r_list->map) { + if (!r_list || !r_list->map) { up(&dev->struct_sem); return -EINVAL; } map.offset = r_list->map->offset; - map.size = r_list->map->size; - map.type = r_list->map->type; - map.flags = r_list->map->flags; - map.handle = (void *)(unsigned long) r_list->user_token; - map.mtrr = r_list->map->mtrr; + map.size = r_list->map->size; + map.type = r_list->map->type; + map.flags = r_list->map->flags; + map.handle = (void *)(unsigned long)r_list->user_token; + map.mtrr = r_list->map->mtrr; up(&dev->struct_sem); - if (copy_to_user(argp, &map, sizeof(map))) return -EFAULT; + if (copy_to_user(argp, &map, sizeof(map))) + return -EFAULT; return 0; } @@ -223,83 +228,81 @@ int drm_getmap( struct inode *inode, struct file *filp, * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_client structure. - * + * * \return zero on success or a negative number on failure. * * Searches for the client with the specified index and copies its information * into userspace */ -int drm_getclient( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getclient(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_client_t __user *argp = (void __user *)arg; drm_client_t client; - drm_file_t *pt; - int idx; - int i; + drm_file_t *pt; + int idx; + int i; if (copy_from_user(&client, argp, sizeof(client))) return -EFAULT; idx = client.idx; down(&dev->struct_sem); - for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) - ; + for (i = 0, pt = dev->file_first; i < idx && pt; i++, pt = pt->next) ; if (!pt) { up(&dev->struct_sem); return -EINVAL; } - client.auth = pt->authenticated; - client.pid = pt->pid; - client.uid = pt->uid; + client.auth = pt->authenticated; + client.pid = pt->pid; + client.uid = pt->uid; client.magic = pt->magic; - client.iocs = pt->ioctl_count; + client.iocs = pt->ioctl_count; up(&dev->struct_sem); - if (copy_to_user((drm_client_t __user *)arg, &client, sizeof(client))) + if (copy_to_user((drm_client_t __user *) arg, &client, sizeof(client))) return -EFAULT; return 0; } -/** - * Get statistics information. - * +/** + * Get statistics information. + * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_stats structure. - * + * * \return zero on success or a negative number on failure. */ -int drm_getstats( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_getstats(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_stats_t stats; - int i; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_stats_t stats; + int i; memset(&stats, 0, sizeof(stats)); - + down(&dev->struct_sem); for (i = 0; i < dev->counters; i++) { if (dev->types[i] == _DRM_STAT_LOCK) stats.data[i].value - = (dev->lock.hw_lock - ? dev->lock.hw_lock->lock : 0); - else + = (dev->lock.hw_lock ? dev->lock.hw_lock->lock : 0); + else stats.data[i].value = atomic_read(&dev->counts[i]); - stats.data[i].type = dev->types[i]; + stats.data[i].type = dev->types[i]; } - + stats.count = dev->counters; up(&dev->struct_sem); - if (copy_to_user((drm_stats_t __user *)arg, &stats, sizeof(stats))) + if (copy_to_user((drm_stats_t __user *) arg, &stats, sizeof(stats))) return -EFAULT; return 0; } @@ -352,7 +355,8 @@ int drm_setversion(DRM_IOCTL_ARGS) if (sv.drm_dd_major != -1) { if (sv.drm_dd_major != version.version_major || - sv.drm_dd_minor < 0 || sv.drm_dd_minor > version.version_minor) + sv.drm_dd_minor < 0 + || sv.drm_dd_minor > version.version_minor) return EINVAL; if (dev->driver->set_version) @@ -363,7 +367,7 @@ int drm_setversion(DRM_IOCTL_ARGS) /** No-op ioctl. */ int drm_noop(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { DRM_DEBUG("\n"); return 0; diff --git a/drivers/char/drm/drm_irq.c b/drivers/char/drm/drm_irq.c index cdd4aecd25e..b0d4b236e83 100644 --- a/drivers/char/drm/drm_irq.c +++ b/drivers/char/drm/drm_irq.c @@ -1,5 +1,5 @@ /** - * \file drm_irq.h + * \file drm_irq.c * IRQ support * * \author Rickard E. (Rik) Faith @@ -39,19 +39,19 @@ /** * Get interrupt from bus id. - * + * * \param inode device inode. * \param filp file pointer. * \param cmd command. * \param arg user argument, pointing to a drm_irq_busid structure. * \return zero on success or a negative number on failure. - * + * * Finds the PCI device with the specified bus id and gets its IRQ number. * This IOCTL is deprecated, and will now return EINVAL for any busid not equal * to that of the device that this DRM instance attached to. */ int drm_irq_by_busid(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -66,14 +66,12 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp, if ((p.busnum >> 8) != dev->pci_domain || (p.busnum & 0xff) != dev->pci_bus || - p.devnum != dev->pci_slot || - p.funcnum != dev->pci_func) + p.devnum != dev->pci_slot || p.funcnum != dev->pci_func) return -EINVAL; p.irq = dev->irq; - DRM_DEBUG("%d:%d:%d => IRQ %d\n", - p.busnum, p.devnum, p.funcnum, p.irq); + DRM_DEBUG("%d:%d:%d => IRQ %d\n", p.busnum, p.devnum, p.funcnum, p.irq); if (copy_to_user(argp, &p, sizeof(p))) return -EFAULT; return 0; @@ -89,61 +87,61 @@ int drm_irq_by_busid(struct inode *inode, struct file *filp, * \c drm_driver_irq_preinstall() and \c drm_driver_irq_postinstall() functions * before and after the installation. */ -static int drm_irq_install( drm_device_t *dev ) +static int drm_irq_install(drm_device_t * dev) { int ret; - unsigned long sh_flags=0; + unsigned long sh_flags = 0; if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return -EINVAL; - if ( dev->irq == 0 ) + if (dev->irq == 0) return -EINVAL; - down( &dev->struct_sem ); + down(&dev->struct_sem); /* Driver must have been initialized */ - if ( !dev->dev_private ) { - up( &dev->struct_sem ); + if (!dev->dev_private) { + up(&dev->struct_sem); return -EINVAL; } - if ( dev->irq_enabled ) { - up( &dev->struct_sem ); + if (dev->irq_enabled) { + up(&dev->struct_sem); return -EBUSY; } dev->irq_enabled = 1; - up( &dev->struct_sem ); + up(&dev->struct_sem); - DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq); if (drm_core_check_feature(dev, DRIVER_IRQ_VBL)) { init_waitqueue_head(&dev->vbl_queue); - - spin_lock_init( &dev->vbl_lock ); - - INIT_LIST_HEAD( &dev->vbl_sigs.head ); - + + spin_lock_init(&dev->vbl_lock); + + INIT_LIST_HEAD(&dev->vbl_sigs.head); + dev->vbl_pending = 0; } - /* Before installing handler */ + /* Before installing handler */ dev->driver->irq_preinstall(dev); - /* Install handler */ + /* Install handler */ if (drm_core_check_feature(dev, DRIVER_IRQ_SHARED)) sh_flags = SA_SHIRQ; - - ret = request_irq( dev->irq, dev->driver->irq_handler, - sh_flags, dev->devname, dev ); - if ( ret < 0 ) { - down( &dev->struct_sem ); + + ret = request_irq(dev->irq, dev->driver->irq_handler, + sh_flags, dev->devname, dev); + if (ret < 0) { + down(&dev->struct_sem); dev->irq_enabled = 0; - up( &dev->struct_sem ); + up(&dev->struct_sem); return ret; } - /* After installing handler */ + /* After installing handler */ dev->driver->irq_postinstall(dev); return 0; @@ -156,29 +154,30 @@ static int drm_irq_install( drm_device_t *dev ) * * Calls the driver's \c drm_driver_irq_uninstall() function, and stops the irq. */ -int drm_irq_uninstall( drm_device_t *dev ) +int drm_irq_uninstall(drm_device_t * dev) { int irq_enabled; if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return -EINVAL; - down( &dev->struct_sem ); + down(&dev->struct_sem); irq_enabled = dev->irq_enabled; dev->irq_enabled = 0; - up( &dev->struct_sem ); + up(&dev->struct_sem); - if ( !irq_enabled ) + if (!irq_enabled) return -EINVAL; - DRM_DEBUG( "%s: irq=%d\n", __FUNCTION__, dev->irq ); + DRM_DEBUG("%s: irq=%d\n", __FUNCTION__, dev->irq); dev->driver->irq_uninstall(dev); - free_irq( dev->irq, dev ); + free_irq(dev->irq, dev); return 0; } + EXPORT_SYMBOL(drm_irq_uninstall); /** @@ -192,30 +191,30 @@ EXPORT_SYMBOL(drm_irq_uninstall); * * Calls irq_install() or irq_uninstall() according to \p arg. */ -int drm_control( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_control(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_control_t ctl; - + /* if we haven't irq we fallback for compatibility reasons - this used to be a separate function in drm_dma.h */ - if ( copy_from_user( &ctl, (drm_control_t __user *)arg, sizeof(ctl) ) ) + if (copy_from_user(&ctl, (drm_control_t __user *) arg, sizeof(ctl))) return -EFAULT; - switch ( ctl.func ) { + switch (ctl.func) { case DRM_INST_HANDLER: if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return 0; if (dev->if_version < DRM_IF_VERSION(1, 2) && ctl.irq != dev->irq) return -EINVAL; - return drm_irq_install( dev ); + return drm_irq_install(dev); case DRM_UNINST_HANDLER: if (!drm_core_check_feature(dev, DRIVER_HAVE_IRQ)) return 0; - return drm_irq_uninstall( dev ); + return drm_irq_uninstall(dev); default: return -EINVAL; } @@ -230,7 +229,7 @@ int drm_control( struct inode *inode, struct file *filp, * \param data user argument, pointing to a drm_wait_vblank structure. * \return zero on success or a negative number on failure. * - * Verifies the IRQ is installed. + * Verifies the IRQ is installed. * * If a signal is requested checks if this task has already scheduled the same signal * for the same vblank sequence number - nothing to be done in @@ -240,7 +239,7 @@ int drm_control( struct inode *inode, struct file *filp, * * If a signal is not requested, then calls vblank_wait(). */ -int drm_wait_vblank( DRM_IOCTL_ARGS ) +int drm_wait_vblank(DRM_IOCTL_ARGS) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -256,11 +255,11 @@ int drm_wait_vblank( DRM_IOCTL_ARGS ) if (!dev->irq) return -EINVAL; - DRM_COPY_FROM_USER_IOCTL( vblwait, argp, sizeof(vblwait) ); + DRM_COPY_FROM_USER_IOCTL(vblwait, argp, sizeof(vblwait)); - switch ( vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK ) { + switch (vblwait.request.type & ~_DRM_VBLANK_FLAGS_MASK) { case _DRM_VBLANK_RELATIVE: - vblwait.request.sequence += atomic_read( &dev->vbl_received ); + vblwait.request.sequence += atomic_read(&dev->vbl_received); vblwait.request.type &= ~_DRM_VBLANK_RELATIVE; case _DRM_VBLANK_ABSOLUTE: break; @@ -269,64 +268,68 @@ int drm_wait_vblank( DRM_IOCTL_ARGS ) } flags = vblwait.request.type & _DRM_VBLANK_FLAGS_MASK; - - if ( flags & _DRM_VBLANK_SIGNAL ) { + + if (flags & _DRM_VBLANK_SIGNAL) { unsigned long irqflags; drm_vbl_sig_t *vbl_sig; - - vblwait.reply.sequence = atomic_read( &dev->vbl_received ); - spin_lock_irqsave( &dev->vbl_lock, irqflags ); + vblwait.reply.sequence = atomic_read(&dev->vbl_received); + + spin_lock_irqsave(&dev->vbl_lock, irqflags); /* Check if this task has already scheduled the same signal * for the same vblank sequence number; nothing to be done in * that case */ - list_for_each_entry( vbl_sig, &dev->vbl_sigs.head, head ) { + list_for_each_entry(vbl_sig, &dev->vbl_sigs.head, head) { if (vbl_sig->sequence == vblwait.request.sequence && vbl_sig->info.si_signo == vblwait.request.signal - && vbl_sig->task == current) - { - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + && vbl_sig->task == current) { + spin_unlock_irqrestore(&dev->vbl_lock, + irqflags); goto done; } } - if ( dev->vbl_pending >= 100 ) { - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + if (dev->vbl_pending >= 100) { + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); return -EBUSY; } dev->vbl_pending++; - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); - if ( !( vbl_sig = drm_alloc( sizeof( drm_vbl_sig_t ), DRM_MEM_DRIVER ) ) ) { + if (! + (vbl_sig = + drm_alloc(sizeof(drm_vbl_sig_t), DRM_MEM_DRIVER))) { return -ENOMEM; } - memset( (void *)vbl_sig, 0, sizeof(*vbl_sig) ); + memset((void *)vbl_sig, 0, sizeof(*vbl_sig)); vbl_sig->sequence = vblwait.request.sequence; vbl_sig->info.si_signo = vblwait.request.signal; vbl_sig->task = current; - spin_lock_irqsave( &dev->vbl_lock, irqflags ); + spin_lock_irqsave(&dev->vbl_lock, irqflags); - list_add_tail( (struct list_head *) vbl_sig, &dev->vbl_sigs.head ); + list_add_tail((struct list_head *)vbl_sig, &dev->vbl_sigs.head); - spin_unlock_irqrestore( &dev->vbl_lock, irqflags ); + spin_unlock_irqrestore(&dev->vbl_lock, irqflags); } else { if (dev->driver->vblank_wait) - ret = dev->driver->vblank_wait( dev, &vblwait.request.sequence ); + ret = + dev->driver->vblank_wait(dev, + &vblwait.request.sequence); - do_gettimeofday( &now ); + do_gettimeofday(&now); vblwait.reply.tval_sec = now.tv_sec; vblwait.reply.tval_usec = now.tv_usec; } -done: - DRM_COPY_TO_USER_IOCTL( argp, vblwait, sizeof(vblwait) ); + done: + DRM_COPY_TO_USER_IOCTL(argp, vblwait, sizeof(vblwait)); return ret; } @@ -340,31 +343,31 @@ done: * * If a signal is not requested, then calls vblank_wait(). */ -void drm_vbl_send_signals( drm_device_t *dev ) +void drm_vbl_send_signals(drm_device_t * dev) { struct list_head *list, *tmp; drm_vbl_sig_t *vbl_sig; - unsigned int vbl_seq = atomic_read( &dev->vbl_received ); + unsigned int vbl_seq = atomic_read(&dev->vbl_received); unsigned long flags; - spin_lock_irqsave( &dev->vbl_lock, flags ); + spin_lock_irqsave(&dev->vbl_lock, flags); - list_for_each_safe( list, tmp, &dev->vbl_sigs.head ) { - vbl_sig = list_entry( list, drm_vbl_sig_t, head ); - if ( ( vbl_seq - vbl_sig->sequence ) <= (1<<23) ) { + list_for_each_safe(list, tmp, &dev->vbl_sigs.head) { + vbl_sig = list_entry(list, drm_vbl_sig_t, head); + if ((vbl_seq - vbl_sig->sequence) <= (1 << 23)) { vbl_sig->info.si_code = vbl_seq; - send_sig_info( vbl_sig->info.si_signo, &vbl_sig->info, vbl_sig->task ); + send_sig_info(vbl_sig->info.si_signo, &vbl_sig->info, + vbl_sig->task); - list_del( list ); + list_del(list); - drm_free( vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER ); + drm_free(vbl_sig, sizeof(*vbl_sig), DRM_MEM_DRIVER); dev->vbl_pending--; } } - spin_unlock_irqrestore( &dev->vbl_lock, flags ); + spin_unlock_irqrestore(&dev->vbl_lock, flags); } -EXPORT_SYMBOL(drm_vbl_send_signals); - +EXPORT_SYMBOL(drm_vbl_send_signals); diff --git a/drivers/char/drm/drm_lock.c b/drivers/char/drm/drm_lock.c index 4702d863bcc..b276ae8a663 100644 --- a/drivers/char/drm/drm_lock.c +++ b/drivers/char/drm/drm_lock.c @@ -1,7 +1,7 @@ /** - * \file drm_lock.h + * \file drm_lock.c * IOCTLs for locking - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -35,12 +35,12 @@ #include "drmP.h" -static int drm_lock_transfer(drm_device_t *dev, +static int drm_lock_transfer(drm_device_t * dev, __volatile__ unsigned int *lock, unsigned int context); static int drm_notifier(void *priv); -/** +/** * Lock ioctl. * * \param inode device inode. @@ -51,91 +51,89 @@ static int drm_notifier(void *priv); * * Add the current task to the lock wait queue, and attempt to take to lock. */ -int drm_lock( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_lock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - DECLARE_WAITQUEUE( entry, current ); - drm_lock_t lock; - int ret = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + DECLARE_WAITQUEUE(entry, current); + drm_lock_t lock; + int ret = 0; ++priv->lock_count; - if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock))) return -EFAULT; - if ( lock.context == DRM_KERNEL_CONTEXT ) { - DRM_ERROR( "Process %d using kernel context %d\n", - current->pid, lock.context ); - return -EINVAL; - } + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); + return -EINVAL; + } - DRM_DEBUG( "%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", - lock.context, current->pid, - dev->lock.hw_lock->lock, lock.flags ); + DRM_DEBUG("%d (pid %d) requests lock (0x%08x), flags = 0x%08x\n", + lock.context, current->pid, + dev->lock.hw_lock->lock, lock.flags); if (drm_core_check_feature(dev, DRIVER_DMA_QUEUE)) - if ( lock.context < 0 ) + if (lock.context < 0) return -EINVAL; - add_wait_queue( &dev->lock.lock_queue, &entry ); + add_wait_queue(&dev->lock.lock_queue, &entry); for (;;) { __set_current_state(TASK_INTERRUPTIBLE); - if ( !dev->lock.hw_lock ) { + if (!dev->lock.hw_lock) { /* Device has been unregistered */ ret = -EINTR; break; } - if ( drm_lock_take( &dev->lock.hw_lock->lock, - lock.context ) ) { - dev->lock.filp = filp; + if (drm_lock_take(&dev->lock.hw_lock->lock, lock.context)) { + dev->lock.filp = filp; dev->lock.lock_time = jiffies; - atomic_inc( &dev->counts[_DRM_STAT_LOCKS] ); - break; /* Got lock */ + atomic_inc(&dev->counts[_DRM_STAT_LOCKS]); + break; /* Got lock */ } - + /* Contention */ schedule(); - if ( signal_pending( current ) ) { + if (signal_pending(current)) { ret = -ERESTARTSYS; break; } } __set_current_state(TASK_RUNNING); - remove_wait_queue( &dev->lock.lock_queue, &entry ); + remove_wait_queue(&dev->lock.lock_queue, &entry); - sigemptyset( &dev->sigmask ); - sigaddset( &dev->sigmask, SIGSTOP ); - sigaddset( &dev->sigmask, SIGTSTP ); - sigaddset( &dev->sigmask, SIGTTIN ); - sigaddset( &dev->sigmask, SIGTTOU ); + sigemptyset(&dev->sigmask); + sigaddset(&dev->sigmask, SIGSTOP); + sigaddset(&dev->sigmask, SIGTSTP); + sigaddset(&dev->sigmask, SIGTTIN); + sigaddset(&dev->sigmask, SIGTTOU); dev->sigdata.context = lock.context; - dev->sigdata.lock = dev->lock.hw_lock; - block_all_signals( drm_notifier, - &dev->sigdata, &dev->sigmask ); - + dev->sigdata.lock = dev->lock.hw_lock; + block_all_signals(drm_notifier, &dev->sigdata, &dev->sigmask); + if (dev->driver->dma_ready && (lock.flags & _DRM_LOCK_READY)) dev->driver->dma_ready(dev); - - if ( dev->driver->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT )) + + if (dev->driver->dma_quiescent && (lock.flags & _DRM_LOCK_QUIESCENT)) return dev->driver->dma_quiescent(dev); - - /* dev->driver->kernel_context_switch isn't used by any of the x86 + + /* dev->driver->kernel_context_switch isn't used by any of the x86 * drivers but is used by the Sparc driver. */ - - if (dev->driver->kernel_context_switch && + + if (dev->driver->kernel_context_switch && dev->last_context != lock.context) { - dev->driver->kernel_context_switch(dev, dev->last_context, - lock.context); + dev->driver->kernel_context_switch(dev, dev->last_context, + lock.context); } - DRM_DEBUG( "%d %s\n", lock.context, ret ? "interrupted" : "has lock" ); + DRM_DEBUG("%d %s\n", lock.context, ret ? "interrupted" : "has lock"); - return ret; + return ret; } -/** +/** * Unlock ioctl. * * \param inode device inode. @@ -146,23 +144,23 @@ int drm_lock( struct inode *inode, struct file *filp, * * Transfer and free the lock. */ -int drm_unlock( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_unlock(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_lock_t lock; - if ( copy_from_user( &lock, (drm_lock_t __user *)arg, sizeof(lock) ) ) + if (copy_from_user(&lock, (drm_lock_t __user *) arg, sizeof(lock))) return -EFAULT; - if ( lock.context == DRM_KERNEL_CONTEXT ) { - DRM_ERROR( "Process %d using kernel context %d\n", - current->pid, lock.context ); + if (lock.context == DRM_KERNEL_CONTEXT) { + DRM_ERROR("Process %d using kernel context %d\n", + current->pid, lock.context); return -EINVAL; } - atomic_inc( &dev->counts[_DRM_STAT_UNLOCKS] ); + atomic_inc(&dev->counts[_DRM_STAT_UNLOCKS]); /* kernel_context_switch isn't used by any of the x86 drm * modules but is required by the Sparc driver. @@ -170,12 +168,12 @@ int drm_unlock( struct inode *inode, struct file *filp, if (dev->driver->kernel_context_switch_unlock) dev->driver->kernel_context_switch_unlock(dev, &lock); else { - drm_lock_transfer( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ); - - if ( drm_lock_free( dev, &dev->lock.hw_lock->lock, - DRM_KERNEL_CONTEXT ) ) { - DRM_ERROR( "\n" ); + drm_lock_transfer(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT); + + if (drm_lock_free(dev, &dev->lock.hw_lock->lock, + DRM_KERNEL_CONTEXT)) { + DRM_ERROR("\n"); } } @@ -198,8 +196,10 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) do { old = *lock; - if (old & _DRM_LOCK_HELD) new = old | _DRM_LOCK_CONT; - else new = context | _DRM_LOCK_HELD; + if (old & _DRM_LOCK_HELD) + new = old | _DRM_LOCK_CONT; + else + new = context | _DRM_LOCK_HELD; prev = cmpxchg(lock, old, new); } while (prev != old); if (_DRM_LOCKING_CONTEXT(old) == context) { @@ -212,7 +212,7 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) } } if (new == (context | _DRM_LOCK_HELD)) { - /* Have lock */ + /* Have lock */ return 1; } return 0; @@ -220,8 +220,8 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) /** * This takes a lock forcibly and hands it to context. Should ONLY be used - * inside *_unlock to give lock to kernel before calling *_dma_schedule. - * + * inside *_unlock to give lock to kernel before calling *_dma_schedule. + * * \param dev DRM device. * \param lock lock pointer. * \param context locking context. @@ -230,7 +230,7 @@ int drm_lock_take(__volatile__ unsigned int *lock, unsigned int context) * Resets the lock file pointer. * Marks the lock as held by the given context, via the \p cmpxchg instruction. */ -static int drm_lock_transfer(drm_device_t *dev, +static int drm_lock_transfer(drm_device_t * dev, __volatile__ unsigned int *lock, unsigned int context) { @@ -238,8 +238,8 @@ static int drm_lock_transfer(drm_device_t *dev, dev->lock.filp = NULL; do { - old = *lock; - new = context | _DRM_LOCK_HELD; + old = *lock; + new = context | _DRM_LOCK_HELD; prev = cmpxchg(lock, old, new); } while (prev != old); return 1; @@ -247,30 +247,29 @@ static int drm_lock_transfer(drm_device_t *dev, /** * Free lock. - * + * * \param dev DRM device. * \param lock lock. * \param context context. - * + * * Resets the lock file pointer. * Marks the lock as not held, via the \p cmpxchg instruction. Wakes any task * waiting on the lock queue. */ -int drm_lock_free(drm_device_t *dev, - __volatile__ unsigned int *lock, unsigned int context) +int drm_lock_free(drm_device_t * dev, + __volatile__ unsigned int *lock, unsigned int context) { unsigned int old, new, prev; dev->lock.filp = NULL; do { - old = *lock; - new = 0; + old = *lock; + new = 0; prev = cmpxchg(lock, old, new); } while (prev != old); if (_DRM_LOCK_IS_HELD(old) && _DRM_LOCKING_CONTEXT(old) != context) { DRM_ERROR("%d freed heavyweight lock held by %d\n", - context, - _DRM_LOCKING_CONTEXT(old)); + context, _DRM_LOCKING_CONTEXT(old)); return 1; } wake_up_interruptible(&dev->lock.lock_queue); @@ -290,19 +289,19 @@ int drm_lock_free(drm_device_t *dev, */ static int drm_notifier(void *priv) { - drm_sigdata_t *s = (drm_sigdata_t *)priv; - unsigned int old, new, prev; - + drm_sigdata_t *s = (drm_sigdata_t *) priv; + unsigned int old, new, prev; - /* Allow signal delivery if lock isn't held */ + /* Allow signal delivery if lock isn't held */ if (!s->lock || !_DRM_LOCK_IS_HELD(s->lock->lock) - || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) return 1; + || _DRM_LOCKING_CONTEXT(s->lock->lock) != s->context) + return 1; - /* Otherwise, set flag to force call to - drmUnlock */ + /* Otherwise, set flag to force call to + drmUnlock */ do { - old = s->lock->lock; - new = old | _DRM_LOCK_CONT; + old = s->lock->lock; + new = old | _DRM_LOCK_CONT; prev = cmpxchg(&s->lock->lock, old, new); } while (prev != old); return 0; diff --git a/drivers/char/drm/drm_memory.c b/drivers/char/drm/drm_memory.c index ff483fb418a..2c74155aa84 100644 --- a/drivers/char/drm/drm_memory.c +++ b/drivers/char/drm/drm_memory.c @@ -1,12 +1,12 @@ -/** - * \file drm_memory.h +/** + * \file drm_memory.c * Memory management wrappers for DRM * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ -/* +/* * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -48,7 +48,7 @@ void drm_mem_init(void) /** * Called when "/proc/dri/%dev%/mem" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -57,10 +57,10 @@ void drm_mem_init(void) * \param data private data. * \return number of written bytes. * - * No-op. + * No-op. */ int drm_mem_info(char *buf, char **start, off_t offset, - int len, int *eof, void *data) + int len, int *eof, void *data) { return 0; } @@ -70,7 +70,8 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) { void *pt; - if (!(pt = kmalloc(size, GFP_KERNEL))) return NULL; + if (!(pt = kmalloc(size, GFP_KERNEL))) + return NULL; if (oldpt && oldsize) { memcpy(pt, oldpt, oldsize); kfree(oldpt); @@ -90,21 +91,20 @@ void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area) unsigned long drm_alloc_pages(int order, int area) { unsigned long address; - unsigned long bytes = PAGE_SIZE << order; + unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; address = __get_free_pages(GFP_KERNEL, order); - if (!address) + if (!address) return 0; - /* Zero */ + /* Zero */ memset((void *)address, 0, bytes); - /* Reserve */ + /* Reserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } @@ -113,7 +113,7 @@ unsigned long drm_alloc_pages(int order, int area) /** * Free pages. - * + * * \param address address of the pages to free. * \param order size order. * \param area memory area. (Not used.) @@ -124,49 +124,51 @@ void drm_free_pages(unsigned long address, int order, int area) { unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; - if (!address) + if (!address) return; /* Unreserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } free_pages(address, order); } - #if __OS_HAS_AGP /** Wrapper around agp_allocate_memory() */ -DRM_AGP_MEM *drm_alloc_agp(drm_device_t *dev, int pages, u32 type) +DRM_AGP_MEM *drm_alloc_agp(drm_device_t * dev, int pages, u32 type) { return drm_agp_allocate_memory(dev->agp->bridge, pages, type); } + EXPORT_SYMBOL(drm_alloc_agp); /** Wrapper around agp_free_memory() */ -int drm_free_agp(DRM_AGP_MEM *handle, int pages) +int drm_free_agp(DRM_AGP_MEM * handle, int pages) { return drm_agp_free_memory(handle) ? 0 : -EINVAL; } + EXPORT_SYMBOL(drm_free_agp); /** Wrapper around agp_bind_memory() */ -int drm_bind_agp(DRM_AGP_MEM *handle, unsigned int start) +int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start) { return drm_agp_bind_memory(handle, start); } + EXPORT_SYMBOL(drm_bind_agp); /** Wrapper around agp_unbind_memory() */ -int drm_unbind_agp(DRM_AGP_MEM *handle) +int drm_unbind_agp(DRM_AGP_MEM * handle) { return drm_agp_unbind_memory(handle); } + EXPORT_SYMBOL(drm_unbind_agp); -#endif /* agp */ -#endif /* debug_memory */ +#endif /* agp */ +#endif /* debug_memory */ diff --git a/drivers/char/drm/drm_memory.h b/drivers/char/drm/drm_memory.h index 422b9426870..3732a61c376 100644 --- a/drivers/char/drm/drm_memory.h +++ b/drivers/char/drm/drm_memory.h @@ -1,12 +1,12 @@ -/** - * \file drm_memory.h +/** + * \file drm_memory.h * Memory management wrappers for DRM * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ -/* +/* * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com * * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. @@ -40,7 +40,7 @@ /** * Cut down version of drm_memory_debug.h, which used to be called - * drm_memory.h. + * drm_memory.h. */ #if __OS_HAS_AGP @@ -60,8 +60,8 @@ /* * Find the drm_map that covers the range [offset, offset+size). */ -static inline drm_map_t * -drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) +static inline drm_map_t *drm_lookup_map(unsigned long offset, + unsigned long size, drm_device_t * dev) { struct list_head *list; drm_map_list_t *r_list; @@ -72,16 +72,18 @@ drm_lookup_map (unsigned long offset, unsigned long size, drm_device_t *dev) map = r_list->map; if (!map) continue; - if (map->offset <= offset && (offset + size) <= (map->offset + map->size)) + if (map->offset <= offset + && (offset + size) <= (map->offset + map->size)) return map; } return NULL; } -static inline void * -agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *agp_remap(unsigned long offset, unsigned long size, + drm_device_t * dev) { - unsigned long *phys_addr_map, i, num_pages = PAGE_ALIGN(size) / PAGE_SIZE; + unsigned long *phys_addr_map, i, num_pages = + PAGE_ALIGN(size) / PAGE_SIZE; struct drm_agp_mem *agpmem; struct page **page_map; void *addr; @@ -94,7 +96,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) if (agpmem->bound <= offset - && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= (offset + size)) + && (agpmem->bound + (agpmem->pages << PAGE_SHIFT)) >= + (offset + size)) break; if (!agpmem) return NULL; @@ -109,7 +112,8 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) if (!page_map) return NULL; - phys_addr_map = agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; + phys_addr_map = + agpmem->memory->memory + (offset - agpmem->bound) / PAGE_SIZE; for (i = 0; i < num_pages; ++i) page_map[i] = pfn_to_page(phys_addr_map[i] >> PAGE_SHIFT); addr = vmap(page_map, num_pages, VM_IOREMAP, PAGE_AGP); @@ -118,36 +122,38 @@ agp_remap (unsigned long offset, unsigned long size, drm_device_t *dev) return addr; } -static inline unsigned long -drm_follow_page (void *vaddr) +static inline unsigned long drm_follow_page(void *vaddr) { - pgd_t *pgd = pgd_offset_k((unsigned long) vaddr); - pud_t *pud = pud_offset(pgd, (unsigned long) vaddr); - pmd_t *pmd = pmd_offset(pud, (unsigned long) vaddr); - pte_t *ptep = pte_offset_kernel(pmd, (unsigned long) vaddr); + pgd_t *pgd = pgd_offset_k((unsigned long)vaddr); + pud_t *pud = pud_offset(pgd, (unsigned long)vaddr); + pmd_t *pmd = pmd_offset(pud, (unsigned long)vaddr); + pte_t *ptep = pte_offset_kernel(pmd, (unsigned long)vaddr); return pte_pfn(*ptep) << PAGE_SHIFT; } -#else /* __OS_HAS_AGP */ +#else /* __OS_HAS_AGP */ -static inline drm_map_t *drm_lookup_map(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline drm_map_t *drm_lookup_map(unsigned long offset, + unsigned long size, drm_device_t * dev) { - return NULL; + return NULL; } -static inline void *agp_remap(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *agp_remap(unsigned long offset, unsigned long size, + drm_device_t * dev) { - return NULL; + return NULL; } -static inline unsigned long drm_follow_page (void *vaddr) +static inline unsigned long drm_follow_page(void *vaddr) { - return 0; + return 0; } #endif -static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_device_t *dev) +static inline void *drm_ioremap(unsigned long offset, unsigned long size, + drm_device_t * dev) { if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { drm_map_t *map = drm_lookup_map(offset, size, dev); @@ -158,8 +164,8 @@ static inline void *drm_ioremap(unsigned long offset, unsigned long size, drm_de return ioremap(offset, size); } -static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size, - drm_device_t *dev) +static inline void *drm_ioremap_nocache(unsigned long offset, + unsigned long size, drm_device_t * dev) { if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture) { drm_map_t *map = drm_lookup_map(offset, size, dev); @@ -170,7 +176,8 @@ static inline void *drm_ioremap_nocache(unsigned long offset, unsigned long size return ioremap_nocache(offset, size); } -static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *dev) +static inline void drm_ioremapfree(void *pt, unsigned long size, + drm_device_t * dev) { /* * This is a bit ugly. It would be much cleaner if the DRM API would use separate @@ -178,12 +185,12 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d * a future revision of the interface... */ if (drm_core_has_AGP(dev) && dev->agp && dev->agp->cant_use_aperture - && ((unsigned long) pt >= VMALLOC_START && (unsigned long) pt < VMALLOC_END)) - { + && ((unsigned long)pt >= VMALLOC_START + && (unsigned long)pt < VMALLOC_END)) { unsigned long offset; drm_map_t *map; - offset = drm_follow_page(pt) | ((unsigned long) pt & ~PAGE_MASK); + offset = drm_follow_page(pt) | ((unsigned long)pt & ~PAGE_MASK); map = drm_lookup_map(offset, size, dev); if (map && map->type == _DRM_AGP) { vunmap(pt); @@ -193,5 +200,3 @@ static inline void drm_ioremapfree(void *pt, unsigned long size, drm_device_t *d iounmap(pt); } - - diff --git a/drivers/char/drm/drm_memory_debug.h b/drivers/char/drm/drm_memory_debug.h index 2c82e69a7fd..4542353195b 100644 --- a/drivers/char/drm/drm_memory_debug.h +++ b/drivers/char/drm/drm_memory_debug.h @@ -1,5 +1,5 @@ /** - * \file drm_memory.h + * \file drm_memory.h * Memory management wrappers for DRM. * * \author Rickard E. (Rik) Faith @@ -35,75 +35,75 @@ #include "drmP.h" typedef struct drm_mem_stats { - const char *name; - int succeed_count; - int free_count; - int fail_count; - unsigned long bytes_allocated; - unsigned long bytes_freed; + const char *name; + int succeed_count; + int free_count; + int fail_count; + unsigned long bytes_allocated; + unsigned long bytes_freed; } drm_mem_stats_t; static DEFINE_SPINLOCK(DRM(mem_lock)); -static unsigned long DRM(ram_available) = 0; /* In pages */ -static unsigned long DRM(ram_used) = 0; -static drm_mem_stats_t DRM(mem_stats)[] = { - [DRM_MEM_DMA] = { "dmabufs" }, - [DRM_MEM_SAREA] = { "sareas" }, - [DRM_MEM_DRIVER] = { "driver" }, - [DRM_MEM_MAGIC] = { "magic" }, - [DRM_MEM_IOCTLS] = { "ioctltab" }, - [DRM_MEM_MAPS] = { "maplist" }, - [DRM_MEM_VMAS] = { "vmalist" }, - [DRM_MEM_BUFS] = { "buflist" }, - [DRM_MEM_SEGS] = { "seglist" }, - [DRM_MEM_PAGES] = { "pagelist" }, - [DRM_MEM_FILES] = { "files" }, - [DRM_MEM_QUEUES] = { "queues" }, - [DRM_MEM_CMDS] = { "commands" }, - [DRM_MEM_MAPPINGS] = { "mappings" }, - [DRM_MEM_BUFLISTS] = { "buflists" }, - [DRM_MEM_AGPLISTS] = { "agplist" }, - [DRM_MEM_SGLISTS] = { "sglist" }, - [DRM_MEM_TOTALAGP] = { "totalagp" }, - [DRM_MEM_BOUNDAGP] = { "boundagp" }, - [DRM_MEM_CTXBITMAP] = { "ctxbitmap"}, - [DRM_MEM_CTXLIST] = { "ctxlist" }, - [DRM_MEM_STUB] = { "stub" }, - { NULL, 0, } /* Last entry must be null */ +static unsigned long DRM(ram_available) = 0; /* In pages */ +static unsigned long DRM(ram_used) = 0; +static drm_mem_stats_t DRM(mem_stats)[] = +{ + [DRM_MEM_DMA] = { + "dmabufs"},[DRM_MEM_SAREA] = { + "sareas"},[DRM_MEM_DRIVER] = { + "driver"},[DRM_MEM_MAGIC] = { + "magic"},[DRM_MEM_IOCTLS] = { + "ioctltab"},[DRM_MEM_MAPS] = { + "maplist"},[DRM_MEM_VMAS] = { + "vmalist"},[DRM_MEM_BUFS] = { + "buflist"},[DRM_MEM_SEGS] = { + "seglist"},[DRM_MEM_PAGES] = { + "pagelist"},[DRM_MEM_FILES] = { + "files"},[DRM_MEM_QUEUES] = { + "queues"},[DRM_MEM_CMDS] = { + "commands"},[DRM_MEM_MAPPINGS] = { + "mappings"},[DRM_MEM_BUFLISTS] = { + "buflists"},[DRM_MEM_AGPLISTS] = { + "agplist"},[DRM_MEM_SGLISTS] = { + "sglist"},[DRM_MEM_TOTALAGP] = { + "totalagp"},[DRM_MEM_BOUNDAGP] = { + "boundagp"},[DRM_MEM_CTXBITMAP] = { + "ctxbitmap"},[DRM_MEM_CTXLIST] = { + "ctxlist"},[DRM_MEM_STUB] = { + "stub"}, { + NULL, 0,} /* Last entry must be null */ }; -void DRM(mem_init)(void) -{ +void DRM(mem_init) (void) { drm_mem_stats_t *mem; - struct sysinfo si; + struct sysinfo si; for (mem = DRM(mem_stats); mem->name; ++mem) { - mem->succeed_count = 0; - mem->free_count = 0; - mem->fail_count = 0; + mem->succeed_count = 0; + mem->free_count = 0; + mem->fail_count = 0; mem->bytes_allocated = 0; - mem->bytes_freed = 0; + mem->bytes_freed = 0; } si_meminfo(&si); DRM(ram_available) = si.totalram; - DRM(ram_used) = 0; + DRM(ram_used) = 0; } /* drm_mem_info is called whenever a process reads /dev/drm/mem. */ -static int DRM(_mem_info)(char *buf, char **start, off_t offset, - int request, int *eof, void *data) -{ +static int DRM(_mem_info) (char *buf, char **start, off_t offset, + int request, int *eof, void *data) { drm_mem_stats_t *pt; - int len = 0; + int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; return 0; } - *eof = 0; + *eof = 0; *start = &buf[offset]; DRM_PROC_PRINT(" total counts " @@ -129,24 +129,23 @@ static int DRM(_mem_info)(char *buf, char **start, off_t offset, - (long)pt->bytes_freed); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } -int DRM(mem_info)(char *buf, char **start, off_t offset, - int len, int *eof, void *data) -{ +int DRM(mem_info) (char *buf, char **start, off_t offset, + int len, int *eof, void *data) { int ret; spin_lock(&DRM(mem_lock)); - ret = DRM(_mem_info)(buf, start, offset, len, eof, data); + ret = DRM(_mem_info) (buf, start, offset, len, eof, data); spin_unlock(&DRM(mem_lock)); return ret; } -void *DRM(alloc)(size_t size, int area) -{ +void *DRM(alloc) (size_t size, int area) { void *pt; if (!size) { @@ -167,40 +166,40 @@ void *DRM(alloc)(size_t size, int area) return pt; } -void *DRM(calloc)(size_t nmemb, size_t size, int area) -{ +void *DRM(calloc) (size_t nmemb, size_t size, int area) { void *addr; - addr = DRM(alloc)(nmemb * size, area); + addr = DRM(alloc) (nmemb * size, area); if (addr != NULL) memset((void *)addr, 0, size * nmemb); return addr; } -void *DRM(realloc)(void *oldpt, size_t oldsize, size_t size, int area) -{ +void *DRM(realloc) (void *oldpt, size_t oldsize, size_t size, int area) { void *pt; - if (!(pt = DRM(alloc)(size, area))) return NULL; + if (!(pt = DRM(alloc) (size, area))) + return NULL; if (oldpt && oldsize) { memcpy(pt, oldpt, oldsize); - DRM(free)(oldpt, oldsize, area); + DRM(free) (oldpt, oldsize, area); } return pt; } -void DRM(free)(void *pt, size_t size, int area) -{ +void DRM(free) (void *pt, size_t size, int area) { int alloc_count; int free_count; - if (!pt) DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); - else kfree(pt); + if (!pt) + DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n"); + else + kfree(pt); spin_lock(&DRM(mem_lock)); DRM(mem_stats)[area].bytes_freed += size; - free_count = ++DRM(mem_stats)[area].free_count; - alloc_count = DRM(mem_stats)[area].succeed_count; + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n", @@ -208,12 +207,11 @@ void DRM(free)(void *pt, size_t size, int area) } } -unsigned long DRM(alloc_pages)(int order, int area) -{ +unsigned long DRM(alloc_pages) (int order, int area) { unsigned long address; - unsigned long bytes = PAGE_SIZE << order; + unsigned long bytes = PAGE_SIZE << order; unsigned long addr; - unsigned int sz; + unsigned int sz; spin_lock(&DRM(mem_lock)); if ((DRM(ram_used) >> PAGE_SHIFT) @@ -233,48 +231,44 @@ unsigned long DRM(alloc_pages)(int order, int area) spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[area].succeed_count; DRM(mem_stats)[area].bytes_allocated += bytes; - DRM(ram_used) += bytes; + DRM(ram_used) += bytes; spin_unlock(&DRM(mem_lock)); - - /* Zero outside the lock */ + /* Zero outside the lock */ memset((void *)address, 0, bytes); - /* Reserve */ + /* Reserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { SetPageReserved(virt_to_page(addr)); } return address; } -void DRM(free_pages)(unsigned long address, int order, int area) -{ +void DRM(free_pages) (unsigned long address, int order, int area) { unsigned long bytes = PAGE_SIZE << order; - int alloc_count; - int free_count; + int alloc_count; + int free_count; unsigned long addr; - unsigned int sz; + unsigned int sz; if (!address) { DRM_MEM_ERROR(area, "Attempt to free address 0\n"); } else { - /* Unreserve */ + /* Unreserve */ for (addr = address, sz = bytes; - sz > 0; - addr += PAGE_SIZE, sz -= PAGE_SIZE) { + sz > 0; addr += PAGE_SIZE, sz -= PAGE_SIZE) { ClearPageReserved(virt_to_page(addr)); } free_pages(address, order); } spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[area].free_count; - alloc_count = DRM(mem_stats)[area].succeed_count; + free_count = ++DRM(mem_stats)[area].free_count; + alloc_count = DRM(mem_stats)[area].succeed_count; DRM(mem_stats)[area].bytes_freed += bytes; - DRM(ram_used) -= bytes; + DRM(ram_used) -= bytes; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(area, @@ -283,8 +277,8 @@ void DRM(free_pages)(unsigned long address, int order, int area) } } -void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) -{ +void *DRM(ioremap) (unsigned long offset, unsigned long size, + drm_device_t * dev) { void *pt; if (!size) { @@ -306,8 +300,8 @@ void *DRM(ioremap)(unsigned long offset, unsigned long size, drm_device_t *dev) return pt; } -void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_t *dev) -{ +void *DRM(ioremap_nocache) (unsigned long offset, unsigned long size, + drm_device_t * dev) { void *pt; if (!size) { @@ -329,8 +323,7 @@ void *DRM(ioremap_nocache)(unsigned long offset, unsigned long size, drm_device_ return pt; } -void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) -{ +void DRM(ioremapfree) (void *pt, unsigned long size, drm_device_t * dev) { int alloc_count; int free_count; @@ -342,8 +335,8 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) spin_lock(&DRM(mem_lock)); DRM(mem_stats)[DRM_MEM_MAPPINGS].bytes_freed += size; - free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; - alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; + free_count = ++DRM(mem_stats)[DRM_MEM_MAPPINGS].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_MAPPINGS].succeed_count; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_MAPPINGS, @@ -354,8 +347,7 @@ void DRM(ioremapfree)(void *pt, unsigned long size, drm_device_t *dev) #if __OS_HAS_AGP -DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) -{ +DRM_AGP_MEM *DRM(alloc_agp) (int pages, u32 type) { DRM_AGP_MEM *handle; if (!pages) { @@ -363,11 +355,11 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) return NULL; } - if ((handle = DRM(agp_allocate_memory)(pages, type))) { + if ((handle = DRM(agp_allocate_memory) (pages, type))) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_allocated - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); return handle; } @@ -377,11 +369,10 @@ DRM_AGP_MEM *DRM(alloc_agp)(int pages, u32 type) return NULL; } -int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) -{ - int alloc_count; - int free_count; - int retval = -EINVAL; +int DRM(free_agp) (DRM_AGP_MEM * handle, int pages) { + int alloc_count; + int free_count; + int retval = -EINVAL; if (!handle) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -389,12 +380,12 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) return retval; } - if (DRM(agp_free_memory)(handle)) { + if (DRM(agp_free_memory) (handle)) { spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; - alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; + free_count = ++DRM(mem_stats)[DRM_MEM_TOTALAGP].free_count; + alloc_count = DRM(mem_stats)[DRM_MEM_TOTALAGP].succeed_count; DRM(mem_stats)[DRM_MEM_TOTALAGP].bytes_freed - += pages << PAGE_SHIFT; + += pages << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_TOTALAGP, @@ -406,8 +397,7 @@ int DRM(free_agp)(DRM_AGP_MEM *handle, int pages) return retval; } -int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) -{ +int DRM(bind_agp) (DRM_AGP_MEM * handle, unsigned int start) { int retcode = -EINVAL; if (!handle) { @@ -416,11 +406,11 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) return retcode; } - if (!(retcode = DRM(agp_bind_memory)(handle, start))) { + if (!(retcode = DRM(agp_bind_memory) (handle, start))) { spin_lock(&DRM(mem_lock)); ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_allocated - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); return retcode; } @@ -430,8 +420,7 @@ int DRM(bind_agp)(DRM_AGP_MEM *handle, unsigned int start) return retcode; } -int DRM(unbind_agp)(DRM_AGP_MEM *handle) -{ +int DRM(unbind_agp) (DRM_AGP_MEM * handle) { int alloc_count; int free_count; int retcode = -EINVAL; @@ -442,12 +431,13 @@ int DRM(unbind_agp)(DRM_AGP_MEM *handle) return retcode; } - if ((retcode = DRM(agp_unbind_memory)(handle))) return retcode; + if ((retcode = DRM(agp_unbind_memory) (handle))) + return retcode; spin_lock(&DRM(mem_lock)); - free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; + free_count = ++DRM(mem_stats)[DRM_MEM_BOUNDAGP].free_count; alloc_count = DRM(mem_stats)[DRM_MEM_BOUNDAGP].succeed_count; DRM(mem_stats)[DRM_MEM_BOUNDAGP].bytes_freed - += handle->page_count << PAGE_SHIFT; + += handle->page_count << PAGE_SHIFT; spin_unlock(&DRM(mem_lock)); if (free_count > alloc_count) { DRM_MEM_ERROR(DRM_MEM_BOUNDAGP, diff --git a/drivers/char/drm/drm_os_linux.h b/drivers/char/drm/drm_os_linux.h index b14cd370dea..d51aeb4966f 100644 --- a/drivers/char/drm/drm_os_linux.h +++ b/drivers/char/drm/drm_os_linux.h @@ -3,7 +3,6 @@ * OS abstraction macros. */ - #include /* For task queue support */ #include @@ -47,25 +46,25 @@ #else /* define some dummy types for non AGP supporting kernels */ struct no_agp_kern { - unsigned long aper_base; - unsigned long aper_size; + unsigned long aper_base; + unsigned long aper_size; }; #define DRM_AGP_MEM int #define DRM_AGP_KERN struct no_agp_kern #endif #if !(__OS_HAS_MTRR) -static __inline__ int mtrr_add (unsigned long base, unsigned long size, - unsigned int type, char increment) +static __inline__ int mtrr_add(unsigned long base, unsigned long size, + unsigned int type, char increment) { return -ENODEV; } -static __inline__ int mtrr_del (int reg, unsigned long base, - unsigned long size) +static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size) { return -ENODEV; } + #define MTRR_TYPE_WRCOMB 1 #endif @@ -99,7 +98,7 @@ static __inline__ int mtrr_del (int reg, unsigned long base, #define DRM_GET_PRIV_WITH_RETURN(_priv, _filp) _priv = _filp->private_data -/** +/** * Get the pointer to the SAREA. * * Searches the SAREA on the mapping lists and points drm_device::sarea to it. @@ -143,7 +142,5 @@ do { \ remove_wait_queue(&(queue), &entry); \ } while (0) - #define DRM_WAKEUP( queue ) wake_up_interruptible( queue ) #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue ) - diff --git a/drivers/char/drm/drm_pci.c b/drivers/char/drm/drm_pci.c index 09ed712c1a7..1fd7ff16481 100644 --- a/drivers/char/drm/drm_pci.c +++ b/drivers/char/drm/drm_pci.c @@ -77,7 +77,7 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align, dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL); if (!dmah) return NULL; - + dmah->size = size; dmah->vaddr = pci_alloc_consistent(dev->pdev, size, &dmah->busaddr); @@ -106,6 +106,7 @@ drm_dma_handle_t *drm_pci_alloc(drm_device_t * dev, size_t size, size_t align, return dmah; } + EXPORT_SYMBOL(drm_pci_alloc); /** @@ -113,8 +114,7 @@ EXPORT_SYMBOL(drm_pci_alloc); * * This function is for internal use in the Linux-specific DRM core code. */ -void -__drm_pci_free(drm_device_t * dev, drm_dma_handle_t *dmah) +void __drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah) { #ifdef DRM_DEBUG_MEMORY int area = DRM_MEM_DMA; @@ -150,12 +150,12 @@ __drm_pci_free(drm_device_t * dev, drm_dma_handle_t *dmah) /** * \brief Free a PCI consistent memory block */ -void -drm_pci_free(drm_device_t *dev, drm_dma_handle_t *dmah) +void drm_pci_free(drm_device_t * dev, drm_dma_handle_t * dmah) { __drm_pci_free(dev, dmah); kfree(dmah); } + EXPORT_SYMBOL(drm_pci_free); /*@}*/ diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h index 58b1747cd44..d66dc55e29a 100644 --- a/drivers/char/drm/drm_pciids.h +++ b/drivers/char/drm/drm_pciids.h @@ -234,4 +234,3 @@ {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ {0, 0, 0} - diff --git a/drivers/char/drm/drm_proc.c b/drivers/char/drm/drm_proc.c index 32d2bb99462..8ec2156b97a 100644 --- a/drivers/char/drm/drm_proc.c +++ b/drivers/char/drm/drm_proc.c @@ -1,5 +1,5 @@ /** - * \file drm_proc.h + * \file drm_proc.c * /proc support for DRM * * \author Rickard E. (Rik) Faith @@ -39,19 +39,19 @@ #include "drmP.h" -static int drm_name_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_vm_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_queues_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); -static int drm_bufs_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); +static int drm_name_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_vm_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_clients_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_queues_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); +static int drm_bufs_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); #if DRM_DEBUG_CODE -static int drm_vma_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data); +static int drm_vma_info(char *buf, char **start, off_t offset, + int request, int *eof, void *data); #endif /** @@ -59,18 +59,21 @@ static int drm_vma_info(char *buf, char **start, off_t offset, */ static struct drm_proc_list { const char *name; /**< file name */ - int (*f)(char *, char **, off_t, int, int *, void *); /**< proc callback*/ + int (*f) (char *, char **, off_t, int, int *, void *); /**< proc callback*/ } drm_proc_list[] = { - { "name", drm_name_info }, - { "mem", drm_mem_info }, - { "vm", drm_vm_info }, - { "clients", drm_clients_info }, - { "queues", drm_queues_info }, - { "bufs", drm_bufs_info }, + { + "name", drm_name_info}, { + "mem", drm_mem_info}, { + "vm", drm_vm_info}, { + "clients", drm_clients_info}, { + "queues", drm_queues_info}, { + "bufs", drm_bufs_info}, #if DRM_DEBUG_CODE - { "vma", drm_vma_info }, + { + "vma", drm_vma_info}, #endif }; + #define DRM_PROC_ENTRIES (sizeof(drm_proc_list)/sizeof(drm_proc_list[0])) /** @@ -81,18 +84,17 @@ static struct drm_proc_list { * \param root DRI proc dir entry. * \param dev_root resulting DRI device proc dir entry. * \return root entry pointer on success, or NULL on failure. - * + * * Create the DRI proc root entry "/proc/dri", the device proc root entry * "/proc/dri/%minor%/", and each entry in proc_list as * "/proc/dri/%minor%/%name%". */ -int drm_proc_init(drm_device_t *dev, int minor, - struct proc_dir_entry *root, - struct proc_dir_entry **dev_root) +int drm_proc_init(drm_device_t * dev, int minor, + struct proc_dir_entry *root, struct proc_dir_entry **dev_root) { struct proc_dir_entry *ent; - int i, j; - char name[64]; + int i, j; + char name[64]; sprintf(name, "%d", minor); *dev_root = create_proc_entry(name, S_IFDIR, root); @@ -103,7 +105,7 @@ int drm_proc_init(drm_device_t *dev, int minor, for (i = 0; i < DRM_PROC_ENTRIES; i++) { ent = create_proc_entry(drm_proc_list[i].name, - S_IFREG|S_IRUGO, *dev_root); + S_IFREG | S_IRUGO, *dev_root); if (!ent) { DRM_ERROR("Cannot create /proc/dri/%s/%s\n", name, drm_proc_list[i].name); @@ -114,13 +116,12 @@ int drm_proc_init(drm_device_t *dev, int minor, return -1; } ent->read_proc = drm_proc_list[i].f; - ent->data = dev; + ent->data = dev; } return 0; } - /** * Cleanup the proc filesystem resources. * @@ -132,12 +133,13 @@ int drm_proc_init(drm_device_t *dev, int minor, * Remove all proc entries created by proc_init(). */ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, - struct proc_dir_entry *dev_root) + struct proc_dir_entry *dev_root) { - int i; + int i; char name[64]; - if (!root || !dev_root) return 0; + if (!root || !dev_root) + return 0; for (i = 0; i < DRM_PROC_ENTRIES; i++) remove_proc_entry(drm_proc_list[i].name, dev_root); @@ -149,7 +151,7 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, /** * Called when "/proc/dri/.../name" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -157,14 +159,14 @@ int drm_proc_cleanup(int minor, struct proc_dir_entry *root, * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. - * + * * Prints the device name together with the bus id if available. */ static int drm_name_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -172,23 +174,26 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; if (dev->unique) { DRM_PROC_PRINT("%s %s %s\n", - dev->driver->pci_driver.name, pci_name(dev->pdev), dev->unique); + dev->driver->pci_driver.name, + pci_name(dev->pdev), dev->unique); } else { - DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name, pci_name(dev->pdev)); + DRM_PROC_PRINT("%s %s\n", dev->driver->pci_driver.name, + pci_name(dev->pdev)); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } /** * Called when "/proc/dri/.../vm" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -196,24 +201,24 @@ static int drm_name_info(char *buf, char **start, off_t offset, int request, * \param eof whether there is no more data to return. * \param data private data. * \return number of written bytes. - * + * * Prints information about all mappings in drm_device::maplist. */ static int drm__vm_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_map_t *map; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_map_t *map; drm_map_list_t *r_list; struct list_head *list; - /* Hardcoded from _DRM_FRAME_BUFFER, - _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and - _DRM_SCATTER_GATHER and _DRM_CONSISTENT */ - const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" }; - const char *type; - int i; + /* Hardcoded from _DRM_FRAME_BUFFER, + _DRM_REGISTERS, _DRM_SHM, _DRM_AGP, and + _DRM_SCATTER_GATHER and _DRM_CONSISTENT */ + const char *types[] = { "FB", "REG", "SHM", "AGP", "SG", "PCI" }; + const char *type; + int i; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -221,36 +226,35 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("slot offset size type flags " "address mtrr\n\n"); i = 0; - if (dev->maplist != NULL) list_for_each(list, &dev->maplist->head) { + if (dev->maplist != NULL) + list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if(!map) + if (!map) continue; if (map->type < 0 || map->type > 5) type = "??"; - else + else type = types[map->type]; DRM_PROC_PRINT("%4d 0x%08lx 0x%08lx %4.4s 0x%02x 0x%08x ", i, map->offset, - map->size, - type, - map->flags, - r_list->user_token); + map->size, type, map->flags, r_list->user_token); if (map->mtrr < 0) { DRM_PROC_PRINT("none\n"); } else { DRM_PROC_PRINT("%4d\n", map->mtrr); } i++; - } + } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -259,10 +263,10 @@ static int drm__vm_info(char *buf, char **start, off_t offset, int request, * Simply calls _vm_info() while holding the drm_device::struct_sem lock. */ static int drm_vm_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__vm_info(buf, start, offset, request, eof, data); @@ -272,7 +276,7 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../queues" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -282,12 +286,12 @@ static int drm_vm_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__queues_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - int i; - drm_queue_t *q; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + int i; + drm_queue_t *q; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -295,7 +299,7 @@ static int drm__queues_info(char *buf, char **start, off_t offset, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT(" ctx/flags use fin" " blk/rw/rwf wait flushed queued" @@ -313,14 +317,17 @@ static int drm__queues_info(char *buf, char **start, off_t offset, atomic_read(&q->block_count), atomic_read(&q->block_read) ? 'r' : '-', atomic_read(&q->block_write) ? 'w' : '-', - waitqueue_active(&q->read_queue) ? 'r':'-', - waitqueue_active(&q->write_queue) ? 'w':'-', - waitqueue_active(&q->flush_queue) ? 'f':'-', + waitqueue_active(&q->read_queue) ? 'r' : '-', + waitqueue_active(&q-> + write_queue) ? 'w' : '-', + waitqueue_active(&q-> + flush_queue) ? 'f' : '-', DRM_BUFCOUNT(&q->waitlist)); atomic_dec(&q->use_count); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -329,10 +336,10 @@ static int drm__queues_info(char *buf, char **start, off_t offset, * Simply calls _queues_info() while holding the drm_device::struct_sem lock. */ static int drm_queues_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__queues_info(buf, start, offset, request, eof, data); @@ -342,7 +349,7 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../bufs" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -352,12 +359,12 @@ static int drm_queues_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; drm_device_dma_t *dma = dev->dma; - int i; + int i; if (!dma || offset > DRM_PROC_LIMIT) { *eof = 1; @@ -365,7 +372,7 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT(" o size count free segs pages kB\n\n"); for (i = 0; i <= DRM_MAX_ORDER; i++) { @@ -378,19 +385,21 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, .freelist.count), dma->bufs[i].seg_count, dma->bufs[i].seg_count - *(1 << dma->bufs[i].page_order), + * (1 << dma->bufs[i].page_order), (dma->bufs[i].seg_count * (1 << dma->bufs[i].page_order)) * PAGE_SIZE / 1024); } DRM_PROC_PRINT("\n"); for (i = 0; i < dma->buf_count; i++) { - if (i && !(i%32)) DRM_PROC_PRINT("\n"); + if (i && !(i % 32)) + DRM_PROC_PRINT("\n"); DRM_PROC_PRINT(" %d", dma->buflist[i]->list); } DRM_PROC_PRINT("\n"); - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -399,10 +408,10 @@ static int drm__bufs_info(char *buf, char **start, off_t offset, int request, * Simply calls _bufs_info() while holding the drm_device::struct_sem lock. */ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__bufs_info(buf, start, offset, request, eof, data); @@ -412,7 +421,7 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, /** * Called when "/proc/dri/.../clients" is read. - * + * * \param buf output buffer. * \param start start of output data. * \param offset requested start offset. @@ -422,11 +431,11 @@ static int drm_bufs_info(char *buf, char **start, off_t offset, int request, * \return number of written bytes. */ static int drm__clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_file_t *priv; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_file_t *priv; if (offset > DRM_PROC_LIMIT) { *eof = 1; @@ -434,7 +443,7 @@ static int drm__clients_info(char *buf, char **start, off_t offset, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("a dev pid uid magic ioctls\n\n"); for (priv = dev->file_first; priv; priv = priv->next) { @@ -442,12 +451,11 @@ static int drm__clients_info(char *buf, char **start, off_t offset, priv->authenticated ? 'y' : 'n', priv->minor, priv->pid, - priv->uid, - priv->magic, - priv->ioctl_count); + priv->uid, priv->magic, priv->ioctl_count); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } @@ -456,10 +464,10 @@ static int drm__clients_info(char *buf, char **start, off_t offset, * Simply calls _clients_info() while holding the drm_device::struct_sem lock. */ static int drm_clients_info(char *buf, char **start, off_t offset, - int request, int *eof, void *data) + int request, int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__clients_info(buf, start, offset, request, eof, data); @@ -470,14 +478,14 @@ static int drm_clients_info(char *buf, char **start, off_t offset, #if DRM_DEBUG_CODE static int drm__vma_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int len = 0; - drm_vma_entry_t *pt; + drm_device_t *dev = (drm_device_t *) data; + int len = 0; + drm_vma_entry_t *pt; struct vm_area_struct *vma; #if defined(__i386__) - unsigned int pgprot; + unsigned int pgprot; #endif if (offset > DRM_PROC_LIMIT) { @@ -486,51 +494,53 @@ static int drm__vma_info(char *buf, char **start, off_t offset, int request, } *start = &buf[offset]; - *eof = 0; + *eof = 0; DRM_PROC_PRINT("vma use count: %d, high_memory = %p, 0x%08lx\n", atomic_read(&dev->vma_count), high_memory, virt_to_phys(high_memory)); for (pt = dev->vmalist; pt; pt = pt->next) { - if (!(vma = pt->vma)) continue; + if (!(vma = pt->vma)) + continue; DRM_PROC_PRINT("\n%5d 0x%08lx-0x%08lx %c%c%c%c%c%c 0x%08lx", pt->pid, vma->vm_start, vma->vm_end, - vma->vm_flags & VM_READ ? 'r' : '-', - vma->vm_flags & VM_WRITE ? 'w' : '-', - vma->vm_flags & VM_EXEC ? 'x' : '-', + vma->vm_flags & VM_READ ? 'r' : '-', + vma->vm_flags & VM_WRITE ? 'w' : '-', + vma->vm_flags & VM_EXEC ? 'x' : '-', vma->vm_flags & VM_MAYSHARE ? 's' : 'p', - vma->vm_flags & VM_LOCKED ? 'l' : '-', - vma->vm_flags & VM_IO ? 'i' : '-', + vma->vm_flags & VM_LOCKED ? 'l' : '-', + vma->vm_flags & VM_IO ? 'i' : '-', VM_OFFSET(vma)); #if defined(__i386__) pgprot = pgprot_val(vma->vm_page_prot); DRM_PROC_PRINT(" %c%c%c%c%c%c%c%c%c", - pgprot & _PAGE_PRESENT ? 'p' : '-', - pgprot & _PAGE_RW ? 'w' : 'r', - pgprot & _PAGE_USER ? 'u' : 's', - pgprot & _PAGE_PWT ? 't' : 'b', - pgprot & _PAGE_PCD ? 'u' : 'c', + pgprot & _PAGE_PRESENT ? 'p' : '-', + pgprot & _PAGE_RW ? 'w' : 'r', + pgprot & _PAGE_USER ? 'u' : 's', + pgprot & _PAGE_PWT ? 't' : 'b', + pgprot & _PAGE_PCD ? 'u' : 'c', pgprot & _PAGE_ACCESSED ? 'a' : '-', - pgprot & _PAGE_DIRTY ? 'd' : '-', - pgprot & _PAGE_PSE ? 'm' : 'k', - pgprot & _PAGE_GLOBAL ? 'g' : 'l' ); + pgprot & _PAGE_DIRTY ? 'd' : '-', + pgprot & _PAGE_PSE ? 'm' : 'k', + pgprot & _PAGE_GLOBAL ? 'g' : 'l'); #endif DRM_PROC_PRINT("\n"); } - if (len > request + offset) return request; + if (len > request + offset) + return request; *eof = 1; return len - offset; } static int drm_vma_info(char *buf, char **start, off_t offset, int request, - int *eof, void *data) + int *eof, void *data) { - drm_device_t *dev = (drm_device_t *)data; - int ret; + drm_device_t *dev = (drm_device_t *) data; + int ret; down(&dev->struct_sem); ret = drm__vma_info(buf, start, offset, request, eof, data); @@ -538,5 +548,3 @@ static int drm_vma_info(char *buf, char **start, off_t offset, int request, return ret; } #endif - - diff --git a/drivers/char/drm/drm_sarea.h b/drivers/char/drm/drm_sarea.h index de782ed2f03..e94297b751b 100644 --- a/drivers/char/drm/drm_sarea.h +++ b/drivers/char/drm/drm_sarea.h @@ -1,5 +1,5 @@ /** - * \file drm_sarea.h + * \file drm_sarea.h * \brief SAREA definitions * * \author Michel Dänzer @@ -38,7 +38,7 @@ #if defined(__alpha__) #define SAREA_MAX 0x2000 #elif defined(__ia64__) -#define SAREA_MAX 0x10000 /* 64kB */ +#define SAREA_MAX 0x10000 /* 64kB */ #else /* Intel 830M driver needs at least 8k SAREA */ #define SAREA_MAX 0x2000 @@ -51,28 +51,28 @@ /** SAREA drawable */ typedef struct drm_sarea_drawable { - unsigned int stamp; - unsigned int flags; + unsigned int stamp; + unsigned int flags; } drm_sarea_drawable_t; /** SAREA frame */ typedef struct drm_sarea_frame { - unsigned int x; - unsigned int y; - unsigned int width; - unsigned int height; - unsigned int fullscreen; + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; } drm_sarea_frame_t; /** SAREA */ typedef struct drm_sarea { /** first thing is always the DRM locking structure */ - drm_hw_lock_t lock; + drm_hw_lock_t lock; /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ - drm_hw_lock_t drawable_lock; - drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ - drm_sarea_frame_t frame; /**< frame */ - drm_context_t dummy_context; + drm_hw_lock_t drawable_lock; + drm_sarea_drawable_t drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ + drm_sarea_frame_t frame; /**< frame */ + drm_context_t dummy_context; } drm_sarea_t; -#endif /* _DRM_SAREA_H_ */ +#endif /* _DRM_SAREA_H_ */ diff --git a/drivers/char/drm/drm_scatter.c b/drivers/char/drm/drm_scatter.c index ed267d49bc6..ce81bf24820 100644 --- a/drivers/char/drm/drm_scatter.c +++ b/drivers/char/drm/drm_scatter.c @@ -1,5 +1,5 @@ /** - * \file drm_scatter.h + * \file drm_scatter.c * IOCTLs to manage scatter/gather memory * * \author Gareth Hughes @@ -37,28 +37,24 @@ #define DEBUG_SCATTER 0 -void drm_sg_cleanup( drm_sg_mem_t *entry ) +void drm_sg_cleanup(drm_sg_mem_t * entry) { struct page *page; int i; - for ( i = 0 ; i < entry->pages ; i++ ) { + for (i = 0; i < entry->pages; i++) { page = entry->pagelist[i]; - if ( page ) - ClearPageReserved( page ); + if (page) + ClearPageReserved(page); } - vfree( entry->virtual ); - - drm_free( entry->busaddr, - entry->pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + vfree(entry->virtual); + + drm_free(entry->busaddr, + entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES); + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); } #ifdef _LP64 @@ -67,8 +63,8 @@ void drm_sg_cleanup( drm_sg_mem_t *entry ) # define ScatterHandle(x) (unsigned int)(x) #endif -int drm_sg_alloc( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_sg_alloc(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -77,75 +73,70 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, drm_sg_mem_t *entry; unsigned long pages, i, j; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - if ( dev->sg ) + if (dev->sg) return -EINVAL; - if ( copy_from_user( &request, argp, sizeof(request) ) ) + if (copy_from_user(&request, argp, sizeof(request))) return -EFAULT; - entry = drm_alloc( sizeof(*entry), DRM_MEM_SGLISTS ); - if ( !entry ) + entry = drm_alloc(sizeof(*entry), DRM_MEM_SGLISTS); + if (!entry) return -ENOMEM; - memset( entry, 0, sizeof(*entry) ); + memset(entry, 0, sizeof(*entry)); pages = (request.size + PAGE_SIZE - 1) / PAGE_SIZE; - DRM_DEBUG( "sg size=%ld pages=%ld\n", request.size, pages ); + DRM_DEBUG("sg size=%ld pages=%ld\n", request.size, pages); entry->pages = pages; - entry->pagelist = drm_alloc( pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - if ( !entry->pagelist ) { - drm_free( entry, sizeof(*entry), DRM_MEM_SGLISTS ); + entry->pagelist = drm_alloc(pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + if (!entry->pagelist) { + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } memset(entry->pagelist, 0, pages * sizeof(*entry->pagelist)); - entry->busaddr = drm_alloc( pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - if ( !entry->busaddr ) { - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + entry->busaddr = drm_alloc(pages * sizeof(*entry->busaddr), + DRM_MEM_PAGES); + if (!entry->busaddr) { + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } - memset( (void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr) ); - - entry->virtual = vmalloc_32( pages << PAGE_SHIFT ); - if ( !entry->virtual ) { - drm_free( entry->busaddr, - entry->pages * sizeof(*entry->busaddr), - DRM_MEM_PAGES ); - drm_free( entry->pagelist, - entry->pages * sizeof(*entry->pagelist), - DRM_MEM_PAGES ); - drm_free( entry, - sizeof(*entry), - DRM_MEM_SGLISTS ); + memset((void *)entry->busaddr, 0, pages * sizeof(*entry->busaddr)); + + entry->virtual = vmalloc_32(pages << PAGE_SHIFT); + if (!entry->virtual) { + drm_free(entry->busaddr, + entry->pages * sizeof(*entry->busaddr), DRM_MEM_PAGES); + drm_free(entry->pagelist, + entry->pages * sizeof(*entry->pagelist), + DRM_MEM_PAGES); + drm_free(entry, sizeof(*entry), DRM_MEM_SGLISTS); return -ENOMEM; } /* This also forces the mapping of COW pages, so our page list * will be valid. Please don't remove it... */ - memset( entry->virtual, 0, pages << PAGE_SHIFT ); + memset(entry->virtual, 0, pages << PAGE_SHIFT); entry->handle = ScatterHandle((unsigned long)entry->virtual); - DRM_DEBUG( "sg alloc handle = %08lx\n", entry->handle ); - DRM_DEBUG( "sg alloc virtual = %p\n", entry->virtual ); + DRM_DEBUG("sg alloc handle = %08lx\n", entry->handle); + DRM_DEBUG("sg alloc virtual = %p\n", entry->virtual); - for (i = (unsigned long)entry->virtual, j = 0; j < pages; - i += PAGE_SIZE, j++) { + for (i = (unsigned long)entry->virtual, j = 0; j < pages; + i += PAGE_SIZE, j++) { entry->pagelist[j] = vmalloc_to_page((void *)i); if (!entry->pagelist[j]) goto failed; @@ -154,8 +145,8 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, request.handle = entry->handle; - if ( copy_to_user( argp, &request, sizeof(request) ) ) { - drm_sg_cleanup( entry ); + if (copy_to_user(argp, &request, sizeof(request))) { + drm_sg_cleanup(entry); return -EFAULT; } @@ -166,50 +157,50 @@ int drm_sg_alloc( struct inode *inode, struct file *filp, * versa. */ { - int error = 0; + int error = 0; - for ( i = 0 ; i < pages ; i++ ) { - unsigned long *tmp; + for (i = 0; i < pages; i++) { + unsigned long *tmp; - tmp = page_address( entry->pagelist[i] ); - for ( j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++ ) { - *tmp = 0xcafebabe; - } - tmp = (unsigned long *)((u8 *)entry->virtual + - (PAGE_SIZE * i)); - for( j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++ ) { - if ( *tmp != 0xcafebabe && error == 0 ) { - error = 1; - DRM_ERROR( "Scatter allocation error, " - "pagelist does not match " - "virtual mapping\n" ); + tmp = page_address(entry->pagelist[i]); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + *tmp = 0xcafebabe; + } + tmp = (unsigned long *)((u8 *) entry->virtual + + (PAGE_SIZE * i)); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + if (*tmp != 0xcafebabe && error == 0) { + error = 1; + DRM_ERROR("Scatter allocation error, " + "pagelist does not match " + "virtual mapping\n"); + } + } + tmp = page_address(entry->pagelist[i]); + for (j = 0; + j < PAGE_SIZE / sizeof(unsigned long); + j++, tmp++) { + *tmp = 0; } } - tmp = page_address( entry->pagelist[i] ); - for(j = 0 ; - j < PAGE_SIZE / sizeof(unsigned long) ; - j++, tmp++) { - *tmp = 0; - } - } - if (error == 0) - DRM_ERROR( "Scatter allocation matches pagelist\n" ); + if (error == 0) + DRM_ERROR("Scatter allocation matches pagelist\n"); } #endif return 0; - failed: - drm_sg_cleanup( entry ); + failed: + drm_sg_cleanup(entry); return -ENOMEM; } -int drm_sg_free( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +int drm_sg_free(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -219,20 +210,20 @@ int drm_sg_free( struct inode *inode, struct file *filp, if (!drm_core_check_feature(dev, DRIVER_SG)) return -EINVAL; - if ( copy_from_user( &request, - (drm_scatter_gather_t __user *)arg, - sizeof(request) ) ) + if (copy_from_user(&request, + (drm_scatter_gather_t __user *) arg, + sizeof(request))) return -EFAULT; entry = dev->sg; dev->sg = NULL; - if ( !entry || entry->handle != request.handle ) + if (!entry || entry->handle != request.handle) return -EINVAL; - DRM_DEBUG( "sg free virtual = %p\n", entry->virtual ); + DRM_DEBUG("sg free virtual = %p\n", entry->virtual); - drm_sg_cleanup( entry ); + drm_sg_cleanup(entry); return 0; } diff --git a/drivers/char/drm/drm_stub.c b/drivers/char/drm/drm_stub.c index 95a976c96eb..7cb7234d628 100644 --- a/drivers/char/drm/drm_stub.c +++ b/drivers/char/drm/drm_stub.c @@ -37,11 +37,11 @@ #include "drm_core.h" unsigned int drm_cards_limit = 16; /* Enough for one machine */ -unsigned int drm_debug = 0; /* 1 to enable debug output */ +unsigned int drm_debug = 0; /* 1 to enable debug output */ EXPORT_SYMBOL(drm_debug); -MODULE_AUTHOR( CORE_AUTHOR ); -MODULE_DESCRIPTION( CORE_DESC ); +MODULE_AUTHOR(CORE_AUTHOR); +MODULE_DESCRIPTION(CORE_DESC); MODULE_LICENSE("GPL and additional rights"); MODULE_PARM_DESC(cards_limit, "Maximum number of graphics cards"); MODULE_PARM_DESC(debug, "Enable debug output"); @@ -53,19 +53,21 @@ drm_head_t **drm_heads; struct drm_sysfs_class *drm_class; struct proc_dir_entry *drm_proc_root; -static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct pci_device_id *ent, struct drm_driver *driver) +static int drm_fill_in_dev(drm_device_t * dev, struct pci_dev *pdev, + const struct pci_device_id *ent, + struct drm_driver *driver) { int retcode; spin_lock_init(&dev->count_lock); - init_timer( &dev->timer ); - sema_init( &dev->struct_sem, 1 ); - sema_init( &dev->ctxlist_sem, 1 ); + init_timer(&dev->timer); + sema_init(&dev->struct_sem, 1); + sema_init(&dev->ctxlist_sem, 1); - dev->pdev = pdev; + dev->pdev = pdev; #ifdef __alpha__ - dev->hose = pdev->sysdata; + dev->hose = pdev->sysdata; dev->pci_domain = dev->hose->bus->number; #else dev->pci_domain = 0; @@ -82,15 +84,15 @@ static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct /* the DRM has 6 basic counters */ dev->counters = 6; - dev->types[0] = _DRM_STAT_LOCK; - dev->types[1] = _DRM_STAT_OPENS; - dev->types[2] = _DRM_STAT_CLOSES; - dev->types[3] = _DRM_STAT_IOCTLS; - dev->types[4] = _DRM_STAT_LOCKS; - dev->types[5] = _DRM_STAT_UNLOCKS; + dev->types[0] = _DRM_STAT_LOCK; + dev->types[1] = _DRM_STAT_OPENS; + dev->types[2] = _DRM_STAT_CLOSES; + dev->types[3] = _DRM_STAT_IOCTLS; + dev->types[4] = _DRM_STAT_LOCKS; + dev->types[5] = _DRM_STAT_UNLOCKS; dev->driver = driver; - + if (dev->driver->preinit) if ((retcode = dev->driver->preinit(dev, ent->driver_data))) goto error_out_unreg; @@ -98,29 +100,30 @@ static int drm_fill_in_dev(drm_device_t *dev, struct pci_dev *pdev, const struct if (drm_core_has_AGP(dev)) { if (drm_device_is_agp(dev)) dev->agp = drm_agp_init(dev); - if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) && (dev->agp == NULL)) { - DRM_ERROR( "Cannot initialize the agpgart module.\n" ); + if (drm_core_check_feature(dev, DRIVER_REQUIRE_AGP) + && (dev->agp == NULL)) { + DRM_ERROR("Cannot initialize the agpgart module.\n"); retcode = -EINVAL; goto error_out_unreg; } if (drm_core_has_MTRR(dev)) { if (dev->agp) - dev->agp->agp_mtrr = mtrr_add( dev->agp->agp_info.aper_base, - dev->agp->agp_info.aper_size*1024*1024, - MTRR_TYPE_WRCOMB, - 1 ); + dev->agp->agp_mtrr = + mtrr_add(dev->agp->agp_info.aper_base, + dev->agp->agp_info.aper_size * + 1024 * 1024, MTRR_TYPE_WRCOMB, 1); } } - retcode = drm_ctxbitmap_init( dev ); - if( retcode ) { - DRM_ERROR( "Cannot allocate memory for context bitmap.\n" ); + retcode = drm_ctxbitmap_init(dev); + if (retcode) { + DRM_ERROR("Cannot allocate memory for context bitmap.\n"); goto error_out_unreg; } return 0; - -error_out_unreg: + + error_out_unreg: drm_takedown(dev); return retcode; } @@ -140,7 +143,7 @@ int drm_stub_open(struct inode *inode, struct file *filp) int minor = iminor(inode); int err = -ENODEV; struct file_operations *old_fops; - + DRM_DEBUG("\n"); if (!((minor >= 0) && (minor < drm_cards_limit))) @@ -148,7 +151,7 @@ int drm_stub_open(struct inode *inode, struct file *filp) if (!drm_heads[minor]) return -ENODEV; - + if (!(dev = drm_heads[minor]->dev)) return -ENODEV; @@ -174,7 +177,7 @@ int drm_stub_open(struct inode *inode, struct file *filp) * create the proc init entry via proc_init(). This routines assigns * minor numbers to secondary heads of multi-headed cards */ -static int drm_get_head(drm_device_t *dev, drm_head_t *head) +static int drm_get_head(drm_device_t * dev, drm_head_t * head) { drm_head_t **heads = drm_heads; int ret; @@ -184,26 +187,27 @@ static int drm_get_head(drm_device_t *dev, drm_head_t *head) for (minor = 0; minor < drm_cards_limit; minor++, heads++) { if (!*heads) { - + *head = (drm_head_t) { - .dev = dev, - .device = MKDEV(DRM_MAJOR, minor), - .minor = minor, - }; - - if ((ret = drm_proc_init(dev, minor, drm_proc_root, &head->dev_root))) { - printk (KERN_ERR "DRM: Failed to initialize /proc/dri.\n"); + .dev = dev,.device = + MKDEV(DRM_MAJOR, minor),.minor = minor,}; + + if ((ret = + drm_proc_init(dev, minor, drm_proc_root, + &head->dev_root))) { + printk(KERN_ERR + "DRM: Failed to initialize /proc/dri.\n"); goto err_g1; } - head->dev_class = drm_sysfs_device_add(drm_class, MKDEV(DRM_MAJOR, minor), &dev->pdev->dev, "card%d", minor); if (IS_ERR(head->dev_class)) { - printk(KERN_ERR "DRM: Error sysfs_device_add.\n"); + printk(KERN_ERR + "DRM: Error sysfs_device_add.\n"); ret = PTR_ERR(head->dev_class); goto err_g2; } @@ -215,13 +219,14 @@ static int drm_get_head(drm_device_t *dev, drm_head_t *head) } DRM_ERROR("out of minors\n"); return -ENOMEM; -err_g2: + err_g2: drm_proc_cleanup(minor, drm_proc_root, head->dev_root); -err_g1: - *head = (drm_head_t) {.dev = NULL}; + err_g1: + *head = (drm_head_t) { + .dev = NULL}; return ret; } - + /** * Register. * @@ -234,7 +239,7 @@ err_g1: * Try and register, if we fail to register, backout previous work. */ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, - struct drm_driver *driver) + struct drm_driver *driver) { drm_device_t *dev; int ret; @@ -261,10 +266,11 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent, return 0; -err_g1: + err_g1: drm_free(dev, sizeof(*dev), DRM_MEM_STUB); return ret; } + EXPORT_SYMBOL(drm_get_dev); /** @@ -305,19 +311,19 @@ int drm_put_dev(drm_device_t * dev) * last minor released. * */ -int drm_put_head(drm_head_t *head) +int drm_put_head(drm_head_t * head) { int minor = head->minor; - + DRM_DEBUG("release secondary minor %d\n", minor); - + drm_proc_cleanup(minor, drm_proc_root, head->dev_root); drm_sysfs_device_remove(MKDEV(DRM_MAJOR, head->minor)); - - *head = (drm_head_t){.dev = NULL}; + + *head = (drm_head_t) { + .dev = NULL}; drm_heads[minor] = NULL; - + return 0; } - diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c index a13d07f4420..e84a7876a1b 100644 --- a/drivers/char/drm/drm_vm.c +++ b/drivers/char/drm/drm_vm.c @@ -1,7 +1,7 @@ /** - * \file drm_vm.h + * \file drm_vm.c * Memory mapping for DRM - * + * * \author Rickard E. (Rik) Faith * \author Gareth Hughes */ @@ -47,32 +47,34 @@ static void drm_vm_close(struct vm_area_struct *vma); * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Find the right map and if it's AGP memory find the real physical page to * map, get the page, increment the use count and return it. */ #if __OS_HAS_AGP static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_file_t *priv = vma->vm_file->private_data; + drm_file_t *priv = vma->vm_file->private_data; drm_device_t *dev = priv->head->dev; - drm_map_t *map = NULL; - drm_map_list_t *r_list; + drm_map_t *map = NULL; + drm_map_list_t *r_list; struct list_head *list; /* - * Find the right map - */ + * Find the right map + */ if (!drm_core_has_AGP(dev)) goto vm_nopage_error; - if(!dev->agp || !dev->agp->cant_use_aperture) goto vm_nopage_error; + if (!dev->agp || !dev->agp->cant_use_aperture) + goto vm_nopage_error; list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if (!map) continue; + if (!map) + continue; if (r_list->user_token == VM_OFFSET(vma)) break; } @@ -85,45 +87,47 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, #ifdef __alpha__ /* - * Adjust to a bus-relative address - */ + * Adjust to a bus-relative address + */ baddr -= dev->hose->mem_space->start; #endif /* - * It's AGP memory - find the real physical page to map - */ - for(agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { + * It's AGP memory - find the real physical page to map + */ + for (agpmem = dev->agp->memory; agpmem; agpmem = agpmem->next) { if (agpmem->bound <= baddr && - agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) + agpmem->bound + agpmem->pages * PAGE_SIZE > baddr) break; } - if (!agpmem) goto vm_nopage_error; + if (!agpmem) + goto vm_nopage_error; /* - * Get the page, inc the use count, and return it - */ + * Get the page, inc the use count, and return it + */ offset = (baddr - agpmem->bound) >> PAGE_SHIFT; page = virt_to_page(__va(agpmem->memory->memory[offset])); get_page(page); - DRM_DEBUG("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", - baddr, __va(agpmem->memory->memory[offset]), offset, - page_count(page)); + DRM_DEBUG + ("baddr = 0x%lx page = 0x%p, offset = 0x%lx, count=%d\n", + baddr, __va(agpmem->memory->memory[offset]), offset, + page_count(page)); return page; - } -vm_nopage_error: - return NOPAGE_SIGBUS; /* Disallow mremap */ + } + vm_nopage_error: + return NOPAGE_SIGBUS; /* Disallow mremap */ } -#else /* __OS_HAS_AGP */ +#else /* __OS_HAS_AGP */ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { return NOPAGE_SIGBUS; } -#endif /* __OS_HAS_AGP */ +#endif /* __OS_HAS_AGP */ /** * \c nopage method for shared virtual memory. @@ -131,25 +135,27 @@ static __inline__ struct page *drm_do_vm_nopage(struct vm_area_struct *vma, * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Get the the mapping, find the real physical page to map, get the page, and * return it. */ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_map_t *map = (drm_map_t *)vma->vm_private_data; - unsigned long offset; - unsigned long i; - struct page *page; + drm_map_t *map = (drm_map_t *) vma->vm_private_data; + unsigned long offset; + unsigned long i; + struct page *page; - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!map) return NOPAGE_OOM; /* Nothing allocated */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!map) + return NOPAGE_OOM; /* Nothing allocated */ - offset = address - vma->vm_start; + offset = address - vma->vm_start; i = (unsigned long)map->handle + offset; - page = (map->type == _DRM_CONSISTENT) ? - virt_to_page((void *)i) : vmalloc_to_page((void *)i); + page = (map->type == _DRM_CONSISTENT) ? + virt_to_page((void *)i) : vmalloc_to_page((void *)i); if (!page) return NOPAGE_OOM; get_page(page); @@ -158,19 +164,18 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, return page; } - /** * \c close method for shared virtual memory. - * + * * \param vma virtual memory area. - * + * * Deletes map information if we are the last * person to close a mapping and it's not in the global maplist. */ static void drm_vm_shm_close(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; drm_vma_entry_t *pt, *prev, *next; drm_map_t *map; drm_map_list_t *r_list; @@ -186,7 +191,8 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) down(&dev->struct_sem); for (pt = dev->vmalist, prev = NULL; pt; pt = next) { next = pt->next; - if (pt->vma->vm_private_data == map) found_maps++; + if (pt->vma->vm_private_data == map) + found_maps++; if (pt->vma == vma) { if (prev) { prev->next = pt->next; @@ -199,8 +205,7 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) } } /* We were the only map that was found */ - if(found_maps == 1 && - map->flags & _DRM_REMOVABLE) { + if (found_maps == 1 && map->flags & _DRM_REMOVABLE) { /* Check to see if we are in the maplist, if we are not, then * we delete this mappings information. */ @@ -208,10 +213,11 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) list = &dev->maplist->head; list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); - if (r_list->map == map) found_maps++; + if (r_list->map == map) + found_maps++; } - if(!found_maps) { + if (!found_maps) { drm_dma_handle_t dmah; switch (map->type) { @@ -251,27 +257,29 @@ static void drm_vm_shm_close(struct vm_area_struct *vma) * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Determine the page number from the page offset and get it from drm_device_dma::pagelist. */ static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->head->dev; - drm_device_dma_t *dma = dev->dma; - unsigned long offset; - unsigned long page_nr; - struct page *page; - - if (!dma) return NOPAGE_SIGBUS; /* Error */ - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!dma->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ - - offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ - page_nr = offset >> PAGE_SHIFT; - page = virt_to_page((dma->pagelist[page_nr] + - (offset & (~PAGE_MASK)))); + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; + drm_device_dma_t *dma = dev->dma; + unsigned long offset; + unsigned long page_nr; + struct page *page; + + if (!dma) + return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!dma->pagelist) + return NOPAGE_OOM; /* Nothing allocated */ + + offset = address - vma->vm_start; /* vm_[pg]off[set] should be 0 */ + page_nr = offset >> PAGE_SHIFT; + page = virt_to_page((dma->pagelist[page_nr] + (offset & (~PAGE_MASK)))); get_page(page); @@ -285,13 +293,13 @@ static __inline__ struct page *drm_do_vm_dma_nopage(struct vm_area_struct *vma, * \param vma virtual memory area. * \param address access address. * \return pointer to the page structure. - * + * * Determine the map offset from the page offset and get it from drm_sg_mem::pagelist. */ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, - unsigned long address) + unsigned long address) { - drm_map_t *map = (drm_map_t *)vma->vm_private_data; + drm_map_t *map = (drm_map_t *) vma->vm_private_data; drm_file_t *priv = vma->vm_file->private_data; drm_device_t *dev = priv->head->dev; drm_sg_mem_t *entry = dev->sg; @@ -300,10 +308,12 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, unsigned long page_offset; struct page *page; - if (!entry) return NOPAGE_SIGBUS; /* Error */ - if (address > vma->vm_end) return NOPAGE_SIGBUS; /* Disallow mremap */ - if (!entry->pagelist) return NOPAGE_OOM ; /* Nothing allocated */ - + if (!entry) + return NOPAGE_SIGBUS; /* Error */ + if (address > vma->vm_end) + return NOPAGE_SIGBUS; /* Disallow mremap */ + if (!entry->pagelist) + return NOPAGE_OOM; /* Nothing allocated */ offset = address - vma->vm_start; map_offset = map->offset - (unsigned long)dev->sg->virtual; @@ -314,76 +324,78 @@ static __inline__ struct page *drm_do_vm_sg_nopage(struct vm_area_struct *vma, return page; } - static struct page *drm_vm_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_nopage(vma, address); } static struct page *drm_vm_shm_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_shm_nopage(vma, address); } static struct page *drm_vm_dma_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_dma_nopage(vma, address); } static struct page *drm_vm_sg_nopage(struct vm_area_struct *vma, - unsigned long address, - int *type) { - if (type) *type = VM_FAULT_MINOR; + unsigned long address, int *type) +{ + if (type) + *type = VM_FAULT_MINOR; return drm_do_vm_sg_nopage(vma, address); } /** AGP virtual memory operations */ -static struct vm_operations_struct drm_vm_ops = { +static struct vm_operations_struct drm_vm_ops = { .nopage = drm_vm_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; /** Shared virtual memory operations */ -static struct vm_operations_struct drm_vm_shm_ops = { +static struct vm_operations_struct drm_vm_shm_ops = { .nopage = drm_vm_shm_nopage, - .open = drm_vm_open, - .close = drm_vm_shm_close, + .open = drm_vm_open, + .close = drm_vm_shm_close, }; /** DMA virtual memory operations */ -static struct vm_operations_struct drm_vm_dma_ops = { +static struct vm_operations_struct drm_vm_dma_ops = { .nopage = drm_vm_dma_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; /** Scatter-gather virtual memory operations */ -static struct vm_operations_struct drm_vm_sg_ops = { +static struct vm_operations_struct drm_vm_sg_ops = { .nopage = drm_vm_sg_nopage, - .open = drm_vm_open, - .close = drm_vm_close, + .open = drm_vm_open, + .close = drm_vm_close, }; - /** * \c open method for shared virtual memory. - * + * * \param vma virtual memory area. - * + * * Create a new drm_vma_entry structure as the \p vma private data entry and * add it to drm_device::vmalist. */ static void drm_vm_open(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; drm_vma_entry_t *vma_entry; DRM_DEBUG("0x%08lx,0x%08lx\n", @@ -393,26 +405,26 @@ static void drm_vm_open(struct vm_area_struct *vma) vma_entry = drm_alloc(sizeof(*vma_entry), DRM_MEM_VMAS); if (vma_entry) { down(&dev->struct_sem); - vma_entry->vma = vma; + vma_entry->vma = vma; vma_entry->next = dev->vmalist; - vma_entry->pid = current->pid; - dev->vmalist = vma_entry; + vma_entry->pid = current->pid; + dev->vmalist = vma_entry; up(&dev->struct_sem); } } /** * \c close method for all virtual memory types. - * + * * \param vma virtual memory area. - * + * * Search the \p vma private data entry in drm_device::vmalist, unlink it, and * free it. */ static void drm_vm_close(struct vm_area_struct *vma) { - drm_file_t *priv = vma->vm_file->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = vma->vm_file->private_data; + drm_device_t *dev = priv->head->dev; drm_vma_entry_t *pt, *prev; DRM_DEBUG("0x%08lx,0x%08lx\n", @@ -440,43 +452,44 @@ static void drm_vm_close(struct vm_area_struct *vma) * \param filp file pointer. * \param vma virtual memory area. * \return zero on success or a negative number on failure. - * + * * Sets the virtual memory area operations structure to vm_dma_ops, the file * pointer, and calls vm_open(). */ static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; drm_device_dma_t *dma; - unsigned long length = vma->vm_end - vma->vm_start; + unsigned long length = vma->vm_end - vma->vm_start; lock_kernel(); - dev = priv->head->dev; - dma = dev->dma; + dev = priv->head->dev; + dma = dev->dma; DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", vma->vm_start, vma->vm_end, VM_OFFSET(vma)); - /* Length must match exact page count */ + /* Length must match exact page count */ if (!dma || (length >> PAGE_SHIFT) != dma->page_count) { unlock_kernel(); return -EINVAL; } unlock_kernel(); - vma->vm_ops = &drm_vm_dma_ops; + vma->vm_ops = &drm_vm_dma_ops; - vma->vm_flags |= VM_RESERVED; /* Don't swap */ + vma->vm_flags |= VM_RESERVED; /* Don't swap */ - vma->vm_file = filp; /* Needed for drm_vm_open() */ + vma->vm_file = filp; /* Needed for drm_vm_open() */ drm_vm_open(vma); return 0; } -unsigned long drm_core_get_map_ofs(drm_map_t *map) +unsigned long drm_core_get_map_ofs(drm_map_t * map) { return map->offset; } + EXPORT_SYMBOL(drm_core_get_map_ofs); unsigned long drm_core_get_reg_ofs(struct drm_device *dev) @@ -487,6 +500,7 @@ unsigned long drm_core_get_reg_ofs(struct drm_device *dev) return 0; #endif } + EXPORT_SYMBOL(drm_core_get_reg_ofs); /** @@ -495,7 +509,7 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs); * \param filp file pointer. * \param vma virtual memory area. * \return zero on success or a negative number on failure. - * + * * If the virtual memory area has no offset associated with it then it's a DMA * area, so calls mmap_dma(). Otherwise searches the map in drm_device::maplist, * checks that the restricted flag is not set, sets the virtual memory operations @@ -504,17 +518,18 @@ EXPORT_SYMBOL(drm_core_get_reg_ofs); */ int drm_mmap(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_map_t *map = NULL; - drm_map_list_t *r_list; - unsigned long offset = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_map_t *map = NULL; + drm_map_list_t *r_list; + unsigned long offset = 0; struct list_head *list; DRM_DEBUG("start = 0x%lx, end = 0x%lx, offset = 0x%lx\n", vma->vm_start, vma->vm_end, VM_OFFSET(vma)); - if ( !priv->authenticated ) return -EACCES; + if (!priv->authenticated) + return -EACCES; /* We check for "dma". On Apple's UniNorth, it's valid to have * the AGP mapped at physical address 0 @@ -522,61 +537,66 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) */ if (!VM_OFFSET(vma) #if __OS_HAS_AGP - && (!dev->agp || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) + && (!dev->agp + || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) #endif ) return drm_mmap_dma(filp, vma); - /* A sequential search of a linked list is - fine here because: 1) there will only be - about 5-10 entries in the list and, 2) a - DRI client only has to do this mapping - once, so it doesn't have to be optimized - for performance, even if the list was a - bit longer. */ + /* A sequential search of a linked list is + fine here because: 1) there will only be + about 5-10 entries in the list and, 2) a + DRI client only has to do this mapping + once, so it doesn't have to be optimized + for performance, even if the list was a + bit longer. */ list_for_each(list, &dev->maplist->head) { r_list = list_entry(list, drm_map_list_t, head); map = r_list->map; - if (!map) continue; + if (!map) + continue; if (r_list->user_token == VM_OFFSET(vma)) break; } - if (!map || ((map->flags&_DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) + if (!map || ((map->flags & _DRM_RESTRICTED) && !capable(CAP_SYS_ADMIN))) return -EPERM; - /* Check for valid size. */ - if (map->size != vma->vm_end - vma->vm_start) return -EINVAL; + /* Check for valid size. */ + if (map->size != vma->vm_end - vma->vm_start) + return -EINVAL; if (!capable(CAP_SYS_ADMIN) && (map->flags & _DRM_READ_ONLY)) { vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE); #if defined(__i386__) || defined(__x86_64__) pgprot_val(vma->vm_page_prot) &= ~_PAGE_RW; #else - /* Ye gads this is ugly. With more thought - we could move this up higher and use - `protection_map' instead. */ - vma->vm_page_prot = __pgprot(pte_val(pte_wrprotect( - __pte(pgprot_val(vma->vm_page_prot))))); + /* Ye gads this is ugly. With more thought + we could move this up higher and use + `protection_map' instead. */ + vma->vm_page_prot = + __pgprot(pte_val + (pte_wrprotect + (__pte(pgprot_val(vma->vm_page_prot))))); #endif } switch (map->type) { - case _DRM_AGP: - if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { - /* - * On some platforms we can't talk to bus dma address from the CPU, so for - * memory of type DRM_AGP, we'll deal with sorting out the real physical - * pages and mappings in nopage() - */ + case _DRM_AGP: + if (drm_core_has_AGP(dev) && dev->agp->cant_use_aperture) { + /* + * On some platforms we can't talk to bus dma address from the CPU, so for + * memory of type DRM_AGP, we'll deal with sorting out the real physical + * pages and mappings in nopage() + */ #if defined(__powerpc__) - pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; + pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE; #endif - vma->vm_ops = &drm_vm_ops; - break; - } - /* fall through to _DRM_FRAME_BUFFER... */ + vma->vm_ops = &drm_vm_ops; + break; + } + /* fall through to _DRM_FRAME_BUFFER... */ case _DRM_FRAME_BUFFER: case _DRM_REGISTERS: #if defined(__i386__) || defined(__x86_64__) @@ -591,27 +611,25 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) #endif vma->vm_flags |= VM_IO; /* not in core dump */ #if defined(__ia64__) - if (efi_range_is_wc(vma->vm_start, vma->vm_end - - vma->vm_start)) + if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start)) vma->vm_page_prot = - pgprot_writecombine(vma->vm_page_prot); + pgprot_writecombine(vma->vm_page_prot); else - vma->vm_page_prot = - pgprot_noncached(vma->vm_page_prot); + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); #endif offset = dev->driver->get_reg_ofs(dev); #ifdef __sparc__ if (io_remap_pfn_range(DRM_RPR_ARG(vma) vma->vm_start, - (map->offset + offset) >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) + (map->offset + offset) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) #else if (io_remap_pfn_range(vma, vma->vm_start, - (map->offset + offset) >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) + (map->offset + offset) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, + vma->vm_page_prot)) #endif - return -EAGAIN; + return -EAGAIN; DRM_DEBUG(" Type = %d; start = 0x%lx, end = 0x%lx," " offset = 0x%lx\n", map->type, @@ -624,22 +642,23 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) * allocate in a different way */ vma->vm_ops = &drm_vm_shm_ops; vma->vm_private_data = (void *)map; - /* Don't let this area swap. Change when - DRM_KERNEL advisory is supported. */ + /* Don't let this area swap. Change when + DRM_KERNEL advisory is supported. */ vma->vm_flags |= VM_RESERVED; break; case _DRM_SCATTER_GATHER: vma->vm_ops = &drm_vm_sg_ops; vma->vm_private_data = (void *)map; vma->vm_flags |= VM_RESERVED; - break; + break; default: return -EINVAL; /* This should never happen. */ } - vma->vm_flags |= VM_RESERVED; /* Don't swap */ + vma->vm_flags |= VM_RESERVED; /* Don't swap */ - vma->vm_file = filp; /* Needed for drm_vm_open() */ + vma->vm_file = filp; /* Needed for drm_vm_open() */ drm_vm_open(vma); return 0; } + EXPORT_SYMBOL(drm_mmap); diff --git a/drivers/char/drm/ffb_context.c b/drivers/char/drm/ffb_context.c index f5181207801..8a6cc2751bc 100644 --- a/drivers/char/drm/ffb_context.c +++ b/drivers/char/drm/ffb_context.c @@ -15,8 +15,7 @@ #include "ffb_drv.h" -static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) -{ +static int DRM(alloc_queue) (drm_device_t * dev, int is_2d_only) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int i; @@ -37,7 +36,7 @@ static int DRM(alloc_queue)(drm_device_t *dev, int is_2d_only) return i + 1; } -static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) +static void ffb_save_context(ffb_dev_priv_t * fpriv, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; @@ -94,36 +93,36 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) /* Capture rendering attributes. */ - ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ - ctx->wid = upa_readl(&ffb->wid); /* Current WID */ - ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ - ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ - ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ - ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ - ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ - ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ + ctx->ppc = upa_readl(&ffb->ppc); /* Pixel Processor Control */ + ctx->wid = upa_readl(&ffb->wid); /* Current WID */ + ctx->fg = upa_readl(&ffb->fg); /* Constant FG color */ + ctx->bg = upa_readl(&ffb->bg); /* Constant BG color */ + ctx->consty = upa_readl(&ffb->consty); /* Constant Y */ + ctx->constz = upa_readl(&ffb->constz); /* Constant Z */ + ctx->xclip = upa_readl(&ffb->xclip); /* X plane clip */ + ctx->dcss = upa_readl(&ffb->dcss); /* Depth Cue Scale Slope */ ctx->vclipmin = upa_readl(&ffb->vclipmin); /* Primary XY clip, minimum */ ctx->vclipmax = upa_readl(&ffb->vclipmax); /* Primary XY clip, maximum */ ctx->vclipzmin = upa_readl(&ffb->vclipzmin); /* Primary Z clip, minimum */ ctx->vclipzmax = upa_readl(&ffb->vclipzmax); /* Primary Z clip, maximum */ - ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ - ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ - ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ - ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ - ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ + ctx->dcsf = upa_readl(&ffb->dcsf); /* Depth Cue Scale Front Bound */ + ctx->dcsb = upa_readl(&ffb->dcsb); /* Depth Cue Scale Back Bound */ + ctx->dczf = upa_readl(&ffb->dczf); /* Depth Cue Scale Z Front */ + ctx->dczb = upa_readl(&ffb->dczb); /* Depth Cue Scale Z Back */ + ctx->blendc = upa_readl(&ffb->blendc); /* Alpha Blend Control */ ctx->blendc1 = upa_readl(&ffb->blendc1); /* Alpha Blend Color 1 */ ctx->blendc2 = upa_readl(&ffb->blendc2); /* Alpha Blend Color 2 */ - ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ - ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ - ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ + ctx->fbc = upa_readl(&ffb->fbc); /* Frame Buffer Control */ + ctx->rop = upa_readl(&ffb->rop); /* Raster Operation */ + ctx->cmp = upa_readl(&ffb->cmp); /* Compare Controls */ ctx->matchab = upa_readl(&ffb->matchab); /* Buffer A/B Match Ops */ - ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ - ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ - ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ - ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ - ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ - ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ - ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ + ctx->matchc = upa_readl(&ffb->matchc); /* Buffer C Match Ops */ + ctx->magnab = upa_readl(&ffb->magnab); /* Buffer A/B Magnitude Ops */ + ctx->magnc = upa_readl(&ffb->magnc); /* Buffer C Magnitude Ops */ + ctx->pmask = upa_readl(&ffb->pmask); /* RGB Plane Mask */ + ctx->xpmask = upa_readl(&ffb->xpmask); /* X Plane Mask */ + ctx->ypmask = upa_readl(&ffb->ypmask); /* Y Plane Mask */ + ctx->zpmask = upa_readl(&ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ ctx->auxclip0min = upa_readl(&ffb->auxclip[0].min); @@ -135,9 +134,9 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->auxclip3min = upa_readl(&ffb->auxclip[3].min); ctx->auxclip3max = upa_readl(&ffb->auxclip[3].max); - ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ - ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ - ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ + ctx->lpat = upa_readl(&ffb->lpat); /* Line Pattern */ + ctx->fontxy = upa_readl(&ffb->fontxy); /* XY Font Coordinate */ + ctx->fontw = upa_readl(&ffb->fontw); /* Font Width */ ctx->fontinc = upa_readl(&ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ @@ -145,12 +144,12 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->dcss1 = upa_readl(&ffb->dcss1); /* Depth Cue Scale Slope 1 */ ctx->dcss2 = upa_readl(&ffb->dcss2); /* Depth Cue Scale Slope 2 */ ctx->dcss2 = upa_readl(&ffb->dcss3); /* Depth Cue Scale Slope 3 */ - ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ - ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ - ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ - ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ - ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ - ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ + ctx->dcs2 = upa_readl(&ffb->dcs2); /* Depth Cue Scale 2 */ + ctx->dcs3 = upa_readl(&ffb->dcs3); /* Depth Cue Scale 3 */ + ctx->dcs4 = upa_readl(&ffb->dcs4); /* Depth Cue Scale 4 */ + ctx->dcd2 = upa_readl(&ffb->dcd2); /* Depth Cue Depth 2 */ + ctx->dcd3 = upa_readl(&ffb->dcd3); /* Depth Cue Depth 3 */ + ctx->dcd4 = upa_readl(&ffb->dcd4); /* Depth Cue Depth 4 */ /* And stencil/stencilctl only exists on FFB2+ and later * due to the introduction of 3DRAM-III. @@ -170,7 +169,7 @@ static void ffb_save_context(ffb_dev_priv_t *fpriv, int idx) ctx->ucsr = upa_readl(&ffb->ucsr); } -static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) +static void ffb_restore_context(ffb_dev_priv_t * fpriv, int old, int idx) { ffb_fbcPtr ffb = fpriv->regs; struct ffb_hw_context *ctx; @@ -193,7 +192,7 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) upa_writel(ctx->ppc, &ffb->ppc); upa_writel(ctx->wid, &ffb->wid); - upa_writel(ctx->fg, &ffb->fg); + upa_writel(ctx->fg, &ffb->fg); upa_writel(ctx->bg, &ffb->bg); upa_writel(ctx->xclip, &ffb->xclip); upa_writel(ctx->fbc, &ffb->fbc); @@ -237,36 +236,36 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) /* Restore rendering attributes. */ - upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ - upa_writel(ctx->wid, &ffb->wid); /* Current WID */ - upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ - upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ - upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ - upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ - upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ - upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ + upa_writel(ctx->ppc, &ffb->ppc); /* Pixel Processor Control */ + upa_writel(ctx->wid, &ffb->wid); /* Current WID */ + upa_writel(ctx->fg, &ffb->fg); /* Constant FG color */ + upa_writel(ctx->bg, &ffb->bg); /* Constant BG color */ + upa_writel(ctx->consty, &ffb->consty); /* Constant Y */ + upa_writel(ctx->constz, &ffb->constz); /* Constant Z */ + upa_writel(ctx->xclip, &ffb->xclip); /* X plane clip */ + upa_writel(ctx->dcss, &ffb->dcss); /* Depth Cue Scale Slope */ upa_writel(ctx->vclipmin, &ffb->vclipmin); /* Primary XY clip, minimum */ upa_writel(ctx->vclipmax, &ffb->vclipmax); /* Primary XY clip, maximum */ upa_writel(ctx->vclipzmin, &ffb->vclipzmin); /* Primary Z clip, minimum */ upa_writel(ctx->vclipzmax, &ffb->vclipzmax); /* Primary Z clip, maximum */ - upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ - upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ - upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ - upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ - upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ + upa_writel(ctx->dcsf, &ffb->dcsf); /* Depth Cue Scale Front Bound */ + upa_writel(ctx->dcsb, &ffb->dcsb); /* Depth Cue Scale Back Bound */ + upa_writel(ctx->dczf, &ffb->dczf); /* Depth Cue Scale Z Front */ + upa_writel(ctx->dczb, &ffb->dczb); /* Depth Cue Scale Z Back */ + upa_writel(ctx->blendc, &ffb->blendc); /* Alpha Blend Control */ upa_writel(ctx->blendc1, &ffb->blendc1); /* Alpha Blend Color 1 */ upa_writel(ctx->blendc2, &ffb->blendc2); /* Alpha Blend Color 2 */ - upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ - upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ - upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ + upa_writel(ctx->fbc, &ffb->fbc); /* Frame Buffer Control */ + upa_writel(ctx->rop, &ffb->rop); /* Raster Operation */ + upa_writel(ctx->cmp, &ffb->cmp); /* Compare Controls */ upa_writel(ctx->matchab, &ffb->matchab); /* Buffer A/B Match Ops */ - upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ - upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ - upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ - upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ - upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ - upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ - upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ + upa_writel(ctx->matchc, &ffb->matchc); /* Buffer C Match Ops */ + upa_writel(ctx->magnab, &ffb->magnab); /* Buffer A/B Magnitude Ops */ + upa_writel(ctx->magnc, &ffb->magnc); /* Buffer C Magnitude Ops */ + upa_writel(ctx->pmask, &ffb->pmask); /* RGB Plane Mask */ + upa_writel(ctx->xpmask, &ffb->xpmask); /* X Plane Mask */ + upa_writel(ctx->ypmask, &ffb->ypmask); /* Y Plane Mask */ + upa_writel(ctx->zpmask, &ffb->zpmask); /* Z Plane Mask */ /* Auxiliary Clips. */ upa_writel(ctx->auxclip0min, &ffb->auxclip[0].min); @@ -278,9 +277,9 @@ static void ffb_restore_context(ffb_dev_priv_t *fpriv, int old, int idx) upa_writel(ctx->auxclip3min, &ffb->auxclip[3].min); upa_writel(ctx->auxclip3max, &ffb->auxclip[3].max); - upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ - upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ - upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ + upa_writel(ctx->lpat, &ffb->lpat); /* Line Pattern */ + upa_writel(ctx->fontxy, &ffb->fontxy); /* XY Font Coordinate */ + upa_writel(ctx->fontw, &ffb->fontw); /* Font Width */ upa_writel(ctx->fontinc, &ffb->fontinc); /* Font X/Y Increment */ /* These registers/features only exist on FFB2 and later chips. */ @@ -354,91 +353,87 @@ static void FFBWait(ffb_fbcPtr ffb) } while (--limit); } -int ffb_driver_context_switch(drm_device_t *dev, int old, int new) +int ffb_driver_context_switch(drm_device_t * dev, int old, int new) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; #ifdef DRM_DMA_HISTOGRAM - dev->ctx_start = get_cycles(); + dev->ctx_start = get_cycles(); #endif - - DRM_DEBUG("Context switch from %d to %d\n", old, new); - if (new == dev->last_context || - dev->last_context == 0) { + DRM_DEBUG("Context switch from %d to %d\n", old, new); + + if (new == dev->last_context || dev->last_context == 0) { dev->last_context = new; - return 0; + return 0; } - + FFBWait(fpriv->regs); ffb_save_context(fpriv, old); ffb_restore_context(fpriv, old, new); FFBWait(fpriv->regs); - + dev->last_context = new; - return 0; + return 0; } int ffb_driver_resctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_ctx_res_t res; - drm_ctx_t ctx; - int i; + drm_ctx_res_t res; + drm_ctx_t ctx; + int i; DRM_DEBUG("%d\n", DRM_RESERVED_CONTEXTS); - if (copy_from_user(&res, (drm_ctx_res_t __user *)arg, sizeof(res))) + if (copy_from_user(&res, (drm_ctx_res_t __user *) arg, sizeof(res))) return -EFAULT; if (res.count >= DRM_RESERVED_CONTEXTS) { memset(&ctx, 0, sizeof(ctx)); for (i = 0; i < DRM_RESERVED_CONTEXTS; i++) { ctx.handle = i; - if (copy_to_user(&res.contexts[i], - &i, - sizeof(i))) + if (copy_to_user(&res.contexts[i], &i, sizeof(i))) return -EFAULT; } } res.count = DRM_RESERVED_CONTEXTS; - if (copy_to_user((drm_ctx_res_t __user *)arg, &res, sizeof(res))) + if (copy_to_user((drm_ctx_res_t __user *) arg, &res, sizeof(res))) return -EFAULT; return 0; } - int ffb_driver_addctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; - idx = DRM(alloc_queue)(dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); + idx = DRM(alloc_queue) (dev, (ctx.flags & _DRM_CONTEXT_2DONLY)); if (idx < 0) return -ENFILE; DRM_DEBUG("%d\n", ctx.handle); ctx.handle = idx; - if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; @@ -458,16 +453,16 @@ int ffb_driver_modctx(struct inode *inode, struct file *filp, unsigned int cmd, } int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; struct ffb_hw_context *hwctx; drm_ctx_t ctx; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; idx = ctx.handle; @@ -483,31 +478,31 @@ int ffb_driver_getctx(struct inode *inode, struct file *filp, unsigned int cmd, else ctx.flags = 0; - if (copy_to_user((drm_ctx_t __user *)arg, &ctx, sizeof(ctx))) + if (copy_to_user((drm_ctx_t __user *) arg, &ctx, sizeof(ctx))) return -EFAULT; return 0; } -int ffb_driver_switchctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) +int ffb_driver_switchctx(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + drm_ctx_t ctx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); return ffb_driver_context_switch(dev, dev->last_context, ctx.handle); } int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_ctx_t ctx; + drm_ctx_t ctx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); @@ -515,15 +510,15 @@ int ffb_driver_newctx(struct inode *inode, struct file *filp, unsigned int cmd, } int ffb_driver_rmctx(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_ctx_t ctx; - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->dev; - ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; + drm_ctx_t ctx; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->dev; + ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int idx; - if (copy_from_user(&ctx, (drm_ctx_t __user *)arg, sizeof(ctx))) + if (copy_from_user(&ctx, (drm_ctx_t __user *) arg, sizeof(ctx))) return -EFAULT; DRM_DEBUG("%d\n", ctx.handle); @@ -544,7 +539,8 @@ void ffb_set_context_ioctls(void) DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RM_CTX)].func = ffb_driver_rmctx; DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_MOD_CTX)].func = ffb_driver_modctx; DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_GET_CTX)].func = ffb_driver_getctx; - DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func = ffb_driver_switchctx; + DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_SWITCH_CTX)].func = + ffb_driver_switchctx; DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_NEW_CTX)].func = ffb_driver_newctx; DRM(ioctls)[DRM_IOCTL_NR(DRM_IOCTL_RES_CTX)].func = ffb_driver_resctx; diff --git a/drivers/char/drm/ffb_drv.c b/drivers/char/drm/ffb_drv.c index 1bd0d55ee0f..5c121d6df9f 100644 --- a/drivers/char/drm/ffb_drv.c +++ b/drivers/char/drm/ffb_drv.c @@ -33,13 +33,13 @@ typedef struct _ffb_position_t { static ffb_position_t *ffb_position; -static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) +static void get_ffb_type(ffb_dev_priv_t * ffb_priv, int instance) { volatile unsigned char *strap_bits; unsigned char val; strap_bits = (volatile unsigned char *) - (ffb_priv->card_phys_base + 0x00200000UL); + (ffb_priv->card_phys_base + 0x00200000UL); /* Don't ask, you have to read the value twice for whatever * reason to get correct contents. @@ -61,7 +61,8 @@ static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) break; case (0x1 << 5) | (0x0 << 3): ffb_priv->ffb_type = ffb2_prototype; - printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", instance); + printk("ffb%d: Detected FFB2/vertical pre-FCS prototype\n", + instance); break; case (0x1 << 5) | (0x1 << 3): ffb_priv->ffb_type = ffb2_vertical; @@ -81,12 +82,13 @@ static void get_ffb_type(ffb_dev_priv_t *ffb_priv, int instance) break; default: ffb_priv->ffb_type = ffb2_vertical; - printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", instance, val); + printk("ffb%d: Unknown boardID[%08x], assuming FFB2\n", + instance, val); break; }; } -static void ffb_apply_upa_parent_ranges(int parent, +static void ffb_apply_upa_parent_ranges(int parent, struct linux_prom64_registers *regs) { struct linux_prom64_ranges ranges[PROMREG_MAX]; @@ -97,7 +99,8 @@ static void ffb_apply_upa_parent_ranges(int parent, if (strcmp(name, "upa") != 0) return; - len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); + len = + prom_getproperty(parent, "ranges", (void *)ranges, sizeof(ranges)); if (len <= 0) return; @@ -117,11 +120,11 @@ static void ffb_apply_upa_parent_ranges(int parent, return; } -static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node, +static int ffb_init_one(drm_device_t * dev, int prom_node, int parent_node, int instance) { - struct linux_prom64_registers regs[2*PROMREG_MAX]; - ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; + struct linux_prom64_registers regs[2 * PROMREG_MAX]; + ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private; int i; ffb_priv->prom_node = prom_node; @@ -132,27 +135,27 @@ static int ffb_init_one(drm_device_t *dev, int prom_node, int parent_node, ffb_apply_upa_parent_ranges(parent_node, ®s[0]); ffb_priv->card_phys_base = regs[0].phys_addr; ffb_priv->regs = (ffb_fbcPtr) - (regs[0].phys_addr + 0x00600000UL); + (regs[0].phys_addr + 0x00600000UL); get_ffb_type(ffb_priv, instance); for (i = 0; i < FFB_MAX_CTXS; i++) ffb_priv->hw_state[i] = NULL; - + return 0; } static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; - drm_map_list_t *r_list; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_map_list_t *r_list; struct list_head *list; - drm_map_t *map; + drm_map_t *map; if (!priv || (dev = priv->dev) == NULL) return NULL; list_for_each(list, &dev->maplist->head) { - r_list = (drm_map_list_t *)list; + r_list = (drm_map_list_t *) list; map = r_list->map; if (!map) continue; @@ -166,8 +169,7 @@ static drm_map_t *ffb_find_map(struct file *filp, unsigned long off) unsigned long ffb_get_unmapped_area(struct file *filp, unsigned long hint, unsigned long len, - unsigned long pgoff, - unsigned long flags) + unsigned long pgoff, unsigned long flags) { drm_map_t *map = ffb_find_map(filp, pgoff << PAGE_SHIFT); unsigned long addr = -ENOMEM; @@ -175,8 +177,7 @@ unsigned long ffb_get_unmapped_area(struct file *filp, if (!map) return get_unmapped_area(NULL, hint, len, pgoff, flags); - if (map->type == _DRM_FRAME_BUFFER || - map->type == _DRM_REGISTERS) { + if (map->type == _DRM_FRAME_BUFFER || map->type == _DRM_REGISTERS) { #ifdef HAVE_ARCH_FB_UNMAPPED_AREA addr = get_fb_unmapped_area(filp, hint, len, pgoff, flags); #else @@ -187,7 +188,7 @@ unsigned long ffb_get_unmapped_area(struct file *filp, addr = get_unmapped_area(NULL, hint, len + slack, pgoff, flags); if (!(addr & ~PAGE_MASK)) { - unsigned long kvirt = (unsigned long) map->handle; + unsigned long kvirt = (unsigned long)map->handle; if ((kvirt & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) { unsigned long koff, aoff; @@ -207,9 +208,9 @@ unsigned long ffb_get_unmapped_area(struct file *filp, return addr; } -static int ffb_presetup(drm_device_t *dev) +static int ffb_presetup(drm_device_t * dev) { - ffb_dev_priv_t *ffb_priv; + ffb_dev_priv_t *ffb_priv; int ret = 0; int i = 0; @@ -224,14 +225,11 @@ static int ffb_presetup(drm_device_t *dev) memset(ffb_priv, 0, sizeof(*ffb_priv)); dev->dev_private = ffb_priv; - ret = ffb_init_one(dev, - ffb_position[i].node, - ffb_position[i].root, - i); + ret = ffb_init_one(dev, ffb_position[i].node, ffb_position[i].root, i); return ret; } -static void ffb_driver_release(drm_device_t *dev, struct file *filp) +static void ffb_driver_release(drm_device_t * dev, struct file *filp) { ffb_dev_priv_t *fpriv = (ffb_dev_priv_t *) dev->dev_private; int context = _DRM_LOCKING_CONTEXT(dev->lock.hw_lock->lock); @@ -239,84 +237,82 @@ static void ffb_driver_release(drm_device_t *dev, struct file *filp) idx = context - 1; if (fpriv && - context != DRM_KERNEL_CONTEXT && - fpriv->hw_state[idx] != NULL) { + context != DRM_KERNEL_CONTEXT && fpriv->hw_state[idx] != NULL) { kfree(fpriv->hw_state[idx]); fpriv->hw_state[idx] = NULL; - } + } } -static void ffb_driver_pretakedown(drm_device_t *dev) +static void ffb_driver_pretakedown(drm_device_t * dev) { - if (dev->dev_private) kfree(dev->dev_private); + if (dev->dev_private) + kfree(dev->dev_private); } -static int ffb_driver_postcleanup(drm_device_t *dev) +static int ffb_driver_postcleanup(drm_device_t * dev) { - if (ffb_position != NULL) kfree(ffb_position); + if (ffb_position != NULL) + kfree(ffb_position); return 0; } -static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev, drm_lock_t *lock) +static void ffb_driver_kernel_context_switch_unlock(struct drm_device *dev, + drm_lock_t * lock) { dev->lock.filp = 0; { __volatile__ unsigned int *plock = &dev->lock.hw_lock->lock; unsigned int old, new, prev, ctx; - + ctx = lock->context; do { - old = *plock; - new = ctx; + old = *plock; + new = ctx; prev = cmpxchg(plock, old, new); } while (prev != old); } wake_up_interruptible(&dev->lock.lock_queue); } -static unsigned long ffb_driver_get_map_ofs(drm_map_t *map) +static unsigned long ffb_driver_get_map_ofs(drm_map_t * map) { return (map->offset & 0xffffffff); } -static unsigned long ffb_driver_get_reg_ofs(drm_device_t *dev) +static unsigned long ffb_driver_get_reg_ofs(drm_device_t * dev) { - ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *)dev->dev_private; - - if (ffb_priv) - return ffb_priv->card_phys_base; - - return 0; + ffb_dev_priv_t *ffb_priv = (ffb_dev_priv_t *) dev->dev_private; + + if (ffb_priv) + return ffb_priv->card_phys_base; + + return 0; } -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->minor - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, DRIVER_PATCHLEVEL, DRIVER_DATE, dev->minor); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } static drm_ioctl_desc_t ioctls[] = { - + }; static struct drm_driver driver = { @@ -335,14 +331,15 @@ static struct drm_driver driver = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + } + , }; static int __init ffb_init(void) @@ -357,6 +354,6 @@ static void __exit ffb_exit(void) module_init(ffb_init); module_exit(ffb_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/ffb_drv.h b/drivers/char/drm/ffb_drv.h index 8bf7f1e143f..582afa6dd2b 100644 --- a/drivers/char/drm/ffb_drv.h +++ b/drivers/char/drm/ffb_drv.h @@ -5,7 +5,7 @@ */ /* Auxilliary clips. */ -typedef struct { +typedef struct { volatile unsigned int min; volatile unsigned int max; } ffb_auxclip, *ffb_auxclipPtr; @@ -15,172 +15,265 @@ typedef struct _ffb_fbc { /* Next vertex registers, on the right we list which drawops * use said register and the logical name the register has in * that context. - */ /* DESCRIPTION DRAWOP(NAME) */ -/*0x00*/unsigned int pad1[3]; /* Reserved */ -/*0x0c*/volatile unsigned int alpha; /* ALPHA Transparency */ -/*0x10*/volatile unsigned int red; /* RED */ -/*0x14*/volatile unsigned int green; /* GREEN */ -/*0x18*/volatile unsigned int blue; /* BLUE */ -/*0x1c*/volatile unsigned int z; /* DEPTH */ -/*0x20*/volatile unsigned int y; /* Y triangle(DOYF) */ - /* aadot(DYF) */ - /* ddline(DYF) */ - /* aaline(DYF) */ -/*0x24*/volatile unsigned int x; /* X triangle(DOXF) */ - /* aadot(DXF) */ - /* ddline(DXF) */ - /* aaline(DXF) */ -/*0x28*/unsigned int pad2[2]; /* Reserved */ -/*0x30*/volatile unsigned int ryf; /* Y (alias to DOYF) ddline(RYF) */ - /* aaline(RYF) */ - /* triangle(RYF) */ -/*0x34*/volatile unsigned int rxf; /* X ddline(RXF) */ - /* aaline(RXF) */ - /* triangle(RXF) */ -/*0x38*/unsigned int pad3[2]; /* Reserved */ -/*0x40*/volatile unsigned int dmyf; /* Y (alias to DOYF) triangle(DMYF) */ -/*0x44*/volatile unsigned int dmxf; /* X triangle(DMXF) */ -/*0x48*/unsigned int pad4[2]; /* Reserved */ -/*0x50*/volatile unsigned int ebyi; /* Y (alias to RYI) polygon(EBYI) */ -/*0x54*/volatile unsigned int ebxi; /* X polygon(EBXI) */ -/*0x58*/unsigned int pad5[2]; /* Reserved */ -/*0x60*/volatile unsigned int by; /* Y brline(RYI) */ - /* fastfill(OP) */ - /* polygon(YI) */ - /* rectangle(YI) */ - /* bcopy(SRCY) */ - /* vscroll(SRCY) */ -/*0x64*/volatile unsigned int bx; /* X brline(RXI) */ - /* polygon(XI) */ - /* rectangle(XI) */ - /* bcopy(SRCX) */ - /* vscroll(SRCX) */ - /* fastfill(GO) */ -/*0x68*/volatile unsigned int dy; /* destination Y fastfill(DSTY) */ - /* bcopy(DSRY) */ - /* vscroll(DSRY) */ -/*0x6c*/volatile unsigned int dx; /* destination X fastfill(DSTX) */ - /* bcopy(DSTX) */ - /* vscroll(DSTX) */ -/*0x70*/volatile unsigned int bh; /* Y (alias to RYI) brline(DYI) */ - /* dot(DYI) */ - /* polygon(ETYI) */ - /* Height fastfill(H) */ - /* bcopy(H) */ - /* vscroll(H) */ - /* Y count fastfill(NY) */ -/*0x74*/volatile unsigned int bw; /* X dot(DXI) */ - /* brline(DXI) */ - /* polygon(ETXI) */ - /* fastfill(W) */ - /* bcopy(W) */ - /* vscroll(W) */ - /* fastfill(NX) */ -/*0x78*/unsigned int pad6[2]; /* Reserved */ -/*0x80*/unsigned int pad7[32]; /* Reserved */ - + *//* DESCRIPTION DRAWOP(NAME) */ + /*0x00*/ unsigned int pad1[3]; + /* Reserved */ + /*0x0c*/ volatile unsigned int alpha; + /* ALPHA Transparency */ + /*0x10*/ volatile unsigned int red; + /* RED */ + /*0x14*/ volatile unsigned int green; + /* GREEN */ + /*0x18*/ volatile unsigned int blue; + /* BLUE */ + /*0x1c*/ volatile unsigned int z; + /* DEPTH */ + /*0x20*/ volatile unsigned int y; + /* Y triangle(DOYF) */ + /* aadot(DYF) */ + /* ddline(DYF) */ + /* aaline(DYF) */ + /*0x24*/ volatile unsigned int x; + /* X triangle(DOXF) */ + /* aadot(DXF) */ + /* ddline(DXF) */ + /* aaline(DXF) */ + /*0x28*/ unsigned int pad2[2]; + /* Reserved */ + /*0x30*/ volatile unsigned int ryf; + /* Y (alias to DOYF) ddline(RYF) */ + /* aaline(RYF) */ + /* triangle(RYF) */ + /*0x34*/ volatile unsigned int rxf; + /* X ddline(RXF) */ + /* aaline(RXF) */ + /* triangle(RXF) */ + /*0x38*/ unsigned int pad3[2]; + /* Reserved */ + /*0x40*/ volatile unsigned int dmyf; + /* Y (alias to DOYF) triangle(DMYF) */ + /*0x44*/ volatile unsigned int dmxf; + /* X triangle(DMXF) */ + /*0x48*/ unsigned int pad4[2]; + /* Reserved */ + /*0x50*/ volatile unsigned int ebyi; + /* Y (alias to RYI) polygon(EBYI) */ + /*0x54*/ volatile unsigned int ebxi; + /* X polygon(EBXI) */ + /*0x58*/ unsigned int pad5[2]; + /* Reserved */ + /*0x60*/ volatile unsigned int by; + /* Y brline(RYI) */ + /* fastfill(OP) */ + /* polygon(YI) */ + /* rectangle(YI) */ + /* bcopy(SRCY) */ + /* vscroll(SRCY) */ + /*0x64*/ volatile unsigned int bx; + /* X brline(RXI) */ + /* polygon(XI) */ + /* rectangle(XI) */ + /* bcopy(SRCX) */ + /* vscroll(SRCX) */ + /* fastfill(GO) */ + /*0x68*/ volatile unsigned int dy; + /* destination Y fastfill(DSTY) */ + /* bcopy(DSRY) */ + /* vscroll(DSRY) */ + /*0x6c*/ volatile unsigned int dx; + /* destination X fastfill(DSTX) */ + /* bcopy(DSTX) */ + /* vscroll(DSTX) */ + /*0x70*/ volatile unsigned int bh; + /* Y (alias to RYI) brline(DYI) */ + /* dot(DYI) */ + /* polygon(ETYI) */ + /* Height fastfill(H) */ + /* bcopy(H) */ + /* vscroll(H) */ + /* Y count fastfill(NY) */ + /*0x74*/ volatile unsigned int bw; + /* X dot(DXI) */ + /* brline(DXI) */ + /* polygon(ETXI) */ + /* fastfill(W) */ + /* bcopy(W) */ + /* vscroll(W) */ + /* fastfill(NX) */ + /*0x78*/ unsigned int pad6[2]; + /* Reserved */ + /*0x80*/ unsigned int pad7[32]; + /* Reserved */ + /* Setup Unit's vertex state register */ -/*100*/ volatile unsigned int suvtx; -/*104*/ unsigned int pad8[63]; /* Reserved */ - +/*100*/ volatile unsigned int suvtx; + /*104*/ unsigned int pad8[63]; + /* Reserved */ + /* Frame Buffer Control Registers */ -/*200*/ volatile unsigned int ppc; /* Pixel Processor Control */ -/*204*/ volatile unsigned int wid; /* Current WID */ -/*208*/ volatile unsigned int fg; /* FG data */ -/*20c*/ volatile unsigned int bg; /* BG data */ -/*210*/ volatile unsigned int consty; /* Constant Y */ -/*214*/ volatile unsigned int constz; /* Constant Z */ -/*218*/ volatile unsigned int xclip; /* X Clip */ -/*21c*/ volatile unsigned int dcss; /* Depth Cue Scale Slope */ -/*220*/ volatile unsigned int vclipmin; /* Viewclip XY Min Bounds */ -/*224*/ volatile unsigned int vclipmax; /* Viewclip XY Max Bounds */ -/*228*/ volatile unsigned int vclipzmin; /* Viewclip Z Min Bounds */ -/*22c*/ volatile unsigned int vclipzmax; /* Viewclip Z Max Bounds */ -/*230*/ volatile unsigned int dcsf; /* Depth Cue Scale Front Bound */ -/*234*/ volatile unsigned int dcsb; /* Depth Cue Scale Back Bound */ -/*238*/ volatile unsigned int dczf; /* Depth Cue Z Front */ -/*23c*/ volatile unsigned int dczb; /* Depth Cue Z Back */ -/*240*/ unsigned int pad9; /* Reserved */ -/*244*/ volatile unsigned int blendc; /* Alpha Blend Control */ -/*248*/ volatile unsigned int blendc1; /* Alpha Blend Color 1 */ -/*24c*/ volatile unsigned int blendc2; /* Alpha Blend Color 2 */ -/*250*/ volatile unsigned int fbramitc; /* FB RAM Interleave Test Control */ -/*254*/ volatile unsigned int fbc; /* Frame Buffer Control */ -/*258*/ volatile unsigned int rop; /* Raster OPeration */ -/*25c*/ volatile unsigned int cmp; /* Frame Buffer Compare */ -/*260*/ volatile unsigned int matchab; /* Buffer AB Match Mask */ -/*264*/ volatile unsigned int matchc; /* Buffer C(YZ) Match Mask */ -/*268*/ volatile unsigned int magnab; /* Buffer AB Magnitude Mask */ -/*26c*/ volatile unsigned int magnc; /* Buffer C(YZ) Magnitude Mask */ -/*270*/ volatile unsigned int fbcfg0; /* Frame Buffer Config 0 */ -/*274*/ volatile unsigned int fbcfg1; /* Frame Buffer Config 1 */ -/*278*/ volatile unsigned int fbcfg2; /* Frame Buffer Config 2 */ -/*27c*/ volatile unsigned int fbcfg3; /* Frame Buffer Config 3 */ -/*280*/ volatile unsigned int ppcfg; /* Pixel Processor Config */ -/*284*/ volatile unsigned int pick; /* Picking Control */ -/*288*/ volatile unsigned int fillmode; /* FillMode */ -/*28c*/ volatile unsigned int fbramwac; /* FB RAM Write Address Control */ -/*290*/ volatile unsigned int pmask; /* RGB PlaneMask */ -/*294*/ volatile unsigned int xpmask; /* X PlaneMask */ -/*298*/ volatile unsigned int ypmask; /* Y PlaneMask */ -/*29c*/ volatile unsigned int zpmask; /* Z PlaneMask */ -/*2a0*/ ffb_auxclip auxclip[4]; /* Auxilliary Viewport Clip */ - + /*200*/ volatile unsigned int ppc; + /* Pixel Processor Control */ + /*204*/ volatile unsigned int wid; + /* Current WID */ + /*208*/ volatile unsigned int fg; + /* FG data */ + /*20c*/ volatile unsigned int bg; + /* BG data */ + /*210*/ volatile unsigned int consty; + /* Constant Y */ + /*214*/ volatile unsigned int constz; + /* Constant Z */ + /*218*/ volatile unsigned int xclip; + /* X Clip */ + /*21c*/ volatile unsigned int dcss; + /* Depth Cue Scale Slope */ + /*220*/ volatile unsigned int vclipmin; + /* Viewclip XY Min Bounds */ + /*224*/ volatile unsigned int vclipmax; + /* Viewclip XY Max Bounds */ + /*228*/ volatile unsigned int vclipzmin; + /* Viewclip Z Min Bounds */ + /*22c*/ volatile unsigned int vclipzmax; + /* Viewclip Z Max Bounds */ + /*230*/ volatile unsigned int dcsf; + /* Depth Cue Scale Front Bound */ + /*234*/ volatile unsigned int dcsb; + /* Depth Cue Scale Back Bound */ + /*238*/ volatile unsigned int dczf; + /* Depth Cue Z Front */ + /*23c*/ volatile unsigned int dczb; + /* Depth Cue Z Back */ + /*240*/ unsigned int pad9; + /* Reserved */ + /*244*/ volatile unsigned int blendc; + /* Alpha Blend Control */ + /*248*/ volatile unsigned int blendc1; + /* Alpha Blend Color 1 */ + /*24c*/ volatile unsigned int blendc2; + /* Alpha Blend Color 2 */ + /*250*/ volatile unsigned int fbramitc; + /* FB RAM Interleave Test Control */ + /*254*/ volatile unsigned int fbc; + /* Frame Buffer Control */ + /*258*/ volatile unsigned int rop; + /* Raster OPeration */ + /*25c*/ volatile unsigned int cmp; + /* Frame Buffer Compare */ + /*260*/ volatile unsigned int matchab; + /* Buffer AB Match Mask */ + /*264*/ volatile unsigned int matchc; + /* Buffer C(YZ) Match Mask */ + /*268*/ volatile unsigned int magnab; + /* Buffer AB Magnitude Mask */ + /*26c*/ volatile unsigned int magnc; + /* Buffer C(YZ) Magnitude Mask */ + /*270*/ volatile unsigned int fbcfg0; + /* Frame Buffer Config 0 */ + /*274*/ volatile unsigned int fbcfg1; + /* Frame Buffer Config 1 */ + /*278*/ volatile unsigned int fbcfg2; + /* Frame Buffer Config 2 */ + /*27c*/ volatile unsigned int fbcfg3; + /* Frame Buffer Config 3 */ + /*280*/ volatile unsigned int ppcfg; + /* Pixel Processor Config */ + /*284*/ volatile unsigned int pick; + /* Picking Control */ + /*288*/ volatile unsigned int fillmode; + /* FillMode */ + /*28c*/ volatile unsigned int fbramwac; + /* FB RAM Write Address Control */ + /*290*/ volatile unsigned int pmask; + /* RGB PlaneMask */ + /*294*/ volatile unsigned int xpmask; + /* X PlaneMask */ + /*298*/ volatile unsigned int ypmask; + /* Y PlaneMask */ + /*29c*/ volatile unsigned int zpmask; + /* Z PlaneMask */ + /*2a0*/ ffb_auxclip auxclip[4]; + /* Auxilliary Viewport Clip */ + /* New 3dRAM III support regs */ -/*2c0*/ volatile unsigned int rawblend2; -/*2c4*/ volatile unsigned int rawpreblend; -/*2c8*/ volatile unsigned int rawstencil; -/*2cc*/ volatile unsigned int rawstencilctl; -/*2d0*/ volatile unsigned int threedram1; -/*2d4*/ volatile unsigned int threedram2; -/*2d8*/ volatile unsigned int passin; -/*2dc*/ volatile unsigned int rawclrdepth; -/*2e0*/ volatile unsigned int rawpmask; -/*2e4*/ volatile unsigned int rawcsrc; -/*2e8*/ volatile unsigned int rawmatch; -/*2ec*/ volatile unsigned int rawmagn; -/*2f0*/ volatile unsigned int rawropblend; -/*2f4*/ volatile unsigned int rawcmp; -/*2f8*/ volatile unsigned int rawwac; -/*2fc*/ volatile unsigned int fbramid; - -/*300*/ volatile unsigned int drawop; /* Draw OPeration */ -/*304*/ unsigned int pad10[2]; /* Reserved */ -/*30c*/ volatile unsigned int lpat; /* Line Pattern control */ -/*310*/ unsigned int pad11; /* Reserved */ -/*314*/ volatile unsigned int fontxy; /* XY Font coordinate */ -/*318*/ volatile unsigned int fontw; /* Font Width */ -/*31c*/ volatile unsigned int fontinc; /* Font Increment */ -/*320*/ volatile unsigned int font; /* Font bits */ -/*324*/ unsigned int pad12[3]; /* Reserved */ -/*330*/ volatile unsigned int blend2; -/*334*/ volatile unsigned int preblend; -/*338*/ volatile unsigned int stencil; -/*33c*/ volatile unsigned int stencilctl; +/*2c0*/ volatile unsigned int rawblend2; +/*2c4*/ volatile unsigned int rawpreblend; +/*2c8*/ volatile unsigned int rawstencil; +/*2cc*/ volatile unsigned int rawstencilctl; +/*2d0*/ volatile unsigned int threedram1; +/*2d4*/ volatile unsigned int threedram2; +/*2d8*/ volatile unsigned int passin; +/*2dc*/ volatile unsigned int rawclrdepth; +/*2e0*/ volatile unsigned int rawpmask; +/*2e4*/ volatile unsigned int rawcsrc; +/*2e8*/ volatile unsigned int rawmatch; +/*2ec*/ volatile unsigned int rawmagn; +/*2f0*/ volatile unsigned int rawropblend; +/*2f4*/ volatile unsigned int rawcmp; +/*2f8*/ volatile unsigned int rawwac; +/*2fc*/ volatile unsigned int fbramid; + + /*300*/ volatile unsigned int drawop; + /* Draw OPeration */ + /*304*/ unsigned int pad10[2]; + /* Reserved */ + /*30c*/ volatile unsigned int lpat; + /* Line Pattern control */ + /*310*/ unsigned int pad11; + /* Reserved */ + /*314*/ volatile unsigned int fontxy; + /* XY Font coordinate */ + /*318*/ volatile unsigned int fontw; + /* Font Width */ + /*31c*/ volatile unsigned int fontinc; + /* Font Increment */ + /*320*/ volatile unsigned int font; + /* Font bits */ + /*324*/ unsigned int pad12[3]; + /* Reserved */ +/*330*/ volatile unsigned int blend2; +/*334*/ volatile unsigned int preblend; +/*338*/ volatile unsigned int stencil; +/*33c*/ volatile unsigned int stencilctl; -/*340*/ unsigned int pad13[4]; /* Reserved */ -/*350*/ volatile unsigned int dcss1; /* Depth Cue Scale Slope 1 */ -/*354*/ volatile unsigned int dcss2; /* Depth Cue Scale Slope 2 */ -/*358*/ volatile unsigned int dcss3; /* Depth Cue Scale Slope 3 */ -/*35c*/ volatile unsigned int widpmask; -/*360*/ volatile unsigned int dcs2; -/*364*/ volatile unsigned int dcs3; -/*368*/ volatile unsigned int dcs4; -/*36c*/ unsigned int pad14; /* Reserved */ -/*370*/ volatile unsigned int dcd2; -/*374*/ volatile unsigned int dcd3; -/*378*/ volatile unsigned int dcd4; -/*37c*/ unsigned int pad15; /* Reserved */ -/*380*/ volatile unsigned int pattern[32]; /* area Pattern */ -/*400*/ unsigned int pad16[8]; /* Reserved */ -/*420*/ volatile unsigned int reset; /* chip RESET */ -/*424*/ unsigned int pad17[247]; /* Reserved */ -/*800*/ volatile unsigned int devid; /* Device ID */ -/*804*/ unsigned int pad18[63]; /* Reserved */ -/*900*/ volatile unsigned int ucsr; /* User Control & Status Register */ -/*904*/ unsigned int pad19[31]; /* Reserved */ -/*980*/ volatile unsigned int mer; /* Mode Enable Register */ -/*984*/ unsigned int pad20[1439]; /* Reserved */ + /*340*/ unsigned int pad13[4]; + /* Reserved */ + /*350*/ volatile unsigned int dcss1; + /* Depth Cue Scale Slope 1 */ + /*354*/ volatile unsigned int dcss2; + /* Depth Cue Scale Slope 2 */ + /*358*/ volatile unsigned int dcss3; + /* Depth Cue Scale Slope 3 */ +/*35c*/ volatile unsigned int widpmask; +/*360*/ volatile unsigned int dcs2; +/*364*/ volatile unsigned int dcs3; +/*368*/ volatile unsigned int dcs4; + /*36c*/ unsigned int pad14; + /* Reserved */ +/*370*/ volatile unsigned int dcd2; +/*374*/ volatile unsigned int dcd3; +/*378*/ volatile unsigned int dcd4; + /*37c*/ unsigned int pad15; + /* Reserved */ + /*380*/ volatile unsigned int pattern[32]; + /* area Pattern */ + /*400*/ unsigned int pad16[8]; + /* Reserved */ + /*420*/ volatile unsigned int reset; + /* chip RESET */ + /*424*/ unsigned int pad17[247]; + /* Reserved */ + /*800*/ volatile unsigned int devid; + /* Device ID */ + /*804*/ unsigned int pad18[63]; + /* Reserved */ + /*900*/ volatile unsigned int ucsr; + /* User Control & Status Register */ + /*904*/ unsigned int pad19[31]; + /* Reserved */ + /*980*/ volatile unsigned int mer; + /* Mode Enable Register */ + /*984*/ unsigned int pad20[1439]; + /* Reserved */ } ffb_fbc, *ffb_fbcPtr; struct ffb_hw_context { @@ -263,16 +356,16 @@ enum ffb_chip_type { typedef struct ffb_dev_priv { /* Misc software state. */ - int prom_node; - enum ffb_chip_type ffb_type; - u64 card_phys_base; - struct miscdevice miscdev; + int prom_node; + enum ffb_chip_type ffb_type; + u64 card_phys_base; + struct miscdevice miscdev; /* Controller registers. */ - ffb_fbcPtr regs; + ffb_fbcPtr regs; /* Context table. */ - struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; + struct ffb_hw_context *hw_state[FFB_MAX_CTXS]; } ffb_dev_priv_t; extern unsigned long ffb_get_unmapped_area(struct file *filp, @@ -283,4 +376,4 @@ extern unsigned long ffb_get_unmapped_area(struct file *filp, extern void ffb_set_context_ioctls(void); extern drm_ioctl_desc_t DRM(ioctls)[]; -extern int ffb_driver_context_switch(drm_device_t *dev, int old, int new); +extern int ffb_driver_context_switch(drm_device_t * dev, int old, int new); diff --git a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c index 2f1659b96fd..810625093c0 100644 --- a/drivers/char/drm/i810_dma.c +++ b/drivers/char/drm/i810_dma.c @@ -45,102 +45,101 @@ #define I810_BUF_UNMAPPED 0 #define I810_BUF_MAPPED 1 -static drm_buf_t *i810_freelist_get(drm_device_t *dev) +static drm_buf_t *i810_freelist_get(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i; - int used; + drm_device_dma_t *dma = dev->dma; + int i; + int used; /* Linear search might not be the best solution */ - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, + used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, I810_BUF_CLIENT); if (used == I810_BUF_FREE) { return buf; } } - return NULL; + return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ -static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf) +static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf) { - drm_i810_buf_priv_t *buf_priv = buf->dev_private; - int used; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; + int used; - /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); if (used != I810_BUF_CLIENT) { - DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); - return -EINVAL; + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; } - return 0; + return 0; } static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; - drm_i810_private_t *dev_priv; - drm_buf_t *buf; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i810_private_t *dev_priv; + drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; lock_kernel(); - dev = priv->head->dev; + dev = priv->head->dev; dev_priv = dev->dev_private; - buf = dev_priv->mmap_buffer; + buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; - buf_priv->currently_mapped = I810_BUF_MAPPED; + buf_priv->currently_mapped = I810_BUF_MAPPED; unlock_kernel(); if (io_remap_pfn_range(vma, vma->vm_start, - VM_OFFSET(vma) >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) return -EAGAIN; + VM_OFFSET(vma) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; return 0; } static struct file_operations i810_buffer_fops = { - .open = drm_open, - .flush = drm_flush, + .open = drm_open, + .flush = drm_flush, .release = drm_release, - .ioctl = drm_ioctl, - .mmap = i810_mmap_buffers, - .fasync = drm_fasync, + .ioctl = drm_ioctl, + .mmap = i810_mmap_buffers, + .fasync = drm_fasync, }; -static int i810_map_buffer(drm_buf_t *buf, struct file *filp) +static int i810_map_buffer(drm_buf_t * buf, struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - drm_i810_private_t *dev_priv = dev->dev_private; - struct file_operations *old_fops; + drm_i810_private_t *dev_priv = dev->dev_private; + struct file_operations *old_fops; int retcode = 0; - if (buf_priv->currently_mapped == I810_BUF_MAPPED) + if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); old_fops = filp->f_op; filp->f_op = &i810_buffer_fops; dev_priv->mmap_buffer = buf; buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, - PROT_READ|PROT_WRITE, - MAP_SHARED, - buf->bus_address); + PROT_READ | PROT_WRITE, + MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; filp->f_op = old_fops; if ((unsigned long)buf_priv->virtual > -1024UL) { @@ -149,12 +148,12 @@ static int i810_map_buffer(drm_buf_t *buf, struct file *filp) retcode = (signed int)buf_priv->virtual; buf_priv->virtual = NULL; } - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); return retcode; } -static int i810_unmap_buffer(drm_buf_t *buf) +static int i810_unmap_buffer(drm_buf_t * buf) { drm_i810_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; @@ -168,43 +167,43 @@ static int i810_unmap_buffer(drm_buf_t *buf) (size_t) buf->total); up_write(¤t->mm->mmap_sem); - buf_priv->currently_mapped = I810_BUF_UNMAPPED; - buf_priv->virtual = NULL; + buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->virtual = NULL; return retcode; } -static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d, +static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d, struct file *filp) { - drm_buf_t *buf; + drm_buf_t *buf; drm_i810_buf_priv_t *buf_priv; int retcode = 0; buf = i810_freelist_get(dev); if (!buf) { retcode = -ENOMEM; - DRM_DEBUG("retcode=%d\n", retcode); + DRM_DEBUG("retcode=%d\n", retcode); return retcode; } retcode = i810_map_buffer(buf, filp); if (retcode) { i810_freelist_put(dev, buf); - DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->filp = filp; buf_priv = buf->dev_private; d->granted = 1; - d->request_idx = buf->idx; - d->request_size = buf->total; - d->virtual = buf_priv->virtual; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; return retcode; } -static int i810_dma_cleanup(drm_device_t *dev) +static int i810_dma_cleanup(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; @@ -217,165 +216,167 @@ static int i810_dma_cleanup(drm_device_t *dev) if (dev->dev_private) { int i; - drm_i810_private_t *dev_priv = - (drm_i810_private_t *) dev->dev_private; + drm_i810_private_t *dev_priv = + (drm_i810_private_t *) dev->dev_private; if (dev_priv->ring.virtual_start) { - drm_ioremapfree((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size, dev); + drm_ioremapfree((void *)dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); } - if (dev_priv->hw_status_page) { - pci_free_consistent(dev->pdev, PAGE_SIZE, + if (dev_priv->hw_status_page) { + pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); - /* Need to rewrite hardware status page */ - I810_WRITE(0x02080, 0x1ffff000); + /* Need to rewrite hardware status page */ + I810_WRITE(0x02080, 0x1ffff000); } - drm_free(dev->dev_private, sizeof(drm_i810_private_t), + drm_free(dev->dev_private, sizeof(drm_i810_private_t), DRM_MEM_DRIVER); - dev->dev_private = NULL; + dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; + drm_buf_t *buf = dma->buflist[i]; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - if ( buf_priv->kernel_virtual && buf->total ) - drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + if (buf_priv->kernel_virtual && buf->total) + drm_ioremapfree(buf_priv->kernel_virtual, + buf->total, dev); } } - return 0; + return 0; } -static int i810_wait_ring(drm_device_t *dev, int n) +static int i810_wait_ring(drm_device_t * dev, int n) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_ring_buffer_t *ring = &(dev_priv->ring); - int iters = 0; - unsigned long end; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - end = jiffies + (HZ*3); - while (ring->space < n) { - ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; - + end = jiffies + (HZ * 3); + while (ring->space < n) { + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + if (ring->head != last_head) { - end = jiffies + (HZ*3); + end = jiffies + (HZ * 3); last_head = ring->head; } - - iters++; + + iters++; if (time_before(end, jiffies)) { - DRM_ERROR("space: %d wanted %d\n", ring->space, n); - DRM_ERROR("lockup\n"); - goto out_wait_ring; + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; } udelay(1); } -out_wait_ring: - return iters; + out_wait_ring: + return iters; } -static void i810_kernel_lost_context(drm_device_t *dev) +static void i810_kernel_lost_context(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_ring_buffer_t *ring = &(dev_priv->ring); + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_ring_buffer_t *ring = &(dev_priv->ring); - ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->tail = I810_READ(LP_RING + RING_TAIL); - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; + ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I810_READ(LP_RING + RING_TAIL); + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; } -static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv) +static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv) { - drm_device_dma_t *dma = dev->dma; - int my_idx = 24; - u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); - int i; + drm_device_dma_t *dma = dev->dma; + int my_idx = 24; + u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); + int i; if (dma->buf_count > 1019) { - /* Not enough space in the status page for the freelist */ - return -EINVAL; + /* Not enough space in the status page for the freelist */ + return -EINVAL; } - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->in_use = hw_status++; - buf_priv->my_use_idx = my_idx; - my_idx += 4; + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; - *buf_priv->in_use = I810_BUF_FREE; + *buf_priv->in_use = I810_BUF_FREE; buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, - buf->total, dev); + buf->total, dev); } return 0; } -static int i810_dma_initialize(drm_device_t *dev, - drm_i810_private_t *dev_priv, - drm_i810_init_t *init) +static int i810_dma_initialize(drm_device_t * dev, + drm_i810_private_t * dev_priv, + drm_i810_init_t * init) { struct list_head *list; - memset(dev_priv, 0, sizeof(drm_i810_private_t)); + memset(dev_priv, 0, sizeof(drm_i810_private_t)); list_for_each(list, &dev->maplist->head) { drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); if (r_list->map && r_list->map->type == _DRM_SHM && - r_list->map->flags & _DRM_CONTAINS_LOCK ) { + r_list->map->flags & _DRM_CONTAINS_LOCK) { dev_priv->sarea_map = r_list->map; - break; - } - } + break; + } + } if (!dev_priv->sarea_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find sarea!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find sarea!\n"); + return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); if (!dev_priv->mmio_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find mmio map!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find mmio map!\n"); + return -EINVAL; } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not find dma buffer map!\n"); - return -EINVAL; + i810_dma_cleanup(dev); + DRM_ERROR("can not find dma buffer map!\n"); + return -EINVAL; } dev_priv->sarea_priv = (drm_i810_sarea_t *) - ((u8 *)dev_priv->sarea_map->handle + - init->sarea_priv_offset); + ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); - dev_priv->ring.Start = init->ring_start; - dev_priv->ring.End = init->ring_end; - dev_priv->ring.Size = init->ring_size; + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; - dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + - init->ring_start, - init->ring_size, dev); + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); - if (dev_priv->ring.virtual_start == NULL) { - dev->dev_private = (void *) dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *)dev_priv; + i810_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return -ENOMEM; + return -ENOMEM; } - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; dev_priv->w = init->w; dev_priv->h = init->h; @@ -391,33 +392,33 @@ static int i810_dma_initialize(drm_device_t *dev, dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv->zi1 = init->depth_offset | init->pitch_bits; - /* Program Hardware Status Page */ - dev_priv->hw_status_page = - pci_alloc_consistent(dev->pdev, PAGE_SIZE, - &dev_priv->dma_status_page); - if (!dev_priv->hw_status_page) { + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { dev->dev_private = (void *)dev_priv; i810_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); - DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); I810_WRITE(0x02080, dev_priv->dma_status_page); - DRM_DEBUG("Enabled hardware status page\n"); + DRM_DEBUG("Enabled hardware status page\n"); - /* Now we need to init our freelist */ + /* Now we need to init our freelist */ if (i810_freelist_init(dev, dev_priv) != 0) { dev->dev_private = (void *)dev_priv; - i810_dma_cleanup(dev); - DRM_ERROR("Not enough space in the status page for" + i810_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" " the freelist\n"); - return -ENOMEM; + return -ENOMEM; } dev->dev_private = (void *)dev_priv; - return 0; + return 0; } /* i810 DRM version 1.1 used a smaller init structure with different @@ -431,12 +432,12 @@ static int i810_dma_initialize(drm_device_t *dev, * If it isn't then we have a v1.1 client. Fix up params. * If it is, then we have a 1.2 client... get the rest of the data. */ -static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) +static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg) { /* Get v1.1 init data */ - if (copy_from_user(init, (drm_i810_pre12_init_t __user *)arg, - sizeof(drm_i810_pre12_init_t))) { + if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg, + sizeof(drm_i810_pre12_init_t))) { return -EFAULT; } @@ -444,7 +445,7 @@ static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) /* This is a v1.2 client, just get the v1.2 init data */ DRM_INFO("Using POST v1.2 init.\n"); - if (copy_from_user(init, (drm_i810_init_t __user *)arg, + if (copy_from_user(init, (drm_i810_init_t __user *) arg, sizeof(drm_i810_init_t))) { return -EFAULT; } @@ -452,246 +453,239 @@ static int i810_dma_init_compat(drm_i810_init_t *init, unsigned long arg) /* This is a v1.1 client, fix the params */ DRM_INFO("Using PRE v1.2 init.\n"); - init->pitch_bits = init->h; - init->pitch = init->w; - init->h = init->overlay_physical; - init->w = init->overlay_offset; - init->overlay_physical = 0; - init->overlay_offset = 0; + init->pitch_bits = init->h; + init->pitch = init->w; + init->h = init->overlay_physical; + init->w = init->overlay_offset; + init->overlay_physical = 0; + init->overlay_offset = 0; } return 0; } static int i810_dma_init(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv; - drm_i810_init_t init; - int retcode = 0; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv; + drm_i810_init_t init; + int retcode = 0; /* Get only the init func */ - if (copy_from_user(&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) + if (copy_from_user + (&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) return -EFAULT; - switch(init.func) { - case I810_INIT_DMA: - /* This case is for backward compatibility. It - * handles XFree 4.1.0 and 4.2.0, and has to - * do some parameter checking as described below. - * It will someday go away. - */ - retcode = i810_dma_init_compat(&init, arg); - if (retcode) - return retcode; - - dev_priv = drm_alloc(sizeof(drm_i810_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - retcode = i810_dma_initialize(dev, dev_priv, &init); - break; - - default: - case I810_INIT_DMA_1_4: - DRM_INFO("Using v1.4 init.\n"); - if (copy_from_user(&init, (drm_i810_init_t __user *)arg, - sizeof(drm_i810_init_t))) { - return -EFAULT; - } - dev_priv = drm_alloc(sizeof(drm_i810_private_t), - DRM_MEM_DRIVER); - if (dev_priv == NULL) - return -ENOMEM; - retcode = i810_dma_initialize(dev, dev_priv, &init); - break; - - case I810_CLEANUP_DMA: - DRM_INFO("DMA Cleanup\n"); - retcode = i810_dma_cleanup(dev); - break; + switch (init.func) { + case I810_INIT_DMA: + /* This case is for backward compatibility. It + * handles XFree 4.1.0 and 4.2.0, and has to + * do some parameter checking as described below. + * It will someday go away. + */ + retcode = i810_dma_init_compat(&init, arg); + if (retcode) + return retcode; + + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + default: + case I810_INIT_DMA_1_4: + DRM_INFO("Using v1.4 init.\n"); + if (copy_from_user(&init, (drm_i810_init_t __user *) arg, + sizeof(drm_i810_init_t))) { + return -EFAULT; + } + dev_priv = drm_alloc(sizeof(drm_i810_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i810_dma_initialize(dev, dev_priv, &init); + break; + + case I810_CLEANUP_DMA: + DRM_INFO("DMA Cleanup\n"); + retcode = i810_dma_cleanup(dev); + break; } - return retcode; + return retcode; } - - /* Most efficient way to verify state for the i810 is as it is * emitted. Non-conformant state is silently dropped. * * Use 'volatile' & local var tmp to force the emitted values to be * identical to the verified ones. */ -static void i810EmitContextVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitContextVerified(drm_device_t * dev, + volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_CTX_SETUP_SIZE ); + BEGIN_LP_RING(I810_CTX_SETUP_SIZE); - OUT_RING( GFX_OP_COLOR_FACTOR ); - OUT_RING( code[I810_CTXREG_CF1] ); + OUT_RING(GFX_OP_COLOR_FACTOR); + OUT_RING(code[I810_CTXREG_CF1]); - OUT_RING( GFX_OP_STIPPLE ); - OUT_RING( code[I810_CTXREG_ST1] ); + OUT_RING(GFX_OP_STIPPLE); + OUT_RING(code[I810_CTXREG_ST1]); - for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) { + for (i = 4; i < I810_CTX_SETUP_SIZE; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == (3<<29) && - (tmp & (0x1f<<24)) < (0x1d<<24)) - { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == (3 << 29) && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; - } - else printk("constext state dropped!!!\n"); + } else + printk("constext state dropped!!!\n"); } if (j & 1) - OUT_RING( 0 ); + OUT_RING(0); ADVANCE_LP_RING(); } -static void i810EmitTexVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_TEX_SETUP_SIZE ); + BEGIN_LP_RING(I810_TEX_SETUP_SIZE); - OUT_RING( GFX_OP_MAP_INFO ); - OUT_RING( code[I810_TEXREG_MI1] ); - OUT_RING( code[I810_TEXREG_MI2] ); - OUT_RING( code[I810_TEXREG_MI3] ); + OUT_RING(GFX_OP_MAP_INFO); + OUT_RING(code[I810_TEXREG_MI1]); + OUT_RING(code[I810_TEXREG_MI2]); + OUT_RING(code[I810_TEXREG_MI3]); - for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) { + for (i = 4; i < I810_TEX_SETUP_SIZE; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == (3<<29) && - (tmp & (0x1f<<24)) < (0x1d<<24)) - { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == (3 << 29) && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; - } - else printk("texture state dropped!!!\n"); + } else + printk("texture state dropped!!!\n"); } if (j & 1) - OUT_RING( 0 ); + OUT_RING(0); ADVANCE_LP_RING(); } - /* Need to do some additional checking when setting the dest buffer. */ -static void i810EmitDestVerified( drm_device_t *dev, - volatile unsigned int *code ) +static void i810EmitDestVerified(drm_device_t * dev, + volatile unsigned int *code) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); tmp = code[I810_DESTREG_DI1]; if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( tmp ); + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(tmp); } else - DRM_DEBUG("bad di1 %x (allow %x or %x)\n", - tmp, dev_priv->front_di1, dev_priv->back_di1); + DRM_DEBUG("bad di1 %x (allow %x or %x)\n", + tmp, dev_priv->front_di1, dev_priv->back_di1); /* invarient: */ - OUT_RING( CMD_OP_Z_BUFFER_INFO ); - OUT_RING( dev_priv->zi1 ); + OUT_RING(CMD_OP_Z_BUFFER_INFO); + OUT_RING(dev_priv->zi1); - OUT_RING( GFX_OP_DESTBUFFER_VARS ); - OUT_RING( code[I810_DESTREG_DV1] ); + OUT_RING(GFX_OP_DESTBUFFER_VARS); + OUT_RING(code[I810_DESTREG_DV1]); - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( code[I810_DESTREG_DR1] ); - OUT_RING( code[I810_DESTREG_DR2] ); - OUT_RING( code[I810_DESTREG_DR3] ); - OUT_RING( code[I810_DESTREG_DR4] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(code[I810_DESTREG_DR1]); + OUT_RING(code[I810_DESTREG_DR2]); + OUT_RING(code[I810_DESTREG_DR3]); + OUT_RING(code[I810_DESTREG_DR4]); + OUT_RING(0); ADVANCE_LP_RING(); } - - -static void i810EmitState( drm_device_t *dev ) +static void i810EmitState(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - + DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); if (dirty & I810_UPLOAD_BUFFERS) { - i810EmitDestVerified( dev, sarea_priv->BufferState ); + i810EmitDestVerified(dev, sarea_priv->BufferState); sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; } if (dirty & I810_UPLOAD_CTX) { - i810EmitContextVerified( dev, sarea_priv->ContextState ); + i810EmitContextVerified(dev, sarea_priv->ContextState); sarea_priv->dirty &= ~I810_UPLOAD_CTX; } if (dirty & I810_UPLOAD_TEX0) { - i810EmitTexVerified( dev, sarea_priv->TexState[0] ); + i810EmitTexVerified(dev, sarea_priv->TexState[0]); sarea_priv->dirty &= ~I810_UPLOAD_TEX0; } if (dirty & I810_UPLOAD_TEX1) { - i810EmitTexVerified( dev, sarea_priv->TexState[1] ); + i810EmitTexVerified(dev, sarea_priv->TexState[1]); sarea_priv->dirty &= ~I810_UPLOAD_TEX1; } } - - /* need to verify */ -static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, - unsigned int clear_color, - unsigned int clear_zval ) +static void i810_dma_dispatch_clear(drm_device_t * dev, int flags, + unsigned int clear_color, + unsigned int clear_zval) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; int cpp = 2; int i; RING_LOCALS; - - if ( dev_priv->current_page == 1 ) { - unsigned int tmp = flags; - + + if (dev_priv->current_page == 1) { + unsigned int tmp = flags; + flags &= ~(I810_FRONT | I810_BACK); - if (tmp & I810_FRONT) flags |= I810_BACK; - if (tmp & I810_BACK) flags |= I810_FRONT; + if (tmp & I810_FRONT) + flags |= I810_BACK; + if (tmp & I810_BACK) + flags |= I810_FRONT; } - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) - nbox = I810_NR_SAREA_CLIPRECTS; + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox ; i++, pbox++) { + for (i = 0; i < nbox; i++, pbox++) { unsigned int x = pbox->x1; unsigned int y = pbox->y1; unsigned int width = (pbox->x2 - x) * cpp; @@ -700,52 +694,48 @@ static void i810_dma_dispatch_clear( drm_device_t *dev, int flags, if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - if ( flags & I810_FRONT ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( start ); - OUT_RING( clear_color ); - OUT_RING( 0 ); + if (flags & I810_FRONT) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(start); + OUT_RING(clear_color); + OUT_RING(0); ADVANCE_LP_RING(); } - if ( flags & I810_BACK ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( dev_priv->back_offset + start ); - OUT_RING( clear_color ); - OUT_RING( 0 ); + if (flags & I810_BACK) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(dev_priv->back_offset + start); + OUT_RING(clear_color); + OUT_RING(0); ADVANCE_LP_RING(); } - if ( flags & I810_DEPTH ) { - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | - BR00_OP_COLOR_BLT | 0x3 ); - OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch ); - OUT_RING( (height << 16) | width ); - OUT_RING( dev_priv->depth_offset + start ); - OUT_RING( clear_zval ); - OUT_RING( 0 ); + if (flags & I810_DEPTH) { + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); + OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); + OUT_RING((height << 16) | width); + OUT_RING(dev_priv->depth_offset + start); + OUT_RING(clear_zval); + OUT_RING(0); ADVANCE_LP_RING(); } } } -static void i810_dma_dispatch_swap( drm_device_t *dev ) +static void i810_dma_dispatch_swap(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -755,75 +745,71 @@ static void i810_dma_dispatch_swap( drm_device_t *dev ) DRM_DEBUG("swapbuffers\n"); - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) - nbox = I810_NR_SAREA_CLIPRECTS; + if (nbox > I810_NR_SAREA_CLIPRECTS) + nbox = I810_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox; i++, pbox++) - { + for (i = 0; i < nbox; i++, pbox++) { unsigned int w = pbox->x2 - pbox->x1; unsigned int h = pbox->y2 - pbox->y1; - unsigned int dst = pbox->x1*cpp + pbox->y1*pitch; + unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch; unsigned int start = dst; if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - BEGIN_LP_RING( 6 ); - OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 ); - OUT_RING( pitch | (0xCC << 16)); - OUT_RING( (h << 16) | (w * cpp)); + BEGIN_LP_RING(6); + OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); + OUT_RING(pitch | (0xCC << 16)); + OUT_RING((h << 16) | (w * cpp)); if (dev_priv->current_page == 0) - OUT_RING(dev_priv->front_offset + start); + OUT_RING(dev_priv->front_offset + start); else - OUT_RING(dev_priv->back_offset + start); - OUT_RING( pitch ); + OUT_RING(dev_priv->back_offset + start); + OUT_RING(pitch); if (dev_priv->current_page == 0) - OUT_RING(dev_priv->back_offset + start); + OUT_RING(dev_priv->back_offset + start); else - OUT_RING(dev_priv->front_offset + start); + OUT_RING(dev_priv->front_offset + start); ADVANCE_LP_RING(); } } - -static void i810_dma_dispatch_vertex(drm_device_t *dev, - drm_buf_t *buf, - int discard, - int used) +static void i810_dma_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, int discard, int used) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; drm_i810_buf_priv_t *buf_priv = buf->dev_private; - drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_clip_rect_t *box = sarea_priv->boxes; - int nbox = sarea_priv->nbox; + drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; unsigned long address = (unsigned long)buf->bus_address; unsigned long start = address - dev->agp->base; int i = 0; - RING_LOCALS; + RING_LOCALS; - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - if (nbox > I810_NR_SAREA_CLIPRECTS) + if (nbox > I810_NR_SAREA_CLIPRECTS) nbox = I810_NR_SAREA_CLIPRECTS; - if (used > 4*1024) + if (used > 4 * 1024) used = 0; if (sarea_priv->dirty) - i810EmitState( dev ); + i810EmitState(dev); if (buf_priv->currently_mapped == I810_BUF_MAPPED) { unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); - *(u32 *)buf_priv->kernel_virtual = ((GFX_OP_PRIMITIVE | prim | ((used/4)-2))); + *(u32 *) buf_priv->kernel_virtual = + ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); if (used & 4) { - *(u32 *)((u32)buf_priv->kernel_virtual + used) = 0; + *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0; used += 4; } @@ -834,19 +820,20 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev, do { if (i < nbox) { BEGIN_LP_RING(4); - OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | - SC_ENABLE ); - OUT_RING( GFX_OP_SCISSOR_INFO ); - OUT_RING( box[i].x1 | (box[i].y1<<16) ); - OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) ); + OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | + SC_ENABLE); + OUT_RING(GFX_OP_SCISSOR_INFO); + OUT_RING(box[i].x1 | (box[i].y1 << 16)); + OUT_RING((box[i].x2 - + 1) | ((box[i].y2 - 1) << 16)); ADVANCE_LP_RING(); } BEGIN_LP_RING(4); - OUT_RING( CMD_OP_BATCH_BUFFER ); - OUT_RING( start | BB1_PROTECTED ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_BATCH_BUFFER); + OUT_RING(start | BB1_PROTECTED); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); } while (++i < nbox); @@ -855,59 +842,59 @@ static void i810_dma_dispatch_vertex(drm_device_t *dev, if (discard) { dev_priv->counter++; - (void) cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, - I810_BUF_HARDWARE); + (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, + I810_BUF_HARDWARE); BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 20 ); - OUT_RING( dev_priv->counter ); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I810_BUF_FREE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I810_BUF_FREE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); ADVANCE_LP_RING(); } } -static void i810_dma_dispatch_flip( drm_device_t *dev ) +static void i810_dma_dispatch_flip(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; int pitch = dev_priv->pitch; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); - - i810_kernel_lost_context(dev); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); + + i810_kernel_lost_context(dev); - BEGIN_LP_RING( 2 ); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 ); + BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); /* On i815 at least ASYNC is buggy */ /* pitch<<5 is from 11.2.8 p158, its the pitch / 8 then left shifted 8, so (pitch >> 3) << 8 */ - OUT_RING( CMD_OP_FRONTBUFFER_INFO | (pitch<<5) /*| ASYNC_FLIP */ ); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); dev_priv->current_page = 1; } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); dev_priv->current_page = 0; } OUT_RING(0); ADVANCE_LP_RING(); BEGIN_LP_RING(2); - OUT_RING( CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); + OUT_RING(0); ADVANCE_LP_RING(); /* Increment the frame counter. The client-side 3D driver must @@ -918,46 +905,46 @@ static void i810_dma_dispatch_flip( drm_device_t *dev ) } -static void i810_dma_quiescent(drm_device_t *dev) +static void i810_dma_quiescent(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; - RING_LOCALS; + drm_i810_private_t *dev_priv = dev->dev_private; + RING_LOCALS; /* printk("%s\n", __FUNCTION__); */ - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - BEGIN_LP_RING(4); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(4); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + OUT_RING(0); + ADVANCE_LP_RING(); - i810_wait_ring( dev, dev_priv->ring.Size - 8 ); + i810_wait_ring(dev, dev_priv->ring.Size - 8); } -static int i810_flush_queue(drm_device_t *dev) +static int i810_flush_queue(drm_device_t * dev) { - drm_i810_private_t *dev_priv = dev->dev_private; + drm_i810_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; - int i, ret = 0; - RING_LOCALS; - + int i, ret = 0; + RING_LOCALS; + /* printk("%s\n", __FUNCTION__); */ - i810_kernel_lost_context(dev); + i810_kernel_lost_context(dev); - BEGIN_LP_RING(2); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + ADVANCE_LP_RING(); - i810_wait_ring( dev, dev_priv->ring.Size - 8 ); + i810_wait_ring(dev, dev_priv->ring.Size - 8); - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, I810_BUF_FREE); @@ -968,24 +955,27 @@ static int i810_flush_queue(drm_device_t *dev) DRM_DEBUG("still on client\n"); } - return ret; + return ret; } /* Must be called with the lock held */ -void i810_reclaim_buffers(drm_device_t *dev, struct file *filp) +void i810_reclaim_buffers(drm_device_t * dev, struct file *filp) { drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; - if (!dev->dev_private) return; - if (!dma->buflist) return; + if (!dma) + return; + if (!dev->dev_private) + return; + if (!dma->buflist) + return; - i810_flush_queue(dev); + i810_flush_queue(dev); for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i810_buf_priv_t *buf_priv = buf->dev_private; + drm_buf_t *buf = dma->buflist[i]; + drm_i810_buf_priv_t *buf_priv = buf->dev_private; if (buf->filp == filp && buf_priv) { int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, @@ -994,7 +984,7 @@ void i810_reclaim_buffers(drm_device_t *dev, struct file *filp) if (used == I810_BUF_CLIENT) DRM_DEBUG("reclaimed from client\n"); if (buf_priv->currently_mapped == I810_BUF_MAPPED) - buf_priv->currently_mapped = I810_BUF_UNMAPPED; + buf_priv->currently_mapped = I810_BUF_UNMAPPED; } } } @@ -1002,29 +992,29 @@ void i810_reclaim_buffers(drm_device_t *dev, struct file *filp) static int i810_flush_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; LOCK_TEST_WITH_RETURN(dev, filp); - i810_flush_queue(dev); - return 0; + i810_flush_queue(dev); + return 0; } - static int i810_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_device_dma_t *dma = dev->dma; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; drm_i810_vertex_t vertex; - if (copy_from_user(&vertex, (drm_i810_vertex_t __user *)arg, sizeof(vertex))) + if (copy_from_user + (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex))) return -EFAULT; LOCK_TEST_WITH_RETURN(dev, filp); @@ -1032,48 +1022,46 @@ static int i810_dma_vertex(struct inode *inode, struct file *filp, DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", vertex.idx, vertex.used, vertex.discard); - if (vertex.idx < 0 || vertex.idx > dma->buf_count) + if (vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; - i810_dma_dispatch_vertex( dev, - dma->buflist[ vertex.idx ], - vertex.discard, vertex.used ); + i810_dma_dispatch_vertex(dev, + dma->buflist[vertex.idx], + vertex.discard, vertex.used); - atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); + atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); atomic_inc(&dev->counts[_DRM_STAT_DMA]); - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } - - static int i810_clear_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_i810_clear_t clear; - if (copy_from_user(&clear, (drm_i810_clear_t __user *)arg, sizeof(clear))) + if (copy_from_user + (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear))) return -EFAULT; LOCK_TEST_WITH_RETURN(dev, filp); - /* GH: Someone's doing nasty things... */ - if (!dev->dev_private) { - return -EINVAL; - } + /* GH: Someone's doing nasty things... */ + if (!dev->dev_private) { + return -EINVAL; + } - i810_dma_dispatch_clear( dev, clear.flags, - clear.clear_color, - clear.clear_depth ); - return 0; + i810_dma_dispatch_clear(dev, clear.flags, + clear.clear_color, clear.clear_depth); + return 0; } static int i810_swap_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1082,37 +1070,37 @@ static int i810_swap_bufs(struct inode *inode, struct file *filp, LOCK_TEST_WITH_RETURN(dev, filp); - i810_dma_dispatch_swap( dev ); - return 0; + i810_dma_dispatch_swap(dev); + return 0; } static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; - - sarea_priv->last_dispatch = (int) hw_status[5]; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - int retcode = 0; - drm_i810_dma_t d; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; - - if (copy_from_user(&d, (drm_i810_dma_t __user *)arg, sizeof(d))) + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode = 0; + drm_i810_dma_t d; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) + dev_priv->sarea_priv; + + if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d))) return -EFAULT; LOCK_TEST_WITH_RETURN(dev, filp); @@ -1124,29 +1112,29 @@ static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); - if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) return -EFAULT; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_dispatch = (int)hw_status[5]; return retcode; } static int i810_copybuf(struct inode *inode, - struct file *filp, unsigned int cmd, unsigned long arg) + struct file *filp, unsigned int cmd, unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; } static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; } -static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, - unsigned int last_render) +static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used, + unsigned int last_render) { drm_i810_private_t *dev_priv = dev->dev_private; drm_i810_buf_priv_t *buf_priv = buf->dev_private; @@ -1158,19 +1146,17 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, i810_kernel_lost_context(dev); - u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, - I810_BUF_HARDWARE); + u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE); if (u != I810_BUF_CLIENT) { DRM_DEBUG("MC found buffer that isn't mine!\n"); } - if (used > 4*1024) + if (used > 4 * 1024) used = 0; sarea_priv->dirty = 0x7f; - DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", - address, used); + DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used); dev_priv->counter++; DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); @@ -1181,46 +1167,45 @@ static void i810_dma_dispatch_mc(drm_device_t *dev, drm_buf_t *buf, int used, if (buf_priv->currently_mapped == I810_BUF_MAPPED) { if (used & 4) { - *(u32 *)((u32)buf_priv->virtual + used) = 0; + *(u32 *) ((u32) buf_priv->virtual + used) = 0; used += 4; } i810_unmap_buffer(buf); } BEGIN_LP_RING(4); - OUT_RING( CMD_OP_BATCH_BUFFER ); - OUT_RING( start | BB1_PROTECTED ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_BATCH_BUFFER); + OUT_RING(start | BB1_PROTECTED); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I810_BUF_FREE ); - OUT_RING( 0 ); - - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 16 ); - OUT_RING( last_render ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I810_BUF_FREE); + OUT_RING(0); + + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(16); + OUT_RING(last_render); + OUT_RING(0); ADVANCE_LP_RING(); } static int i810_dma_mc(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_device_dma_t *dma = dev->dma; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; u32 *hw_status = dev_priv->hw_status_page; drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) - dev_priv->sarea_priv; + dev_priv->sarea_priv; drm_i810_mc_t mc; - if (copy_from_user(&mc, (drm_i810_mc_t __user *)arg, sizeof(mc))) + if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc))) return -EFAULT; LOCK_TEST_WITH_RETURN(dev, filp); @@ -1229,12 +1214,12 @@ static int i810_dma_mc(struct inode *inode, struct file *filp, return -EINVAL; i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, - mc.last_render ); + mc.last_render); atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); atomic_inc(&dev->counts[_DRM_STAT_DMA]); - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } @@ -1244,22 +1229,23 @@ static int i810_rstatus(struct inode *inode, struct file *filp, { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; - return (int)(((u32 *)(dev_priv->hw_status_page))[4]); + return (int)(((u32 *) (dev_priv->hw_status_page))[4]); } static int i810_ov0_info(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; drm_i810_overlay_t data; data.offset = dev_priv->overlay_offset; data.physical = dev_priv->overlay_physical; - if (copy_to_user((drm_i810_overlay_t __user *)arg,&data,sizeof(data))) + if (copy_to_user + ((drm_i810_overlay_t __user *) arg, &data, sizeof(data))) return -EFAULT; return 0; } @@ -1269,7 +1255,7 @@ static int i810_fstatus(struct inode *inode, struct file *filp, { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; LOCK_TEST_WITH_RETURN(dev, filp); @@ -1277,47 +1263,46 @@ static int i810_fstatus(struct inode *inode, struct file *filp, } static int i810_ov0_flip(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private; + drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; LOCK_TEST_WITH_RETURN(dev, filp); //Tell the overlay to update - I810_WRITE(0x30000,dev_priv->overlay_physical | 0x80000000); + I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000); return 0; } - /* Not sure why this isn't set all the time: - */ -static void i810_do_init_pageflip( drm_device_t *dev ) + */ +static void i810_do_init_pageflip(drm_device_t * dev) { drm_i810_private_t *dev_priv = dev->dev_private; - + DRM_DEBUG("%s\n", __FUNCTION__); dev_priv->page_flipping = 1; dev_priv->current_page = 0; dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -static int i810_do_cleanup_pageflip( drm_device_t *dev ) +static int i810_do_cleanup_pageflip(drm_device_t * dev) { drm_i810_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if (dev_priv->current_page != 0) - i810_dma_dispatch_flip( dev ); + i810_dma_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; } static int i810_flip_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1327,19 +1312,19 @@ static int i810_flip_bufs(struct inode *inode, struct file *filp, LOCK_TEST_WITH_RETURN(dev, filp); - if (!dev_priv->page_flipping) - i810_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + i810_do_init_pageflip(dev); - i810_dma_dispatch_flip( dev ); - return 0; + i810_dma_dispatch_flip(dev); + return 0; } -void i810_driver_pretakedown(drm_device_t *dev) +void i810_driver_pretakedown(drm_device_t * dev) { - i810_dma_cleanup( dev ); + i810_dma_cleanup(dev); } -void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp) { if (dev->dev_private) { drm_i810_private_t *dev_priv = dev->dev_private; @@ -1349,33 +1334,47 @@ void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp) } } -void i810_driver_release(drm_device_t *dev, struct file *filp) +void i810_driver_release(drm_device_t * dev, struct file *filp) { i810_reclaim_buffers(dev, filp); } -int i810_driver_dma_quiescent(drm_device_t *dev) +int i810_driver_dma_quiescent(drm_device_t * dev) { - i810_dma_quiescent( dev ); + i810_dma_quiescent(dev); return 0; } drm_ioctl_desc_t i810_ioctls[] = { - [DRM_IOCTL_NR(DRM_I810_INIT)] = { i810_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_I810_VERTEX)] = { i810_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_CLEAR)] = { i810_clear_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FLUSH)] = { i810_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_GETAGE)] = { i810_getage, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_GETBUF)] = { i810_getbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_SWAP)] = { i810_swap_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_COPY)] = { i810_copybuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = { i810_docopy, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = { i810_ov0_info, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = { i810_fstatus, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = { i810_ov0_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_MC)] = { i810_dma_mc, 1, 1 }, - [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = { i810_rstatus, 1, 0 }, - [DRM_IOCTL_NR(DRM_I810_FLIP)] = { i810_flip_bufs, 1, 0 } + [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1} + , + [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0} + , + [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, 1, 0} }; int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); diff --git a/drivers/char/drm/i810_drm.h b/drivers/char/drm/i810_drm.h index 73ac40563b1..2deb925a94f 100644 --- a/drivers/char/drm/i810_drm.h +++ b/drivers/char/drm/i810_drm.h @@ -19,21 +19,20 @@ #define I810_LOG_MIN_TEX_REGION_SIZE 16 #endif -#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ -#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ +#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ +#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ #define I810_UPLOAD_CTX 0x4 #define I810_UPLOAD_BUFFERS 0x8 #define I810_UPLOAD_TEX0 0x10 #define I810_UPLOAD_TEX1 0x20 #define I810_UPLOAD_CLIPRECTS 0x40 - /* Indices into buf.Setup where various bits of state are mirrored per * context and per buffer. These can be fired at the card as a unit, * or in a piecewise fashion as required. */ -/* Destbuffer state +/* Destbuffer state * - backbuffer linear offset and pitch -- invarient in the current dri * - zbuffer linear offset and pitch -- also invarient * - drawing origin in back and depth buffers. @@ -55,13 +54,13 @@ /* Context state */ #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ -#define I810_CTXREG_CF1 1 -#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ +#define I810_CTXREG_CF1 1 +#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ #define I810_CTXREG_ST1 3 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ -#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ +#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ @@ -74,14 +73,14 @@ #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ -#define I810_CTX_SETUP_SIZE 20 +#define I810_CTX_SETUP_SIZE 20 /* Texture state (per tex unit) */ #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ -#define I810_TEXREG_MI1 1 -#define I810_TEXREG_MI2 2 -#define I810_TEXREG_MI3 3 +#define I810_TEXREG_MI1 1 +#define I810_TEXREG_MI2 2 +#define I810_TEXREG_MI3 3 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ @@ -98,7 +97,7 @@ typedef enum _drm_i810_init_func { I810_INIT_DMA = 0x01, I810_CLEANUP_DMA = 0x02, I810_INIT_DMA_1_4 = 0x03 - } drm_i810_init_func_t; +} drm_i810_init_func_t; /* This is the init structure after v1.2 */ typedef struct _drm_i810_init { @@ -122,7 +121,7 @@ typedef struct _drm_i810_init { unsigned int w; unsigned int h; unsigned int pitch; - unsigned int pitch_bits; + unsigned int pitch_bits; } drm_i810_init_t; /* This is the init structure prior to v1.2 */ @@ -140,23 +139,23 @@ typedef struct _drm_i810_pre12_init { unsigned int w; unsigned int h; unsigned int pitch; - unsigned int pitch_bits; + unsigned int pitch_bits; } drm_i810_pre12_init_t; /* Warning: If you change the SAREA structure you must change the Xserver * structure as well */ typedef struct _drm_i810_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i810_tex_region_t; typedef struct _drm_i810_sarea { - unsigned int ContextState[I810_CTX_SETUP_SIZE]; - unsigned int BufferState[I810_DEST_SETUP_SIZE]; - unsigned int TexState[2][I810_TEX_SETUP_SIZE]; - unsigned int dirty; + unsigned int ContextState[I810_CTX_SETUP_SIZE]; + unsigned int BufferState[I810_DEST_SETUP_SIZE]; + unsigned int TexState[2][I810_TEX_SETUP_SIZE]; + unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; @@ -174,22 +173,22 @@ typedef struct _drm_i810_sarea { * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject - * them all in LRU order. + * them all in LRU order. */ - - drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS+1]; - /* Last elt is sentinal */ - int texAge; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ + + drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; + /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ - int last_quiescent; /* */ + int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; - int pf_enabled; /* is pageflipping allowed? */ + int pf_enabled; /* is pageflipping allowed? */ int pf_active; - int pf_current_page; /* which buffer is being displayed? */ + int pf_current_page; /* which buffer is being displayed? */ } drm_i810_sarea_t; /* WARNING: If you change any of these defines, make sure to change the @@ -243,13 +242,13 @@ typedef struct _drm_i810_clear { * new set of cliprects. */ typedef struct _drm_i810_vertex { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i810_vertex_t; typedef struct _drm_i810_copy_t { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ void *address; /* Address to copy from */ } drm_i810_copy_t; @@ -264,7 +263,6 @@ typedef struct _drm_i810_copy_t { #define PR_RECTS (0x7<<18) #define PR_MASK (0x7<<18) - typedef struct drm_i810_dma { void *virtual; int request_idx; @@ -273,17 +271,16 @@ typedef struct drm_i810_dma { } drm_i810_dma_t; typedef struct _drm_i810_overlay_t { - unsigned int offset; /* Address of the Overlay Regs */ + unsigned int offset; /* Address of the Overlay Regs */ unsigned int physical; } drm_i810_overlay_t; typedef struct _drm_i810_mc { - int idx; /* buffer index */ - int used; /* nr bytes in use */ - int num_blocks; /* number of GFXBlocks */ - int *length; /* List of lengths for GFXBlocks (FUTURE)*/ - unsigned int last_render; /* Last Render Request */ + int idx; /* buffer index */ + int used; /* nr bytes in use */ + int num_blocks; /* number of GFXBlocks */ + int *length; /* List of lengths for GFXBlocks (FUTURE) */ + unsigned int last_render; /* Last Render Request */ } drm_i810_mc_t; - -#endif /* _I810_DRM_H_ */ +#endif /* _I810_DRM_H_ */ diff --git a/drivers/char/drm/i810_drv.c b/drivers/char/drm/i810_drv.c index 00609329d57..327e2f1cc99 100644 --- a/drivers/char/drm/i810_drv.c +++ b/drivers/char/drm/i810_drv.c @@ -38,7 +38,7 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { /* i810 has 4 more counters */ dev->counters += 4; @@ -46,29 +46,27 @@ static int postinit( struct drm_device *dev, unsigned long flags ) dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -80,7 +78,9 @@ extern drm_ioctl_desc_t i810_ioctls[]; extern int i810_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, .dev_priv_size = sizeof(drm_i810_buf_priv_t), .pretakedown = i810_driver_pretakedown, .prerelease = i810_driver_prerelease, @@ -94,18 +94,20 @@ static struct drm_driver driver = { .version = version, .ioctls = i810_ioctls, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + } + , .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - }, + .name = DRIVER_NAME, + .id_table = pciidlist, + } + , }; static int __init i810_init(void) @@ -122,6 +124,6 @@ static void __exit i810_exit(void) module_init(i810_init); module_exit(i810_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h index 62ee4f58c59..2d6b594afa0 100644 --- a/drivers/char/drm/i810_drv.h +++ b/drivers/char/drm/i810_drv.h @@ -56,14 +56,14 @@ #define DRIVER_PATCHLEVEL 0 typedef struct drm_i810_buf_priv { - u32 *in_use; - int my_use_idx; + u32 *in_use; + int my_use_idx; int currently_mapped; void *virtual; void *kernel_virtual; } drm_i810_buf_priv_t; -typedef struct _drm_i810_ring_buffer{ +typedef struct _drm_i810_ring_buffer { int tail_mask; unsigned long Start; unsigned long End; @@ -79,16 +79,15 @@ typedef struct drm_i810_private { drm_map_t *mmio_map; drm_i810_sarea_t *sarea_priv; - drm_i810_ring_buffer_t ring; + drm_i810_ring_buffer_t ring; - void *hw_status_page; - unsigned long counter; + void *hw_status_page; + unsigned long counter; dma_addr_t dma_status_page; drm_buf_t *mmap_buffer; - u32 front_di1, back_di1, zi1; int back_offset; @@ -97,7 +96,7 @@ typedef struct drm_i810_private { int overlay_physical; int w, h; int pitch; - int back_pitch; + int back_pitch; int depth_pitch; int do_boxes; @@ -107,19 +106,19 @@ typedef struct drm_i810_private { int page_flipping; wait_queue_head_t irq_queue; - atomic_t irq_received; - atomic_t irq_emitted; - - int front_offset; + atomic_t irq_received; + atomic_t irq_emitted; + + int front_offset; } drm_i810_private_t; /* i810_dma.c */ -extern void i810_reclaim_buffers(drm_device_t *dev, struct file *filp); +extern void i810_reclaim_buffers(drm_device_t * dev, struct file *filp); -extern int i810_driver_dma_quiescent(drm_device_t *dev); -extern void i810_driver_release(drm_device_t *dev, struct file *filp); -extern void i810_driver_pretakedown(drm_device_t *dev); -extern void i810_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern int i810_driver_dma_quiescent(drm_device_t * dev); +extern void i810_driver_release(drm_device_t * dev, struct file *filp); +extern void i810_driver_pretakedown(drm_device_t * dev); +extern void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp); extern int i810_driver_device_is_agp(drm_device_t * dev); #define I810_BASE(reg) ((unsigned long) \ @@ -170,7 +169,6 @@ extern int i810_driver_device_is_agp(drm_device_t * dev); #define INST_OP_FLUSH 0x02000000 #define INST_FLUSH_MAP_CACHE 0x00000001 - #define BB1_START_ADDR_MASK (~0x7) #define BB1_PROTECTED (1<<0) #define BB1_UNPROTECTED (0<<0) @@ -229,8 +227,8 @@ extern int i810_driver_device_is_agp(drm_device_t * dev); #define BR00_OP_SRC_COPY_BLT 0x10C00000 #define BR13_SOLID_PATTERN 0x80000000 -#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) -#define WAIT_FOR_PLANE_A_FLIP (1<<2) +#define WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define WAIT_FOR_PLANE_A_FLIP (1<<2) #define WAIT_FOR_VBLANK (1<<3) #endif diff --git a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c index 6f89d5796ef..e1107ecb16e 100644 --- a/drivers/char/drm/i830_dma.c +++ b/drivers/char/drm/i830_dma.c @@ -11,11 +11,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -47,103 +47,104 @@ #define I830_BUF_UNMAPPED 0 #define I830_BUF_MAPPED 1 -static drm_buf_t *i830_freelist_get(drm_device_t *dev) +static drm_buf_t *i830_freelist_get(drm_device_t * dev) { - drm_device_dma_t *dma = dev->dma; - int i; - int used; - + drm_device_dma_t *dma = dev->dma; + int i; + int used; + /* Linear search might not be the best solution */ - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, + used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, I830_BUF_CLIENT); - if(used == I830_BUF_FREE) { + if (used == I830_BUF_FREE) { return buf; } } - return NULL; + return NULL; } /* This should only be called if the buffer is not sent to the hardware * yet, the hardware updates in use for us once its on the ring buffer. */ -static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf) +static int i830_freelist_put(drm_device_t * dev, drm_buf_t * buf) { - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - int used; - - /* In use is already a pointer */ - used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); - if(used != I830_BUF_CLIENT) { - DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); - return -EINVAL; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + int used; + + /* In use is already a pointer */ + used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); + if (used != I830_BUF_CLIENT) { + DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); + return -EINVAL; } - - return 0; + + return 0; } static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev; - drm_i830_private_t *dev_priv; - drm_buf_t *buf; + drm_file_t *priv = filp->private_data; + drm_device_t *dev; + drm_i830_private_t *dev_priv; + drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; lock_kernel(); - dev = priv->head->dev; + dev = priv->head->dev; dev_priv = dev->dev_private; - buf = dev_priv->mmap_buffer; + buf = dev_priv->mmap_buffer; buf_priv = buf->dev_private; - + vma->vm_flags |= (VM_IO | VM_DONTCOPY); vma->vm_file = filp; - - buf_priv->currently_mapped = I830_BUF_MAPPED; + + buf_priv->currently_mapped = I830_BUF_MAPPED; unlock_kernel(); if (io_remap_pfn_range(vma, vma->vm_start, - VM_OFFSET(vma) >> PAGE_SHIFT, - vma->vm_end - vma->vm_start, - vma->vm_page_prot)) return -EAGAIN; + VM_OFFSET(vma) >> PAGE_SHIFT, + vma->vm_end - vma->vm_start, vma->vm_page_prot)) + return -EAGAIN; return 0; } static struct file_operations i830_buffer_fops = { - .open = drm_open, - .flush = drm_flush, + .open = drm_open, + .flush = drm_flush, .release = drm_release, - .ioctl = drm_ioctl, - .mmap = i830_mmap_buffers, - .fasync = drm_fasync, + .ioctl = drm_ioctl, + .mmap = i830_mmap_buffers, + .fasync = drm_fasync, }; -static int i830_map_buffer(drm_buf_t *buf, struct file *filp) +static int i830_map_buffer(drm_buf_t * buf, struct file *filp) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - drm_i830_private_t *dev_priv = dev->dev_private; - struct file_operations *old_fops; + drm_i830_private_t *dev_priv = dev->dev_private; + struct file_operations *old_fops; unsigned long virtual; int retcode = 0; - if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL; + if (buf_priv->currently_mapped == I830_BUF_MAPPED) + return -EINVAL; - down_write( ¤t->mm->mmap_sem ); + down_write(¤t->mm->mmap_sem); old_fops = filp->f_op; filp->f_op = &i830_buffer_fops; dev_priv->mmap_buffer = buf; - virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE, - MAP_SHARED, buf->bus_address); + virtual = do_mmap(filp, 0, buf->total, PROT_READ | PROT_WRITE, + MAP_SHARED, buf->bus_address); dev_priv->mmap_buffer = NULL; filp->f_op = old_fops; - if (IS_ERR((void *)virtual)) { /* ugh */ + if (IS_ERR((void *)virtual)) { /* ugh */ /* Real error */ DRM_ERROR("mmap error\n"); retcode = virtual; @@ -151,17 +152,17 @@ static int i830_map_buffer(drm_buf_t *buf, struct file *filp) } else { buf_priv->virtual = (void __user *)virtual; } - up_write( ¤t->mm->mmap_sem ); + up_write(¤t->mm->mmap_sem); return retcode; } -static int i830_unmap_buffer(drm_buf_t *buf) +static int i830_unmap_buffer(drm_buf_t * buf) { drm_i830_buf_priv_t *buf_priv = buf->dev_private; int retcode = 0; - if(buf_priv->currently_mapped != I830_BUF_MAPPED) + if (buf_priv->currently_mapped != I830_BUF_MAPPED) return -EINVAL; down_write(¤t->mm->mmap_sem); @@ -170,43 +171,43 @@ static int i830_unmap_buffer(drm_buf_t *buf) (size_t) buf->total); up_write(¤t->mm->mmap_sem); - buf_priv->currently_mapped = I830_BUF_UNMAPPED; - buf_priv->virtual = NULL; + buf_priv->currently_mapped = I830_BUF_UNMAPPED; + buf_priv->virtual = NULL; return retcode; } -static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, +static int i830_dma_get_buffer(drm_device_t * dev, drm_i830_dma_t * d, struct file *filp) { - drm_buf_t *buf; + drm_buf_t *buf; drm_i830_buf_priv_t *buf_priv; int retcode = 0; buf = i830_freelist_get(dev); if (!buf) { retcode = -ENOMEM; - DRM_DEBUG("retcode=%d\n", retcode); + DRM_DEBUG("retcode=%d\n", retcode); return retcode; } - + retcode = i830_map_buffer(buf, filp); - if(retcode) { + if (retcode) { i830_freelist_put(dev, buf); - DRM_ERROR("mapbuf failed, retcode %d\n", retcode); + DRM_ERROR("mapbuf failed, retcode %d\n", retcode); return retcode; } buf->filp = filp; - buf_priv = buf->dev_private; + buf_priv = buf->dev_private; d->granted = 1; - d->request_idx = buf->idx; - d->request_size = buf->total; - d->virtual = buf_priv->virtual; + d->request_idx = buf->idx; + d->request_size = buf->total; + d->virtual = buf_priv->virtual; return retcode; } -static int i830_dma_cleanup(drm_device_t *dev) +static int i830_dma_cleanup(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; @@ -214,140 +215,144 @@ static int i830_dma_cleanup(drm_device_t *dev) * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); if (dev->dev_private) { int i; - drm_i830_private_t *dev_priv = - (drm_i830_private_t *) dev->dev_private; - - if (dev_priv->ring.virtual_start) { - drm_ioremapfree((void *) dev_priv->ring.virtual_start, - dev_priv->ring.Size, dev); + drm_i830_private_t *dev_priv = + (drm_i830_private_t *) dev->dev_private; + + if (dev_priv->ring.virtual_start) { + drm_ioremapfree((void *)dev_priv->ring.virtual_start, + dev_priv->ring.Size, dev); } - if (dev_priv->hw_status_page) { + if (dev_priv->hw_status_page) { pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); - /* Need to rewrite hardware status page */ - I830_WRITE(0x02080, 0x1ffff000); + /* Need to rewrite hardware status page */ + I830_WRITE(0x02080, 0x1ffff000); } - drm_free(dev->dev_private, sizeof(drm_i830_private_t), + drm_free(dev->dev_private, sizeof(drm_i830_private_t), DRM_MEM_DRIVER); - dev->dev_private = NULL; + dev->dev_private = NULL; for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; + drm_buf_t *buf = dma->buflist[i]; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - if ( buf_priv->kernel_virtual && buf->total ) - drm_ioremapfree(buf_priv->kernel_virtual, buf->total, dev); + if (buf_priv->kernel_virtual && buf->total) + drm_ioremapfree(buf_priv->kernel_virtual, + buf->total, dev); } } - return 0; + return 0; } -int i830_wait_ring(drm_device_t *dev, int n, const char *caller) +int i830_wait_ring(drm_device_t * dev, int n, const char *caller) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_ring_buffer_t *ring = &(dev_priv->ring); - int iters = 0; - unsigned long end; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + int iters = 0; + unsigned long end; unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - end = jiffies + (HZ*3); - while (ring->space < n) { - ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; - + end = jiffies + (HZ * 3); + while (ring->space < n) { + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; + if (ring->head != last_head) { - end = jiffies + (HZ*3); + end = jiffies + (HZ * 3); last_head = ring->head; } - - iters++; - if(time_before(end, jiffies)) { - DRM_ERROR("space: %d wanted %d\n", ring->space, n); - DRM_ERROR("lockup\n"); - goto out_wait_ring; + + iters++; + if (time_before(end, jiffies)) { + DRM_ERROR("space: %d wanted %d\n", ring->space, n); + DRM_ERROR("lockup\n"); + goto out_wait_ring; } udelay(1); dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; } -out_wait_ring: - return iters; + out_wait_ring: + return iters; } -static void i830_kernel_lost_context(drm_device_t *dev) +static void i830_kernel_lost_context(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_ring_buffer_t *ring = &(dev_priv->ring); - - ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; - ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; - ring->space = ring->head - (ring->tail+8); - if (ring->space < 0) ring->space += ring->Size; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_ring_buffer_t *ring = &(dev_priv->ring); + + ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR; + ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR; + ring->space = ring->head - (ring->tail + 8); + if (ring->space < 0) + ring->space += ring->Size; if (ring->head == ring->tail) dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; } -static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv) +static int i830_freelist_init(drm_device_t * dev, drm_i830_private_t * dev_priv) { - drm_device_dma_t *dma = dev->dma; - int my_idx = 36; - u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx); - int i; - - if(dma->buf_count > 1019) { - /* Not enough space in the status page for the freelist */ - return -EINVAL; + drm_device_dma_t *dma = dev->dma; + int my_idx = 36; + u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); + int i; + + if (dma->buf_count > 1019) { + /* Not enough space in the status page for the freelist */ + return -EINVAL; } - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; - buf_priv->in_use = hw_status++; - buf_priv->my_use_idx = my_idx; - my_idx += 4; + buf_priv->in_use = hw_status++; + buf_priv->my_use_idx = my_idx; + my_idx += 4; - *buf_priv->in_use = I830_BUF_FREE; + *buf_priv->in_use = I830_BUF_FREE; - buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, - buf->total, dev); + buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, + buf->total, dev); } return 0; } -static int i830_dma_initialize(drm_device_t *dev, - drm_i830_private_t *dev_priv, - drm_i830_init_t *init) +static int i830_dma_initialize(drm_device_t * dev, + drm_i830_private_t * dev_priv, + drm_i830_init_t * init) { struct list_head *list; - memset(dev_priv, 0, sizeof(drm_i830_private_t)); + memset(dev_priv, 0, sizeof(drm_i830_private_t)); list_for_each(list, &dev->maplist->head) { drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); - if( r_list->map && + if (r_list->map && r_list->map->type == _DRM_SHM && - r_list->map->flags & _DRM_CONTAINS_LOCK ) { + r_list->map->flags & _DRM_CONTAINS_LOCK) { dev_priv->sarea_map = r_list->map; - break; - } - } + break; + } + } - if(!dev_priv->sarea_map) { + if (!dev_priv->sarea_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find sarea!\n"); return -EINVAL; } dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio_map) { + if (!dev_priv->mmio_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find mmio map!\n"); @@ -355,7 +360,7 @@ static int i830_dma_initialize(drm_device_t *dev, } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("can not find dma buffer map!\n"); @@ -363,27 +368,26 @@ static int i830_dma_initialize(drm_device_t *dev, } dev_priv->sarea_priv = (drm_i830_sarea_t *) - ((u8 *)dev_priv->sarea_map->handle + - init->sarea_priv_offset); + ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); - dev_priv->ring.Start = init->ring_start; - dev_priv->ring.End = init->ring_end; - dev_priv->ring.Size = init->ring_size; + dev_priv->ring.Start = init->ring_start; + dev_priv->ring.End = init->ring_end; + dev_priv->ring.Size = init->ring_size; - dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + - init->ring_start, - init->ring_size, dev); + dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + + init->ring_start, + init->ring_size, dev); - if (dev_priv->ring.virtual_start == NULL) { - dev->dev_private = (void *) dev_priv; - i830_dma_cleanup(dev); - DRM_ERROR("can not ioremap virtual address for" + if (dev_priv->ring.virtual_start == NULL) { + dev->dev_private = (void *)dev_priv; + i830_dma_cleanup(dev); + DRM_ERROR("can not ioremap virtual address for" " ring buffer\n"); - return -ENOMEM; + return -ENOMEM; } - dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; - + dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; + dev_priv->w = init->w; dev_priv->h = init->h; dev_priv->pitch = init->pitch; @@ -395,10 +399,10 @@ static int i830_dma_initialize(drm_device_t *dev, dev_priv->back_di1 = init->back_offset | init->pitch_bits; dev_priv->zi1 = init->depth_offset | init->pitch_bits; - DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); + DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1); DRM_DEBUG("back_offset %x\n", dev_priv->back_offset); - DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); - DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); + DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1); + DRM_DEBUG("pitch_bits %x\n", init->pitch_bits); dev_priv->cpp = init->cpp; /* We are using separate values as placeholders for mechanisms for @@ -410,63 +414,64 @@ static int i830_dma_initialize(drm_device_t *dev, dev_priv->do_boxes = 0; dev_priv->use_mi_batchbuffer_start = 0; - /* Program Hardware Status Page */ - dev_priv->hw_status_page = - pci_alloc_consistent(dev->pdev, PAGE_SIZE, - &dev_priv->dma_status_page); - if (!dev_priv->hw_status_page) { + /* Program Hardware Status Page */ + dev_priv->hw_status_page = + pci_alloc_consistent(dev->pdev, PAGE_SIZE, + &dev_priv->dma_status_page); + if (!dev_priv->hw_status_page) { dev->dev_private = (void *)dev_priv; i830_dma_cleanup(dev); DRM_ERROR("Can not allocate hardware status page\n"); return -ENOMEM; } - memset(dev_priv->hw_status_page, 0, PAGE_SIZE); + memset(dev_priv->hw_status_page, 0, PAGE_SIZE); DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); - - I830_WRITE(0x02080, dev_priv->dma_status_page); + + I830_WRITE(0x02080, dev_priv->dma_status_page); DRM_DEBUG("Enabled hardware status page\n"); - - /* Now we need to init our freelist */ - if(i830_freelist_init(dev, dev_priv) != 0) { + + /* Now we need to init our freelist */ + if (i830_freelist_init(dev, dev_priv) != 0) { dev->dev_private = (void *)dev_priv; - i830_dma_cleanup(dev); - DRM_ERROR("Not enough space in the status page for" + i830_dma_cleanup(dev); + DRM_ERROR("Not enough space in the status page for" " the freelist\n"); - return -ENOMEM; + return -ENOMEM; } dev->dev_private = (void *)dev_priv; - return 0; + return 0; } static int i830_dma_init(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_i830_private_t *dev_priv; - drm_i830_init_t init; - int retcode = 0; - - if (copy_from_user(&init, (void * __user) arg, sizeof(init))) + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv; + drm_i830_init_t init; + int retcode = 0; + + if (copy_from_user(&init, (void *__user)arg, sizeof(init))) return -EFAULT; - - switch(init.func) { - case I830_INIT_DMA: - dev_priv = drm_alloc(sizeof(drm_i830_private_t), - DRM_MEM_DRIVER); - if(dev_priv == NULL) return -ENOMEM; - retcode = i830_dma_initialize(dev, dev_priv, &init); - break; - case I830_CLEANUP_DMA: - retcode = i830_dma_cleanup(dev); - break; - default: - retcode = -EINVAL; - break; + + switch (init.func) { + case I830_INIT_DMA: + dev_priv = drm_alloc(sizeof(drm_i830_private_t), + DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + retcode = i830_dma_initialize(dev, dev_priv, &init); + break; + case I830_CLEANUP_DMA: + retcode = i830_dma_cleanup(dev); + break; + default: + retcode = -EINVAL; + break; } - - return retcode; + + return retcode; } #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) @@ -476,92 +481,89 @@ static int i830_dma_init(struct inode *inode, struct file *filp, /* Most efficient way to verify state for the i830 is as it is * emitted. Non-conformant state is silently dropped. */ -static void i830EmitContextVerified( drm_device_t *dev, - unsigned int *code ) +static void i830EmitContextVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 ); + BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4); - for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) { + for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == CMD_3D && - (tmp & (0x1f<<24)) < (0x1d<<24)) { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == CMD_3D && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; } else { DRM_ERROR("Skipping %d\n", i); } } - OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD ); - OUT_RING( code[I830_CTXREG_BLENDCOLR] ); + OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD); + OUT_RING(code[I830_CTXREG_BLENDCOLR]); j += 2; - for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) { + for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) { tmp = code[i]; - if ((tmp & (7<<29)) == CMD_3D && - (tmp & (0x1f<<24)) < (0x1d<<24)) { - OUT_RING( tmp ); + if ((tmp & (7 << 29)) == CMD_3D && + (tmp & (0x1f << 24)) < (0x1d << 24)) { + OUT_RING(tmp); j++; } else { DRM_ERROR("Skipping %d\n", i); } } - OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD ); - OUT_RING( code[I830_CTXREG_MCSB1] ); + OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD); + OUT_RING(code[I830_CTXREG_MCSB1]); j += 2; - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code ) +static void i830EmitTexVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO || - (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) == - (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) { - - BEGIN_LP_RING( I830_TEX_SETUP_SIZE ); - - OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */ - OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */ - OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */ - OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */ - OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */ - OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */ - - for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) { + (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) == + (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) { + + BEGIN_LP_RING(I830_TEX_SETUP_SIZE); + + OUT_RING(code[I830_TEXREG_MI0]); /* TM0LI */ + OUT_RING(code[I830_TEXREG_MI1]); /* TM0S0 */ + OUT_RING(code[I830_TEXREG_MI2]); /* TM0S1 */ + OUT_RING(code[I830_TEXREG_MI3]); /* TM0S2 */ + OUT_RING(code[I830_TEXREG_MI4]); /* TM0S3 */ + OUT_RING(code[I830_TEXREG_MI5]); /* TM0S4 */ + + for (i = 6; i < I830_TEX_SETUP_SIZE; i++) { tmp = code[i]; - OUT_RING( tmp ); + OUT_RING(tmp); j++; - } + } - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); - } - else + } else printk("rejected packet %x\n", code[0]); } -static void i830EmitTexBlendVerified( drm_device_t *dev, - unsigned int *code, - unsigned int num) +static void i830EmitTexBlendVerified(drm_device_t * dev, + unsigned int *code, unsigned int num) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i, j = 0; unsigned int tmp; RING_LOCALS; @@ -569,59 +571,54 @@ static void i830EmitTexBlendVerified( drm_device_t *dev, if (!num) return; - BEGIN_LP_RING( num + 1 ); + BEGIN_LP_RING(num + 1); - for ( i = 0 ; i < num ; i++ ) { + for (i = 0; i < num; i++) { tmp = code[i]; - OUT_RING( tmp ); + OUT_RING(tmp); j++; } - if (j & 1) - OUT_RING( 0 ); + if (j & 1) + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitTexPalette( drm_device_t *dev, - unsigned int *palette, - int number, - int is_shared ) +static void i830EmitTexPalette(drm_device_t * dev, + unsigned int *palette, int number, int is_shared) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; return; - BEGIN_LP_RING( 258 ); + BEGIN_LP_RING(258); - if(is_shared == 1) { + if (is_shared == 1) { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | - MAP_PALETTE_NUM(0) | - MAP_PALETTE_BOTH); + MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH); } else { OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number)); } - for(i = 0; i < 256; i++) { + for (i = 0; i < 256; i++) { OUT_RING(palette[i]); } OUT_RING(0); - /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! + /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop! */ } /* Need to do some additional checking when setting the dest buffer. */ -static void i830EmitDestVerified( drm_device_t *dev, - unsigned int *code ) -{ - drm_i830_private_t *dev_priv = dev->dev_private; +static void i830EmitDestVerified(drm_device_t * dev, unsigned int *code) +{ + drm_i830_private_t *dev_priv = dev->dev_private; unsigned int tmp; RING_LOCALS; - BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 ); - + BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10); tmp = code[I830_DESTREG_CBUFADDR]; if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { @@ -630,18 +627,18 @@ static void i830EmitDestVerified( drm_device_t *dev, OUT_RING(0); } - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( BUF_3D_ID_COLOR_BACK | - BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | - BUF_3D_USE_FENCE); - OUT_RING( tmp ); - OUT_RING( 0 ); - - OUT_RING( CMD_OP_DESTBUFFER_INFO ); - OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | - BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); - OUT_RING( dev_priv->zi1 ); - OUT_RING( 0 ); + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(BUF_3D_ID_COLOR_BACK | + BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) | + BUF_3D_USE_FENCE); + OUT_RING(tmp); + OUT_RING(0); + + OUT_RING(CMD_OP_DESTBUFFER_INFO); + OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | + BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp)); + OUT_RING(dev_priv->zi1); + OUT_RING(0); } else { DRM_ERROR("bad di1 %x (allow %x or %x)\n", tmp, dev_priv->front_di1, dev_priv->back_di1); @@ -650,83 +647,80 @@ static void i830EmitDestVerified( drm_device_t *dev, /* invarient: */ + OUT_RING(GFX_OP_DESTBUFFER_VARS); + OUT_RING(code[I830_DESTREG_DV1]); - OUT_RING( GFX_OP_DESTBUFFER_VARS ); - OUT_RING( code[I830_DESTREG_DV1] ); - - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( code[I830_DESTREG_DR1] ); - OUT_RING( code[I830_DESTREG_DR2] ); - OUT_RING( code[I830_DESTREG_DR3] ); - OUT_RING( code[I830_DESTREG_DR4] ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(code[I830_DESTREG_DR1]); + OUT_RING(code[I830_DESTREG_DR2]); + OUT_RING(code[I830_DESTREG_DR3]); + OUT_RING(code[I830_DESTREG_DR4]); /* Need to verify this */ tmp = code[I830_DESTREG_SENABLE]; - if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { - OUT_RING( tmp ); + if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) { + OUT_RING(tmp); } else { DRM_ERROR("bad scissor enable\n"); - OUT_RING( 0 ); + OUT_RING(0); } - OUT_RING( GFX_OP_SCISSOR_RECT ); - OUT_RING( code[I830_DESTREG_SR1] ); - OUT_RING( code[I830_DESTREG_SR2] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_SCISSOR_RECT); + OUT_RING(code[I830_DESTREG_SR1]); + OUT_RING(code[I830_DESTREG_SR2]); + OUT_RING(0); ADVANCE_LP_RING(); } -static void i830EmitStippleVerified( drm_device_t *dev, - unsigned int *code ) +static void i830EmitStippleVerified(drm_device_t * dev, unsigned int *code) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; - BEGIN_LP_RING( 2 ); - OUT_RING( GFX_OP_STIPPLE ); - OUT_RING( code[1] ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(GFX_OP_STIPPLE); + OUT_RING(code[1]); + ADVANCE_LP_RING(); } - -static void i830EmitState( drm_device_t *dev ) +static void i830EmitState(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); if (dirty & I830_UPLOAD_BUFFERS) { - i830EmitDestVerified( dev, sarea_priv->BufferState ); + i830EmitDestVerified(dev, sarea_priv->BufferState); sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; } if (dirty & I830_UPLOAD_CTX) { - i830EmitContextVerified( dev, sarea_priv->ContextState ); + i830EmitContextVerified(dev, sarea_priv->ContextState); sarea_priv->dirty &= ~I830_UPLOAD_CTX; } if (dirty & I830_UPLOAD_TEX0) { - i830EmitTexVerified( dev, sarea_priv->TexState[0] ); + i830EmitTexVerified(dev, sarea_priv->TexState[0]); sarea_priv->dirty &= ~I830_UPLOAD_TEX0; } if (dirty & I830_UPLOAD_TEX1) { - i830EmitTexVerified( dev, sarea_priv->TexState[1] ); + i830EmitTexVerified(dev, sarea_priv->TexState[1]); sarea_priv->dirty &= ~I830_UPLOAD_TEX1; } if (dirty & I830_UPLOAD_TEXBLEND0) { - i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0], - sarea_priv->TexBlendStateWordsUsed[0]); + i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0], + sarea_priv->TexBlendStateWordsUsed[0]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0; } if (dirty & I830_UPLOAD_TEXBLEND1) { - i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1], - sarea_priv->TexBlendStateWordsUsed[1]); + i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1], + sarea_priv->TexBlendStateWordsUsed[1]); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1; } @@ -759,36 +753,32 @@ static void i830EmitState( drm_device_t *dev ) /* 1.3: */ if (dirty & I830_UPLOAD_STIPPLE) { - i830EmitStippleVerified( dev, - sarea_priv->StippleState); + i830EmitStippleVerified(dev, sarea_priv->StippleState); sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE; } if (dirty & I830_UPLOAD_TEX2) { - i830EmitTexVerified( dev, sarea_priv->TexState2 ); + i830EmitTexVerified(dev, sarea_priv->TexState2); sarea_priv->dirty &= ~I830_UPLOAD_TEX2; } if (dirty & I830_UPLOAD_TEX3) { - i830EmitTexVerified( dev, sarea_priv->TexState3 ); + i830EmitTexVerified(dev, sarea_priv->TexState3); sarea_priv->dirty &= ~I830_UPLOAD_TEX3; } - if (dirty & I830_UPLOAD_TEXBLEND2) { - i830EmitTexBlendVerified( - dev, - sarea_priv->TexBlendState2, - sarea_priv->TexBlendStateWordsUsed2); + i830EmitTexBlendVerified(dev, + sarea_priv->TexBlendState2, + sarea_priv->TexBlendStateWordsUsed2); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2; } if (dirty & I830_UPLOAD_TEXBLEND3) { - i830EmitTexBlendVerified( - dev, - sarea_priv->TexBlendState3, - sarea_priv->TexBlendStateWordsUsed3); + i830EmitTexBlendVerified(dev, + sarea_priv->TexBlendState3, + sarea_priv->TexBlendStateWordsUsed3); sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3; } } @@ -797,97 +787,96 @@ static void i830EmitState( drm_device_t *dev ) * Performance monitoring functions */ -static void i830_fill_box( drm_device_t *dev, - int x, int y, int w, int h, - int r, int g, int b ) +static void i830_fill_box(drm_device_t * dev, + int x, int y, int w, int h, int r, int g, int b) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; u32 color; unsigned int BR13, CMD; RING_LOCALS; - BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24); + BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24); CMD = XY_COLOR_BLT_CMD; x += dev_priv->sarea_priv->boxes[0].x1; y += dev_priv->sarea_priv->boxes[0].y1; if (dev_priv->cpp == 4) { - BR13 |= (1<<25); + BR13 |= (1 << 25); CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); } else { color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); } - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (y << 16) | x ); - OUT_RING( ((y+h) << 16) | (x+w) ); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((y << 16) | x); + OUT_RING(((y + h) << 16) | (x + w)); - if ( dev_priv->current_page == 1 ) { - OUT_RING( dev_priv->front_offset ); - } else { - OUT_RING( dev_priv->back_offset ); - } + if (dev_priv->current_page == 1) { + OUT_RING(dev_priv->front_offset); + } else { + OUT_RING(dev_priv->back_offset); + } - OUT_RING( color ); + OUT_RING(color); ADVANCE_LP_RING(); } -static void i830_cp_performance_boxes( drm_device_t *dev ) +static void i830_cp_performance_boxes(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; /* Purple box for page flipping */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP ) - i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP) + i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255); /* Red box if we have to wait for idle at any point */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT ) - i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT) + i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0); /* Blue box: lost context? */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT ) - i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT) + i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255); /* Yellow box for texture swaps */ - if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD ) - i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 ); + if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD) + i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0); /* Green box if hardware never idles (as far as we can tell) */ - if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) ) - i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 ); - + if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY)) + i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0); - /* Draw bars indicating number of buffers allocated + /* Draw bars indicating number of buffers allocated * (not a great measure, easily confused) */ if (dev_priv->dma_used) { int bar = dev_priv->dma_used / 10240; - if (bar > 100) bar = 100; - if (bar < 1) bar = 1; - i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 ); + if (bar > 100) + bar = 100; + if (bar < 1) + bar = 1; + i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128); dev_priv->dma_used = 0; } dev_priv->sarea_priv->perf_boxes = 0; } -static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, +static void i830_dma_dispatch_clear(drm_device_t * dev, int flags, unsigned int clear_color, unsigned int clear_zval, unsigned int clear_depthmask) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -896,90 +885,90 @@ static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, unsigned int BR13, CMD, D_CMD; RING_LOCALS; - - if ( dev_priv->current_page == 1 ) { + if (dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(I830_FRONT | I830_BACK); - if ( tmp & I830_FRONT ) flags |= I830_BACK; - if ( tmp & I830_BACK ) flags |= I830_FRONT; + if (tmp & I830_FRONT) + flags |= I830_BACK; + if (tmp & I830_BACK) + flags |= I830_FRONT; } - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - switch(cpp) { - case 2: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + switch (cpp) { + case 2: + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; case 4: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25); + CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB); D_CMD = XY_COLOR_BLT_CMD; - if(clear_depthmask & 0x00ffffff) + if (clear_depthmask & 0x00ffffff) D_CMD |= XY_COLOR_BLT_WRITE_RGB; - if(clear_depthmask & 0xff000000) + if (clear_depthmask & 0xff000000) D_CMD |= XY_COLOR_BLT_WRITE_ALPHA; break; default: - BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24); + BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24); D_CMD = CMD = XY_COLOR_BLT_CMD; break; } - if (nbox > I830_NR_SAREA_CLIPRECTS) - nbox = I830_NR_SAREA_CLIPRECTS; + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; - for (i = 0 ; i < nbox ; i++, pbox++) { + for (i = 0; i < nbox; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - if ( flags & I830_FRONT ) { - DRM_DEBUG("clear front\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->front_offset ); - OUT_RING( clear_color ); + if (flags & I830_FRONT) { + DRM_DEBUG("clear front\n"); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->front_offset); + OUT_RING(clear_color); ADVANCE_LP_RING(); } - if ( flags & I830_BACK ) { + if (flags & I830_BACK) { DRM_DEBUG("clear back\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->back_offset ); - OUT_RING( clear_color ); + BEGIN_LP_RING(6); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->back_offset); + OUT_RING(clear_color); ADVANCE_LP_RING(); } - if ( flags & I830_DEPTH ) { + if (flags & I830_DEPTH) { DRM_DEBUG("clear depth\n"); - BEGIN_LP_RING( 6 ); - OUT_RING( D_CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); - OUT_RING( dev_priv->depth_offset ); - OUT_RING( clear_zval ); + BEGIN_LP_RING(6); + OUT_RING(D_CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); + OUT_RING(dev_priv->depth_offset); + OUT_RING(clear_zval); ADVANCE_LP_RING(); } } } -static void i830_dma_dispatch_swap( drm_device_t *dev ) +static void i830_dma_dispatch_swap(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; int pitch = dev_priv->pitch; @@ -990,202 +979,192 @@ static void i830_dma_dispatch_swap( drm_device_t *dev ) DRM_DEBUG("swapbuffers\n"); - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); if (dev_priv->do_boxes) - i830_cp_performance_boxes( dev ); + i830_cp_performance_boxes(dev); - switch(cpp) { - case 2: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + switch (cpp) { + case 2: + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24); CMD = XY_SRC_COPY_BLT_CMD; break; case 4: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25); + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB); break; default: - BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24); + BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24); CMD = XY_SRC_COPY_BLT_CMD; break; } + if (nbox > I830_NR_SAREA_CLIPRECTS) + nbox = I830_NR_SAREA_CLIPRECTS; - if (nbox > I830_NR_SAREA_CLIPRECTS) - nbox = I830_NR_SAREA_CLIPRECTS; - - for (i = 0 ; i < nbox; i++, pbox++) - { + for (i = 0; i < nbox; i++, pbox++) { if (pbox->x1 > pbox->x2 || pbox->y1 > pbox->y2 || - pbox->x2 > dev_priv->w || - pbox->y2 > dev_priv->h) + pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) continue; - + DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n", - pbox->x1, pbox->y1, - pbox->x2, pbox->y2); + pbox->x1, pbox->y1, pbox->x2, pbox->y2); - BEGIN_LP_RING( 8 ); - OUT_RING( CMD ); - OUT_RING( BR13 ); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( (pbox->y2 << 16) | pbox->x2 ); + BEGIN_LP_RING(8); + OUT_RING(CMD); + OUT_RING(BR13); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING((pbox->y2 << 16) | pbox->x2); - if (dev_priv->current_page == 0) - OUT_RING( dev_priv->front_offset ); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->front_offset); else - OUT_RING( dev_priv->back_offset ); + OUT_RING(dev_priv->back_offset); - OUT_RING( (pbox->y1 << 16) | pbox->x1 ); - OUT_RING( BR13 & 0xffff ); + OUT_RING((pbox->y1 << 16) | pbox->x1); + OUT_RING(BR13 & 0xffff); - if (dev_priv->current_page == 0) - OUT_RING( dev_priv->back_offset ); + if (dev_priv->current_page == 0) + OUT_RING(dev_priv->back_offset); else - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); ADVANCE_LP_RING(); } } -static void i830_dma_dispatch_flip( drm_device_t *dev ) +static void i830_dma_dispatch_flip(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pf_current_page); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, + dev_priv->sarea_priv->pf_current_page); - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); if (dev_priv->do_boxes) { dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP; - i830_cp_performance_boxes( dev ); + i830_cp_performance_boxes(dev); } - - BEGIN_LP_RING( 2 ); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(0); ADVANCE_LP_RING(); - BEGIN_LP_RING( 6 ); - OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP ); - OUT_RING( 0 ); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + BEGIN_LP_RING(6); + OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP); + OUT_RING(0); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); dev_priv->current_page = 1; } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); dev_priv->current_page = 0; } OUT_RING(0); ADVANCE_LP_RING(); - - BEGIN_LP_RING( 2 ); - OUT_RING( MI_WAIT_FOR_EVENT | - MI_WAIT_FOR_PLANE_A_FLIP ); - OUT_RING( 0 ); + BEGIN_LP_RING(2); + OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP); + OUT_RING(0); ADVANCE_LP_RING(); - dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -static void i830_dma_dispatch_vertex(drm_device_t *dev, - drm_buf_t *buf, - int discard, - int used) +static void i830_dma_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, int discard, int used) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_buf_priv_t *buf_priv = buf->dev_private; - drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; - drm_clip_rect_t *box = sarea_priv->boxes; - int nbox = sarea_priv->nbox; + drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; + drm_clip_rect_t *box = sarea_priv->boxes; + int nbox = sarea_priv->nbox; unsigned long address = (unsigned long)buf->bus_address; - unsigned long start = address - dev->agp->base; + unsigned long start = address - dev->agp->base; int i = 0, u; - RING_LOCALS; + RING_LOCALS; - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - if (nbox > I830_NR_SAREA_CLIPRECTS) + if (nbox > I830_NR_SAREA_CLIPRECTS) nbox = I830_NR_SAREA_CLIPRECTS; if (discard) { - u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_HARDWARE); - if(u != I830_BUF_CLIENT) { + if (u != I830_BUF_CLIENT) { DRM_DEBUG("xxxx 2\n"); } } - if (used > 4*1023) + if (used > 4 * 1023) used = 0; if (sarea_priv->dirty) - i830EmitState( dev ); + i830EmitState(dev); - DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", + DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", address, used, nbox); - dev_priv->counter++; - DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter); - DRM_DEBUG( "i830_dma_dispatch\n"); - DRM_DEBUG( "start : %lx\n", start); - DRM_DEBUG( "used : %d\n", used); - DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4); + dev_priv->counter++; + DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); + DRM_DEBUG("i830_dma_dispatch\n"); + DRM_DEBUG("start : %lx\n", start); + DRM_DEBUG("used : %d\n", used); + DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4); if (buf_priv->currently_mapped == I830_BUF_MAPPED) { u32 *vp = buf_priv->kernel_virtual; vp[0] = (GFX_OP_PRIMITIVE | - sarea_priv->vertex_prim | - ((used/4)-2)); + sarea_priv->vertex_prim | ((used / 4) - 2)); if (dev_priv->use_mi_batchbuffer_start) { - vp[used/4] = MI_BATCH_BUFFER_END; - used += 4; + vp[used / 4] = MI_BATCH_BUFFER_END; + used += 4; } - + if (used & 4) { - vp[used/4] = 0; + vp[used / 4] = 0; used += 4; } i830_unmap_buffer(buf); } - + if (used) { do { if (i < nbox) { BEGIN_LP_RING(6); - OUT_RING( GFX_OP_DRAWRECT_INFO ); - OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] ); - OUT_RING( box[i].x1 | (box[i].y1<<16) ); - OUT_RING( box[i].x2 | (box[i].y2<<16) ); - OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] ); - OUT_RING( 0 ); + OUT_RING(GFX_OP_DRAWRECT_INFO); + OUT_RING(sarea_priv-> + BufferState[I830_DESTREG_DR1]); + OUT_RING(box[i].x1 | (box[i].y1 << 16)); + OUT_RING(box[i].x2 | (box[i].y2 << 16)); + OUT_RING(sarea_priv-> + BufferState[I830_DESTREG_DR4]); + OUT_RING(0); ADVANCE_LP_RING(); } if (dev_priv->use_mi_batchbuffer_start) { BEGIN_LP_RING(2); - OUT_RING( MI_BATCH_BUFFER_START | (2<<6) ); - OUT_RING( start | MI_BATCH_NON_SECURE ); + OUT_RING(MI_BATCH_BUFFER_START | (2 << 6)); + OUT_RING(start | MI_BATCH_NON_SECURE); ADVANCE_LP_RING(); - } - else { + } else { BEGIN_LP_RING(4); - OUT_RING( MI_BATCH_BUFFER ); - OUT_RING( start | MI_BATCH_NON_SECURE ); - OUT_RING( start + used - 4 ); - OUT_RING( 0 ); + OUT_RING(MI_BATCH_BUFFER); + OUT_RING(start | MI_BATCH_NON_SECURE); + OUT_RING(start + used - 4); + OUT_RING(0); ADVANCE_LP_RING(); } @@ -1195,61 +1174,60 @@ static void i830_dma_dispatch_vertex(drm_device_t *dev, if (discard) { dev_priv->counter++; - (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, - I830_BUF_HARDWARE); + (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + I830_BUF_HARDWARE); BEGIN_LP_RING(8); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( 20 ); - OUT_RING( dev_priv->counter ); - OUT_RING( CMD_STORE_DWORD_IDX ); - OUT_RING( buf_priv->my_use_idx ); - OUT_RING( I830_BUF_FREE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(20); + OUT_RING(dev_priv->counter); + OUT_RING(CMD_STORE_DWORD_IDX); + OUT_RING(buf_priv->my_use_idx); + OUT_RING(I830_BUF_FREE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); ADVANCE_LP_RING(); } } - -static void i830_dma_quiescent(drm_device_t *dev) +static void i830_dma_quiescent(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; - RING_LOCALS; + drm_i830_private_t *dev_priv = dev->dev_private; + RING_LOCALS; - i830_kernel_lost_context(dev); + i830_kernel_lost_context(dev); - BEGIN_LP_RING(4); - OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE ); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(4); + OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + OUT_RING(0); + ADVANCE_LP_RING(); - i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); + i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); } -static int i830_flush_queue(drm_device_t *dev) +static int i830_flush_queue(drm_device_t * dev) { - drm_i830_private_t *dev_priv = dev->dev_private; + drm_i830_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; - int i, ret = 0; - RING_LOCALS; - - i830_kernel_lost_context(dev); - - BEGIN_LP_RING(2); - OUT_RING( CMD_REPORT_HEAD ); - OUT_RING( 0 ); - ADVANCE_LP_RING(); - - i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ ); - - for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - - int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, + int i, ret = 0; + RING_LOCALS; + + i830_kernel_lost_context(dev); + + BEGIN_LP_RING(2); + OUT_RING(CMD_REPORT_HEAD); + OUT_RING(0); + ADVANCE_LP_RING(); + + i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__); + + for (i = 0; i < dma->buf_count; i++) { + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + + int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, I830_BUF_FREE); if (used == I830_BUF_HARDWARE) @@ -1258,62 +1236,66 @@ static int i830_flush_queue(drm_device_t *dev) DRM_DEBUG("still on client\n"); } - return ret; + return ret; } /* Must be called with the lock held */ -void i830_reclaim_buffers(drm_device_t *dev, struct file *filp) +void i830_reclaim_buffers(drm_device_t * dev, struct file *filp) { drm_device_dma_t *dma = dev->dma; - int i; + int i; - if (!dma) return; - if (!dev->dev_private) return; - if (!dma->buflist) return; + if (!dma) + return; + if (!dev->dev_private) + return; + if (!dma->buflist) + return; - i830_flush_queue(dev); + i830_flush_queue(dev); for (i = 0; i < dma->buf_count; i++) { - drm_buf_t *buf = dma->buflist[ i ]; - drm_i830_buf_priv_t *buf_priv = buf->dev_private; - + drm_buf_t *buf = dma->buflist[i]; + drm_i830_buf_priv_t *buf_priv = buf->dev_private; + if (buf->filp == filp && buf_priv) { - int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, + int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE); if (used == I830_BUF_CLIENT) DRM_DEBUG("reclaimed from client\n"); - if(buf_priv->currently_mapped == I830_BUF_MAPPED) - buf_priv->currently_mapped = I830_BUF_UNMAPPED; + if (buf_priv->currently_mapped == I830_BUF_MAPPED) + buf_priv->currently_mapped = I830_BUF_UNMAPPED; } } } -static int i830_flush_ioctl(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) +static int i830_flush_ioctl(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; LOCK_TEST_WITH_RETURN(dev, filp); - i830_flush_queue(dev); - return 0; + i830_flush_queue(dev); + return 0; } static int i830_dma_vertex(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; drm_device_dma_t *dma = dev->dma; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; drm_i830_vertex_t vertex; - if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex))) + if (copy_from_user + (&vertex, (drm_i830_vertex_t __user *) arg, sizeof(vertex))) return -EFAULT; LOCK_TEST_WITH_RETURN(dev, filp); @@ -1321,15 +1303,16 @@ static int i830_dma_vertex(struct inode *inode, struct file *filp, DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n", vertex.idx, vertex.used, vertex.discard); - if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL; + if (vertex.idx < 0 || vertex.idx > dma->buf_count) + return -EINVAL; - i830_dma_dispatch_vertex( dev, - dma->buflist[ vertex.idx ], - vertex.discard, vertex.used ); + i830_dma_dispatch_vertex(dev, + dma->buflist[vertex.idx], + vertex.discard, vertex.used); + + sarea_priv->last_enqueue = dev_priv->counter - 1; + sarea_priv->last_dispatch = (int)hw_status[5]; - sarea_priv->last_enqueue = dev_priv->counter-1; - sarea_priv->last_dispatch = (int) hw_status[5]; - return 0; } @@ -1340,9 +1323,10 @@ static int i830_clear_bufs(struct inode *inode, struct file *filp, drm_device_t *dev = priv->head->dev; drm_i830_clear_t clear; - if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear))) + if (copy_from_user + (&clear, (drm_i830_clear_t __user *) arg, sizeof(clear))) return -EFAULT; - + LOCK_TEST_WITH_RETURN(dev, filp); /* GH: Someone's doing nasty things... */ @@ -1350,11 +1334,10 @@ static int i830_clear_bufs(struct inode *inode, struct file *filp, return -EINVAL; } - i830_dma_dispatch_clear( dev, clear.flags, - clear.clear_color, - clear.clear_depth, - clear.clear_depthmask); - return 0; + i830_dma_dispatch_clear(dev, clear.flags, + clear.clear_color, + clear.clear_depth, clear.clear_depthmask); + return 0; } static int i830_swap_bufs(struct inode *inode, struct file *filp, @@ -1362,20 +1345,18 @@ static int i830_swap_bufs(struct inode *inode, struct file *filp, { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; - + DRM_DEBUG("i830_swap_bufs\n"); LOCK_TEST_WITH_RETURN(dev, filp); - i830_dma_dispatch_swap( dev ); - return 0; + i830_dma_dispatch_swap(dev); + return 0; } - - /* Not sure why this isn't set all the time: - */ -static void i830_do_init_pageflip( drm_device_t *dev ) + */ +static void i830_do_init_pageflip(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; @@ -1385,20 +1366,20 @@ static void i830_do_init_pageflip( drm_device_t *dev ) dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; } -static int i830_do_cleanup_pageflip( drm_device_t *dev ) +static int i830_do_cleanup_pageflip(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; DRM_DEBUG("%s\n", __FUNCTION__); if (dev_priv->current_page != 0) - i830_dma_dispatch_flip( dev ); + i830_dma_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; } static int i830_flip_bufs(struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg) + unsigned int cmd, unsigned long arg) { drm_file_t *priv = filp->private_data; drm_device_t *dev = priv->head->dev; @@ -1408,45 +1389,45 @@ static int i830_flip_bufs(struct inode *inode, struct file *filp, LOCK_TEST_WITH_RETURN(dev, filp); - if (!dev_priv->page_flipping) - i830_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + i830_do_init_pageflip(dev); - i830_dma_dispatch_flip( dev ); - return 0; + i830_dma_dispatch_flip(dev); + return 0; } static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; - - sarea_priv->last_dispatch = (int) hw_status[5]; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; + + sarea_priv->last_dispatch = (int)hw_status[5]; return 0; } static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; - int retcode = 0; - drm_i830_dma_t d; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u32 *hw_status = dev_priv->hw_status_page; - drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) - dev_priv->sarea_priv; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; + int retcode = 0; + drm_i830_dma_t d; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u32 *hw_status = dev_priv->hw_status_page; + drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) + dev_priv->sarea_priv; DRM_DEBUG("getbuf\n"); - if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d))) + if (copy_from_user(&d, (drm_i830_dma_t __user *) arg, sizeof(d))) return -EFAULT; - + LOCK_TEST_WITH_RETURN(dev, filp); - + d.granted = 0; retcode = i830_dma_get_buffer(dev, &d, filp); @@ -1454,46 +1435,45 @@ static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n", current->pid, retcode, d.granted); - if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d))) + if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) return -EFAULT; - sarea_priv->last_dispatch = (int) hw_status[5]; + sarea_priv->last_dispatch = (int)hw_status[5]; return retcode; } static int i830_copybuf(struct inode *inode, - struct file *filp, unsigned int cmd, unsigned long arg) + struct file *filp, unsigned int cmd, unsigned long arg) { /* Never copy - 2.4.x doesn't need it */ return 0; } static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg) + unsigned long arg) { return 0; } - - -static int i830_getparam( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +static int i830_getparam(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user(¶m, (drm_i830_getparam_t __user *)arg, sizeof(param) )) + if (copy_from_user + (¶m, (drm_i830_getparam_t __user *) arg, sizeof(param))) return -EFAULT; - switch( param.param ) { + switch (param.param) { case I830_PARAM_IRQ_ACTIVE: value = dev->irq_enabled; break; @@ -1501,32 +1481,32 @@ static int i830_getparam( struct inode *inode, struct file *filp, return -EINVAL; } - if ( copy_to_user( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (copy_to_user(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return -EFAULT; } - + return 0; } - -static int i830_setparam( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ) +static int i830_setparam(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_setparam_t param; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user(¶m, (drm_i830_setparam_t __user *)arg, sizeof(param) )) + if (copy_from_user + (¶m, (drm_i830_setparam_t __user *) arg, sizeof(param))) return -EFAULT; - switch( param.param ) { + switch (param.param) { case I830_SETPARAM_USE_MI_BATCHBUFFER_START: dev_priv->use_mi_batchbuffer_start = param.value; break; @@ -1537,13 +1517,12 @@ static int i830_setparam( struct inode *inode, struct file *filp, return 0; } - -void i830_driver_pretakedown(drm_device_t *dev) +void i830_driver_pretakedown(drm_device_t * dev) { - i830_dma_cleanup( dev ); + i830_dma_cleanup(dev); } -void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp) { if (dev->dev_private) { drm_i830_private_t *dev_priv = dev->dev_private; @@ -1553,32 +1532,45 @@ void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp) } } -void i830_driver_release(drm_device_t *dev, struct file *filp) +void i830_driver_release(drm_device_t * dev, struct file *filp) { i830_reclaim_buffers(dev, filp); } -int i830_driver_dma_quiescent(drm_device_t *dev) +int i830_driver_dma_quiescent(drm_device_t * dev) { - i830_dma_quiescent( dev ); + i830_dma_quiescent(dev); return 0; } drm_ioctl_desc_t i830_ioctls[] = { - [DRM_IOCTL_NR(DRM_I830_INIT)] = { i830_dma_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_I830_VERTEX)] = { i830_dma_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_CLEAR)] = { i830_clear_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_FLUSH)] = { i830_flush_ioctl, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETAGE)] = { i830_getage, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETBUF)] = { i830_getbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_SWAP)] = { i830_swap_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_COPY)] = { i830_copybuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = { i830_docopy, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_FLIP)] = { i830_flip_bufs, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = { i830_irq_emit, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = { i830_irq_wait, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = { i830_getparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = { i830_setparam, 1, 0 } + [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0} + , + [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, 1, 0} }; int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls); diff --git a/drivers/char/drm/i830_drm.h b/drivers/char/drm/i830_drm.h index 03382c0beee..66dd7502796 100644 --- a/drivers/char/drm/i830_drm.h +++ b/drivers/char/drm/i830_drm.h @@ -33,14 +33,14 @@ #define I830_UPLOAD_CTX 0x1 #define I830_UPLOAD_BUFFERS 0x2 #define I830_UPLOAD_CLIPRECTS 0x4 -#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ -#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ -#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ -#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ -#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ -#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ -#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ -#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ +#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */ +#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */ +#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */ +#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */ +#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */ +#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */ +#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */ +#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */ #define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2)) #define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2)) #define I830_UPLOAD_TEXIMAGE_MASK 0xff00 @@ -65,7 +65,7 @@ * or in a piecewise fashion as required. */ -/* Destbuffer state +/* Destbuffer state * - backbuffer linear offset and pitch -- invarient in the current dri * - zbuffer linear offset and pitch -- also invarient * - drawing origin in back and depth buffers. @@ -103,7 +103,7 @@ #define I830_CTXREG_AA 9 #define I830_CTXREG_FOGCOLOR 10 #define I830_CTXREG_BLENDCOLR0 11 -#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ +#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */ #define I830_CTXREG_VF 13 #define I830_CTXREG_VF2 14 #define I830_CTXREG_MCSB0 15 @@ -111,12 +111,11 @@ #define I830_CTX_SETUP_SIZE 17 /* 1.3: Stipple state - */ + */ #define I830_STPREG_ST0 0 #define I830_STPREG_ST1 1 #define I830_STP_SETUP_SIZE 2 - /* Texture state (per tex unit) */ @@ -132,23 +131,23 @@ #define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */ #define I830_TEX_SETUP_SIZE 10 -#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ +#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */ #define I830_TEXREG_TM0S0 1 #define I830_TEXREG_TM0S1 2 #define I830_TEXREG_TM0S2 3 #define I830_TEXREG_TM0S3 4 #define I830_TEXREG_TM0S4 5 -#define I830_TEXREG_NOP0 6 /* noop */ -#define I830_TEXREG_NOP1 7 /* noop */ -#define I830_TEXREG_NOP2 8 /* noop */ -#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ +#define I830_TEXREG_NOP0 6 /* noop */ +#define I830_TEXREG_NOP1 7 /* noop */ +#define I830_TEXREG_NOP2 8 /* noop */ +#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */ #define __I830_TEX_SETUP_SIZE 10 #define I830_FRONT 0x1 #define I830_BACK 0x2 #define I830_DEPTH 0x4 -#endif /* _I830_DEFINES_ */ +#endif /* _I830_DEFINES_ */ typedef struct _drm_i830_init { enum { @@ -177,19 +176,19 @@ typedef struct _drm_i830_init { * structure as well */ typedef struct _drm_i830_tex_region { - unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char next, prev; /* indices to form a circular LRU */ unsigned char in_use; /* owned by a client, or free? */ int age; /* tracked by clients to update local LRU's */ } drm_i830_tex_region_t; typedef struct _drm_i830_sarea { unsigned int ContextState[I830_CTX_SETUP_SIZE]; - unsigned int BufferState[I830_DEST_SETUP_SIZE]; + unsigned int BufferState[I830_DEST_SETUP_SIZE]; unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE]; unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE]; unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT]; unsigned int Palette[2][256]; - unsigned int dirty; + unsigned int dirty; unsigned int nbox; drm_clip_rect_t boxes[I830_NR_SAREA_CLIPRECTS]; @@ -207,26 +206,26 @@ typedef struct _drm_i830_sarea { * texture space, and can make informed decisions as to which * areas to kick out. There is no need to choose whether to * kick out your own texture or someone else's - simply eject - * them all in LRU order. + * them all in LRU order. */ - drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS+1]; - /* Last elt is sentinal */ - int texAge; /* last time texture was uploaded */ - int last_enqueue; /* last time a buffer was enqueued */ + drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1]; + /* Last elt is sentinal */ + int texAge; /* last time texture was uploaded */ + int last_enqueue; /* last time a buffer was enqueued */ int last_dispatch; /* age of the most recently dispatched buffer */ - int last_quiescent; /* */ + int last_quiescent; /* */ int ctxOwner; /* last context to upload state */ int vertex_prim; - int pf_enabled; /* is pageflipping allowed? */ - int pf_active; - int pf_current_page; /* which buffer is being displayed? */ + int pf_enabled; /* is pageflipping allowed? */ + int pf_active; + int pf_current_page; /* which buffer is being displayed? */ + + int perf_boxes; /* performance boxes to be displayed */ - int perf_boxes; /* performance boxes to be displayed */ - - /* Here's the state for texunits 2,3: + /* Here's the state for texunits 2,3: */ unsigned int TexState2[I830_TEX_SETUP_SIZE]; unsigned int TexBlendState2[I830_TEXBLEND_SIZE]; @@ -241,12 +240,11 @@ typedef struct _drm_i830_sarea { /* Flags for perf_boxes */ -#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ -#define I830_BOX_FLIP 0x2 /* populated by kernel */ -#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ -#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ -#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ - +#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */ +#define I830_BOX_FLIP 0x2 /* populated by kernel */ +#define I830_BOX_WAIT 0x4 /* populated by kernel & client */ +#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */ +#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */ /* I830 specific ioctls * The device specific ioctl range is 0x40 to 0x79. @@ -289,23 +287,21 @@ typedef struct _drm_i830_clear { unsigned int clear_depthmask; } drm_i830_clear_t; - - /* These may be placeholders if we have more cliprects than * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to * false, indicating that the buffer will be dispatched again with a * new set of cliprects. */ typedef struct _drm_i830_vertex { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ int discard; /* client is finished with the buffer? */ } drm_i830_vertex_t; typedef struct _drm_i830_copy_t { - int idx; /* buffer index */ + int idx; /* buffer index */ int used; /* nr bytes in use */ - void __user *address; /* Address to copy from */ + void __user *address; /* Address to copy from */ } drm_i830_copy_t; typedef struct drm_i830_dma { @@ -315,7 +311,6 @@ typedef struct drm_i830_dma { int granted; } drm_i830_dma_t; - /* 1.3: Userspace can request & wait on irq's: */ typedef struct drm_i830_irq_emit { @@ -326,7 +321,6 @@ typedef struct drm_i830_irq_wait { int irq_seq; } drm_i830_irq_wait_t; - /* 1.3: New ioctl to query kernel params: */ #define I830_PARAM_IRQ_ACTIVE 1 @@ -336,7 +330,6 @@ typedef struct drm_i830_getparam { int __user *value; } drm_i830_getparam_t; - /* 1.3: New ioctl to set kernel params: */ #define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1 @@ -346,5 +339,4 @@ typedef struct drm_i830_setparam { int value; } drm_i830_setparam_t; - -#endif /* _I830_DRM_H_ */ +#endif /* _I830_DRM_H_ */ diff --git a/drivers/char/drm/i830_drv.c b/drivers/char/drm/i830_drv.c index 0da9cd19919..6dad356450b 100644 --- a/drivers/char/drm/i830_drv.c +++ b/drivers/char/drm/i830_drv.c @@ -40,36 +40,34 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -81,7 +79,9 @@ extern drm_ioctl_desc_t i830_ioctls[]; extern int i830_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE, #if USE_IRQS .driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ, #endif @@ -104,18 +104,19 @@ static struct drm_driver driver = { .version = version, .ioctls = i830_ioctls, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + } + , .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; @@ -133,6 +134,6 @@ static void __exit i830_exit(void) module_init(i830_init); module_exit(i830_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h index 63f96a8b6a4..99835465c44 100644 --- a/drivers/char/drm/i830_drv.h +++ b/drivers/char/drm/i830_drv.h @@ -11,11 +11,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -63,14 +63,14 @@ #define USE_IRQS 0 typedef struct drm_i830_buf_priv { - u32 *in_use; - int my_use_idx; + u32 *in_use; + int my_use_idx; int currently_mapped; void __user *virtual; void *kernel_virtual; } drm_i830_buf_priv_t; -typedef struct _drm_i830_ring_buffer{ +typedef struct _drm_i830_ring_buffer { int tail_mask; unsigned long Start; unsigned long End; @@ -86,17 +86,17 @@ typedef struct drm_i830_private { drm_map_t *mmio_map; drm_i830_sarea_t *sarea_priv; - drm_i830_ring_buffer_t ring; + drm_i830_ring_buffer_t ring; - void * hw_status_page; - unsigned long counter; + void *hw_status_page; + unsigned long counter; dma_addr_t dma_status_page; drm_buf_t *mmap_buffer; - + u32 front_di1, back_di1, zi1; - + int back_offset; int depth_offset; int front_offset; @@ -113,30 +113,30 @@ typedef struct drm_i830_private { int page_flipping; wait_queue_head_t irq_queue; - atomic_t irq_received; - atomic_t irq_emitted; + atomic_t irq_received; + atomic_t irq_emitted; int use_mi_batchbuffer_start; } drm_i830_private_t; /* i830_dma.c */ -extern void i830_reclaim_buffers(drm_device_t *dev, struct file *filp); +extern void i830_reclaim_buffers(drm_device_t * dev, struct file *filp); /* i830_irq.c */ -extern int i830_irq_emit( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); -extern int i830_irq_wait( struct inode *inode, struct file *filp, - unsigned int cmd, unsigned long arg ); - -extern irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ); -extern void i830_driver_irq_preinstall( drm_device_t *dev ); -extern void i830_driver_irq_postinstall( drm_device_t *dev ); -extern void i830_driver_irq_uninstall( drm_device_t *dev ); -extern void i830_driver_pretakedown(drm_device_t *dev); -extern void i830_driver_release(drm_device_t *dev, struct file *filp); -extern int i830_driver_dma_quiescent(drm_device_t *dev); -extern void i830_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern int i830_irq_emit(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); +extern int i830_irq_wait(struct inode *inode, struct file *filp, + unsigned int cmd, unsigned long arg); + +extern irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS); +extern void i830_driver_irq_preinstall(drm_device_t * dev); +extern void i830_driver_irq_postinstall(drm_device_t * dev); +extern void i830_driver_irq_uninstall(drm_device_t * dev); +extern void i830_driver_pretakedown(drm_device_t * dev); +extern void i830_driver_release(drm_device_t * dev, struct file *filp); +extern int i830_driver_dma_quiescent(drm_device_t * dev); +extern void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp); extern int i830_driver_device_is_agp(drm_device_t * dev); #define I830_BASE(reg) ((unsigned long) \ @@ -149,8 +149,6 @@ extern int i830_driver_device_is_agp(drm_device_t * dev); #define I830_READ16(reg) I830_DEREF16(reg) #define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) - - #define I830_VERBOSE 0 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ @@ -168,7 +166,6 @@ extern int i830_driver_device_is_agp(drm_device_t * dev); virt = dev_priv->ring.virtual_start; \ } while (0) - #define OUT_RING(n) do { \ if (I830_VERBOSE) printk(" OUT_RING %x\n", (int)(n)); \ *(volatile unsigned int *)(virt + outring) = n; \ @@ -184,8 +181,7 @@ extern int i830_driver_device_is_agp(drm_device_t * dev); I830_WRITE(LP_RING + RING_TAIL, outring); \ } while(0) -extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); - +extern int i830_wait_ring(drm_device_t * dev, int n, const char *caller); #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) @@ -200,7 +196,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define INST_OP_FLUSH 0x02000000 #define INST_FLUSH_MAP_CACHE 0x00000001 - #define BB1_START_ADDR_MASK (~0x7) #define BB1_PROTECTED (1<<0) #define BB1_UNPROTECTED (0<<0) @@ -213,7 +208,6 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define I830_IRQ_RESERVED ((1<<13)|(3<<2)) - #define LP_RING 0x2030 #define HP_RING 0x2040 #define RING_TAIL 0x00 @@ -225,7 +219,7 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define RING_START 0x08 #define START_ADDR 0x0xFFFFF000 #define RING_LEN 0x0C -#define RING_NR_PAGES 0x001FF000 +#define RING_NR_PAGES 0x001FF000 #define RING_REPORT_MASK 0x00000006 #define RING_REPORT_64K 0x00000002 #define RING_REPORT_128K 0x00000004 @@ -291,10 +285,9 @@ extern int i830_wait_ring(drm_device_t *dev, int n, const char *caller); #define MI_BATCH_NON_SECURE (1) #define MI_WAIT_FOR_EVENT ((0x3<<23)) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) +#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) #endif - diff --git a/drivers/char/drm/i830_irq.c b/drivers/char/drm/i830_irq.c index a5923e5d0a7..5841f767495 100644 --- a/drivers/char/drm/i830_irq.c +++ b/drivers/char/drm/i830_irq.c @@ -9,11 +9,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -33,28 +33,27 @@ #include /* For task queue support */ #include - -irqreturn_t i830_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t i830_driver_irq_handler(DRM_IRQ_ARGS) { - drm_device_t *dev = (drm_device_t *)arg; - drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private; - u16 temp; + drm_device_t *dev = (drm_device_t *) arg; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; + u16 temp; - temp = I830_READ16(I830REG_INT_IDENTITY_R); + temp = I830_READ16(I830REG_INT_IDENTITY_R); DRM_DEBUG("%x\n", temp); - if ( !( temp & 2 ) ) + if (!(temp & 2)) return IRQ_NONE; - I830_WRITE16(I830REG_INT_IDENTITY_R, temp); + I830_WRITE16(I830REG_INT_IDENTITY_R, temp); atomic_inc(&dev_priv->irq_received); - wake_up_interruptible(&dev_priv->irq_queue); + wake_up_interruptible(&dev_priv->irq_queue); return IRQ_HANDLED; } -static int i830_emit_irq(drm_device_t *dev) +static int i830_emit_irq(drm_device_t * dev) { drm_i830_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -63,27 +62,25 @@ static int i830_emit_irq(drm_device_t *dev) atomic_inc(&dev_priv->irq_emitted); - BEGIN_LP_RING(2); - OUT_RING( 0 ); - OUT_RING( GFX_OP_USER_INTERRUPT ); - ADVANCE_LP_RING(); + BEGIN_LP_RING(2); + OUT_RING(0); + OUT_RING(GFX_OP_USER_INTERRUPT); + ADVANCE_LP_RING(); return atomic_read(&dev_priv->irq_emitted); } - -static int i830_wait_irq(drm_device_t *dev, int irq_nr) +static int i830_wait_irq(drm_device_t * dev, int irq_nr) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; DECLARE_WAITQUEUE(entry, current); - unsigned long end = jiffies + HZ*3; + unsigned long end = jiffies + HZ * 3; int ret = 0; DRM_DEBUG("%s\n", __FUNCTION__); - if (atomic_read(&dev_priv->irq_received) >= irq_nr) - return 0; + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + return 0; dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; @@ -91,21 +88,21 @@ static int i830_wait_irq(drm_device_t *dev, int irq_nr) for (;;) { __set_current_state(TASK_INTERRUPTIBLE); - if (atomic_read(&dev_priv->irq_received) >= irq_nr) - break; - if((signed)(end - jiffies) <= 0) { + if (atomic_read(&dev_priv->irq_received) >= irq_nr) + break; + if ((signed)(end - jiffies) <= 0) { DRM_ERROR("timeout iir %x imr %x ier %x hwstam %x\n", - I830_READ16( I830REG_INT_IDENTITY_R ), - I830_READ16( I830REG_INT_MASK_R ), - I830_READ16( I830REG_INT_ENABLE_R ), - I830_READ16( I830REG_HWSTAM )); + I830_READ16(I830REG_INT_IDENTITY_R), + I830_READ16(I830REG_INT_MASK_R), + I830_READ16(I830REG_INT_ENABLE_R), + I830_READ16(I830REG_HWSTAM)); - ret = -EBUSY; /* Lockup? Missed irq? */ + ret = -EBUSY; /* Lockup? Missed irq? */ break; } - schedule_timeout(HZ*3); - if (signal_pending(current)) { - ret = -EINTR; + schedule_timeout(HZ * 3); + if (signal_pending(current)) { + ret = -EINTR; break; } } @@ -115,89 +112,87 @@ static int i830_wait_irq(drm_device_t *dev, int irq_nr) return ret; } - /* Needs the lock as it touches the ring. */ -int i830_irq_emit( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_irq_emit(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_irq_emit_t emit; int result; LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user( &emit, (drm_i830_irq_emit_t __user *)arg, sizeof(emit) )) + if (copy_from_user + (&emit, (drm_i830_irq_emit_t __user *) arg, sizeof(emit))) return -EFAULT; - result = i830_emit_irq( dev ); + result = i830_emit_irq(dev); - if ( copy_to_user( emit.irq_seq, &result, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (copy_to_user(emit.irq_seq, &result, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return -EFAULT; } return 0; } - /* Doesn't need the hardware lock. */ -int i830_irq_wait( struct inode *inode, struct file *filp, unsigned int cmd, - unsigned long arg ) +int i830_irq_wait(struct inode *inode, struct file *filp, unsigned int cmd, + unsigned long arg) { - drm_file_t *priv = filp->private_data; - drm_device_t *dev = priv->head->dev; + drm_file_t *priv = filp->private_data; + drm_device_t *dev = priv->head->dev; drm_i830_private_t *dev_priv = dev->dev_private; drm_i830_irq_wait_t irqwait; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return -EINVAL; } - if (copy_from_user( &irqwait, (drm_i830_irq_wait_t __user *)arg, - sizeof(irqwait) )) + if (copy_from_user(&irqwait, (drm_i830_irq_wait_t __user *) arg, + sizeof(irqwait))) return -EFAULT; - return i830_wait_irq( dev, irqwait.irq_seq ); + return i830_wait_irq(dev, irqwait.irq_seq); } - /* drm_dma.h hooks */ -void i830_driver_irq_preinstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_preinstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; - I830_WRITE16( I830REG_HWSTAM, 0xffff ); - I830_WRITE16( I830REG_INT_MASK_R, 0x0 ); - I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); + I830_WRITE16(I830REG_HWSTAM, 0xffff); + I830_WRITE16(I830REG_INT_MASK_R, 0x0); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x0); atomic_set(&dev_priv->irq_received, 0); atomic_set(&dev_priv->irq_emitted, 0); init_waitqueue_head(&dev_priv->irq_queue); } -void i830_driver_irq_postinstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_postinstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; - I830_WRITE16( I830REG_INT_ENABLE_R, 0x2 ); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x2); } -void i830_driver_irq_uninstall( drm_device_t *dev ) { - drm_i830_private_t *dev_priv = - (drm_i830_private_t *)dev->dev_private; +void i830_driver_irq_uninstall(drm_device_t * dev) +{ + drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private; if (!dev_priv) return; - I830_WRITE16( I830REG_INT_MASK_R, 0xffff ); - I830_WRITE16( I830REG_INT_ENABLE_R, 0x0 ); + I830_WRITE16(I830REG_INT_MASK_R, 0xffff); + I830_WRITE16(I830REG_INT_ENABLE_R, 0x0); } diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c index 34f552f90c4..f0bb0bdbb6e 100644 --- a/drivers/char/drm/i915_dma.c +++ b/drivers/char/drm/i915_dma.c @@ -85,14 +85,14 @@ static int i915_dma_cleanup(drm_device_t * dev) * is freed, it's too late. */ if (dev->irq) - drm_irq_uninstall (dev); + drm_irq_uninstall(dev); if (dev->dev_private) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; if (dev_priv->ring.virtual_start) { - drm_core_ioremapfree( &dev_priv->ring.map, dev); + drm_core_ioremapfree(&dev_priv->ring.map, dev); } if (dev_priv->status_page_dmah) { @@ -101,8 +101,8 @@ static int i915_dma_cleanup(drm_device_t * dev) I915_WRITE(0x02080, 0x1ffff000); } - drm_free (dev->dev_private, sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); + drm_free(dev->dev_private, sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } @@ -146,7 +146,7 @@ static int i915_initialize(drm_device_t * dev, dev_priv->ring.map.flags = 0; dev_priv->ring.map.mtrr = 0; - drm_core_ioremap( &dev_priv->ring.map, dev ); + drm_core_ioremap(&dev_priv->ring.map, dev); if (dev_priv->ring.map.handle == NULL) { dev->dev_private = (void *)dev_priv; @@ -243,8 +243,8 @@ static int i915_dma_init(DRM_IOCTL_ARGS) switch (init.func) { case I915_INIT_DMA: - dev_priv = drm_alloc (sizeof(drm_i915_private_t), - DRM_MEM_DRIVER); + dev_priv = drm_alloc(sizeof(drm_i915_private_t), + DRM_MEM_DRIVER); if (dev_priv == NULL) return DRM_ERR(ENOMEM); retcode = i915_initialize(dev, dev_priv, &init); @@ -297,7 +297,7 @@ static int do_validate_cmd(int cmd) case 0x1c: return 1; case 0x1d: - switch ((cmd>>16)&0xff) { + switch ((cmd >> 16) & 0xff) { case 0x3: return (cmd & 0x1f) + 2; case 0x4: @@ -699,35 +699,46 @@ static int i915_setparam(DRM_IOCTL_ARGS) return 0; } -void i915_driver_pretakedown(drm_device_t *dev) +void i915_driver_pretakedown(drm_device_t * dev) { - if ( dev->dev_private ) { + if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_takedown( &(dev_priv->agp_heap) ); - } - i915_dma_cleanup( dev ); + i915_mem_takedown(&(dev_priv->agp_heap)); + } + i915_dma_cleanup(dev); } -void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp) { - if ( dev->dev_private ) { + if (dev->dev_private) { drm_i915_private_t *dev_priv = dev->dev_private; - i915_mem_release( dev, filp, dev_priv->agp_heap ); + i915_mem_release(dev, filp, dev_priv->agp_heap); } } drm_ioctl_desc_t i915_ioctls[] = { - [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}, - [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}, - [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}, - [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1} + , + [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0} + , + [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1} + , [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0} }; diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c index 106b9ec0221..665da6ac11c 100644 --- a/drivers/char/drm/i915_drv.c +++ b/drivers/char/drm/i915_drv.c @@ -34,36 +34,34 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { dev->counters += 4; dev->types[6] = _DRM_STAT_IRQ; dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; - - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -75,8 +73,9 @@ extern drm_ioctl_desc_t i915_ioctls[]; extern int i915_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | - DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, .pretakedown = i915_driver_pretakedown, .prerelease = i915_driver_prerelease, .device_is_agp = i915_driver_device_is_agp, @@ -91,21 +90,21 @@ static struct drm_driver driver = { .version = version, .ioctls = i915_ioctls, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, #ifdef CONFIG_COMPAT - .compat_ioctl = i915_compat_ioctl, + .compat_ioctl = i915_compat_ioctl, #endif - }, + }, .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init i915_init(void) @@ -122,6 +121,6 @@ static void __exit i915_exit(void) module_init(i915_init); module_exit(i915_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index 70ed4e68eac..511ef1d8763 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h @@ -101,18 +101,18 @@ typedef struct drm_i915_private { /* i915_dma.c */ extern void i915_kernel_lost_context(drm_device_t * dev); -extern void i915_driver_pretakedown(drm_device_t *dev); -extern void i915_driver_prerelease(drm_device_t *dev, DRMFILE filp); -extern int i915_driver_device_is_agp(drm_device_t *dev); +extern void i915_driver_pretakedown(drm_device_t * dev); +extern void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp); +extern int i915_driver_device_is_agp(drm_device_t * dev); /* i915_irq.c */ extern int i915_irq_emit(DRM_IOCTL_ARGS); extern int i915_irq_wait(DRM_IOCTL_ARGS); extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); -extern void i915_driver_irq_preinstall(drm_device_t *dev); -extern void i915_driver_irq_postinstall(drm_device_t *dev); -extern void i915_driver_irq_uninstall(drm_device_t *dev); +extern void i915_driver_irq_preinstall(drm_device_t * dev); +extern void i915_driver_irq_postinstall(drm_device_t * dev); +extern void i915_driver_irq_uninstall(drm_device_t * dev); /* i915_mem.c */ extern int i915_mem_alloc(DRM_IOCTL_ARGS); @@ -125,7 +125,6 @@ extern void i915_mem_release(drm_device_t * dev, extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); - #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) diff --git a/drivers/char/drm/i915_ioc32.c b/drivers/char/drm/i915_ioc32.c index fe009e1b3a3..2218a946ec8 100644 --- a/drivers/char/drm/i915_ioc32.c +++ b/drivers/char/drm/i915_ioc32.c @@ -3,7 +3,7 @@ * * 32-bit ioctl compatibility routines for the i915 DRM. * - * \author Alan Hourihane + * \author Alan Hourihane * * * Copyright (C) Paul Mackerras 2005 @@ -42,51 +42,55 @@ typedef struct _drm_i915_batchbuffer32 { int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - u32 cliprects; /* pointer to userspace cliprects */ + u32 cliprects; /* pointer to userspace cliprects */ } drm_i915_batchbuffer32_t; static int compat_i915_batchbuffer(struct file *file, unsigned int cmd, - unsigned long arg) + unsigned long arg) { drm_i915_batchbuffer32_t batchbuffer32; drm_i915_batchbuffer_t __user *batchbuffer; - - if (copy_from_user(&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32))) + + if (copy_from_user + (&batchbuffer32, (void __user *)arg, sizeof(batchbuffer32))) return -EFAULT; - + batchbuffer = compat_alloc_user_space(sizeof(*batchbuffer)); if (!access_ok(VERIFY_WRITE, batchbuffer, sizeof(*batchbuffer)) || __put_user(batchbuffer32.start, &batchbuffer->start) || __put_user(batchbuffer32.used, &batchbuffer->used) || __put_user(batchbuffer32.DR1, &batchbuffer->DR1) || __put_user(batchbuffer32.DR4, &batchbuffer->DR4) - || __put_user(batchbuffer32.num_cliprects, &batchbuffer->num_cliprects) + || __put_user(batchbuffer32.num_cliprects, + &batchbuffer->num_cliprects) || __put_user((int __user *)(unsigned long)batchbuffer32.cliprects, &batchbuffer->cliprects)) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_I915_BATCHBUFFER, (unsigned long) batchbuffer); + DRM_IOCTL_I915_BATCHBUFFER, + (unsigned long)batchbuffer); } typedef struct _drm_i915_cmdbuffer32 { - u32 buf; /* pointer to userspace command buffer */ + u32 buf; /* pointer to userspace command buffer */ int sz; /* nr bytes in buf */ int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ int num_cliprects; /* mulitpass with multiple cliprects? */ - u32 cliprects; /* pointer to userspace cliprects */ + u32 cliprects; /* pointer to userspace cliprects */ } drm_i915_cmdbuffer32_t; static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd, - unsigned long arg) + unsigned long arg) { drm_i915_cmdbuffer32_t cmdbuffer32; drm_i915_cmdbuffer_t __user *cmdbuffer; - - if (copy_from_user(&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32))) + + if (copy_from_user + (&cmdbuffer32, (void __user *)arg, sizeof(cmdbuffer32))) return -EFAULT; - + cmdbuffer = compat_alloc_user_space(sizeof(*cmdbuffer)); if (!access_ok(VERIFY_WRITE, cmdbuffer, sizeof(*cmdbuffer)) || __put_user((int __user *)(unsigned long)cmdbuffer32.buf, @@ -98,9 +102,9 @@ static int compat_i915_cmdbuffer(struct file *file, unsigned int cmd, || __put_user((int __user *)(unsigned long)cmdbuffer32.cliprects, &cmdbuffer->cliprects)) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_I915_CMDBUFFER, (unsigned long) cmdbuffer); + DRM_IOCTL_I915_CMDBUFFER, (unsigned long)cmdbuffer); } typedef struct drm_i915_irq_emit32 { @@ -108,12 +112,12 @@ typedef struct drm_i915_irq_emit32 { } drm_i915_irq_emit32_t; static int compat_i915_irq_emit(struct file *file, unsigned int cmd, - unsigned long arg) + unsigned long arg) { drm_i915_irq_emit32_t req32; drm_i915_irq_emit_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -123,7 +127,7 @@ static int compat_i915_irq_emit(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_I915_IRQ_EMIT, (unsigned long) request); + DRM_IOCTL_I915_IRQ_EMIT, (unsigned long)request); } typedef struct drm_i915_getparam32 { int param; @@ -131,12 +135,12 @@ typedef struct drm_i915_getparam32 { } drm_i915_getparam32_t; static int compat_i915_getparam(struct file *file, unsigned int cmd, - unsigned long arg) + unsigned long arg) { drm_i915_getparam32_t req32; drm_i915_getparam_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -147,7 +151,7 @@ static int compat_i915_getparam(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_I915_GETPARAM, (unsigned long) request); + DRM_IOCTL_I915_GETPARAM, (unsigned long)request); } typedef struct drm_i915_mem_alloc32 { @@ -158,12 +162,12 @@ typedef struct drm_i915_mem_alloc32 { } drm_i915_mem_alloc32_t; static int compat_i915_alloc(struct file *file, unsigned int cmd, - unsigned long arg) + unsigned long arg) { drm_i915_mem_alloc32_t req32; drm_i915_mem_alloc_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -176,10 +180,9 @@ static int compat_i915_alloc(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_I915_ALLOC, (unsigned long) request); + DRM_IOCTL_I915_ALLOC, (unsigned long)request); } - drm_ioctl_compat_t *i915_compat_ioctls[] = { [DRM_I915_BATCHBUFFER] = compat_i915_batchbuffer, [DRM_I915_CMDBUFFER] = compat_i915_cmdbuffer, @@ -197,8 +200,7 @@ drm_ioctl_compat_t *i915_compat_ioctls[] = { * \param arg user argument. * \return zero on success or negative number on failure. */ -long i915_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg) +long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int nr = DRM_IOCTL_NR(cmd); drm_ioctl_compat_t *fn = NULL; @@ -206,13 +208,13 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, if (nr < DRM_COMMAND_BASE) return drm_compat_ioctl(filp, cmd, arg); - + if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(i915_compat_ioctls)) fn = i915_compat_ioctls[nr - DRM_COMMAND_BASE]; lock_kernel(); /* XXX for now */ if (fn != NULL) - ret = (*fn)(filp, cmd, arg); + ret = (*fn) (filp, cmd, arg); else ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); unlock_kernel(); diff --git a/drivers/char/drm/i915_mem.c b/drivers/char/drm/i915_mem.c index 9b1698f521b..13176d136a9 100644 --- a/drivers/char/drm/i915_mem.c +++ b/drivers/char/drm/i915_mem.c @@ -86,7 +86,7 @@ static void mark_block(drm_device_t * dev, struct mem_block *p, int in_use) } /* Very simple allocator for agp memory, working on a static range - * already mapped into each client's address space. + * already mapped into each client's address space. */ static struct mem_block *split_block(struct mem_block *p, int start, int size, @@ -94,7 +94,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, { /* Maybe cut off the start of an existing block */ if (start > p->start) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); if (!newblock) goto out; newblock->start = start; @@ -110,7 +111,8 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, /* Maybe cut off the end of an existing block */ if (size < p->size) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFLISTS); if (!newblock) goto out; newblock->start = start + size; diff --git a/drivers/char/drm/mga_dma.c b/drivers/char/drm/mga_dma.c index fc7d4a594bc..cfbe35d5d86 100644 --- a/drivers/char/drm/mga_dma.c +++ b/drivers/char/drm/mga_dma.c @@ -28,7 +28,7 @@ /** * \file mga_dma.c * DMA support for MGA G200 / G400. - * + * * \author Rickard E. (Rik) Faith * \author Jeff Hartmann * \author Keith Whitwell @@ -44,40 +44,40 @@ #define MGA_DEFAULT_USEC_TIMEOUT 10000 #define MGA_FREELIST_DEBUG 0 -static int mga_do_cleanup_dma( drm_device_t *dev ); +static int mga_do_cleanup_dma(drm_device_t * dev); /* ================================================================ * Engine control */ -int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ) +int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) { u32 status = 0; int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) { - MGA_WRITE8( MGA_CRTC_INDEX, 0 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + if (status == MGA_ENDPRDMASTS) { + MGA_WRITE8(MGA_CRTC_INDEX, 0); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if MGA_DMA_DEBUG - DRM_ERROR( "failed!\n" ); - DRM_INFO( " status=0x%08x\n", status ); + DRM_ERROR("failed!\n"); + DRM_INFO(" status=0x%08x\n", status); #endif return DRM_ERR(EBUSY); } -static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) +static int mga_do_dma_reset(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_primary_buffer_t *primary = &dev_priv->prim; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The primary DMA stream should look like new right about now. */ @@ -100,24 +100,25 @@ static int mga_do_dma_reset( drm_mga_private_t *dev_priv ) * Primary DMA stream */ -void mga_do_dma_flush( drm_mga_private_t *dev_priv ) +void mga_do_dma_flush(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; u32 head, tail; u32 status = 0; int i; - DMA_LOCALS; - DRM_DEBUG( "\n" ); - - /* We need to wait so that we can do an safe flush */ - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - if ( status == MGA_ENDPRDMASTS ) break; - DRM_UDELAY( 1 ); + DMA_LOCALS; + DRM_DEBUG("\n"); + + /* We need to wait so that we can do an safe flush */ + for (i = 0; i < dev_priv->usec_timeout; i++) { + status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + if (status == MGA_ENDPRDMASTS) + break; + DRM_UDELAY(1); } - if ( primary->tail == primary->last_flush ) { - DRM_DEBUG( " bailing out...\n" ); + if (primary->tail == primary->last_flush) { + DRM_DEBUG(" bailing out...\n"); return; } @@ -127,48 +128,46 @@ void mga_do_dma_flush( drm_mga_private_t *dev_priv ) * actually (partially?) reads the first of these commands. * See page 4-16 in the G400 manual, middle of the page or so. */ - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); primary->last_flush = primary->tail; - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); - if ( head <= tail ) { + if (head <= tail) { primary->space = primary->size - primary->tail; } else { primary->space = head - tail; } - DRM_DEBUG( " head = 0x%06lx\n", head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06lx\n", tail - dev_priv->primary->offset ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); + DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); + DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); + DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_flush_write_combine(); MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); - DRM_DEBUG( "done.\n" ); + DRM_DEBUG("done.\n"); } -void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) +void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; u32 head, tail; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); BEGIN_DMA_WRAP(); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); @@ -178,45 +177,43 @@ void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ) primary->last_flush = 0; primary->last_wrap++; - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); - if ( head == dev_priv->primary->offset ) { + if (head == dev_priv->primary->offset) { primary->space = primary->size; } else { primary->space = head - dev_priv->primary->offset; } - DRM_DEBUG( " head = 0x%06lx\n", - head - dev_priv->primary->offset ); - DRM_DEBUG( " tail = 0x%06x\n", primary->tail ); - DRM_DEBUG( " wrap = %d\n", primary->last_wrap ); - DRM_DEBUG( " space = 0x%06x\n", primary->space ); + DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); + DRM_DEBUG(" tail = 0x%06x\n", primary->tail); + DRM_DEBUG(" wrap = %d\n", primary->last_wrap); + DRM_DEBUG(" space = 0x%06x\n", primary->space); mga_flush_write_combine(); MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); - set_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); + set_bit(0, &primary->wrapped); + DRM_DEBUG("done.\n"); } -void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) +void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) { drm_mga_primary_buffer_t *primary = &dev_priv->prim; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; u32 head = dev_priv->primary->offset; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); sarea_priv->last_wrap++; - DRM_DEBUG( " wrap = %d\n", sarea_priv->last_wrap ); + DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); mga_flush_write_combine(); - MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL ); + MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); - clear_bit( 0, &primary->wrapped ); - DRM_DEBUG( "done.\n" ); + clear_bit(0, &primary->wrapped); + DRM_DEBUG("done.\n"); } - /* ================================================================ * Freelist management */ @@ -225,63 +222,61 @@ void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ) #define MGA_BUFFER_FREE 0 #if MGA_FREELIST_DEBUG -static void mga_freelist_print( drm_device_t *dev ) +static void mga_freelist_print(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; - DRM_INFO( "\n" ); - DRM_INFO( "current dispatch: last=0x%x done=0x%x\n", - dev_priv->sarea_priv->last_dispatch, - (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) - - dev_priv->primary->offset) ); - DRM_INFO( "current freelist:\n" ); - - for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) { - DRM_INFO( " %p idx=%2d age=0x%x 0x%06lx\n", - entry, entry->buf->idx, entry->age.head, - entry->age.head - dev_priv->primary->offset ); + DRM_INFO("\n"); + DRM_INFO("current dispatch: last=0x%x done=0x%x\n", + dev_priv->sarea_priv->last_dispatch, + (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - + dev_priv->primary->offset)); + DRM_INFO("current freelist:\n"); + + for (entry = dev_priv->head->next; entry; entry = entry->next) { + DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", + entry, entry->buf->idx, entry->age.head, + entry->age.head - dev_priv->primary->offset); } - DRM_INFO( "\n" ); + DRM_INFO("\n"); } #endif -static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) +static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) { drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_freelist_t *entry; int i; - DRM_DEBUG( "count=%d\n", dma->buf_count ); + DRM_DEBUG("count=%d\n", dma->buf_count); - dev_priv->head = drm_alloc( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) + dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if (dev_priv->head == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) ); - SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 ); + memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); + SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; - buf_priv = buf->dev_private; + buf_priv = buf->dev_private; - entry = drm_alloc( sizeof(drm_mga_freelist_t), - DRM_MEM_DRIVER ); - if ( entry == NULL ) + entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); + if (entry == NULL) return DRM_ERR(ENOMEM); - memset( entry, 0, sizeof(drm_mga_freelist_t) ); + memset(entry, 0, sizeof(drm_mga_freelist_t)); entry->next = dev_priv->head->next; entry->prev = dev_priv->head; - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); entry->buf = buf; - if ( dev_priv->head->next != NULL ) + if (dev_priv->head->next != NULL) dev_priv->head->next->prev = entry; - if ( entry->next == NULL ) + if (entry->next == NULL) dev_priv->tail = entry; buf_priv->list_entry = entry; @@ -294,17 +289,17 @@ static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv ) return 0; } -static void mga_freelist_cleanup( drm_device_t *dev ) +static void mga_freelist_cleanup(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *entry; drm_mga_freelist_t *next; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); entry = dev_priv->head; - while ( entry ) { + while (entry) { next = entry->next; - drm_free( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER ); + drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); entry = next; } @@ -314,71 +309,69 @@ static void mga_freelist_cleanup( drm_device_t *dev ) #if 0 /* FIXME: Still needed? */ -static void mga_freelist_reset( drm_device_t *dev ) +static void mga_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; int i; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; - buf_priv = buf->dev_private; - SET_AGE( &buf_priv->list_entry->age, - MGA_BUFFER_FREE, 0 ); + buf_priv = buf->dev_private; + SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0); } } #endif -static drm_buf_t *mga_freelist_get( drm_device_t *dev ) +static drm_buf_t *mga_freelist_get(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_freelist_t *next; drm_mga_freelist_t *prev; drm_mga_freelist_t *tail = dev_priv->tail; u32 head, wrap; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - head = MGA_READ( MGA_PRIMADDRESS ); + head = MGA_READ(MGA_PRIMADDRESS); wrap = dev_priv->sarea_priv->last_wrap; - DRM_DEBUG( " tail=0x%06lx %d\n", - tail->age.head ? - tail->age.head - dev_priv->primary->offset : 0, - tail->age.wrap ); - DRM_DEBUG( " head=0x%06lx %d\n", - head - dev_priv->primary->offset, wrap ); + DRM_DEBUG(" tail=0x%06lx %d\n", + tail->age.head ? + tail->age.head - dev_priv->primary->offset : 0, + tail->age.wrap); + DRM_DEBUG(" head=0x%06lx %d\n", + head - dev_priv->primary->offset, wrap); - if ( TEST_AGE( &tail->age, head, wrap ) ) { + if (TEST_AGE(&tail->age, head, wrap)) { prev = dev_priv->tail->prev; next = dev_priv->tail; prev->next = NULL; next->prev = next->next = NULL; dev_priv->tail = prev; - SET_AGE( &next->age, MGA_BUFFER_USED, 0 ); + SET_AGE(&next->age, MGA_BUFFER_USED, 0); return next->buf; } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } -int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) +int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_freelist_t *head, *entry, *prev; - DRM_DEBUG( "age=0x%06lx wrap=%d\n", - buf_priv->list_entry->age.head - - dev_priv->primary->offset, - buf_priv->list_entry->age.wrap ); + DRM_DEBUG("age=0x%06lx wrap=%d\n", + buf_priv->list_entry->age.head - + dev_priv->primary->offset, buf_priv->list_entry->age.wrap); entry = buf_priv->list_entry; head = dev_priv->head; - if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) { - SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 ); + if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { + SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); prev = dev_priv->tail; prev->next = entry; entry->prev = prev; @@ -394,15 +387,13 @@ int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ) return 0; } - /* ================================================================ * DMA initialization, cleanup */ - -int mga_driver_preinit(drm_device_t *dev, unsigned long flags) +int mga_driver_preinit(drm_device_t * dev, unsigned long flags) { - drm_mga_private_t * dev_priv; + drm_mga_private_t *dev_priv; dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); if (!dev_priv) @@ -420,7 +411,7 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags) #if __OS_HAS_AGP /** * Bootstrap the driver for AGP DMA. - * + * * \todo * Investigate whether there is any benifit to storing the WARP microcode in * AGP memory. If not, the microcode may as well always be put in PCI @@ -436,18 +427,18 @@ int mga_driver_preinit(drm_device_t *dev, unsigned long flags) static int mga_do_agp_dma_bootstrap(drm_device_t * dev, drm_mga_dma_bootstrap_t * dma_bs) { - drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; const unsigned int warp_size = mga_warp_microcode_size(dev_priv); int err; - unsigned offset; + unsigned offset; const unsigned secondary_size = dma_bs->secondary_bin_count - * dma_bs->secondary_bin_size; + * dma_bs->secondary_bin_size; const unsigned agp_size = (dma_bs->agp_size << 20); drm_buf_desc_t req; drm_agp_mode_t mode; drm_agp_info_t info; - /* Acquire AGP. */ err = drm_agp_acquire(dev); if (err) { @@ -468,7 +459,6 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, return err; } - /* In addition to the usual AGP mode configuration, the G200 AGP cards * need to have the AGP mode "manually" set. */ @@ -476,68 +466,66 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, if (dev_priv->chipset == MGA_CARD_TYPE_G200) { if (mode.mode & 0x02) { MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); - } - else { + } else { MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); } } - /* Allocate and bind AGP memory. */ dev_priv->agp_pages = agp_size / PAGE_SIZE; - dev_priv->agp_mem = drm_alloc_agp( dev, dev_priv->agp_pages, 0 ); + dev_priv->agp_mem = drm_alloc_agp(dev, dev_priv->agp_pages, 0); if (dev_priv->agp_mem == NULL) { dev_priv->agp_pages = 0; DRM_ERROR("Unable to allocate %uMB AGP memory\n", dma_bs->agp_size); return DRM_ERR(ENOMEM); } - - err = drm_bind_agp( dev_priv->agp_mem, 0 ); + + err = drm_bind_agp(dev_priv->agp_mem, 0); if (err) { DRM_ERROR("Unable to bind AGP memory\n"); return err; } offset = 0; - err = drm_addmap( dev, offset, warp_size, - _DRM_AGP, _DRM_READ_ONLY, & dev_priv->warp ); + err = drm_addmap(dev, offset, warp_size, + _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); if (err) { DRM_ERROR("Unable to map WARP microcode\n"); return err; } offset += warp_size; - err = drm_addmap( dev, offset, dma_bs->primary_size, - _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary ); + err = drm_addmap(dev, offset, dma_bs->primary_size, + _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); if (err) { DRM_ERROR("Unable to map primary DMA region\n"); return err; } offset += dma_bs->primary_size; - err = drm_addmap( dev, offset, secondary_size, - _DRM_AGP, 0, & dev->agp_buffer_map ); + err = drm_addmap(dev, offset, secondary_size, + _DRM_AGP, 0, &dev->agp_buffer_map); if (err) { DRM_ERROR("Unable to map secondary DMA region\n"); return err; } - (void) memset( &req, 0, sizeof(req) ); + (void)memset(&req, 0, sizeof(req)); req.count = dma_bs->secondary_bin_count; req.size = dma_bs->secondary_bin_size; req.flags = _DRM_AGP_BUFFER; req.agp_start = offset; - err = drm_addbufs_agp( dev, & req ); + err = drm_addbufs_agp(dev, &req); if (err) { DRM_ERROR("Unable to add secondary DMA buffers\n"); return err; } offset += secondary_size; - err = drm_addmap( dev, offset, agp_size - offset, - _DRM_AGP, 0, & dev_priv->agp_textures ); + err = drm_addmap(dev, offset, agp_size - offset, + _DRM_AGP, 0, &dev_priv->agp_textures); if (err) { DRM_ERROR("Unable to map AGP texture region\n"); return err; @@ -571,7 +559,7 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, /** * Bootstrap the driver for PCI DMA. - * + * * \todo * The algorithm for decreasing the size of the primary DMA buffer could be * better. The size should be rounded up to the nearest page size, then @@ -580,20 +568,20 @@ static int mga_do_agp_dma_bootstrap(drm_device_t * dev, * \todo * Determine whether the maximum address passed to drm_pci_alloc is correct. * The same goes for drm_addbufs_pci. - * + * * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap */ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, drm_mga_dma_bootstrap_t * dma_bs) { - drm_mga_private_t * const dev_priv = (drm_mga_private_t *) dev->dev_private; + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; const unsigned int warp_size = mga_warp_microcode_size(dev_priv); unsigned int primary_size; unsigned int bin_count; int err; drm_buf_desc_t req; - if (dev->dma == NULL) { DRM_ERROR("dev->dma is NULL\n"); return DRM_ERR(EFAULT); @@ -612,9 +600,8 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, * alignment of the primary or secondary DMA buffers. */ - for ( primary_size = dma_bs->primary_size - ; primary_size != 0 - ; primary_size >>= 1 ) { + for (primary_size = dma_bs->primary_size; primary_size != 0; + primary_size >>= 1) { /* The proper alignment for this mapping is 0x04 */ err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, _DRM_READ_ONLY, &dev_priv->primary); @@ -629,24 +616,23 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, if (dev_priv->primary->size != dma_bs->primary_size) { DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", - dma_bs->primary_size, - (unsigned) dev_priv->primary->size); + dma_bs->primary_size, + (unsigned)dev_priv->primary->size); dma_bs->primary_size = dev_priv->primary->size; } - for ( bin_count = dma_bs->secondary_bin_count - ; bin_count > 0 - ; bin_count-- ) { - (void) memset( &req, 0, sizeof(req) ); + for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; + bin_count--) { + (void)memset(&req, 0, sizeof(req)); req.count = bin_count; req.size = dma_bs->secondary_bin_size; - err = drm_addbufs_pci( dev, & req ); + err = drm_addbufs_pci(dev, &req); if (!err) { break; } } - + if (bin_count == 0) { DRM_ERROR("Unable to add secondary DMA buffers\n"); return err; @@ -668,38 +654,34 @@ static int mga_do_pci_dma_bootstrap(drm_device_t * dev, return 0; } - static int mga_do_dma_bootstrap(drm_device_t * dev, drm_mga_dma_bootstrap_t * dma_bs) { const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); int err; - drm_mga_private_t * const dev_priv = - (drm_mga_private_t *) dev->dev_private; - + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; dev_priv->used_new_dma_init = 1; /* The first steps are the same for both PCI and AGP based DMA. Map * the cards MMIO registers and map a status page. */ - err = drm_addmap( dev, dev_priv->mmio_base, dev_priv->mmio_size, - _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio ); + err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, + _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); if (err) { DRM_ERROR("Unable to map MMIO region\n"); return err; } - - err = drm_addmap( dev, 0, SAREA_MAX, _DRM_SHM, - _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, - & dev_priv->status ); + err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, + _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, + &dev_priv->status); if (err) { DRM_ERROR("Unable to map status region\n"); return err; } - /* The DMA initialization procedure is slightly different for PCI and * AGP cards. AGP cards just allocate a large block of AGP memory and * carve off portions of it for internal uses. The remaining memory @@ -708,7 +690,7 @@ static int mga_do_dma_bootstrap(drm_device_t * dev, if (is_agp) { err = mga_do_agp_dma_bootstrap(dev, dma_bs); } - + /* If we attempted to initialize the card for AGP DMA but failed, * clean-up any mess that may have been created. */ @@ -717,7 +699,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev, mga_do_cleanup_dma(dev); } - /* Not only do we want to try and initialized PCI cards for PCI DMA, * but we also try to initialized AGP cards that could not be * initialized for AGP DMA. This covers the case where we have an AGP @@ -730,7 +711,6 @@ static int mga_do_dma_bootstrap(drm_device_t * dev, err = mga_do_pci_dma_bootstrap(dev, dma_bs); } - return err; } @@ -740,45 +720,42 @@ int mga_dma_bootstrap(DRM_IOCTL_ARGS) drm_mga_dma_bootstrap_t bootstrap; int err; - DRM_COPY_FROM_USER_IOCTL(bootstrap, (drm_mga_dma_bootstrap_t __user *) data, sizeof(bootstrap)); - err = mga_do_dma_bootstrap(dev, & bootstrap); - if (! err) { + err = mga_do_dma_bootstrap(dev, &bootstrap); + if (!err) { static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; - const drm_mga_private_t * const dev_priv = - (drm_mga_private_t *) dev->dev_private; + const drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; if (dev_priv->agp_textures != NULL) { - bootstrap.texture_handle = dev_priv->agp_textures->offset; + bootstrap.texture_handle = + dev_priv->agp_textures->offset; bootstrap.texture_size = dev_priv->agp_textures->size; - } - else { + } else { bootstrap.texture_handle = 0; bootstrap.texture_size = 0; } - bootstrap.agp_mode = modes[ bootstrap.agp_mode & 0x07 ]; - if (DRM_COPY_TO_USER( (void __user *) data, & bootstrap, + bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07]; + if (DRM_COPY_TO_USER((void __user *)data, &bootstrap, sizeof(bootstrap))) { err = DRM_ERR(EFAULT); } - } - else { + } else { mga_do_cleanup_dma(dev); } return err; } -static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) +static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) { drm_mga_private_t *dev_priv; int ret; - DRM_DEBUG( "\n" ); - + DRM_DEBUG("\n"); dev_priv = dev->dev_private; @@ -787,17 +764,17 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) } else { dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; } - dev_priv->maccess = init->maccess; + dev_priv->maccess = init->maccess; - dev_priv->fb_cpp = init->fb_cpp; - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->fb_cpp = init->fb_cpp; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - dev_priv->depth_cpp = init->depth_cpp; - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; + dev_priv->depth_cpp = init->depth_cpp; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; /* FIXME: Need to support AGP textures... */ @@ -811,7 +788,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) return DRM_ERR(EINVAL); } - if (! dev_priv->used_new_dma_init) { + if (!dev_priv->used_new_dma_init) { dev_priv->status = drm_core_findmap(dev, init->status_offset); if (!dev_priv->status) { DRM_ERROR("failed to find status page!\n"); @@ -833,7 +810,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) return DRM_ERR(EINVAL); } dev->agp_buffer_token = init->buffers_offset; - dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); + dev->agp_buffer_map = + drm_core_findmap(dev, init->buffers_offset); if (!dev->agp_buffer_map) { DRM_ERROR("failed to find dma buffer region!\n"); return DRM_ERR(EINVAL); @@ -845,8 +823,8 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) } dev_priv->sarea_priv = - (drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); if (!dev_priv->warp->handle || !dev_priv->primary->handle || @@ -869,23 +847,20 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) return ret; } - dev_priv->prim.status = (u32 *)dev_priv->status->handle; + dev_priv->prim.status = (u32 *) dev_priv->status->handle; - mga_do_wait_for_idle( dev_priv ); + mga_do_wait_for_idle(dev_priv); /* Init the primary DMA registers. */ - MGA_WRITE( MGA_PRIMADDRESS, - dev_priv->primary->offset | MGA_DMA_GENERAL ); + MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); #if 0 - MGA_WRITE( MGA_PRIMPTR, - virt_to_bus((void *)dev_priv->prim.status) | - MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ - MGA_PRIMPTREN1 ); /* DWGSYNC */ + MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */ + MGA_PRIMPTREN1); /* DWGSYNC */ #endif - dev_priv->prim.start = (u8 *)dev_priv->primary->handle; - dev_priv->prim.end = ((u8 *)dev_priv->primary->handle + dev_priv->prim.start = (u8 *) dev_priv->primary->handle; + dev_priv->prim.end = ((u8 *) dev_priv->primary->handle + dev_priv->primary->size); dev_priv->prim.size = dev_priv->primary->size; @@ -913,7 +888,7 @@ static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init ) return 0; } -static int mga_do_cleanup_dma( drm_device_t *dev ) +static int mga_do_cleanup_dma(drm_device_t * dev) { int err = 0; DRM_DEBUG("\n"); @@ -922,16 +897,17 @@ static int mga_do_cleanup_dma( drm_device_t *dev ) * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - if ( dev->dev_private ) { + if (dev->dev_private) { drm_mga_private_t *dev_priv = dev->dev_private; - if ((dev_priv->warp != NULL) + if ((dev_priv->warp != NULL) && (dev_priv->mmio->type != _DRM_CONSISTENT)) drm_core_ioremapfree(dev_priv->warp, dev); - if ((dev_priv->primary != NULL) + if ((dev_priv->primary != NULL) && (dev_priv->primary->type != _DRM_CONSISTENT)) drm_core_ioremapfree(dev_priv->primary, dev); @@ -944,7 +920,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev ) dev_priv->agp_textures = NULL; drm_unbind_agp(dev_priv->agp_mem); - drm_free_agp(dev_priv->agp_mem, dev_priv->agp_pages); + drm_free_agp(dev_priv->agp_mem, + dev_priv->agp_pages); dev_priv->agp_pages = 0; dev_priv->agp_mem = NULL; } @@ -966,7 +943,8 @@ static int mga_do_cleanup_dma( drm_device_t *dev ) memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); dev_priv->warp_pipe = 0; - memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); + memset(dev_priv->warp_pipe_phys, 0, + sizeof(dev_priv->warp_pipe_phys)); if (dev_priv->head != NULL) { mga_freelist_cleanup(dev); @@ -976,103 +954,102 @@ static int mga_do_cleanup_dma( drm_device_t *dev ) return err; } -int mga_dma_init( DRM_IOCTL_ARGS ) +int mga_dma_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_init_t init; int err; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, sizeof(init)); - switch ( init.func ) { + switch (init.func) { case MGA_INIT_DMA: err = mga_do_init_dma(dev, &init); if (err) { - (void) mga_do_cleanup_dma(dev); + (void)mga_do_cleanup_dma(dev); } return err; case MGA_CLEANUP_DMA: - return mga_do_cleanup_dma( dev ); + return mga_do_cleanup_dma(dev); } return DRM_ERR(EINVAL); } - /* ================================================================ * Primary DMA stream management */ -int mga_dma_flush( DRM_IOCTL_ARGS ) +int mga_dma_flush(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; drm_lock_t lock; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( lock, (drm_lock_t __user *)data, sizeof(lock) ); + DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data, + sizeof(lock)); - DRM_DEBUG( "%s%s%s\n", - (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", - (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", - (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "" ); + DRM_DEBUG("%s%s%s\n", + (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", + (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", + (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); - WRAP_WAIT_WITH_RETURN( dev_priv ); + WRAP_WAIT_WITH_RETURN(dev_priv); - if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) { - mga_do_dma_flush( dev_priv ); + if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { + mga_do_dma_flush(dev_priv); } - if ( lock.flags & _DRM_LOCK_QUIESCENT ) { + if (lock.flags & _DRM_LOCK_QUIESCENT) { #if MGA_DMA_DEBUG - int ret = mga_do_wait_for_idle( dev_priv ); - if ( ret < 0 ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + int ret = mga_do_wait_for_idle(dev_priv); + if (ret < 0) + DRM_INFO("%s: -EBUSY\n", __FUNCTION__); return ret; #else - return mga_do_wait_for_idle( dev_priv ); + return mga_do_wait_for_idle(dev_priv); #endif } else { return 0; } } -int mga_dma_reset( DRM_IOCTL_ARGS ) +int mga_dma_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return mga_do_dma_reset( dev_priv ); + return mga_do_dma_reset(dev_priv); } - /* ================================================================ * DMA buffer management */ -static int mga_dma_get_buffers( DRMFILE filp, - drm_device_t *dev, drm_dma_t *d ) +static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) { drm_buf_t *buf; int i; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = mga_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); + for (i = d->granted_count; i < d->request_count; i++) { + buf = mga_freelist_get(dev); + if (!buf) + return DRM_ERR(EAGAIN); buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], - &buf->idx, sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], + &buf->idx, sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], - &buf->total, sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], + &buf->total, sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -1080,44 +1057,44 @@ static int mga_dma_get_buffers( DRMFILE filp, return 0; } -int mga_dma_buffers( DRM_IOCTL_ARGS ) +int mga_dma_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; - drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; int ret = 0; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); d.granted_count = 0; - if ( d.request_count ) { - ret = mga_dma_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = mga_dma_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } @@ -1138,11 +1115,11 @@ int mga_driver_postcleanup(drm_device_t * dev) */ void mga_driver_pretakedown(drm_device_t * dev) { - mga_do_cleanup_dma( dev ); + mga_do_cleanup_dma(dev); } -int mga_driver_dma_quiescent(drm_device_t *dev) +int mga_driver_dma_quiescent(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; - return mga_do_wait_for_idle( dev_priv ); + return mga_do_wait_for_idle(dev_priv); } diff --git a/drivers/char/drm/mga_drm.h b/drivers/char/drm/mga_drm.h index d20aab3bd57..44d1293e294 100644 --- a/drivers/char/drm/mga_drm.h +++ b/drivers/char/drm/mga_drm.h @@ -44,10 +44,10 @@ /* WARP pipe flags */ -#define MGA_F 0x1 /* fog */ -#define MGA_A 0x2 /* alpha */ -#define MGA_S 0x4 /* specular */ -#define MGA_T2 0x8 /* multitexture */ +#define MGA_F 0x1 /* fog */ +#define MGA_A 0x2 /* alpha */ +#define MGA_S 0x4 /* specular */ +#define MGA_T2 0x8 /* multitexture */ #define MGA_WARP_TGZ 0 #define MGA_WARP_TGZF (MGA_F) @@ -66,14 +66,14 @@ #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) -#define MGA_MAX_G200_PIPES 8 /* no multitex */ +#define MGA_MAX_G200_PIPES 8 /* no multitex */ #define MGA_MAX_G400_PIPES 16 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES -#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ +#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ #define MGA_CARD_TYPE_G200 1 #define MGA_CARD_TYPE_G400 2 -#define MGA_CARD_TYPE_G450 3 /* not currently used */ +#define MGA_CARD_TYPE_G450 3 /* not currently used */ #define MGA_CARD_TYPE_G550 4 #define MGA_FRONT 0x1 @@ -86,14 +86,14 @@ #define MGA_UPLOAD_TEX0 0x2 #define MGA_UPLOAD_TEX1 0x4 #define MGA_UPLOAD_PIPE 0x8 -#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ -#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ #define MGA_UPLOAD_2D 0x40 -#define MGA_WAIT_AGE 0x80 /* handled client-side */ -#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ #if 0 -#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock - quiescent */ +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ #endif /* 32 buffers of 64k each, total 2 meg. @@ -120,8 +120,7 @@ #define DRM_MGA_IDLE_RETRY 2048 -#endif /* __MGA_SAREA_DEFINES__ */ - +#endif /* __MGA_SAREA_DEFINES__ */ /* Setup registers for 3D context */ @@ -165,25 +164,25 @@ typedef struct { /* General aging mechanism */ typedef struct { - unsigned int head; /* Position of head pointer */ - unsigned int wrap; /* Primary DMA wrap count */ + unsigned int head; /* Position of head pointer */ + unsigned int wrap; /* Primary DMA wrap count */ } drm_mga_age_t; typedef struct _drm_mga_sarea { /* The channel for communication of state information to the kernel * on firing a vertex dma buffer. */ - drm_mga_context_regs_t context_state; - drm_mga_server_regs_t server_state; - drm_mga_texture_regs_t tex_state[2]; - unsigned int warp_pipe; - unsigned int dirty; - unsigned int vertsize; + drm_mga_context_regs_t context_state; + drm_mga_server_regs_t server_state; + drm_mga_texture_regs_t tex_state[2]; + unsigned int warp_pipe; + unsigned int dirty; + unsigned int vertsize; /* The current cliprects, or a subset thereof. */ - drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; - unsigned int nbox; + drm_clip_rect_t boxes[MGA_NR_SAREA_CLIPRECTS]; + unsigned int nbox; /* Information about the most recently used 3d drawable. The * client fills in the req_* fields, the server fills in the @@ -192,18 +191,18 @@ typedef struct _drm_mga_sarea { * The client clears the exported_drawable field before * clobbering the boxes data. */ - unsigned int req_drawable; /* the X drawable id */ - unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ - unsigned int exported_drawable; + unsigned int exported_drawable; unsigned int exported_index; - unsigned int exported_stamp; - unsigned int exported_buffers; - unsigned int exported_nfront; - unsigned int exported_nback; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; int exported_back_x, exported_front_x, exported_w; int exported_back_y, exported_front_y, exported_h; - drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + drm_clip_rect_t exported_boxes[MGA_NR_SAREA_CLIPRECTS]; /* Counters for aging textures and for client-side throttling. */ @@ -211,21 +210,20 @@ typedef struct _drm_mga_sarea { unsigned int last_wrap; drm_mga_age_t last_frame; - unsigned int last_enqueue; /* last time a buffer was enqueued */ + unsigned int last_enqueue; /* last time a buffer was enqueued */ unsigned int last_dispatch; /* age of the most recently dispatched buffer */ - unsigned int last_quiescent; /* */ + unsigned int last_quiescent; /* */ /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS+1]; + drm_tex_region_t texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; unsigned int texAge[MGA_NR_TEX_HEAPS]; /* Mechanism to validate card state. */ - int ctxOwner; + int ctxOwner; } drm_mga_sarea_t; - /* MGA specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ @@ -247,7 +245,6 @@ typedef struct _drm_mga_sarea { #define DRM_MGA_WAIT_FENCE 0x0b #define DRM_MGA_DMA_BOOTSTRAP 0x0c - #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) @@ -263,33 +260,33 @@ typedef struct _drm_mga_sarea { #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) typedef struct _drm_mga_warp_index { - int installed; - unsigned long phys_addr; - int size; + int installed; + unsigned long phys_addr; + int size; } drm_mga_warp_index_t; typedef struct drm_mga_init { - enum { - MGA_INIT_DMA = 0x01, - MGA_CLEANUP_DMA = 0x02 + enum { + MGA_INIT_DMA = 0x01, + MGA_CLEANUP_DMA = 0x02 } func; - unsigned long sarea_priv_offset; + unsigned long sarea_priv_offset; int chipset; - int sgram; + int sgram; unsigned int maccess; - unsigned int fb_cpp; + unsigned int fb_cpp; unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; + unsigned int back_offset, back_pitch; - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; + unsigned int texture_offset[MGA_NR_TEX_HEAPS]; + unsigned int texture_size[MGA_NR_TEX_HEAPS]; unsigned long fb_offset; unsigned long mmio_offset; @@ -302,64 +299,59 @@ typedef struct drm_mga_init { typedef struct drm_mga_dma_bootstrap { /** * \name AGP texture region - * + * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will * be filled in with the actual AGP texture settings. - * + * * \warning * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode * is zero, it means that PCI memory (most likely through the use of * an IOMMU) is being used for "AGP" textures. */ - /*@{*/ + /*@{ */ unsigned long texture_handle; /**< Handle used to map AGP textures. */ - uint32_t texture_size; /**< Size of the AGP texture region. */ - /*@}*/ - + uint32_t texture_size; /**< Size of the AGP texture region. */ + /*@} */ /** * Requested size of the primary DMA region. - * + * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual AGP mode. If AGP was not available */ uint32_t primary_size; - /** * Requested number of secondary DMA buffers. - * + * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual number of secondary DMA buffers * allocated. Particularly when PCI DMA is used, this may be * (subtantially) less than the number requested. */ uint32_t secondary_bin_count; - - + /** * Requested size of each secondary DMA buffer. - * + * * While the kernel \b is free to reduce * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed * to reduce dma_mga_dma_bootstrap::secondary_bin_size. */ uint32_t secondary_bin_size; - /** * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is * zero, it means that PCI DMA should be used, even if AGP is * possible. - * + * * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be * filled in with the actual AGP mode. If AGP was not available * (i.e., PCI DMA was used), this value will be zero. */ uint32_t agp_mode; - /** * Desired AGP GART size, measured in megabytes. */ @@ -375,16 +367,16 @@ typedef struct drm_mga_clear { } drm_mga_clear_t; typedef struct drm_mga_vertex { - int idx; /* buffer to queue */ - int used; /* bytes in use */ - int discard; /* client finished with buffer? */ + int idx; /* buffer to queue */ + int used; /* bytes in use */ + int discard; /* client finished with buffer? */ } drm_mga_vertex_t; typedef struct drm_mga_indices { - int idx; /* buffer to queue */ + int idx; /* buffer to queue */ unsigned int start; unsigned int end; - int discard; /* client finished with buffer? */ + int discard; /* client finished with buffer? */ } drm_mga_indices_t; typedef struct drm_mga_iload { @@ -400,12 +392,12 @@ typedef struct _drm_mga_blit { int src_pitch, dst_pitch; int delta_sx, delta_sy; int delta_dx, delta_dy; - int height, ydir; /* flip image vertically */ + int height, ydir; /* flip image vertically */ int source_pitch, dest_pitch; } drm_mga_blit_t; /* 3.1: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ #define MGA_PARAM_IRQ_NR 1 diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c index daabbba3b29..220037a91c0 100644 --- a/drivers/char/drm/mga_drv.c +++ b/drivers/char/drm/mga_drv.c @@ -35,14 +35,13 @@ #include "mga_drm.h" #include "mga_drv.h" - #include "drm_pciids.h" static int mga_driver_device_is_agp(drm_device_t * dev); -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - drm_mga_private_t * const dev_priv = - (drm_mga_private_t *) dev->dev_private; + drm_mga_private_t *const dev_priv = + (drm_mga_private_t *) dev->dev_private; dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); dev_priv->mmio_size = pci_resource_len(dev->pdev, 1); @@ -52,28 +51,26 @@ static int postinit( struct drm_device *dev, unsigned long flags ) dev->types[7] = _DRM_STAT_PRIMARY; dev->types[8] = _DRM_STAT_SECONDARY; - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -85,7 +82,10 @@ extern drm_ioctl_desc_t mga_ioctls[]; extern int mga_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | + DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .preinit = mga_driver_preinit, .postcleanup = mga_driver_postcleanup, .pretakedown = mga_driver_pretakedown, @@ -104,21 +104,21 @@ static struct drm_driver driver = { .ioctls = mga_ioctls, .dma_ioctl = mga_dma_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, #ifdef CONFIG_COMPAT - .compat_ioctl = mga_compat_ioctl, + .compat_ioctl = mga_compat_ioctl, #endif - }, + }, .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init mga_init(void) @@ -135,8 +135,8 @@ static void __exit mga_exit(void) module_init(mga_init); module_exit(mga_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); /** @@ -153,8 +153,7 @@ MODULE_LICENSE("GPL and additional rights"); */ int mga_driver_device_is_agp(drm_device_t * dev) { - const struct pci_dev * const pdev = dev->pdev; - + const struct pci_dev *const pdev = dev->pdev; /* There are PCI versions of the G450. These cards have the * same PCI ID as the AGP G450, but have an additional PCI-to-PCI @@ -164,10 +163,10 @@ int mga_driver_device_is_agp(drm_device_t * dev) * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the * device. */ - - if ( (pdev->device == 0x0525) - && (pdev->bus->self->vendor == 0x3388) - && (pdev->bus->self->device == 0x0021) ) { + + if ((pdev->device == 0x0525) + && (pdev->bus->self->vendor == 0x3388) + && (pdev->bus->self->device == 0x0021)) { return 0; } diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h index b22fdbd4f83..05f0f913ded 100644 --- a/drivers/char/drm/mga_drv.h +++ b/drivers/char/drm/mga_drv.h @@ -62,14 +62,14 @@ typedef struct drm_mga_primary_buffer { } drm_mga_primary_buffer_t; typedef struct drm_mga_freelist { - struct drm_mga_freelist *next; - struct drm_mga_freelist *prev; + struct drm_mga_freelist *next; + struct drm_mga_freelist *prev; drm_mga_age_t age; - drm_buf_t *buf; + drm_buf_t *buf; } drm_mga_freelist_t; typedef struct { - drm_mga_freelist_t *list_entry; + drm_mga_freelist_t *list_entry; int discard; int dispatched; } drm_mga_buf_priv_t; @@ -78,8 +78,8 @@ typedef struct drm_mga_private { drm_mga_primary_buffer_t prim; drm_mga_sarea_t *sarea_priv; - drm_mga_freelist_t *head; - drm_mga_freelist_t *tail; + drm_mga_freelist_t *head; + drm_mga_freelist_t *tail; unsigned int warp_pipe; unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; @@ -109,13 +109,13 @@ typedef struct drm_mga_private { /** * \name MMIO region parameters. - * + * * \sa drm_mga_private_t::mmio */ - /*@{*/ - u32 mmio_base; /**< Bus address of base of MMIO. */ - u32 mmio_size; /**< Size of the MMIO region. */ - /*@}*/ + /*@{ */ + u32 mmio_base; /**< Bus address of base of MMIO. */ + u32 mmio_size; /**< Size of the MMIO region. */ + /*@} */ u32 clear_cmd; u32 maccess; @@ -143,7 +143,7 @@ typedef struct drm_mga_private { drm_local_map_t *warp; drm_local_map_t *primary; drm_local_map_t *agp_textures; - + DRM_AGP_MEM *agp_mem; unsigned int agp_pages; } drm_mga_private_t; @@ -165,7 +165,7 @@ extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); -extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); +extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf); /* mga_warp.c */ extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); @@ -196,7 +196,7 @@ extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) -static inline u32 _MGA_READ(u32 *addr) +static inline u32 _MGA_READ(u32 * addr) { DRM_MEMORYBARRIER(); return *(volatile u32 *)addr; @@ -218,8 +218,6 @@ static inline u32 _MGA_READ(u32 *addr) #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) - - /* ================================================================ * Helper macross... */ @@ -261,7 +259,6 @@ do { \ } \ } while (0) - /* ================================================================ * Primary DMA command stream */ @@ -346,7 +343,6 @@ do { \ write += DMA_BLOCK_SIZE; \ } while (0) - /* Buffer aging via primary DMA stream head pointer. */ @@ -373,7 +369,6 @@ do { \ } \ } while (0) - #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ MGA_DWGENGSTS | \ MGA_ENDPRDMASTS) @@ -382,8 +377,6 @@ do { \ #define MGA_DMA_DEBUG 0 - - /* A reduced set of the mga registers. */ #define MGA_CRTC_INDEX 0x1fd4 @@ -644,7 +637,6 @@ do { \ # define MGA_G400_WR_MAGIC (1 << 6) # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ - #define MGA_ILOAD_ALIGN 64 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) @@ -679,10 +671,10 @@ do { \ /* Simple idle test. */ -static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) +static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) { - u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; - return ( status == MGA_ENDPRDMASTS ); + u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; + return (status == MGA_ENDPRDMASTS); } #endif diff --git a/drivers/char/drm/mga_ioc32.c b/drivers/char/drm/mga_ioc32.c index 77d738e75a4..24a9d4e86af 100644 --- a/drivers/char/drm/mga_ioc32.c +++ b/drivers/char/drm/mga_ioc32.c @@ -39,17 +39,17 @@ typedef struct drm32_mga_init { int func; - u32 sarea_priv_offset; + u32 sarea_priv_offset; int chipset; - int sgram; + int sgram; unsigned int maccess; - unsigned int fb_cpp; + unsigned int fb_cpp; unsigned int front_offset, front_pitch; - unsigned int back_offset, back_pitch; - unsigned int depth_cpp; - unsigned int depth_offset, depth_pitch; - unsigned int texture_offset[MGA_NR_TEX_HEAPS]; - unsigned int texture_size[MGA_NR_TEX_HEAPS]; + unsigned int back_offset, back_pitch; + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; + unsigned int texture_offset[MGA_NR_TEX_HEAPS]; + unsigned int texture_size[MGA_NR_TEX_HEAPS]; u32 fb_offset; u32 mmio_offset; u32 status_offset; @@ -64,10 +64,10 @@ static int compat_mga_init(struct file *file, unsigned int cmd, drm_mga_init32_t init32; drm_mga_init_t __user *init; int err = 0, i; - + if (copy_from_user(&init32, (void __user *)arg, sizeof(init32))) return -EFAULT; - + init = compat_alloc_user_space(sizeof(*init)); if (!access_ok(VERIFY_WRITE, init, sizeof(*init)) || __put_user(init32.func, &init->func) @@ -90,42 +90,43 @@ static int compat_mga_init(struct file *file, unsigned int cmd, || __put_user(init32.primary_offset, &init->primary_offset) || __put_user(init32.buffers_offset, &init->buffers_offset)) return -EFAULT; - - for (i=0; itexture_offset[i]); - err |= __put_user(init32.texture_size[i], &init->texture_size[i]); + + for (i = 0; i < MGA_NR_TEX_HEAPS; i++) { + err |= + __put_user(init32.texture_offset[i], + &init->texture_offset[i]); + err |= + __put_user(init32.texture_size[i], &init->texture_size[i]); } if (err) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_MGA_INIT, (unsigned long) init); + DRM_IOCTL_MGA_INIT, (unsigned long)init); } - typedef struct drm_mga_getparam32 { int param; u32 value; } drm_mga_getparam32_t; - static int compat_mga_getparam(struct file *file, unsigned int cmd, unsigned long arg) { drm_mga_getparam32_t getparam32; drm_mga_getparam_t __user *getparam; - + if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32))) return -EFAULT; getparam = compat_alloc_user_space(sizeof(*getparam)); if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam)) || __put_user(getparam32.param, &getparam->param) - || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value)) + || __put_user((void __user *)(unsigned long)getparam32.value, + &getparam->value)) return -EFAULT; - return drm_ioctl(file->f_dentry->d_inode, file, + return drm_ioctl(file->f_dentry->d_inode, file, DRM_IOCTL_MGA_GETPARAM, (unsigned long)getparam); } @@ -182,14 +183,12 @@ static int compat_mga_dma_bootstrap(struct file *file, unsigned int cmd, &dma_bootstrap->secondary_bin_count) || __get_user(dma_bootstrap32.secondary_bin_size, &dma_bootstrap->secondary_bin_size) - || __get_user(dma_bootstrap32.agp_mode, - &dma_bootstrap->agp_mode) - || __get_user(dma_bootstrap32.agp_size, - &dma_bootstrap->agp_size)) + || __get_user(dma_bootstrap32.agp_mode, &dma_bootstrap->agp_mode) + || __get_user(dma_bootstrap32.agp_size, &dma_bootstrap->agp_size)) return -EFAULT; if (copy_to_user((void __user *)arg, &dma_bootstrap32, - sizeof(dma_bootstrap32))) + sizeof(dma_bootstrap32))) return -EFAULT; return 0; @@ -210,8 +209,7 @@ drm_ioctl_compat_t *mga_compat_ioctls[] = { * \param arg user argument. * \return zero on success or negative number on failure. */ -long mga_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg) +long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int nr = DRM_IOCTL_NR(cmd); drm_ioctl_compat_t *fn = NULL; @@ -219,13 +217,13 @@ long mga_compat_ioctl(struct file *filp, unsigned int cmd, if (nr < DRM_COMMAND_BASE) return drm_compat_ioctl(filp, cmd, arg); - + if (nr < DRM_COMMAND_BASE + DRM_ARRAY_SIZE(mga_compat_ioctls)) fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE]; lock_kernel(); /* XXX for now */ if (fn != NULL) - ret = (*fn)(filp, cmd, arg); + ret = (*fn) (filp, cmd, arg); else ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); unlock_kernel(); diff --git a/drivers/char/drm/mga_irq.c b/drivers/char/drm/mga_irq.c index 52eaa4e788f..eb964402417 100644 --- a/drivers/char/drm/mga_irq.c +++ b/drivers/char/drm/mga_irq.c @@ -1,7 +1,7 @@ /* mga_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,19 +35,18 @@ #include "mga_drm.h" #include "mga_drv.h" -irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; int status; int handled = 0; status = MGA_READ(MGA_STATUS); /* VBLANK interrupt */ - if ( status & MGA_VLINEPEN ) { - MGA_WRITE( MGA_ICLEAR, MGA_VLINEICLR ); + if (status & MGA_VLINEPEN) { + MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR); atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); drm_vbl_send_signals(dev); @@ -57,15 +56,14 @@ irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) /* SOFTRAP interrupt */ if (status & MGA_SOFTRAPEN) { const u32 prim_start = MGA_READ(MGA_PRIMADDRESS); - const u32 prim_end = MGA_READ(MGA_PRIMEND); - + const u32 prim_end = MGA_READ(MGA_PRIMEND); MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR); /* In addition to clearing the interrupt-pending bit, we * have to write to MGA_PRIMEND to re-start the DMA operation. */ - if ( (prim_start & ~0x03) != (prim_end & ~0x03) ) { + if ((prim_start & ~0x03) != (prim_end & ~0x03)) { MGA_WRITE(MGA_PRIMEND, prim_end); } @@ -74,24 +72,24 @@ irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS ) handled = 1; } - if ( handled ) { + if (handled) { return IRQ_HANDLED; } return IRQ_NONE; } -int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; @@ -122,29 +120,29 @@ void mga_driver_irq_preinstall(drm_device_t * dev) drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; /* Disable *all* interrupts */ - MGA_WRITE( MGA_IEN, 0 ); + MGA_WRITE(MGA_IEN, 0); /* Clear bits if they're already high */ - MGA_WRITE( MGA_ICLEAR, ~0 ); + MGA_WRITE(MGA_ICLEAR, ~0); } void mga_driver_irq_postinstall(drm_device_t * dev) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - DRM_INIT_WAITQUEUE( &dev_priv->fence_queue ); + DRM_INIT_WAITQUEUE(&dev_priv->fence_queue); /* Turn on vertical blank interrupt and soft trap interrupt. */ MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); } -void mga_driver_irq_uninstall( drm_device_t *dev ) { - drm_mga_private_t *dev_priv = - (drm_mga_private_t *)dev->dev_private; +void mga_driver_irq_uninstall(drm_device_t * dev) +{ + drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ MGA_WRITE(MGA_IEN, 0); - + dev->irq_enabled = 0; } diff --git a/drivers/char/drm/mga_state.c b/drivers/char/drm/mga_state.c index 05bbb471937..15114f8aa46 100644 --- a/drivers/char/drm/mga_state.c +++ b/drivers/char/drm/mga_state.c @@ -41,15 +41,15 @@ * DMA hardware state programming functions */ -static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, - drm_clip_rect_t *box ) +static void mga_emit_clip_rect(drm_mga_private_t * dev_priv, + drm_clip_rect_t * box) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; unsigned int pitch = dev_priv->front_pitch; DMA_LOCALS; - BEGIN_DMA( 2 ); + BEGIN_DMA(2); /* Force reset of DWGCTL on G400 (eliminates clip disable bit). */ @@ -61,101 +61,90 @@ static void mga_emit_clip_rect( drm_mga_private_t *dev_priv, } DMA_BLOCK(MGA_DMAPAD, 0x00000000, MGA_CXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YTOP, box->y1 * pitch, - MGA_YBOT, (box->y2 - 1) * pitch); + MGA_YTOP, box->y1 * pitch, MGA_YBOT, (box->y2 - 1) * pitch); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; - BEGIN_DMA( 3 ); + BEGIN_DMA(3); - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); + DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); - DMA_BLOCK( MGA_FCOL, ctx->fcol, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_FCOL, ctx->fcol, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; DMA_LOCALS; - BEGIN_DMA( 4 ); + BEGIN_DMA(4); - DMA_BLOCK( MGA_DSTORG, ctx->dstorg, - MGA_MACCESS, ctx->maccess, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DSTORG, ctx->dstorg, + MGA_MACCESS, ctx->maccess, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); - DMA_BLOCK( MGA_ALPHACTRL, ctx->alphactrl, - MGA_FOGCOL, ctx->fogcolor, - MGA_WFLAG, ctx->wflag, - MGA_ZORG, dev_priv->depth_offset ); + DMA_BLOCK(MGA_ALPHACTRL, ctx->alphactrl, + MGA_FOGCOL, ctx->fogcolor, + MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); - DMA_BLOCK( MGA_WFLAG1, ctx->wflag, - MGA_TDUALSTAGE0, ctx->tdualstage0, - MGA_TDUALSTAGE1, ctx->tdualstage1, - MGA_FCOL, ctx->fcol ); + DMA_BLOCK(MGA_WFLAG1, ctx->wflag, + MGA_TDUALSTAGE0, ctx->tdualstage0, + MGA_TDUALSTAGE1, ctx->tdualstage1, MGA_FCOL, ctx->fcol); - DMA_BLOCK( MGA_STENCIL, ctx->stencil, - MGA_STENCILCTL, ctx->stencilctl, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_STENCIL, ctx->stencil, + MGA_STENCILCTL, ctx->stencilctl, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_tex0(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; DMA_LOCALS; - BEGIN_DMA( 4 ); + BEGIN_DMA(4); - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, tex->texctl2, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR24, tex->texwidth ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR24, tex->texwidth); - DMA_BLOCK( MGA_WR34, tex->texheight, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WR34, tex->texheight, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, MGA_DMAPAD, 0x00000000); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_tex0(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0]; @@ -164,42 +153,38 @@ static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ - BEGIN_DMA( 6 ); + BEGIN_DMA(6); - DMA_BLOCK( MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC, + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000); - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, MGA_G400_WR_MAGIC ); + DMA_BLOCK(MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, MGA_WR52, MGA_G400_WR_MAGIC); - DMA_BLOCK( MGA_WR60, MGA_G400_WR_MAGIC, - MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, - MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WR60, MGA_G400_WR_MAGIC, + MGA_WR54, tex->texwidth | MGA_G400_WR_MAGIC, + MGA_WR62, tex->texheight | MGA_G400_WR_MAGIC, + MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_TEXTRANS, 0x0000ffff, MGA_TEXTRANSHIGH, 0x0000ffff); ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_tex1(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1]; @@ -208,55 +193,51 @@ static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg, */ /* tex->texctl, tex->texctl2); */ - BEGIN_DMA( 5 ); + BEGIN_DMA(5); - DMA_BLOCK( MGA_TEXCTL2, (tex->texctl2 | - MGA_MAP1_ENABLE | - MGA_G400_TC2_MAGIC), - MGA_TEXCTL, tex->texctl, - MGA_TEXFILTER, tex->texfilter, - MGA_TEXBORDERCOL, tex->texbordercol ); + DMA_BLOCK(MGA_TEXCTL2, (tex->texctl2 | + MGA_MAP1_ENABLE | + MGA_G400_TC2_MAGIC), + MGA_TEXCTL, tex->texctl, + MGA_TEXFILTER, tex->texfilter, + MGA_TEXBORDERCOL, tex->texbordercol); - DMA_BLOCK( MGA_TEXORG, tex->texorg, - MGA_TEXORG1, tex->texorg1, - MGA_TEXORG2, tex->texorg2, - MGA_TEXORG3, tex->texorg3 ); + DMA_BLOCK(MGA_TEXORG, tex->texorg, + MGA_TEXORG1, tex->texorg1, + MGA_TEXORG2, tex->texorg2, MGA_TEXORG3, tex->texorg3); - DMA_BLOCK( MGA_TEXORG4, tex->texorg4, - MGA_TEXWIDTH, tex->texwidth, - MGA_TEXHEIGHT, tex->texheight, - MGA_WR49, 0x00000000 ); + DMA_BLOCK(MGA_TEXORG4, tex->texorg4, + MGA_TEXWIDTH, tex->texwidth, + MGA_TEXHEIGHT, tex->texheight, MGA_WR49, 0x00000000); - DMA_BLOCK( MGA_WR57, 0x00000000, - MGA_WR53, 0x00000000, - MGA_WR61, 0x00000000, - MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC ); + DMA_BLOCK(MGA_WR57, 0x00000000, + MGA_WR53, 0x00000000, + MGA_WR61, 0x00000000, + MGA_WR52, tex->texwidth | MGA_G400_WR_MAGIC); - DMA_BLOCK( MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, - MGA_TEXTRANS, 0x0000ffff, - MGA_TEXTRANSHIGH, 0x0000ffff, - MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC ); + DMA_BLOCK(MGA_WR60, tex->texheight | MGA_G400_WR_MAGIC, + MGA_TEXTRANS, 0x0000ffff, + MGA_TEXTRANSHIGH, 0x0000ffff, + MGA_TEXCTL2, tex->texctl2 | MGA_G400_TC2_MAGIC); ADVANCE_DMA(); } -static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g200_emit_pipe(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; DMA_LOCALS; - BEGIN_DMA( 3 ); + BEGIN_DMA(3); - DMA_BLOCK( MGA_WIADDR, MGA_WMODE_SUSPEND, - MGA_WVRTXSZ, 0x00000007, - MGA_WFLAG, 0x00000000, - MGA_WR24, 0x00000000 ); + DMA_BLOCK(MGA_WIADDR, MGA_WMODE_SUSPEND, + MGA_WVRTXSZ, 0x00000007, + MGA_WFLAG, 0x00000000, MGA_WR24, 0x00000000); - DMA_BLOCK( MGA_WR25, 0x00000100, - MGA_WR34, 0x00000000, - MGA_WR42, 0x0000ffff, - MGA_WR60, 0x0000ffff ); + DMA_BLOCK(MGA_WR25, 0x00000100, + MGA_WR34, 0x00000000, + MGA_WR42, 0x0000ffff, MGA_WR60, 0x0000ffff); /* Padding required to to hardware bug. */ @@ -269,7 +250,7 @@ static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv ) ADVANCE_DMA(); } -static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) +static __inline__ void mga_g400_emit_pipe(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int pipe = sarea_priv->warp_pipe; @@ -277,68 +258,64 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) /* printk("mga_g400_emit_pipe %x\n", pipe); */ - BEGIN_DMA( 10 ); + BEGIN_DMA(10); - DMA_BLOCK( MGA_WIADDR2, MGA_WMODE_SUSPEND, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WIADDR2, MGA_WMODE_SUSPEND, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - if ( pipe & MGA_T2 ) { - DMA_BLOCK( MGA_WVRTXSZ, 0x00001e09, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + if (pipe & MGA_T2) { + DMA_BLOCK(MGA_WVRTXSZ, 0x00001e09, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x1e000000 ); + DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x1e000000); } else { - if ( dev_priv->warp_pipe & MGA_T2 ) { + if (dev_priv->warp_pipe & MGA_T2) { /* Flush the WARP pipe */ - DMA_BLOCK( MGA_YDST, 0x00000000, - MGA_FXLEFT, 0x00000000, - MGA_FXRIGHT, 0x00000001, - MGA_DWGCTL, MGA_DWGCTL_FLUSH ); - - DMA_BLOCK( MGA_LEN + MGA_EXEC, 0x00000001, - MGA_DWGSYNC, 0x00007000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_LEN + MGA_EXEC, 0x00000000 ); - - DMA_BLOCK( MGA_TEXCTL2, (MGA_DUALTEX | - MGA_G400_TC2_MAGIC), - MGA_LEN + MGA_EXEC, 0x00000000, - MGA_TEXCTL2, MGA_G400_TC2_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_YDST, 0x00000000, + MGA_FXLEFT, 0x00000000, + MGA_FXRIGHT, 0x00000001, + MGA_DWGCTL, MGA_DWGCTL_FLUSH); + + DMA_BLOCK(MGA_LEN + MGA_EXEC, 0x00000001, + MGA_DWGSYNC, 0x00007000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_LEN + MGA_EXEC, 0x00000000); + + DMA_BLOCK(MGA_TEXCTL2, (MGA_DUALTEX | + MGA_G400_TC2_MAGIC), + MGA_LEN + MGA_EXEC, 0x00000000, + MGA_TEXCTL2, MGA_G400_TC2_MAGIC, + MGA_DMAPAD, 0x00000000); } - DMA_BLOCK( MGA_WVRTXSZ, 0x00001807, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WVRTXSZ, 0x00001807, + MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x00000000, - MGA_WACCEPTSEQ, 0x18000000 ); + DMA_BLOCK(MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x00000000, + MGA_WACCEPTSEQ, 0x18000000); } - DMA_BLOCK( MGA_WFLAG, 0x00000000, - MGA_WFLAG1, 0x00000000, - MGA_WR56, MGA_G400_WR56_MAGIC, - MGA_DMAPAD, 0x00000000 ); + DMA_BLOCK(MGA_WFLAG, 0x00000000, + MGA_WFLAG1, 0x00000000, + MGA_WR56, MGA_G400_WR56_MAGIC, MGA_DMAPAD, 0x00000000); - DMA_BLOCK( MGA_WR49, 0x00000000, /* tex0 */ - MGA_WR57, 0x00000000, /* tex0 */ - MGA_WR53, 0x00000000, /* tex1 */ - MGA_WR61, 0x00000000 ); /* tex1 */ + DMA_BLOCK(MGA_WR49, 0x00000000, /* tex0 */ + MGA_WR57, 0x00000000, /* tex0 */ + MGA_WR53, 0x00000000, /* tex1 */ + MGA_WR61, 0x00000000); /* tex1 */ - DMA_BLOCK( MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ - MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ - MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ - MGA_WR60, MGA_G400_WR_MAGIC ); /* tex1 height */ + DMA_BLOCK(MGA_WR54, MGA_G400_WR_MAGIC, /* tex0 width */ + MGA_WR62, MGA_G400_WR_MAGIC, /* tex0 height */ + MGA_WR52, MGA_G400_WR_MAGIC, /* tex1 width */ + MGA_WR60, MGA_G400_WR_MAGIC); /* tex1 height */ /* Padding required to to hardware bug */ DMA_BLOCK(MGA_DMAPAD, 0xffffffff, @@ -350,71 +327,70 @@ static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv ) ADVANCE_DMA(); } -static void mga_g200_emit_state( drm_mga_private_t *dev_priv ) +static void mga_g200_emit_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g200_emit_pipe( dev_priv ); + if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { + mga_g200_emit_pipe(dev_priv); dev_priv->warp_pipe = sarea_priv->warp_pipe; } - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g200_emit_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) { + mga_g200_emit_context(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g200_emit_tex0( dev_priv ); + if (dirty & MGA_UPLOAD_TEX0) { + mga_g200_emit_tex0(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } } -static void mga_g400_emit_state( drm_mga_private_t *dev_priv ) +static void mga_g400_emit_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int multitex = sarea_priv->warp_pipe & MGA_T2; - if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) { - mga_g400_emit_pipe( dev_priv ); + if (sarea_priv->warp_pipe != dev_priv->warp_pipe) { + mga_g400_emit_pipe(dev_priv); dev_priv->warp_pipe = sarea_priv->warp_pipe; } - if ( dirty & MGA_UPLOAD_CONTEXT ) { - mga_g400_emit_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) { + mga_g400_emit_context(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT; } - if ( dirty & MGA_UPLOAD_TEX0 ) { - mga_g400_emit_tex0( dev_priv ); + if (dirty & MGA_UPLOAD_TEX0) { + mga_g400_emit_tex0(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX0; } - if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) { - mga_g400_emit_tex1( dev_priv ); + if ((dirty & MGA_UPLOAD_TEX1) && multitex) { + mga_g400_emit_tex1(dev_priv); sarea_priv->dirty &= ~MGA_UPLOAD_TEX1; } } - /* ================================================================ * SAREA state verification */ /* Disallow all write destinations except the front and backbuffer. */ -static int mga_verify_context( drm_mga_private_t *dev_priv ) +static int mga_verify_context(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_context_regs_t *ctx = &sarea_priv->context_state; - if ( ctx->dstorg != dev_priv->front_offset && - ctx->dstorg != dev_priv->back_offset ) { - DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n", - ctx->dstorg, dev_priv->front_offset, - dev_priv->back_offset ); + if (ctx->dstorg != dev_priv->front_offset && + ctx->dstorg != dev_priv->back_offset) { + DRM_ERROR("*** bad DSTORG: %x (front %x, back %x)\n\n", + ctx->dstorg, dev_priv->front_offset, + dev_priv->back_offset); ctx->dstorg = 0; return DRM_ERR(EINVAL); } @@ -424,7 +400,7 @@ static int mga_verify_context( drm_mga_private_t *dev_priv ) /* Disallow texture reads from PCI space. */ -static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) +static int mga_verify_tex(drm_mga_private_t * dev_priv, int unit) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit]; @@ -432,9 +408,8 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK); - if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) { - DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n", - tex->texorg, unit ); + if (org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI)) { + DRM_ERROR("*** bad TEXORG: 0x%x, unit %d\n", tex->texorg, unit); tex->texorg = 0; return DRM_ERR(EINVAL); } @@ -442,73 +417,70 @@ static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit ) return 0; } -static int mga_verify_state( drm_mga_private_t *dev_priv ) +static int mga_verify_state(drm_mga_private_t * dev_priv) { drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; int ret = 0; - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if ( dirty & MGA_UPLOAD_CONTEXT ) - ret |= mga_verify_context( dev_priv ); + if (dirty & MGA_UPLOAD_CONTEXT) + ret |= mga_verify_context(dev_priv); - if ( dirty & MGA_UPLOAD_TEX0 ) - ret |= mga_verify_tex( dev_priv, 0 ); + if (dirty & MGA_UPLOAD_TEX0) + ret |= mga_verify_tex(dev_priv, 0); if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { if (dirty & MGA_UPLOAD_TEX1) ret |= mga_verify_tex(dev_priv, 1); - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES ); + if (dirty & MGA_UPLOAD_PIPE) + ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES); } else { - if ( dirty & MGA_UPLOAD_PIPE ) - ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES ); + if (dirty & MGA_UPLOAD_PIPE) + ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES); } - return ( ret == 0 ); + return (ret == 0); } -static int mga_verify_iload( drm_mga_private_t *dev_priv, - unsigned int dstorg, unsigned int length ) +static int mga_verify_iload(drm_mga_private_t * dev_priv, + unsigned int dstorg, unsigned int length) { - if ( dstorg < dev_priv->texture_offset || - dstorg + length > (dev_priv->texture_offset + - dev_priv->texture_size) ) { - DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg ); + if (dstorg < dev_priv->texture_offset || + dstorg + length > (dev_priv->texture_offset + + dev_priv->texture_size)) { + DRM_ERROR("*** bad iload DSTORG: 0x%x\n", dstorg); return DRM_ERR(EINVAL); } - if ( length & MGA_ILOAD_MASK ) { - DRM_ERROR( "*** bad iload length: 0x%x\n", - length & MGA_ILOAD_MASK ); + if (length & MGA_ILOAD_MASK) { + DRM_ERROR("*** bad iload length: 0x%x\n", + length & MGA_ILOAD_MASK); return DRM_ERR(EINVAL); } return 0; } -static int mga_verify_blit( drm_mga_private_t *dev_priv, - unsigned int srcorg, unsigned int dstorg ) +static int mga_verify_blit(drm_mga_private_t * dev_priv, + unsigned int srcorg, unsigned int dstorg) { - if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || - (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) { - DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n", - srcorg, dstorg ); + if ((srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) || + (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM)) { + DRM_ERROR("*** bad blit: src=0x%x dst=0x%x\n", srcorg, dstorg); return DRM_ERR(EINVAL); } return 0; } - /* ================================================================ * */ -static void mga_dma_dispatch_clear( drm_device_t *dev, - drm_mga_clear_t *clear ) +static void mga_dma_dispatch_clear(drm_device_t * dev, drm_mga_clear_t * clear) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -517,92 +489,86 @@ static void mga_dma_dispatch_clear( drm_device_t *dev, int nbox = sarea_priv->nbox; int i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_DMA( 1 ); + BEGIN_DMA(1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); ADVANCE_DMA(); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2); - if ( clear->flags & MGA_FRONT ) { - BEGIN_DMA( 2 ); + if (clear->flags & MGA_FRONT) { + BEGIN_DMA(2); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->front_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->front_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } + if (clear->flags & MGA_BACK) { + BEGIN_DMA(2); - if ( clear->flags & MGA_BACK ) { - BEGIN_DMA( 2 ); - - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->color_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->color_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_color, - MGA_DSTORG, dev_priv->back_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_color, + MGA_DSTORG, dev_priv->back_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } - if ( clear->flags & MGA_DEPTH ) { - BEGIN_DMA( 2 ); + if (clear->flags & MGA_DEPTH) { + BEGIN_DMA(2); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, clear->depth_mask, - MGA_YDSTLEN, (box->y1 << 16) | height, - MGA_FXBNDRY, (box->x2 << 16) | box->x1 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, clear->depth_mask, + MGA_YDSTLEN, (box->y1 << 16) | height, + MGA_FXBNDRY, (box->x2 << 16) | box->x1); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_FCOL, clear->clear_depth, - MGA_DSTORG, dev_priv->depth_offset, - MGA_DWGCTL + MGA_EXEC, - dev_priv->clear_cmd ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_FCOL, clear->clear_depth, + MGA_DSTORG, dev_priv->depth_offset, + MGA_DWGCTL + MGA_EXEC, dev_priv->clear_cmd); ADVANCE_DMA(); } } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); FLUSH_DMA(); } -static void mga_dma_dispatch_swap( drm_device_t *dev ) +static void mga_dma_dispatch_swap(drm_device_t * dev) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -611,56 +577,52 @@ static void mga_dma_dispatch_swap( drm_device_t *dev ) int nbox = sarea_priv->nbox; int i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); sarea_priv->last_frame.head = dev_priv->prim.tail; sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap; - BEGIN_DMA( 4 + nbox ); + BEGIN_DMA(4 + nbox); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DSTORG, dev_priv->front_offset, - MGA_MACCESS, dev_priv->maccess, - MGA_SRCORG, dev_priv->back_offset, - MGA_AR5, dev_priv->front_pitch ); + DMA_BLOCK(MGA_DSTORG, dev_priv->front_offset, + MGA_MACCESS, dev_priv->maccess, + MGA_SRCORG, dev_priv->back_offset, + MGA_AR5, dev_priv->front_pitch); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_PLNWT, 0xffffffff, - MGA_DWGCTL, MGA_DWGCTL_COPY ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_PLNWT, 0xffffffff, MGA_DWGCTL, MGA_DWGCTL_COPY); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { drm_clip_rect_t *box = &pbox[i]; u32 height = box->y2 - box->y1; u32 start = box->y1 * dev_priv->front_pitch; - DRM_DEBUG( " from=%d,%d to=%d,%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" from=%d,%d to=%d,%d\n", + box->x1, box->y1, box->x2, box->y2); - DMA_BLOCK( MGA_AR0, start + box->x2 - 1, - MGA_AR3, start + box->x1, - MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, - MGA_YDSTLEN + MGA_EXEC, - (box->y1 << 16) | height ); + DMA_BLOCK(MGA_AR0, start + box->x2 - 1, + MGA_AR3, start + box->x1, + MGA_FXBNDRY, ((box->x2 - 1) << 16) | box->x1, + MGA_YDSTLEN + MGA_EXEC, (box->y1 << 16) | height); } - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); FLUSH_DMA(); - DRM_DEBUG( "%s... done.\n", __FUNCTION__ ); + DRM_DEBUG("%s... done.\n", __FUNCTION__); } -static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) +static void mga_dma_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -669,20 +631,20 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) u32 length = (u32) buf->used; int i = 0; DMA_LOCALS; - DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used ); + DRM_DEBUG("vertex: buf=%d used=%d\n", buf->idx, buf->used); - if ( buf->used ) { + if (buf->used) { buf_priv->dispatched = 1; - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < sarea_priv->nbox) { + mga_emit_clip_rect(dev_priv, + &sarea_priv->boxes[i]); } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); DMA_BLOCK(MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, @@ -692,23 +654,23 @@ static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf ) dev_priv->dma_access)); ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); + } while (++i < sarea_priv->nbox); } - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); + if (buf_priv->discard) { + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } FLUSH_DMA(); } -static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, - unsigned int start, unsigned int end ) +static void mga_dma_dispatch_indices(drm_device_t * dev, drm_buf_t * buf, + unsigned int start, unsigned int end) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; @@ -716,20 +678,20 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, u32 address = (u32) buf->bus_address; int i = 0; DMA_LOCALS; - DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end ); + DRM_DEBUG("indices: buf=%d start=%d end=%d\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { buf_priv->dispatched = 1; - MGA_EMIT_STATE( dev_priv, sarea_priv->dirty ); + MGA_EMIT_STATE(dev_priv, sarea_priv->dirty); do { - if ( i < sarea_priv->nbox ) { - mga_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < sarea_priv->nbox) { + mga_emit_clip_rect(dev_priv, + &sarea_priv->boxes[i]); } - BEGIN_DMA( 1 ); + BEGIN_DMA(1); DMA_BLOCK(MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, @@ -738,16 +700,16 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, dev_priv->dma_access)); ADVANCE_DMA(); - } while ( ++i < sarea_priv->nbox ); + } while (++i < sarea_priv->nbox); } - if ( buf_priv->discard ) { - AGE_BUFFER( buf_priv ); + if (buf_priv->discard) { + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } FLUSH_DMA(); @@ -756,61 +718,55 @@ static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf, /* This copies a 64 byte aligned agp region to the frambuffer with a * standard blit, the ioctl needs to do checking. */ -static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf, - unsigned int dstorg, unsigned int length ) +static void mga_dma_dispatch_iload(drm_device_t * dev, drm_buf_t * buf, + unsigned int dstorg, unsigned int length) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_buf_priv_t *buf_priv = buf->dev_private; drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state; - u32 srcorg = buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; + u32 srcorg = + buf->bus_address | dev_priv->dma_access | MGA_SRCMAP_SYSMEM; u32 y2; DMA_LOCALS; - DRM_DEBUG( "buf=%d used=%d\n", buf->idx, buf->used ); + DRM_DEBUG("buf=%d used=%d\n", buf->idx, buf->used); y2 = length / 64; - BEGIN_DMA( 5 ); + BEGIN_DMA(5); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DSTORG, dstorg, - MGA_MACCESS, 0x00000000, - MGA_SRCORG, srcorg, - MGA_AR5, 64 ); + DMA_BLOCK(MGA_DSTORG, dstorg, + MGA_MACCESS, 0x00000000, MGA_SRCORG, srcorg, MGA_AR5, 64); - DMA_BLOCK( MGA_PITCH, 64, - MGA_PLNWT, 0xffffffff, - MGA_DMAPAD, 0x00000000, - MGA_DWGCTL, MGA_DWGCTL_COPY ); + DMA_BLOCK(MGA_PITCH, 64, + MGA_PLNWT, 0xffffffff, + MGA_DMAPAD, 0x00000000, MGA_DWGCTL, MGA_DWGCTL_COPY); - DMA_BLOCK( MGA_AR0, 63, - MGA_AR3, 0, - MGA_FXBNDRY, (63 << 16) | 0, - MGA_YDSTLEN + MGA_EXEC, y2 ); + DMA_BLOCK(MGA_AR0, 63, + MGA_AR3, 0, + MGA_FXBNDRY, (63 << 16) | 0, MGA_YDSTLEN + MGA_EXEC, y2); - DMA_BLOCK( MGA_PLNWT, ctx->plnwt, - MGA_SRCORG, dev_priv->front_offset, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_PLNWT, ctx->plnwt, + MGA_SRCORG, dev_priv->front_offset, + MGA_PITCH, dev_priv->front_pitch, MGA_DWGSYNC, 0x00007000); ADVANCE_DMA(); - AGE_BUFFER( buf_priv ); + AGE_BUFFER(buf_priv); buf->pending = 0; buf->used = 0; buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); FLUSH_DMA(); } -static void mga_dma_dispatch_blit( drm_device_t *dev, - drm_mga_blit_t *blit ) +static void mga_dma_dispatch_blit(drm_device_t * dev, drm_mga_blit_t * blit) { drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -819,26 +775,24 @@ static void mga_dma_dispatch_blit( drm_device_t *dev, int nbox = sarea_priv->nbox; u32 scandir = 0, i; DMA_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_DMA( 4 + nbox ); + BEGIN_DMA(4 + nbox); - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_DWGSYNC, 0x00007100, - MGA_DWGSYNC, 0x00007000 ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_DMAPAD, 0x00000000, + MGA_DWGSYNC, 0x00007100, MGA_DWGSYNC, 0x00007000); - DMA_BLOCK( MGA_DWGCTL, MGA_DWGCTL_COPY, - MGA_PLNWT, blit->planemask, - MGA_SRCORG, blit->srcorg, - MGA_DSTORG, blit->dstorg ); + DMA_BLOCK(MGA_DWGCTL, MGA_DWGCTL_COPY, + MGA_PLNWT, blit->planemask, + MGA_SRCORG, blit->srcorg, MGA_DSTORG, blit->dstorg); - DMA_BLOCK( MGA_SGN, scandir, - MGA_MACCESS, dev_priv->maccess, - MGA_AR5, blit->ydir * blit->src_pitch, - MGA_PITCH, blit->dst_pitch ); + DMA_BLOCK(MGA_SGN, scandir, + MGA_MACCESS, dev_priv->maccess, + MGA_AR5, blit->ydir * blit->src_pitch, + MGA_PITCH, blit->dst_pitch); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int srcx = pbox[i].x1 + blit->delta_sx; int srcy = pbox[i].y1 + blit->delta_sy; int dstx = pbox[i].x1 + blit->delta_dx; @@ -847,52 +801,51 @@ static void mga_dma_dispatch_blit( drm_device_t *dev, int w = pbox[i].x2 - pbox[i].x1 - 1; int start; - if ( blit->ydir == -1 ) { + if (blit->ydir == -1) { srcy = blit->height - srcy - 1; } start = srcy * blit->src_pitch + srcx; - DMA_BLOCK( MGA_AR0, start + w, - MGA_AR3, start, - MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), - MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h ); + DMA_BLOCK(MGA_AR0, start + w, + MGA_AR3, start, + MGA_FXBNDRY, ((dstx + w) << 16) | (dstx & 0xffff), + MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h); } /* Do something to flush AGP? */ /* Force reset of DWGCTL */ - DMA_BLOCK( MGA_DMAPAD, 0x00000000, - MGA_PLNWT, ctx->plnwt, - MGA_PITCH, dev_priv->front_pitch, - MGA_DWGCTL, ctx->dwgctl ); + DMA_BLOCK(MGA_DMAPAD, 0x00000000, + MGA_PLNWT, ctx->plnwt, + MGA_PITCH, dev_priv->front_pitch, MGA_DWGCTL, ctx->dwgctl); ADVANCE_DMA(); } - /* ================================================================ * */ -static int mga_dma_clear( DRM_IOCTL_ARGS ) +static int mga_dma_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_clear_t clear; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_mga_clear_t __user *)data, sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_mga_clear_t __user *) data, + sizeof(clear)); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_clear( dev, &clear ); + mga_dma_dispatch_clear(dev, &clear); /* Make sure we restore the 3D state next time. */ @@ -901,20 +854,20 @@ static int mga_dma_clear( DRM_IOCTL_ARGS ) return 0; } -static int mga_dma_swap( DRM_IOCTL_ARGS ) +static int mga_dma_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_swap( dev ); + mga_dma_dispatch_swap(dev); /* Make sure we restore the 3D state next time. */ @@ -923,7 +876,7 @@ static int mga_dma_swap( DRM_IOCTL_ARGS ) return 0; } -static int mga_dma_vertex( DRM_IOCTL_ARGS ) +static int mga_dma_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; @@ -932,37 +885,38 @@ static int mga_dma_vertex( DRM_IOCTL_ARGS ) drm_mga_buf_priv_t *buf_priv; drm_mga_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, - (drm_mga_vertex_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, + (drm_mga_vertex_t __user *) data, + sizeof(vertex)); - if(vertex.idx < 0 || vertex.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (vertex.idx < 0 || vertex.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; buf->used = vertex.used; buf_priv->discard = vertex.discard; - if ( !mga_verify_state( dev_priv ) ) { - if ( vertex.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); + if (!mga_verify_state(dev_priv)) { + if (vertex.discard) { + if (buf_priv->dispatched == 1) + AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_vertex( dev, buf ); + mga_dma_dispatch_vertex(dev, buf); return 0; } -static int mga_dma_indices( DRM_IOCTL_ARGS ) +static int mga_dma_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; @@ -971,37 +925,38 @@ static int mga_dma_indices( DRM_IOCTL_ARGS ) drm_mga_buf_priv_t *buf_priv; drm_mga_indices_t indices; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( indices, - (drm_mga_indices_t __user *)data, - sizeof(indices) ); + DRM_COPY_FROM_USER_IOCTL(indices, + (drm_mga_indices_t __user *) data, + sizeof(indices)); - if(indices.idx < 0 || indices.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (indices.idx < 0 || indices.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[indices.idx]; buf_priv = buf->dev_private; buf_priv->discard = indices.discard; - if ( !mga_verify_state( dev_priv ) ) { - if ( indices.discard ) { - if ( buf_priv->dispatched == 1 ) - AGE_BUFFER( buf_priv ); + if (!mga_verify_state(dev_priv)) { + if (indices.discard) { + if (buf_priv->dispatched == 1) + AGE_BUFFER(buf_priv); buf_priv->dispatched = 0; - mga_freelist_put( dev, buf ); + mga_freelist_put(dev, buf); } return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_indices( dev, buf, indices.start, indices.end ); + mga_dma_dispatch_indices(dev, buf, indices.start, indices.end); return 0; } -static int mga_dma_iload( DRM_IOCTL_ARGS ) +static int mga_dma_iload(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -1009,32 +964,34 @@ static int mga_dma_iload( DRM_IOCTL_ARGS ) drm_buf_t *buf; drm_mga_buf_priv_t *buf_priv; drm_mga_iload_t iload; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( iload, (drm_mga_iload_t __user *)data, sizeof(iload) ); + DRM_COPY_FROM_USER_IOCTL(iload, (drm_mga_iload_t __user *) data, + sizeof(iload)); #if 0 - if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { - if ( MGA_DMA_DEBUG ) - DRM_INFO( "%s: -EBUSY\n", __FUNCTION__ ); + if (mga_do_wait_for_idle(dev_priv) < 0) { + if (MGA_DMA_DEBUG) + DRM_INFO("%s: -EBUSY\n", __FUNCTION__); return DRM_ERR(EBUSY); } #endif - if(iload.idx < 0 || iload.idx > dma->buf_count) return DRM_ERR(EINVAL); + if (iload.idx < 0 || iload.idx > dma->buf_count) + return DRM_ERR(EINVAL); buf = dma->buflist[iload.idx]; buf_priv = buf->dev_private; - if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) { - mga_freelist_put( dev, buf ); + if (mga_verify_iload(dev_priv, iload.dstorg, iload.length)) { + mga_freelist_put(dev, buf); return DRM_ERR(EINVAL); } - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length ); + mga_dma_dispatch_iload(dev, buf, iload.dstorg, iload.length); /* Make sure we restore the 3D state next time. */ @@ -1043,27 +1000,28 @@ static int mga_dma_iload( DRM_IOCTL_ARGS ) return 0; } -static int mga_dma_blit( DRM_IOCTL_ARGS ) +static int mga_dma_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_mga_blit_t blit; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( blit, (drm_mga_blit_t __user *)data, sizeof(blit) ); + DRM_COPY_FROM_USER_IOCTL(blit, (drm_mga_blit_t __user *) data, + sizeof(blit)); - if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS) sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS; - if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) ) + if (mga_verify_blit(dev_priv, blit.srcorg, blit.dstorg)) return DRM_ERR(EINVAL); - WRAP_TEST_WITH_RETURN( dev_priv ); + WRAP_TEST_WITH_RETURN(dev_priv); - mga_dma_dispatch_blit( dev, &blit ); + mga_dma_dispatch_blit(dev, &blit); /* Make sure we restore the 3D state next time. */ @@ -1072,24 +1030,24 @@ static int mga_dma_blit( DRM_IOCTL_ARGS ) return 0; } -static int mga_getparam( DRM_IOCTL_ARGS ) +static int mga_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_mga_private_t *dev_priv = dev->dev_private; drm_mga_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_mga_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_mga_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case MGA_PARAM_IRQ_NR: value = dev->irq; break; @@ -1100,11 +1058,11 @@ static int mga_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } @@ -1132,11 +1090,10 @@ static int mga_set_fence(DRM_IOCTL_ARGS) BEGIN_DMA(1); DMA_BLOCK(MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000, - MGA_DMAPAD, 0x00000000, - MGA_SOFTRAP, 0x00000000); + MGA_DMAPAD, 0x00000000, MGA_SOFTRAP, 0x00000000); ADVANCE_DMA(); - if (DRM_COPY_TO_USER( (u32 __user *) data, & temp, sizeof(u32))) { + if (DRM_COPY_TO_USER((u32 __user *) data, &temp, sizeof(u32))) { DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } @@ -1159,9 +1116,9 @@ static int mga_wait_fence(DRM_IOCTL_ARGS) DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - mga_driver_fence_wait(dev, & fence); + mga_driver_fence_wait(dev, &fence); - if (DRM_COPY_TO_USER( (u32 __user *) data, & fence, sizeof(u32))) { + if (DRM_COPY_TO_USER((u32 __user *) data, &fence, sizeof(u32))) { DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } @@ -1170,19 +1127,32 @@ static int mga_wait_fence(DRM_IOCTL_ARGS) } drm_ioctl_desc_t mga_ioctls[] = { - [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}, - [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}, - [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}, + [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0} + , + [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1} + , }; diff --git a/drivers/char/drm/mga_ucode.h b/drivers/char/drm/mga_ucode.h index fa0f82ec9fa..b611e27470e 100644 --- a/drivers/char/drm/mga_ucode.h +++ b/drivers/char/drm/mga_ucode.h @@ -40,11606 +40,11606 @@ static unsigned char warp_g200_tgz[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x98, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x98, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x81, 0x04, -0x89, 0x04, -0x01, 0x04, -0x09, 0x04, + 0x81, 0x04, + 0x89, 0x04, + 0x01, 0x04, + 0x09, 0x04, -0xC9, 0x41, 0xC0, 0xEC, -0x11, 0x04, -0x00, 0xE0, + 0xC9, 0x41, 0xC0, 0xEC, + 0x11, 0x04, + 0x00, 0xE0, -0x41, 0xCC, 0x41, 0xCD, -0x49, 0xCC, 0x49, 0xCD, + 0x41, 0xCC, 0x41, 0xCD, + 0x49, 0xCC, 0x49, 0xCD, -0xD1, 0x41, 0xC0, 0xEC, -0x51, 0xCC, 0x51, 0xCD, + 0xD1, 0x41, 0xC0, 0xEC, + 0x51, 0xCC, 0x51, 0xCD, -0x80, 0x04, -0x10, 0x04, -0x08, 0x04, -0x00, 0xE0, + 0x80, 0x04, + 0x10, 0x04, + 0x08, 0x04, + 0x00, 0xE0, -0x00, 0xCC, 0xC0, 0xCD, -0xD1, 0x49, 0xC0, 0xEC, + 0x00, 0xCC, 0xC0, 0xCD, + 0xD1, 0x49, 0xC0, 0xEC, -0x8A, 0x1F, 0x20, 0xE9, -0x8B, 0x3F, 0x20, 0xE9, + 0x8A, 0x1F, 0x20, 0xE9, + 0x8B, 0x3F, 0x20, 0xE9, -0x41, 0x3C, 0x41, 0xAD, -0x49, 0x3C, 0x49, 0xAD, + 0x41, 0x3C, 0x41, 0xAD, + 0x49, 0x3C, 0x49, 0xAD, -0x10, 0xCC, 0x10, 0xCD, -0x08, 0xCC, 0x08, 0xCD, + 0x10, 0xCC, 0x10, 0xCD, + 0x08, 0xCC, 0x08, 0xCD, -0xB9, 0x41, 0x49, 0xBB, -0x1F, 0xF0, 0x41, 0xCD, + 0xB9, 0x41, 0x49, 0xBB, + 0x1F, 0xF0, 0x41, 0xCD, -0x51, 0x3C, 0x51, 0xAD, -0x00, 0x98, 0x80, 0xE9, + 0x51, 0x3C, 0x51, 0xAD, + 0x00, 0x98, 0x80, 0xE9, -0x72, 0x80, 0x07, 0xEA, -0x24, 0x1F, 0x20, 0xE9, + 0x72, 0x80, 0x07, 0xEA, + 0x24, 0x1F, 0x20, 0xE9, -0x15, 0x41, 0x49, 0xBD, -0x1D, 0x41, 0x51, 0xBD, + 0x15, 0x41, 0x49, 0xBD, + 0x1D, 0x41, 0x51, 0xBD, -0x2E, 0x41, 0x2A, 0xB8, -0x34, 0x53, 0xA0, 0xE8, + 0x2E, 0x41, 0x2A, 0xB8, + 0x34, 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0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x7F, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x7F, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgza[] = { -0x00, 0x98, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x98, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x81, 0x04, -0x89, 0x04, -0x01, 0x04, -0x09, 0x04, + 0x81, 0x04, + 0x89, 0x04, + 0x01, 0x04, + 0x09, 0x04, -0xC9, 0x41, 0xC0, 0xEC, -0x11, 0x04, -0x00, 0xE0, + 0xC9, 0x41, 0xC0, 0xEC, + 0x11, 0x04, + 0x00, 0xE0, -0x41, 0xCC, 0x41, 0xCD, -0x49, 0xCC, 0x49, 0xCD, + 0x41, 0xCC, 0x41, 0xCD, + 0x49, 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-0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x77, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x77, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x74, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x74, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzaf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 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0x16, 0x28, 0x20, 0xE9, + 0x1D, 0x3B, 0x20, 0xE9, -0x1E, 0x2B, 0x20, 0xE9, -0x2B, 0x32, 0x20, 0xE9, + 0x1E, 0x2B, 0x20, 0xE9, + 0x2B, 0x32, 0x20, 0xE9, -0x1C, 0x23, 0x20, 0xE9, -0x57, 0x36, 0x20, 0xE9, + 0x1C, 0x23, 0x20, 0xE9, + 0x57, 0x36, 0x20, 0xE9, -0x00, 0x80, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x90, 0xE2, -0x00, 0xE0, + 0xFF, 0x80, 0xC0, 0xE9, + 0x90, 0xE2, + 0x00, 0xE0, -0x74, 0xFF, 0x20, 0xEA, -0x19, 0xC8, 0xC1, 0xCD, + 0x74, 0xFF, 0x20, 0xEA, + 0x19, 0xC8, 0xC1, 0xCD, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x9F, 0x41, 0x49, 0xBD, -0x00, 0x80, 0x00, 0xE8, + 0x9F, 0x41, 0x49, 0xBD, + 0x00, 0x80, 0x00, 0xE8, -0x25, 0x41, 0x49, 0xBD, -0x2D, 0x41, 0x51, 0xBD, + 0x25, 0x41, 0x49, 0xBD, + 0x2D, 0x41, 0x51, 0xBD, -0x0D, 0x80, 0x07, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x0D, 0x80, 0x07, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x35, 0x40, 0x48, 0xBD, -0x3D, 0x40, 0x50, 0xBD, + 0x35, 0x40, 0x48, 0xBD, + 0x3D, 0x40, 0x50, 0xBD, -0x00, 0x80, 0x00, 0xE8, -0x25, 0x30, -0x2D, 0x30, + 0x00, 0x80, 0x00, 0xE8, + 0x25, 0x30, + 0x2D, 0x30, -0x35, 0x30, -0xB5, 0x30, -0xBD, 0x30, -0x3D, 0x30, + 0x35, 0x30, + 0xB5, 0x30, + 0xBD, 0x30, + 0x3D, 0x30, -0x9C, 0xA7, 0x5B, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x9C, 0xA7, 0x5B, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x73, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x73, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x71, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x71, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x6E, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x6E, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 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0x68, -0x97, 0x25, -0x00, 0x80, 0x00, 0xE8, + 0xB3, 0x68, + 0x97, 0x25, + 0x00, 0x80, 0x00, 0xE8, -0x33, 0xC0, 0x33, 0xAF, -0x3C, 0x27, 0x4F, 0xE9, + 0x33, 0xC0, 0x33, 0xAF, + 0x3C, 0x27, 0x4F, 0xE9, -0x17, 0x50, 0x56, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x17, 0x50, 0x56, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x37, 0x0F, 0x5C, 0x9F, -0x00, 0xE0, -0x2F, 0x20, + 0x37, 0x0F, 0x5C, 0x9F, + 0x00, 0xE0, + 0x2F, 0x20, -0x00, 0x80, 0x00, 0xE8, -0x28, 0x19, 0x60, 0xEC, + 0x00, 0x80, 0x00, 0xE8, + 0x28, 0x19, 0x60, 0xEC, -0xB3, 0x05, -0x00, 0xE0, -0x00, 0x80, 0x00, 0xE8, + 0xB3, 0x05, + 0x00, 0xE0, + 0x00, 0x80, 0x00, 0xE8, -0x23, 0x3B, 0x33, 0xAD, -0x00, 0x80, 0x00, 0xE8, + 0x23, 0x3B, 0x33, 0xAD, + 0x00, 0x80, 0x00, 0xE8, -0x17, 0x26, 0x17, 0xDF, -0x35, 0x17, 0x4F, 0xE9, + 0x17, 0x26, 0x17, 0xDF, + 0x35, 0x17, 0x4F, 0xE9, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x39, 0x37, 0x4F, 0xE9, + 0x00, 0x80, 0x00, 0xE8, + 0x39, 0x37, 0x4F, 0xE9, -0x2F, 0x2F, 0x17, 0xAF, -0x00, 0x80, 0x00, 0xE8, + 0x2F, 0x2F, 0x17, 0xAF, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x31, 0x80, 0x4F, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x31, 0x80, 0x4F, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x57, 0x39, 0x20, 0xE9, + 0x00, 0x80, 0x00, 0xE8, + 0x57, 0x39, 0x20, 0xE9, -0x16, 0x28, 0x20, 0xE9, -0x1D, 0x3B, 0x20, 0xE9, + 0x16, 0x28, 0x20, 0xE9, + 0x1D, 0x3B, 0x20, 0xE9, -0x1E, 0x2B, 0x20, 0xE9, -0x2B, 0x32, 0x20, 0xE9, + 0x1E, 0x2B, 0x20, 0xE9, + 0x2B, 0x32, 0x20, 0xE9, -0x1C, 0x23, 0x20, 0xE9, -0x57, 0x36, 0x20, 0xE9, + 0x1C, 0x23, 0x20, 0xE9, + 0x57, 0x36, 0x20, 0xE9, -0x00, 0x80, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x90, 0xE2, -0x00, 0xE0, + 0xFF, 0x80, 0xC0, 0xE9, + 0x90, 0xE2, + 0x00, 0xE0, -0x78, 0xFF, 0x20, 0xEA, -0x19, 0xC8, 0xC1, 0xCD, + 0x78, 0xFF, 0x20, 0xEA, + 0x19, 0xC8, 0xC1, 0xCD, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x9F, 0x41, 0x49, 0xBD, -0x00, 0x80, 0x00, 0xE8, + 0x9F, 0x41, 0x49, 0xBD, + 0x00, 0x80, 0x00, 0xE8, -0x25, 0x41, 0x49, 0xBD, -0x2D, 0x41, 0x51, 0xBD, + 0x25, 0x41, 0x49, 0xBD, + 0x2D, 0x41, 0x51, 0xBD, -0x0D, 0x80, 0x07, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x0D, 0x80, 0x07, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x35, 0x40, 0x48, 0xBD, -0x3D, 0x40, 0x50, 0xBD, + 0x35, 0x40, 0x48, 0xBD, + 0x3D, 0x40, 0x50, 0xBD, -0x00, 0x80, 0x00, 0xE8, -0x25, 0x30, -0x2D, 0x30, + 0x00, 0x80, 0x00, 0xE8, + 0x25, 0x30, + 0x2D, 0x30, -0x35, 0x30, -0xB5, 0x30, -0xBD, 0x30, -0x3D, 0x30, + 0x35, 0x30, + 0xB5, 0x30, + 0xBD, 0x30, + 0x3D, 0x30, -0x9C, 0xA7, 0x5B, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x9C, 0xA7, 0x5B, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x77, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x77, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x75, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x75, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x72, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x72, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzs[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 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0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsa[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 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0xE9, + 0x1D, 0x3B, 0x20, 0xE9, -0x1E, 0x2B, 0x20, 0xE9, -0x2B, 0x32, 0x20, 0xE9, + 0x1E, 0x2B, 0x20, 0xE9, + 0x2B, 0x32, 0x20, 0xE9, -0x1C, 0x23, 0x20, 0xE9, -0x57, 0x36, 0x20, 0xE9, + 0x1C, 0x23, 0x20, 0xE9, + 0x57, 0x36, 0x20, 0xE9, -0x00, 0x80, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x90, 0xE2, -0x00, 0xE0, + 0xFF, 0x80, 0xC0, 0xE9, + 0x90, 0xE2, + 0x00, 0xE0, -0x68, 0xFF, 0x20, 0xEA, -0x19, 0xC8, 0xC1, 0xCD, + 0x68, 0xFF, 0x20, 0xEA, + 0x19, 0xC8, 0xC1, 0xCD, -0x1F, 0xD7, 0x18, 0xBD, -0x3F, 0xD7, 0x22, 0xBD, + 0x1F, 0xD7, 0x18, 0xBD, + 0x3F, 0xD7, 0x22, 0xBD, -0x9F, 0x41, 0x49, 0xBD, -0x00, 0x80, 0x00, 0xE8, + 0x9F, 0x41, 0x49, 0xBD, + 0x00, 0x80, 0x00, 0xE8, -0x25, 0x41, 0x49, 0xBD, -0x2D, 0x41, 0x51, 0xBD, + 0x25, 0x41, 0x49, 0xBD, + 0x2D, 0x41, 0x51, 0xBD, -0x0D, 0x80, 0x07, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x0D, 0x80, 0x07, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x35, 0x40, 0x48, 0xBD, -0x3D, 0x40, 0x50, 0xBD, + 0x35, 0x40, 0x48, 0xBD, + 0x3D, 0x40, 0x50, 0xBD, -0x00, 0x80, 0x00, 0xE8, -0x25, 0x30, -0x2D, 0x30, + 0x00, 0x80, 0x00, 0xE8, + 0x25, 0x30, + 0x2D, 0x30, -0x35, 0x30, -0xB5, 0x30, -0xBD, 0x30, -0x3D, 0x30, + 0x35, 0x30, + 0xB5, 0x30, + 0xBD, 0x30, + 0x3D, 0x30, -0x9C, 0xA7, 0x5B, 0x9F, -0x00, 0x80, 0x00, 0xE8, + 0x9C, 0xA7, 0x5B, 0x9F, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x67, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x67, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x65, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x65, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x62, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x62, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsaf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x98, 0xA0, 0xE9, -0x40, 0x40, 0xD8, 0xEC, + 0x00, 0x98, 0xA0, 0xE9, + 0x40, 0x40, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 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0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x5D, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x5D, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g200_tgzsf[] = { -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 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0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0x67, 0xFF, 0x0A, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x67, 0xFF, 0x0A, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0xC9, 0x41, 0xC8, 0xEC, -0x42, 0xE1, -0x00, 0xE0, + 0xC9, 0x41, 0xC8, 0xEC, + 0x42, 0xE1, + 0x00, 0xE0, -0x65, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x65, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, -0xC8, 0x40, 0xC0, 0xEC, -0x00, 0x80, 0x00, 0xE8, + 0xC8, 0x40, 0xC0, 0xEC, + 0x00, 0x80, 0x00, 0xE8, -0x62, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0x62, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, + 0x00, 0x80, 0x00, 0xE8, }; static unsigned char warp_g400_t2gz[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 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0xCF, -0x79, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x79, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzaf[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 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0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzf[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, -0x32, 0x41, 0x51, 0xBF, -0x3A, 0x41, 0x61, 0xBF, + 0x32, 0x41, 0x51, 0xBF, + 0x3A, 0x41, 0x61, 0xBF, -0xC3, 0x6B, -0xD3, 0x6B, -0x00, 0x8A, 0x98, 0xE9, + 0xC3, 0x6B, + 0xD3, 0x6B, + 0x00, 0x8A, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x53, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x53, 0xA0, 0xE8, -0xAD, 0xEE, 0x23, 0x9F, -0x00, 0xE0, -0x51, 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0xCF, + 0x59, 0x80, 0x59, 0xCF, -0x68, 0x33, 0x68, 0xCF, -0x49, 0x3B, 0x49, 0xCF, + 0x68, 0x33, 0x68, 0xCF, + 0x49, 0x3B, 0x49, 0xCF, -0xBB, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xBB, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x78, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x78, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzs[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x0A, 0x40, 0x50, 0xBF, -0x2A, 0x40, 0x60, 0xBF, + 0x0A, 0x40, 0x50, 0xBF, + 0x2A, 0x40, 0x60, 0xBF, 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0xE8, -0x34, 0x80, 0x34, 0xBD, -0x3C, 0x80, 0x3C, 0xBD, + 0x34, 0x80, 0x34, 0xBD, + 0x3C, 0x80, 0x3C, 0xBD, -0x33, 0xD7, 0x0B, 0xBD, -0x3B, 0xD7, 0x1B, 0xBD, + 0x33, 0xD7, 0x0B, 0xBD, + 0x3B, 0xD7, 0x1B, 0xBD, -0x48, 0x80, 0x48, 0xCF, -0x59, 0x80, 0x59, 0xCF, + 0x48, 0x80, 0x48, 0xCF, + 0x59, 0x80, 0x59, 0xCF, -0x68, 0x33, 0x68, 0xCF, -0x49, 0x3B, 0x49, 0xCF, + 0x68, 0x33, 0x68, 0xCF, + 0x49, 0x3B, 0x49, 0xCF, -0xB2, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xB2, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x70, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x70, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_t2gzsa[] = { -0x00, 0x8A, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x8A, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, 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0xBD, -0x48, 0x80, 0x48, 0xCF, -0x59, 0x80, 0x59, 0xCF, + 0x48, 0x80, 0x48, 0xCF, + 0x59, 0x80, 0x59, 0xCF, -0x68, 0x33, 0x68, 0xCF, -0x49, 0x3B, 0x49, 0xCF, + 0x68, 0x33, 0x68, 0xCF, + 0x49, 0x3B, 0x49, 0xCF, -0xAD, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xAD, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x58, 0x33, 0x58, 0xCF, -0x69, 0x3B, 0x69, 0xCF, + 0x58, 0x33, 0x58, 0xCF, + 0x69, 0x3B, 0x69, 0xCF, -0x6B, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x6B, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgz[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 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0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x9D, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x9D, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgza[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 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-0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x99, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x99, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzaf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 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0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzs[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x4B, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x4B, 0xA0, 0xE8, -0xAD, 0xEE, 0x29, 0x9F, -0x00, 0xE0, -0x49, 0x04, + 0xAD, 0xEE, 0x29, 0x9F, + 0x00, 0xE0, + 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+ 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsa[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, -0xCB, 0x6B, -0x00, 0x88, 0x98, 0xE9, + 0xC3, 0x6B, + 0xCB, 0x6B, + 0x00, 0x88, 0x98, 0xE9, -0x73, 0x7B, 0xC8, 0xEC, -0x96, 0xE2, -0x41, 0x04, + 0x73, 0x7B, 0xC8, 0xEC, + 0x96, 0xE2, + 0x41, 0x04, -0x7B, 0x43, 0xA0, 0xE8, -0x73, 0x4B, 0xA0, 0xE8, + 0x7B, 0x43, 0xA0, 0xE8, + 0x73, 0x4B, 0xA0, 0xE8, -0xAD, 0xEE, 0x29, 0x9F, -0x00, 0xE0, -0x49, 0x04, + 0xAD, 0xEE, 0x29, 0x9F, + 0x00, 0xE0, + 0x49, 0x04, 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0x4F, 0xCF, -0x56, 0x33, 0x56, 0xCF, -0x47, 0x3B, 0x47, 0xCF, + 0x56, 0x33, 0x56, 0xCF, + 0x47, 0x3B, 0x47, 0xCF, -0xC5, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xC5, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x8B, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x8B, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsaf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 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0x47, 0x3B, 0x47, 0xCF, -0xC1, 0xFF, 0x20, 0xEA, -0x00, 0x80, 0x00, 0xE8, + 0xC1, 0xFF, 0x20, 0xEA, + 0x00, 0x80, 0x00, 0xE8, -0x4E, 0x33, 0x4E, 0xCF, -0x57, 0x3B, 0x57, 0xCF, + 0x4E, 0x33, 0x4E, 0xCF, + 0x57, 0x3B, 0x57, 0xCF, -0x87, 0xFF, 0x20, 0xEA, -0x57, 0xC0, 0xBF, 0xEA, + 0x87, 0xFF, 0x20, 0xEA, + 0x57, 0xC0, 0xBF, 0xEA, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, }; static unsigned char warp_g400_tgzsf[] = { -0x00, 0x88, 0x98, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0x00, 0x88, 0x98, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x00, 0x80, 0xA0, 0xE9, -0x00, 0x00, 0xD8, 0xEC, + 0x00, 0x80, 0xA0, 0xE9, + 0x00, 0x00, 0xD8, 0xEC, -0xFF, 0x80, 0xC0, 0xE9, -0x00, 0x80, 0x00, 0xE8, + 0xFF, 0x80, 0xC0, 0xE9, + 0x00, 0x80, 0x00, 0xE8, -0x22, 0x40, 0x48, 0xBF, -0x2A, 0x40, 0x50, 0xBF, + 0x22, 0x40, 0x48, 0xBF, + 0x2A, 0x40, 0x50, 0xBF, -0x32, 0x41, 0x49, 0xBF, -0x3A, 0x41, 0x51, 0xBF, + 0x32, 0x41, 0x49, 0xBF, + 0x3A, 0x41, 0x51, 0xBF, -0xC3, 0x6B, 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index 55ccc8a0ac2..d67f4925fba 100644 --- a/drivers/char/drm/mga_warp.c +++ b/drivers/char/drm/mga_warp.c @@ -33,8 +33,7 @@ #include "mga_drv.h" #include "mga_ucode.h" - -#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ +#define MGA_WARP_CODE_ALIGN 256 /* in bytes */ #define WARP_UCODE_SIZE( which ) \ ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN) @@ -49,33 +48,30 @@ do { \ } while (0) static const unsigned int mga_warp_g400_microcode_size = - (WARP_UCODE_SIZE(warp_g400_tgz) + - WARP_UCODE_SIZE(warp_g400_tgza) + - WARP_UCODE_SIZE(warp_g400_tgzaf) + - WARP_UCODE_SIZE(warp_g400_tgzf) + - WARP_UCODE_SIZE(warp_g400_tgzs) + - WARP_UCODE_SIZE(warp_g400_tgzsa) + - WARP_UCODE_SIZE(warp_g400_tgzsaf) + - WARP_UCODE_SIZE(warp_g400_tgzsf) + - WARP_UCODE_SIZE(warp_g400_t2gz) + - WARP_UCODE_SIZE(warp_g400_t2gza) + - WARP_UCODE_SIZE(warp_g400_t2gzaf) + - WARP_UCODE_SIZE(warp_g400_t2gzf) + - WARP_UCODE_SIZE(warp_g400_t2gzs) + - WARP_UCODE_SIZE(warp_g400_t2gzsa) + - WARP_UCODE_SIZE(warp_g400_t2gzsaf) + - WARP_UCODE_SIZE(warp_g400_t2gzsf)); + (WARP_UCODE_SIZE(warp_g400_tgz) + + WARP_UCODE_SIZE(warp_g400_tgza) + + WARP_UCODE_SIZE(warp_g400_tgzaf) + + WARP_UCODE_SIZE(warp_g400_tgzf) + + WARP_UCODE_SIZE(warp_g400_tgzs) + + WARP_UCODE_SIZE(warp_g400_tgzsa) + + WARP_UCODE_SIZE(warp_g400_tgzsaf) + + WARP_UCODE_SIZE(warp_g400_tgzsf) + + WARP_UCODE_SIZE(warp_g400_t2gz) + + WARP_UCODE_SIZE(warp_g400_t2gza) + + WARP_UCODE_SIZE(warp_g400_t2gzaf) + + WARP_UCODE_SIZE(warp_g400_t2gzf) + + WARP_UCODE_SIZE(warp_g400_t2gzs) + + WARP_UCODE_SIZE(warp_g400_t2gzsa) + + WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf)); static const unsigned int mga_warp_g200_microcode_size = - (WARP_UCODE_SIZE(warp_g200_tgz) + - WARP_UCODE_SIZE(warp_g200_tgza) + - WARP_UCODE_SIZE(warp_g200_tgzaf) + - WARP_UCODE_SIZE(warp_g200_tgzf) + - WARP_UCODE_SIZE(warp_g200_tgzs) + - WARP_UCODE_SIZE(warp_g200_tgzsa) + - WARP_UCODE_SIZE(warp_g200_tgzsaf) + - WARP_UCODE_SIZE(warp_g200_tgzsf)); - + (WARP_UCODE_SIZE(warp_g200_tgz) + + WARP_UCODE_SIZE(warp_g200_tgza) + + WARP_UCODE_SIZE(warp_g200_tgzaf) + + WARP_UCODE_SIZE(warp_g200_tgzf) + + WARP_UCODE_SIZE(warp_g200_tgzs) + + WARP_UCODE_SIZE(warp_g200_tgzsa) + + WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf)); unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) { @@ -90,36 +86,35 @@ unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv) } } -static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv ) +static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv) { unsigned char *vcbase = dev_priv->warp->handle; unsigned long pcbase = dev_priv->warp->offset; - memset( dev_priv->warp_pipe_phys, 0, - sizeof(dev_priv->warp_pipe_phys) ); - - WARP_UCODE_INSTALL( warp_g400_tgz, MGA_WARP_TGZ ); - WARP_UCODE_INSTALL( warp_g400_tgzf, MGA_WARP_TGZF ); - WARP_UCODE_INSTALL( warp_g400_tgza, MGA_WARP_TGZA ); - WARP_UCODE_INSTALL( warp_g400_tgzaf, MGA_WARP_TGZAF ); - WARP_UCODE_INSTALL( warp_g400_tgzs, MGA_WARP_TGZS ); - WARP_UCODE_INSTALL( warp_g400_tgzsf, MGA_WARP_TGZSF ); - WARP_UCODE_INSTALL( warp_g400_tgzsa, MGA_WARP_TGZSA ); - WARP_UCODE_INSTALL( warp_g400_tgzsaf, MGA_WARP_TGZSAF ); - - WARP_UCODE_INSTALL( warp_g400_t2gz, MGA_WARP_T2GZ ); - WARP_UCODE_INSTALL( warp_g400_t2gzf, MGA_WARP_T2GZF ); - WARP_UCODE_INSTALL( warp_g400_t2gza, MGA_WARP_T2GZA ); - WARP_UCODE_INSTALL( warp_g400_t2gzaf, MGA_WARP_T2GZAF ); - WARP_UCODE_INSTALL( warp_g400_t2gzs, MGA_WARP_T2GZS ); - WARP_UCODE_INSTALL( warp_g400_t2gzsf, MGA_WARP_T2GZSF ); - WARP_UCODE_INSTALL( warp_g400_t2gzsa, MGA_WARP_T2GZSA ); - WARP_UCODE_INSTALL( warp_g400_t2gzsaf, MGA_WARP_T2GZSAF ); + memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys)); + + WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ); + WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF); + WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA); + WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF); + WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS); + WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF); + WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA); + WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF); + + WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ); + WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF); + WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA); + WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF); + WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS); + WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF); + WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA); + WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF); return 0; } -static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) +static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv) { unsigned char *vcbase = dev_priv->warp->handle; unsigned long pcbase = dev_priv->warp->offset; @@ -138,7 +133,7 @@ static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv ) return 0; } -int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) +int mga_warp_install_microcode(drm_mga_private_t * dev_priv) { const unsigned int size = mga_warp_microcode_size(dev_priv); @@ -154,7 +149,7 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) case MGA_CARD_TYPE_G550: return mga_warp_install_g400_microcode(dev_priv); case MGA_CARD_TYPE_G200: - return mga_warp_install_g200_microcode( dev_priv ); + return mga_warp_install_g200_microcode(dev_priv); default: return DRM_ERR(EINVAL); } @@ -162,13 +157,13 @@ int mga_warp_install_microcode( drm_mga_private_t *dev_priv ) #define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE) -int mga_warp_init( drm_mga_private_t *dev_priv ) +int mga_warp_init(drm_mga_private_t * dev_priv) { u32 wmisc; /* FIXME: Get rid of these damned magic numbers... */ - switch ( dev_priv->chipset ) { + switch (dev_priv->chipset) { case MGA_CARD_TYPE_G400: case MGA_CARD_TYPE_G550: MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND); @@ -177,21 +172,20 @@ int mga_warp_init( drm_mga_private_t *dev_priv ) MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000); break; case MGA_CARD_TYPE_G200: - MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND ); - MGA_WRITE( MGA_WGETMSB, 0x1606 ); - MGA_WRITE( MGA_WVRTXSZ, 7 ); + MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND); + MGA_WRITE(MGA_WGETMSB, 0x1606); + MGA_WRITE(MGA_WVRTXSZ, 7); break; default: return DRM_ERR(EINVAL); } - MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE | - MGA_WMASTER_ENABLE | - MGA_WCACHEFLUSH_ENABLE) ); - wmisc = MGA_READ( MGA_WMISC ); - if ( wmisc != WMISC_EXPECTED ) { - DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n", - wmisc, WMISC_EXPECTED ); + MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE | + MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE)); + wmisc = MGA_READ(MGA_WMISC); + if (wmisc != WMISC_EXPECTED) { + DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n", + wmisc, WMISC_EXPECTED); return DRM_ERR(EINVAL); } diff --git a/drivers/char/drm/r128_cce.c b/drivers/char/drm/r128_cce.c index ac3ea2bc9b2..7452753d4d0 100644 --- a/drivers/char/drm/r128_cce.c +++ b/drivers/char/drm/r128_cce.c @@ -80,7 +80,7 @@ static u32 r128_cce_microcode[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static int R128_READ_PLL(drm_device_t *dev, int addr) +static int R128_READ_PLL(drm_device_t * dev, int addr) { drm_r128_private_t *dev_priv = dev->dev_private; @@ -89,106 +89,105 @@ static int R128_READ_PLL(drm_device_t *dev, int addr) } #if R128_FIFO_DEBUG -static void r128_status( drm_r128_private_t *dev_priv ) +static void r128_status(drm_r128_private_t * dev_priv) { - printk( "GUI_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_GUI_STAT ) ); - printk( "PM4_STAT = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_STAT ) ); - printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); - printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); - printk( "PM4_MICRO_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); - printk( "PM4_BUFFER_CNTL = 0x%08x\n", - (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); + printk("GUI_STAT = 0x%08x\n", + (unsigned int)R128_READ(R128_GUI_STAT)); + printk("PM4_STAT = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_STAT)); + printk("PM4_BUFFER_DL_WPTR = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR)); + printk("PM4_BUFFER_DL_RPTR = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR)); + printk("PM4_MICRO_CNTL = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_MICRO_CNTL)); + printk("PM4_BUFFER_CNTL = 0x%08x\n", + (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL)); } #endif - /* ================================================================ * Engine, FIFO control */ -static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) +static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) { u32 tmp; int i; - tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; - R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); + tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL; + R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) { return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) +static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) { int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK; + if (slots >= entries) + return 0; + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) +static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) { int i, ret; - ret = r128_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; + ret = r128_do_wait_for_fifo(dev_priv, 64); + if (ret) + return ret; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { - r128_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) { + r128_do_pixcache_flush(dev_priv); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } - /* ================================================================ * CCE control, initialization */ /* Load the microcode for the CCE */ -static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) +static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) { int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - r128_do_wait_for_idle( dev_priv ); + r128_do_wait_for_idle(dev_priv); - R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); - for ( i = 0 ; i < 256 ; i++ ) { - R128_WRITE( R128_PM4_MICROCODE_DATAH, - r128_cce_microcode[i * 2] ); - R128_WRITE( R128_PM4_MICROCODE_DATAL, - r128_cce_microcode[i * 2 + 1] ); + R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); + for (i = 0; i < 256; i++) { + R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); + R128_WRITE(R128_PM4_MICROCODE_DATAL, + r128_cce_microcode[i * 2 + 1]); } } @@ -196,51 +195,51 @@ static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ -static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) +static void r128_do_cce_flush(drm_r128_private_t * dev_priv) { u32 tmp; - tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); + tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE; + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); } /* Wait for the CCE to go idle. */ -int r128_do_cce_idle( drm_r128_private_t *dev_priv ) +int r128_do_cce_idle(drm_r128_private_t * dev_priv) { int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( GET_RING_HEAD( dev_priv ) == dev_priv->ring.tail ) { - int pm4stat = R128_READ( R128_PM4_STAT ); - if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= - dev_priv->cce_fifo_size ) && - !(pm4stat & (R128_PM4_BUSY | - R128_PM4_GUI_ACTIVE)) ) { - return r128_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { + int pm4stat = R128_READ(R128_PM4_STAT); + if (((pm4stat & R128_PM4_FIFOCNT_MASK) >= + dev_priv->cce_fifo_size) && + !(pm4stat & (R128_PM4_BUSY | + R128_PM4_GUI_ACTIVE))) { + return r128_do_pixcache_flush(dev_priv); } } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if R128_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - r128_status( dev_priv ); + DRM_ERROR("failed!\n"); + r128_status(dev_priv); #endif return DRM_ERR(EBUSY); } /* Start the Concurrent Command Engine. */ -static void r128_do_cce_start( drm_r128_private_t *dev_priv ) +static void r128_do_cce_start(drm_r128_private_t * dev_priv) { - r128_do_wait_for_idle( dev_priv ); + r128_do_wait_for_idle(dev_priv); - R128_WRITE( R128_PM4_BUFFER_CNTL, - dev_priv->cce_mode | dev_priv->ring.size_l2qw - | R128_PM4_BUFFER_CNTL_NOUPDATE ); - R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ - R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); + R128_WRITE(R128_PM4_BUFFER_CNTL, + dev_priv->cce_mode | dev_priv->ring.size_l2qw + | R128_PM4_BUFFER_CNTL_NOUPDATE); + R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */ + R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); dev_priv->cce_running = 1; } @@ -249,10 +248,10 @@ static void r128_do_cce_start( drm_r128_private_t *dev_priv ) * commands, so you must wait for the CCE command stream to complete * before calling this routine. */ -static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) +static void r128_do_cce_reset(drm_r128_private_t * dev_priv) { - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); + R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); dev_priv->ring.tail = 0; } @@ -260,122 +259,120 @@ static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) * commands, so you must flush the command stream and wait for the CCE * to go idle before calling this routine. */ -static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) +static void r128_do_cce_stop(drm_r128_private_t * dev_priv) { - R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); - R128_WRITE( R128_PM4_BUFFER_CNTL, - R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE ); + R128_WRITE(R128_PM4_MICRO_CNTL, 0); + R128_WRITE(R128_PM4_BUFFER_CNTL, + R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE); dev_priv->cce_running = 0; } /* Reset the engine. This will stop the CCE if it is running. */ -static int r128_do_engine_reset( drm_device_t *dev ) +static int r128_do_engine_reset(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; - r128_do_pixcache_flush( dev_priv ); + r128_do_pixcache_flush(dev_priv); - clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); - mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); + clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX); + mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL); - R128_WRITE_PLL( R128_MCLK_CNTL, - mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); + R128_WRITE_PLL(R128_MCLK_CNTL, + mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); - gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); + gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL); /* Taken from the sample code - do not change */ - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl | R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); - R128_WRITE( R128_GEN_RESET_CNTL, - gen_reset_cntl & ~R128_SOFT_RESET_GUI ); - R128_READ( R128_GEN_RESET_CNTL ); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); + R128_READ(R128_GEN_RESET_CNTL); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); + R128_READ(R128_GEN_RESET_CNTL); - R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); - R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); - R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); + R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl); + R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); + R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); /* Reset the CCE ring */ - r128_do_cce_reset( dev_priv ); + r128_do_cce_reset(dev_priv); /* The CCE is no longer running after an engine reset */ dev_priv->cce_running = 0; /* Reset any pending vertex, indirect buffers */ - r128_freelist_reset( dev ); + r128_freelist_reset(dev); return 0; } -static void r128_cce_init_ring_buffer( drm_device_t *dev, - drm_r128_private_t *dev_priv ) +static void r128_cce_init_ring_buffer(drm_device_t * dev, + drm_r128_private_t * dev_priv) { u32 ring_start; u32 tmp; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The manual (p. 2) says this address is in "VM space". This * means it's an offset from the start of AGP space. */ #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) + if (!dev_priv->is_pci) ring_start = dev_priv->cce_ring->offset - dev->agp->base; else #endif - ring_start = dev_priv->cce_ring->offset - - (unsigned long)dev->sg->virtual; + ring_start = dev_priv->cce_ring->offset - + (unsigned long)dev->sg->virtual; - R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); + R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); - R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); - R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); + R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); + R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); /* Set watermark control */ - R128_WRITE( R128_PM4_BUFFER_WM_CNTL, - ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) - | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) - | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) - | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); + R128_WRITE(R128_PM4_BUFFER_WM_CNTL, + ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT) + | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT) + | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT) + | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT)); /* Force read. Why? Because it's in the examples... */ - R128_READ( R128_PM4_BUFFER_ADDR ); + R128_READ(R128_PM4_BUFFER_ADDR); /* Turn on bus mastering */ - tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; - R128_WRITE( R128_BUS_CNTL, tmp ); + tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS; + R128_WRITE(R128_BUS_CNTL, tmp); } -static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) +static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) { drm_r128_private_t *dev_priv; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - dev_priv = drm_alloc( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); - if ( dev_priv == NULL ) + dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); + if (dev_priv == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv, 0, sizeof(drm_r128_private_t) ); + memset(dev_priv, 0, sizeof(drm_r128_private_t)); dev_priv->is_pci = init->is_pci; - if ( dev_priv->is_pci && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); + if (dev_priv->is_pci && !dev->sg) { + DRM_ERROR("PCI GART memory not allocated!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); + if (dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { + DRM_DEBUG("TIMEOUT problem!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } @@ -383,23 +380,23 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) /* GH: Simple idle check. */ - atomic_set( &dev_priv->idle_count, 0 ); + atomic_set(&dev_priv->idle_count, 0); /* We don't support anything other than bus-mastering ring mode, * but the ring can be in either AGP or PCI space for the ring * read pointer. */ - if ( ( init->cce_mode != R128_PM4_192BM ) && - ( init->cce_mode != R128_PM4_128BM_64INDBM ) && - ( init->cce_mode != R128_PM4_64BM_128INDBM ) && - ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { - DRM_DEBUG( "Bad cce_mode!\n" ); + if ((init->cce_mode != R128_PM4_192BM) && + (init->cce_mode != R128_PM4_128BM_64INDBM) && + (init->cce_mode != R128_PM4_64BM_128INDBM) && + (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) { + DRM_DEBUG("Bad cce_mode!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } - switch ( init->cce_mode ) { + switch (init->cce_mode) { case R128_PM4_NONPM4: dev_priv->cce_fifo_size = 0; break; @@ -420,7 +417,7 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) break; } - switch ( init->fb_bpp ) { + switch (init->fb_bpp) { case 16: dev_priv->color_fmt = R128_DATATYPE_RGB565; break; @@ -429,12 +426,12 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) dev_priv->color_fmt = R128_DATATYPE_ARGB8888; break; } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - switch ( init->depth_bpp ) { + switch (init->depth_bpp) { case 16: dev_priv->depth_fmt = R128_DATATYPE_RGB565; break; @@ -444,131 +441,130 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; break; } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; - dev_priv->span_offset = init->span_offset; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; + dev_priv->span_offset = init->span_offset; - dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | + dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | (dev_priv->front_offset >> 5)); - dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | + dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | (dev_priv->back_offset >> 5)); - dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | (dev_priv->depth_offset >> 5) | R128_DST_TILE); - dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | + dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | (dev_priv->span_offset >> 5)); DRM_GETSAREA(); - - if(!dev_priv->sarea) { + + if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { + if (!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cce_ring) { + if (!dev_priv->cce_ring) { DRM_ERROR("could not find cce ring region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { + if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } - if ( !dev_priv->is_pci ) { - dev_priv->agp_textures = drm_core_findmap(dev, init->agp_textures_offset); - if(!dev_priv->agp_textures) { + if (!dev_priv->is_pci) { + dev_priv->agp_textures = + drm_core_findmap(dev, init->agp_textures_offset); + if (!dev_priv->agp_textures) { DRM_ERROR("could not find agp texture region!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(EINVAL); } } dev_priv->sarea_priv = - (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - drm_core_ioremap( dev_priv->cce_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cce_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { + if (!dev_priv->is_pci) { + drm_core_ioremap(dev_priv->cce_ring, dev); + drm_core_ioremap(dev_priv->ring_rptr, dev); + drm_core_ioremap(dev->agp_buffer_map, dev); + if (!dev_priv->cce_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { DRM_ERROR("Could not ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(ENOMEM); } } else #endif { - dev_priv->cce_ring->handle = - (void *)dev_priv->cce_ring->offset; + dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = + (void *)dev->agp_buffer_map->offset; } #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) + if (!dev_priv->is_pci) dev_priv->cce_buffers_offset = dev->agp->base; else #endif dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; - dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle + dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; + dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; + dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = 128; dev_priv->sarea_priv->last_frame = 0; - R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); + R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv->sarea_priv->last_dispatch = 0; - R128_WRITE( R128_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); + R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); #if __OS_HAS_AGP - if ( dev_priv->is_pci ) { + if (dev_priv->is_pci) { #endif dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr = 0; - dev_priv->gart_info.is_pcie = 0; + dev_priv->gart_info.is_pcie = 0; if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { - DRM_ERROR( "failed to init PCI GART!\n" ); + DRM_ERROR("failed to init PCI GART!\n"); dev->dev_private = (void *)dev_priv; - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); return DRM_ERR(ENOMEM); } R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); @@ -576,88 +572,92 @@ static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) } #endif - r128_cce_init_ring_buffer( dev, dev_priv ); - r128_cce_load_microcode( dev_priv ); + r128_cce_init_ring_buffer(dev, dev_priv); + r128_cce_load_microcode(dev_priv); dev->dev_private = (void *)dev_priv; - r128_do_engine_reset( dev ); + r128_do_engine_reset(dev); return 0; } -int r128_do_cleanup_cce( drm_device_t *dev ) +int r128_do_cleanup_cce(drm_device_t * dev) { /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); - if ( dev->dev_private ) { + if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - if ( dev_priv->cce_ring != NULL ) - drm_core_ioremapfree( dev_priv->cce_ring, dev ); - if ( dev_priv->ring_rptr != NULL ) - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); - if ( dev->agp_buffer_map != NULL ) - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (!dev_priv->is_pci) { + if (dev_priv->cce_ring != NULL) + drm_core_ioremapfree(dev_priv->cce_ring, dev); + if (dev_priv->ring_rptr != NULL) + drm_core_ioremapfree(dev_priv->ring_rptr, dev); + if (dev->agp_buffer_map != NULL) + drm_core_ioremapfree(dev->agp_buffer_map, dev); } else #endif { - if (dev_priv->gart_info.bus_addr) - if (!drm_ati_pcigart_cleanup( dev, - &dev_priv->gart_info)) - DRM_ERROR( "failed to cleanup PCI GART!\n" ); + if (dev_priv->gart_info.bus_addr) + if (!drm_ati_pcigart_cleanup(dev, + &dev_priv-> + gart_info)) + DRM_ERROR + ("failed to cleanup PCI GART!\n"); } - drm_free( dev->dev_private, sizeof(drm_r128_private_t), - DRM_MEM_DRIVER ); + drm_free(dev->dev_private, sizeof(drm_r128_private_t), + DRM_MEM_DRIVER); dev->dev_private = NULL; } return 0; } -int r128_cce_init( DRM_IOCTL_ARGS ) +int r128_cce_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_init_t init; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_r128_init_t __user *)data, sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, + sizeof(init)); - switch ( init.func ) { + switch (init.func) { case R128_INIT_CCE: - return r128_do_init_cce( dev, &init ); + return r128_do_init_cce(dev, &init); case R128_CLEANUP_CCE: - return r128_do_cleanup_cce( dev ); + return r128_do_cleanup_cce(dev); } return DRM_ERR(EINVAL); } -int r128_cce_start( DRM_IOCTL_ARGS ) +int r128_cce_start(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { - DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ ); + if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { + DRM_DEBUG("%s while CCE running\n", __FUNCTION__); return 0; } - r128_do_cce_start( dev_priv ); + r128_do_cce_start(dev_priv); return 0; } @@ -665,61 +665,63 @@ int r128_cce_start( DRM_IOCTL_ARGS ) /* Stop the CCE. The engine must have been idled before calling this * routine. */ -int r128_cce_stop( DRM_IOCTL_ARGS ) +int r128_cce_stop(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_cce_stop_t stop; int ret; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *)data, sizeof(stop) ); + DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, + sizeof(stop)); /* Flush any pending CCE commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if ( stop.flush ) { - r128_do_cce_flush( dev_priv ); + if (stop.flush) { + r128_do_cce_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if ( stop.idle ) { - ret = r128_do_cce_idle( dev_priv ); - if ( ret ) return ret; + if (stop.idle) { + ret = r128_do_cce_idle(dev_priv); + if (ret) + return ret; } /* Finally, we can turn off the CCE. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CCE is shut down. */ - r128_do_cce_stop( dev_priv ); + r128_do_cce_stop(dev_priv); /* Reset the engine */ - r128_do_engine_reset( dev ); + r128_do_engine_reset(dev); return 0; } /* Just reset the CCE ring. Called as part of an X Server engine reset. */ -int r128_cce_reset( DRM_IOCTL_ARGS ) +int r128_cce_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_DEBUG("%s called before init done\n", __FUNCTION__); return DRM_ERR(EINVAL); } - r128_do_cce_reset( dev_priv ); + r128_do_cce_reset(dev_priv); /* The CCE is no longer running after an engine reset */ dev_priv->cce_running = 0; @@ -727,37 +729,36 @@ int r128_cce_reset( DRM_IOCTL_ARGS ) return 0; } -int r128_cce_idle( DRM_IOCTL_ARGS ) +int r128_cce_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cce_running ) { - r128_do_cce_flush( dev_priv ); + if (dev_priv->cce_running) { + r128_do_cce_flush(dev_priv); } - return r128_do_cce_idle( dev_priv ); + return r128_do_cce_idle(dev_priv); } -int r128_engine_reset( DRM_IOCTL_ARGS ) +int r128_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return r128_do_engine_reset( dev ); + return r128_do_engine_reset(dev); } -int r128_fullscreen( DRM_IOCTL_ARGS ) +int r128_fullscreen(DRM_IOCTL_ARGS) { return DRM_ERR(EINVAL); } - /* ================================================================ * Freelist management */ @@ -765,7 +766,7 @@ int r128_fullscreen( DRM_IOCTL_ARGS ) #define R128_BUFFER_FREE 0 #if 0 -static int r128_freelist_init( drm_device_t *dev ) +static int r128_freelist_init(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; @@ -774,27 +775,26 @@ static int r128_freelist_init( drm_device_t *dev ) drm_r128_freelist_t *entry; int i; - dev_priv->head = drm_alloc( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( dev_priv->head == NULL ) + dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); + if (dev_priv->head == NULL) return DRM_ERR(ENOMEM); - memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); + memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); dev_priv->head->age = R128_BUFFER_USED; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - entry = drm_alloc( sizeof(drm_r128_freelist_t), - DRM_MEM_DRIVER ); - if ( !entry ) return DRM_ERR(ENOMEM); + entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); + if (!entry) + return DRM_ERR(ENOMEM); entry->age = R128_BUFFER_FREE; entry->buf = buf; entry->prev = dev_priv->head; entry->next = dev_priv->head->next; - if ( !entry->next ) + if (!entry->next) dev_priv->tail = entry; buf_priv->discard = 0; @@ -803,7 +803,7 @@ static int r128_freelist_init( drm_device_t *dev ) dev_priv->head->next = entry; - if ( dev_priv->head->next ) + if (dev_priv->head->next) dev_priv->head->next->prev = entry; } @@ -812,7 +812,7 @@ static int r128_freelist_init( drm_device_t *dev ) } #endif -static drm_buf_t *r128_freelist_get( drm_device_t *dev ) +static drm_buf_t *r128_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_r128_private_t *dev_priv = dev->dev_private; @@ -822,20 +822,20 @@ static drm_buf_t *r128_freelist_get( drm_device_t *dev ) /* FIXME: Optimize -- use freelist code */ - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 ) + if (buf->filp == 0) return buf; } - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); + for (t = 0; t < dev_priv->usec_timeout; t++) { + u32 done_age = R128_READ(R128_LAST_DISPATCH_REG); - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->pending && buf_priv->age <= done_age ) { + if (buf->pending && buf_priv->age <= done_age) { /* The buffer has been processed, so it * can now be used. */ @@ -843,63 +843,63 @@ static drm_buf_t *r128_freelist_get( drm_device_t *dev ) return buf; } } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } -void r128_freelist_reset( drm_device_t *dev ) +void r128_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; int i; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; drm_r128_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } - /* ================================================================ * CCE command submission */ -int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) +int r128_wait_ring(drm_r128_private_t * dev_priv, int n) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - r128_update_ring_snapshot( dev_priv ); - if ( ring->space >= n ) + for (i = 0; i < dev_priv->usec_timeout; i++) { + r128_update_ring_snapshot(dev_priv); + if (ring->space >= n) return 0; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } /* FIXME: This is being ignored... */ - DRM_ERROR( "failed!\n" ); + DRM_ERROR("failed!\n"); return DRM_ERR(EBUSY); } -static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) { int i; drm_buf_t *buf; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = r128_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EAGAIN); + for (i = d->granted_count; i < d->request_count; i++) { + buf = r128_freelist_get(dev); + if (!buf) + return DRM_ERR(EAGAIN); buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, + sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, + sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -907,7 +907,7 @@ static int r128_cce_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) return 0; } -int r128_cce_buffers( DRM_IOCTL_ARGS ) +int r128_cce_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -915,33 +915,33 @@ int r128_cce_buffers( DRM_IOCTL_ARGS ) drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } d.granted_count = 0; - if ( d.request_count ) { - ret = r128_cce_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = r128_cce_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } diff --git a/drivers/char/drm/r128_drm.h b/drivers/char/drm/r128_drm.h index b616cd3ed2c..5ddc0320241 100644 --- a/drivers/char/drm/r128_drm.h +++ b/drivers/char/drm/r128_drm.h @@ -93,7 +93,7 @@ #define R128_MAX_TEXTURE_LEVELS 11 #define R128_MAX_TEXTURE_UNITS 2 -#endif /* __R128_SAREA_DEFINES__ */ +#endif /* __R128_SAREA_DEFINES__ */ typedef struct { /* Context state - can be written in one large chunk */ @@ -140,7 +140,6 @@ typedef struct { unsigned int tex_border_color; } drm_r128_texture_regs_t; - typedef struct drm_r128_sarea { /* The channel for communication of state information to the kernel * on firing a vertex buffer. @@ -161,14 +160,13 @@ typedef struct drm_r128_sarea { unsigned int last_frame; unsigned int last_dispatch; - drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS+1]; + drm_tex_region_t tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; unsigned int tex_age[R128_NR_TEX_HEAPS]; int ctx_owner; - int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ - int pfCurrentPage; /* which buffer is being displayed? */ + int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ + int pfCurrentPage; /* which buffer is being displayed? */ } drm_r128_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ @@ -220,7 +218,7 @@ typedef struct drm_r128_sarea { typedef struct drm_r128_init { enum { - R128_INIT_CCE = 0x01, + R128_INIT_CCE = 0x01, R128_CLEANUP_CCE = 0x02 } func; #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) @@ -278,9 +276,9 @@ typedef struct drm_r128_clear { typedef struct drm_r128_vertex { int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ } drm_r128_vertex_t; typedef struct drm_r128_indices { @@ -288,7 +286,7 @@ typedef struct drm_r128_indices { int idx; int start; int end; - int discard; /* Client finished with buffer? */ + int discard; /* Client finished with buffer? */ } drm_r128_indices_t; typedef struct drm_r128_blit { @@ -302,10 +300,10 @@ typedef struct drm_r128_blit { typedef struct drm_r128_depth { enum { - R128_WRITE_SPAN = 0x01, - R128_WRITE_PIXELS = 0x02, - R128_READ_SPAN = 0x03, - R128_READ_PIXELS = 0x04 + R128_WRITE_SPAN = 0x01, + R128_WRITE_PIXELS = 0x02, + R128_READ_SPAN = 0x03, + R128_READ_PIXELS = 0x04 } func; int n; int __user *x; @@ -327,13 +325,13 @@ typedef struct drm_r128_indirect { typedef struct drm_r128_fullscreen { enum { - R128_INIT_FULLSCREEN = 0x01, + R128_INIT_FULLSCREEN = 0x01, R128_CLEANUP_FULLSCREEN = 0x02 } func; } drm_r128_fullscreen_t; /* 2.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ #define R128_PARAM_IRQ_NR 1 diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c index bc446da1b21..4d9224645f0 100644 --- a/drivers/char/drm/r128_drv.c +++ b/drivers/char/drm/r128_drv.c @@ -37,30 +37,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -72,7 +70,10 @@ extern drm_ioctl_desc_t r128_ioctls[]; extern int r128_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | + DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .dev_priv_size = sizeof(drm_r128_buf_priv_t), .prerelease = r128_driver_prerelease, .pretakedown = r128_driver_pretakedown, @@ -89,21 +90,22 @@ static struct drm_driver driver = { .ioctls = r128_ioctls, .dma_ioctl = r128_cce_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, #ifdef CONFIG_COMPAT - .compat_ioctl = r128_compat_ioctl, + .compat_ioctl = r128_compat_ioctl, #endif - }, + } + , .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init r128_init(void) @@ -120,6 +122,6 @@ static void __exit r128_exit(void) module_init(r128_init); module_exit(r128_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h index 938dfaea553..87c5e1381ba 100644 --- a/drivers/char/drm/r128_drv.h +++ b/drivers/char/drm/r128_drv.h @@ -52,14 +52,13 @@ #define DRIVER_MINOR 5 #define DRIVER_PATCHLEVEL 0 - #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) typedef struct drm_r128_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_r128_freelist *next; - struct drm_r128_freelist *prev; + unsigned int age; + drm_buf_t *buf; + struct drm_r128_freelist *next; + struct drm_r128_freelist *prev; } drm_r128_freelist_t; typedef struct drm_r128_ring_buffer { @@ -83,8 +82,8 @@ typedef struct drm_r128_private { int cce_fifo_size; int cce_running; - drm_r128_freelist_t *head; - drm_r128_freelist_t *tail; + drm_r128_freelist_t *head; + drm_r128_freelist_t *tail; int usec_timeout; int is_pci; @@ -126,34 +125,34 @@ typedef struct drm_r128_buf_priv { int prim; int discard; int dispatched; - drm_r128_freelist_t *list_entry; + drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; /* r128_cce.c */ -extern int r128_cce_init( DRM_IOCTL_ARGS ); -extern int r128_cce_start( DRM_IOCTL_ARGS ); -extern int r128_cce_stop( DRM_IOCTL_ARGS ); -extern int r128_cce_reset( DRM_IOCTL_ARGS ); -extern int r128_cce_idle( DRM_IOCTL_ARGS ); -extern int r128_engine_reset( DRM_IOCTL_ARGS ); -extern int r128_fullscreen( DRM_IOCTL_ARGS ); -extern int r128_cce_buffers( DRM_IOCTL_ARGS ); +extern int r128_cce_init(DRM_IOCTL_ARGS); +extern int r128_cce_start(DRM_IOCTL_ARGS); +extern int r128_cce_stop(DRM_IOCTL_ARGS); +extern int r128_cce_reset(DRM_IOCTL_ARGS); +extern int r128_cce_idle(DRM_IOCTL_ARGS); +extern int r128_engine_reset(DRM_IOCTL_ARGS); +extern int r128_fullscreen(DRM_IOCTL_ARGS); +extern int r128_cce_buffers(DRM_IOCTL_ARGS); -extern void r128_freelist_reset( drm_device_t *dev ); +extern void r128_freelist_reset(drm_device_t * dev); -extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); +extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); -extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); -extern int r128_do_cleanup_cce( drm_device_t *dev ); +extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); +extern int r128_do_cleanup_cce(drm_device_t * dev); -extern int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); +extern int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); -extern irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ); -extern void r128_driver_irq_preinstall( drm_device_t *dev ); -extern void r128_driver_irq_postinstall( drm_device_t *dev ); -extern void r128_driver_irq_uninstall( drm_device_t *dev ); -extern void r128_driver_pretakedown(drm_device_t *dev); -extern void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp); +extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); +extern void r128_driver_irq_preinstall(drm_device_t * dev); +extern void r128_driver_irq_postinstall(drm_device_t * dev); +extern void r128_driver_irq_uninstall(drm_device_t * dev); +extern void r128_driver_pretakedown(drm_device_t * dev); +extern void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp); extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); @@ -265,7 +264,6 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, # define R128_EVENT_CRTC_OFFSET (1 << 0) #define R128_WINDOW_XY_OFFSET 0x1bcc - /* CCE registers */ #define R128_PM4_BUFFER_OFFSET 0x0700 @@ -316,7 +314,6 @@ extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, #define R128_PM4_FIFO_DATA_EVEN 0x1000 #define R128_PM4_FIFO_DATA_ODD 0x1004 - /* CCE command packets */ #define R128_CCE_PACKET0 0x00000000 @@ -394,7 +391,6 @@ do { \ R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ } while (0) - #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ ((n) << 16) | ((reg) >> 2)) #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ @@ -403,13 +399,11 @@ do { \ #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ (pkt) | ((n) << 16)) - -static __inline__ void -r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) +static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) { drm_r128_ring_buffer_t *ring = &dev_priv->ring; - ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) + ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); + if (ring->space <= 0) ring->space += ring->size; } @@ -450,7 +444,6 @@ do { \ OUT_RING( R128_EVENT_CRTC_OFFSET ); \ } while (0) - /* ================================================================ * Ring control */ @@ -520,4 +513,4 @@ do { \ write &= tail_mask; \ } while (0) -#endif /* __R128_DRV_H__ */ +#endif /* __R128_DRV_H__ */ diff --git a/drivers/char/drm/r128_ioc32.c b/drivers/char/drm/r128_ioc32.c index 60598ef9475..1e2e367b8b8 100644 --- a/drivers/char/drm/r128_ioc32.c +++ b/drivers/char/drm/r128_ioc32.c @@ -65,10 +65,10 @@ static int compat_r128_init(struct file *file, unsigned int cmd, { drm_r128_init32_t init32; drm_r128_init_t __user *init; - + if (copy_from_user(&init32, (void __user *)arg, sizeof(init32))) return -EFAULT; - + init = compat_alloc_user_space(sizeof(*init)); if (!access_ok(VERIFY_WRITE, init, sizeof(*init)) || __put_user(init32.func, &init->func) @@ -92,14 +92,14 @@ static int compat_r128_init(struct file *file, unsigned int cmd, || __put_user(init32.ring_offset, &init->ring_offset) || __put_user(init32.ring_rptr_offset, &init->ring_rptr_offset) || __put_user(init32.buffers_offset, &init->buffers_offset) - || __put_user(init32.agp_textures_offset, &init->agp_textures_offset)) + || __put_user(init32.agp_textures_offset, + &init->agp_textures_offset)) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, DRM_IOCTL_R128_INIT, (unsigned long)init); } - typedef struct drm_r128_depth32 { int func; int n; @@ -124,13 +124,15 @@ static int compat_r128_depth(struct file *file, unsigned int cmd, || __put_user(depth32.n, &depth->n) || __put_user((int __user *)(unsigned long)depth32.x, &depth->x) || __put_user((int __user *)(unsigned long)depth32.y, &depth->y) - || __put_user((unsigned int __user *)(unsigned long)depth32.buffer, &depth->buffer) - || __put_user((unsigned char __user *)(unsigned long)depth32.mask, &depth->mask)) + || __put_user((unsigned int __user *)(unsigned long)depth32.buffer, + &depth->buffer) + || __put_user((unsigned char __user *)(unsigned long)depth32.mask, + &depth->mask)) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_R128_DEPTH, (unsigned long)depth); - + DRM_IOCTL_R128_DEPTH, (unsigned long)depth); + } typedef struct drm_r128_stipple32 { @@ -148,7 +150,8 @@ static int compat_r128_stipple(struct file *file, unsigned int cmd, stipple = compat_alloc_user_space(sizeof(*stipple)); if (!access_ok(VERIFY_WRITE, stipple, sizeof(*stipple)) - || __put_user((unsigned int __user *)(unsigned long)stipple32.mask, &stipple->mask)) + || __put_user((unsigned int __user *)(unsigned long)stipple32.mask, + &stipple->mask)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, @@ -172,9 +175,10 @@ static int compat_r128_getparam(struct file *file, unsigned int cmd, getparam = compat_alloc_user_space(sizeof(*getparam)); if (!access_ok(VERIFY_WRITE, getparam, sizeof(*getparam)) || __put_user(getparam32.param, &getparam->param) - || __put_user((void __user *)(unsigned long)getparam32.value, &getparam->value)) + || __put_user((void __user *)(unsigned long)getparam32.value, + &getparam->value)) return -EFAULT; - + return drm_ioctl(file->f_dentry->d_inode, file, DRM_IOCTL_R128_GETPARAM, (unsigned long)getparam); } @@ -195,8 +199,7 @@ drm_ioctl_compat_t *r128_compat_ioctls[] = { * \param arg user argument. * \return zero on success or negative number on failure. */ -long r128_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg) +long r128_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int nr = DRM_IOCTL_NR(cmd); drm_ioctl_compat_t *fn = NULL; @@ -210,7 +213,7 @@ long r128_compat_ioctl(struct file *filp, unsigned int cmd, lock_kernel(); /* XXX for now */ if (fn != NULL) - ret = (*fn)(filp, cmd, arg); + ret = (*fn) (filp, cmd, arg); else ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); unlock_kernel(); diff --git a/drivers/char/drm/r128_irq.c b/drivers/char/drm/r128_irq.c index 643a30785fe..27eb0e31bd3 100644 --- a/drivers/char/drm/r128_irq.c +++ b/drivers/char/drm/r128_irq.c @@ -1,7 +1,7 @@ /* r128_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,68 +35,67 @@ #include "r128_drm.h" #include "r128_drv.h" -irqreturn_t r128_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; int status; - status = R128_READ( R128_GEN_INT_STATUS ); - + status = R128_READ(R128_GEN_INT_STATUS); + /* VBLANK interrupt */ - if ( status & R128_CRTC_VBLANK_INT ) { - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); + if (status & R128_CRTC_VBLANK_INT) { + R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); + drm_vbl_send_signals(dev); return IRQ_HANDLED; } return IRQ_NONE; } -int r128_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int r128_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { unsigned int cur_vblank; int ret = 0; /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } -void r128_driver_irq_preinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_preinstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); + R128_WRITE(R128_GEN_INT_CNTL, 0); /* Clear vblank bit if it's already high */ - R128_WRITE( R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK ); + R128_WRITE(R128_GEN_INT_STATUS, R128_CRTC_VBLANK_INT_AK); } -void r128_driver_irq_postinstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_postinstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; /* Turn on VBL interrupt */ - R128_WRITE( R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN ); + R128_WRITE(R128_GEN_INT_CNTL, R128_CRTC_VBLANK_INT_EN); } -void r128_driver_irq_uninstall( drm_device_t *dev ) { - drm_r128_private_t *dev_priv = - (drm_r128_private_t *)dev->dev_private; +void r128_driver_irq_uninstall(drm_device_t * dev) +{ + drm_r128_private_t *dev_priv = (drm_r128_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ - R128_WRITE( R128_GEN_INT_CNTL, 0 ); + R128_WRITE(R128_GEN_INT_CNTL, 0); } diff --git a/drivers/char/drm/r128_state.c b/drivers/char/drm/r128_state.c index 426a71c049d..14479cc08a5 100644 --- a/drivers/char/drm/r128_state.c +++ b/drivers/char/drm/r128_state.c @@ -32,235 +32,233 @@ #include "r128_drm.h" #include "r128_drv.h" - /* ================================================================ * CCE hardware state programming functions */ -static void r128_emit_clip_rects( drm_r128_private_t *dev_priv, - drm_clip_rect_t *boxes, int count ) +static void r128_emit_clip_rects(drm_r128_private_t * dev_priv, + drm_clip_rect_t * boxes, int count) { u32 aux_sc_cntl = 0x00000000; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( (count < 3? count: 3) * 5 + 2 ); + BEGIN_RING((count < 3 ? count : 3) * 5 + 2); - if ( count >= 1 ) { - OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) ); - OUT_RING( boxes[0].x1 ); - OUT_RING( boxes[0].x2 - 1 ); - OUT_RING( boxes[0].y1 ); - OUT_RING( boxes[0].y2 - 1 ); + if (count >= 1) { + OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); + OUT_RING(boxes[0].x1); + OUT_RING(boxes[0].x2 - 1); + OUT_RING(boxes[0].y1); + OUT_RING(boxes[0].y2 - 1); aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); } - if ( count >= 2 ) { - OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) ); - OUT_RING( boxes[1].x1 ); - OUT_RING( boxes[1].x2 - 1 ); - OUT_RING( boxes[1].y1 ); - OUT_RING( boxes[1].y2 - 1 ); + if (count >= 2) { + OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); + OUT_RING(boxes[1].x1); + OUT_RING(boxes[1].x2 - 1); + OUT_RING(boxes[1].y1); + OUT_RING(boxes[1].y2 - 1); aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); } - if ( count >= 3 ) { - OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) ); - OUT_RING( boxes[2].x1 ); - OUT_RING( boxes[2].x2 - 1 ); - OUT_RING( boxes[2].y1 ); - OUT_RING( boxes[2].y2 - 1 ); + if (count >= 3) { + OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); + OUT_RING(boxes[2].x1); + OUT_RING(boxes[2].x2 - 1); + OUT_RING(boxes[2].y1); + OUT_RING(boxes[2].y2 - 1); aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); } - OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) ); - OUT_RING( aux_sc_cntl ); + OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); + OUT_RING(aux_sc_cntl); ADVANCE_RING(); } -static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) ); - OUT_RING( ctx->scale_3d_cntl ); + OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); + OUT_RING(ctx->scale_3d_cntl); ADVANCE_RING(); } -static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); - - BEGIN_RING( 13 ); - - OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) ); - OUT_RING( ctx->dst_pitch_offset_c ); - OUT_RING( ctx->dp_gui_master_cntl_c ); - OUT_RING( ctx->sc_top_left_c ); - OUT_RING( ctx->sc_bottom_right_c ); - OUT_RING( ctx->z_offset_c ); - OUT_RING( ctx->z_pitch_c ); - OUT_RING( ctx->z_sten_cntl_c ); - OUT_RING( ctx->tex_cntl_c ); - OUT_RING( ctx->misc_3d_state_cntl_reg ); - OUT_RING( ctx->texture_clr_cmp_clr_c ); - OUT_RING( ctx->texture_clr_cmp_msk_c ); - OUT_RING( ctx->fog_color_c ); + DRM_DEBUG(" %s\n", __FUNCTION__); + + BEGIN_RING(13); + + OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); + OUT_RING(ctx->dst_pitch_offset_c); + OUT_RING(ctx->dp_gui_master_cntl_c); + OUT_RING(ctx->sc_top_left_c); + OUT_RING(ctx->sc_bottom_right_c); + OUT_RING(ctx->z_offset_c); + OUT_RING(ctx->z_pitch_c); + OUT_RING(ctx->z_sten_cntl_c); + OUT_RING(ctx->tex_cntl_c); + OUT_RING(ctx->misc_3d_state_cntl_reg); + OUT_RING(ctx->texture_clr_cmp_clr_c); + OUT_RING(ctx->texture_clr_cmp_msk_c); + OUT_RING(ctx->fog_color_c); ADVANCE_RING(); } -static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) ); - OUT_RING( ctx->setup_cntl ); - OUT_RING( ctx->pm4_vc_fpu_setup ); + OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); + OUT_RING(ctx->setup_cntl); + OUT_RING(ctx->pm4_vc_fpu_setup); ADVANCE_RING(); } -static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( ctx->dp_write_mask ); + OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); + OUT_RING(ctx->dp_write_mask); - OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) ); - OUT_RING( ctx->sten_ref_mask_c ); - OUT_RING( ctx->plane_3d_mask_c ); + OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); + OUT_RING(ctx->sten_ref_mask_c); + OUT_RING(ctx->plane_3d_mask_c); ADVANCE_RING(); } -static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) ); - OUT_RING( ctx->window_xy_offset ); + OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); + OUT_RING(ctx->window_xy_offset); ADVANCE_RING(); } -static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_context_regs_t *ctx = &sarea_priv->context_state; drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; int i; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS ); + BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); - OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C, - 2 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - OUT_RING( ctx->tex_size_pitch_c ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); + OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, + 2 + R128_MAX_TEXTURE_LEVELS)); + OUT_RING(tex->tex_cntl); + OUT_RING(tex->tex_combine_cntl); + OUT_RING(ctx->tex_size_pitch_c); + for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { + OUT_RING(tex->tex_offset[i]); } - OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) ); - OUT_RING( ctx->constant_color_c ); - OUT_RING( tex->tex_border_color ); + OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); + OUT_RING(ctx->constant_color_c); + OUT_RING(tex->tex_border_color); ADVANCE_RING(); } -static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; int i; RING_LOCALS; - DRM_DEBUG( " %s\n", __FUNCTION__ ); + DRM_DEBUG(" %s\n", __FUNCTION__); - BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS ); + BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); - OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C, - 1 + R128_MAX_TEXTURE_LEVELS ) ); - OUT_RING( tex->tex_cntl ); - OUT_RING( tex->tex_combine_cntl ); - for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) { - OUT_RING( tex->tex_offset[i] ); + OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); + OUT_RING(tex->tex_cntl); + OUT_RING(tex->tex_combine_cntl); + for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { + OUT_RING(tex->tex_offset[i]); } - OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) ); - OUT_RING( tex->tex_border_color ); + OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); + OUT_RING(tex->tex_border_color); ADVANCE_RING(); } -static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) +static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv) { drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; unsigned int dirty = sarea_priv->dirty; - DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty ); + DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty); - if ( dirty & R128_UPLOAD_CORE ) { - r128_emit_core( dev_priv ); + if (dirty & R128_UPLOAD_CORE) { + r128_emit_core(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_CORE; } - if ( dirty & R128_UPLOAD_CONTEXT ) { - r128_emit_context( dev_priv ); + if (dirty & R128_UPLOAD_CONTEXT) { + r128_emit_context(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; } - if ( dirty & R128_UPLOAD_SETUP ) { - r128_emit_setup( dev_priv ); + if (dirty & R128_UPLOAD_SETUP) { + r128_emit_setup(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_SETUP; } - if ( dirty & R128_UPLOAD_MASKS ) { - r128_emit_masks( dev_priv ); + if (dirty & R128_UPLOAD_MASKS) { + r128_emit_masks(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_MASKS; } - if ( dirty & R128_UPLOAD_WINDOW ) { - r128_emit_window( dev_priv ); + if (dirty & R128_UPLOAD_WINDOW) { + r128_emit_window(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; } - if ( dirty & R128_UPLOAD_TEX0 ) { - r128_emit_tex0( dev_priv ); + if (dirty & R128_UPLOAD_TEX0) { + r128_emit_tex0(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_TEX0; } - if ( dirty & R128_UPLOAD_TEX1 ) { - r128_emit_tex1( dev_priv ); + if (dirty & R128_UPLOAD_TEX1) { + r128_emit_tex1(dev_priv); sarea_priv->dirty &= ~R128_UPLOAD_TEX1; } @@ -270,26 +268,23 @@ static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv ) sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; } - #if R128_PERFORMANCE_BOXES /* ================================================================ * Performance monitoring functions */ -static void r128_clear_box( drm_r128_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) +static void r128_clear_box(drm_r128_private_t * dev_priv, + int x, int y, int w, int h, int r, int g, int b) { u32 pitch, offset; u32 fb_bpp, color; RING_LOCALS; - switch ( dev_priv->fb_bpp ) { + switch (dev_priv->fb_bpp) { case 16: fb_bpp = R128_GMC_DST_16BPP; color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; case 24: fb_bpp = R128_GMC_DST_24BPP; @@ -297,7 +292,7 @@ static void r128_clear_box( drm_r128_private_t *dev_priv, break; case 32: fb_bpp = R128_GMC_DST_32BPP; - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); break; default: return; @@ -306,60 +301,58 @@ static void r128_clear_box( drm_r128_private_t *dev_priv, offset = dev_priv->back_offset; pitch = dev_priv->back_pitch >> 3; - BEGIN_RING( 6 ); + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - fb_bpp | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + fb_bpp | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); - OUT_RING( (pitch << 21) | (offset >> 5) ); - OUT_RING( color ); + OUT_RING((pitch << 21) | (offset >> 5)); + OUT_RING(color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } -static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv ) +static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv) { - if ( atomic_read( &dev_priv->idle_count ) == 0 ) { - r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); + if (atomic_read(&dev_priv->idle_count) == 0) { + r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); } else { - atomic_set( &dev_priv->idle_count, 0 ); + atomic_set(&dev_priv->idle_count, 0); } } #endif - /* ================================================================ * CCE command dispatch functions */ -static void r128_print_dirty( const char *msg, unsigned int flags ) +static void r128_print_dirty(const char *msg, unsigned int flags) { - DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", - msg, - flags, - (flags & R128_UPLOAD_CORE) ? "core, " : "", - (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", - (flags & R128_UPLOAD_SETUP) ? "setup, " : "", - (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", - (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", - (flags & R128_UPLOAD_MASKS) ? "masks, " : "", - (flags & R128_UPLOAD_WINDOW) ? "window, " : "", - (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", - (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" ); + DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", + msg, + flags, + (flags & R128_UPLOAD_CORE) ? "core, " : "", + (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", + (flags & R128_UPLOAD_SETUP) ? "setup, " : "", + (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", + (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", + (flags & R128_UPLOAD_MASKS) ? "masks, " : "", + (flags & R128_UPLOAD_WINDOW) ? "window, " : "", + (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", + (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); } -static void r128_cce_dispatch_clear( drm_device_t *dev, - drm_r128_clear_t *clear ) +static void r128_cce_dispatch_clear(drm_device_t * dev, + drm_r128_clear_t * clear) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -368,102 +361,103 @@ static void r128_cce_dispatch_clear( drm_device_t *dev, unsigned int flags = clear->flags; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + if (dev_priv->page_flipping && dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(R128_FRONT | R128_BACK); - if ( tmp & R128_FRONT ) flags |= R128_BACK; - if ( tmp & R128_BACK ) flags |= R128_FRONT; + if (tmp & R128_FRONT) + flags |= R128_BACK; + if (tmp & R128_BACK) + flags |= R128_FRONT; } - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - pbox[i].x1, pbox[i].y1, pbox[i].x2, - pbox[i].y2, flags ); + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", + pbox[i].x1, pbox[i].y1, pbox[i].x2, + pbox[i].y2, flags); - if ( flags & (R128_FRONT | R128_BACK) ) { - BEGIN_RING( 2 ); + if (flags & (R128_FRONT | R128_BACK)) { + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); + OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); + OUT_RING(clear->color_mask); ADVANCE_RING(); } - if ( flags & R128_FRONT ) { - BEGIN_RING( 6 ); + if (flags & R128_FRONT) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS); - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( clear->clear_color ); + OUT_RING(dev_priv->front_pitch_offset_c); + OUT_RING(clear->clear_color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } - if ( flags & R128_BACK ) { - BEGIN_RING( 6 ); + if (flags & R128_BACK) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS); - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( clear->clear_color ); + OUT_RING(dev_priv->back_pitch_offset_c); + OUT_RING(clear->clear_color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } - if ( flags & R128_DEPTH ) { - BEGIN_RING( 6 ); + if (flags & R128_DEPTH) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( clear->clear_depth ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(clear->clear_depth); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } } } -static void r128_cce_dispatch_swap( drm_device_t *dev ) +static void r128_cce_dispatch_swap(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -471,48 +465,46 @@ static void r128_cce_dispatch_swap( drm_device_t *dev ) drm_clip_rect_t *pbox = sarea_priv->boxes; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ - r128_cce_performance_boxes( dev_priv ); + r128_cce_performance_boxes(dev_priv); #endif - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - BEGIN_RING( 7 ); + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); /* Make this work even if front & back are flipped: */ if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset_c ); - OUT_RING( dev_priv->front_pitch_offset_c ); - } - else { - OUT_RING( dev_priv->front_pitch_offset_c ); - OUT_RING( dev_priv->back_pitch_offset_c ); + OUT_RING(dev_priv->back_pitch_offset_c); + OUT_RING(dev_priv->front_pitch_offset_c); + } else { + OUT_RING(dev_priv->front_pitch_offset_c); + OUT_RING(dev_priv->back_pitch_offset_c); } - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } @@ -523,38 +515,37 @@ static void r128_cce_dispatch_swap( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); + OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); + OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static void r128_cce_dispatch_flip( drm_device_t *dev ) +static void r128_cce_dispatch_flip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); #if R128_PERFORMANCE_BOXES /* Do some trivial performance monitoring... */ - r128_cce_performance_boxes( dev_priv ); + r128_cce_performance_boxes(dev_priv); #endif - BEGIN_RING( 4 ); + BEGIN_RING(4); R128_WAIT_UNTIL_PAGE_FLIPPED(); - OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) ); + OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); - if ( dev_priv->current_page == 0 ) { - OUT_RING( dev_priv->back_offset ); + if (dev_priv->current_page == 0) { + OUT_RING(dev_priv->back_offset); } else { - OUT_RING( dev_priv->front_offset ); + OUT_RING(dev_priv->front_offset); } ADVANCE_RING(); @@ -565,18 +556,17 @@ static void r128_cce_dispatch_flip( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; + 1 - dev_priv->current_page; - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) ); - OUT_RING( dev_priv->sarea_priv->last_frame ); + OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); + OUT_RING(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static void r128_cce_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf ) +static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -587,50 +577,50 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev, int prim = buf_priv->prim; int i = 0; RING_LOCALS; - DRM_DEBUG( "buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox ); + DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); - if ( 0 ) - r128_print_dirty( "dispatch_vertex", sarea_priv->dirty ); + if (0) + r128_print_dirty("dispatch_vertex", sarea_priv->dirty); - if ( buf->used ) { + if (buf->used) { buf_priv->dispatched = 1; - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); + if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { + r128_emit_state(dev_priv); } do { /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); + if (i < sarea_priv->nbox) { + r128_emit_clip_rects(dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i); } /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( size ); - OUT_RING( format ); - OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | - (size << R128_CCE_VC_CNTL_NUM_SHIFT) ); + OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); + OUT_RING(offset); + OUT_RING(size); + OUT_RING(format); + OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | + (size << R128_CCE_VC_CNTL_NUM_SHIFT)); ADVANCE_RING(); i += 3; - } while ( i < sarea_priv->nbox ); + } while (i < sarea_priv->nbox); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -646,17 +636,15 @@ static void r128_cce_dispatch_vertex( drm_device_t *dev, sarea_priv->nbox = 0; } -static void r128_cce_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) +static void r128_cce_dispatch_indirect(drm_device_t * dev, + drm_buf_t * buf, int start, int end) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); + DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { int offset = buf->bus_address + start; int dwords = (end - start + 3) / sizeof(u32); @@ -664,33 +652,33 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev, * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CCE packet. */ - if ( dwords & 1 ) { + if (dwords & 1) { u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); - data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 ); + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); + data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); } buf_priv->dispatched = 1; /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); + OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); + OUT_RING(offset); + OUT_RING(dwords); ADVANCE_RING(); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the indirect buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -703,10 +691,9 @@ static void r128_cce_dispatch_indirect( drm_device_t *dev, dev_priv->sarea_priv->last_dispatch++; } -static void r128_cce_dispatch_indices( drm_device_t *dev, - drm_buf_t *buf, - int start, int end, - int count ) +static void r128_cce_dispatch_indices(drm_device_t * dev, + drm_buf_t * buf, + int start, int end, int count) { drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_buf_priv_t *buf_priv = buf->dev_private; @@ -718,62 +705,62 @@ static void r128_cce_dispatch_indices( drm_device_t *dev, int dwords; int i = 0; RING_LOCALS; - DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count ); + DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); - if ( 0 ) - r128_print_dirty( "dispatch_indices", sarea_priv->dirty ); + if (0) + r128_print_dirty("dispatch_indices", sarea_priv->dirty); - if ( start != end ) { + if (start != end) { buf_priv->dispatched = 1; - if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) { - r128_emit_state( dev_priv ); + if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { + r128_emit_state(dev_priv); } dwords = (end - start + 3) / sizeof(u32); - data = (u32 *)((char *)dev->agp_buffer_map->handle - + buf->offset + start); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + + buf->offset + start); - data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, - dwords-2 ) ); + data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, + dwords - 2)); - data[1] = cpu_to_le32( offset ); - data[2] = cpu_to_le32( R128_MAX_VB_VERTS ); - data[3] = cpu_to_le32( format ); - data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | - (count << 16)) ); + data[1] = cpu_to_le32(offset); + data[2] = cpu_to_le32(R128_MAX_VB_VERTS); + data[3] = cpu_to_le32(format); + data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | + (count << 16))); - if ( count & 0x1 ) { + if (count & 0x1) { #ifdef __LITTLE_ENDIAN - data[dwords-1] &= 0x0000ffff; + data[dwords - 1] &= 0x0000ffff; #else - data[dwords-1] &= 0xffff0000; + data[dwords - 1] &= 0xffff0000; #endif } do { /* Emit the next set of up to three cliprects */ - if ( i < sarea_priv->nbox ) { - r128_emit_clip_rects( dev_priv, - &sarea_priv->boxes[i], - sarea_priv->nbox - i ); + if (i < sarea_priv->nbox) { + r128_emit_clip_rects(dev_priv, + &sarea_priv->boxes[i], + sarea_priv->nbox - i); } - r128_cce_dispatch_indirect( dev, buf, start, end ); + r128_cce_dispatch_indirect(dev, buf, start, end); i += 3; - } while ( i < sarea_priv->nbox ); + } while (i < sarea_priv->nbox); } - if ( buf_priv->discard ) { + if (buf_priv->discard) { buf_priv->age = dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) ); - OUT_RING( buf_priv->age ); + OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); + OUT_RING(buf_priv->age); ADVANCE_RING(); @@ -788,9 +775,8 @@ static void r128_cce_dispatch_indices( drm_device_t *dev, sarea_priv->nbox = 0; } -static int r128_cce_dispatch_blit( DRMFILE filp, - drm_device_t *dev, - drm_r128_blit_t *blit ) +static int r128_cce_dispatch_blit(DRMFILE filp, + drm_device_t * dev, drm_r128_blit_t * blit) { drm_r128_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; @@ -799,13 +785,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp, u32 *data; int dword_shift, dwords; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* The compiler won't optimize away a division by a variable, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ - switch ( blit->format ) { + switch (blit->format) { case R128_DATATYPE_ARGB8888: dword_shift = 0; break; @@ -821,7 +807,7 @@ static int r128_cce_dispatch_blit( DRMFILE filp, dword_shift = 2; break; default: - DRM_ERROR( "invalid blit format %d\n", blit->format ); + DRM_ERROR("invalid blit format %d\n", blit->format); return DRM_ERR(EINVAL); } @@ -830,10 +816,10 @@ static int r128_cce_dispatch_blit( DRMFILE filp, * data from the host data blit, otherwise part of the texture * image may be corrupted. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI ); + OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); + OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); ADVANCE_RING(); @@ -842,13 +828,13 @@ static int r128_cce_dispatch_blit( DRMFILE filp, buf = dma->buflist[blit->idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", blit->idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", blit->idx); return DRM_ERR(EINVAL); } @@ -856,45 +842,43 @@ static int r128_cce_dispatch_blit( DRMFILE filp, dwords = (blit->width * blit->height) >> dword_shift; - data = (u32 *)((char *)dev->agp_buffer_map->handle + buf->offset); - - data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) ); - data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (blit->format << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_HOST_DATA | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_AUX_CLIP_DIS | - R128_GMC_WR_MSK_DIS) ); - - data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) ); - data[3] = cpu_to_le32( 0xffffffff ); - data[4] = cpu_to_le32( 0xffffffff ); - data[5] = cpu_to_le32( (blit->y << 16) | blit->x ); - data[6] = cpu_to_le32( (blit->height << 16) | blit->width ); - data[7] = cpu_to_le32( dwords ); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); + + data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); + data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (blit->format << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_HOST_DATA | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); + + data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); + data[3] = cpu_to_le32(0xffffffff); + data[4] = cpu_to_le32(0xffffffff); + data[5] = cpu_to_le32((blit->y << 16) | blit->x); + data[6] = cpu_to_le32((blit->height << 16) | blit->width); + data[7] = cpu_to_le32(dwords); buf->used = (dwords + 8) * sizeof(u32); - r128_cce_dispatch_indirect( dev, buf, 0, buf->used ); + r128_cce_dispatch_indirect(dev, buf, 0, buf->used); /* Flush the pixel cache after the blit completes. This ensures * the texture data is written out to memory before rendering * continues. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); - OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) ); - OUT_RING( R128_PC_FLUSH_GUI ); + OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); + OUT_RING(R128_PC_FLUSH_GUI); ADVANCE_RING(); return 0; } - /* ================================================================ * Tiled depth buffer management * @@ -902,8 +886,8 @@ static int r128_cce_dispatch_blit( DRMFILE filp, * have hardware stencil support. */ -static int r128_cce_dispatch_write_span( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_write_span(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; @@ -911,95 +895,95 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev, u8 *mask; int i, buffer_size, mask_size; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return DRM_ERR(EFAULT); } buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) + buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); + if (buffer == NULL) return DRM_ERR(ENOMEM); - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS); + if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } mask_size = depth->n * sizeof(u8); - if ( depth->mask ) { - mask = drm_alloc( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + if (depth->mask) { + mask = drm_alloc(mask_size, DRM_MEM_BUFS); + if (mask == NULL) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); - drm_free( mask, mask_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { + drm_free(buffer, buffer_size, DRM_MEM_BUFS); + drm_free(mask, mask_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++, x++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++, x++) { + if (mask[i]) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( mask, mask_size, DRM_MEM_BUFS ); + drm_free(mask, mask_size, DRM_MEM_BUFS); } else { - for ( i = 0 ; i < count ; i++, x++ ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++, x++) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x << 16) | y ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } -static int r128_cce_dispatch_write_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_write_pixels(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; @@ -1007,7 +991,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, u8 *mask; int i, xbuf_size, ybuf_size, buffer_size, mask_size; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) @@ -1015,270 +999,266 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev, xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); - x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { + x = drm_alloc(xbuf_size, DRM_MEM_BUFS); + if (x == NULL) { return DRM_ERR(ENOMEM); } - y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); + y = drm_alloc(ybuf_size, DRM_MEM_BUFS); + if (y == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } buffer_size = depth->n * sizeof(u32); - buffer = drm_alloc( buffer_size, DRM_MEM_BUFS ); - if ( buffer == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); + if (buffer == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( buffer, depth->buffer, buffer_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( depth->mask ) { + if (depth->mask) { mask_size = depth->n * sizeof(u8); - mask = drm_alloc( mask_size, DRM_MEM_BUFS ); - if ( mask == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + mask = drm_alloc(mask_size, DRM_MEM_BUFS); + if (mask == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( mask, depth->mask, mask_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); - drm_free( mask, mask_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); + drm_free(mask, mask_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++ ) { - if ( mask[i] ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++) { + if (mask[i]) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( mask, mask_size, DRM_MEM_BUFS ); + drm_free(mask, mask_size, DRM_MEM_BUFS); } else { - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 6 ); + for (i = 0; i < count; i++) { + BEGIN_RING(6); - OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_SOLID_COLOR | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_P | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); + OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_SOLID_COLOR | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_P | + R128_GMC_CLR_CMP_CNTL_DIS | + R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( buffer[i] ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(buffer[i]); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } } - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); - drm_free( buffer, buffer_size, DRM_MEM_BUFS ); + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); + drm_free(buffer, buffer_size, DRM_MEM_BUFS); return 0; } -static int r128_cce_dispatch_read_span( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_read_span(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, x, y; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) { + if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( &y, depth->y, sizeof(y) ) ) { + if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { return DRM_ERR(EFAULT); } - BEGIN_RING( 7 ); + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(dev_priv->span_pitch_offset_c); - OUT_RING( (x << 16) | y ); - OUT_RING( (0 << 16) | 0 ); - OUT_RING( (count << 16) | 1 ); + OUT_RING((x << 16) | y); + OUT_RING((0 << 16) | 0); + OUT_RING((count << 16) | 1); ADVANCE_RING(); return 0; } -static int r128_cce_dispatch_read_pixels( drm_device_t *dev, - drm_r128_depth_t *depth ) +static int r128_cce_dispatch_read_pixels(drm_device_t * dev, + drm_r128_depth_t * depth) { drm_r128_private_t *dev_priv = dev->dev_private; int count, *x, *y; int i, xbuf_size, ybuf_size; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); count = depth->n; if (count > 4096 || count <= 0) return DRM_ERR(EMSGSIZE); - if ( count > dev_priv->depth_pitch ) { + if (count > dev_priv->depth_pitch) { count = dev_priv->depth_pitch; } xbuf_size = count * sizeof(*x); ybuf_size = count * sizeof(*y); - x = drm_alloc( xbuf_size, DRM_MEM_BUFS ); - if ( x == NULL ) { + x = drm_alloc(xbuf_size, DRM_MEM_BUFS); + if (x == NULL) { return DRM_ERR(ENOMEM); } - y = drm_alloc( ybuf_size, DRM_MEM_BUFS ); - if ( y == NULL ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); + y = drm_alloc(ybuf_size, DRM_MEM_BUFS); + if (y == NULL) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } - if ( DRM_COPY_FROM_USER( x, depth->x, xbuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - if ( DRM_COPY_FROM_USER( y, depth->y, ybuf_size ) ) { - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return DRM_ERR(EFAULT); } - for ( i = 0 ; i < count ; i++ ) { - BEGIN_RING( 7 ); + for (i = 0; i < count; i++) { + BEGIN_RING(7); - OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL | - R128_GMC_DST_PITCH_OFFSET_CNTL | - R128_GMC_BRUSH_NONE | - (dev_priv->depth_fmt << 8) | - R128_GMC_SRC_DATATYPE_COLOR | - R128_ROP3_S | - R128_DP_SRC_SOURCE_MEMORY | - R128_GMC_CLR_CMP_CNTL_DIS | - R128_GMC_WR_MSK_DIS ); + OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); + OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | + R128_GMC_DST_PITCH_OFFSET_CNTL | + R128_GMC_BRUSH_NONE | + (dev_priv->depth_fmt << 8) | + R128_GMC_SRC_DATATYPE_COLOR | + R128_ROP3_S | + R128_DP_SRC_SOURCE_MEMORY | + R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); - OUT_RING( dev_priv->depth_pitch_offset_c ); - OUT_RING( dev_priv->span_pitch_offset_c ); + OUT_RING(dev_priv->depth_pitch_offset_c); + OUT_RING(dev_priv->span_pitch_offset_c); - OUT_RING( (x[i] << 16) | y[i] ); - OUT_RING( (i << 16) | 0 ); - OUT_RING( (1 << 16) | 1 ); + OUT_RING((x[i] << 16) | y[i]); + OUT_RING((i << 16) | 0); + OUT_RING((1 << 16) | 1); ADVANCE_RING(); } - drm_free( x, xbuf_size, DRM_MEM_BUFS ); - drm_free( y, ybuf_size, DRM_MEM_BUFS ); + drm_free(x, xbuf_size, DRM_MEM_BUFS); + drm_free(y, ybuf_size, DRM_MEM_BUFS); return 0; } - /* ================================================================ * Polygon stipple */ -static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple) { drm_r128_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - BEGIN_RING( 33 ); + BEGIN_RING(33); - OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); + OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); + for (i = 0; i < 32; i++) { + OUT_RING(stipple[i]); } ADVANCE_RING(); } - /* ================================================================ * IOCTL functions */ -static int r128_cce_clear( DRM_IOCTL_ARGS ) +static int r128_cce_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_r128_clear_t clear; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_r128_clear_t __user *) data, - sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data, + sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - r128_cce_dispatch_clear( dev, &clear ); + r128_cce_dispatch_clear(dev, &clear); COMMIT_RING(); /* Make sure we restore the 3D state next time. @@ -1288,17 +1268,17 @@ static int r128_cce_clear( DRM_IOCTL_ARGS ) return 0; } -static int r128_do_init_pageflip( drm_device_t *dev ) +static int r128_do_init_pageflip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); - dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); + dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); + dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); - R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, - dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); + R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); + R128_WRITE(R128_CRTC_OFFSET_CNTL, + dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); dev_priv->page_flipping = 1; dev_priv->current_page = 0; @@ -1307,16 +1287,16 @@ static int r128_do_init_pageflip( drm_device_t *dev ) return 0; } -static int r128_do_cleanup_pageflip( drm_device_t *dev ) +static int r128_do_cleanup_pageflip(drm_device_t * dev) { drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); - R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); + R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); + R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); if (dev_priv->current_page != 0) { - r128_cce_dispatch_flip( dev ); + r128_cce_dispatch_flip(dev); COMMIT_RING(); } @@ -1325,43 +1305,43 @@ static int r128_do_cleanup_pageflip( drm_device_t *dev ) } /* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. + * They can & should be intermixed to support multiple 3d windows. */ -static int r128_cce_flip( DRM_IOCTL_ARGS ) +static int r128_cce_flip(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if (!dev_priv->page_flipping) - r128_do_init_pageflip( dev ); + if (!dev_priv->page_flipping) + r128_do_init_pageflip(dev); - r128_cce_dispatch_flip( dev ); + r128_cce_dispatch_flip(dev); COMMIT_RING(); return 0; } -static int r128_cce_swap( DRM_IOCTL_ARGS ) +static int r128_cce_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "%s\n", __FUNCTION__ ); + DRM_DEBUG("%s\n", __FUNCTION__); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; - r128_cce_dispatch_swap( dev ); + r128_cce_dispatch_swap(dev); dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS); @@ -1369,7 +1349,7 @@ static int r128_cce_swap( DRM_IOCTL_ARGS ) return 0; } -static int r128_cce_vertex( DRM_IOCTL_ARGS ) +static int r128_cce_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1378,44 +1358,43 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS ) drm_r128_buf_priv_t *buf_priv; drm_r128_vertex_t vertex; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_r128_vertex_t __user *) data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); + DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( vertex.prim < 0 || - vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); + if (vertex.prim < 0 || + vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", vertex.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } @@ -1423,13 +1402,13 @@ static int r128_cce_vertex( DRM_IOCTL_ARGS ) buf_priv->prim = vertex.prim; buf_priv->discard = vertex.discard; - r128_cce_dispatch_vertex( dev, buf ); + r128_cce_dispatch_vertex(dev, buf); COMMIT_RING(); return 0; } -static int r128_cce_indices( DRM_IOCTL_ARGS ) +static int r128_cce_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1439,55 +1418,54 @@ static int r128_cce_indices( DRM_IOCTL_ARGS ) drm_r128_indices_t elts; int count; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( elts, (drm_r128_indices_t __user *) data, - sizeof(elts) ); + DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data, + sizeof(elts)); - DRM_DEBUG( "pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); + DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, + elts.idx, elts.start, elts.end, elts.discard); - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); + if (elts.idx < 0 || elts.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( elts.prim < 0 || - elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); + if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { + DRM_ERROR("buffer prim %d\n", elts.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[elts.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", elts.idx); return DRM_ERR(EINVAL); } count = (elts.end - elts.start) / sizeof(u16); elts.start -= R128_INDEX_PRIM_OFFSET; - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + if (elts.start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts.start); return DRM_ERR(EINVAL); } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + if (elts.start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); return DRM_ERR(EINVAL); } @@ -1495,13 +1473,13 @@ static int r128_cce_indices( DRM_IOCTL_ARGS ) buf_priv->prim = elts.prim; buf_priv->discard = elts.discard; - r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count ); + r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count); COMMIT_RING(); return 0; } -static int r128_cce_blit( DRM_IOCTL_ARGS ) +static int r128_cce_blit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -1509,55 +1487,55 @@ static int r128_cce_blit( DRM_IOCTL_ARGS ) drm_r128_blit_t blit; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( blit, (drm_r128_blit_t __user *) data, - sizeof(blit) ); + DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data, + sizeof(blit)); - DRM_DEBUG( "pid=%d index=%d\n", DRM_CURRENTPID, blit.idx ); + DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx); - if ( blit.idx < 0 || blit.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - blit.idx, dma->buf_count - 1 ); + if (blit.idx < 0 || blit.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + blit.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = r128_cce_dispatch_blit( filp, dev, &blit ); + ret = r128_cce_dispatch_blit(filp, dev, &blit); COMMIT_RING(); return ret; } -static int r128_cce_depth( DRM_IOCTL_ARGS ) +static int r128_cce_depth(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_depth_t depth; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( depth, (drm_r128_depth_t __user *) data, - sizeof(depth) ); + DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data, + sizeof(depth)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); ret = DRM_ERR(EINVAL); - switch ( depth.func ) { + switch (depth.func) { case R128_WRITE_SPAN: - ret = r128_cce_dispatch_write_span( dev, &depth ); + ret = r128_cce_dispatch_write_span(dev, &depth); break; case R128_WRITE_PIXELS: - ret = r128_cce_dispatch_write_pixels( dev, &depth ); + ret = r128_cce_dispatch_write_pixels(dev, &depth); break; case R128_READ_SPAN: - ret = r128_cce_dispatch_read_span( dev, &depth ); + ret = r128_cce_dispatch_read_span(dev, &depth); break; case R128_READ_PIXELS: - ret = r128_cce_dispatch_read_pixels( dev, &depth ); + ret = r128_cce_dispatch_read_pixels(dev, &depth); break; } @@ -1565,31 +1543,30 @@ static int r128_cce_depth( DRM_IOCTL_ARGS ) return ret; } -static int r128_cce_stipple( DRM_IOCTL_ARGS ) +static int r128_cce_stipple(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_r128_stipple_t __user *) data, - sizeof(stipple) ); + DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data, + sizeof(stipple)); - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, - 32 * sizeof(u32) ) ) - return DRM_ERR( EFAULT ); + if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) + return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - r128_cce_dispatch_stipple( dev, mask ); + r128_cce_dispatch_stipple(dev, mask); COMMIT_RING(); return 0; } -static int r128_cce_indirect( DRM_IOCTL_ARGS ) +static int r128_cce_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; @@ -1601,47 +1578,46 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS ) RING_LOCALS; #endif - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_r128_indirect_t __user *) data, - sizeof(indirect) ); + DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data, + sizeof(indirect)); - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); + DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, indirect.end, indirect.discard); - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); + if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } buf = dma->buflist[indirect.idx]; buf_priv = buf->dev_private; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", indirect.idx); return DRM_ERR(EINVAL); } - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); + if (indirect.start < buf->used) { + DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf->used = indirect.end; buf_priv->discard = indirect.discard; @@ -1650,7 +1626,7 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS ) /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); #endif @@ -1659,30 +1635,30 @@ static int r128_cce_indirect( DRM_IOCTL_ARGS ) * X server. This is insecure and is thus only available to * privileged clients. */ - r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end); COMMIT_RING(); return 0; } -static int r128_getparam( DRM_IOCTL_ARGS ) +static int r128_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_r128_private_t *dev_priv = dev->dev_private; drm_r128_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_r128_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case R128_PARAM_IRQ_NR: value = dev->irq; break; @@ -1690,47 +1666,47 @@ static int r128_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } -void r128_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp) { - if ( dev->dev_private ) { + if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - r128_do_cleanup_pageflip( dev ); + if (dev_priv->page_flipping) { + r128_do_cleanup_pageflip(dev); } - } + } } -void r128_driver_pretakedown(drm_device_t *dev) +void r128_driver_pretakedown(drm_device_t * dev) { - r128_do_cleanup_cce( dev ); + r128_do_cleanup_cce(dev); } drm_ioctl_desc_t r128_ioctls[] = { - [DRM_IOCTL_NR(DRM_R128_INIT)] = { r128_cce_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_START)] = { r128_cce_start, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = { r128_cce_stop, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = { r128_cce_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = { r128_cce_idle, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_RESET)] = { r128_engine_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = { r128_fullscreen, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_SWAP)] = { r128_cce_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_FLIP)] = { r128_cce_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_CLEAR)] = { r128_cce_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_VERTEX)] = { r128_cce_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_INDICES)] = { r128_cce_indices, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_BLIT)] = { r128_cce_blit, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_DEPTH)] = { r128_cce_depth, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = { r128_cce_stipple, 1, 0 }, - [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = { r128_cce_indirect, 1, 1 }, - [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = { r128_getparam, 1, 0 }, + [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0}, + [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1}, + [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0}, }; int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c index 623f1f460cb..aa66f46279e 100644 --- a/drivers/char/drm/r300_cmdbuf.c +++ b/drivers/char/drm/r300_cmdbuf.c @@ -37,7 +37,6 @@ #include "radeon_drv.h" #include "r300_reg.h" - #define R300_SIMULTANEOUS_CLIPRECTS 4 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects @@ -49,14 +48,12 @@ static const int r300_cliprect_cntl[4] = { 0xFFFE }; - /** * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command * buffer, starting with index n. */ -static int r300_emit_cliprects(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, - int n) +static int r300_emit_cliprects(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf, int n) { drm_clip_rect_t box; int nr; @@ -70,38 +67,47 @@ static int r300_emit_cliprects(drm_radeon_private_t* dev_priv, DRM_DEBUG("%i cliprects\n", nr); if (nr) { - BEGIN_RING(6 + nr*2); - OUT_RING( CP_PACKET0( R300_RE_CLIPRECT_TL_0, nr*2 - 1 ) ); + BEGIN_RING(6 + nr * 2); + OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); - for(i = 0; i < nr; ++i) { - if (DRM_COPY_FROM_USER_UNCHECKED(&box, &cmdbuf->boxes[n+i], sizeof(box))) { + for (i = 0; i < nr; ++i) { + if (DRM_COPY_FROM_USER_UNCHECKED + (&box, &cmdbuf->boxes[n + i], sizeof(box))) { DRM_ERROR("copy cliprect faulted\n"); return DRM_ERR(EFAULT); } - box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; - box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; - box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; - box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; + box.x1 = + (box.x1 + + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; + box.y1 = + (box.y1 + + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; + box.x2 = + (box.x2 + + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; + box.y2 = + (box.y2 + + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK; OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | - (box.y1 << R300_CLIPRECT_Y_SHIFT)); + (box.y1 << R300_CLIPRECT_Y_SHIFT)); OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | - (box.y2 << R300_CLIPRECT_Y_SHIFT)); + (box.y2 << R300_CLIPRECT_Y_SHIFT)); } - OUT_RING_REG( R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr-1] ); + OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]); /* TODO/SECURITY: Force scissors to a safe value, otherwise the - * client might be able to trample over memory. - * The impact should be very limited, but I'd rather be safe than - * sorry. - */ - OUT_RING( CP_PACKET0( R300_RE_SCISSORS_TL, 1 ) ); - OUT_RING( 0 ); - OUT_RING( R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK ); + * client might be able to trample over memory. + * The impact should be very limited, but I'd rather be safe than + * sorry. + */ + OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); + OUT_RING(0); + OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); ADVANCE_RING(); - } else { + } else { /* Why we allow zero cliprect rendering: * There are some commands in a command buffer that must be submitted * even when there are no cliprects, e.g. DMA buffer discard @@ -118,28 +124,27 @@ static int r300_emit_cliprects(drm_radeon_private_t* dev_priv, * can't produce any fragments. */ BEGIN_RING(2); - OUT_RING_REG( R300_RE_CLIPRECT_CNTL, 0 ); + OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0); ADVANCE_RING(); - } + } return 0; } -u8 r300_reg_flags[0x10000>>2]; - +u8 r300_reg_flags[0x10000 >> 2]; void r300_init_reg_flags(void) { int i; - memset(r300_reg_flags, 0, 0x10000>>2); - #define ADD_RANGE_MARK(reg, count,mark) \ + memset(r300_reg_flags, 0, 0x10000 >> 2); +#define ADD_RANGE_MARK(reg, count,mark) \ for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\ r300_reg_flags[i]|=(mark); - - #define MARK_SAFE 1 - #define MARK_CHECK_OFFSET 2 - - #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) + +#define MARK_SAFE 1 +#define MARK_CHECK_OFFSET 2 + +#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */ ADD_RANGE(R300_SE_VPORT_XSCALE, 6); @@ -193,15 +198,15 @@ void r300_init_reg_flags(void) ADD_RANGE(R300_RB3D_CBLEND, 2); ADD_RANGE(R300_RB3D_COLORMASK, 1); ADD_RANGE(0x4E10, 3); - ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ + ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */ ADD_RANGE(R300_RB3D_COLORPITCH0, 1); ADD_RANGE(0x4E50, 9); ADD_RANGE(0x4E88, 1); ADD_RANGE(0x4EA0, 2); ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); ADD_RANGE(0x4F10, 4); - ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ - ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); + ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ + ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); ADD_RANGE(0x4F28, 1); ADD_RANGE(0x4F30, 2); ADD_RANGE(0x4F44, 1); @@ -211,7 +216,7 @@ void r300_init_reg_flags(void) ADD_RANGE(R300_TX_UNK1_0, 16); ADD_RANGE(R300_TX_SIZE_0, 16); ADD_RANGE(R300_TX_FORMAT_0, 16); - /* Texture offset is dangerous and needs more checking */ + /* Texture offset is dangerous and needs more checking */ ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET); ADD_RANGE(R300_TX_UNK4_0, 16); ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); @@ -224,33 +229,41 @@ void r300_init_reg_flags(void) } -static __inline__ int r300_check_range(unsigned reg, int count) +static __inline__ int r300_check_range(unsigned reg, int count) { int i; - if(reg & ~0xffff)return -1; - for(i=(reg>>2);i<(reg>>2)+count;i++) - if(r300_reg_flags[i]!=MARK_SAFE)return 1; + if (reg & ~0xffff) + return -1; + for (i = (reg >> 2); i < (reg >> 2) + count; i++) + if (r300_reg_flags[i] != MARK_SAFE) + return 1; return 0; } /* we expect offsets passed to the framebuffer to be either within video memory or - within AGP space */ -static __inline__ int r300_check_offset(drm_radeon_private_t* dev_priv, u32 offset) + within AGP space */ +static __inline__ int r300_check_offset(drm_radeon_private_t * dev_priv, + u32 offset) { /* we realy want to check against end of video aperture - but this value is not being kept. - This code is correct for now (does the same thing as the - code that sets MC_FB_LOCATION) in radeon_cp.c */ - if((offset>=dev_priv->fb_location) && - (offsetgart_vm_start))return 0; - if((offset>=dev_priv->gart_vm_start) && - (offsetgart_vm_start+dev_priv->gart_size))return 0; + but this value is not being kept. + This code is correct for now (does the same thing as the + code that sets MC_FB_LOCATION) in radeon_cp.c */ + if ((offset >= dev_priv->fb_location) && + (offset < dev_priv->gart_vm_start)) + return 0; + if ((offset >= dev_priv->gart_vm_start) && + (offset < dev_priv->gart_vm_start + dev_priv->gart_size)) + return 0; return 1; } -static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, - drm_r300_cmd_header_t header) +static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * + dev_priv, + drm_radeon_cmd_buffer_t + * cmdbuf, + drm_r300_cmd_header_t + header) { int reg; int sz; @@ -260,35 +273,40 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t* sz = header.packet0.count; reg = (header.packet0.reghi << 8) | header.packet0.reglo; - - if((sz>64)||(sz<0)){ - DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", reg, sz); + + if ((sz > 64) || (sz < 0)) { + DRM_ERROR + ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", + reg, sz); return DRM_ERR(EINVAL); - } - for(i=0;ibuf)[i]; - switch(r300_reg_flags[(reg>>2)+i]){ + } + for (i = 0; i < sz; i++) { + values[i] = ((int __user *)cmdbuf->buf)[i]; + switch (r300_reg_flags[(reg >> 2) + i]) { case MARK_SAFE: break; case MARK_CHECK_OFFSET: - if(r300_check_offset(dev_priv, (u32)values[i])){ - DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", reg, sz); + if (r300_check_offset(dev_priv, (u32) values[i])) { + DRM_ERROR + ("Offset failed range check (reg=%04x sz=%d)\n", + reg, sz); return DRM_ERR(EINVAL); - } + } break; default: - DRM_ERROR("Register %04x failed check as flag=%02x\n", reg+i*4, r300_reg_flags[(reg>>2)+i]); + DRM_ERROR("Register %04x failed check as flag=%02x\n", + reg + i * 4, r300_reg_flags[(reg >> 2) + i]); return DRM_ERR(EINVAL); - } } - - BEGIN_RING(1+sz); - OUT_RING( CP_PACKET0( reg, sz-1 ) ); - OUT_RING_TABLE( values, sz ); + } + + BEGIN_RING(1 + sz); + OUT_RING(CP_PACKET0(reg, sz - 1)); + OUT_RING_TABLE(values, sz); ADVANCE_RING(); - cmdbuf->buf += sz*4; - cmdbuf->bufsz -= sz*4; + cmdbuf->buf += sz * 4; + cmdbuf->bufsz -= sz * 4; return 0; } @@ -299,9 +317,9 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t* * * Note that checks are performed on contents and addresses of the registers */ -static __inline__ int r300_emit_packet0(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, - drm_r300_cmd_header_t header) +static __inline__ int r300_emit_packet0(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf, + drm_r300_cmd_header_t header) { int reg; int sz; @@ -313,39 +331,40 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t* dev_priv, if (!sz) return 0; - if (sz*4 > cmdbuf->bufsz) + if (sz * 4 > cmdbuf->bufsz) return DRM_ERR(EINVAL); - - if (reg+sz*4 >= 0x10000){ - DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, sz); + + if (reg + sz * 4 >= 0x10000) { + DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, + sz); return DRM_ERR(EINVAL); - } + } - if(r300_check_range(reg, sz)){ + if (r300_check_range(reg, sz)) { /* go and check everything */ - return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, header); - } + return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, + header); + } /* the rest of the data is safe to emit, whatever the values the user passed */ - BEGIN_RING(1+sz); - OUT_RING( CP_PACKET0( reg, sz-1 ) ); - OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz ); + BEGIN_RING(1 + sz); + OUT_RING(CP_PACKET0(reg, sz - 1)); + OUT_RING_TABLE((int __user *)cmdbuf->buf, sz); ADVANCE_RING(); - cmdbuf->buf += sz*4; - cmdbuf->bufsz -= sz*4; + cmdbuf->buf += sz * 4; + cmdbuf->bufsz -= sz * 4; return 0; } - /** * Uploads user-supplied vertex program instructions or parameters onto * the graphics card. * Called by r300_do_cp_cmdbuf. */ -static __inline__ int r300_emit_vpu(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, +static __inline__ int r300_emit_vpu(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) { int sz; @@ -357,114 +376,121 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t* dev_priv, if (!sz) return 0; - if (sz*16 > cmdbuf->bufsz) + if (sz * 16 > cmdbuf->bufsz) return DRM_ERR(EINVAL); - BEGIN_RING(5+sz*4); + BEGIN_RING(5 + sz * 4); /* Wait for VAP to come to senses.. */ /* there is no need to emit it multiple times, (only once before VAP is programmed, but this optimization is for later */ - OUT_RING_REG( R300_VAP_PVS_WAITIDLE, 0 ); - OUT_RING_REG( R300_VAP_PVS_UPLOAD_ADDRESS, addr ); - OUT_RING( CP_PACKET0_TABLE( R300_VAP_PVS_UPLOAD_DATA, sz*4 - 1 ) ); - OUT_RING_TABLE( (int __user*)cmdbuf->buf, sz*4 ); + OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0); + OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); + OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); + OUT_RING_TABLE((int __user *)cmdbuf->buf, sz * 4); ADVANCE_RING(); - cmdbuf->buf += sz*16; - cmdbuf->bufsz -= sz*16; + cmdbuf->buf += sz * 16; + cmdbuf->bufsz -= sz * 16; return 0; } - /** * Emit a clear packet from userspace. * Called by r300_emit_packet3. */ -static __inline__ int r300_emit_clear(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf) +static __inline__ int r300_emit_clear(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf) { RING_LOCALS; - if (8*4 > cmdbuf->bufsz) + if (8 * 4 > cmdbuf->bufsz) return DRM_ERR(EINVAL); BEGIN_RING(10); - OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 8 ) ); - OUT_RING( R300_PRIM_TYPE_POINT|R300_PRIM_WALK_RING| - (1<buf, 8 ); + OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); + OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | + (1 << R300_PRIM_NUM_VERTICES_SHIFT)); + OUT_RING_TABLE((int __user *)cmdbuf->buf, 8); ADVANCE_RING(); - cmdbuf->buf += 8*4; - cmdbuf->bufsz -= 8*4; + cmdbuf->buf += 8 * 4; + cmdbuf->bufsz -= 8 * 4; return 0; } -static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, - u32 header) +static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf, + u32 header) { - int count, i,k; - #define MAX_ARRAY_PACKET 64 + int count, i, k; +#define MAX_ARRAY_PACKET 64 u32 payload[MAX_ARRAY_PACKET]; u32 narrays; RING_LOCALS; - count=(header>>16) & 0x3fff; - - if((count+1)>MAX_ARRAY_PACKET){ - DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count); + count = (header >> 16) & 0x3fff; + + if ((count + 1) > MAX_ARRAY_PACKET) { + DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", + count); return DRM_ERR(EINVAL); - } - memset(payload, 0, MAX_ARRAY_PACKET*4); - memcpy(payload, cmdbuf->buf+4, (count+1)*4); - + } + memset(payload, 0, MAX_ARRAY_PACKET * 4); + memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4); + /* carefully check packet contents */ - - narrays=payload[0]; - k=0; - i=1; - while((kbuf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; + cmdbuf->buf += (count + 2) * 4; + cmdbuf->bufsz -= (count + 2) * 4; return 0; } -static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf) +static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf) { u32 header; int count; @@ -473,36 +499,37 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv, if (4 > cmdbuf->bufsz) return DRM_ERR(EINVAL); - /* Fixme !! This simply emits a packet without much checking. + /* Fixme !! This simply emits a packet without much checking. We need to be smarter. */ /* obtain first word - actual packet3 header */ - header = *(u32 __user*)cmdbuf->buf; + header = *(u32 __user *) cmdbuf->buf; /* Is it packet 3 ? */ - if( (header>>30)!=0x3 ) { + if ((header >> 30) != 0x3) { DRM_ERROR("Not a packet3 header (0x%08x)\n", header); return DRM_ERR(EINVAL); - } + } - count=(header>>16) & 0x3fff; + count = (header >> 16) & 0x3fff; /* Check again now that we know how much data to expect */ - if ((count+2)*4 > cmdbuf->bufsz){ - DRM_ERROR("Expected packet3 of length %d but have only %d bytes left\n", - (count+2)*4, cmdbuf->bufsz); + if ((count + 2) * 4 > cmdbuf->bufsz) { + DRM_ERROR + ("Expected packet3 of length %d but have only %d bytes left\n", + (count + 2) * 4, cmdbuf->bufsz); return DRM_ERR(EINVAL); - } + } /* Is it a packet type we know about ? */ - switch(header & 0xff00){ - case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ + switch (header & 0xff00) { + case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */ return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header); - case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ - case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ - case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ - case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */ + case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */ + case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */ + case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */ + case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */ case RADEON_WAIT_FOR_IDLE: case RADEON_CP_NOP: /* these packets are safe */ @@ -510,32 +537,30 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t* dev_priv, default: DRM_ERROR("Unknown packet3 header (0x%08x)\n", header); return DRM_ERR(EINVAL); - } - + } - BEGIN_RING(count+2); + BEGIN_RING(count + 2); OUT_RING(header); - OUT_RING_TABLE( (int __user*)(cmdbuf->buf+4), count+1); + OUT_RING_TABLE((int __user *)(cmdbuf->buf + 4), count + 1); ADVANCE_RING(); - cmdbuf->buf += (count+2)*4; - cmdbuf->bufsz -= (count+2)*4; + cmdbuf->buf += (count + 2) * 4; + cmdbuf->bufsz -= (count + 2) * 4; return 0; } - /** * Emit a rendering packet3 from userspace. * Called by r300_do_cp_cmdbuf. */ -static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv, - drm_radeon_cmd_buffer_t* cmdbuf, +static __inline__ int r300_emit_packet3(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) { int n; int ret; - char __user* orig_buf = cmdbuf->buf; + char __user *orig_buf = cmdbuf->buf; int orig_bufsz = cmdbuf->bufsz; /* This is a do-while-loop so that we run the interior at least once, @@ -550,16 +575,16 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv, cmdbuf->buf = orig_buf; cmdbuf->bufsz = orig_bufsz; - } + } - switch(header.packet3.packet) { + switch (header.packet3.packet) { case R300_CMD_PACKET3_CLEAR: DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n"); ret = r300_emit_clear(dev_priv, cmdbuf); if (ret) { DRM_ERROR("r300_emit_clear failed\n"); return ret; - } + } break; case R300_CMD_PACKET3_RAW: @@ -568,18 +593,18 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv, if (ret) { DRM_ERROR("r300_emit_raw_packet3 failed\n"); return ret; - } + } break; default: DRM_ERROR("bad packet3 type %i at %p\n", - header.packet3.packet, - cmdbuf->buf - sizeof(header)); + header.packet3.packet, + cmdbuf->buf - sizeof(header)); return DRM_ERR(EINVAL); - } + } n += R300_SIMULTANEOUS_CLIPRECTS; - } while(n < cmdbuf->nbox); + } while (n < cmdbuf->nbox); return 0; } @@ -598,21 +623,20 @@ static __inline__ int r300_emit_packet3(drm_radeon_private_t* dev_priv, /** * Emit the sequence to pacify R300. */ -static __inline__ void r300_pacify(drm_radeon_private_t* dev_priv) +static __inline__ void r300_pacify(drm_radeon_private_t * dev_priv) { RING_LOCALS; BEGIN_RING(6); - OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); - OUT_RING( 0xa ); - OUT_RING( CP_PACKET0( 0x4f18, 0 ) ); - OUT_RING( 0x3 ); - OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) ); - OUT_RING( 0x0 ); + OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); + OUT_RING(0xa); + OUT_RING(CP_PACKET0(0x4f18, 0)); + OUT_RING(0x3); + OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); + OUT_RING(0x0); ADVANCE_RING(); } - /** * Called by r300_do_cp_cmdbuf to update the internal buffer age and state. * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must @@ -628,20 +652,18 @@ static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf) buf->used = 0; } - /** * Parses and validates a user-supplied command buffer and emits appropriate * commands on the DMA ring buffer. * Called by the ioctl handler function radeon_cp_cmdbuf. */ -int r300_do_cp_cmdbuf(drm_device_t* dev, - DRMFILE filp, - drm_file_t* filp_priv, - drm_radeon_cmd_buffer_t* cmdbuf) +int r300_do_cp_cmdbuf(drm_device_t * dev, + DRMFILE filp, + drm_file_t * filp_priv, drm_radeon_cmd_buffer_t * cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_device_dma_t *dma = dev->dma; - drm_buf_t *buf = NULL; + drm_device_dma_t *dma = dev->dma; + drm_buf_t *buf = NULL; int emit_dispatch_age = 0; int ret = 0; @@ -655,9 +677,9 @@ int r300_do_cp_cmdbuf(drm_device_t* dev, ret = r300_emit_cliprects(dev_priv, cmdbuf, 0); if (ret) goto cleanup; - } + } - while(cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { + while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) { int idx; drm_r300_cmd_header_t header; @@ -666,14 +688,14 @@ int r300_do_cp_cmdbuf(drm_device_t* dev, cmdbuf->buf += sizeof(header); cmdbuf->bufsz -= sizeof(header); - switch(header.header.cmd_type) { - case R300_CMD_PACKET0: + switch (header.header.cmd_type) { + case R300_CMD_PACKET0: DRM_DEBUG("R300_CMD_PACKET0\n"); ret = r300_emit_packet0(dev_priv, cmdbuf, header); if (ret) { DRM_ERROR("r300_emit_packet0 failed\n"); goto cleanup; - } + } break; case R300_CMD_VPU: @@ -682,7 +704,7 @@ int r300_do_cp_cmdbuf(drm_device_t* dev, if (ret) { DRM_ERROR("r300_emit_vpu failed\n"); goto cleanup; - } + } break; case R300_CMD_PACKET3: @@ -691,26 +713,26 @@ int r300_do_cp_cmdbuf(drm_device_t* dev, if (ret) { DRM_ERROR("r300_emit_packet3 failed\n"); goto cleanup; - } + } break; case R300_CMD_END3D: DRM_DEBUG("R300_CMD_END3D\n"); - /* TODO: - Ideally userspace driver should not need to issue this call, - i.e. the drm driver should issue it automatically and prevent - lockups. - - In practice, we do not understand why this call is needed and what - it does (except for some vague guesses that it has to do with cache - coherence) and so the user space driver does it. - - Once we are sure which uses prevent lockups the code could be moved - into the kernel and the userspace driver will not - need to use this command. - - Note that issuing this command does not hurt anything - except, possibly, performance */ + /* TODO: + Ideally userspace driver should not need to issue this call, + i.e. the drm driver should issue it automatically and prevent + lockups. + + In practice, we do not understand why this call is needed and what + it does (except for some vague guesses that it has to do with cache + coherence) and so the user space driver does it. + + Once we are sure which uses prevent lockups the code could be moved + into the kernel and the userspace driver will not + need to use this command. + + Note that issuing this command does not hurt anything + except, possibly, performance */ r300_pacify(dev_priv); break; @@ -722,7 +744,7 @@ int r300_do_cp_cmdbuf(drm_device_t* dev, RING_LOCALS; BEGIN_RING(header.delay.count); - for(i=0;i= dma->buf_count) { - DRM_ERROR("buffer index %d (of %d max)\n", - idx, dma->buf_count - 1); + idx = header.dma.buf_idx; + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + idx, dma->buf_count - 1); ret = DRM_ERR(EINVAL); - goto cleanup; - } - - buf = dma->buflist[idx]; - if (buf->filp != filp || buf->pending) { - DRM_ERROR("bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); - ret = DRM_ERR(EINVAL); goto cleanup; - } + } + + buf = dma->buflist[idx]; + if (buf->filp != filp || buf->pending) { + DRM_ERROR("bad buffer %p %p %d\n", + buf->filp, filp, buf->pending); + ret = DRM_ERR(EINVAL); + goto cleanup; + } emit_dispatch_age = 1; r300_discard_buffer(dev, buf); - break; + break; case R300_CMD_WAIT: /* simple enough, we can do it here */ DRM_DEBUG("R300_CMD_WAIT\n"); - if(header.wait.flags==0)break; /* nothing to do */ + if (header.wait.flags == 0) + break; /* nothing to do */ { RING_LOCALS; BEGIN_RING(2); - OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); - OUT_RING( (header.wait.flags & 0xf)<<14 ); + OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); + OUT_RING((header.wait.flags & 0xf) << 14); ADVANCE_RING(); } break; default: DRM_ERROR("bad cmd_type %i at %p\n", - header.header.cmd_type, + header.header.cmd_type, cmdbuf->buf - sizeof(header)); ret = DRM_ERR(EINVAL); goto cleanup; - } + } } DRM_DEBUG("END\n"); -cleanup: + cleanup: r300_pacify(dev_priv); /* We emit the vertex buffer age here, outside the pacifier "brackets" @@ -792,10 +815,9 @@ cleanup: BEGIN_RING(2); RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch); ADVANCE_RING(); - } + } COMMIT_RING(); return ret; } - diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h index c3e7ca3dbe3..e5b73c00239 100644 --- a/drivers/char/drm/r300_reg.h +++ b/drivers/char/drm/r300_reg.h @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 - #define R300_MC_INIT_GFX_LAT_TIMER 0x154 # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 @@ -62,7 +61,6 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_SE_VPORT_ZSCALE 0x1DA8 #define R300_SE_VPORT_ZOFFSET 0x1DAC - /* This register is written directly and also starts data section in many 3d CP_PACKET3's */ #define R300_VAP_VF_CNTL 0x2084 @@ -93,17 +91,17 @@ I am fairly certain that they are correct unless stated otherwise in comments. /* index size - when not set the indices are assumed to be 16 bit */ # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) - /* number of vertices */ + /* number of vertices */ # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 /* BEGIN: Wild guesses */ #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ -# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ +# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 @@ -159,14 +157,14 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) -# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ +# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 -# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ +# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ # define R300_VAP_INPUT_ROUTE_END (1 << 13) -# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ -# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ +# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ #define R300_VAP_INPUT_ROUTE_0_1 0x2154 #define R300_VAP_INPUT_ROUTE_0_2 0x2158 #define R300_VAP_INPUT_ROUTE_0_3 0x215C @@ -188,12 +186,12 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_INPUT_CNTL_COLOR 0x00000004 # define R300_INPUT_CNTL_TC0 0x00000400 # define R300_INPUT_CNTL_TC1 0x00000800 -# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ -# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ -# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ -# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ -# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ -# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ +# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ +# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ +# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ +# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ +# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ +# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ /* gap */ /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 @@ -270,12 +268,12 @@ I am fairly certain that they are correct unless stated otherwise in comments. // rendering commands and overwriting vertex program parameters. // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and // avoids bugs caused by still running shaders reading bad data from memory. */ -#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ +#define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ /* Absolutely no clue what this register is about. */ #define R300_VAP_UNKNOWN_2288 0x2288 -# define R300_2288_R300 0x00750000 /* -- nh */ -# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ +# define R300_2288_R300 0x00750000 /* -- nh */ +# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ /* gap */ /* Addresses are relative to the vertex program instruction area of the @@ -286,10 +284,10 @@ I am fairly certain that they are correct unless stated otherwise in comments. // experiments so far have shown that both *must* point to an instruction // inside the vertex program, otherwise the GPU locks up. // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and -// CNTL_1_UNKNOWN points to instruction where last write to position takes place. +// CNTL_1_UNKNOWN points to instruction where last write to position takes place. // Most likely this is used to ignore rest of the program in cases where group of verts arent visible. // For some reason this "section" is sometimes accepted other instruction that have -// no relationship with position calculations. +// no relationship with position calculations. */ #define R300_VAP_PVS_CNTL_1 0x22D0 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 @@ -308,13 +306,13 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_VAP_VTX_COLOR_R 0x2464 #define R300_VAP_VTX_COLOR_G 0x2468 #define R300_VAP_VTX_COLOR_B 0x246C -#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ +#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ #define R300_VAP_VTX_POS_0_Y_1 0x2494 -#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ -#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ +#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ +#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ #define R300_VAP_VTX_POS_0_Y_2 0x24A4 #define R300_VAP_VTX_POS_0_Z_2 0x24A8 -#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ +#define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ /* gap */ @@ -385,7 +383,6 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_GB_MSPOS1__MS_Y5_SHIFT 20 # define R300_GB_MSPOS1__MSBD1 24 - #define R300_GB_TILE_CONFIG 0x4018 # define R300_GB_TILE_ENABLE (1<<0) # define R300_GB_TILE_PIPE_COUNT_RV300 0 @@ -478,9 +475,9 @@ I am fairly certain that they are correct unless stated otherwise in comments. // framebuffer. */ #define R300_RE_POINTSIZE 0x421C # define R300_POINTSIZE_Y_SHIFT 0 -# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ +# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ # define R300_POINTSIZE_X_SHIFT 16 -# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ +# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) /* The line width is given in multiples of 6. @@ -491,7 +488,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. */ #define R300_RE_LINE_CNT 0x4234 # define R300_LINESIZE_SHIFT 0 -# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ +# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) # define R300_LINE_CNT_HO (1 << 16) # define R300_LINE_CNT_VE (1 << 17) @@ -513,8 +510,8 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_PM_BACK_LINE (1 << 7) # define R300_PM_BACK_FILL (1 << 8) -/* Not sure why there are duplicate of factor and constant values. - My best guess so far is that there are seperate zbiases for test and write. +/* Not sure why there are duplicate of factor and constant values. + My best guess so far is that there are seperate zbiases for test and write. Ordering might be wrong. Some of the tests indicate that fgl has a fallback implementation of zbias via pixel shaders. */ @@ -540,7 +537,6 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_FRONT_FACE_CCW (0 << 2) # define R300_FRONT_FACE_CW (1 << 2) - /* BEGIN: Rasterization / Interpolators - many guesses // 0_UNKNOWN_18 has always been set except for clear operations. // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends @@ -548,7 +544,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_RS_CNTL_0 0x4300 # define R300_RS_CNTL_TC_CNT_SHIFT 2 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2) -# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ +# define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ #define R300_RS_CNTL_1 0x4304 @@ -585,29 +581,29 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_RS_ROUTE_0 0x4330 #define R300_RS_ROUTE_1 0x4334 #define R300_RS_ROUTE_2 0x4338 -#define R300_RS_ROUTE_3 0x433C /* GUESS */ -#define R300_RS_ROUTE_4 0x4340 /* GUESS */ -#define R300_RS_ROUTE_5 0x4344 /* GUESS */ -#define R300_RS_ROUTE_6 0x4348 /* GUESS */ -#define R300_RS_ROUTE_7 0x434C /* GUESS */ +#define R300_RS_ROUTE_3 0x433C /* GUESS */ +#define R300_RS_ROUTE_4 0x4340 /* GUESS */ +#define R300_RS_ROUTE_5 0x4344 /* GUESS */ +#define R300_RS_ROUTE_6 0x4348 /* GUESS */ +#define R300_RS_ROUTE_7 0x434C /* GUESS */ # define R300_RS_ROUTE_SOURCE_INTERP_0 0 # define R300_RS_ROUTE_SOURCE_INTERP_1 1 # define R300_RS_ROUTE_SOURCE_INTERP_2 2 # define R300_RS_ROUTE_SOURCE_INTERP_3 3 # define R300_RS_ROUTE_SOURCE_INTERP_4 4 -# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ -# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ -# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ -# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ +# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ +# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ # define R300_RS_ROUTE_DEST_SHIFT 6 -# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ +# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ /* Special handling for color: When the fragment program uses color, // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the // color register index. */ # define R300_RS_ROUTE_0_COLOR (1 << 14) # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 -# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ +# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ /* As above, but for secondary color */ # define R300_RS_ROUTE_1_COLOR1 (1 << 14) # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 @@ -721,7 +717,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TX_HEIGHTMASK_SHIFT 11 # define R300_TX_HEIGHTMASK_MASK (2047 << 11) # define R300_TX_UNK23 (1 << 23) -# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ +# define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ # define R300_TX_SIZE_MASK (15 << 26) #define R300_TX_FORMAT_0 0x44C0 /* The interpretation of the format word by Wladimir van der Laan */ @@ -746,12 +742,12 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TX_FORMAT_DXT1 0xF # define R300_TX_FORMAT_DXT3 0x10 # define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ +# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ /* 0x16 - some 16 bit green format.. ?? */ -# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ +# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ /* gap */ /* Floating point formats */ @@ -777,8 +773,8 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TX_FORMAT_W 3 # define R300_TX_FORMAT_ZERO 4 # define R300_TX_FORMAT_ONE 5 -# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ # define R300_TX_FORMAT_B_SHIFT 18 # define R300_TX_FORMAT_G_SHIFT 15 @@ -811,7 +807,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_TXO_OFFSET_SHIFT 5 /* END */ #define R300_TX_UNK4_0 0x4580 -#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } +#define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } /* END */ @@ -844,9 +840,9 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_PFS_CNTL_ALU_END_SHIFT 6 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0) # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 -# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ +# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ # define R300_PFS_CNTL_TEX_END_SHIFT 18 -# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ +# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ /* gap */ /* Nodes are stored backwards. The last active node is always stored in @@ -877,11 +873,11 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_PFS_TEXI_0 0x4620 # define R300_FPITX_SRC_SHIFT 0 # define R300_FPITX_SRC_MASK (31 << 0) -# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ +# define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ # define R300_FPITX_DST_SHIFT 6 # define R300_FPITX_DST_MASK (31 << 6) # define R300_FPITX_IMAGE_SHIFT 11 -# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ +# define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ /* Unsure if these are opcodes, or some kind of bitfield, but this is how * they were set when I checked */ @@ -1003,7 +999,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_FPI0_ARGC_SRC1C_LRP 15 # define R300_FPI0_ARGC_ZERO 20 # define R300_FPI0_ARGC_ONE 21 -# define R300_FPI0_ARGC_HALF 22 /* GUESS */ +# define R300_FPI0_ARGC_HALF 22 /* GUESS */ # define R300_FPI0_ARGC_SRC0C_YZX 23 # define R300_FPI0_ARGC_SRC1C_YZX 24 # define R300_FPI0_ARGC_SRC2C_YZX 25 @@ -1054,20 +1050,20 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_FPI2_ARGA_SRC1A_LRP 15 # define R300_FPI2_ARGA_ZERO 16 # define R300_FPI2_ARGA_ONE 17 -# define R300_FPI2_ARGA_HALF 18 /* GUESS */ +# define R300_FPI2_ARGA_HALF 18 /* GUESS */ # define R300_FPI2_ARG0A_SHIFT 0 # define R300_FPI2_ARG0A_MASK (31 << 0) # define R300_FPI2_ARG0A_NEG (1 << 5) -# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ +# define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ # define R300_FPI2_ARG1A_SHIFT 7 # define R300_FPI2_ARG1A_MASK (31 << 7) # define R300_FPI2_ARG1A_NEG (1 << 12) -# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ +# define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ # define R300_FPI2_ARG2A_SHIFT 14 # define R300_FPI2_ARG2A_MASK (31 << 14) # define R300_FPI2_ARG2A_NEG (1 << 19) -# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ +# define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ # define R300_FPI2_SPECIAL_LRP (1 << 21) # define R300_FPI2_OUTA_MAD (0 << 23) # define R300_FPI2_OUTA_DP4 (1 << 23) @@ -1157,26 +1153,26 @@ I am fairly certain that they are correct unless stated otherwise in comments. /* gap */ #define R300_RB3D_COLOROFFSET0 0x4E28 -# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ -#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ -#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ -#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ +# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ +#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ +#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ +#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ /* gap */ /* Bit 16: Larger tiles // Bit 17: 4x2 tiles // Bit 18: Extremely weird tile like, but some pixels duplicated? */ #define R300_RB3D_COLORPITCH0 0x4E38 -# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ -# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ -# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ -# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ -# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ -# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ +# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ +# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ +# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ +# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ +# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ +# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ # define R300_COLOR_FORMAT_RGB565 (2 << 22) # define R300_COLOR_FORMAT_ARGB8888 (3 << 22) -#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ -#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ -#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ +#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ +#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ +#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ /* gap */ /* Guess by Vladimir. @@ -1189,8 +1185,8 @@ I am fairly certain that they are correct unless stated otherwise in comments. /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 -# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ -# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ +# define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ +# define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ # define R300_RB3D_Z_TEST 0x00000012 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 # define R300_RB3D_Z_WRITE_ONLY 0x00000006 @@ -1233,8 +1229,6 @@ I am fairly certain that they are correct unless stated otherwise in comments. # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 - - #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 # define R300_RB3D_ZS2_STENCIL_MASK 0xFF @@ -1250,12 +1244,12 @@ I am fairly certain that they are correct unless stated otherwise in comments. /* gap */ #define R300_RB3D_DEPTHOFFSET 0x4F20 #define R300_RB3D_DEPTHPITCH 0x4F24 -# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ -# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ -# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ -# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ -# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ -# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ +# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ +# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ +# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ +# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ +# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ +# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ /* BEGIN: Vertex program instruction set // Every instruction is four dwords long: @@ -1295,26 +1289,26 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_VPI_OUT_OP_MIN (8 << 0) #define R300_VPI_OUT_OP_SGE (9 << 0) #define R300_VPI_OUT_OP_SLT (10 << 0) -#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ +#define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ #define R300_VPI_OUT_OP_EXP (65 << 0) #define R300_VPI_OUT_OP_LOG (66 << 0) -#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ +#define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ #define R300_VPI_OUT_OP_LIT (68 << 0) #define R300_VPI_OUT_OP_POW (69 << 0) #define R300_VPI_OUT_OP_RCP (70 << 0) #define R300_VPI_OUT_OP_RSQ (72 << 0) -#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ +#define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ #define R300_VPI_OUT_OP_EX2 (75 << 0) #define R300_VPI_OUT_OP_LG2 (76 << 0) #define R300_VPI_OUT_OP_MAD_2 (128 << 0) -#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ +#define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) #define R300_VPI_OUT_REG_INDEX_SHIFT 13 -#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ +#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ #define R300_VPI_OUT_WRITE_X (1 << 20) #define R300_VPI_OUT_WRITE_Y (1 << 21) @@ -1325,10 +1319,10 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) #define R300_VPI_IN_REG_CLASS_NONE (9 << 0) -#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ +#define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ #define R300_VPI_IN_REG_INDEX_SHIFT 5 -#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ +#define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ /* The R300 can select components from the input register arbitrarily. // Use the following constants, shifted by the component shift you @@ -1366,7 +1360,7 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_PRIM_TYPE_RECT_LIST (8 << 0) #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) -#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) +#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) #define R300_PRIM_TYPE_LINE_LOOP (12 << 0) #define R300_PRIM_TYPE_QUADS (13 << 0) #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) @@ -1376,8 +1370,8 @@ I am fairly certain that they are correct unless stated otherwise in comments. #define R300_PRIM_WALK_LIST (2 << 4) #define R300_PRIM_WALK_RING (3 << 4) #define R300_PRIM_WALK_MASK (3 << 4) -#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) -#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS +#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) +#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS #define R300_PRIM_NUM_VERTICES_SHIFT 16 // Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. @@ -1409,4 +1403,4 @@ I am fairly certain that they are correct unless stated otherwise in comments. //END -#endif /* _R300_REG_H */ +#endif /* _R300_REG_H */ diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 6dff5e43f71..447bfbe0da8 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c @@ -36,788 +36,787 @@ #define RADEON_FIFO_DEBUG 0 -static int radeon_do_cleanup_cp( drm_device_t *dev ); +static int radeon_do_cleanup_cp(drm_device_t * dev); /* CP microcode (from ATI) */ static u32 R200_cp_microcode[][2] = { - { 0x21007000, 0000000000 }, - { 0x20007000, 0000000000 }, - { 0x000000ab, 0x00000004 }, - { 0x000000af, 0x00000004 }, - { 0x66544a49, 0000000000 }, - { 0x49494174, 0000000000 }, - { 0x54517d83, 0000000000 }, - { 0x498d8b64, 0000000000 }, - { 0x49494949, 0000000000 }, - { 0x49da493c, 0000000000 }, - { 0x49989898, 0000000000 }, - { 0xd34949d5, 0000000000 }, - { 0x9dc90e11, 0000000000 }, - { 0xce9b9b9b, 0000000000 }, - { 0x000f0000, 0x00000016 }, - { 0x352e232c, 0000000000 }, - { 0x00000013, 0x00000004 }, - { 0x000f0000, 0x00000016 }, - { 0x352e272c, 0000000000 }, - { 0x000f0001, 0x00000016 }, - { 0x3239362f, 0000000000 }, - { 0x000077ef, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00061000, 0x00000002 }, - { 0x00000020, 0x0000001a }, - { 0x00004000, 0x0000001e }, - { 0x00000016, 0x00000004 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000002 }, - { 0x00000016, 0x00000004 }, - { 0x000077e0, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x000037e1, 0x00000002 }, - { 0x040067e1, 0x00000006 }, - { 0x000077e0, 0x00000002 }, - { 0x000077e1, 0x00000002 }, - { 0x000077e1, 0x00000006 }, - { 0xffffffff, 0000000000 }, - { 0x10000000, 0000000000 }, - { 0x0003802a, 0x00000002 }, - { 0x040067e0, 0x00000006 }, - { 0x00007675, 0x00000002 }, - { 0x00007676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0003802b, 0x00000002 }, - { 0x04002676, 0x00000002 }, - { 0x00007677, 0x00000002 }, - { 0x00007678, 0x00000006 }, - { 0x0000002e, 0x00000018 }, - { 0x0000002e, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x0000002f, 0x00000018 }, - { 0x0000002f, 0x00000018 }, - { 0000000000, 0x00000006 }, - { 0x01605000, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00098000, 0x00000002 }, - { 0x00061000, 0x00000002 }, - { 0x64c0603d, 0x00000004 }, - { 0x00080000, 0x00000016 }, - { 0000000000, 0000000000 }, - { 0x0400251d, 0x00000002 }, - { 0x00007580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x04002580, 0x00000002 }, - { 0x00067581, 0x00000002 }, - { 0x00000046, 0x00000004 }, - { 0x00005000, 0000000000 }, - { 0x00061000, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x00019000, 0x00000002 }, - { 0x00011055, 0x00000014 }, - { 0x00000055, 0x00000012 }, - { 0x0400250f, 0x00000002 }, - { 0x0000504a, 0x00000004 }, - { 0x00007565, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000051, 0x00000004 }, - { 0x01e655b4, 0x00000002 }, - { 0x4401b0dc, 0x00000002 }, - { 0x01c110dc, 0x00000002 }, - { 0x2666705d, 0x00000018 }, - { 0x040c2565, 0x00000002 }, - { 0x0000005d, 0x00000018 }, - { 0x04002564, 0x00000002 }, - { 0x00007566, 0x00000002 }, - { 0x00000054, 0x00000004 }, - { 0x00401060, 0x00000008 }, - { 0x00101000, 0x00000002 }, - { 0x000d80ff, 0x00000002 }, - { 0x00800063, 0x00000008 }, - { 0x000f9000, 0x00000002 }, - { 0x000e00ff, 0x00000002 }, - { 0000000000, 0x00000006 }, - { 0x00000080, 0x00000018 }, - { 0x00000054, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00065000, 0x00000002 }, - { 0x00009000, 0x00000002 }, - { 0x00041000, 0x00000002 }, - { 0x0c00350e, 0x00000002 }, - { 0x00049000, 0x00000002 }, - { 0x00051000, 0x00000002 }, - { 0x01e785f8, 0x00000002 }, - { 0x00200000, 0x00000002 }, - { 0x00600073, 0x0000000c }, - { 0x00007563, 0x00000002 }, - { 0x006075f0, 0x00000021 }, - { 0x20007068, 0x00000004 }, - { 0x00005068, 0x00000004 }, - { 0x00007576, 0x00000002 }, - { 0x00007577, 0x00000002 }, - { 0x0000750e, 0x00000002 }, - { 0x0000750f, 0x00000002 }, - { 0x00a05000, 0x00000002 }, - { 0x00600076, 0x0000000c }, - { 0x006075f0, 0x00000021 }, - { 0x000075f8, 0x00000002 }, - { 0x00000076, 0x00000004 }, - { 0x000a750e, 0x00000002 }, - { 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{0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, }; static u32 R300_cp_microcode[][2] = { - { 0x4200e000, 0000000000 }, - { 0x4000e000, 0000000000 }, - { 0x000000af, 0x00000008 }, - { 0x000000b3, 0x00000008 }, - { 0x6c5a504f, 0000000000 }, - { 0x4f4f497a, 0000000000 }, - { 0x5a578288, 0000000000 }, - { 0x4f91906a, 0000000000 }, - { 0x4f4f4f4f, 0000000000 }, - { 0x4fe24f44, 0000000000 }, - { 0x4f9c9c9c, 0000000000 }, - { 0xdc4f4fde, 0000000000 }, - { 0xa1cd4f4f, 0000000000 }, - { 0xd29d9d9d, 0000000000 }, - { 0x4f0f9fd7, 0000000000 }, - { 0x000ca000, 0x00000004 }, - { 0x000d0012, 0x00000038 }, - { 0x0000e8b4, 0x00000004 }, - { 0x000d0014, 0x00000038 }, - { 0x0000e8b6, 0x00000004 }, - { 0x000d0016, 0x00000038 }, - { 0x0000e854, 0x00000004 }, - { 0x000d0018, 0x00000038 }, - { 0x0000e855, 0x00000004 }, - { 0x000d001a, 0x00000038 }, - { 0x0000e856, 0x00000004 }, - { 0x000d001c, 0x00000038 }, - { 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0x000000c4, 0x00000008 }, - { 0x0080e5bd, 0x00000005 }, - { 0x0000e5bb, 0x00000005 }, - { 0x0080e5bc, 0x00000005 }, - { 0x00210000, 0x00000004 }, - { 0x02800000, 0x00000004 }, - { 0x00c000c8, 0x00000018 }, - { 0x4180e000, 0x00000040 }, - { 0x000000ca, 0x00000024 }, - { 0x01000000, 0x0000000c }, - { 0x0100e51d, 0x0000000c }, - { 0x000045bb, 0x00000004 }, - { 0x000080c4, 0x00000008 }, - { 0x0000f3ce, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053cf, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f3d2, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c053d3, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x0000f39d, 0x00000004 }, - { 0x0140a000, 0x00000004 }, - { 0x00cc2000, 0x00000004 }, - { 0x08c0539e, 0x00000040 }, - { 0x00008000, 0000000000 }, - { 0x03c00830, 0x00000004 }, - { 0x4200e000, 0000000000 }, - { 0x0000a000, 0x00000004 }, - { 0x200045e0, 0x00000004 }, - { 0x0000e5e1, 0000000000 }, - { 0x00000001, 0000000000 }, - { 0x000700e1, 0x00000004 }, - { 0x0800e394, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, - { 0000000000, 0000000000 }, + {0x4200e000, 0000000000}, + {0x4000e000, 0000000000}, + {0x000000af, 0x00000008}, + {0x000000b3, 0x00000008}, + {0x6c5a504f, 0000000000}, + {0x4f4f497a, 0000000000}, + {0x5a578288, 0000000000}, + {0x4f91906a, 0000000000}, + {0x4f4f4f4f, 0000000000}, + {0x4fe24f44, 0000000000}, + {0x4f9c9c9c, 0000000000}, + {0xdc4f4fde, 0000000000}, + {0xa1cd4f4f, 0000000000}, + {0xd29d9d9d, 0000000000}, + {0x4f0f9fd7, 0000000000}, + {0x000ca000, 0x00000004}, + {0x000d0012, 0x00000038}, + {0x0000e8b4, 0x00000004}, + {0x000d0014, 0x00000038}, + {0x0000e8b6, 0x00000004}, + {0x000d0016, 0x00000038}, + {0x0000e854, 0x00000004}, + {0x000d0018, 0x00000038}, + {0x0000e855, 0x00000004}, + {0x000d001a, 0x00000038}, + {0x0000e856, 0x00000004}, + {0x000d001c, 0x00000038}, + {0x0000e857, 0x00000004}, + {0x000d001e, 0x00000038}, + {0x0000e824, 0x00000004}, + {0x000d0020, 0x00000038}, + {0x0000e825, 0x00000004}, + {0x000d0022, 0x00000038}, + {0x0000e830, 0x00000004}, + {0x000d0024, 0x00000038}, + {0x0000f0c0, 0x00000004}, + {0x000d0026, 0x00000038}, + {0x0000f0c1, 0x00000004}, + {0x000d0028, 0x00000038}, + {0x0000f041, 0x00000004}, + {0x000d002a, 0x00000038}, + {0x0000f184, 0x00000004}, + {0x000d002c, 0x00000038}, + {0x0000f185, 0x00000004}, + {0x000d002e, 0x00000038}, + {0x0000f186, 0x00000004}, + {0x000d0030, 0x00000038}, + {0x0000f187, 0x00000004}, + {0x000d0032, 0x00000038}, + {0x0000f180, 0x00000004}, + {0x000d0034, 0x00000038}, + {0x0000f393, 0x00000004}, + {0x000d0036, 0x00000038}, + {0x0000f38a, 0x00000004}, + {0x000d0038, 0x00000038}, + {0x0000f38e, 0x00000004}, + {0x0000e821, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x00000043, 0x00000018}, + {0x00cce800, 0x00000004}, + {0x001b0001, 0x00000004}, + {0x08004800, 0x00000004}, + {0x001b0001, 0x00000004}, + {0x08004800, 0x00000004}, + {0x001b0001, 0x00000004}, + {0x08004800, 0x00000004}, + {0x0000003a, 0x00000008}, + {0x0000a000, 0000000000}, + {0x02c0a000, 0x00000004}, + {0x000ca000, 0x00000004}, + {0x00130000, 0x00000004}, + {0x000c2000, 0x00000004}, + {0xc980c045, 0x00000008}, + {0x2000451d, 0x00000004}, + {0x0000e580, 0x00000004}, + {0x000ce581, 0x00000004}, + {0x08004580, 0x00000004}, + {0x000ce581, 0x00000004}, + {0x0000004c, 0x00000008}, + {0x0000a000, 0000000000}, + {0x000c2000, 0x00000004}, + {0x0000e50e, 0x00000004}, + {0x00032000, 0x00000004}, + {0x00022056, 0x00000028}, + {0x00000056, 0x00000024}, + {0x0800450f, 0x00000004}, + {0x0000a050, 0x00000008}, + {0x0000e565, 0x00000004}, + {0x0000e566, 0x00000004}, + {0x00000057, 0x00000008}, + {0x03cca5b4, 0x00000004}, + {0x05432000, 0x00000004}, + {0x00022000, 0x00000004}, + {0x4ccce063, 0x00000030}, + {0x08274565, 0x00000004}, + {0x00000063, 0x00000030}, + {0x08004564, 0x00000004}, + {0x0000e566, 0x00000004}, + {0x0000005a, 0x00000008}, + {0x00802066, 0x00000010}, + {0x00202000, 0x00000004}, + {0x001b00ff, 0x00000004}, + {0x01000069, 0x00000010}, + {0x001f2000, 0x00000004}, + {0x001c00ff, 0x00000004}, + {0000000000, 0x0000000c}, + {0x00000085, 0x00000030}, + {0x0000005a, 0x00000008}, + {0x0000e576, 0x00000004}, + {0x000ca000, 0x00000004}, + {0x00012000, 0x00000004}, + {0x00082000, 0x00000004}, + {0x1800650e, 0x00000004}, + {0x00092000, 0x00000004}, + {0x000a2000, 0x00000004}, + {0x000f0000, 0x00000004}, + {0x00400000, 0x00000004}, + {0x00000079, 0x00000018}, + {0x0000e563, 0x00000004}, + {0x00c0e5f9, 0x000000c2}, + {0x0000006e, 0x00000008}, + {0x0000a06e, 0x00000008}, + {0x0000e576, 0x00000004}, + {0x0000e577, 0x00000004}, + {0x0000e50e, 0x00000004}, + {0x0000e50f, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x0000007c, 0x00000018}, + {0x00c0e5f9, 0x000000c2}, + {0x0000007c, 0x00000008}, + {0x0014e50e, 0x00000004}, + {0x0040e50f, 0x00000004}, + {0x00c0007f, 0x00000008}, + {0x0000e570, 0x00000004}, + {0x0000e571, 0x00000004}, + {0x0000e572, 0x0000000c}, + {0x0000a000, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x0000e568, 0x00000004}, + {0x000c2000, 0x00000004}, + {0x00000089, 0x00000018}, + {0x000b0000, 0x00000004}, + {0x18c0e562, 0x00000004}, + {0x0000008b, 0x00000008}, + {0x00c0008a, 0x00000008}, + {0x000700e4, 0x00000004}, + {0x00000097, 0x00000038}, + {0x000ca099, 0x00000030}, + {0x080045bb, 0x00000004}, + {0x000c209a, 0x00000030}, + {0x0800e5bc, 0000000000}, + {0x0000e5bb, 0x00000004}, + {0x0000e5bc, 0000000000}, + {0x00120000, 0x0000000c}, + {0x00120000, 0x00000004}, + {0x001b0002, 0x0000000c}, + {0x0000a000, 0x00000004}, + {0x0000e821, 0x00000004}, + {0x0000e800, 0000000000}, + {0x0000e821, 0x00000004}, + {0x0000e82e, 0000000000}, + {0x02cca000, 0x00000004}, + {0x00140000, 0x00000004}, + {0x000ce1cc, 0x00000004}, + {0x050de1cd, 0x00000004}, + {0x000000a7, 0x00000020}, + {0x4200e000, 0000000000}, + {0x000000ae, 0x00000038}, + {0x000ca000, 0x00000004}, + {0x00140000, 0x00000004}, + {0x000c2000, 0x00000004}, + {0x00160000, 0x00000004}, + {0x700ce000, 0x00000004}, + {0x001400aa, 0x00000008}, + {0x4000e000, 0000000000}, + {0x02400000, 0x00000004}, + {0x400ee000, 0x00000004}, + {0x02400000, 0x00000004}, + {0x4000e000, 0000000000}, + {0x000c2000, 0x00000004}, + {0x0240e51b, 0x00000004}, + {0x0080e50a, 0x00000005}, + {0x0080e50b, 0x00000005}, + {0x00220000, 0x00000004}, + {0x000700e4, 0x00000004}, + {0x000000c1, 0x00000038}, + {0x000c209a, 0x00000030}, + {0x0880e5bd, 0x00000005}, + {0x000c2099, 0x00000030}, + {0x0800e5bb, 0x00000005}, + {0x000c209a, 0x00000030}, + {0x0880e5bc, 0x00000005}, + {0x000000c4, 0x00000008}, + {0x0080e5bd, 0x00000005}, + {0x0000e5bb, 0x00000005}, + {0x0080e5bc, 0x00000005}, + {0x00210000, 0x00000004}, + {0x02800000, 0x00000004}, + {0x00c000c8, 0x00000018}, + {0x4180e000, 0x00000040}, + {0x000000ca, 0x00000024}, + {0x01000000, 0x0000000c}, + {0x0100e51d, 0x0000000c}, + {0x000045bb, 0x00000004}, + {0x000080c4, 0x00000008}, + {0x0000f3ce, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x00cc2000, 0x00000004}, + {0x08c053cf, 0x00000040}, + {0x00008000, 0000000000}, + {0x0000f3d2, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x00cc2000, 0x00000004}, + {0x08c053d3, 0x00000040}, + {0x00008000, 0000000000}, + {0x0000f39d, 0x00000004}, + {0x0140a000, 0x00000004}, + {0x00cc2000, 0x00000004}, + {0x08c0539e, 0x00000040}, + {0x00008000, 0000000000}, + {0x03c00830, 0x00000004}, + {0x4200e000, 0000000000}, + {0x0000a000, 0x00000004}, + {0x200045e0, 0x00000004}, + {0x0000e5e1, 0000000000}, + {0x00000001, 0000000000}, + {0x000700e1, 0x00000004}, + {0x0800e394, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, + {0000000000, 0000000000}, }; -static int RADEON_READ_PLL(drm_device_t *dev, int addr) +static int RADEON_READ_PLL(drm_device_t * dev, int addr) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -825,151 +824,148 @@ static int RADEON_READ_PLL(drm_device_t *dev, int addr) return RADEON_READ(RADEON_CLOCK_CNTL_DATA); } -static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) +static int RADEON_READ_PCIE(drm_radeon_private_t * dev_priv, int addr) { RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); return RADEON_READ(RADEON_PCIE_DATA); } #if RADEON_FIFO_DEBUG -static void radeon_status( drm_radeon_private_t *dev_priv ) +static void radeon_status(drm_radeon_private_t * dev_priv) { - printk( "%s:\n", __FUNCTION__ ); - printk( "RBBM_STATUS = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) ); - printk( "CP_RB_RTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) ); - printk( "CP_RB_WTPR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) ); - printk( "AIC_CNTL = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) ); - printk( "AIC_STAT = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_STAT ) ); - printk( "AIC_PT_BASE = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) ); - printk( "TLB_ADDR = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) ); - printk( "TLB_DATA = 0x%08x\n", - (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) ); + printk("%s:\n", __FUNCTION__); + printk("RBBM_STATUS = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); + printk("CP_RB_RTPR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); + printk("CP_RB_WTPR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); + printk("AIC_CNTL = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); + printk("AIC_STAT = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_STAT)); + printk("AIC_PT_BASE = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); + printk("TLB_ADDR = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); + printk("TLB_DATA = 0x%08x\n", + (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); } #endif - /* ================================================================ * Engine, FIFO control */ -static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv ) +static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) { u32 tmp; int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ); + tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT); tmp |= RADEON_RB2D_DC_FLUSH_ALL; - RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp ); + RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT ) - & RADEON_RB2D_DC_BUSY) ) { + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT) + & RADEON_RB2D_DC_BUSY)) { return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } -static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv, - int entries ) +static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) { int i; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - int slots = ( RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_FIFOCNT_MASK ); - if ( slots >= entries ) return 0; - DRM_UDELAY( 1 ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + int slots = (RADEON_READ(RADEON_RBBM_STATUS) + & RADEON_RBBM_FIFOCNT_MASK); + if (slots >= entries) + return 0; + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } -static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv ) +static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) { int i, ret; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - ret = radeon_do_wait_for_fifo( dev_priv, 64 ); - if ( ret ) return ret; + ret = radeon_do_wait_for_fifo(dev_priv, 64); + if (ret) + return ret; - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - if ( !(RADEON_READ( RADEON_RBBM_STATUS ) - & RADEON_RBBM_ACTIVE) ) { - radeon_do_pixcache_flush( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + if (!(RADEON_READ(RADEON_RBBM_STATUS) + & RADEON_RBBM_ACTIVE)) { + radeon_do_pixcache_flush(dev_priv); return 0; } - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } #if RADEON_FIFO_DEBUG - DRM_ERROR( "failed!\n" ); - radeon_status( dev_priv ); + DRM_ERROR("failed!\n"); + radeon_status(dev_priv); #endif return DRM_ERR(EBUSY); } - /* ================================================================ * CP control, initialization */ /* Load the microcode for the CP */ -static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) +static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) { int i; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); - RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 ); + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); - if (dev_priv->microcode_version==UCODE_R200) { + if (dev_priv->microcode_version == UCODE_R200) { DRM_INFO("Loading R200 Microcode\n"); - for ( i = 0 ; i < 256 ; i++ ) - { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - R200_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - R200_cp_microcode[i][0] ); + for (i = 0; i < 256; i++) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, + R200_cp_microcode[i][1]); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, + R200_cp_microcode[i][0]); } - } else if (dev_priv->microcode_version==UCODE_R300) { + } else if (dev_priv->microcode_version == UCODE_R300) { DRM_INFO("Loading R300 Microcode\n"); - for ( i = 0 ; i < 256 ; i++ ) - { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - R300_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - R300_cp_microcode[i][0] ); + for (i = 0; i < 256; i++) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, + R300_cp_microcode[i][1]); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, + R300_cp_microcode[i][0]); } } else { - for ( i = 0 ; i < 256 ; i++ ) { - RADEON_WRITE( RADEON_CP_ME_RAM_DATAH, - radeon_cp_microcode[i][1] ); - RADEON_WRITE( RADEON_CP_ME_RAM_DATAL, - radeon_cp_microcode[i][0] ); + for (i = 0; i < 256; i++) { + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, + radeon_cp_microcode[i][1]); + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, + radeon_cp_microcode[i][0]); } } } @@ -978,25 +974,25 @@ static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv ) * prior to a wait for idle, as it informs the engine that the command * stream is ending. */ -static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); #if 0 u32 tmp; - tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31); - RADEON_WRITE( RADEON_CP_RB_WPTR, tmp ); + tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); + RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); #endif } /* Wait for the CP to go idle. */ -int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) +int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) { RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); @@ -1005,23 +1001,23 @@ int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ) ADVANCE_RING(); COMMIT_RING(); - return radeon_do_wait_for_idle( dev_priv ); + return radeon_do_wait_for_idle(dev_priv); } /* Start the Command Processor. */ -static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) { RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); - RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode ); + RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); dev_priv->cp_running = 1; - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_PURGE_CACHE(); RADEON_PURGE_ZCACHE(); @@ -1035,14 +1031,14 @@ static void radeon_do_cp_start( drm_radeon_private_t *dev_priv ) * commands, so you must wait for the CP command stream to complete * before calling this routine. */ -static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) { u32 cur_read_ptr; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); + cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); + RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); + SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; } @@ -1050,120 +1046,116 @@ static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv ) * commands, so you must flush the command stream and wait for the CP * to go idle before calling this routine. */ -static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv ) +static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) { - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS ); + RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); dev_priv->cp_running = 0; } /* Reset the engine. This will stop the CP if it is running. */ -static int radeon_do_engine_reset( drm_device_t *dev ) +static int radeon_do_engine_reset(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; - DRM_DEBUG( "\n" ); - - radeon_do_pixcache_flush( dev_priv ); - - clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX ); - mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL ); - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl | - RADEON_FORCEON_MCLKA | - RADEON_FORCEON_MCLKB | - RADEON_FORCEON_YCLKA | - RADEON_FORCEON_YCLKB | - RADEON_FORCEON_MC | - RADEON_FORCEON_AIC ) ); - - rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET ); + DRM_DEBUG("\n"); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset | - RADEON_SOFT_RESET_CP | + radeon_do_pixcache_flush(dev_priv); + + clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); + mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); + + RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | + RADEON_FORCEON_MCLKA | + RADEON_FORCEON_MCLKB | + RADEON_FORCEON_YCLKA | + RADEON_FORCEON_YCLKB | + RADEON_FORCEON_MC | + RADEON_FORCEON_AIC)); + + rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); + + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | + RADEON_SOFT_RESET_CP | + RADEON_SOFT_RESET_HI | + RADEON_SOFT_RESET_SE | + RADEON_SOFT_RESET_RE | + RADEON_SOFT_RESET_PP | + RADEON_SOFT_RESET_E2 | + RADEON_SOFT_RESET_RB)); + RADEON_READ(RADEON_RBBM_SOFT_RESET); + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & + ~(RADEON_SOFT_RESET_CP | RADEON_SOFT_RESET_HI | RADEON_SOFT_RESET_SE | RADEON_SOFT_RESET_RE | RADEON_SOFT_RESET_PP | RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset & - ~( RADEON_SOFT_RESET_CP | - RADEON_SOFT_RESET_HI | - RADEON_SOFT_RESET_SE | - RADEON_SOFT_RESET_RE | - RADEON_SOFT_RESET_PP | - RADEON_SOFT_RESET_E2 | - RADEON_SOFT_RESET_RB ) ) ); - RADEON_READ( RADEON_RBBM_SOFT_RESET ); - - - RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl ); - RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index ); - RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset ); + RADEON_SOFT_RESET_RB))); + RADEON_READ(RADEON_RBBM_SOFT_RESET); + + RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); + RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); /* Reset the CP ring */ - radeon_do_cp_reset( dev_priv ); + radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; /* Reset any pending vertex, indirect buffers */ - radeon_freelist_reset( dev ); + radeon_freelist_reset(dev); return 0; } -static void radeon_cp_init_ring_buffer( drm_device_t *dev, - drm_radeon_private_t *dev_priv ) +static void radeon_cp_init_ring_buffer(drm_device_t * dev, + drm_radeon_private_t * dev_priv) { u32 ring_start, cur_read_ptr; u32 tmp; /* Initialize the memory controller */ - RADEON_WRITE( RADEON_MC_FB_LOCATION, - ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 ) - | ( dev_priv->fb_location >> 16 ) ); + RADEON_WRITE(RADEON_MC_FB_LOCATION, + ((dev_priv->gart_vm_start - 1) & 0xffff0000) + | (dev_priv->fb_location >> 16)); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - RADEON_WRITE( RADEON_MC_AGP_LOCATION, - (((dev_priv->gart_vm_start - 1 + - dev_priv->gart_size) & 0xffff0000) | - (dev_priv->gart_vm_start >> 16)) ); + if (!dev_priv->is_pci) { + RADEON_WRITE(RADEON_MC_AGP_LOCATION, + (((dev_priv->gart_vm_start - 1 + + dev_priv->gart_size) & 0xffff0000) | + (dev_priv->gart_vm_start >> 16))); ring_start = (dev_priv->cp_ring->offset - - dev->agp->base - + dev_priv->gart_vm_start); - } else + - dev->agp->base + dev_priv->gart_vm_start); + } else #endif ring_start = (dev_priv->cp_ring->offset - - dev->sg->handle - + dev_priv->gart_vm_start); + - dev->sg->handle + dev_priv->gart_vm_start); - RADEON_WRITE( RADEON_CP_RB_BASE, ring_start ); + RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); /* Set the write pointer delay */ - RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 ); + RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); /* Initialize the ring buffer's read and write pointers */ - cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR ); - RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr ); - SET_RING_HEAD( dev_priv, cur_read_ptr ); + cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); + RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); + SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { + if (!dev_priv->is_pci) { /* set RADEON_AGP_BASE here instead of relying on X from user space */ RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - dev_priv->ring_rptr->offset - - dev->agp->base - + dev_priv->gart_vm_start); + RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, + dev_priv->ring_rptr->offset + - dev->agp->base + dev_priv->gart_vm_start); } else #endif { @@ -1173,11 +1165,10 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; page_ofs = tmp_ofs >> PAGE_SHIFT; - RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, - entry->busaddr[page_ofs]); - DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", - (unsigned long) entry->busaddr[page_ofs], - entry->handle + tmp_ofs ); + RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]); + DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n", + (unsigned long)entry->busaddr[page_ofs], + entry->handle + tmp_ofs); } /* Initialize the scratch register pointer. This will cause @@ -1187,64 +1178,64 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev, * We simply put this behind the ring read pointer, this works * with PCI GART as well as (whatever kind of) AGP GART */ - RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR ) - + RADEON_SCRATCH_REG_OFFSET ); + RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) + + RADEON_SCRATCH_REG_OFFSET); dev_priv->scratch = ((__volatile__ u32 *) dev_priv->ring_rptr->handle + (RADEON_SCRATCH_REG_OFFSET / sizeof(u32))); - RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 ); + RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); /* Writeback doesn't seem to work everywhere, test it first */ - DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 ); - RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef ); + DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0); + RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); - for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) { - if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef ) + for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { + if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) == + 0xdeadbeef) break; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } - if ( tmp < dev_priv->usec_timeout ) { + if (tmp < dev_priv->usec_timeout) { dev_priv->writeback_works = 1; - DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp ); + DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp); } else { dev_priv->writeback_works = 0; - DRM_DEBUG( "writeback test failed\n" ); + DRM_DEBUG("writeback test failed\n"); } dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; - RADEON_WRITE( RADEON_LAST_FRAME_REG, - dev_priv->sarea_priv->last_frame ); + RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; - RADEON_WRITE( RADEON_LAST_DISPATCH_REG, - dev_priv->sarea_priv->last_dispatch ); + RADEON_WRITE(RADEON_LAST_DISPATCH_REG, + dev_priv->sarea_priv->last_dispatch); dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; - RADEON_WRITE( RADEON_LAST_CLEAR_REG, - dev_priv->sarea_priv->last_clear ); + RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); /* Set ring buffer size */ #ifdef __BIG_ENDIAN - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT ); + RADEON_WRITE(RADEON_CP_RB_CNTL, + dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT); #else - RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw ); + RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw); #endif - radeon_do_wait_for_idle( dev_priv ); + radeon_do_wait_for_idle(dev_priv); /* Turn on bus mastering */ - tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE( RADEON_BUS_CNTL, tmp ); + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE(RADEON_BUS_CNTL, tmp); /* Sync everything up */ - RADEON_WRITE( RADEON_ISYNC_CNTL, - (RADEON_ISYNC_ANY2D_IDLE3D | - RADEON_ISYNC_ANY3D_IDLE2D | - RADEON_ISYNC_WAIT_IDLEGUI | - RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); + RADEON_WRITE(RADEON_ISYNC_CNTL, + (RADEON_ISYNC_ANY2D_IDLE3D | + RADEON_ISYNC_ANY3D_IDLE2D | + RADEON_ISYNC_WAIT_IDLEGUI | + RADEON_ISYNC_CPSCRATCH_IDLEGUI)); } /* Enable or disable PCI-E GART on the chip */ @@ -1254,35 +1245,42 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) if (on) { DRM_DEBUG("programming pcie %08X %08lX %08X\n", - dev_priv->gart_vm_start, (long)dev_priv->gart_info.bus_addr, + dev_priv->gart_vm_start, + (long)dev_priv->gart_info.bus_addr, dev_priv->gart_size); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, dev_priv->gart_vm_start); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, dev_priv->gart_info.bus_addr); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, dev_priv->gart_vm_start); - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, dev_priv->gart_vm_start - + dev_priv->gart_size - 1); - + RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, + dev_priv->gart_vm_start); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, + dev_priv->gart_info.bus_addr); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, + dev_priv->gart_vm_start); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, + dev_priv->gart_vm_start + + dev_priv->gart_size - 1); + RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ - - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, RADEON_PCIE_TX_GART_EN); + + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, + RADEON_PCIE_TX_GART_EN); } else { - RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); + RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, + tmp & ~RADEON_PCIE_TX_GART_EN); } } /* Enable or disable PCI GART on the chip */ -static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) +static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) { - u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); + u32 tmp = RADEON_READ(RADEON_AIC_CNTL); - if (dev_priv->flags & CHIP_IS_PCIE) - { + if (dev_priv->flags & CHIP_IS_PCIE) { radeon_set_pciegart(dev_priv, on); return; } - if ( on ) { - RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); + if (on) { + RADEON_WRITE(RADEON_AIC_CNTL, + tmp | RADEON_PCIGART_TRANSLATE_EN); /* set PCI GART page-table base address */ @@ -1290,53 +1288,54 @@ static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) /* set address range for PCI address translate */ - RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start ); - RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start - + dev_priv->gart_size - 1); + RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); + RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start + + dev_priv->gart_size - 1); /* Turn off AGP aperture -- is this required for PCI GART? */ - RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ - RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ + RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */ + RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ } else { - RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); + RADEON_WRITE(RADEON_AIC_CNTL, + tmp & ~RADEON_PCIGART_TRANSLATE_EN); } } -static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) +static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init) { drm_radeon_private_t *dev_priv = dev->dev_private;; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); dev_priv->is_pci = init->is_pci; - if ( dev_priv->is_pci && !dev->sg ) { - DRM_ERROR( "PCI GART memory not allocated!\n" ); + if (dev_priv->is_pci && !dev->sg) { + DRM_ERROR("PCI GART memory not allocated!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->usec_timeout = init->usec_timeout; - if ( dev_priv->usec_timeout < 1 || - dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) { - DRM_DEBUG( "TIMEOUT problem!\n" ); + if (dev_priv->usec_timeout < 1 || + dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { + DRM_DEBUG("TIMEOUT problem!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } - switch(init->func) { + switch (init->func) { case RADEON_INIT_R200_CP: - dev_priv->microcode_version=UCODE_R200; + dev_priv->microcode_version = UCODE_R200; break; case RADEON_INIT_R300_CP: - dev_priv->microcode_version=UCODE_R300; + dev_priv->microcode_version = UCODE_R300; break; default: - dev_priv->microcode_version=UCODE_R100; + dev_priv->microcode_version = UCODE_R100; } - + dev_priv->do_boxes = 0; dev_priv->cp_mode = init->cp_mode; @@ -1344,15 +1343,15 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) * but the ring can be in either AGP or PCI space for the ring * read pointer. */ - if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) && - ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) { - DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode ); + if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && + (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { + DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } - switch ( init->fb_bpp ) { + switch (init->fb_bpp) { case 16: dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; break; @@ -1361,12 +1360,12 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; break; } - dev_priv->front_offset = init->front_offset; - dev_priv->front_pitch = init->front_pitch; - dev_priv->back_offset = init->back_offset; - dev_priv->back_pitch = init->back_pitch; + dev_priv->front_offset = init->front_offset; + dev_priv->front_pitch = init->front_pitch; + dev_priv->back_offset = init->back_offset; + dev_priv->back_pitch = init->back_pitch; - switch ( init->depth_bpp ) { + switch (init->depth_bpp) { case 16: dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; break; @@ -1375,8 +1374,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; break; } - dev_priv->depth_offset = init->depth_offset; - dev_priv->depth_pitch = init->depth_pitch; + dev_priv->depth_offset = init->depth_offset; + dev_priv->depth_pitch = init->depth_pitch; /* Hardware state for depth clears. Remove this if/when we no * longer clear the depth buffer with a 3D rectangle. Hard-code @@ -1385,16 +1384,16 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) */ dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | (dev_priv->color_fmt << 10) | - (dev_priv->microcode_version == UCODE_R100 ? RADEON_ZBLOCK16 : 0)); + (dev_priv->microcode_version == + UCODE_R100 ? RADEON_ZBLOCK16 : 0)); - dev_priv->depth_clear.rb3d_zstencilcntl = - (dev_priv->depth_fmt | - RADEON_Z_TEST_ALWAYS | - RADEON_STENCIL_TEST_ALWAYS | - RADEON_STENCIL_S_FAIL_REPLACE | - RADEON_STENCIL_ZPASS_REPLACE | - RADEON_STENCIL_ZFAIL_REPLACE | - RADEON_Z_WRITE_ENABLE); + dev_priv->depth_clear.rb3d_zstencilcntl = + (dev_priv->depth_fmt | + RADEON_Z_TEST_ALWAYS | + RADEON_STENCIL_TEST_ALWAYS | + RADEON_STENCIL_S_FAIL_REPLACE | + RADEON_STENCIL_ZPASS_REPLACE | + RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | RADEON_BFACE_SOLID | @@ -1416,8 +1415,8 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) dev_priv->ring_rptr_offset = init->ring_rptr_offset; dev_priv->buffers_offset = init->buffers_offset; dev_priv->gart_textures_offset = init->gart_textures_offset; - - if(!dev_priv->sarea) { + + if (!dev_priv->sarea) { DRM_ERROR("could not find sarea!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); @@ -1425,21 +1424,21 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); - if(!dev_priv->mmio) { + if (!dev_priv->mmio) { DRM_ERROR("could not find mmio region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); - if(!dev_priv->cp_ring) { + if (!dev_priv->cp_ring) { DRM_ERROR("could not find cp ring region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); - if(!dev_priv->ring_rptr) { + if (!dev_priv->ring_rptr) { DRM_ERROR("could not find ring read pointer!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); @@ -1447,16 +1446,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } dev->agp_buffer_token = init->buffers_offset; dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); - if(!dev->agp_buffer_map) { + if (!dev->agp_buffer_map) { DRM_ERROR("could not find dma buffer region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } - if ( init->gart_textures_offset ) { - dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset); - if ( !dev_priv->gart_textures ) { + if (init->gart_textures_offset) { + dev_priv->gart_textures = + drm_core_findmap(dev, init->gart_textures_offset); + if (!dev_priv->gart_textures) { DRM_ERROR("could not find GART texture region!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); @@ -1465,17 +1465,17 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } dev_priv->sarea_priv = - (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle + + init->sarea_priv_offset); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - drm_core_ioremap( dev_priv->cp_ring, dev ); - drm_core_ioremap( dev_priv->ring_rptr, dev ); - drm_core_ioremap( dev->agp_buffer_map, dev ); - if(!dev_priv->cp_ring->handle || - !dev_priv->ring_rptr->handle || - !dev->agp_buffer_map->handle) { + if (!dev_priv->is_pci) { + drm_core_ioremap(dev_priv->cp_ring, dev); + drm_core_ioremap(dev_priv->ring_rptr, dev); + drm_core_ioremap(dev->agp_buffer_map, dev); + if (!dev_priv->cp_ring->handle || + !dev_priv->ring_rptr->handle || + !dev->agp_buffer_map->handle) { DRM_ERROR("could not find ioremap agp regions!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); @@ -1484,140 +1484,146 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) } else #endif { - dev_priv->cp_ring->handle = - (void *)dev_priv->cp_ring->offset; + dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset; dev_priv->ring_rptr->handle = - (void *)dev_priv->ring_rptr->offset; - dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset; - - DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", - dev_priv->cp_ring->handle ); - DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n", - dev_priv->ring_rptr->handle ); - DRM_DEBUG( "dev->agp_buffer_map->handle %p\n", - dev->agp_buffer_map->handle ); + (void *)dev_priv->ring_rptr->offset; + dev->agp_buffer_map->handle = + (void *)dev->agp_buffer_map->offset; + + DRM_DEBUG("dev_priv->cp_ring->handle %p\n", + dev_priv->cp_ring->handle); + DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", + dev_priv->ring_rptr->handle); + DRM_DEBUG("dev->agp_buffer_map->handle %p\n", + dev->agp_buffer_map->handle); } - dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION ) - & 0xffff ) << 16; + dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION) + & 0xffff) << 16; - dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) | - ( ( dev_priv->front_offset - + dev_priv->fb_location ) >> 10 ) ); + dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | + ((dev_priv->front_offset + + dev_priv->fb_location) >> 10)); - dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) | - ( ( dev_priv->back_offset - + dev_priv->fb_location ) >> 10 ) ); - - dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) | - ( ( dev_priv->depth_offset - + dev_priv->fb_location ) >> 10 ) ); + dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | + ((dev_priv->back_offset + + dev_priv->fb_location) >> 10)); + dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | + ((dev_priv->depth_offset + + dev_priv->fb_location) >> 10)); dev_priv->gart_size = init->gart_size; dev_priv->gart_vm_start = dev_priv->fb_location - + RADEON_READ( RADEON_CONFIG_APER_SIZE ); + + RADEON_READ(RADEON_CONFIG_APER_SIZE); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) + if (!dev_priv->is_pci) dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->agp->base - + dev_priv->gart_vm_start); + - dev->agp->base + + dev_priv->gart_vm_start); else #endif dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - - dev->sg->handle - + dev_priv->gart_vm_start); - - DRM_DEBUG( "dev_priv->gart_size %d\n", - dev_priv->gart_size ); - DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n", - dev_priv->gart_vm_start ); - DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n", - dev_priv->gart_buffers_offset ); - - dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle; - dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle + - dev->sg->handle + + dev_priv->gart_vm_start); + + DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); + DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); + DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", + dev_priv->gart_buffers_offset); + + dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; + dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle + init->ring_size / sizeof(u32)); dev_priv->ring.size = init->ring_size; - dev_priv->ring.size_l2qw = drm_order( init->ring_size / 8 ); + dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); - dev_priv->ring.tail_mask = - (dev_priv->ring.size / sizeof(u32)) - 1; + dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { + if (!dev_priv->is_pci) { /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); + radeon_set_pcigart(dev_priv, 0); } else #endif { /* if we have an offset set from userspace */ if (dev_priv->pcigart_offset) { - dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; - dev_priv->gart_info.addr = (unsigned long)drm_ioremap(dev_priv->gart_info.bus_addr, RADEON_PCIGART_TABLE_SIZE, dev); - - dev_priv->gart_info.is_pcie = !!(dev_priv->flags & CHIP_IS_PCIE); - dev_priv->gart_info.gart_table_location = DRM_ATI_GART_FB; - - DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", dev_priv->gart_info.addr, dev_priv->pcigart_offset); - } - else { - dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; - dev_priv->gart_info.addr = dev_priv->gart_info.bus_addr= 0; - if (dev_priv->flags & CHIP_IS_PCIE) - { - DRM_ERROR("Cannot use PCI Express without GART in FB memory\n"); + dev_priv->gart_info.bus_addr = + dev_priv->pcigart_offset + dev_priv->fb_location; + dev_priv->gart_info.addr = + (unsigned long)drm_ioremap(dev_priv->gart_info. + bus_addr, + RADEON_PCIGART_TABLE_SIZE, + dev); + + dev_priv->gart_info.is_pcie = + !!(dev_priv->flags & CHIP_IS_PCIE); + dev_priv->gart_info.gart_table_location = + DRM_ATI_GART_FB; + + DRM_DEBUG("Setting phys_pci_gart to %08lX %08lX\n", + dev_priv->gart_info.addr, + dev_priv->pcigart_offset); + } else { + dev_priv->gart_info.gart_table_location = + DRM_ATI_GART_MAIN; + dev_priv->gart_info.addr = + dev_priv->gart_info.bus_addr = 0; + if (dev_priv->flags & CHIP_IS_PCIE) { + DRM_ERROR + ("Cannot use PCI Express without GART in FB memory\n"); radeon_do_cleanup_cp(dev); return DRM_ERR(EINVAL); } } if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { - DRM_ERROR( "failed to init PCI GART!\n" ); + DRM_ERROR("failed to init PCI GART!\n"); dev->dev_private = (void *)dev_priv; radeon_do_cleanup_cp(dev); return DRM_ERR(ENOMEM); } /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); + radeon_set_pcigart(dev_priv, 1); } - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); + radeon_cp_load_microcode(dev_priv); + radeon_cp_init_ring_buffer(dev, dev_priv); dev_priv->last_buf = 0; dev->dev_private = (void *)dev_priv; - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); return 0; } -static int radeon_do_cleanup_cp( drm_device_t *dev ) +static int radeon_do_cleanup_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Make sure interrupts are disabled here because the uninstall ioctl * may not have been called from userspace and after dev_private * is freed, it's too late. */ - if ( dev->irq_enabled ) drm_irq_uninstall(dev); + if (dev->irq_enabled) + drm_irq_uninstall(dev); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { - if ( dev_priv->cp_ring != NULL ) - drm_core_ioremapfree( dev_priv->cp_ring, dev ); - if ( dev_priv->ring_rptr != NULL ) - drm_core_ioremapfree( dev_priv->ring_rptr, dev ); - if ( dev->agp_buffer_map != NULL ) - { - drm_core_ioremapfree( dev->agp_buffer_map, dev ); + if (!dev_priv->is_pci) { + if (dev_priv->cp_ring != NULL) + drm_core_ioremapfree(dev_priv->cp_ring, dev); + if (dev_priv->ring_rptr != NULL) + drm_core_ioremapfree(dev_priv->ring_rptr, dev); + if (dev->agp_buffer_map != NULL) { + drm_core_ioremapfree(dev->agp_buffer_map, dev); dev->agp_buffer_map = NULL; } } else @@ -1626,103 +1632,103 @@ static int radeon_do_cleanup_cp( drm_device_t *dev ) if (dev_priv->gart_info.bus_addr) if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) DRM_ERROR("failed to cleanup PCI GART!\n"); - - if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) - { - drm_ioremapfree((void *)dev_priv->gart_info.addr, RADEON_PCIGART_TABLE_SIZE, dev); + + if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { + drm_ioremapfree((void *)dev_priv->gart_info.addr, + RADEON_PCIGART_TABLE_SIZE, dev); dev_priv->gart_info.addr = 0; } } - + /* only clear to the start of flags */ memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); return 0; } -/* This code will reinit the Radeon CP hardware after a resume from disc. - * AFAIK, it would be very difficult to pickle the state at suspend time, so +/* This code will reinit the Radeon CP hardware after a resume from disc. + * AFAIK, it would be very difficult to pickle the state at suspend time, so * here we make sure that all Radeon hardware initialisation is re-done without * affecting running applications. * * Charl P. Botha */ -static int radeon_do_resume_cp( drm_device_t *dev ) +static int radeon_do_resume_cp(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - if ( !dev_priv ) { - DRM_ERROR( "Called with no initialization\n" ); - return DRM_ERR( EINVAL ); + if (!dev_priv) { + DRM_ERROR("Called with no initialization\n"); + return DRM_ERR(EINVAL); } DRM_DEBUG("Starting radeon_do_resume_cp()\n"); #if __OS_HAS_AGP - if ( !dev_priv->is_pci ) { + if (!dev_priv->is_pci) { /* Turn off PCI GART */ - radeon_set_pcigart( dev_priv, 0 ); + radeon_set_pcigart(dev_priv, 0); } else #endif { /* Turn on PCI GART */ - radeon_set_pcigart( dev_priv, 1 ); + radeon_set_pcigart(dev_priv, 1); } - radeon_cp_load_microcode( dev_priv ); - radeon_cp_init_ring_buffer( dev, dev_priv ); + radeon_cp_load_microcode(dev_priv); + radeon_cp_init_ring_buffer(dev, dev_priv); - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); DRM_DEBUG("radeon_do_resume_cp() complete\n"); return 0; } - -int radeon_cp_init( DRM_IOCTL_ARGS ) +int radeon_cp_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_init_t init; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) ); + DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data, + sizeof(init)); - if(init.func == RADEON_INIT_R300_CP) + if (init.func == RADEON_INIT_R300_CP) r300_init_reg_flags(); - switch ( init.func ) { + switch (init.func) { case RADEON_INIT_CP: case RADEON_INIT_R200_CP: case RADEON_INIT_R300_CP: - return radeon_do_init_cp( dev, &init ); + return radeon_do_init_cp(dev, &init); case RADEON_CLEANUP_CP: - return radeon_do_cleanup_cp( dev ); + return radeon_do_cleanup_cp(dev); } return DRM_ERR(EINVAL); } -int radeon_cp_start( DRM_IOCTL_ARGS ) +int radeon_cp_start(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( dev_priv->cp_running ) { - DRM_DEBUG( "%s while CP running\n", __FUNCTION__ ); + if (dev_priv->cp_running) { + DRM_DEBUG("%s while CP running\n", __FUNCTION__); return 0; } - if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) { - DRM_DEBUG( "%s called with bogus CP mode (%d)\n", - __FUNCTION__, dev_priv->cp_mode ); + if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { + DRM_DEBUG("%s called with bogus CP mode (%d)\n", + __FUNCTION__, dev_priv->cp_mode); return 0; } - radeon_do_cp_start( dev_priv ); + radeon_do_cp_start(dev_priv); return 0; } @@ -1730,17 +1736,18 @@ int radeon_cp_start( DRM_IOCTL_ARGS ) /* Stop the CP. The engine must have been idled before calling this * routine. */ -int radeon_cp_stop( DRM_IOCTL_ARGS ) +int radeon_cp_stop(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_cp_stop_t stop; int ret; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) ); + DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data, + sizeof(stop)); if (!dev_priv->cp_running) return 0; @@ -1748,32 +1755,32 @@ int radeon_cp_stop( DRM_IOCTL_ARGS ) /* Flush any pending CP commands. This ensures any outstanding * commands are exectuted by the engine before we turn it off. */ - if ( stop.flush ) { - radeon_do_cp_flush( dev_priv ); + if (stop.flush) { + radeon_do_cp_flush(dev_priv); } /* If we fail to make the engine go idle, we return an error * code so that the DRM ioctl wrapper can try again. */ - if ( stop.idle ) { - ret = radeon_do_cp_idle( dev_priv ); - if ( ret ) return ret; + if (stop.idle) { + ret = radeon_do_cp_idle(dev_priv); + if (ret) + return ret; } /* Finally, we can turn off the CP. If the engine isn't idle, * we will get some dropped triangles as they won't be fully * rendered before the CP is shut down. */ - radeon_do_cp_stop( dev_priv ); + radeon_do_cp_stop(dev_priv); /* Reset the engine */ - radeon_do_engine_reset( dev ); + radeon_do_engine_reset(dev); return 0; } - -void radeon_do_release( drm_device_t *dev ) +void radeon_do_release(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; int i, ret; @@ -1781,7 +1788,7 @@ void radeon_do_release( drm_device_t *dev ) if (dev_priv) { if (dev_priv->cp_running) { /* Stop the cp */ - while ((ret = radeon_do_cp_idle( dev_priv )) != 0) { + while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { DRM_DEBUG("radeon_do_cp_idle %d\n", ret); #ifdef __linux__ schedule(); @@ -1789,47 +1796,49 @@ void radeon_do_release( drm_device_t *dev ) tsleep(&ret, PZERO, "rdnrel", 1); #endif } - radeon_do_cp_stop( dev_priv ); - radeon_do_engine_reset( dev ); + radeon_do_cp_stop(dev_priv); + radeon_do_engine_reset(dev); } /* Disable *all* interrupts */ if (dev_priv->mmio) /* remove this after permanent addmaps */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); - if (dev_priv->mmio) {/* remove all surfaces */ + if (dev_priv->mmio) { /* remove all surfaces */ for (i = 0; i < RADEON_MAX_SURFACES; i++) { - RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0); - RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0); - RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0); + RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); + RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + + 16 * i, 0); + RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + + 16 * i, 0); } } /* Free memory heap structures */ - radeon_mem_takedown( &(dev_priv->gart_heap) ); - radeon_mem_takedown( &(dev_priv->fb_heap) ); + radeon_mem_takedown(&(dev_priv->gart_heap)); + radeon_mem_takedown(&(dev_priv->fb_heap)); /* deallocate kernel resources */ - radeon_do_cleanup_cp( dev ); + radeon_do_cleanup_cp(dev); } } /* Just reset the CP ring. Called as part of an X Server engine reset. */ -int radeon_cp_reset( DRM_IOCTL_ARGS ) +int radeon_cp_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_DEBUG( "%s called before init done\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_DEBUG("%s called before init done\n", __FUNCTION__); return DRM_ERR(EINVAL); } - radeon_do_cp_reset( dev_priv ); + radeon_do_cp_reset(dev_priv); /* The CP is no longer running after an engine reset */ dev_priv->cp_running = 0; @@ -1837,50 +1846,47 @@ int radeon_cp_reset( DRM_IOCTL_ARGS ) return 0; } -int radeon_cp_idle( DRM_IOCTL_ARGS ) +int radeon_cp_idle(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return radeon_do_cp_idle( dev_priv ); + return radeon_do_cp_idle(dev_priv); } /* Added by Charl P. Botha to call radeon_do_resume_cp(). */ -int radeon_cp_resume( DRM_IOCTL_ARGS ) +int radeon_cp_resume(DRM_IOCTL_ARGS) { DRM_DEVICE; return radeon_do_resume_cp(dev); } - -int radeon_engine_reset( DRM_IOCTL_ARGS ) +int radeon_engine_reset(DRM_IOCTL_ARGS) { DRM_DEVICE; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - return radeon_do_engine_reset( dev ); + return radeon_do_engine_reset(dev); } - /* ================================================================ * Fullscreen mode */ /* KW: Deprecated to say the least: */ -int radeon_fullscreen( DRM_IOCTL_ARGS ) +int radeon_fullscreen(DRM_IOCTL_ARGS) { return 0; } - /* ================================================================ * Freelist management */ @@ -1889,20 +1895,20 @@ int radeon_fullscreen( DRM_IOCTL_ARGS ) * bufs until freelist code is used. Note this hides a problem with * the scratch register * (used to keep track of last buffer * completed) being written to before * the last buffer has actually - * completed rendering. + * completed rendering. * * KW: It's also a good way to find free buffers quickly. * * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't * sleep. However, bugs in older versions of radeon_accel.c mean that * we essentially have to do this, else old clients will break. - * + * * However, it does leave open a potential deadlock where all the * buffers are held by other clients, which can't release them because - * they can't get the lock. + * they can't get the lock. */ -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1911,19 +1917,19 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) int i, t; int start; - if ( ++dev_priv->last_buf >= dma->buf_count ) + if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; - for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { - u32 done_age = GET_SCRATCH( 1 ); - DRM_DEBUG("done_age = %d\n",done_age); - for ( i = start ; i < dma->buf_count ; i++ ) { + for (t = 0; t < dev_priv->usec_timeout; t++) { + u32 done_age = GET_SCRATCH(1); + DRM_DEBUG("done_age = %d\n", done_age); + for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { + if (buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -1932,16 +1938,17 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) } if (t) { - DRM_UDELAY( 1 ); + DRM_UDELAY(1); dev_priv->stats.freelist_loops++; } } - DRM_DEBUG( "returning NULL!\n" ); + DRM_DEBUG("returning NULL!\n"); return NULL; } + #if 0 -drm_buf_t *radeon_freelist_get( drm_device_t *dev ) +drm_buf_t *radeon_freelist_get(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -1951,18 +1958,18 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) int start; u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)); - if ( ++dev_priv->last_buf >= dma->buf_count ) + if (++dev_priv->last_buf >= dma->buf_count) dev_priv->last_buf = 0; start = dev_priv->last_buf; dev_priv->stats.freelist_loops++; - - for ( t = 0 ; t < 2 ; t++ ) { - for ( i = start ; i < dma->buf_count ; i++ ) { + + for (t = 0; t < 2; t++) { + for (i = start; i < dma->buf_count; i++) { buf = dma->buflist[i]; buf_priv = buf->dev_private; - if ( buf->filp == 0 || (buf->pending && - buf_priv->age <= done_age) ) { + if (buf->filp == 0 || (buf->pending && + buf_priv->age <= done_age)) { dev_priv->stats.requested_bufs++; buf->pending = 0; return buf; @@ -1975,73 +1982,74 @@ drm_buf_t *radeon_freelist_get( drm_device_t *dev ) } #endif -void radeon_freelist_reset( drm_device_t *dev ) +void radeon_freelist_reset(drm_device_t * dev) { drm_device_dma_t *dma = dev->dma; drm_radeon_private_t *dev_priv = dev->dev_private; int i; dev_priv->last_buf = 0; - for ( i = 0 ; i < dma->buf_count ; i++ ) { + for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; buf_priv->age = 0; } } - /* ================================================================ * CP command submission */ -int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ) +int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) { drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i; - u32 last_head = GET_RING_HEAD( dev_priv ); + u32 last_head = GET_RING_HEAD(dev_priv); - for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { - u32 head = GET_RING_HEAD( dev_priv ); + for (i = 0; i < dev_priv->usec_timeout; i++) { + u32 head = GET_RING_HEAD(dev_priv); ring->space = (head - ring->tail) * sizeof(u32); - if ( ring->space <= 0 ) + if (ring->space <= 0) ring->space += ring->size; - if ( ring->space > n ) + if (ring->space > n) return 0; - + dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; if (head != last_head) i = 0; last_head = head; - DRM_UDELAY( 1 ); + DRM_UDELAY(1); } /* FIXME: This return value is ignored in the BEGIN_RING macro! */ #if RADEON_FIFO_DEBUG - radeon_status( dev_priv ); - DRM_ERROR( "failed!\n" ); + radeon_status(dev_priv); + DRM_ERROR("failed!\n"); #endif return DRM_ERR(EBUSY); } -static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d ) +static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev, + drm_dma_t * d) { int i; drm_buf_t *buf; - for ( i = d->granted_count ; i < d->request_count ; i++ ) { - buf = radeon_freelist_get( dev ); - if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */ + for (i = d->granted_count; i < d->request_count; i++) { + buf = radeon_freelist_get(dev); + if (!buf) + return DRM_ERR(EBUSY); /* NOTE: broken client */ buf->filp = filp; - if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx, - sizeof(buf->idx) ) ) + if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, + sizeof(buf->idx))) return DRM_ERR(EFAULT); - if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total, - sizeof(buf->total) ) ) + if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, + sizeof(buf->total))) return DRM_ERR(EFAULT); d->granted_count++; @@ -2049,7 +2057,7 @@ static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d return 0; } -int radeon_cp_buffers( DRM_IOCTL_ARGS ) +int radeon_cp_buffers(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_device_dma_t *dma = dev->dma; @@ -2057,33 +2065,33 @@ int radeon_cp_buffers( DRM_IOCTL_ARGS ) drm_dma_t __user *argp = (void __user *)data; drm_dma_t d; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) ); + DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); /* Please don't send us buffers. */ - if ( d.send_count != 0 ) { - DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", - DRM_CURRENTPID, d.send_count ); + if (d.send_count != 0) { + DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", + DRM_CURRENTPID, d.send_count); return DRM_ERR(EINVAL); } /* We'll send you buffers. */ - if ( d.request_count < 0 || d.request_count > dma->buf_count ) { - DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", - DRM_CURRENTPID, d.request_count, dma->buf_count ); + if (d.request_count < 0 || d.request_count > dma->buf_count) { + DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", + DRM_CURRENTPID, d.request_count, dma->buf_count); return DRM_ERR(EINVAL); } d.granted_count = 0; - if ( d.request_count ) { - ret = radeon_cp_get_buffers( filp, dev, &d ); + if (d.request_count) { + ret = radeon_cp_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) ); + DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); return ret; } @@ -2110,13 +2118,13 @@ int radeon_driver_preinit(struct drm_device *dev, unsigned long flags) dev_priv->flags |= CHIP_HAS_HIERZ; break; default: - /* all other chips have no hierarchical z buffer */ + /* all other chips have no hierarchical z buffer */ break; } if (drm_device_is_agp(dev)) dev_priv->flags |= CHIP_IS_AGP; - + if (drm_device_is_pcie(dev)) dev_priv->flags |= CHIP_IS_PCIE; diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h index dd526617fae..1cd81a671a3 100644 --- a/drivers/char/drm/radeon_drm.h +++ b/drivers/char/drm/radeon_drm.h @@ -57,78 +57,77 @@ #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 -#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ #define RADEON_REQUIRE_QUIESCENCE 0x00010000 -#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ +#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ #define RADEON_UPLOAD_ALL 0x003effff #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff - /* New style per-packet identifiers for use in cmd_buffer ioctl with * the RADEON_EMIT_PACKET command. Comments relate new packets to old * state bits and the packet size: */ -#define RADEON_EMIT_PP_MISC 0 /* context/7 */ -#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ -#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ -#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ -#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ -#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ -#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ -#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ -#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ -#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ -#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ -#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ -#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ -#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ -#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ -#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ -#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ -#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ -#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ -#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ -#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ -#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ -#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ -#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ -#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ -#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ -#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ -#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ -#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ -#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ -#define R200_EMIT_VAP_CTL 32 /* vap/1 */ -#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ -#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ -#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ -#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ -#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ -#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ -#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ -#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ -#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ -#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ -#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ -#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ -#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ -#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ -#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ -#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ -#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ -#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ -#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ -#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ -#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ -#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ -#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ -#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ -#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ -#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ -#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ +#define RADEON_EMIT_PP_MISC 0 /* context/7 */ +#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ +#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ +#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ +#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ +#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ +#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ +#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ +#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ +#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ +#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ +#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ +#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ +#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ +#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ +#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ +#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ +#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ +#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ +#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ +#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ +#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ +#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ +#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ +#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ +#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ +#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ +#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ +#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ +#define R200_EMIT_VAP_CTL 32 /* vap/1 */ +#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ +#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ +#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ +#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ +#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ +#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ +#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ +#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ +#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ +#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ +#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ +#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ +#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ +#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ +#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ +#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ +#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ +#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ +#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ +#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ +#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ +#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ +#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ +#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ +#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ +#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ #define R200_EMIT_PP_CUBIC_FACES_0 61 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 #define R200_EMIT_PP_CUBIC_FACES_1 63 @@ -167,37 +166,36 @@ /* Commands understood by cmd_buffer ioctl. More can be added but * obviously these can't be removed or changed: */ -#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ -#define RADEON_CMD_SCALARS 2 /* emit scalar data */ -#define RADEON_CMD_VECTORS 3 /* emit vector data */ -#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ -#define RADEON_CMD_PACKET3 5 /* emit hw packet */ -#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ -#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ -#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: - * doesn't make the cpu wait, just - * the graphics hardware */ - +#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ +#define RADEON_CMD_SCALARS 2 /* emit scalar data */ +#define RADEON_CMD_VECTORS 3 /* emit vector data */ +#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ +#define RADEON_CMD_PACKET3 5 /* emit hw packet */ +#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ +#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ +#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: + * doesn't make the cpu wait, just + * the graphics hardware */ typedef union { int i; - struct { + struct { unsigned char cmd_type, pad0, pad1, pad2; } header; - struct { + struct { unsigned char cmd_type, packet_id, pad0, pad1; } packet; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } scalars; - struct { - unsigned char cmd_type, offset, stride, count; + struct { + unsigned char cmd_type, offset, stride, count; } vectors; - struct { - unsigned char cmd_type, buf_idx, pad0, pad1; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; } dma; - struct { - unsigned char cmd_type, flags, pad0, pad1; + struct { + unsigned char cmd_type, flags, pad0, pad1; } wait; } drm_radeon_cmd_header_t; @@ -213,10 +211,10 @@ typedef union { * The interface has not been stabilized, so some of these may be removed * and eventually reordered before stabilization. */ -#define R300_CMD_PACKET0 1 -#define R300_CMD_VPU 2 /* emit vertex program upload */ -#define R300_CMD_PACKET3 3 /* emit a packet3 */ -#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ +#define R300_CMD_PACKET0 1 +#define R300_CMD_VPU 2 /* emit vertex program upload */ +#define R300_CMD_PACKET3 3 /* emit a packet3 */ +#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ #define R300_CMD_CP_DELAY 5 #define R300_CMD_DMA_DISCARD 6 #define R300_CMD_WAIT 7 @@ -241,13 +239,13 @@ typedef union { } packet3; struct { unsigned char cmd_type, packet; - unsigned short count; /* amount of packet2 to emit */ + unsigned short count; /* amount of packet2 to emit */ } delay; struct { unsigned char cmd_type, buf_idx, pad0, pad1; } dma; struct { - unsigned char cmd_type, flags, pad0, pad1; + unsigned char cmd_type, flags, pad0, pad1; } wait; } drm_r300_cmd_header_t; @@ -301,7 +299,7 @@ typedef union { #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) -#endif /* __RADEON_SAREA_DEFINES__ */ +#endif /* __RADEON_SAREA_DEFINES__ */ typedef struct { unsigned int red; @@ -312,7 +310,7 @@ typedef struct { typedef struct { /* Context state */ - unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_misc; /* 0x1c14 */ unsigned int pp_fog_color; unsigned int re_solid_color; unsigned int rb3d_blendcntl; @@ -320,7 +318,7 @@ typedef struct { unsigned int rb3d_depthpitch; unsigned int rb3d_zstencilcntl; - unsigned int pp_cntl; /* 0x1c38 */ + unsigned int pp_cntl; /* 0x1c38 */ unsigned int rb3d_cntl; unsigned int rb3d_coloroffset; unsigned int re_width_height; @@ -328,27 +326,27 @@ typedef struct { unsigned int se_cntl; /* Vertex format state */ - unsigned int se_coord_fmt; /* 0x1c50 */ + unsigned int se_coord_fmt; /* 0x1c50 */ /* Line state */ - unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_pattern; /* 0x1cd0 */ unsigned int re_line_state; - unsigned int se_line_width; /* 0x1db8 */ + unsigned int se_line_width; /* 0x1db8 */ /* Bumpmap state */ - unsigned int pp_lum_matrix; /* 0x1d00 */ + unsigned int pp_lum_matrix; /* 0x1d00 */ - unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_0; /* 0x1d58 */ unsigned int pp_rot_matrix_1; /* Mask state */ - unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ unsigned int rb3d_ropcntl; unsigned int rb3d_planemask; /* Viewport state */ - unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xscale; /* 0x1d98 */ unsigned int se_vport_xoffset; unsigned int se_vport_yscale; unsigned int se_vport_yoffset; @@ -356,20 +354,19 @@ typedef struct { unsigned int se_vport_zoffset; /* Setup state */ - unsigned int se_cntl_status; /* 0x2140 */ + unsigned int se_cntl_status; /* 0x2140 */ /* Misc state */ - unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_top_left; /* 0x26c0 */ unsigned int re_misc; } drm_radeon_context_regs_t; typedef struct { /* Zbias state */ - unsigned int se_zbias_factor; /* 0x1dac */ + unsigned int se_zbias_factor; /* 0x1dac */ unsigned int se_zbias_constant; } drm_radeon_context2_regs_t; - /* Setup registers for each texture unit */ typedef struct { @@ -387,11 +384,10 @@ typedef struct { unsigned int finish; unsigned int prim:8; unsigned int stateidx:8; - unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ - unsigned int vc_format; /* vertex format */ + unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ + unsigned int vc_format; /* vertex format */ } drm_radeon_prim_t; - typedef struct { drm_radeon_context_regs_t context; drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; @@ -399,7 +395,6 @@ typedef struct { unsigned int dirty; } drm_radeon_state_t; - typedef struct { /* The channel for communication of state information to the * kernel on firing a vertex buffer with either of the @@ -422,16 +417,16 @@ typedef struct { unsigned int last_dispatch; unsigned int last_clear; - drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; + drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + + 1]; unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; - int pfState; /* number of 3d windows (0,1,2ormore) */ - int pfCurrentPage; /* which buffer is being displayed? */ - int crtc2_base; /* CRTC2 frame offset */ + int pfState; /* number of 3d windows (0,1,2ormore) */ + int pfCurrentPage; /* which buffer is being displayed? */ + int crtc2_base; /* CRTC2 frame offset */ int tiling_enabled; /* set by drm, read by 2d + 3d clients */ } drm_radeon_sarea_t; - /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) * @@ -441,15 +436,15 @@ typedef struct { /* Radeon specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ -#define DRM_RADEON_CP_INIT 0x00 -#define DRM_RADEON_CP_START 0x01 +#define DRM_RADEON_CP_INIT 0x00 +#define DRM_RADEON_CP_START 0x01 #define DRM_RADEON_CP_STOP 0x02 #define DRM_RADEON_CP_RESET 0x03 #define DRM_RADEON_CP_IDLE 0x04 -#define DRM_RADEON_RESET 0x05 +#define DRM_RADEON_RESET 0x05 #define DRM_RADEON_FULLSCREEN 0x06 -#define DRM_RADEON_SWAP 0x07 -#define DRM_RADEON_CLEAR 0x08 +#define DRM_RADEON_SWAP 0x07 +#define DRM_RADEON_CLEAR 0x08 #define DRM_RADEON_VERTEX 0x09 #define DRM_RADEON_INDICES 0x0A #define DRM_RADEON_NOT_USED @@ -500,7 +495,7 @@ typedef struct { typedef struct drm_radeon_init { enum { - RADEON_INIT_CP = 0x01, + RADEON_INIT_CP = 0x01, RADEON_CLEANUP_CP = 0x02, RADEON_INIT_R200_CP = 0x03, RADEON_INIT_R300_CP = 0x04 @@ -533,7 +528,7 @@ typedef struct drm_radeon_cp_stop { typedef struct drm_radeon_fullscreen { enum { - RADEON_INIT_FULLSCREEN = 0x01, + RADEON_INIT_FULLSCREEN = 0x01, RADEON_CLEANUP_FULLSCREEN = 0x02 } func; } drm_radeon_fullscreen_t; @@ -554,15 +549,15 @@ typedef struct drm_radeon_clear { unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ + unsigned int depth_mask; /* misnamed field: should be stencil */ drm_radeon_clear_rect_t __user *depth_boxes; } drm_radeon_clear_t; typedef struct drm_radeon_vertex { int prim; - int idx; /* Index of vertex buffer */ - int count; /* Number of vertices in buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ } drm_radeon_vertex_t; typedef struct drm_radeon_indices { @@ -570,7 +565,7 @@ typedef struct drm_radeon_indices { int idx; int start; int end; - int discard; /* Client finished with buffer? */ + int discard; /* Client finished with buffer? */ } drm_radeon_indices_t; /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices @@ -578,8 +573,8 @@ typedef struct drm_radeon_indices { * - supports driver change to emit native primitives */ typedef struct drm_radeon_vertex2 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ int nr_states; drm_radeon_state_t __user *state; int nr_prims; @@ -587,10 +582,10 @@ typedef struct drm_radeon_vertex2 { } drm_radeon_vertex2_t; /* v1.3 - obsoletes drm_radeon_vertex2 - * - allows arbitarily large cliprect list + * - allows arbitarily large cliprect list * - allows updating of tcl packet, vector and scalar state * - allows memory-efficient description of state updates - * - allows state to be emitted without a primitive + * - allows state to be emitted without a primitive * (for clears, ctx switches) * - allows more than one dma buffer to be referenced per ioctl * - supports tcl driver @@ -604,7 +599,7 @@ typedef struct drm_radeon_cmd_buffer { } drm_radeon_cmd_buffer_t; typedef struct drm_radeon_tex_image { - unsigned int x, y; /* Blit coordinates */ + unsigned int x, y; /* Blit coordinates */ unsigned int width, height; const void __user *data; } drm_radeon_tex_image_t; @@ -613,7 +608,7 @@ typedef struct drm_radeon_texture { unsigned int offset; int pitch; int format; - int width; /* Texture image coordinates */ + int width; /* Texture image coordinates */ int height; drm_radeon_tex_image_t __user *image; } drm_radeon_texture_t; @@ -629,19 +624,18 @@ typedef struct drm_radeon_indirect { int discard; } drm_radeon_indirect_t; - /* 1.3: An ioctl to get parameters that aren't available to the 3d - * client any other way. + * client any other way. */ -#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ +#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ #define RADEON_PARAM_LAST_FRAME 2 #define RADEON_PARAM_LAST_DISPATCH 3 #define RADEON_PARAM_LAST_CLEAR 4 /* Added with DRM version 1.6. */ #define RADEON_PARAM_IRQ_NR 5 -#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ +#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ /* Added with DRM version 1.8. */ -#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ #define RADEON_PARAM_STATUS_HANDLE 8 #define RADEON_PARAM_SAREA_HANDLE 9 #define RADEON_PARAM_GART_TEX_HANDLE 10 @@ -672,10 +666,9 @@ typedef struct drm_radeon_mem_free { typedef struct drm_radeon_mem_init_heap { int region; int size; - int start; + int start; } drm_radeon_mem_init_heap_t; - /* 1.6: Userspace can request & wait on irq's: */ typedef struct drm_radeon_irq_emit { @@ -686,19 +679,18 @@ typedef struct drm_radeon_irq_wait { int irq_seq; } drm_radeon_irq_wait_t; - /* 1.10: Clients tell the DRM where they think the framebuffer is located in * the card's address space, via a new generic ioctl to set parameters */ typedef struct drm_radeon_setparam { unsigned int param; - int64_t value; + int64_t value; } drm_radeon_setparam_t; #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ -#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ +#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ /* 1.14: Clients can allocate/free a surface */ diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c index e0682f64b40..6c1766120c1 100644 --- a/drivers/char/drm/radeon_drv.c +++ b/drivers/char/drm/radeon_drv.c @@ -29,7 +29,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ - #include #include "drmP.h" #include "drm.h" @@ -38,30 +37,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -73,7 +70,10 @@ extern drm_ioctl_desc_t radeon_ioctls[]; extern int radeon_max_ioctl; static struct drm_driver driver = { - .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL, + .driver_features = + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | + DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | + DRIVER_IRQ_VBL, .dev_priv_size = sizeof(drm_radeon_buf_priv_t), .preinit = radeon_driver_preinit, .presetup = radeon_presetup, @@ -95,21 +95,22 @@ static struct drm_driver driver = { .ioctls = radeon_ioctls, .dma_ioctl = radeon_cp_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, #ifdef CONFIG_COMPAT - .compat_ioctl = radeon_compat_ioctl, + .compat_ioctl = radeon_compat_ioctl, #endif - }, + } + , .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init radeon_init(void) @@ -126,6 +127,6 @@ static void __exit radeon_exit(void) module_init(radeon_init); module_exit(radeon_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 9c10141845e..e36076981d1 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -68,7 +68,7 @@ * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. * Add texture rectangle support for r100. * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which - * clients use to tell the DRM where they think the framebuffer is + * clients use to tell the DRM where they think the framebuffer is * located in the card's address space * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color * and GL_EXT_blend_[func|equation]_separate on r200 @@ -134,15 +134,15 @@ enum radeon_chip_flags { CHIP_IS_IGP = 0x00020000UL, CHIP_SINGLE_CRTC = 0x00040000UL, CHIP_IS_AGP = 0x00080000UL, - CHIP_HAS_HIERZ = 0x00100000UL, + CHIP_HAS_HIERZ = 0x00100000UL, CHIP_IS_PCIE = 0x00200000UL, }; typedef struct drm_radeon_freelist { - unsigned int age; - drm_buf_t *buf; - struct drm_radeon_freelist *next; - struct drm_radeon_freelist *prev; + unsigned int age; + drm_buf_t *buf; + struct drm_radeon_freelist *next; + struct drm_radeon_freelist *prev; } drm_radeon_freelist_t; typedef struct drm_radeon_ring_buffer { @@ -204,8 +204,8 @@ typedef struct drm_radeon_private { int cp_mode; int cp_running; - drm_radeon_freelist_t *head; - drm_radeon_freelist_t *tail; + drm_radeon_freelist_t *head; + drm_radeon_freelist_t *tail; int last_buf; volatile u32 *scratch; int writeback_works; @@ -246,7 +246,7 @@ typedef struct drm_radeon_private { u32 depth_pitch_offset; drm_radeon_depth_clear_t depth_clear; - + unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; @@ -264,14 +264,14 @@ typedef struct drm_radeon_private { struct mem_block *fb_heap; /* SW interrupt */ - wait_queue_head_t swi_queue; - atomic_t swi_emitted; + wait_queue_head_t swi_queue; + atomic_t swi_emitted; struct radeon_surface surfaces[RADEON_MAX_SURFACES]; - struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; + struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; - unsigned long pcigart_offset; - drm_ati_pcigart_info gart_info; + unsigned long pcigart_offset; + drm_ati_pcigart_info gart_info; /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ @@ -282,62 +282,64 @@ typedef struct drm_radeon_buf_priv { } drm_radeon_buf_priv_t; /* radeon_cp.c */ -extern int radeon_cp_init( DRM_IOCTL_ARGS ); -extern int radeon_cp_start( DRM_IOCTL_ARGS ); -extern int radeon_cp_stop( DRM_IOCTL_ARGS ); -extern int radeon_cp_reset( DRM_IOCTL_ARGS ); -extern int radeon_cp_idle( DRM_IOCTL_ARGS ); -extern int radeon_cp_resume( DRM_IOCTL_ARGS ); -extern int radeon_engine_reset( DRM_IOCTL_ARGS ); -extern int radeon_fullscreen( DRM_IOCTL_ARGS ); -extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); +extern int radeon_cp_init(DRM_IOCTL_ARGS); +extern int radeon_cp_start(DRM_IOCTL_ARGS); +extern int radeon_cp_stop(DRM_IOCTL_ARGS); +extern int radeon_cp_reset(DRM_IOCTL_ARGS); +extern int radeon_cp_idle(DRM_IOCTL_ARGS); +extern int radeon_cp_resume(DRM_IOCTL_ARGS); +extern int radeon_engine_reset(DRM_IOCTL_ARGS); +extern int radeon_fullscreen(DRM_IOCTL_ARGS); +extern int radeon_cp_buffers(DRM_IOCTL_ARGS); -extern void radeon_freelist_reset( drm_device_t *dev ); -extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); +extern void radeon_freelist_reset(drm_device_t * dev); +extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); -extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); +extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); -extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv ); +extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); extern int radeon_presetup(struct drm_device *dev); extern int radeon_driver_postcleanup(struct drm_device *dev); -extern int radeon_mem_alloc( DRM_IOCTL_ARGS ); -extern int radeon_mem_free( DRM_IOCTL_ARGS ); -extern int radeon_mem_init_heap( DRM_IOCTL_ARGS ); -extern void radeon_mem_takedown( struct mem_block **heap ); -extern void radeon_mem_release( DRMFILE filp, struct mem_block *heap ); +extern int radeon_mem_alloc(DRM_IOCTL_ARGS); +extern int radeon_mem_free(DRM_IOCTL_ARGS); +extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); +extern void radeon_mem_takedown(struct mem_block **heap); +extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); /* radeon_irq.c */ -extern int radeon_irq_emit( DRM_IOCTL_ARGS ); -extern int radeon_irq_wait( DRM_IOCTL_ARGS ); - -extern void radeon_do_release(drm_device_t *dev); -extern int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence); -extern irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ); -extern void radeon_driver_irq_preinstall( drm_device_t *dev ); -extern void radeon_driver_irq_postinstall( drm_device_t *dev ); -extern void radeon_driver_irq_uninstall( drm_device_t *dev ); -extern void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp); -extern void radeon_driver_pretakedown(drm_device_t *dev); -extern int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv); -extern void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv); - -extern int radeon_preinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postinit( struct drm_device *dev, unsigned long flags ); -extern int radeon_postcleanup( struct drm_device *dev ); +extern int radeon_irq_emit(DRM_IOCTL_ARGS); +extern int radeon_irq_wait(DRM_IOCTL_ARGS); + +extern void radeon_do_release(drm_device_t * dev); +extern int radeon_driver_vblank_wait(drm_device_t * dev, + unsigned int *sequence); +extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); +extern void radeon_driver_irq_preinstall(drm_device_t * dev); +extern void radeon_driver_irq_postinstall(drm_device_t * dev); +extern void radeon_driver_irq_uninstall(drm_device_t * dev); +extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp); +extern void radeon_driver_pretakedown(drm_device_t * dev); +extern int radeon_driver_open_helper(drm_device_t * dev, + drm_file_t * filp_priv); +extern void radeon_driver_free_filp_priv(drm_device_t * dev, + drm_file_t * filp_priv); + +extern int radeon_preinit(struct drm_device *dev, unsigned long flags); +extern int radeon_postinit(struct drm_device *dev, unsigned long flags); +extern int radeon_postcleanup(struct drm_device *dev); extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); - /* r300_cmdbuf.c */ extern void r300_init_reg_flags(void); -extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, - drm_file_t* filp_priv, - drm_radeon_cmd_buffer_t* cmdbuf); +extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * cmdbuf); /* Flags for stats.boxes */ @@ -347,8 +349,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define RADEON_BOX_WAIT_IDLE 0x8 #define RADEON_BOX_TEXTURE_LOAD 0x10 - - /* Register definitions, register access macros and drmAddMap constants * for Radeon kernel driver. */ @@ -442,7 +442,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) - #define RADEON_GEN_INT_CNTL 0x0040 # define RADEON_CRTC_VBLANK_MASK (1 << 0) # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) @@ -650,7 +649,6 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) - /* CP registers */ #define RADEON_CP_ME_RAM_ADDR 0x07d4 #define RADEON_CP_ME_RAM_RADDR 0x07d8 @@ -698,7 +696,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, # define RADEON_CP_NEXT_CHAR 0x00001900 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 # define RADEON_CP_SET_SCISSORS 0x00001E00 - /* GEN_INDX_PRIM is unsupported starting with R300 */ + /* GEN_INDX_PRIM is unsupported starting with R300 */ # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 # define RADEON_WAIT_FOR_IDLE 0x00002600 # define RADEON_3D_DRAW_VBUF 0x00002800 @@ -782,19 +780,19 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define R200_PP_TXCBLEND_5 0x2f50 #define R200_PP_TXCBLEND_6 0x2f60 #define R200_PP_TXCBLEND_7 0x2f70 -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 +#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 #define R200_PP_TFACTOR_0 0x2ee0 #define R200_SE_VTX_FMT_0 0x2088 #define R200_SE_VAP_CNTL 0x2080 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_0 0x2c00 +#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 +#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 +#define R200_PP_TXFILTER_5 0x2ca0 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_0 0x2c00 #define R200_PP_TXOFFSET_5 0x2d78 #define R200_PP_TXOFFSET_4 0x2d60 #define R200_PP_TXOFFSET_3 0x2d48 @@ -848,13 +846,13 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define R200_RE_SCISSOR_TL_0 0x1cd8 #define R200_RE_SCISSOR_TL_1 0x1ce0 #define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 +#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 #define R200_SE_VTX_STATE_CNTL 0x2180 #define R200_RE_POINTSIZE 0x2648 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ #define RADEON_PP_TEX_SIZE_1 0x1d0c #define RADEON_PP_TEX_SIZE_2 0x1d14 @@ -875,7 +873,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b #define R200_3D_DRAW_IMMD_2 0xC0003500 #define R200_SE_VTX_FMT_1 0x208c -#define R200_RE_CNTL 0x1c50 +#define R200_RE_CNTL 0x1c50 #define R200_RB3D_BLENDCOLOR 0x3218 @@ -884,7 +882,7 @@ extern int r300_do_cp_cmdbuf(drm_device_t* dev, DRMFILE filp, #define R200_PP_TRI_PERF 0x2cf8 #define R200_PP_AFS_0 0x2f80 -#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ +#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ /* Constants */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ @@ -932,7 +930,6 @@ do { \ #define CP_PACKET3( pkt, n ) \ (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) - /* ================================================================ * Engine control helper macros */ @@ -981,12 +978,11 @@ do { \ OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ } while (0) - /* ================================================================ * Misc helper macros */ -/* Perfbox functionality only. +/* Perfbox functionality only. */ #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ do { \ @@ -1023,7 +1019,6 @@ do { \ OUT_RING( age ); \ } while (0) - /* ================================================================ * Ring control */ @@ -1084,7 +1079,6 @@ do { \ OUT_RING( val ); \ } while (0) - #define OUT_RING_TABLE( tab, sz ) do { \ int _size = (sz); \ int *_tab = (int *)(tab); \ @@ -1109,5 +1103,4 @@ do { \ write &= mask; \ } while (0) - -#endif /* __RADEON_DRV_H__ */ +#endif /* __RADEON_DRV_H__ */ diff --git a/drivers/char/drm/radeon_ioc32.c b/drivers/char/drm/radeon_ioc32.c index bfe612215fb..fef4a2b84c1 100644 --- a/drivers/char/drm/radeon_ioc32.c +++ b/drivers/char/drm/radeon_ioc32.c @@ -94,7 +94,7 @@ static int compat_radeon_cp_init(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_CP_INIT, (unsigned long) init); + DRM_IOCTL_RADEON_CP_INIT, (unsigned long)init); } typedef struct drm_radeon_clear32 { @@ -102,8 +102,8 @@ typedef struct drm_radeon_clear32 { unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; - unsigned int depth_mask; /* misnamed field: should be stencil */ - u32 depth_boxes; + unsigned int depth_mask; /* misnamed field: should be stencil */ + u32 depth_boxes; } drm_radeon_clear32_t; static int compat_radeon_cp_clear(struct file *file, unsigned int cmd, @@ -127,7 +127,7 @@ static int compat_radeon_cp_clear(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_CLEAR, (unsigned long) clr); + DRM_IOCTL_RADEON_CLEAR, (unsigned long)clr); } typedef struct drm_radeon_stipple32 { @@ -137,7 +137,7 @@ typedef struct drm_radeon_stipple32 { static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd, unsigned long arg) { - drm_radeon_stipple32_t __user *argp = (void __user *) arg; + drm_radeon_stipple32_t __user *argp = (void __user *)arg; drm_radeon_stipple_t __user *request; u32 mask; @@ -146,16 +146,16 @@ static int compat_radeon_cp_stipple(struct file *file, unsigned int cmd, request = compat_alloc_user_space(sizeof(*request)); if (!access_ok(VERIFY_WRITE, request, sizeof(*request)) - || __put_user((unsigned int __user *)(unsigned long) mask, + || __put_user((unsigned int __user *)(unsigned long)mask, &request->mask)) return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_STIPPLE, (unsigned long) request); + DRM_IOCTL_RADEON_STIPPLE, (unsigned long)request); } typedef struct drm_radeon_tex_image32 { - unsigned int x, y; /* Blit coordinates */ + unsigned int x, y; /* Blit coordinates */ unsigned int width, height; u32 data; } drm_radeon_tex_image32_t; @@ -164,7 +164,7 @@ typedef struct drm_radeon_texture32 { unsigned int offset; int pitch; int format; - int width; /* Texture image coordinates */ + int width; /* Texture image coordinates */ int height; u32 image; } drm_radeon_texture32_t; @@ -177,7 +177,7 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd, drm_radeon_tex_image32_t img32; drm_radeon_tex_image_t __user *image; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; if (req32.image == 0) return -EINVAL; @@ -206,12 +206,12 @@ static int compat_radeon_cp_texture(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_TEXTURE, (unsigned long) request); + DRM_IOCTL_RADEON_TEXTURE, (unsigned long)request); } typedef struct drm_radeon_vertex2_32 { - int idx; /* Index of vertex buffer */ - int discard; /* Client finished with buffer? */ + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ int nr_states; u32 state; int nr_prims; @@ -224,7 +224,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd, drm_radeon_vertex2_32_t req32; drm_radeon_vertex2_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -240,7 +240,7 @@ static int compat_radeon_cp_vertex2(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_VERTEX2, (unsigned long) request); + DRM_IOCTL_RADEON_VERTEX2, (unsigned long)request); } typedef struct drm_radeon_cmd_buffer32 { @@ -256,7 +256,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd, drm_radeon_cmd_buffer32_t req32; drm_radeon_cmd_buffer_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -270,7 +270,7 @@ static int compat_radeon_cp_cmdbuf(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_CMDBUF, (unsigned long) request); + DRM_IOCTL_RADEON_CMDBUF, (unsigned long)request); } typedef struct drm_radeon_getparam32 { @@ -284,7 +284,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd, drm_radeon_getparam32_t req32; drm_radeon_getparam_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -295,7 +295,7 @@ static int compat_radeon_cp_getparam(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_GETPARAM, (unsigned long) request); + DRM_IOCTL_RADEON_GETPARAM, (unsigned long)request); } typedef struct drm_radeon_mem_alloc32 { @@ -311,7 +311,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd, drm_radeon_mem_alloc32_t req32; drm_radeon_mem_alloc_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -324,7 +324,7 @@ static int compat_radeon_mem_alloc(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_ALLOC, (unsigned long) request); + DRM_IOCTL_RADEON_ALLOC, (unsigned long)request); } typedef struct drm_radeon_irq_emit32 { @@ -337,7 +337,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd, drm_radeon_irq_emit32_t req32; drm_radeon_irq_emit_t __user *request; - if (copy_from_user(&req32, (void __user *) arg, sizeof(req32))) + if (copy_from_user(&req32, (void __user *)arg, sizeof(req32))) return -EFAULT; request = compat_alloc_user_space(sizeof(*request)); @@ -347,7 +347,7 @@ static int compat_radeon_irq_emit(struct file *file, unsigned int cmd, return -EFAULT; return drm_ioctl(file->f_dentry->d_inode, file, - DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long) request); + DRM_IOCTL_RADEON_IRQ_EMIT, (unsigned long)request); } drm_ioctl_compat_t *radeon_compat_ioctls[] = { @@ -371,8 +371,7 @@ drm_ioctl_compat_t *radeon_compat_ioctls[] = { * \param arg user argument. * \return zero on success or negative number on failure. */ -long radeon_compat_ioctl(struct file *filp, unsigned int cmd, - unsigned long arg) +long radeon_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { unsigned int nr = DRM_IOCTL_NR(cmd); drm_ioctl_compat_t *fn = NULL; @@ -386,7 +385,7 @@ long radeon_compat_ioctl(struct file *filp, unsigned int cmd, lock_kernel(); /* XXX for now */ if (fn != NULL) - ret = (*fn)(filp, cmd, arg); + ret = (*fn) (filp, cmd, arg); else ret = drm_ioctl(filp->f_dentry->d_inode, filp, cmd, arg); unlock_kernel(); diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c index 40474a65f56..d60519de887 100644 --- a/drivers/char/drm/radeon_irq.c +++ b/drivers/char/drm/radeon_irq.c @@ -1,7 +1,7 @@ /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,7 +35,8 @@ #include "radeon_drm.h" #include "radeon_drv.h" -static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask) +static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, + u32 mask) { u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask; if (irqs) @@ -61,37 +62,37 @@ static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u3 * tied to dma at all, this is just a hangover from dri prehistory. */ -irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS ) +irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS) { drm_device_t *dev = (drm_device_t *) arg; - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; - u32 stat; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; + u32 stat; /* Only consider the bits we're interested in - others could be used * outside the DRM */ - stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | + stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT)); if (!stat) return IRQ_NONE; /* SW interrupt */ if (stat & RADEON_SW_INT_TEST) { - DRM_WAKEUP( &dev_priv->swi_queue ); + DRM_WAKEUP(&dev_priv->swi_queue); } /* VBLANK interrupt */ if (stat & RADEON_CRTC_VBLANK_STAT) { atomic_inc(&dev->vbl_received); DRM_WAKEUP(&dev->vbl_queue); - drm_vbl_send_signals( dev ); + drm_vbl_send_signals(dev); } return IRQ_HANDLED; } -static int radeon_emit_irq(drm_device_t *dev) +static int radeon_emit_irq(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int ret; @@ -100,42 +101,41 @@ static int radeon_emit_irq(drm_device_t *dev) atomic_inc(&dev_priv->swi_emitted); ret = atomic_read(&dev_priv->swi_emitted); - BEGIN_RING( 4 ); - OUT_RING_REG( RADEON_LAST_SWI_REG, ret ); - OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE ); - ADVANCE_RING(); - COMMIT_RING(); + BEGIN_RING(4); + OUT_RING_REG(RADEON_LAST_SWI_REG, ret); + OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE); + ADVANCE_RING(); + COMMIT_RING(); return ret; } - -static int radeon_wait_irq(drm_device_t *dev, int swi_nr) +static int radeon_wait_irq(drm_device_t * dev, int swi_nr) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; int ret = 0; - if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr) - return 0; + if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr) + return 0; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; - DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ, - RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr ); + DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ, + RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr); return ret; } -int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) +int radeon_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) { - drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + drm_radeon_private_t *dev_priv = + (drm_radeon_private_t *) dev->dev_private; unsigned int cur_vblank; int ret = 0; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } @@ -145,101 +145,100 @@ int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence) /* Assume that the user has missed the current sequence number * by about a day rather than she wants to wait for years - * using vertical blanks... + * using vertical blanks... */ - DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ, - ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) ) - - *sequence ) <= (1<<23) ) ); + DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, + (((cur_vblank = atomic_read(&dev->vbl_received)) + - *sequence) <= (1 << 23))); *sequence = cur_vblank; return ret; } - /* Needs the lock as it touches the ring. */ -int radeon_irq_emit( DRM_IOCTL_ARGS ) +int radeon_irq_emit(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_emit_t emit; int result; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data, - sizeof(emit) ); + DRM_COPY_FROM_USER_IOCTL(emit, (drm_radeon_irq_emit_t __user *) data, + sizeof(emit)); - result = radeon_emit_irq( dev ); + result = radeon_emit_irq(dev); - if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } return 0; } - /* Doesn't need the hardware lock. */ -int radeon_irq_wait( DRM_IOCTL_ARGS ) +int radeon_irq_wait(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_irq_wait_t irqwait; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data, - sizeof(irqwait) ); + DRM_COPY_FROM_USER_IOCTL(irqwait, (drm_radeon_irq_wait_t __user *) data, + sizeof(irqwait)); - return radeon_wait_irq( dev, irqwait.irq_seq ); + return radeon_wait_irq(dev, irqwait.irq_seq); } - /* drm_dma.h hooks */ -void radeon_driver_irq_preinstall( drm_device_t *dev ) { +void radeon_driver_irq_preinstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; - /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + /* Disable *all* interrupts */ + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); /* Clear bits if they're already high */ radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT)); } -void radeon_driver_irq_postinstall( drm_device_t *dev ) { +void radeon_driver_irq_postinstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; - atomic_set(&dev_priv->swi_emitted, 0); - DRM_INIT_WAITQUEUE( &dev_priv->swi_queue ); + atomic_set(&dev_priv->swi_emitted, 0); + DRM_INIT_WAITQUEUE(&dev_priv->swi_queue); /* Turn on SW and VBL ints */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, - RADEON_CRTC_VBLANK_MASK | - RADEON_SW_INT_ENABLE ); + RADEON_WRITE(RADEON_GEN_INT_CNTL, + RADEON_CRTC_VBLANK_MASK | RADEON_SW_INT_ENABLE); } -void radeon_driver_irq_uninstall( drm_device_t *dev ) { +void radeon_driver_irq_uninstall(drm_device_t * dev) +{ drm_radeon_private_t *dev_priv = - (drm_radeon_private_t *)dev->dev_private; + (drm_radeon_private_t *) dev->dev_private; if (!dev_priv) return; /* Disable *all* interrupts */ - RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 ); + RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); } diff --git a/drivers/char/drm/radeon_mem.c b/drivers/char/drm/radeon_mem.c index 134f894e6e4..030a6fad0d8 100644 --- a/drivers/char/drm/radeon_mem.c +++ b/drivers/char/drm/radeon_mem.c @@ -1,7 +1,7 @@ /* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- * * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - * + * * The Weather Channel (TM) funded Tungsten Graphics to develop the * initial release of the Radeon 8500 driver under the XFree86 license. * This notice must be preserved. @@ -35,16 +35,17 @@ #include "radeon_drv.h" /* Very simple allocator for GART memory, working on a static range - * already mapped into each client's address space. + * already mapped into each client's address space. */ static struct mem_block *split_block(struct mem_block *p, int start, int size, - DRMFILE filp ) + DRMFILE filp) { /* Maybe cut off the start of an existing block */ if (start > p->start) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); - if (!newblock) + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); + if (!newblock) goto out; newblock->start = start; newblock->size = p->size - (start - p->start); @@ -56,10 +57,11 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, p->size -= newblock->size; p = newblock; } - + /* Maybe cut off the end of an existing block */ if (size < p->size) { - struct mem_block *newblock = drm_alloc(sizeof(*newblock), DRM_MEM_BUFS ); + struct mem_block *newblock = + drm_alloc(sizeof(*newblock), DRM_MEM_BUFS); if (!newblock) goto out; newblock->start = start + size; @@ -72,40 +74,39 @@ static struct mem_block *split_block(struct mem_block *p, int start, int size, p->size = size; } - out: + out: /* Our block is in the middle */ p->filp = filp; return p; } -static struct mem_block *alloc_block( struct mem_block *heap, int size, - int align2, DRMFILE filp ) +static struct mem_block *alloc_block(struct mem_block *heap, int size, + int align2, DRMFILE filp) { struct mem_block *p; - int mask = (1 << align2)-1; + int mask = (1 << align2) - 1; list_for_each(p, heap) { int start = (p->start + mask) & ~mask; if (p->filp == 0 && start + size <= p->start + p->size) - return split_block( p, start, size, filp ); + return split_block(p, start, size, filp); } return NULL; } -static struct mem_block *find_block( struct mem_block *heap, int start ) +static struct mem_block *find_block(struct mem_block *heap, int start) { struct mem_block *p; list_for_each(p, heap) - if (p->start == start) - return p; + if (p->start == start) + return p; return NULL; } - -static void free_block( struct mem_block *p ) +static void free_block(struct mem_block *p) { p->filp = NULL; @@ -117,7 +118,7 @@ static void free_block( struct mem_block *p ) p->size += q->size; p->next = q->next; p->next->prev = p; - drm_free(q, sizeof(*q), DRM_MEM_BUFS ); + drm_free(q, sizeof(*q), DRM_MEM_BUFS); } if (p->prev->filp == 0) { @@ -125,7 +126,7 @@ static void free_block( struct mem_block *p ) q->size += p->size; q->next = p->next; q->next->prev = q; - drm_free(p, sizeof(*q), DRM_MEM_BUFS ); + drm_free(p, sizeof(*q), DRM_MEM_BUFS); } } @@ -133,14 +134,14 @@ static void free_block( struct mem_block *p ) */ static int init_heap(struct mem_block **heap, int start, int size) { - struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS ); + struct mem_block *blocks = drm_alloc(sizeof(*blocks), DRM_MEM_BUFS); - if (!blocks) + if (!blocks) return DRM_ERR(ENOMEM); - - *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS ); + + *heap = drm_alloc(sizeof(**heap), DRM_MEM_BUFS); if (!*heap) { - drm_free( blocks, sizeof(*blocks), DRM_MEM_BUFS ); + drm_free(blocks, sizeof(*blocks), DRM_MEM_BUFS); return DRM_ERR(ENOMEM); } @@ -149,16 +150,15 @@ static int init_heap(struct mem_block **heap, int start, int size) blocks->filp = NULL; blocks->next = blocks->prev = *heap; - memset( *heap, 0, sizeof(**heap) ); - (*heap)->filp = (DRMFILE) -1; + memset(*heap, 0, sizeof(**heap)); + (*heap)->filp = (DRMFILE) - 1; (*heap)->next = (*heap)->prev = blocks; return 0; } - /* Free all blocks associated with the releasing file. */ -void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) +void radeon_mem_release(DRMFILE filp, struct mem_block *heap) { struct mem_block *p; @@ -166,7 +166,7 @@ void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) return; list_for_each(p, heap) { - if (p->filp == filp) + if (p->filp == filp) p->filp = NULL; } @@ -179,40 +179,37 @@ void radeon_mem_release( DRMFILE filp, struct mem_block *heap ) p->size += q->size; p->next = q->next; p->next->prev = p; - drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } } } /* Shutdown. */ -void radeon_mem_takedown( struct mem_block **heap ) +void radeon_mem_takedown(struct mem_block **heap) { struct mem_block *p; - + if (!*heap) return; - for (p = (*heap)->next ; p != *heap ; ) { + for (p = (*heap)->next; p != *heap;) { struct mem_block *q = p; p = p->next; - drm_free(q, sizeof(*q),DRM_MEM_DRIVER); + drm_free(q, sizeof(*q), DRM_MEM_DRIVER); } - drm_free( *heap, sizeof(**heap),DRM_MEM_DRIVER ); + drm_free(*heap, sizeof(**heap), DRM_MEM_DRIVER); *heap = NULL; } - - /* IOCTL HANDLERS */ -static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, - int region ) +static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region) { - switch( region ) { + switch (region) { case RADEON_MEM_REGION_GART: - return &dev_priv->gart_heap; + return &dev_priv->gart_heap; case RADEON_MEM_REGION_FB: return &dev_priv->fb_heap; default: @@ -220,103 +217,98 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv, } } -int radeon_mem_alloc( DRM_IOCTL_ARGS ) +int radeon_mem_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_alloc_t alloc; struct mem_block *block, **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( alloc, (drm_radeon_mem_alloc_t __user *)data, - sizeof(alloc) ); + DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_mem_alloc_t __user *) data, + sizeof(alloc)); - heap = get_heap( dev_priv, alloc.region ); + heap = get_heap(dev_priv, alloc.region); if (!heap || !*heap) return DRM_ERR(EFAULT); - + /* Make things easier on ourselves: all allocations at least * 4k aligned. */ if (alloc.alignment < 12) alloc.alignment = 12; - block = alloc_block( *heap, alloc.size, alloc.alignment, - filp ); + block = alloc_block(*heap, alloc.size, alloc.alignment, filp); - if (!block) + if (!block) return DRM_ERR(ENOMEM); - if ( DRM_COPY_TO_USER( alloc.region_offset, &block->start, - sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(alloc.region_offset, &block->start, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } - - -int radeon_mem_free( DRM_IOCTL_ARGS ) +int radeon_mem_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_free_t memfree; struct mem_block *block, **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( memfree, (drm_radeon_mem_free_t __user *)data, - sizeof(memfree) ); + DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data, + sizeof(memfree)); - heap = get_heap( dev_priv, memfree.region ); + heap = get_heap(dev_priv, memfree.region); if (!heap || !*heap) return DRM_ERR(EFAULT); - - block = find_block( *heap, memfree.region_offset ); + + block = find_block(*heap, memfree.region_offset); if (!block) return DRM_ERR(EFAULT); if (block->filp != filp) return DRM_ERR(EPERM); - free_block( block ); + free_block(block); return 0; } -int radeon_mem_init_heap( DRM_IOCTL_ARGS ) +int radeon_mem_init_heap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_mem_init_heap_t initheap; struct mem_block **heap; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( initheap, (drm_radeon_mem_init_heap_t __user *)data, - sizeof(initheap) ); + DRM_COPY_FROM_USER_IOCTL(initheap, + (drm_radeon_mem_init_heap_t __user *) data, + sizeof(initheap)); - heap = get_heap( dev_priv, initheap.region ); - if (!heap) + heap = get_heap(dev_priv, initheap.region); + if (!heap) return DRM_ERR(EFAULT); - + if (*heap) { DRM_ERROR("heap already initialized?"); return DRM_ERR(EFAULT); } - - return init_heap( heap, initheap.start, initheap.size ); -} - + return init_heap(heap, initheap.start, initheap.size); +} diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 74c2fe8033c..42e8ce4dbe9 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -37,51 +37,58 @@ * Helper functions for client state checking and fixup */ -static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - u32 *offset ) { +static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + u32 * offset) +{ u32 off = *offset; struct drm_radeon_driver_file_fields *radeon_priv; - if ( off >= dev_priv->fb_location && - off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) + if (off >= dev_priv->fb_location && + off < (dev_priv->gart_vm_start + dev_priv->gart_size)) return 0; radeon_priv = filp_priv->driver_priv; off += radeon_priv->radeon_fb_delta; - DRM_DEBUG( "offset fixed up to 0x%x\n", off ); + DRM_DEBUG("offset fixed up to 0x%x\n", off); - if ( off < dev_priv->fb_location || - off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) ) - return DRM_ERR( EINVAL ); + if (off < dev_priv->fb_location || + off >= (dev_priv->gart_vm_start + dev_priv->gart_size)) + return DRM_ERR(EINVAL); *offset = off; return 0; } -static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - int id, - u32 __user *data ) { - switch ( id ) { +static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + int id, u32 __user * data) +{ + switch (id) { case RADEON_EMIT_PP_MISC: - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &data[( RADEON_RB3D_DEPTHOFFSET - - RADEON_PP_MISC ) / 4] ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &data[(RADEON_RB3D_DEPTHOFFSET + - + RADEON_PP_MISC) / + 4])) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } break; case RADEON_EMIT_PP_CNTL: - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &data[( RADEON_RB3D_COLOROFFSET - - RADEON_PP_CNTL ) / 4] ) ) { - DRM_ERROR( "Invalid colour buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &data[(RADEON_RB3D_COLOROFFSET + - + RADEON_PP_CNTL) / + 4])) { + DRM_ERROR("Invalid colour buffer offset\n"); + return DRM_ERR(EINVAL); } break; @@ -91,21 +98,23 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case R200_EMIT_PP_TXOFFSET_3: case R200_EMIT_PP_TXOFFSET_4: case R200_EMIT_PP_TXOFFSET_5: - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &data[0] ) ) { - DRM_ERROR( "Invalid R200 texture offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &data[0])) { + DRM_ERROR("Invalid R200 texture offset\n"); + return DRM_ERR(EINVAL); } break; case RADEON_EMIT_PP_TXFILTER_0: case RADEON_EMIT_PP_TXFILTER_1: case RADEON_EMIT_PP_TXFILTER_2: - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &data[( RADEON_PP_TXOFFSET_0 - - RADEON_PP_TXFILTER_0 ) / 4] ) ) { - DRM_ERROR( "Invalid R100 texture offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &data[(RADEON_PP_TXOFFSET_0 + - + RADEON_PP_TXFILTER_0) / + 4])) { + DRM_ERROR("Invalid R100 texture offset\n"); + return DRM_ERR(EINVAL); } break; @@ -114,17 +123,18 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ case R200_EMIT_PP_CUBIC_OFFSETS_2: case R200_EMIT_PP_CUBIC_OFFSETS_3: case R200_EMIT_PP_CUBIC_OFFSETS_4: - case R200_EMIT_PP_CUBIC_OFFSETS_5: { - int i; - for ( i = 0; i < 5; i++ ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &data[i] ) ) { - DRM_ERROR( "Invalid R200 cubic texture offset\n" ); - return DRM_ERR( EINVAL ); + case R200_EMIT_PP_CUBIC_OFFSETS_5:{ + int i; + for (i = 0; i < 5; i++) { + if (radeon_check_and_fixup_offset + (dev_priv, filp_priv, &data[i])) { + DRM_ERROR + ("Invalid R200 cubic texture offset\n"); + return DRM_ERR(EINVAL); + } } + break; } - break; - } case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: @@ -220,243 +230,247 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_ break; default: - DRM_ERROR( "Unknown state packet ID %d\n", id ); - return DRM_ERR( EINVAL ); + DRM_ERROR("Unknown state packet ID %d\n", id); + return DRM_ERR(EINVAL); } return 0; } -static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - unsigned int *cmdsz ) { +static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * + dev_priv, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * + cmdbuf, + unsigned int *cmdsz) +{ u32 *cmd = (u32 *) cmdbuf->buf; - *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 ); + *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); - if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) { - DRM_ERROR( "Not a type 3 packet\n" ); - return DRM_ERR( EINVAL ); + if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { + DRM_ERROR("Not a type 3 packet\n"); + return DRM_ERR(EINVAL); } - if ( 4 * *cmdsz > cmdbuf->bufsz ) { - DRM_ERROR( "Packet size larger than size of data provided\n" ); - return DRM_ERR( EINVAL ); + if (4 * *cmdsz > cmdbuf->bufsz) { + DRM_ERROR("Packet size larger than size of data provided\n"); + return DRM_ERR(EINVAL); } /* Check client state and fix it up if necessary */ - if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */ + if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */ u32 offset; - if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL - | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL + | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = cmd[2] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid first packet offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset + (dev_priv, filp_priv, &offset)) { + DRM_ERROR("Invalid first packet offset\n"); + return DRM_ERR(EINVAL); } - cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10; + cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; } - if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) && - ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) { + if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && + (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { offset = cmd[3] << 10; - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) { - DRM_ERROR( "Invalid second packet offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset + (dev_priv, filp_priv, &offset)) { + DRM_ERROR("Invalid second packet offset\n"); + return DRM_ERR(EINVAL); } - cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10; + cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; } } return 0; } - /* ================================================================ * CP hardware state programming functions */ -static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv, - drm_clip_rect_t *box ) +static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, + drm_clip_rect_t * box) { RING_LOCALS; - DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n", - box->x1, box->y1, box->x2, box->y2 ); + DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", + box->x1, box->y1, box->x2, box->y2); - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) ); - OUT_RING( (box->y1 << 16) | box->x1 ); - OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) ); - OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) ); + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); + OUT_RING((box->y1 << 16) | box->x1); + OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); + OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); ADVANCE_RING(); } /* Emit 1.1 state */ -static int radeon_emit_state( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_context_regs_t *ctx, - drm_radeon_texture_regs_t *tex, - unsigned int dirty ) +static int radeon_emit_state(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_context_regs_t * ctx, + drm_radeon_texture_regs_t * tex, + unsigned int dirty) { RING_LOCALS; - DRM_DEBUG( "dirty=0x%08x\n", dirty ); + DRM_DEBUG("dirty=0x%08x\n", dirty); - if ( dirty & RADEON_UPLOAD_CONTEXT ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_depthoffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_CONTEXT) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &ctx->rb3d_depthoffset)) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &ctx->rb3d_coloroffset ) ) { - DRM_ERROR( "Invalid depth buffer offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &ctx->rb3d_coloroffset)) { + DRM_ERROR("Invalid depth buffer offset\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) ); - OUT_RING( ctx->pp_misc ); - OUT_RING( ctx->pp_fog_color ); - OUT_RING( ctx->re_solid_color ); - OUT_RING( ctx->rb3d_blendcntl ); - OUT_RING( ctx->rb3d_depthoffset ); - OUT_RING( ctx->rb3d_depthpitch ); - OUT_RING( ctx->rb3d_zstencilcntl ); - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) ); - OUT_RING( ctx->pp_cntl ); - OUT_RING( ctx->rb3d_cntl ); - OUT_RING( ctx->rb3d_coloroffset ); - OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) ); - OUT_RING( ctx->rb3d_colorpitch ); + BEGIN_RING(14); + OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); + OUT_RING(ctx->pp_misc); + OUT_RING(ctx->pp_fog_color); + OUT_RING(ctx->re_solid_color); + OUT_RING(ctx->rb3d_blendcntl); + OUT_RING(ctx->rb3d_depthoffset); + OUT_RING(ctx->rb3d_depthpitch); + OUT_RING(ctx->rb3d_zstencilcntl); + OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); + OUT_RING(ctx->pp_cntl); + OUT_RING(ctx->rb3d_cntl); + OUT_RING(ctx->rb3d_coloroffset); + OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); + OUT_RING(ctx->rb3d_colorpitch); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_VERTFMT ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) ); - OUT_RING( ctx->se_coord_fmt ); + if (dirty & RADEON_UPLOAD_VERTFMT) { + BEGIN_RING(2); + OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); + OUT_RING(ctx->se_coord_fmt); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_LINE ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) ); - OUT_RING( ctx->re_line_pattern ); - OUT_RING( ctx->re_line_state ); - OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) ); - OUT_RING( ctx->se_line_width ); + if (dirty & RADEON_UPLOAD_LINE) { + BEGIN_RING(5); + OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); + OUT_RING(ctx->re_line_pattern); + OUT_RING(ctx->re_line_state); + OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); + OUT_RING(ctx->se_line_width); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_BUMPMAP ) { - BEGIN_RING( 5 ); - OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) ); - OUT_RING( ctx->pp_lum_matrix ); - OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) ); - OUT_RING( ctx->pp_rot_matrix_0 ); - OUT_RING( ctx->pp_rot_matrix_1 ); + if (dirty & RADEON_UPLOAD_BUMPMAP) { + BEGIN_RING(5); + OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); + OUT_RING(ctx->pp_lum_matrix); + OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); + OUT_RING(ctx->pp_rot_matrix_0); + OUT_RING(ctx->pp_rot_matrix_1); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_MASKS ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) ); - OUT_RING( ctx->rb3d_stencilrefmask ); - OUT_RING( ctx->rb3d_ropcntl ); - OUT_RING( ctx->rb3d_planemask ); + if (dirty & RADEON_UPLOAD_MASKS) { + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); + OUT_RING(ctx->rb3d_stencilrefmask); + OUT_RING(ctx->rb3d_ropcntl); + OUT_RING(ctx->rb3d_planemask); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_VIEWPORT ) { - BEGIN_RING( 7 ); - OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) ); - OUT_RING( ctx->se_vport_xscale ); - OUT_RING( ctx->se_vport_xoffset ); - OUT_RING( ctx->se_vport_yscale ); - OUT_RING( ctx->se_vport_yoffset ); - OUT_RING( ctx->se_vport_zscale ); - OUT_RING( ctx->se_vport_zoffset ); + if (dirty & RADEON_UPLOAD_VIEWPORT) { + BEGIN_RING(7); + OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); + OUT_RING(ctx->se_vport_xscale); + OUT_RING(ctx->se_vport_xoffset); + OUT_RING(ctx->se_vport_yscale); + OUT_RING(ctx->se_vport_yoffset); + OUT_RING(ctx->se_vport_zscale); + OUT_RING(ctx->se_vport_zoffset); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_SETUP ) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) ); - OUT_RING( ctx->se_cntl ); - OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) ); - OUT_RING( ctx->se_cntl_status ); + if (dirty & RADEON_UPLOAD_SETUP) { + BEGIN_RING(4); + OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); + OUT_RING(ctx->se_cntl); + OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); + OUT_RING(ctx->se_cntl_status); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_MISC ) { - BEGIN_RING( 2 ); - OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) ); - OUT_RING( ctx->re_misc ); + if (dirty & RADEON_UPLOAD_MISC) { + BEGIN_RING(2); + OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); + OUT_RING(ctx->re_misc); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX0 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[0].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 0\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX0) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[0].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 0\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) ); - OUT_RING( tex[0].pp_txfilter ); - OUT_RING( tex[0].pp_txformat ); - OUT_RING( tex[0].pp_txoffset ); - OUT_RING( tex[0].pp_txcblend ); - OUT_RING( tex[0].pp_txablend ); - OUT_RING( tex[0].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) ); - OUT_RING( tex[0].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); + OUT_RING(tex[0].pp_txfilter); + OUT_RING(tex[0].pp_txformat); + OUT_RING(tex[0].pp_txoffset); + OUT_RING(tex[0].pp_txcblend); + OUT_RING(tex[0].pp_txablend); + OUT_RING(tex[0].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); + OUT_RING(tex[0].pp_border_color); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX1 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[1].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 1\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX1) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[1].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 1\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) ); - OUT_RING( tex[1].pp_txfilter ); - OUT_RING( tex[1].pp_txformat ); - OUT_RING( tex[1].pp_txoffset ); - OUT_RING( tex[1].pp_txcblend ); - OUT_RING( tex[1].pp_txablend ); - OUT_RING( tex[1].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) ); - OUT_RING( tex[1].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); + OUT_RING(tex[1].pp_txfilter); + OUT_RING(tex[1].pp_txformat); + OUT_RING(tex[1].pp_txoffset); + OUT_RING(tex[1].pp_txcblend); + OUT_RING(tex[1].pp_txablend); + OUT_RING(tex[1].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); + OUT_RING(tex[1].pp_border_color); ADVANCE_RING(); } - if ( dirty & RADEON_UPLOAD_TEX2 ) { - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, - &tex[2].pp_txoffset ) ) { - DRM_ERROR( "Invalid texture offset for unit 2\n" ); - return DRM_ERR( EINVAL ); + if (dirty & RADEON_UPLOAD_TEX2) { + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, + &tex[2].pp_txoffset)) { + DRM_ERROR("Invalid texture offset for unit 2\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING( 9 ); - OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) ); - OUT_RING( tex[2].pp_txfilter ); - OUT_RING( tex[2].pp_txformat ); - OUT_RING( tex[2].pp_txoffset ); - OUT_RING( tex[2].pp_txcblend ); - OUT_RING( tex[2].pp_txablend ); - OUT_RING( tex[2].pp_tfactor ); - OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) ); - OUT_RING( tex[2].pp_border_color ); + BEGIN_RING(9); + OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); + OUT_RING(tex[2].pp_txfilter); + OUT_RING(tex[2].pp_txformat); + OUT_RING(tex[2].pp_txoffset); + OUT_RING(tex[2].pp_txcblend); + OUT_RING(tex[2].pp_txablend); + OUT_RING(tex[2].pp_tfactor); + OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); + OUT_RING(tex[2].pp_border_color); ADVANCE_RING(); } @@ -465,138 +479,137 @@ static int radeon_emit_state( drm_radeon_private_t *dev_priv, /* Emit 1.2 state */ -static int radeon_emit_state2( drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_state_t *state ) +static int radeon_emit_state2(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_state_t * state) { RING_LOCALS; if (state->dirty & RADEON_UPLOAD_ZBIAS) { - BEGIN_RING( 3 ); - OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) ); - OUT_RING( state->context2.se_zbias_factor ); - OUT_RING( state->context2.se_zbias_constant ); + BEGIN_RING(3); + OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); + OUT_RING(state->context2.se_zbias_factor); + OUT_RING(state->context2.se_zbias_constant); ADVANCE_RING(); } - return radeon_emit_state( dev_priv, filp_priv, &state->context, - state->tex, state->dirty ); + return radeon_emit_state(dev_priv, filp_priv, &state->context, + state->tex, state->dirty); } /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. + * the tcl scalar and vector areas. */ -static struct { - int start; - int len; +static struct { + int start; + int len; const char *name; } packet[RADEON_MAX_STATE_PACKETS] = { - { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, - { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, - { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, - { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, - { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, - { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, - { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, - { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, - { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, - { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, - { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, - { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, - { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, - { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, - { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, - { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, - { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, - { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, - { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, - { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, - { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" }, - { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, - { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, - { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, - { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, - { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, - { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, - { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, - { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, - { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, - { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, - { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, - { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, - { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, - { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, - { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, - { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, - { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, - { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, - { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, - { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, - { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, - { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, - { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, - { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, - { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, - { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, - { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, - { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, - { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, - { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, - { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, - { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, - { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ - { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ - { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, - { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, - { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, - { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, - { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, - { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, - { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, - { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, - { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, - { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, - { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, - { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, - { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, - { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, - { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, - { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, - { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, - { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, - { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, - { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, - { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, - { R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ - { R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, - { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, - { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, - { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, - { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, - { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, - { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, - { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, + {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, + {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, + {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, + {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, + {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, + {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, + {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, + {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, + {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, + {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, + {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, + {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, + {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, + {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, + {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, + {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, + {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, + {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, + {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, + {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, + {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, + "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, + {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, + {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, + {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, + {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, + {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, + {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, + {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, + {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, + {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, + {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, + {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, + {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, + {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, + {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, + {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, + {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, + {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, + {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, + {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, + {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, + {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, + {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, + {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, + {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, + {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, + {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, + {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, + {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, + {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, + {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, + {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, + {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, + {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, + {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, + {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, + {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, + {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, + {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, + {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, + {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, + "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, + {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ + {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ + {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, + {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, + {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, + {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, + {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, + {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, + {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, + {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, + {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, + {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, + {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, + {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, + {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, + {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, + {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, + {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, + {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, + {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, + {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, + {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, + {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, + {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, + {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ + {R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, + {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, + {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, + {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, + {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, + {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, + {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, + {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, }; - - /* ================================================================ * Performance monitoring functions */ -static void radeon_clear_box( drm_radeon_private_t *dev_priv, - int x, int y, int w, int h, - int r, int g, int b ) +static void radeon_clear_box(drm_radeon_private_t * dev_priv, + int x, int y, int w, int h, int r, int g, int b) { u32 color; RING_LOCALS; @@ -604,49 +617,47 @@ static void radeon_clear_box( drm_radeon_private_t *dev_priv, x += dev_priv->sarea_priv->boxes[0].x1; y += dev_priv->sarea_priv->boxes[0].y1; - switch ( dev_priv->color_fmt ) { + switch (dev_priv->color_fmt) { case RADEON_COLOR_FORMAT_RGB565: color = (((r & 0xf8) << 8) | - ((g & 0xfc) << 3) | - ((b & 0xf8) >> 3)); + ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); break; case RADEON_COLOR_FORMAT_ARGB8888: default: - color = (((0xff) << 24) | (r << 16) | (g << 8) | b); + color = (((0xff) << 24) | (r << 16) | (g << 8) | b); break; } - BEGIN_RING( 4 ); - RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( 0xffffffff ); + BEGIN_RING(4); + RADEON_WAIT_UNTIL_3D_IDLE(); + OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); + OUT_RING(0xffffffff); ADVANCE_RING(); - BEGIN_RING( 6 ); + BEGIN_RING(6); - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); + OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { - OUT_RING( dev_priv->front_pitch_offset ); - } else { - OUT_RING( dev_priv->back_pitch_offset ); - } + if (dev_priv->page_flipping && dev_priv->current_page == 1) { + OUT_RING(dev_priv->front_pitch_offset); + } else { + OUT_RING(dev_priv->back_pitch_offset); + } - OUT_RING( color ); + OUT_RING(color); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } -static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) +static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) { /* Collapse various things into a wait flag -- trying to * guess if userspase slept -- better just to have them tell us. @@ -662,50 +673,50 @@ static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv ) /* Purple box for page flipping */ - if ( dev_priv->stats.boxes & RADEON_BOX_FLIP ) - radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 ); + if (dev_priv->stats.boxes & RADEON_BOX_FLIP) + radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255); /* Red box if we have to wait for idle at any point */ - if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE ) - radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 ); + if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) + radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0); /* Blue box: lost context? */ /* Yellow box for texture swaps */ - if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD ) - radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 ); + if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) + radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0); /* Green box if hardware never idles (as far as we can tell) */ - if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) ) - radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 ); - + if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) + radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); - /* Draw bars indicating number of buffers allocated + /* Draw bars indicating number of buffers allocated * (not a great measure, easily confused) */ if (dev_priv->stats.requested_bufs) { if (dev_priv->stats.requested_bufs > 100) dev_priv->stats.requested_bufs = 100; - radeon_clear_box( dev_priv, 4, 16, - dev_priv->stats.requested_bufs, 4, - 196, 128, 128 ); + radeon_clear_box(dev_priv, 4, 16, + dev_priv->stats.requested_bufs, 4, + 196, 128, 128); } - memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) ); + memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); } + /* ================================================================ * CP command dispatch functions */ -static void radeon_cp_dispatch_clear( drm_device_t *dev, - drm_radeon_clear_t *clear, - drm_radeon_clear_rect_t *depth_boxes ) +static void radeon_cp_dispatch_clear(drm_device_t * dev, + drm_radeon_clear_t * clear, + drm_radeon_clear_rect_t * depth_boxes) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -713,32 +724,34 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, int nbox = sarea_priv->nbox; drm_clip_rect_t *pbox = sarea_priv->boxes; unsigned int flags = clear->flags; - u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0; + u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; int i; RING_LOCALS; - DRM_DEBUG( "flags = 0x%x\n", flags ); + DRM_DEBUG("flags = 0x%x\n", flags); dev_priv->stats.clears++; - if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) { + if (dev_priv->page_flipping && dev_priv->current_page == 1) { unsigned int tmp = flags; flags &= ~(RADEON_FRONT | RADEON_BACK); - if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK; - if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT; + if (tmp & RADEON_FRONT) + flags |= RADEON_BACK; + if (tmp & RADEON_BACK) + flags |= RADEON_FRONT; } - if ( flags & (RADEON_FRONT | RADEON_BACK) ) { + if (flags & (RADEON_FRONT | RADEON_BACK)) { - BEGIN_RING( 4 ); + BEGIN_RING(4); /* Ensure the 3D stream is idle before doing a * 2D fill to clear the front or back buffer. */ RADEON_WAIT_UNTIL_3D_IDLE(); - - OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) ); - OUT_RING( clear->color_mask ); + + OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); + OUT_RING(clear->color_mask); ADVANCE_RING(); @@ -746,121 +759,130 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n", - x, y, w, h, flags ); - - if ( flags & RADEON_FRONT ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); - + DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", + x, y, w, h, flags); + + if (flags & RADEON_FRONT) { + BEGIN_RING(6); + + OUT_RING(CP_PACKET3 + (RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv-> + color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS); + + OUT_RING(dev_priv->front_pitch_offset); + OUT_RING(clear->clear_color); + + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); + ADVANCE_RING(); } - - if ( flags & RADEON_BACK ) { - BEGIN_RING( 6 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) ); - OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS ); - - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( clear->clear_color ); - - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + + if (flags & RADEON_BACK) { + BEGIN_RING(6); + + OUT_RING(CP_PACKET3 + (RADEON_CNTL_PAINT_MULTI, 4)); + OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dev_priv-> + color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_P | + RADEON_GMC_CLR_CMP_CNTL_DIS); + + OUT_RING(dev_priv->back_pitch_offset); + OUT_RING(clear->clear_color); + + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } } } - + /* hyper z clear */ /* no docs available, based on reverse engeneering by Stephane Marchesin */ - if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { + if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) + && (flags & RADEON_CLEAR_FASTZ)) { int i; - int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? - (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); - + int depthpixperline = + dev_priv->depth_fmt == + RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch / + 2) : (dev_priv-> + depth_pitch / 4); + u32 clearmask; u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | - ((clear->depth_mask & 0xff) << 24); - - + ((clear->depth_mask & 0xff) << 24); + /* Make sure we restore the 3D state next time. * we haven't touched any "normal" state - still need this? */ dev_priv->sarea_priv->ctx_owner = 0; - if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { - /* FIXME : reverse engineer that for Rx00 cards */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ - /* pattern seems to work for r100, though get slight - rendering errors with glxgears. If hierz is not enabled for r100, - only 4 bits which indicate clear (15,16,31,32, all zero) matter, the - other ones are ignored, and the same clear mask can be used. That's - very different behaviour than R200 which needs different clear mask - and different number of tiles to clear if hierz is enabled or not !?! - */ - clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; - } - else { - /* clear mask : chooses the clearing pattern. - rv250: could be used to clear only parts of macrotiles - (but that would get really complicated...)? - bit 0 and 1 (either or both of them ?!?!) are used to - not clear tile (or maybe one of the bits indicates if the tile is - compressed or not), bit 2 and 3 to not clear tile 1,...,. - Pattern is as follows: - | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| - bits ------------------------------------------------- - | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| - rv100: clearmask covers 2x8 4x1 tiles, but one clear still - covers 256 pixels ?!? - */ + if ((dev_priv->flags & CHIP_HAS_HIERZ) + && (flags & RADEON_USE_HIERZ)) { + /* FIXME : reverse engineer that for Rx00 cards */ + /* FIXME : the mask supposedly contains low-res z values. So can't set + just to the max (0xff? or actually 0x3fff?), need to take z clear + value into account? */ + /* pattern seems to work for r100, though get slight + rendering errors with glxgears. If hierz is not enabled for r100, + only 4 bits which indicate clear (15,16,31,32, all zero) matter, the + other ones are ignored, and the same clear mask can be used. That's + very different behaviour than R200 which needs different clear mask + and different number of tiles to clear if hierz is enabled or not !?! + */ + clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f; + } else { + /* clear mask : chooses the clearing pattern. + rv250: could be used to clear only parts of macrotiles + (but that would get really complicated...)? + bit 0 and 1 (either or both of them ?!?!) are used to + not clear tile (or maybe one of the bits indicates if the tile is + compressed or not), bit 2 and 3 to not clear tile 1,...,. + Pattern is as follows: + | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| + bits ------------------------------------------------- + | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| + rv100: clearmask covers 2x8 4x1 tiles, but one clear still + covers 256 pixels ?!? + */ clearmask = 0x0; } - BEGIN_RING( 8 ); + BEGIN_RING(8); RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, - tempRB3D_DEPTHCLEARVALUE); + OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE, + tempRB3D_DEPTHCLEARVALUE); /* what offset is this exactly ? */ - OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); + OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0); /* need ctlstat, otherwise get some strange black flickering */ - OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); + OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT, + RADEON_RB3D_ZC_FLUSH_ALL); ADVANCE_RING(); for (i = 0; i < nbox; i++) { int tileoffset, nrtilesx, nrtilesy, j; /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ - if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { + if ((dev_priv->flags & CHIP_HAS_HIERZ) + && !(dev_priv->microcode_version == UCODE_R200)) { /* FIXME : figure this out for r200 (when hierz is enabled). Or maybe r200 actually doesn't need to put the low-res z value into the tile cache like r100, but just needs to clear the hi-level z-buffer? @@ -868,59 +890,74 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, R100 seems to operate on 2x1 8x8 tiles, but... odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially problematic with resolutions which are not 64 pix aligned? */ - tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; - nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); + tileoffset = + ((pbox[i].y1 >> 3) * depthpixperline + + pbox[i].x1) >> 6; + nrtilesx = + ((pbox[i].x2 & ~63) - + (pbox[i].x1 & ~63)) >> 4; + nrtilesy = + (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); + BEGIN_RING(4); + OUT_RING(CP_PACKET3 + (RADEON_3D_CLEAR_ZMASK, 2)); /* first tile */ - OUT_RING( tileoffset * 8 ); + OUT_RING(tileoffset * 8); /* the number of tiles to clear */ - OUT_RING( nrtilesx + 4 ); + OUT_RING(nrtilesx + 4); /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); + OUT_RING(clearmask); ADVANCE_RING(); tileoffset += depthpixperline >> 6; } - } - else if (dev_priv->microcode_version==UCODE_R200) { + } else if (dev_priv->microcode_version == UCODE_R200) { /* works for rv250. */ /* find first macro tile (8x2 4x4 z-pixels on rv250) */ - tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; - nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); - nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); + tileoffset = + ((pbox[i].y1 >> 3) * depthpixperline + + pbox[i].x1) >> 5; + nrtilesx = + (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); + nrtilesy = + (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); + BEGIN_RING(4); + OUT_RING(CP_PACKET3 + (RADEON_3D_CLEAR_ZMASK, 2)); /* first tile */ /* judging by the first tile offset needed, could possibly directly address/clear 4x4 tiles instead of 8x2 * 4x4 macro tiles, though would still need clear mask for right/bottom if truely 4x4 granularity is desired ? */ - OUT_RING( tileoffset * 16 ); + OUT_RING(tileoffset * 16); /* the number of tiles to clear */ - OUT_RING( nrtilesx + 1 ); + OUT_RING(nrtilesx + 1); /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); + OUT_RING(clearmask); ADVANCE_RING(); tileoffset += depthpixperline >> 5; } - } - else { /* rv 100 */ + } else { /* rv 100 */ /* rv100 might not need 64 pix alignment, who knows */ /* offsets are, hmm, weird */ - tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; - nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; - nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); + tileoffset = + ((pbox[i].y1 >> 4) * depthpixperline + + pbox[i].x1) >> 6; + nrtilesx = + ((pbox[i].x2 & ~63) - + (pbox[i].x1 & ~63)) >> 4; + nrtilesy = + (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); for (j = 0; j <= nrtilesy; j++) { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); - OUT_RING( tileoffset * 128 ); + BEGIN_RING(4); + OUT_RING(CP_PACKET3 + (RADEON_3D_CLEAR_ZMASK, 2)); + OUT_RING(tileoffset * 128); /* the number of tiles to clear */ - OUT_RING( nrtilesx + 4 ); + OUT_RING(nrtilesx + 4); /* clear mask : chooses the clearing pattern. */ - OUT_RING( clearmask ); + OUT_RING(clearmask); ADVANCE_RING(); tileoffset += depthpixperline >> 6; } @@ -928,18 +965,19 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, } /* TODO don't always clear all hi-level z tiles */ - if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) - && (flags & RADEON_USE_HIERZ)) - /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ - /* FIXME : the mask supposedly contains low-res z values. So can't set - just to the max (0xff? or actually 0x3fff?), need to take z clear - value into account? */ + if ((dev_priv->flags & CHIP_HAS_HIERZ) + && (dev_priv->microcode_version == UCODE_R200) + && (flags & RADEON_USE_HIERZ)) + /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ + /* FIXME : the mask supposedly contains low-res z values. So can't set + just to the max (0xff? or actually 0x3fff?), need to take z clear + value into account? */ { - BEGIN_RING( 4 ); - OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); - OUT_RING( 0x0 ); /* First tile */ - OUT_RING( 0x3cc0 ); - OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); + BEGIN_RING(4); + OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); + OUT_RING(0x0); /* First tile */ + OUT_RING(0x3cc0); + OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); ADVANCE_RING(); } } @@ -974,30 +1012,27 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, tempSE_CNTL = depth_clear->se_cntl; - - /* Disable TCL */ - tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ - (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); + tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ + (0x9 << + SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); tempRB3D_PLANEMASK = 0x0; tempRE_AUX_SCISSOR_CNTL = 0x0; tempSE_VTE_CNTL = - SE_VTE_CNTL__VTX_XY_FMT_MASK | - SE_VTE_CNTL__VTX_Z_FMT_MASK; + SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK; - /* Vertex format (X, Y, Z, W)*/ + /* Vertex format (X, Y, Z, W) */ tempSE_VTX_FMT_0 = - SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | - SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; + SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | + SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; tempSE_VTX_FMT_1 = 0x0; - - /* - * Depth buffer specific enables + /* + * Depth buffer specific enables */ if (flags & RADEON_DEPTH) { /* Enable depth buffer */ @@ -1007,12 +1042,12 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, tempRB3D_CNTL &= ~RADEON_Z_ENABLE; } - /* + /* * Stencil buffer specific enables */ - if ( flags & RADEON_STENCIL ) { - tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; - tempRB3D_STENCILREFMASK = clear->depth_mask; + if (flags & RADEON_STENCIL) { + tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; + tempRB3D_STENCILREFMASK = clear->depth_mask; } else { tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; tempRB3D_STENCILREFMASK = 0x00000000; @@ -1020,79 +1055,75 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, if (flags & RADEON_USE_COMP_ZBUF) { tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; + RADEON_Z_DECOMPRESSION_ENABLE; } if (flags & RADEON_USE_HIERZ) { tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; } - BEGIN_RING( 26 ); + BEGIN_RING(26); RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL ); - OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL ); - OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL ); - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, - tempRB3D_ZSTENCILCNTL ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - tempRB3D_STENCILREFMASK ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK ); - OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL ); - OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL ); - OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 ); - OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 ); - OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL ); - OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL, - tempRE_AUX_SCISSOR_CNTL ); + OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); + OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); + OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); + OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); + OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, + tempRB3D_STENCILREFMASK); + OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); + OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL); + OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL); + OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0); + OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1); + OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL); + OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL); ADVANCE_RING(); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- + for (i = 0; i < nbox; i++) { + + /* Funny that this should be required -- * sets top-left? */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 14 ); - OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) ); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x3f800000 ); + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); + + BEGIN_RING(14); + OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); + OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + (3 << RADEON_NUM_VERTICES_SHIFT))); + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); + OUT_RING(depth_boxes[i].ui[CLEAR_X2]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x3f800000); ADVANCE_RING(); } - } - else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) { + } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) { int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; rb3d_cntl = depth_clear->rb3d_cntl; - if ( flags & RADEON_DEPTH ) { - rb3d_cntl |= RADEON_Z_ENABLE; + if (flags & RADEON_DEPTH) { + rb3d_cntl |= RADEON_Z_ENABLE; } else { rb3d_cntl &= ~RADEON_Z_ENABLE; } - if ( flags & RADEON_STENCIL ) { - rb3d_cntl |= RADEON_STENCIL_ENABLE; - rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ + if (flags & RADEON_STENCIL) { + rb3d_cntl |= RADEON_STENCIL_ENABLE; + rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ } else { rb3d_cntl &= ~RADEON_STENCIL_ENABLE; rb3d_stencilrefmask = 0x00000000; @@ -1100,66 +1131,61 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, if (flags & RADEON_USE_COMP_ZBUF) { tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | - RADEON_Z_DECOMPRESSION_ENABLE; + RADEON_Z_DECOMPRESSION_ENABLE; } if (flags & RADEON_USE_HIERZ) { tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; } - BEGIN_RING( 13 ); + BEGIN_RING(13); RADEON_WAIT_UNTIL_2D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) ); - OUT_RING( 0x00000000 ); - OUT_RING( rb3d_cntl ); - - OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL ); - OUT_RING_REG( RADEON_RB3D_STENCILREFMASK, - rb3d_stencilrefmask ); - OUT_RING_REG( RADEON_RB3D_PLANEMASK, - 0x00000000 ); - OUT_RING_REG( RADEON_SE_CNTL, - depth_clear->se_cntl ); + OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); + OUT_RING(0x00000000); + OUT_RING(rb3d_cntl); + + OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); + OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask); + OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000); + OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl); ADVANCE_RING(); /* Make sure we restore the 3D state next time. */ dev_priv->sarea_priv->ctx_owner = 0; - for ( i = 0 ; i < nbox ; i++ ) { - - /* Funny that this should be required -- + for (i = 0; i < nbox; i++) { + + /* Funny that this should be required -- * sets top-left? */ - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); - - BEGIN_RING( 15 ); - - OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) ); - OUT_RING( RADEON_VTX_Z_PRESENT | - RADEON_VTX_PKCOLOR_PRESENT); - OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST | - RADEON_PRIM_WALK_RING | - RADEON_MAOS_ENABLE | - RADEON_VTX_FMT_RADEON_MODE | - (3 << RADEON_NUM_VERTICES_SHIFT)) ); - - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X1] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); - - OUT_RING( depth_boxes[i].ui[CLEAR_X2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_Y2] ); - OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] ); - OUT_RING( 0x0 ); + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); + + BEGIN_RING(15); + + OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); + OUT_RING(RADEON_VTX_Z_PRESENT | + RADEON_VTX_PKCOLOR_PRESENT); + OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | + RADEON_PRIM_WALK_RING | + RADEON_MAOS_ENABLE | + RADEON_VTX_FMT_RADEON_MODE | + (3 << RADEON_NUM_VERTICES_SHIFT))); + + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); + + OUT_RING(depth_boxes[i].ui[CLEAR_X1]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); + + OUT_RING(depth_boxes[i].ui[CLEAR_X2]); + OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); + OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); + OUT_RING(0x0); ADVANCE_RING(); } @@ -1171,15 +1197,15 @@ static void radeon_cp_dispatch_clear( drm_device_t *dev, */ dev_priv->sarea_priv->last_clear++; - BEGIN_RING( 4 ); + BEGIN_RING(4); - RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear ); + RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); } -static void radeon_cp_dispatch_swap( drm_device_t *dev ) +static void radeon_cp_dispatch_swap(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1187,59 +1213,55 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) drm_clip_rect_t *pbox = sarea_priv->boxes; int i; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); /* Do some trivial performance monitoring... */ if (dev_priv->do_boxes) - radeon_cp_performance_boxes( dev_priv ); - + radeon_cp_performance_boxes(dev_priv); /* Wait for the 3D stream to idle before dispatching the bitblt. * This will prevent data corruption between the two streams. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); - for ( i = 0 ; i < nbox ; i++ ) { + for (i = 0; i < nbox; i++) { int x = pbox[i].x1; int y = pbox[i].y1; int w = pbox[i].x2 - x; int h = pbox[i].y2 - y; - DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n", - x, y, w, h ); - - BEGIN_RING( 7 ); - - OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) ); - OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL | - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_NONE | - (dev_priv->color_fmt << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_S | - RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); - + DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h); + + BEGIN_RING(7); + + OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); + OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | + RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_NONE | + (dev_priv->color_fmt << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + RADEON_ROP3_S | + RADEON_DP_SRC_SOURCE_MEMORY | + RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); + /* Make this work even if front & back are flipped: */ if (dev_priv->current_page == 0) { - OUT_RING( dev_priv->back_pitch_offset ); - OUT_RING( dev_priv->front_pitch_offset ); - } - else { - OUT_RING( dev_priv->front_pitch_offset ); - OUT_RING( dev_priv->back_pitch_offset ); + OUT_RING(dev_priv->back_pitch_offset); + OUT_RING(dev_priv->front_pitch_offset); + } else { + OUT_RING(dev_priv->front_pitch_offset); + OUT_RING(dev_priv->back_pitch_offset); } - OUT_RING( (x << 16) | y ); - OUT_RING( (x << 16) | y ); - OUT_RING( (w << 16) | h ); + OUT_RING((x << 16) | y); + OUT_RING((x << 16) | y); + OUT_RING((w << 16) | h); ADVANCE_RING(); } @@ -1250,44 +1272,43 @@ static void radeon_cp_dispatch_swap( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; - BEGIN_RING( 4 ); + BEGIN_RING(4); - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); } -static void radeon_cp_dispatch_flip( drm_device_t *dev ) +static void radeon_cp_dispatch_flip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle; + drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle; int offset = (dev_priv->current_page == 1) - ? dev_priv->front_offset : dev_priv->back_offset; + ? dev_priv->front_offset : dev_priv->back_offset; RING_LOCALS; - DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n", - __FUNCTION__, - dev_priv->current_page, - dev_priv->sarea_priv->pfCurrentPage); + DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", + __FUNCTION__, + dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); /* Do some trivial performance monitoring... */ if (dev_priv->do_boxes) { dev_priv->stats.boxes |= RADEON_BOX_FLIP; - radeon_cp_performance_boxes( dev_priv ); + radeon_cp_performance_boxes(dev_priv); } /* Update the frame offsets for both CRTCs */ - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch - + sarea->frame.x - * ( dev_priv->color_fmt - 2 ) ) & ~7 ) - + offset ); - OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base - + offset ); + OUT_RING_REG(RADEON_CRTC_OFFSET, + ((sarea->frame.y * dev_priv->front_pitch + + sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) + + offset); + OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base + + offset); ADVANCE_RING(); @@ -1297,16 +1318,16 @@ static void radeon_cp_dispatch_flip( drm_device_t *dev ) */ dev_priv->sarea_priv->last_frame++; dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = - 1 - dev_priv->current_page; + 1 - dev_priv->current_page; - BEGIN_RING( 2 ); + BEGIN_RING(2); - RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame ); + RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); ADVANCE_RING(); } -static int bad_prim_vertex_nr( int primitive, int nr ) +static int bad_prim_vertex_nr(int primitive, int nr) { switch (primitive & RADEON_PRIM_TYPE_MASK) { case RADEON_PRIM_TYPE_NONE: @@ -1326,24 +1347,21 @@ static int bad_prim_vertex_nr( int primitive, int nr ) return nr < 3; default: return 1; - } + } } - - typedef struct { unsigned int start; unsigned int finish; unsigned int prim; unsigned int numverts; - unsigned int offset; - unsigned int vc_format; + unsigned int offset; + unsigned int vc_format; } drm_radeon_tcl_prim_t; -static void radeon_cp_dispatch_vertex( drm_device_t *dev, - drm_buf_t *buf, - drm_radeon_tcl_prim_t *prim ) - +static void radeon_cp_dispatch_vertex(drm_device_t * dev, + drm_buf_t * buf, + drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1355,45 +1373,39 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev, DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", prim->prim, - prim->vc_format, - prim->start, - prim->finish, - prim->numverts); + prim->vc_format, prim->start, prim->finish, prim->numverts); - if (bad_prim_vertex_nr( prim->prim, prim->numverts )) { - DRM_ERROR( "bad prim %x numverts %d\n", - prim->prim, prim->numverts ); + if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { + DRM_ERROR("bad prim %x numverts %d\n", + prim->prim, prim->numverts); return; } do { /* Emit the next cliprect */ - if ( i < nbox ) { - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < nbox) { + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); } /* Emit the vertex buffer rendering commands */ - BEGIN_RING( 5 ); + BEGIN_RING(5); - OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) ); - OUT_RING( offset ); - OUT_RING( numverts ); - OUT_RING( prim->vc_format ); - OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST | - RADEON_COLOR_ORDER_RGBA | - RADEON_VTX_FMT_RADEON_MODE | - (numverts << RADEON_NUM_VERTICES_SHIFT) ); + OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); + OUT_RING(offset); + OUT_RING(numverts); + OUT_RING(prim->vc_format); + OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | + RADEON_COLOR_ORDER_RGBA | + RADEON_VTX_FMT_RADEON_MODE | + (numverts << RADEON_NUM_VERTICES_SHIFT)); ADVANCE_RING(); i++; - } while ( i < nbox ); + } while (i < nbox); } - - -static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) +static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_buf_priv_t *buf_priv = buf->dev_private; @@ -1402,24 +1414,22 @@ static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf ) buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; /* Emit the vertex buffer age */ - BEGIN_RING( 2 ); - RADEON_DISPATCH_AGE( buf_priv->age ); + BEGIN_RING(2); + RADEON_DISPATCH_AGE(buf_priv->age); ADVANCE_RING(); buf->pending = 1; buf->used = 0; } -static void radeon_cp_dispatch_indirect( drm_device_t *dev, - drm_buf_t *buf, - int start, int end ) +static void radeon_cp_dispatch_indirect(drm_device_t * dev, + drm_buf_t * buf, int start, int end) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n", - buf->idx, start, end ); + DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); - if ( start != end ) { + if (start != end) { int offset = (dev_priv->gart_buffers_offset + buf->offset + start); int dwords = (end - start + 3) / sizeof(u32); @@ -1428,28 +1438,27 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, * dwords, so if we've been given an odd number we must * pad the data with a Type-2 CP packet. */ - if ( dwords & 1 ) { + if (dwords & 1) { u32 *data = (u32 *) - ((char *)dev->agp_buffer_map->handle - + buf->offset + start); + ((char *)dev->agp_buffer_map->handle + + buf->offset + start); data[dwords++] = RADEON_CP_PACKET2; } /* Fire off the indirect buffer */ - BEGIN_RING( 3 ); + BEGIN_RING(3); - OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) ); - OUT_RING( offset ); - OUT_RING( dwords ); + OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); + OUT_RING(offset); + OUT_RING(dwords); ADVANCE_RING(); } } - -static void radeon_cp_dispatch_indices( drm_device_t *dev, - drm_buf_t *elt_buf, - drm_radeon_tcl_prim_t *prim ) +static void radeon_cp_dispatch_indices(drm_device_t * dev, + drm_buf_t * elt_buf, + drm_radeon_tcl_prim_t * prim) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; @@ -1464,30 +1473,24 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", prim->prim, prim->vc_format, - prim->start, - prim->finish, - prim->offset, - prim->numverts); - - if (bad_prim_vertex_nr( prim->prim, count )) { - DRM_ERROR( "bad prim %x count %d\n", - prim->prim, count ); + prim->start, prim->finish, prim->offset, prim->numverts); + + if (bad_prim_vertex_nr(prim->prim, count)) { + DRM_ERROR("bad prim %x count %d\n", prim->prim, count); return; } - - if ( start >= prim->finish || - (prim->start & 0x7) ) { - DRM_ERROR( "buffer prim %d\n", prim->prim ); + if (start >= prim->finish || (prim->start & 0x7)) { + DRM_ERROR("buffer prim %d\n", prim->prim); return; } dwords = (prim->finish - prim->start + 3) / sizeof(u32); - data = (u32 *)((char *)dev->agp_buffer_map->handle + - elt_buf->offset + prim->start); + data = (u32 *) ((char *)dev->agp_buffer_map->handle + + elt_buf->offset + prim->start); - data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 ); + data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2); data[1] = offset; data[2] = prim->numverts; data[3] = prim->vc_format; @@ -1495,28 +1498,26 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, RADEON_PRIM_WALK_IND | RADEON_COLOR_ORDER_RGBA | RADEON_VTX_FMT_RADEON_MODE | - (count << RADEON_NUM_VERTICES_SHIFT) ); + (count << RADEON_NUM_VERTICES_SHIFT)); do { - if ( i < nbox ) - radeon_emit_clip_rect( dev_priv, - &sarea_priv->boxes[i] ); + if (i < nbox) + radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); - radeon_cp_dispatch_indirect( dev, elt_buf, - prim->start, - prim->finish ); + radeon_cp_dispatch_indirect(dev, elt_buf, + prim->start, prim->finish); i++; - } while ( i < nbox ); + } while (i < nbox); } #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE -static int radeon_cp_dispatch_texture( DRMFILE filp, - drm_device_t *dev, - drm_radeon_texture_t *tex, - drm_radeon_tex_image_t *image ) +static int radeon_cp_dispatch_texture(DRMFILE filp, + drm_device_t * dev, + drm_radeon_texture_t * tex, + drm_radeon_tex_image_t * image) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_file_t *filp_priv; @@ -1531,11 +1532,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, u32 offset; RING_LOCALS; - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) { - DRM_ERROR( "Invalid destination offset\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { + DRM_ERROR("Invalid destination offset\n"); + return DRM_ERR(EINVAL); } dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; @@ -1544,7 +1545,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * up with the texture data from the host data blit, otherwise * part of the texture image may be corrupted. */ - BEGIN_RING( 4 ); + BEGIN_RING(4); RADEON_FLUSH_CACHE(); RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); @@ -1553,7 +1554,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * even if the only legal values are powers of two. Thus, we'll * use a shift instead. */ - switch ( tex->format ) { + switch (tex->format) { case RADEON_TXFORMAT_ARGB8888: case RADEON_TXFORMAT_RGBA8888: format = RADEON_COLOR_FORMAT_ARGB8888; @@ -1577,7 +1578,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, blit_width = image->width * 1; break; default: - DRM_ERROR( "invalid texture format %d\n", tex->format ); + DRM_ERROR("invalid texture format %d\n", tex->format); return DRM_ERR(EINVAL); } spitch = blit_width >> 6; @@ -1592,49 +1593,49 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, /* we got tiled coordinates, untile them */ image->x *= 2; } - } - else microtile = 0; + } else + microtile = 0; - DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width ); + DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); do { - DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", - tex->offset >> 10, tex->pitch, tex->format, - image->x, image->y, image->width, image->height ); + DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", + tex->offset >> 10, tex->pitch, tex->format, + image->x, image->y, image->width, image->height); /* Make a copy of some parameters in case we have to * update them for a multi-pass texture blit. */ height = image->height; data = (const u8 __user *)image->data; - + size = height * blit_width; - if ( size > RADEON_MAX_TEXTURE_SIZE ) { + if (size > RADEON_MAX_TEXTURE_SIZE) { height = RADEON_MAX_TEXTURE_SIZE / blit_width; size = height * blit_width; - } else if ( size < 4 && size > 0 ) { + } else if (size < 4 && size > 0) { size = 4; - } else if ( size == 0 ) { + } else if (size == 0) { return 0; } - buf = radeon_freelist_get( dev ); - if ( 0 && !buf ) { - radeon_do_cp_idle( dev_priv ); - buf = radeon_freelist_get( dev ); + buf = radeon_freelist_get(dev); + if (0 && !buf) { + radeon_do_cp_idle(dev_priv); + buf = radeon_freelist_get(dev); } - if ( !buf ) { + if (!buf) { DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); - if (DRM_COPY_TO_USER( tex->image, image, sizeof(*image) )) + if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) return DRM_ERR(EFAULT); return DRM_ERR(EAGAIN); } - /* Dispatch the indirect buffer. */ - buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset); + buffer = + (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); dwords = size / 4; if (microtile) { @@ -1649,20 +1650,26 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, if (tex->height == 1) { if (tex_width >= 64 || tex_width <= 16) { if (DRM_COPY_FROM_USER(buffer, data, - tex_width * sizeof(u32))) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + tex_width * + sizeof(u32))) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } } else if (tex_width == 32) { - if (DRM_COPY_FROM_USER(buffer, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer, data, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } - if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer + 8, data + 16, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } } @@ -1675,9 +1682,11 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, } } else if (tex_width < 16) { for (i = 0; i < tex->height; i++) { - if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer, data, tex_width)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } buffer += 4; @@ -1687,35 +1696,42 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, /* TODO: make sure this works when not fitting in one buffer (i.e. 32bytes x 2048...) */ for (i = 0; i < tex->height; i += 2) { - if (DRM_COPY_FROM_USER(buffer, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer, data, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } data += 16; - if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer + 8, data, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } data += 16; - if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer + 4, data, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } data += 16; - if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { - DRM_ERROR("EFAULT on pad, %d bytes\n", - tex_width); + if (DRM_COPY_FROM_USER + (buffer + 12, data, 16)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } data += 16; buffer += 16; } } - } - else { + } else { if (tex_width >= 32) { /* Texture image width is larger than the minimum, so we * can upload it directly. @@ -1731,9 +1747,12 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * need to pad out each image scanline to the minimum * width. */ - for (i = 0 ; i < tex->height ; i++) { - if (DRM_COPY_FROM_USER(buffer, data, tex_width )) { - DRM_ERROR("EFAULT on pad, %d bytes\n", tex_width); + for (i = 0; i < tex->height; i++) { + if (DRM_COPY_FROM_USER + (buffer, data, tex_width)) { + DRM_ERROR + ("EFAULT on pad, %d bytes\n", + tex_width); return DRM_ERR(EFAULT); } buffer += 8; @@ -1754,8 +1773,7 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, RADEON_GMC_SRC_DATATYPE_COLOR | RADEON_ROP3_S | RADEON_DP_SRC_SOURCE_MEMORY | - RADEON_GMC_CLR_CMP_CNTL_DIS | - RADEON_GMC_WR_MSK_DIS ); + RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); OUT_RING((spitch << 22) | (offset >> 10)); OUT_RING((texpitch << 22) | (tex->offset >> 10)); OUT_RING(0); @@ -1776,62 +1794,62 @@ static int radeon_cp_dispatch_texture( DRMFILE filp, * the texture data is written out to memory before rendering * continues. */ - BEGIN_RING( 4 ); + BEGIN_RING(4); RADEON_FLUSH_CACHE(); RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); return 0; } - -static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple ) +static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple) { drm_radeon_private_t *dev_priv = dev->dev_private; int i; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 35 ); + BEGIN_RING(35); - OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) ); - OUT_RING( 0x00000000 ); + OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); + OUT_RING(0x00000000); - OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) ); - for ( i = 0 ; i < 32 ; i++ ) { - OUT_RING( stipple[i] ); + OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); + for (i = 0; i < 32; i++) { + OUT_RING(stipple[i]); } ADVANCE_RING(); } -static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) +static void radeon_apply_surface_regs(int surf_index, + drm_radeon_private_t * dev_priv) { if (!dev_priv->mmio) return; radeon_do_cp_idle(dev_priv); - RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, - dev_priv->surfaces[surf_index].flags); - RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, - dev_priv->surfaces[surf_index].lower); - RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, - dev_priv->surfaces[surf_index].upper); + RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index, + dev_priv->surfaces[surf_index].flags); + RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index, + dev_priv->surfaces[surf_index].lower); + RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index, + dev_priv->surfaces[surf_index].upper); } - /* Allocates a virtual surface - * doesn't always allocate a real surface, will stretch an existing + * doesn't always allocate a real surface, will stretch an existing * surface when possible. * * Note that refcount can be at most 2, since during a free refcount=3 * might mean we have to allocate a new surface which might not always * be available. - * For example : we allocate three contigous surfaces ABC. If B is + * For example : we allocate three contigous surfaces ABC. If B is * freed, we suddenly need two surfaces to store A and C, which might * not always be available. */ -static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) +static int alloc_surface(drm_radeon_surface_alloc_t * new, + drm_radeon_private_t * dev_priv, DRMFILE filp) { struct radeon_virt_surface *s; int i; @@ -1843,34 +1861,37 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t * /* sanity check */ if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || - ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || - ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) + ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != + RADEON_SURF_ADDRESS_FIXED_MASK) + || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) return -1; /* make sure there is no overlap with existing surfaces */ for (i = 0; i < RADEON_MAX_SURFACES; i++) { if ((dev_priv->surfaces[i].refcount != 0) && - (( (new_lower >= dev_priv->surfaces[i].lower) && - (new_lower < dev_priv->surfaces[i].upper) ) || - ( (new_lower < dev_priv->surfaces[i].lower) && - (new_upper > dev_priv->surfaces[i].lower) )) ){ - return -1;} + (((new_lower >= dev_priv->surfaces[i].lower) && + (new_lower < dev_priv->surfaces[i].upper)) || + ((new_lower < dev_priv->surfaces[i].lower) && + (new_upper > dev_priv->surfaces[i].lower)))) { + return -1; + } } /* find a virtual surface */ - for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) + for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) if (dev_priv->virt_surfaces[i].filp == 0) break; - if (i == 2*RADEON_MAX_SURFACES) { - return -1;} + if (i == 2 * RADEON_MAX_SURFACES) { + return -1; + } virt_surface_index = i; /* try to reuse an existing surface */ for (i = 0; i < RADEON_MAX_SURFACES; i++) { /* extend before */ if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_upper + 1 == dev_priv->surfaces[i].lower)) { + (new->flags == dev_priv->surfaces[i].flags) && + (new_upper + 1 == dev_priv->surfaces[i].lower)) { s = &(dev_priv->virt_surfaces[virt_surface_index]); s->surface_index = i; s->lower = new_lower; @@ -1885,8 +1906,8 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t * /* extend after */ if ((dev_priv->surfaces[i].refcount == 1) && - (new->flags == dev_priv->surfaces[i].flags) && - (new_lower == dev_priv->surfaces[i].upper + 1)) { + (new->flags == dev_priv->surfaces[i].flags) && + (new_lower == dev_priv->surfaces[i].upper + 1)) { s = &(dev_priv->virt_surfaces[virt_surface_index]); s->surface_index = i; s->lower = new_lower; @@ -1922,26 +1943,34 @@ static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t * return -1; } -static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) +static int free_surface(DRMFILE filp, drm_radeon_private_t * dev_priv, + int lower) { struct radeon_virt_surface *s; int i; /* find the virtual surface */ - for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { + for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { s = &(dev_priv->virt_surfaces[i]); if (s->filp) { if ((lower == s->lower) && (filp == s->filp)) { - if (dev_priv->surfaces[s->surface_index].lower == s->lower) - dev_priv->surfaces[s->surface_index].lower = s->upper; + if (dev_priv->surfaces[s->surface_index]. + lower == s->lower) + dev_priv->surfaces[s->surface_index]. + lower = s->upper; - if (dev_priv->surfaces[s->surface_index].upper == s->upper) - dev_priv->surfaces[s->surface_index].upper = s->lower; + if (dev_priv->surfaces[s->surface_index]. + upper == s->upper) + dev_priv->surfaces[s->surface_index]. + upper = s->lower; dev_priv->surfaces[s->surface_index].refcount--; - if (dev_priv->surfaces[s->surface_index].refcount == 0) - dev_priv->surfaces[s->surface_index].flags = 0; + if (dev_priv->surfaces[s->surface_index]. + refcount == 0) + dev_priv->surfaces[s->surface_index]. + flags = 0; s->filp = NULL; - radeon_apply_surface_regs(s->surface_index, dev_priv); + radeon_apply_surface_regs(s->surface_index, + dev_priv); return 0; } } @@ -1949,13 +1978,14 @@ static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) return 1; } -static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) +static void radeon_surfaces_release(DRMFILE filp, + drm_radeon_private_t * dev_priv) { int i; - for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) - { + for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { if (dev_priv->virt_surfaces[i].filp == filp) - free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); + free_surface(filp, dev_priv, + dev_priv->virt_surfaces[i].lower); } } @@ -1969,12 +1999,13 @@ static int radeon_surface_alloc(DRM_IOCTL_ARGS) drm_radeon_surface_alloc_t alloc; if (!dev_priv) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, - sizeof(alloc)); + DRM_COPY_FROM_USER_IOCTL(alloc, + (drm_radeon_surface_alloc_t __user *) data, + sizeof(alloc)); if (alloc_surface(&alloc, dev_priv, filp) == -1) return DRM_ERR(EINVAL); @@ -1989,12 +2020,12 @@ static int radeon_surface_free(DRM_IOCTL_ARGS) drm_radeon_surface_free_t memfree; if (!dev_priv) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *)data, - sizeof(memfree) ); + DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_mem_free_t __user *) data, + sizeof(memfree)); if (free_surface(filp, dev_priv, memfree.address)) return DRM_ERR(EINVAL); @@ -2002,51 +2033,52 @@ static int radeon_surface_free(DRM_IOCTL_ARGS) return 0; } -static int radeon_cp_clear( DRM_IOCTL_ARGS ) +static int radeon_cp_clear(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; drm_radeon_clear_t clear; drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data, - sizeof(clear) ); + DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, + sizeof(clear)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes, - sarea_priv->nbox * sizeof(depth_boxes[0]) ) ) + if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, + sarea_priv->nbox * sizeof(depth_boxes[0]))) return DRM_ERR(EFAULT); - radeon_cp_dispatch_clear( dev, &clear, depth_boxes ); + radeon_cp_dispatch_clear(dev, &clear, depth_boxes); COMMIT_RING(); return 0; } - /* Not sure why this isn't set all the time: - */ -static int radeon_do_init_pageflip( drm_device_t *dev ) + */ +static int radeon_do_init_pageflip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - BEGIN_RING( 6 ); + BEGIN_RING(6); RADEON_WAIT_UNTIL_3D_IDLE(); - OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); - OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) ); - OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL ); + OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); + OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | + RADEON_CRTC_OFFSET_FLIP_CNTL); + OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); + OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | + RADEON_CRTC_OFFSET_FLIP_CNTL); ADVANCE_RING(); dev_priv->page_flipping = 1; @@ -2059,62 +2091,62 @@ static int radeon_do_init_pageflip( drm_device_t *dev ) /* Called whenever a client dies, from drm_release. * NOTE: Lock isn't necessarily held when this is called! */ -static int radeon_do_cleanup_pageflip( drm_device_t *dev ) +static int radeon_do_cleanup_pageflip(drm_device_t * dev) { drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); if (dev_priv->current_page != 0) - radeon_cp_dispatch_flip( dev ); + radeon_cp_dispatch_flip(dev); dev_priv->page_flipping = 0; return 0; } /* Swapping and flipping are different operations, need different ioctls. - * They can & should be intermixed to support multiple 3d windows. + * They can & should be intermixed to support multiple 3d windows. */ -static int radeon_cp_flip( DRM_IOCTL_ARGS ) +static int radeon_cp_flip(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); + + LOCK_TEST_WITH_RETURN(dev, filp); - LOCK_TEST_WITH_RETURN( dev, filp ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + if (!dev_priv->page_flipping) + radeon_do_init_pageflip(dev); - if (!dev_priv->page_flipping) - radeon_do_init_pageflip( dev ); - - radeon_cp_dispatch_flip( dev ); + radeon_cp_dispatch_flip(dev); COMMIT_RING(); return 0; } -static int radeon_cp_swap( DRM_IOCTL_ARGS ) +static int radeon_cp_swap(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - DRM_DEBUG( "\n" ); + DRM_DEBUG("\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS ) + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; - radeon_cp_dispatch_swap( dev ); + radeon_cp_dispatch_swap(dev); dev_priv->sarea_priv->ctx_owner = 0; COMMIT_RING(); return 0; } -static int radeon_cp_vertex( DRM_IOCTL_ARGS ) +static int radeon_cp_vertex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2125,55 +2157,53 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS ) drm_radeon_vertex_t vertex; drm_radeon_tcl_prim_t prim; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.count, vertex.discard ); + DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( vertex.prim < 0 || - vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", vertex.prim ); + if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", vertex.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } /* Build up a prim_t record: */ if (vertex.count) { - buf->used = vertex.count; /* not used? */ - - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); + buf->used = vertex.count; /* not used? */ + + if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { + if (radeon_emit_state(dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty)) { + DRM_ERROR("radeon_emit_state failed\n"); + return DRM_ERR(EINVAL); } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -2183,23 +2213,23 @@ static int radeon_cp_vertex( DRM_IOCTL_ARGS ) } prim.start = 0; - prim.finish = vertex.count; /* unused */ + prim.finish = vertex.count; /* unused */ prim.prim = vertex.prim; prim.numverts = vertex.count; prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_vertex( dev, buf, &prim ); + + radeon_cp_dispatch_vertex(dev, buf, &prim); } if (vertex.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } -static int radeon_cp_indices( DRM_IOCTL_ARGS ) +static int radeon_cp_indices(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2211,69 +2241,67 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS ) drm_radeon_tcl_prim_t prim; int count; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data, - sizeof(elts) ); + DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, + sizeof(elts)); - DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n", - DRM_CURRENTPID, - elts.idx, elts.start, elts.end, elts.discard ); + DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", + DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard); - if ( elts.idx < 0 || elts.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - elts.idx, dma->buf_count - 1 ); + if (elts.idx < 0 || elts.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + elts.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - if ( elts.prim < 0 || - elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) { - DRM_ERROR( "buffer prim %d\n", elts.prim ); + if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { + DRM_ERROR("buffer prim %d\n", elts.prim); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[elts.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", elts.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", elts.idx); return DRM_ERR(EINVAL); } count = (elts.end - elts.start) / sizeof(u16); elts.start -= RADEON_INDEX_PRIM_OFFSET; - if ( elts.start & 0x7 ) { - DRM_ERROR( "misaligned buffer 0x%x\n", elts.start ); + if (elts.start & 0x7) { + DRM_ERROR("misaligned buffer 0x%x\n", elts.start); return DRM_ERR(EINVAL); } - if ( elts.start < buf->used ) { - DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used ); + if (elts.start < buf->used) { + DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); return DRM_ERR(EINVAL); } buf->used = elts.end; - if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) { - if ( radeon_emit_state( dev_priv, filp_priv, - &sarea_priv->context_state, - sarea_priv->tex_state, - sarea_priv->dirty ) ) { - DRM_ERROR( "radeon_emit_state failed\n" ); - return DRM_ERR( EINVAL ); + if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { + if (radeon_emit_state(dev_priv, filp_priv, + &sarea_priv->context_state, + sarea_priv->tex_state, + sarea_priv->dirty)) { + DRM_ERROR("radeon_emit_state failed\n"); + return DRM_ERR(EINVAL); } sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | @@ -2282,26 +2310,25 @@ static int radeon_cp_indices( DRM_IOCTL_ARGS ) RADEON_REQUIRE_QUIESCENCE); } - /* Build up a prim_t record: */ prim.start = elts.start; - prim.finish = elts.end; + prim.finish = elts.end; prim.prim = elts.prim; prim.offset = 0; /* offset from start of dma buffers */ - prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ prim.vc_format = dev_priv->sarea_priv->vc_format; - - radeon_cp_dispatch_indices( dev, buf, &prim ); + + radeon_cp_dispatch_indices(dev, buf, &prim); if (elts.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } -static int radeon_cp_texture( DRM_IOCTL_ARGS ) +static int radeon_cp_texture(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2309,53 +2336,54 @@ static int radeon_cp_texture( DRM_IOCTL_ARGS ) drm_radeon_tex_image_t image; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) ); + DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, + sizeof(tex)); - if ( tex.image == NULL ) { - DRM_ERROR( "null texture image!\n" ); + if (tex.image == NULL) { + DRM_ERROR("null texture image!\n"); return DRM_ERR(EINVAL); } - if ( DRM_COPY_FROM_USER( &image, - (drm_radeon_tex_image_t __user *)tex.image, - sizeof(image) ) ) + if (DRM_COPY_FROM_USER(&image, + (drm_radeon_tex_image_t __user *) tex.image, + sizeof(image))) return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image ); + ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image); COMMIT_RING(); return ret; } -static int radeon_cp_stipple( DRM_IOCTL_ARGS ) +static int radeon_cp_stipple(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_stipple_t stipple; u32 mask[32]; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data, - sizeof(stipple) ); + DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, + sizeof(stipple)); - if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) ) + if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) return DRM_ERR(EFAULT); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); - radeon_cp_dispatch_stipple( dev, mask ); + radeon_cp_dispatch_stipple(dev, mask); COMMIT_RING(); return 0; } -static int radeon_cp_indirect( DRM_IOCTL_ARGS ) +static int radeon_cp_indirect(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2364,53 +2392,53 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS ) drm_radeon_indirect_t indirect; RING_LOCALS; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data, - sizeof(indirect) ); + DRM_COPY_FROM_USER_IOCTL(indirect, + (drm_radeon_indirect_t __user *) data, + sizeof(indirect)); - DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n", - indirect.idx, indirect.start, - indirect.end, indirect.discard ); + DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", + indirect.idx, indirect.start, indirect.end, indirect.discard); - if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - indirect.idx, dma->buf_count - 1 ); + if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + indirect.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } buf = dma->buflist[indirect.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", indirect.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", indirect.idx); return DRM_ERR(EINVAL); } - if ( indirect.start < buf->used ) { - DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n", - indirect.start, buf->used ); + if (indirect.start < buf->used) { + DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", + indirect.start, buf->used); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf->used = indirect.end; /* Wait for the 3D stream to idle before the indirect buffer * containing 2D acceleration commands is processed. */ - BEGIN_RING( 2 ); + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); @@ -2420,17 +2448,16 @@ static int radeon_cp_indirect( DRM_IOCTL_ARGS ) * X server. This is insecure and is thus only available to * privileged clients. */ - radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end ); + radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end); if (indirect.discard) { - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); } - COMMIT_RING(); return 0; } -static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) +static int radeon_cp_vertex2(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2442,65 +2469,64 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) int i; unsigned char laststate; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data, - sizeof(vertex) ); + DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, + sizeof(vertex)); - DRM_DEBUG( "pid=%d index=%d discard=%d\n", - DRM_CURRENTPID, - vertex.idx, vertex.discard ); + DRM_DEBUG("pid=%d index=%d discard=%d\n", + DRM_CURRENTPID, vertex.idx, vertex.discard); - if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - vertex.idx, dma->buf_count - 1 ); + if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + vertex.idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); buf = dma->buflist[vertex.idx]; - if ( buf->filp != filp ) { - DRM_ERROR( "process %d using buffer owned by %p\n", - DRM_CURRENTPID, buf->filp ); + if (buf->filp != filp) { + DRM_ERROR("process %d using buffer owned by %p\n", + DRM_CURRENTPID, buf->filp); return DRM_ERR(EINVAL); } - if ( buf->pending ) { - DRM_ERROR( "sending pending buffer %d\n", vertex.idx ); + if (buf->pending) { + DRM_ERROR("sending pending buffer %d\n", vertex.idx); return DRM_ERR(EINVAL); } - + if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) return DRM_ERR(EINVAL); - for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) { + for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { drm_radeon_prim_t prim; drm_radeon_tcl_prim_t tclprim; - - if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) ) + + if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) return DRM_ERR(EFAULT); - - if ( prim.stateidx != laststate ) { - drm_radeon_state_t state; - - if ( DRM_COPY_FROM_USER( &state, - &vertex.state[prim.stateidx], - sizeof(state) ) ) + + if (prim.stateidx != laststate) { + drm_radeon_state_t state; + + if (DRM_COPY_FROM_USER(&state, + &vertex.state[prim.stateidx], + sizeof(state))) return DRM_ERR(EFAULT); - if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) { - DRM_ERROR( "radeon_emit_state2 failed\n" ); - return DRM_ERR( EINVAL ); + if (radeon_emit_state2(dev_priv, filp_priv, &state)) { + DRM_ERROR("radeon_emit_state2 failed\n"); + return DRM_ERR(EINVAL); } laststate = prim.stateidx; @@ -2511,42 +2537,40 @@ static int radeon_cp_vertex2( DRM_IOCTL_ARGS ) tclprim.prim = prim.prim; tclprim.vc_format = prim.vc_format; - if ( prim.prim & RADEON_PRIM_WALK_IND ) { + if (prim.prim & RADEON_PRIM_WALK_IND) { tclprim.offset = prim.numverts * 64; - tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ + tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ - radeon_cp_dispatch_indices( dev, buf, &tclprim ); + radeon_cp_dispatch_indices(dev, buf, &tclprim); } else { tclprim.numverts = prim.numverts; - tclprim.offset = 0; /* not used */ + tclprim.offset = 0; /* not used */ - radeon_cp_dispatch_vertex( dev, buf, &tclprim ); + radeon_cp_dispatch_vertex(dev, buf, &tclprim); } - + if (sarea_priv->nbox == 1) sarea_priv->nbox = 0; } - if ( vertex.discard ) { - radeon_cp_discard_buffer( dev, buf ); + if (vertex.discard) { + radeon_cp_discard_buffer(dev, buf); } COMMIT_RING(); return 0; } - -static int radeon_emit_packets( - drm_radeon_private_t *dev_priv, - drm_file_t *filp_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static int radeon_emit_packets(drm_radeon_private_t * dev_priv, + drm_file_t * filp_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int id = (int)header.packet.packet_id; int sz, reg; int *data = (int *)cmdbuf->buf; RING_LOCALS; - + if (id >= RADEON_MAX_STATE_PACKETS) return DRM_ERR(EINVAL); @@ -2554,18 +2578,18 @@ static int radeon_emit_packets( reg = packet[id].start; if (sz * sizeof(int) > cmdbuf->bufsz) { - DRM_ERROR( "Packet size provided larger than data provided\n" ); + DRM_ERROR("Packet size provided larger than data provided\n"); return DRM_ERR(EINVAL); } - if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) { - DRM_ERROR( "Packet verification failed\n" ); - return DRM_ERR( EINVAL ); + if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { + DRM_ERROR("Packet verification failed\n"); + return DRM_ERR(EINVAL); } - BEGIN_RING(sz+1); - OUT_RING( CP_PACKET0( reg, (sz-1) ) ); - OUT_RING_TABLE( data, sz ); + BEGIN_RING(sz + 1); + OUT_RING(CP_PACKET0(reg, (sz - 1))); + OUT_RING_TABLE(data, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); @@ -2573,21 +2597,20 @@ static int radeon_emit_packets( return 0; } -static __inline__ int radeon_emit_scalars( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int start = header.scalars.offset; int stride = header.scalars.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_TABLE( cmdbuf->buf, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); + OUT_RING_TABLE(cmdbuf->buf, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); @@ -2596,42 +2619,40 @@ static __inline__ int radeon_emit_scalars( /* God this is ugly */ -static __inline__ int radeon_emit_scalars2( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int start = ((unsigned int)header.scalars.offset) + 0x100; int stride = header.scalars.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) ); - OUT_RING_TABLE( cmdbuf->buf, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); + OUT_RING_TABLE(cmdbuf->buf, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); cmdbuf->bufsz -= sz * sizeof(int); return 0; } -static __inline__ int radeon_emit_vectors( - drm_radeon_private_t *dev_priv, - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) +static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv, + drm_radeon_cmd_header_t header, + drm_radeon_cmd_buffer_t * cmdbuf) { int sz = header.vectors.count; int start = header.vectors.offset; int stride = header.vectors.stride; RING_LOCALS; - BEGIN_RING( 3+sz ); - OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) ); - OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); - OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) ); - OUT_RING_TABLE( cmdbuf->buf, sz ); + BEGIN_RING(3 + sz); + OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); + OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); + OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); + OUT_RING_TABLE(cmdbuf->buf, sz); ADVANCE_RING(); cmdbuf->buf += sz * sizeof(int); @@ -2639,10 +2660,9 @@ static __inline__ int radeon_emit_vectors( return 0; } - -static int radeon_emit_packet3( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf ) +static int radeon_emit_packet3(drm_device_t * dev, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int cmdsz; @@ -2651,14 +2671,14 @@ static int radeon_emit_packet3( drm_device_t *dev, DRM_DEBUG("\n"); - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); + if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + cmdbuf, &cmdsz))) { + DRM_ERROR("Packet verification failed\n"); return ret; } - BEGIN_RING( cmdsz ); - OUT_RING_TABLE( cmdbuf->buf, cmdsz ); + BEGIN_RING(cmdsz); + OUT_RING_TABLE(cmdbuf->buf, cmdsz); ADVANCE_RING(); cmdbuf->buf += cmdsz * 4; @@ -2666,11 +2686,10 @@ static int radeon_emit_packet3( drm_device_t *dev, return 0; } - -static int radeon_emit_packet3_cliprect( drm_device_t *dev, - drm_file_t *filp_priv, - drm_radeon_cmd_buffer_t *cmdbuf, - int orig_nbox ) +static int radeon_emit_packet3_cliprect(drm_device_t * dev, + drm_file_t * filp_priv, + drm_radeon_cmd_buffer_t * cmdbuf, + int orig_nbox) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_clip_rect_t box; @@ -2682,9 +2701,9 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, DRM_DEBUG("\n"); - if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv, - cmdbuf, &cmdsz ) ) ) { - DRM_ERROR( "Packet verification failed\n" ); + if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, + cmdbuf, &cmdsz))) { + DRM_ERROR("Packet verification failed\n"); return ret; } @@ -2692,8 +2711,8 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, goto out; do { - if ( i < cmdbuf->nbox ) { - if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) )) + if (i < cmdbuf->nbox) { + if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) return DRM_ERR(EFAULT); /* FIXME The second and subsequent times round * this loop, send a WAIT_UNTIL_3D_IDLE before @@ -2707,30 +2726,29 @@ static int radeon_emit_packet3_cliprect( drm_device_t *dev, * the correct place to fix it but this works * around it until I can figure that out - Tim * Smith */ - if ( i ) { - BEGIN_RING( 2 ); + if (i) { + BEGIN_RING(2); RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); } - radeon_emit_clip_rect( dev_priv, &box ); + radeon_emit_clip_rect(dev_priv, &box); } - - BEGIN_RING( cmdsz ); - OUT_RING_TABLE( cmdbuf->buf, cmdsz ); + + BEGIN_RING(cmdsz); + OUT_RING_TABLE(cmdbuf->buf, cmdsz); ADVANCE_RING(); - } while ( ++i < cmdbuf->nbox ); - if (cmdbuf->nbox == 1) + } while (++i < cmdbuf->nbox); + if (cmdbuf->nbox == 1) cmdbuf->nbox = 0; - out: + out: cmdbuf->buf += cmdsz * 4; cmdbuf->bufsz -= cmdsz * 4; return 0; } - -static int radeon_emit_wait( drm_device_t *dev, int flags ) +static int radeon_emit_wait(drm_device_t * dev, int flags) { drm_radeon_private_t *dev_priv = dev->dev_private; RING_LOCALS; @@ -2738,18 +2756,18 @@ static int radeon_emit_wait( drm_device_t *dev, int flags ) DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); switch (flags) { case RADEON_WAIT_2D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_2D_IDLE(); + BEGIN_RING(2); + RADEON_WAIT_UNTIL_2D_IDLE(); ADVANCE_RING(); break; case RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_3D_IDLE(); + BEGIN_RING(2); + RADEON_WAIT_UNTIL_3D_IDLE(); ADVANCE_RING(); break; - case RADEON_WAIT_2D|RADEON_WAIT_3D: - BEGIN_RING( 2 ); - RADEON_WAIT_UNTIL_IDLE(); + case RADEON_WAIT_2D | RADEON_WAIT_3D: + BEGIN_RING(2); + RADEON_WAIT_UNTIL_IDLE(); ADVANCE_RING(); break; default: @@ -2759,7 +2777,7 @@ static int radeon_emit_wait( drm_device_t *dev, int flags ) return 0; } -static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) +static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2770,24 +2788,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) drm_radeon_cmd_buffer_t cmdbuf; drm_radeon_cmd_header_t header; int orig_nbox, orig_bufsz; - char *kbuf=NULL; + char *kbuf = NULL; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data, - sizeof(cmdbuf) ); + DRM_COPY_FROM_USER_IOCTL(cmdbuf, + (drm_radeon_cmd_buffer_t __user *) data, + sizeof(cmdbuf)); - RING_SPACE_TEST_WITH_RETURN( dev_priv ); - VB_AGE_TEST_WITH_RETURN( dev_priv ); + RING_SPACE_TEST_WITH_RETURN(dev_priv); + VB_AGE_TEST_WITH_RETURN(dev_priv); - if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) { + if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { return DRM_ERR(EINVAL); } @@ -2809,27 +2828,28 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) orig_nbox = cmdbuf.nbox; - if(dev_priv->microcode_version == UCODE_R300) { + if (dev_priv->microcode_version == UCODE_R300) { int temp; - temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); - + temp = r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); + if (orig_bufsz != 0) drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); - + return temp; } /* microcode_version != r300 */ - while ( cmdbuf.bufsz >= sizeof(header) ) { + while (cmdbuf.bufsz >= sizeof(header)) { header.i = *(int *)cmdbuf.buf; cmdbuf.buf += sizeof(header); cmdbuf.bufsz -= sizeof(header); switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: + case RADEON_CMD_PACKET: DRM_DEBUG("RADEON_CMD_PACKET\n"); - if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) { + if (radeon_emit_packets + (dev_priv, filp_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_packets failed\n"); goto err; } @@ -2837,7 +2857,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_SCALARS: DRM_DEBUG("RADEON_CMD_SCALARS\n"); - if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) { + if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_scalars failed\n"); goto err; } @@ -2845,7 +2865,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_VECTORS: DRM_DEBUG("RADEON_CMD_VECTORS\n"); - if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) { + if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_vectors failed\n"); goto err; } @@ -2854,25 +2874,25 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_DMA_DISCARD: DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); idx = header.dma.buf_idx; - if ( idx < 0 || idx >= dma->buf_count ) { - DRM_ERROR( "buffer index %d (of %d max)\n", - idx, dma->buf_count - 1 ); + if (idx < 0 || idx >= dma->buf_count) { + DRM_ERROR("buffer index %d (of %d max)\n", + idx, dma->buf_count - 1); goto err; } buf = dma->buflist[idx]; - if ( buf->filp != filp || buf->pending ) { - DRM_ERROR( "bad buffer %p %p %d\n", - buf->filp, filp, buf->pending); + if (buf->filp != filp || buf->pending) { + DRM_ERROR("bad buffer %p %p %d\n", + buf->filp, filp, buf->pending); goto err; } - radeon_cp_discard_buffer( dev, buf ); + radeon_cp_discard_buffer(dev, buf); break; case RADEON_CMD_PACKET3: DRM_DEBUG("RADEON_CMD_PACKET3\n"); - if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) { + if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) { DRM_ERROR("radeon_emit_packet3 failed\n"); goto err; } @@ -2880,7 +2900,8 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_PACKET3_CLIP: DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); - if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) { + if (radeon_emit_packet3_cliprect + (dev, filp_priv, &cmdbuf, orig_nbox)) { DRM_ERROR("radeon_emit_packet3_clip failed\n"); goto err; } @@ -2888,7 +2909,7 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_SCALARS2: DRM_DEBUG("RADEON_CMD_SCALARS2\n"); - if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) { + if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) { DRM_ERROR("radeon_emit_scalars2 failed\n"); goto err; } @@ -2896,13 +2917,13 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) case RADEON_CMD_WAIT: DRM_DEBUG("RADEON_CMD_WAIT\n"); - if (radeon_emit_wait( dev, header.wait.flags )) { + if (radeon_emit_wait(dev, header.wait.flags)) { DRM_ERROR("radeon_emit_wait failed\n"); goto err; } break; default: - DRM_ERROR("bad cmd_type %d at %p\n", + DRM_ERROR("bad cmd_type %d at %p\n", header.header.cmd_type, cmdbuf.buf - sizeof(header)); goto err; @@ -2916,45 +2937,43 @@ static int radeon_cp_cmdbuf( DRM_IOCTL_ARGS ) COMMIT_RING(); return 0; -err: + err: if (orig_bufsz != 0) drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); return DRM_ERR(EINVAL); } - - -static int radeon_cp_getparam( DRM_IOCTL_ARGS ) +static int radeon_cp_getparam(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_getparam_t param; int value; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); return DRM_ERR(EINVAL); } - DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data, - sizeof(param) ); + DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, + sizeof(param)); - DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); + DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); - switch( param.param ) { + switch (param.param) { case RADEON_PARAM_GART_BUFFER_OFFSET: value = dev_priv->gart_buffers_offset; break; case RADEON_PARAM_LAST_FRAME: dev_priv->stats.last_frame_reads++; - value = GET_SCRATCH( 0 ); + value = GET_SCRATCH(0); break; case RADEON_PARAM_LAST_DISPATCH: - value = GET_SCRATCH( 1 ); + value = GET_SCRATCH(1); break; case RADEON_PARAM_LAST_CLEAR: dev_priv->stats.last_clear_reads++; - value = GET_SCRATCH( 2 ); + value = GET_SCRATCH(2); break; case RADEON_PARAM_IRQ_NR: value = dev->irq; @@ -2969,15 +2988,15 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS ) value = dev_priv->ring_rptr_offset; break; #if BITS_PER_LONG == 32 - /* - * This ioctl() doesn't work on 64-bit platforms because hw_lock is a - * pointer which can't fit into an int-sized variable. According to - * Michel Dänzer, the ioctl() is only used on embedded platforms, so - * not supporting it shouldn't be a problem. If the same functionality - * is needed on 64-bit platforms, a new ioctl() would have to be added, - * so backwards-compatibility for the embedded platforms can be - * maintained. --davidm 4-Feb-2004. - */ + /* + * This ioctl() doesn't work on 64-bit platforms because hw_lock is a + * pointer which can't fit into an int-sized variable. According to + * Michel Dänzer, the ioctl() is only used on embedded platforms, so + * not supporting it shouldn't be a problem. If the same functionality + * is needed on 64-bit platforms, a new ioctl() would have to be added, + * so backwards-compatibility for the embedded platforms can be + * maintained. --davidm 4-Feb-2004. + */ case RADEON_PARAM_SAREA_HANDLE: /* The lock is the first dword in the sarea. */ value = (long)dev->lock.hw_lock; @@ -2990,56 +3009,56 @@ static int radeon_cp_getparam( DRM_IOCTL_ARGS ) return DRM_ERR(EINVAL); } - if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) { - DRM_ERROR( "copy_to_user\n" ); + if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { + DRM_ERROR("copy_to_user\n"); return DRM_ERR(EFAULT); } - + return 0; } -static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { +static int radeon_cp_setparam(DRM_IOCTL_ARGS) +{ DRM_DEVICE; drm_radeon_private_t *dev_priv = dev->dev_private; drm_file_t *filp_priv; drm_radeon_setparam_t sp; struct drm_radeon_driver_file_fields *radeon_priv; - if ( !dev_priv ) { - DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); - return DRM_ERR( EINVAL ); + if (!dev_priv) { + DRM_ERROR("%s called with no initialization\n", __FUNCTION__); + return DRM_ERR(EINVAL); } - DRM_GET_PRIV_WITH_RETURN( filp_priv, filp ); + DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); - DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data, - sizeof( sp ) ); + DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, + sizeof(sp)); - switch( sp.param ) { + switch (sp.param) { case RADEON_SETPARAM_FB_LOCATION: radeon_priv = filp_priv->driver_priv; radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; break; case RADEON_SETPARAM_SWITCH_TILING: if (sp.value == 0) { - DRM_DEBUG( "color tiling disabled\n" ); + DRM_DEBUG("color tiling disabled\n"); dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; dev_priv->sarea_priv->tiling_enabled = 0; - } - else if (sp.value == 1) { - DRM_DEBUG( "color tiling enabled\n" ); + } else if (sp.value == 1) { + DRM_DEBUG("color tiling enabled\n"); dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; dev_priv->sarea_priv->tiling_enabled = 1; } - break; + break; case RADEON_SETPARAM_PCIGART_LOCATION: dev_priv->pcigart_offset = sp.value; break; default: - DRM_DEBUG( "Invalid parameter %d\n", sp.param ); - return DRM_ERR( EINVAL ); + DRM_DEBUG("Invalid parameter %d\n", sp.param); + return DRM_ERR(EINVAL); } return 0; @@ -3051,78 +3070,106 @@ static int radeon_cp_setparam( DRM_IOCTL_ARGS ) { * * DRM infrastructure takes care of reclaiming dma buffers. */ -void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp) +void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp) { - if ( dev->dev_private ) { - drm_radeon_private_t *dev_priv = dev->dev_private; - if ( dev_priv->page_flipping ) { - radeon_do_cleanup_pageflip( dev ); - } - radeon_mem_release( filp, dev_priv->gart_heap ); - radeon_mem_release( filp, dev_priv->fb_heap ); + if (dev->dev_private) { + drm_radeon_private_t *dev_priv = dev->dev_private; + if (dev_priv->page_flipping) { + radeon_do_cleanup_pageflip(dev); + } + radeon_mem_release(filp, dev_priv->gart_heap); + radeon_mem_release(filp, dev_priv->fb_heap); radeon_surfaces_release(filp, dev_priv); - } + } } -void radeon_driver_pretakedown(drm_device_t *dev) +void radeon_driver_pretakedown(drm_device_t * dev) { radeon_do_release(dev); } -int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv) +int radeon_driver_open_helper(drm_device_t * dev, drm_file_t * filp_priv) { drm_radeon_private_t *dev_priv = dev->dev_private; struct drm_radeon_driver_file_fields *radeon_priv; - - radeon_priv = (struct drm_radeon_driver_file_fields *)drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); - + + radeon_priv = + (struct drm_radeon_driver_file_fields *) + drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); + if (!radeon_priv) return -ENOMEM; filp_priv->driver_priv = radeon_priv; - if ( dev_priv ) + if (dev_priv) radeon_priv->radeon_fb_delta = dev_priv->fb_location; else radeon_priv->radeon_fb_delta = 0; return 0; } - -void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv) +void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv) { - struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv; - - drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); + struct drm_radeon_driver_file_fields *radeon_priv = + filp_priv->driver_priv; + + drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); } drm_ioctl_desc_t radeon_ioctls[] = { - [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = { radeon_cp_init, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = { radeon_cp_start, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = { radeon_cp_stop, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = { radeon_cp_reset, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = { radeon_cp_idle, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = { radeon_cp_resume, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = { radeon_cp_clear, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = { radeon_cp_vertex, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = { radeon_cp_indices, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = { radeon_cp_texture, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = { radeon_cp_stipple, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = { radeon_cp_indirect, 1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = { radeon_cp_vertex2, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = { radeon_cp_cmdbuf, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = { radeon_cp_getparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = { radeon_cp_flip, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = { radeon_mem_alloc, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_FREE)] = { radeon_mem_free, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = { radeon_mem_init_heap,1, 1 }, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = { radeon_irq_emit, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = { radeon_irq_wait, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = { radeon_cp_setparam, 1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = { radeon_surface_alloc,1, 0 }, - [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = { radeon_surface_free, 1, 0 } + [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1} + , + [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0} + , + [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0} }; int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); diff --git a/drivers/char/drm/savage_bci.c b/drivers/char/drm/savage_bci.c index 2fd40bac7c9..0ad9201af8b 100644 --- a/drivers/char/drm/savage_bci.c +++ b/drivers/char/drm/savage_bci.c @@ -28,12 +28,12 @@ /* Need a long timeout for shadow status updates can take a while * and so can waiting for events when the queue is full. */ -#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ -#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ +#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ +#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ #define SAVAGE_FREELIST_DEBUG 0 static int -savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) +savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n) { uint32_t mask = dev_priv->status_used_mask; uint32_t threshold = dev_priv->bci_threshold_hi; @@ -62,7 +62,7 @@ savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) } static int -savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) +savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n) { uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; uint32_t status; @@ -83,7 +83,7 @@ savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) } static int -savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) +savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n) { uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; uint32_t status; @@ -115,7 +115,7 @@ savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) * rule. Otherwise there may be glitches every 2^16 events. */ static int -savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) +savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e) { uint32_t status; int i; @@ -138,7 +138,7 @@ savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) } static int -savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) +savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e) { uint32_t status; int i; @@ -159,7 +159,7 @@ savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) return DRM_ERR(EBUSY); } -uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, +uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, unsigned int flags) { uint16_t count; @@ -175,12 +175,12 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, } count = (count + 1) & 0xffff; if (count == 0) { - count++; /* See the comment above savage_wait_event_*. */ + count++; /* See the comment above savage_wait_event_*. */ dev_priv->event_wrap++; } dev_priv->event_counter = count; if (dev_priv->status_ptr) - dev_priv->status_ptr[1023] = (uint32_t)count; + dev_priv->status_ptr[1023] = (uint32_t) count; if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { unsigned int wait_cmd = BCI_CMD_WAIT; @@ -193,7 +193,7 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, } else { BEGIN_BCI(1); } - BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count); + BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count); return count; } @@ -201,7 +201,7 @@ uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, /* * Freelist management */ -static int savage_freelist_init(drm_device_t *dev) +static int savage_freelist_init(drm_device_t * dev) { drm_savage_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; @@ -234,7 +234,7 @@ static int savage_freelist_init(drm_device_t *dev) return 0; } -static drm_buf_t *savage_freelist_get(drm_device_t *dev) +static drm_buf_t *savage_freelist_get(drm_device_t * dev) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *tail = dev_priv->tail.prev; @@ -249,7 +249,7 @@ static drm_buf_t *savage_freelist_get(drm_device_t *dev) event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; wrap = dev_priv->event_wrap; if (event > dev_priv->event_counter) - wrap--; /* hardware hasn't passed the last wrap yet */ + wrap--; /* hardware hasn't passed the last wrap yet */ DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); DRM_DEBUG(" head=0x%04x %d\n", event, wrap); @@ -267,7 +267,7 @@ static drm_buf_t *savage_freelist_get(drm_device_t *dev) return NULL; } -void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf) +void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf) { drm_savage_private_t *dev_priv = dev->dev_private; drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; @@ -290,15 +290,14 @@ void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf) /* * Command DMA */ -static int savage_dma_init(drm_savage_private_t *dev_priv) +static int savage_dma_init(drm_savage_private_t * dev_priv) { unsigned int i; dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / - (SAVAGE_DMA_PAGE_SIZE*4); + (SAVAGE_DMA_PAGE_SIZE * 4); dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * - dev_priv->nr_dma_pages, - DRM_MEM_DRIVER); + dev_priv->nr_dma_pages, DRM_MEM_DRIVER); if (dev_priv->dma_pages == NULL) return DRM_ERR(ENOMEM); @@ -315,7 +314,7 @@ static int savage_dma_init(drm_savage_private_t *dev_priv) return 0; } -void savage_dma_reset(drm_savage_private_t *dev_priv) +void savage_dma_reset(drm_savage_private_t * dev_priv) { uint16_t event; unsigned int wrap, i; @@ -330,7 +329,7 @@ void savage_dma_reset(drm_savage_private_t *dev_priv) dev_priv->first_dma_page = dev_priv->current_dma_page = 0; } -void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) +void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page) { uint16_t event; unsigned int wrap; @@ -346,7 +345,7 @@ void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; wrap = dev_priv->event_wrap; if (event > dev_priv->event_counter) - wrap--; /* hardware hasn't passed the last wrap yet */ + wrap--; /* hardware hasn't passed the last wrap yet */ if (dev_priv->dma_pages[page].age.wrap > wrap || (dev_priv->dma_pages[page].age.wrap == wrap && @@ -358,13 +357,13 @@ void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) } } -uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) +uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n) { unsigned int cur = dev_priv->current_dma_page; unsigned int rest = SAVAGE_DMA_PAGE_SIZE - - dev_priv->dma_pages[cur].used; - unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE-1) / - SAVAGE_DMA_PAGE_SIZE; + dev_priv->dma_pages[cur].used; + unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / + SAVAGE_DMA_PAGE_SIZE; uint32_t *dma_ptr; unsigned int i; @@ -372,9 +371,8 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); if (cur + nr_pages < dev_priv->nr_dma_pages) { - dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - cur*SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[cur].used; + dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + + cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; if (n < rest) rest = n; dev_priv->dma_pages[cur].used += rest; @@ -382,13 +380,14 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) cur++; } else { dev_priv->dma_flush(dev_priv); - nr_pages = (n + SAVAGE_DMA_PAGE_SIZE-1) / SAVAGE_DMA_PAGE_SIZE; + nr_pages = + (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; for (i = cur; i < dev_priv->nr_dma_pages; ++i) { dev_priv->dma_pages[i].age = dev_priv->last_dma_age; dev_priv->dma_pages[i].used = 0; dev_priv->dma_pages[i].flushed = 0; } - dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle; + dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle; dev_priv->first_dma_page = cur = 0; } for (i = cur; nr_pages > 0; ++i, --nr_pages) { @@ -414,7 +413,7 @@ uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) return dma_ptr; } -static void savage_dma_flush(drm_savage_private_t *dev_priv) +static void savage_dma_flush(drm_savage_private_t * dev_priv) { unsigned int first = dev_priv->first_dma_page; unsigned int cur = dev_priv->current_dma_page; @@ -439,11 +438,10 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv) /* pad with noops */ if (pad) { - uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - cur * SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[cur].used; + uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + + cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; dev_priv->dma_pages[cur].used += pad; - while(pad != 0) { + while (pad != 0) { *dma_ptr++ = BCI_CMD_WAIT; pad--; } @@ -453,11 +451,10 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv) /* do flush ... */ phys_addr = dev_priv->cmd_dma->offset + - (first * SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[first].flushed) * 4; + (first * SAVAGE_DMA_PAGE_SIZE + + dev_priv->dma_pages[first].flushed) * 4; len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + - dev_priv->dma_pages[cur].used - - dev_priv->dma_pages[first].flushed; + dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; DRM_DEBUG("phys_addr=%lx, len=%u\n", phys_addr | dev_priv->dma_type, len); @@ -499,7 +496,7 @@ static void savage_dma_flush(drm_savage_private_t *dev_priv) dev_priv->dma_pages[cur].flushed); } -static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) +static void savage_fake_dma_flush(drm_savage_private_t * dev_priv) { unsigned int i, j; BCI_LOCALS; @@ -515,8 +512,8 @@ static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) for (i = dev_priv->first_dma_page; i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; ++i) { - uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + - i * SAVAGE_DMA_PAGE_SIZE; + uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle + + i * SAVAGE_DMA_PAGE_SIZE; #if SAVAGE_DMA_DEBUG /* Sanity check: all pages except the last one must be full. */ if (i < dev_priv->current_dma_page && @@ -543,7 +540,7 @@ static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) * initialized. We also need to take care of deleting the MTRRs in * postcleanup. */ -int savage_preinit(drm_device_t *dev, unsigned long chipset) +int savage_preinit(drm_device_t * dev, unsigned long chipset) { drm_savage_private_t *dev_priv; unsigned long mmio_base, fb_base, fb_size, aperture_base; @@ -578,19 +575,22 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset) * MTRRs. */ dev_priv->mtrr[0].base = fb_base; dev_priv->mtrr[0].size = 0x01000000; - dev_priv->mtrr[0].handle = mtrr_add( - dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, - MTRR_TYPE_WRCOMB, 1); - dev_priv->mtrr[1].base = fb_base+0x02000000; + dev_priv->mtrr[0].handle = + mtrr_add(dev_priv->mtrr[0].base, + dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB, + 1); + dev_priv->mtrr[1].base = fb_base + 0x02000000; dev_priv->mtrr[1].size = 0x02000000; - dev_priv->mtrr[1].handle = mtrr_add( - dev_priv->mtrr[1].base, dev_priv->mtrr[1].size, - MTRR_TYPE_WRCOMB, 1); - dev_priv->mtrr[2].base = fb_base+0x04000000; + dev_priv->mtrr[1].handle = + mtrr_add(dev_priv->mtrr[1].base, + dev_priv->mtrr[1].size, MTRR_TYPE_WRCOMB, + 1); + dev_priv->mtrr[2].base = fb_base + 0x04000000; dev_priv->mtrr[2].size = 0x04000000; - dev_priv->mtrr[2].handle = mtrr_add( - dev_priv->mtrr[2].base, dev_priv->mtrr[2].size, - MTRR_TYPE_WRCOMB, 1); + dev_priv->mtrr[2].handle = + mtrr_add(dev_priv->mtrr[2].base, + dev_priv->mtrr[2].size, MTRR_TYPE_WRCOMB, + 1); } else { DRM_ERROR("strange pci_resource_len %08lx\n", drm_get_resource_len(dev, 0)); @@ -608,9 +608,10 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset) * aperture. */ dev_priv->mtrr[0].base = fb_base; dev_priv->mtrr[0].size = 0x08000000; - dev_priv->mtrr[0].handle = mtrr_add( - dev_priv->mtrr[0].base, dev_priv->mtrr[0].size, - MTRR_TYPE_WRCOMB, 1); + dev_priv->mtrr[0].handle = + mtrr_add(dev_priv->mtrr[0].base, + dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB, + 1); } else { DRM_ERROR("strange pci_resource_len %08lx\n", drm_get_resource_len(dev, 1)); @@ -647,7 +648,7 @@ int savage_preinit(drm_device_t *dev, unsigned long chipset) /* * Delete MTRRs and free device-private data. */ -int savage_postcleanup(drm_device_t *dev) +int savage_postcleanup(drm_device_t * dev) { drm_savage_private_t *dev_priv = dev->dev_private; int i; @@ -663,7 +664,7 @@ int savage_postcleanup(drm_device_t *dev) return 0; } -static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) +static int savage_do_init_bci(drm_device_t * dev, drm_savage_init_t * init) { drm_savage_private_t *dev_priv = dev->dev_private; @@ -731,7 +732,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) } if (init->agp_textures_offset) { dev_priv->agp_textures = - drm_core_findmap(dev, init->agp_textures_offset); + drm_core_findmap(dev, init->agp_textures_offset); if (!dev_priv->agp_textures) { DRM_ERROR("could not find agp texture region!\n"); savage_do_cleanup_bci(dev); @@ -802,8 +803,8 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) } dev_priv->sarea_priv = - (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->handle + - init->sarea_priv_offset); + (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle + + init->sarea_priv_offset); /* setup bitmap descriptors */ { @@ -812,35 +813,36 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) unsigned int front_stride, back_stride, depth_stride; if (dev_priv->chipset <= S3_SAVAGE4) { color_tile_format = dev_priv->fb_bpp == 16 ? - SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; + SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; depth_tile_format = dev_priv->depth_bpp == 16 ? - SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; + SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; } else { color_tile_format = SAVAGE_BD_TILE_DEST; depth_tile_format = SAVAGE_BD_TILE_DEST; } - front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp/8); - back_stride = dev_priv-> back_pitch / (dev_priv->fb_bpp/8); - depth_stride = dev_priv->depth_pitch / (dev_priv->depth_bpp/8); + front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); + back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); + depth_stride = + dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | - (color_tile_format << SAVAGE_BD_TILE_SHIFT); + (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | + (color_tile_format << SAVAGE_BD_TILE_SHIFT); - dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | - (color_tile_format << SAVAGE_BD_TILE_SHIFT); + dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE | + (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | + (color_tile_format << SAVAGE_BD_TILE_SHIFT); dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | - (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | - (depth_tile_format << SAVAGE_BD_TILE_SHIFT); + (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | + (depth_tile_format << SAVAGE_BD_TILE_SHIFT); } /* setup status and bci ptr */ dev_priv->event_counter = 0; dev_priv->event_wrap = 0; dev_priv->bci_ptr = (volatile uint32_t *) - ((uint8_t *)dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); + ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET); if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; } else { @@ -848,7 +850,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) } if (dev_priv->status != NULL) { dev_priv->status_ptr = - (volatile uint32_t *)dev_priv->status->handle; + (volatile uint32_t *)dev_priv->status->handle; dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; dev_priv->wait_evnt = savage_bci_wait_event_shadow; dev_priv->status_ptr[1023] = dev_priv->event_counter; @@ -874,7 +876,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) return DRM_ERR(ENOMEM); } - if (savage_dma_init(dev_priv) < 0) { + if (savage_dma_init(dev_priv) < 0) { DRM_ERROR("could not initialize command DMA\n"); savage_do_cleanup_bci(dev); return DRM_ERR(ENOMEM); @@ -883,7 +885,7 @@ static int savage_do_init_bci(drm_device_t *dev, drm_savage_init_t *init) return 0; } -int savage_do_cleanup_bci(drm_device_t *dev) +int savage_do_cleanup_bci(drm_device_t * dev) { drm_savage_private_t *dev_priv = dev->dev_private; @@ -907,7 +909,7 @@ int savage_do_cleanup_bci(drm_device_t *dev) if (dev_priv->dma_pages) drm_free(dev_priv->dma_pages, - sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages, + sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages, DRM_MEM_DRIVER); return 0; @@ -920,7 +922,7 @@ static int savage_bci_init(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *)data, + DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data, sizeof(init)); switch (init.func) { @@ -943,13 +945,13 @@ static int savage_bci_event_emit(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *)data, + DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data, sizeof(event)); event.count = savage_bci_emit_event(dev_priv, event.flags); event.count |= dev_priv->event_wrap << 16; - DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *)data)->count, - event.count, sizeof(event.count)); + DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *) data)-> + count, event.count, sizeof(event.count)); return 0; } @@ -963,7 +965,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) DRM_DEBUG("\n"); - DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *)data, + DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data, sizeof(event)); UPDATE_EVENT_COUNTER(); @@ -973,7 +975,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; hw_w = dev_priv->event_wrap; if (hw_e > dev_priv->event_counter) - hw_w--; /* hardware hasn't passed the last wrap yet */ + hw_w--; /* hardware hasn't passed the last wrap yet */ event_e = event.count & 0xffff; event_w = event.count >> 16; @@ -982,7 +984,7 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) * - event counter wrapped since the event was emitted or * - the hardware has advanced up to or over the event to wait for. */ - if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e) ) + if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) return 0; else return dev_priv->wait_evnt(dev_priv, event_e); @@ -992,7 +994,8 @@ static int savage_bci_event_wait(DRM_IOCTL_ARGS) * DMA buffer management */ -static int savage_bci_get_buffers(DRMFILE filp, drm_device_t *dev, drm_dma_t *d) +static int savage_bci_get_buffers(DRMFILE filp, drm_device_t * dev, + drm_dma_t * d) { drm_buf_t *buf; int i; @@ -1025,7 +1028,7 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *)data, sizeof(d)); + DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *) data, sizeof(d)); /* Please don't send us buffers. */ @@ -1049,12 +1052,13 @@ int savage_bci_buffers(DRM_IOCTL_ARGS) ret = savage_bci_get_buffers(filp, dev, &d); } - DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *)data, d, sizeof(d)); + DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *) data, d, sizeof(d)); return ret; } -void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) { +void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp) +{ drm_device_dma_t *dma = dev->dma; drm_savage_private_t *dev_priv = dev->dev_private; int i; @@ -1066,7 +1070,7 @@ void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) { if (!dma->buflist) return; - /*i830_flush_queue(dev);*/ + /*i830_flush_queue(dev); */ for (i = 0; i < dma->buf_count; i++) { drm_buf_t *buf = dma->buflist[i]; @@ -1085,12 +1089,15 @@ void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp) { drm_core_reclaim_buffers(dev, filp); } - drm_ioctl_desc_t savage_ioctls[] = { - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0}, - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1} + , + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0} + , + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0} + , + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0} + , }; int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); diff --git a/drivers/char/drm/savage_drm.h b/drivers/char/drm/savage_drm.h index 6526c9aa758..e1148e8e799 100644 --- a/drivers/char/drm/savage_drm.h +++ b/drivers/char/drm/savage_drm.h @@ -42,12 +42,13 @@ #define SAVAGE_NR_TEX_REGIONS 16 #define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 -#endif /* __SAVAGE_SAREA_DEFINES__ */ +#endif /* __SAVAGE_SAREA_DEFINES__ */ typedef struct _drm_savage_sarea { /* LRU lists for texture memory in agp space and on the card. */ - drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1]; + drm_tex_region_t texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + + 1]; unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; /* Mechanism to validate card state. @@ -101,24 +102,24 @@ typedef struct drm_savage_init { typedef union drm_savage_cmd_header drm_savage_cmd_header_t; typedef struct drm_savage_cmdbuf { - /* command buffer in client's address space */ + /* command buffer in client's address space */ drm_savage_cmd_header_t __user *cmd_addr; unsigned int size; /* size of the command buffer in 64bit units */ unsigned int dma_idx; /* DMA buffer index to use */ int discard; /* discard DMA buffer when done */ - /* vertex buffer in client's address space */ + /* vertex buffer in client's address space */ unsigned int __user *vb_addr; unsigned int vb_size; /* size of client vertex buffer in bytes */ unsigned int vb_stride; /* stride of vertices in 32bit words */ - /* boxes in client's address space */ + /* boxes in client's address space */ drm_clip_rect_t __user *box_addr; unsigned int nbox; /* number of clipping boxes */ } drm_savage_cmdbuf_t; -#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ -#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ -#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ +#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ +#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ +#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ typedef struct drm_savage_event { unsigned int count; unsigned int flags; @@ -126,21 +127,21 @@ typedef struct drm_savage_event { /* Commands for the cmdbuf ioctl */ -#define SAVAGE_CMD_STATE 0 /* a range of state registers */ -#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ -#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ -#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ -#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ -#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ -#define SAVAGE_CMD_SWAP 6 /* swap buffers */ +#define SAVAGE_CMD_STATE 0 /* a range of state registers */ +#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ +#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ +#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ +#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ +#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ +#define SAVAGE_CMD_SWAP 6 /* swap buffers */ /* Primitive types */ -#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ -#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ -#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ -#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat - * shading on s3d */ +#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ +#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ +#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ +#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat + * shading on s3d */ /* Skip flags (vertex format) */ @@ -172,38 +173,38 @@ union drm_savage_cmd_header { unsigned short pad1; unsigned short pad2; unsigned short pad3; - } cmd; /* generic */ + } cmd; /* generic */ struct { unsigned char cmd; unsigned char global; /* need idle engine? */ unsigned short count; /* number of consecutive registers */ unsigned short start; /* first register */ unsigned short pad3; - } state; /* SAVAGE_CMD_STATE */ + } state; /* SAVAGE_CMD_STATE */ struct { unsigned char cmd; unsigned char prim; /* primitive type */ unsigned short skip; /* vertex format (skip flags) */ unsigned short count; /* number of vertices */ unsigned short start; /* first vertex in DMA/vertex buffer */ - } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ + } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ struct { unsigned char cmd; unsigned char prim; unsigned short skip; unsigned short count; /* number of indices that follow */ unsigned short pad3; - } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ + } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ struct { unsigned char cmd; unsigned char pad0; unsigned short pad1; unsigned int flags; - } clear0; /* SAVAGE_CMD_CLEAR */ + } clear0; /* SAVAGE_CMD_CLEAR */ struct { unsigned int mask; unsigned int value; - } clear1; /* SAVAGE_CMD_CLEAR data */ + } clear1; /* SAVAGE_CMD_CLEAR data */ }; #endif diff --git a/drivers/char/drm/savage_drv.c b/drivers/char/drm/savage_drv.c index ac8d270427c..0906f9a5d8f 100644 --- a/drivers/char/drm/savage_drv.c +++ b/drivers/char/drm/savage_drv.c @@ -30,30 +30,28 @@ #include "drm_pciids.h" -static int postinit( struct drm_device *dev, unsigned long flags ) +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -66,8 +64,7 @@ extern int savage_max_ioctl; static struct drm_driver driver = { .driver_features = - DRIVER_USE_AGP | DRIVER_USE_MTRR | - DRIVER_HAVE_DMA | DRIVER_PCI_DMA, + DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_PCI_DMA, .dev_priv_size = sizeof(drm_savage_buf_priv_t), .preinit = savage_preinit, .postinit = postinit, @@ -79,18 +76,19 @@ static struct drm_driver driver = { .ioctls = savage_ioctls, .dma_ioctl = savage_bci_buffers, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + } + , .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init savage_init(void) @@ -107,6 +105,6 @@ static void __exit savage_exit(void) module_init(savage_init); module_exit(savage_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/savage_drv.h b/drivers/char/drm/savage_drv.h index a4543494465..358f4fb2712 100644 --- a/drivers/char/drm/savage_drv.h +++ b/drivers/char/drm/savage_drv.h @@ -65,7 +65,7 @@ typedef struct drm_savage_dma_page { drm_savage_age_t age; unsigned int used, flushed; } drm_savage_dma_page_t; -#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ +#define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command * size of 16kbytes or 4k entries. Minimum requirement would be * 10kbytes for 255 40-byte vertices in one drawing command. */ @@ -184,13 +184,13 @@ typedef struct drm_savage_private { unsigned int waiting; /* config/hardware-dependent function pointers */ - int (*wait_fifo)(struct drm_savage_private *dev_priv, unsigned int n); - int (*wait_evnt)(struct drm_savage_private *dev_priv, uint16_t e); + int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); + int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); /* Err, there is a macro wait_event in include/linux/wait.h. * Avoid unwanted macro expansion. */ - void (*emit_clip_rect)(struct drm_savage_private *dev_priv, - drm_clip_rect_t *pbox); - void (*dma_flush)(struct drm_savage_private *dev_priv); + void (*emit_clip_rect) (struct drm_savage_private * dev_priv, + drm_clip_rect_t * pbox); + void (*dma_flush) (struct drm_savage_private * dev_priv); } drm_savage_private_t; /* ioctls */ @@ -198,23 +198,23 @@ extern int savage_bci_cmdbuf(DRM_IOCTL_ARGS); extern int savage_bci_buffers(DRM_IOCTL_ARGS); /* BCI functions */ -extern uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, +extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, unsigned int flags); -extern void savage_freelist_put(drm_device_t *dev, drm_buf_t *buf); -extern void savage_dma_reset(drm_savage_private_t *dev_priv); -extern void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page); -extern uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, +extern void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf); +extern void savage_dma_reset(drm_savage_private_t * dev_priv); +extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); +extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n); -extern int savage_preinit(drm_device_t *dev, unsigned long chipset); -extern int savage_postcleanup(drm_device_t *dev); -extern int savage_do_cleanup_bci(drm_device_t *dev); -extern void savage_reclaim_buffers(drm_device_t *dev, DRMFILE filp); +extern int savage_preinit(drm_device_t * dev, unsigned long chipset); +extern int savage_postcleanup(drm_device_t * dev); +extern int savage_do_cleanup_bci(drm_device_t * dev); +extern void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp); /* state functions */ -extern void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - drm_clip_rect_t *pbox); -extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - drm_clip_rect_t *pbox); +extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, + drm_clip_rect_t * pbox); +extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, + drm_clip_rect_t * pbox); #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ @@ -222,10 +222,10 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ -#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region +#define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region * inside the MMIO region */ -#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip - * BCI FIFO */ +#define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip + * BCI FIFO */ /* * MMIO registers @@ -278,7 +278,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define SAVAGE_TEXADDR1_S4 0x23 #define SAVAGE_TEXBLEND0_S4 0x24 #define SAVAGE_TEXBLEND1_S4 0x25 -#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ +#define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ #define SAVAGE_TEXDESCR_S4 0x27 #define SAVAGE_FOGTABLE_S4 0x28 #define SAVAGE_FOGCTRL_S4 0x30 @@ -293,7 +293,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define SAVAGE_TEXBLENDCOLOR_S4 0x39 /* Savage3D/MX/IX 3D registers */ #define SAVAGE_TEXPALADDR_S3D 0x18 -#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ +#define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ #define SAVAGE_TEXADDR_S3D 0x1A #define SAVAGE_TEXDESCR_S3D 0x1B #define SAVAGE_TEXCTRL_S3D 0x1C @@ -305,7 +305,7 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define SAVAGE_DESTCTRL_S3D 0x34 #define SAVAGE_SCSTART_S3D 0x35 #define SAVAGE_SCEND_S3D 0x36 -#define SAVAGE_ZWATERMARK_S3D 0x37 +#define SAVAGE_ZWATERMARK_S3D 0x37 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 /* common stuff */ #define SAVAGE_VERTBUFADDR 0x3e @@ -313,9 +313,9 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define SAVAGE_DMABUFADDR 0x51 /* texture enable bits (needed for tex addr checking) */ -#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ -#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ -#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ +#define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ +#define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ +#define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ /* Global fields in Savage4/Twister/ProSavage 3D registers: * @@ -576,4 +576,4 @@ extern void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, #define TEST_AGE( age, e, w ) \ ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) -#endif /* __SAVAGE_DRV_H__ */ +#endif /* __SAVAGE_DRV_H__ */ diff --git a/drivers/char/drm/savage_state.c b/drivers/char/drm/savage_state.c index 475695a0008..39654cb5d57 100644 --- a/drivers/char/drm/savage_state.c +++ b/drivers/char/drm/savage_state.c @@ -26,48 +26,48 @@ #include "savage_drm.h" #include "savage_drv.h" -void savage_emit_clip_rect_s3d(drm_savage_private_t *dev_priv, - drm_clip_rect_t *pbox) +void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, + drm_clip_rect_t * pbox) { uint32_t scstart = dev_priv->state.s3d.new_scstart; - uint32_t scend = dev_priv->state.s3d.new_scend; + uint32_t scend = dev_priv->state.s3d.new_scend; scstart = (scstart & ~SAVAGE_SCISSOR_MASK_S3D) | - ((uint32_t)pbox->x1 & 0x000007ff) | - (((uint32_t)pbox->y1 << 16) & 0x07ff0000); - scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) | - (((uint32_t)pbox->x2-1) & 0x000007ff) | - ((((uint32_t)pbox->y2-1) << 16) & 0x07ff0000); + ((uint32_t) pbox->x1 & 0x000007ff) | + (((uint32_t) pbox->y1 << 16) & 0x07ff0000); + scend = (scend & ~SAVAGE_SCISSOR_MASK_S3D) | + (((uint32_t) pbox->x2 - 1) & 0x000007ff) | + ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000); if (scstart != dev_priv->state.s3d.scstart || - scend != dev_priv->state.s3d.scend) { + scend != dev_priv->state.s3d.scend) { DMA_LOCALS; BEGIN_DMA(4); - DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D); + DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); DMA_SET_REGISTERS(SAVAGE_SCSTART_S3D, 2); DMA_WRITE(scstart); DMA_WRITE(scend); dev_priv->state.s3d.scstart = scstart; - dev_priv->state.s3d.scend = scend; + dev_priv->state.s3d.scend = scend; dev_priv->waiting = 1; DMA_COMMIT(); } } -void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, - drm_clip_rect_t *pbox) +void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, + drm_clip_rect_t * pbox) { uint32_t drawctrl0 = dev_priv->state.s4.new_drawctrl0; uint32_t drawctrl1 = dev_priv->state.s4.new_drawctrl1; drawctrl0 = (drawctrl0 & ~SAVAGE_SCISSOR_MASK_S4) | - ((uint32_t)pbox->x1 & 0x000007ff) | - (((uint32_t)pbox->y1 << 12) & 0x00fff000); + ((uint32_t) pbox->x1 & 0x000007ff) | + (((uint32_t) pbox->y1 << 12) & 0x00fff000); drawctrl1 = (drawctrl1 & ~SAVAGE_SCISSOR_MASK_S4) | - (((uint32_t)pbox->x2-1) & 0x000007ff) | - ((((uint32_t)pbox->y2-1) << 12) & 0x00fff000); + (((uint32_t) pbox->x2 - 1) & 0x000007ff) | + ((((uint32_t) pbox->y2 - 1) << 12) & 0x00fff000); if (drawctrl0 != dev_priv->state.s4.drawctrl0 || drawctrl1 != dev_priv->state.s4.drawctrl1) { DMA_LOCALS; BEGIN_DMA(4); - DMA_WRITE(BCI_CMD_WAIT|BCI_CMD_WAIT_3D); + DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); DMA_SET_REGISTERS(SAVAGE_DRAWCTRL0_S4, 2); DMA_WRITE(drawctrl0); DMA_WRITE(drawctrl1); @@ -78,22 +78,23 @@ void savage_emit_clip_rect_s4(drm_savage_private_t *dev_priv, } } -static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, +static int savage_verify_texaddr(drm_savage_private_t * dev_priv, int unit, uint32_t addr) { - if ((addr & 6) != 2) { /* reserved bits */ + if ((addr & 6) != 2) { /* reserved bits */ DRM_ERROR("bad texAddr%d %08x (reserved bits)\n", unit, addr); return DRM_ERR(EINVAL); } - if (!(addr & 1)) { /* local */ + if (!(addr & 1)) { /* local */ addr &= ~7; - if (addr < dev_priv->texture_offset || - addr >= dev_priv->texture_offset+dev_priv->texture_size) { - DRM_ERROR("bad texAddr%d %08x (local addr out of range)\n", - unit, addr); + if (addr < dev_priv->texture_offset || + addr >= dev_priv->texture_offset + dev_priv->texture_size) { + DRM_ERROR + ("bad texAddr%d %08x (local addr out of range)\n", + unit, addr); return DRM_ERR(EINVAL); } - } else { /* AGP */ + } else { /* AGP */ if (!dev_priv->agp_textures) { DRM_ERROR("bad texAddr%d %08x (AGP not available)\n", unit, addr); @@ -103,8 +104,9 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, if (addr < dev_priv->agp_textures->offset || addr >= (dev_priv->agp_textures->offset + dev_priv->agp_textures->size)) { - DRM_ERROR("bad texAddr%d %08x (AGP addr out of range)\n", - unit, addr); + DRM_ERROR + ("bad texAddr%d %08x (AGP addr out of range)\n", + unit, addr); return DRM_ERR(EINVAL); } } @@ -122,14 +124,14 @@ static int savage_verify_texaddr(drm_savage_private_t *dev_priv, int unit, (dev_priv->state.where & ~(mask)); \ } \ } while (0) -static int savage_verify_state_s3d(drm_savage_private_t *dev_priv, +static int savage_verify_state_s3d(drm_savage_private_t * dev_priv, unsigned int start, unsigned int count, - const uint32_t __user *regs) + const uint32_t __user * regs) { if (start < SAVAGE_TEXPALADDR_S3D || - start+count-1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { + start + count - 1 > SAVAGE_DESTTEXRWWATERMARK_S3D) { DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", - start, start+count-1); + start, start + count - 1); return DRM_ERR(EINVAL); } @@ -140,28 +142,29 @@ static int savage_verify_state_s3d(drm_savage_private_t *dev_priv, /* if any texture regs were changed ... */ if (start <= SAVAGE_TEXCTRL_S3D && - start+count > SAVAGE_TEXPALADDR_S3D) { + start + count > SAVAGE_TEXPALADDR_S3D) { /* ... check texture state */ SAVE_STATE(SAVAGE_TEXCTRL_S3D, s3d.texctrl); SAVE_STATE(SAVAGE_TEXADDR_S3D, s3d.texaddr); if (dev_priv->state.s3d.texctrl & SAVAGE_TEXCTRL_TEXEN_MASK) - return savage_verify_texaddr( - dev_priv, 0, dev_priv->state.s3d.texaddr); + return savage_verify_texaddr(dev_priv, 0, + dev_priv->state.s3d. + texaddr); } return 0; } -static int savage_verify_state_s4(drm_savage_private_t *dev_priv, +static int savage_verify_state_s4(drm_savage_private_t * dev_priv, unsigned int start, unsigned int count, - const uint32_t __user *regs) + const uint32_t __user * regs) { int ret = 0; if (start < SAVAGE_DRAWLOCALCTRL_S4 || - start+count-1 > SAVAGE_TEXBLENDCOLOR_S4) { + start + count - 1 > SAVAGE_TEXBLENDCOLOR_S4) { DRM_ERROR("invalid register range (0x%04x-0x%04x)\n", - start, start+count-1); + start, start + count - 1); return DRM_ERR(EINVAL); } @@ -171,28 +174,30 @@ static int savage_verify_state_s4(drm_savage_private_t *dev_priv, ~SAVAGE_SCISSOR_MASK_S4); /* if any texture regs were changed ... */ - if (start <= SAVAGE_TEXDESCR_S4 && - start+count > SAVAGE_TEXPALADDR_S4) { + if (start <= SAVAGE_TEXDESCR_S4 && start + count > SAVAGE_TEXPALADDR_S4) { /* ... check texture state */ SAVE_STATE(SAVAGE_TEXDESCR_S4, s4.texdescr); SAVE_STATE(SAVAGE_TEXADDR0_S4, s4.texaddr0); SAVE_STATE(SAVAGE_TEXADDR1_S4, s4.texaddr1); if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX0EN_MASK) - ret |= savage_verify_texaddr( - dev_priv, 0, dev_priv->state.s4.texaddr0); + ret |= + savage_verify_texaddr(dev_priv, 0, + dev_priv->state.s4.texaddr0); if (dev_priv->state.s4.texdescr & SAVAGE_TEXDESCR_TEX1EN_MASK) - ret |= savage_verify_texaddr( - dev_priv, 1, dev_priv->state.s4.texaddr1); + ret |= + savage_verify_texaddr(dev_priv, 1, + dev_priv->state.s4.texaddr1); } return ret; } + #undef SAVE_STATE #undef SAVE_STATE_MASK -static int savage_dispatch_state(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint32_t __user *regs) +static int savage_dispatch_state(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const uint32_t __user * regs) { unsigned int count = cmd_header->state.count; unsigned int start = cmd_header->state.start; @@ -204,7 +209,7 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv, if (!count) return 0; - if (DRM_VERIFYAREA_READ(regs, count*4)) + if (DRM_VERIFYAREA_READ(regs, count * 4)) return DRM_ERR(EFAULT); if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { @@ -213,14 +218,14 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv, return ret; /* scissor regs are emitted in savage_dispatch_draw */ if (start < SAVAGE_SCSTART_S3D) { - if (start+count > SAVAGE_SCEND_S3D+1) - count2 = count - (SAVAGE_SCEND_S3D+1 - start); - if (start+count > SAVAGE_SCSTART_S3D) + if (start + count > SAVAGE_SCEND_S3D + 1) + count2 = count - (SAVAGE_SCEND_S3D + 1 - start); + if (start + count > SAVAGE_SCSTART_S3D) count = SAVAGE_SCSTART_S3D - start; } else if (start <= SAVAGE_SCEND_S3D) { - if (start+count > SAVAGE_SCEND_S3D+1) { - count -= SAVAGE_SCEND_S3D+1 - start; - start = SAVAGE_SCEND_S3D+1; + if (start + count > SAVAGE_SCEND_S3D + 1) { + count -= SAVAGE_SCEND_S3D + 1 - start; + start = SAVAGE_SCEND_S3D + 1; } else return 0; } @@ -230,23 +235,24 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv, return ret; /* scissor regs are emitted in savage_dispatch_draw */ if (start < SAVAGE_DRAWCTRL0_S4) { - if (start+count > SAVAGE_DRAWCTRL1_S4+1) - count2 = count - (SAVAGE_DRAWCTRL1_S4+1 - start); - if (start+count > SAVAGE_DRAWCTRL0_S4) + if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) + count2 = + count - (SAVAGE_DRAWCTRL1_S4 + 1 - start); + if (start + count > SAVAGE_DRAWCTRL0_S4) count = SAVAGE_DRAWCTRL0_S4 - start; } else if (start <= SAVAGE_DRAWCTRL1_S4) { - if (start+count > SAVAGE_DRAWCTRL1_S4+1) { - count -= SAVAGE_DRAWCTRL1_S4+1 - start; - start = SAVAGE_DRAWCTRL1_S4+1; + if (start + count > SAVAGE_DRAWCTRL1_S4 + 1) { + count -= SAVAGE_DRAWCTRL1_S4 + 1 - start; + start = SAVAGE_DRAWCTRL1_S4 + 1; } else return 0; } } - bci_size = count + (count+254)/255 + count2 + (count2+254)/255; + bci_size = count + (count + 254) / 255 + count2 + (count2 + 254) / 255; if (cmd_header->state.global) { - BEGIN_DMA(bci_size+1); + BEGIN_DMA(bci_size + 1); DMA_WRITE(BCI_CMD_WAIT | BCI_CMD_WAIT_3D); dev_priv->waiting = 1; } else { @@ -273,9 +279,9 @@ static int savage_dispatch_state(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const drm_buf_t *dmabuf) +static int savage_dispatch_dma_prim(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const drm_buf_t * dmabuf) { unsigned char reorder = 0; unsigned int prim = cmd_header->prim.prim; @@ -286,8 +292,8 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, BCI_LOCALS; if (!dmabuf) { - DRM_ERROR("called without dma buffers!\n"); - return DRM_ERR(EINVAL); + DRM_ERROR("called without dma buffers!\n"); + return DRM_ERR(EINVAL); } if (!n) @@ -307,8 +313,9 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, case SAVAGE_PRIM_TRISTRIP: case SAVAGE_PRIM_TRIFAN: if (n < 3) { - DRM_ERROR("wrong number of vertices %u in TRIFAN/STRIP\n", - n); + DRM_ERROR + ("wrong number of vertices %u in TRIFAN/STRIP\n", + n); return DRM_ERR(EINVAL); } break; @@ -319,17 +326,15 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip != 0) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", - skip); + DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); return DRM_ERR(EINVAL); } } else { unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - - (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - - (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); + (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - + (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", - skip); + DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); return DRM_ERR(EINVAL); } if (reorder) { @@ -338,9 +343,9 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, } } - if (start + n > dmabuf->total/32) { + if (start + n > dmabuf->total / 32) { DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", - start, start + n - 1, dmabuf->total/32); + start, start + n - 1, dmabuf->total / 32); return DRM_ERR(EINVAL); } @@ -375,32 +380,33 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, /* Need to reorder indices for correct flat * shading while preserving the clock sense * for correct culling. Only on Savage3D. */ - int reorder[3] = {-1, -1, -1}; - reorder[start%3] = 2; + int reorder[3] = { -1, -1, -1 }; + reorder[start % 3] = 2; - BEGIN_BCI((count+1+1)/2); - BCI_DRAW_INDICES_S3D(count, prim, start+2); + BEGIN_BCI((count + 1 + 1) / 2); + BCI_DRAW_INDICES_S3D(count, prim, start + 2); - for (i = start+1; i+1 < start+count; i += 2) + for (i = start + 1; i + 1 < start + count; i += 2) BCI_WRITE((i + reorder[i % 3]) | - ((i+1 + reorder[(i+1) % 3]) << 16)); - if (i < start+count) - BCI_WRITE(i + reorder[i%3]); + ((i + 1 + + reorder[(i + 1) % 3]) << 16)); + if (i < start + count) + BCI_WRITE(i + reorder[i % 3]); } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - BEGIN_BCI((count+1+1)/2); + BEGIN_BCI((count + 1 + 1) / 2); BCI_DRAW_INDICES_S3D(count, prim, start); - for (i = start+1; i+1 < start+count; i += 2) - BCI_WRITE(i | ((i+1) << 16)); - if (i < start+count) + for (i = start + 1; i + 1 < start + count; i += 2) + BCI_WRITE(i | ((i + 1) << 16)); + if (i < start + count) BCI_WRITE(i); } else { - BEGIN_BCI((count+2+1)/2); + BEGIN_BCI((count + 2 + 1) / 2); BCI_DRAW_INDICES_S4(count, prim, skip); - for (i = start; i+1 < start+count; i += 2) - BCI_WRITE(i | ((i+1) << 16)); - if (i < start+count) + for (i = start; i + 1 < start + count; i += 2) + BCI_WRITE(i | ((i + 1) << 16)); + if (i < start + count) BCI_WRITE(i); } @@ -413,11 +419,10 @@ static int savage_dispatch_dma_prim(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint32_t __user *vtxbuf, - unsigned int vb_size, - unsigned int vb_stride) +static int savage_dispatch_vb_prim(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const uint32_t __user * vtxbuf, + unsigned int vb_size, unsigned int vb_stride) { unsigned char reorder = 0; unsigned int prim = cmd_header->prim.prim; @@ -445,8 +450,9 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, case SAVAGE_PRIM_TRISTRIP: case SAVAGE_PRIM_TRIFAN: if (n < 3) { - DRM_ERROR("wrong number of vertices %u in TRIFAN/STRIP\n", - n); + DRM_ERROR + ("wrong number of vertices %u in TRIFAN/STRIP\n", + n); return DRM_ERR(EINVAL); } break; @@ -460,18 +466,18 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, DRM_ERROR("invalid skip flags 0x%04x\n", skip); return DRM_ERR(EINVAL); } - vtx_size = 8; /* full vertex */ + vtx_size = 8; /* full vertex */ } else { if (skip > SAVAGE_SKIP_ALL_S4) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); return DRM_ERR(EINVAL); } - vtx_size = 10; /* full vertex */ + vtx_size = 10; /* full vertex */ } vtx_size -= (skip & 1) + (skip >> 1 & 1) + - (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + - (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); + (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + + (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); if (vtx_size > vb_stride) { DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", @@ -479,9 +485,9 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, return DRM_ERR(EINVAL); } - if (start + n > vb_size / (vb_stride*4)) { + if (start + n > vb_size / (vb_stride * 4)) { DRM_ERROR("vertex indices (%u-%u) out of range (0-%u)\n", - start, start + n - 1, vb_size / (vb_stride*4)); + start, start + n - 1, vb_size / (vb_stride * 4)); return DRM_ERR(EINVAL); } @@ -493,31 +499,31 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, /* Need to reorder vertices for correct flat * shading while preserving the clock sense * for correct culling. Only on Savage3D. */ - int reorder[3] = {-1, -1, -1}; - reorder[start%3] = 2; + int reorder[3] = { -1, -1, -1 }; + reorder[start % 3] = 2; - BEGIN_DMA(count*vtx_size+1); + BEGIN_DMA(count * vtx_size + 1); DMA_DRAW_PRIMITIVE(count, prim, skip); - for (i = start; i < start+count; ++i) { + for (i = start; i < start + count; ++i) { unsigned int j = i + reorder[i % 3]; - DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], + DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j], vtx_size); } DMA_COMMIT(); } else { - BEGIN_DMA(count*vtx_size+1); + BEGIN_DMA(count * vtx_size + 1); DMA_DRAW_PRIMITIVE(count, prim, skip); if (vb_stride == vtx_size) { - DMA_COPY_FROM_USER(&vtxbuf[vb_stride*start], - vtx_size*count); + DMA_COPY_FROM_USER(&vtxbuf[vb_stride * start], + vtx_size * count); } else { - for (i = start; i < start+count; ++i) { - DMA_COPY_FROM_USER( - &vtxbuf[vb_stride*i], - vtx_size); + for (i = start; i < start + count; ++i) { + DMA_COPY_FROM_USER(&vtxbuf + [vb_stride * i], + vtx_size); } } @@ -533,10 +539,10 @@ static int savage_dispatch_vb_prim(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint16_t __user *usr_idx, - const drm_buf_t *dmabuf) +static int savage_dispatch_dma_idx(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const uint16_t __user * usr_idx, + const drm_buf_t * dmabuf) { unsigned char reorder = 0; unsigned int prim = cmd_header->idx.prim; @@ -546,8 +552,8 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, BCI_LOCALS; if (!dmabuf) { - DRM_ERROR("called without dma buffers!\n"); - return DRM_ERR(EINVAL); + DRM_ERROR("called without dma buffers!\n"); + return DRM_ERR(EINVAL); } if (!n) @@ -559,16 +565,15 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, prim = SAVAGE_PRIM_TRILIST; case SAVAGE_PRIM_TRILIST: if (n % 3 != 0) { - DRM_ERROR("wrong number of indices %u in TRILIST\n", - n); + DRM_ERROR("wrong number of indices %u in TRILIST\n", n); return DRM_ERR(EINVAL); } break; case SAVAGE_PRIM_TRISTRIP: case SAVAGE_PRIM_TRIFAN: if (n < 3) { - DRM_ERROR("wrong number of indices %u in TRIFAN/STRIP\n", - n); + DRM_ERROR + ("wrong number of indices %u in TRIFAN/STRIP\n", n); return DRM_ERR(EINVAL); } break; @@ -579,17 +584,15 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { if (skip != 0) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", - skip); + DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); return DRM_ERR(EINVAL); } } else { unsigned int size = 10 - (skip & 1) - (skip >> 1 & 1) - - (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - - (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); + (skip >> 2 & 1) - (skip >> 3 & 1) - (skip >> 4 & 1) - + (skip >> 5 & 1) - (skip >> 6 & 1) - (skip >> 7 & 1); if (skip > SAVAGE_SKIP_ALL_S4 || size != 8) { - DRM_ERROR("invalid skip flags 0x%04x for DMA\n", - skip); + DRM_ERROR("invalid skip flags 0x%04x for DMA\n", skip); return DRM_ERR(EINVAL); } if (reorder) { @@ -629,11 +632,11 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, uint16_t idx[255]; /* Copy and check indices */ - DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count*2); + DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count * 2); for (i = 0; i < count; ++i) { - if (idx[i] > dmabuf->total/32) { + if (idx[i] > dmabuf->total / 32) { DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", - i, idx[i], dmabuf->total/32); + i, idx[i], dmabuf->total / 32); return DRM_ERR(EINVAL); } } @@ -642,30 +645,31 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, /* Need to reorder indices for correct flat * shading while preserving the clock sense * for correct culling. Only on Savage3D. */ - int reorder[3] = {2, -1, -1}; + int reorder[3] = { 2, -1, -1 }; - BEGIN_BCI((count+1+1)/2); + BEGIN_BCI((count + 1 + 1) / 2); BCI_DRAW_INDICES_S3D(count, prim, idx[2]); - for (i = 1; i+1 < count; i += 2) + for (i = 1; i + 1 < count; i += 2) BCI_WRITE(idx[i + reorder[i % 3]] | - (idx[i+1 + reorder[(i+1) % 3]] << 16)); + (idx[i + 1 + reorder[(i + 1) % 3]] << + 16)); if (i < count) - BCI_WRITE(idx[i + reorder[i%3]]); + BCI_WRITE(idx[i + reorder[i % 3]]); } else if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { - BEGIN_BCI((count+1+1)/2); + BEGIN_BCI((count + 1 + 1) / 2); BCI_DRAW_INDICES_S3D(count, prim, idx[0]); - for (i = 1; i+1 < count; i += 2) - BCI_WRITE(idx[i] | (idx[i+1] << 16)); + for (i = 1; i + 1 < count; i += 2) + BCI_WRITE(idx[i] | (idx[i + 1] << 16)); if (i < count) BCI_WRITE(idx[i]); } else { - BEGIN_BCI((count+2+1)/2); + BEGIN_BCI((count + 2 + 1) / 2); BCI_DRAW_INDICES_S4(count, prim, skip); - for (i = 0; i+1 < count; i += 2) - BCI_WRITE(idx[i] | (idx[i+1] << 16)); + for (i = 0; i + 1 < count; i += 2) + BCI_WRITE(idx[i] | (idx[i + 1] << 16)); if (i < count) BCI_WRITE(idx[i]); } @@ -679,12 +683,11 @@ static int savage_dispatch_dma_idx(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const uint16_t __user *usr_idx, - const uint32_t __user *vtxbuf, - unsigned int vb_size, - unsigned int vb_stride) +static int savage_dispatch_vb_idx(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const uint16_t __user * usr_idx, + const uint32_t __user * vtxbuf, + unsigned int vb_size, unsigned int vb_stride) { unsigned char reorder = 0; unsigned int prim = cmd_header->idx.prim; @@ -703,16 +706,15 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, prim = SAVAGE_PRIM_TRILIST; case SAVAGE_PRIM_TRILIST: if (n % 3 != 0) { - DRM_ERROR("wrong number of indices %u in TRILIST\n", - n); + DRM_ERROR("wrong number of indices %u in TRILIST\n", n); return DRM_ERR(EINVAL); } break; case SAVAGE_PRIM_TRISTRIP: case SAVAGE_PRIM_TRIFAN: if (n < 3) { - DRM_ERROR("wrong number of indices %u in TRIFAN/STRIP\n", - n); + DRM_ERROR + ("wrong number of indices %u in TRIFAN/STRIP\n", n); return DRM_ERR(EINVAL); } break; @@ -726,18 +728,18 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, DRM_ERROR("invalid skip flags 0x%04x\n", skip); return DRM_ERR(EINVAL); } - vtx_size = 8; /* full vertex */ + vtx_size = 8; /* full vertex */ } else { if (skip > SAVAGE_SKIP_ALL_S4) { DRM_ERROR("invalid skip flags 0x%04x\n", skip); return DRM_ERR(EINVAL); } - vtx_size = 10; /* full vertex */ + vtx_size = 10; /* full vertex */ } vtx_size -= (skip & 1) + (skip >> 1 & 1) + - (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + - (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); + (skip >> 2 & 1) + (skip >> 3 & 1) + (skip >> 4 & 1) + + (skip >> 5 & 1) + (skip >> 6 & 1) + (skip >> 7 & 1); if (vtx_size > vb_stride) { DRM_ERROR("vertex size greater than vb stride (%u > %u)\n", @@ -753,11 +755,11 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, uint16_t idx[255]; /* Copy and check indices */ - DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count*2); + DRM_COPY_FROM_USER_UNCHECKED(idx, usr_idx, count * 2); for (i = 0; i < count; ++i) { - if (idx[i] > vb_size / (vb_stride*4)) { + if (idx[i] > vb_size / (vb_stride * 4)) { DRM_ERROR("idx[%u]=%u out of range (0-%u)\n", - i, idx[i], vb_size / (vb_stride*4)); + i, idx[i], vb_size / (vb_stride * 4)); return DRM_ERR(EINVAL); } } @@ -766,25 +768,25 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, /* Need to reorder vertices for correct flat * shading while preserving the clock sense * for correct culling. Only on Savage3D. */ - int reorder[3] = {2, -1, -1}; + int reorder[3] = { 2, -1, -1 }; - BEGIN_DMA(count*vtx_size+1); + BEGIN_DMA(count * vtx_size + 1); DMA_DRAW_PRIMITIVE(count, prim, skip); for (i = 0; i < count; ++i) { unsigned int j = idx[i + reorder[i % 3]]; - DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], + DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j], vtx_size); } DMA_COMMIT(); } else { - BEGIN_DMA(count*vtx_size+1); + BEGIN_DMA(count * vtx_size + 1); DMA_DRAW_PRIMITIVE(count, prim, skip); for (i = 0; i < count; ++i) { unsigned int j = idx[i]; - DMA_COPY_FROM_USER(&vtxbuf[vb_stride*j], + DMA_COPY_FROM_USER(&vtxbuf[vb_stride * j], vtx_size); } @@ -800,11 +802,11 @@ static int savage_dispatch_vb_idx(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_clear(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t *cmd_header, - const drm_savage_cmd_header_t __user *data, +static int savage_dispatch_clear(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t * cmd_header, + const drm_savage_cmd_header_t __user * data, unsigned int nbox, - const drm_clip_rect_t __user *usr_boxes) + const drm_clip_rect_t __user * usr_boxes) { unsigned int flags = cmd_header->clear0.flags, mask, value; unsigned int clear_cmd; @@ -814,18 +816,17 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv, if (nbox == 0) return 0; - DRM_GET_USER_UNCHECKED(mask, &((const drm_savage_cmd_header_t*)data) + DRM_GET_USER_UNCHECKED(mask, &((const drm_savage_cmd_header_t *)data) ->clear1.mask); - DRM_GET_USER_UNCHECKED(value, &((const drm_savage_cmd_header_t*)data) + DRM_GET_USER_UNCHECKED(value, &((const drm_savage_cmd_header_t *)data) ->clear1.value); clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | - BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW; - BCI_CMD_SET_ROP(clear_cmd,0xCC); + BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW; + BCI_CMD_SET_ROP(clear_cmd, 0xCC); nbufs = ((flags & SAVAGE_FRONT) ? 1 : 0) + - ((flags & SAVAGE_BACK) ? 1 : 0) + - ((flags & SAVAGE_DEPTH) ? 1 : 0); + ((flags & SAVAGE_BACK) ? 1 : 0) + ((flags & SAVAGE_DEPTH) ? 1 : 0); if (nbufs == 0) return 0; @@ -844,12 +845,12 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv, x = box.x1, y = box.y1; w = box.x2 - box.x1; h = box.y2 - box.y1; - BEGIN_DMA(nbufs*6); + BEGIN_DMA(nbufs * 6); for (buf = SAVAGE_FRONT; buf <= SAVAGE_DEPTH; buf <<= 1) { if (!(flags & buf)) continue; DMA_WRITE(clear_cmd); - switch(buf) { + switch (buf) { case SAVAGE_FRONT: DMA_WRITE(dev_priv->front_offset); DMA_WRITE(dev_priv->front_bd); @@ -880,9 +881,9 @@ static int savage_dispatch_clear(drm_savage_private_t *dev_priv, return 0; } -static int savage_dispatch_swap(drm_savage_private_t *dev_priv, +static int savage_dispatch_swap(drm_savage_private_t * dev_priv, unsigned int nbox, - const drm_clip_rect_t __user *usr_boxes) + const drm_clip_rect_t __user * usr_boxes) { unsigned int swap_cmd; unsigned int i; @@ -892,8 +893,8 @@ static int savage_dispatch_swap(drm_savage_private_t *dev_priv, return 0; swap_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | - BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD; - BCI_CMD_SET_ROP(swap_cmd,0xCC); + BCI_CMD_SRC_PBD_COLOR_NEW | BCI_CMD_DEST_GBD; + BCI_CMD_SET_ROP(swap_cmd, 0xCC); for (i = 0; i < nbox; ++i) { drm_clip_rect_t box; @@ -905,21 +906,21 @@ static int savage_dispatch_swap(drm_savage_private_t *dev_priv, DMA_WRITE(dev_priv->back_bd); DMA_WRITE(BCI_X_Y(box.x1, box.y1)); DMA_WRITE(BCI_X_Y(box.x1, box.y1)); - DMA_WRITE(BCI_W_H(box.x2-box.x1, box.y2-box.y1)); + DMA_WRITE(BCI_W_H(box.x2 - box.x1, box.y2 - box.y1)); DMA_COMMIT(); } return 0; } -static int savage_dispatch_draw(drm_savage_private_t *dev_priv, - const drm_savage_cmd_header_t __user *start, - const drm_savage_cmd_header_t __user *end, - const drm_buf_t *dmabuf, - const unsigned int __user *usr_vtxbuf, +static int savage_dispatch_draw(drm_savage_private_t * dev_priv, + const drm_savage_cmd_header_t __user * start, + const drm_savage_cmd_header_t __user * end, + const drm_buf_t * dmabuf, + const unsigned int __user * usr_vtxbuf, unsigned int vb_size, unsigned int vb_stride, unsigned int nbox, - const drm_clip_rect_t __user *usr_boxes) + const drm_clip_rect_t __user * usr_boxes) { unsigned int i, j; int ret; @@ -938,32 +939,42 @@ static int savage_dispatch_draw(drm_savage_private_t *dev_priv, usr_cmdbuf++; switch (cmd_header.cmd.cmd) { case SAVAGE_CMD_DMA_PRIM: - ret = savage_dispatch_dma_prim( - dev_priv, &cmd_header, dmabuf); + ret = + savage_dispatch_dma_prim(dev_priv, + &cmd_header, + dmabuf); break; case SAVAGE_CMD_VB_PRIM: - ret = savage_dispatch_vb_prim( - dev_priv, &cmd_header, - (const uint32_t __user *)usr_vtxbuf, - vb_size, vb_stride); + ret = + savage_dispatch_vb_prim(dev_priv, + &cmd_header, + (const uint32_t + __user *) + usr_vtxbuf, vb_size, + vb_stride); break; case SAVAGE_CMD_DMA_IDX: j = (cmd_header.idx.count + 3) / 4; /* j was check in savage_bci_cmdbuf */ - ret = savage_dispatch_dma_idx( - dev_priv, &cmd_header, - (const uint16_t __user *)usr_cmdbuf, - dmabuf); + ret = + savage_dispatch_dma_idx(dev_priv, + &cmd_header, + (const uint16_t + __user *) + usr_cmdbuf, dmabuf); usr_cmdbuf += j; break; case SAVAGE_CMD_VB_IDX: j = (cmd_header.idx.count + 3) / 4; /* j was check in savage_bci_cmdbuf */ - ret = savage_dispatch_vb_idx( - dev_priv, &cmd_header, - (const uint16_t __user *)usr_cmdbuf, - (const uint32_t __user *)usr_vtxbuf, - vb_size, vb_stride); + ret = + savage_dispatch_vb_idx(dev_priv, + &cmd_header, + (const uint16_t + __user *)usr_cmdbuf, + (const uint32_t + __user *)usr_vtxbuf, + vb_size, vb_stride); usr_cmdbuf += j; break; default: @@ -997,16 +1008,17 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) int ret = 0; DRM_DEBUG("\n"); - + LOCK_TEST_WITH_RETURN(dev, filp); - DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *)data, + DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_savage_cmdbuf_t __user *) data, sizeof(cmdbuf)); if (dma && dma->buflist) { if (cmdbuf.dma_idx > dma->buf_count) { - DRM_ERROR("vertex buffer index %u out of range (0-%u)\n", - cmdbuf.dma_idx, dma->buf_count-1); + DRM_ERROR + ("vertex buffer index %u out of range (0-%u)\n", + cmdbuf.dma_idx, dma->buf_count - 1); return DRM_ERR(EINVAL); } dmabuf = dma->buflist[cmdbuf.dma_idx]; @@ -1014,14 +1026,14 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) dmabuf = NULL; } - usr_cmdbuf = (drm_savage_cmd_header_t __user *)cmdbuf.cmd_addr; + usr_cmdbuf = (drm_savage_cmd_header_t __user *) cmdbuf.cmd_addr; usr_vtxbuf = (unsigned int __user *)cmdbuf.vb_addr; - usr_boxes = (drm_clip_rect_t __user *)cmdbuf.box_addr; - if ((cmdbuf.size && DRM_VERIFYAREA_READ(usr_cmdbuf, cmdbuf.size*8)) || - (cmdbuf.vb_size && DRM_VERIFYAREA_READ( - usr_vtxbuf, cmdbuf.vb_size)) || - (cmdbuf.nbox && DRM_VERIFYAREA_READ( - usr_boxes, cmdbuf.nbox*sizeof(drm_clip_rect_t)))) + usr_boxes = (drm_clip_rect_t __user *) cmdbuf.box_addr; + if ((cmdbuf.size && DRM_VERIFYAREA_READ(usr_cmdbuf, cmdbuf.size * 8)) || + (cmdbuf.vb_size && DRM_VERIFYAREA_READ(usr_vtxbuf, cmdbuf.vb_size)) + || (cmdbuf.nbox + && DRM_VERIFYAREA_READ(usr_boxes, + cmdbuf.nbox * sizeof(drm_clip_rect_t)))) return DRM_ERR(EFAULT); /* Make sure writes to DMA buffers are finished before sending @@ -1058,17 +1070,21 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) case SAVAGE_CMD_DMA_PRIM: case SAVAGE_CMD_VB_PRIM: if (!first_draw_cmd) - first_draw_cmd = usr_cmdbuf-1; + first_draw_cmd = usr_cmdbuf - 1; usr_cmdbuf += j; i += j; break; default: if (first_draw_cmd) { - ret = savage_dispatch_draw ( - dev_priv, first_draw_cmd, usr_cmdbuf-1, - dmabuf, usr_vtxbuf, cmdbuf.vb_size, - cmdbuf.vb_stride, - cmdbuf.nbox, usr_boxes); + ret = + savage_dispatch_draw(dev_priv, + first_draw_cmd, + usr_cmdbuf - 1, dmabuf, + usr_vtxbuf, + cmdbuf.vb_size, + cmdbuf.vb_stride, + cmdbuf.nbox, + usr_boxes); if (ret != 0) return ret; first_draw_cmd = NULL; @@ -1086,9 +1102,9 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) DMA_FLUSH(); return DRM_ERR(EINVAL); } - ret = savage_dispatch_state( - dev_priv, &cmd_header, - (uint32_t __user *)usr_cmdbuf); + ret = savage_dispatch_state(dev_priv, &cmd_header, + (uint32_t __user *) + usr_cmdbuf); usr_cmdbuf += j; i += j; break; @@ -1122,10 +1138,11 @@ int savage_bci_cmdbuf(DRM_IOCTL_ARGS) } if (first_draw_cmd) { - ret = savage_dispatch_draw ( - dev_priv, first_draw_cmd, usr_cmdbuf, dmabuf, - usr_vtxbuf, cmdbuf.vb_size, cmdbuf.vb_stride, - cmdbuf.nbox, usr_boxes); + ret = + savage_dispatch_draw(dev_priv, first_draw_cmd, usr_cmdbuf, + dmabuf, usr_vtxbuf, cmdbuf.vb_size, + cmdbuf.vb_stride, cmdbuf.nbox, + usr_boxes); if (ret != 0) { DMA_FLUSH(); return ret; diff --git a/drivers/char/drm/sis_drm.h b/drivers/char/drm/sis_drm.h index e99c3a43abb..8f273da76dd 100644 --- a/drivers/char/drm/sis_drm.h +++ b/drivers/char/drm/sis_drm.h @@ -39,4 +39,4 @@ typedef struct { unsigned int offset, size; } drm_sis_fb_t; -#endif /* __SIS_DRM_H__ */ +#endif /* __SIS_DRM_H__ */ diff --git a/drivers/char/drm/sis_drv.c b/drivers/char/drm/sis_drv.c index f441714faae..6d0cb222600 100644 --- a/drivers/char/drm/sis_drv.c +++ b/drivers/char/drm/sis_drv.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -31,31 +31,29 @@ #include "sis_drv.h" #include "drm_pciids.h" - -static int postinit( struct drm_device *dev, unsigned long flags ) + +static int postinit(struct drm_device *dev, unsigned long flags) { - DRM_INFO( "Initialized %s %d.%d.%d %s on minor %d: %s\n", - DRIVER_NAME, - DRIVER_MAJOR, - DRIVER_MINOR, - DRIVER_PATCHLEVEL, - DRIVER_DATE, - dev->primary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -77,18 +75,18 @@ static struct drm_driver driver = { .version = version, .ioctls = sis_ioctls, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init sis_init(void) @@ -105,6 +103,6 @@ static void __exit sis_exit(void) module_init(sis_init); module_exit(sis_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/sis_drv.h b/drivers/char/drm/sis_drv.h index 5be36b5caec..4ef3d622641 100644 --- a/drivers/char/drm/sis_drv.h +++ b/drivers/char/drm/sis_drv.h @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,7 +22,7 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * */ #ifndef _SIS_DRV_H_ @@ -46,7 +46,7 @@ typedef struct drm_sis_private { memHeap_t *FBHeap; } drm_sis_private_t; -extern int sis_init_context(drm_device_t *dev, int context); -extern int sis_final_context(drm_device_t *dev, int context); +extern int sis_init_context(drm_device_t * dev, int context); +extern int sis_final_context(drm_device_t * dev, int context); #endif diff --git a/drivers/char/drm/sis_ds.c b/drivers/char/drm/sis_ds.c index e37ed8ce48d..2e485d48294 100644 --- a/drivers/char/drm/sis_ds.c +++ b/drivers/char/drm/sis_ds.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,10 +22,10 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ #include "drmP.h" @@ -41,13 +41,13 @@ set_t *setInit(void) int i; set_t *set; - set = (set_t *)drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); + set = (set_t *) drm_alloc(sizeof(set_t), DRM_MEM_DRIVER); if (set != NULL) { for (i = 0; i < SET_SIZE; i++) { - set->list[i].free_next = i + 1; + set->list[i].free_next = i + 1; set->list[i].alloc_next = -1; } - set->list[SET_SIZE-1].free_next = -1; + set->list[SET_SIZE - 1].free_next = -1; set->free = 0; set->alloc = -1; set->trace = -1; @@ -55,10 +55,10 @@ set_t *setInit(void) return set; } -int setAdd(set_t *set, ITEM_TYPE item) +int setAdd(set_t * set, ITEM_TYPE item) { int free = set->free; - + if (free != -1) { set->list[free].val = item; set->free = set->list[free].free_next; @@ -67,16 +67,16 @@ int setAdd(set_t *set, ITEM_TYPE item) } set->list[free].alloc_next = set->alloc; - set->alloc = free; - set->list[free].free_next = -1; + set->alloc = free; + set->list[free].free_next = -1; return 1; } -int setDel(set_t *set, ITEM_TYPE item) +int setDel(set_t * set, ITEM_TYPE item) { int alloc = set->alloc; - int prev = -1; + int prev = -1; while (alloc != -1) { if (set->list[alloc].val == item) { @@ -103,7 +103,7 @@ int setDel(set_t *set, ITEM_TYPE item) /* setFirst -> setAdd -> setNext is wrong */ -int setFirst(set_t *set, ITEM_TYPE *item) +int setFirst(set_t * set, ITEM_TYPE * item) { if (set->alloc == -1) return 0; @@ -114,7 +114,7 @@ int setFirst(set_t *set, ITEM_TYPE *item) return 1; } -int setNext(set_t *set, ITEM_TYPE *item) +int setNext(set_t * set, ITEM_TYPE * item) { if (set->trace == -1) return 0; @@ -125,7 +125,7 @@ int setNext(set_t *set, ITEM_TYPE *item) return 1; } -int setDestroy(set_t *set) +int setDestroy(set_t * set) { drm_free(set, sizeof(set_t), DRM_MEM_DRIVER); @@ -149,35 +149,34 @@ int setDestroy(set_t *set) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ #define ISFREE(bptr) ((bptr)->free) -memHeap_t *mmInit(int ofs, - int size) +memHeap_t *mmInit(int ofs, int size) { PMemBlock blocks; if (size <= 0) return NULL; - blocks = (TMemBlock *)drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); + blocks = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), DRM_MEM_DRIVER); if (blocks != NULL) { blocks->ofs = ofs; blocks->size = size; blocks->free = 1; - return (memHeap_t *)blocks; + return (memHeap_t *) blocks; } else return NULL; } /* Checks if a pointer 'b' is part of the heap 'heap' */ -int mmBlockInHeap(memHeap_t *heap, PMemBlock b) +int mmBlockInHeap(memHeap_t * heap, PMemBlock b) { TMemBlock *p; @@ -194,16 +193,16 @@ int mmBlockInHeap(memHeap_t *heap, PMemBlock b) return 0; } -static TMemBlock* SliceBlock(TMemBlock *p, - int startofs, int size, +static TMemBlock *SliceBlock(TMemBlock * p, + int startofs, int size, int reserved, int alignment) { TMemBlock *newblock; /* break left */ if (startofs > p->ofs) { - newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); + newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); newblock->ofs = startofs; newblock->size = p->size - (startofs - p->ofs); newblock->free = 1; @@ -215,8 +214,8 @@ static TMemBlock* SliceBlock(TMemBlock *p, /* break right */ if (size < p->size) { - newblock = (TMemBlock*) drm_calloc(1, sizeof(TMemBlock), - DRM_MEM_DRIVER); + newblock = (TMemBlock *) drm_calloc(1, sizeof(TMemBlock), + DRM_MEM_DRIVER); newblock->ofs = startofs + size; newblock->size = p->size - size; newblock->free = 1; @@ -232,37 +231,37 @@ static TMemBlock* SliceBlock(TMemBlock *p, return p; } -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch) +PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch) { - int mask,startofs, endofs; + int mask, startofs, endofs; TMemBlock *p; - + if (heap == NULL || align2 < 0 || size <= 0) return NULL; - mask = (1 << align2)-1; + mask = (1 << align2) - 1; startofs = 0; - p = (TMemBlock *)heap; + p = (TMemBlock *) heap; while (p != NULL) { if (ISFREE(p)) { startofs = (p->ofs + mask) & ~mask; - if ( startofs < startSearch ) { + if (startofs < startSearch) { startofs = startSearch; } - endofs = startofs+size; - if (endofs <= (p->ofs+p->size)) + endofs = startofs + size; + if (endofs <= (p->ofs + p->size)) break; } p = p->next; } if (p == NULL) return NULL; - p = SliceBlock(p,startofs,size,0,mask+1); + p = SliceBlock(p, startofs, size, 0, mask + 1); p->heap = heap; return p; } -static __inline__ int Join2Blocks(TMemBlock *p) +static __inline__ int Join2Blocks(TMemBlock * p) { if (p->free && p->next && p->next->free) { TMemBlock *q = p->next; @@ -295,7 +294,6 @@ int mmFreeMem(PMemBlock b) p->free = 1; Join2Blocks(p); if (prev) - Join2Blocks(prev); + Join2Blocks(prev); return 0; } - diff --git a/drivers/char/drm/sis_ds.h b/drivers/char/drm/sis_ds.h index 171ee75afa5..da850b4f544 100644 --- a/drivers/char/drm/sis_ds.h +++ b/drivers/char/drm/sis_ds.h @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,10 +22,10 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ #ifndef __SIS_DS_H__ @@ -50,11 +50,11 @@ typedef struct { } set_t; set_t *setInit(void); -int setAdd(set_t *set, ITEM_TYPE item); -int setDel(set_t *set, ITEM_TYPE item); -int setFirst(set_t *set, ITEM_TYPE *item); -int setNext(set_t *set, ITEM_TYPE *item); -int setDestroy(set_t *set); +int setAdd(set_t * set, ITEM_TYPE item); +int setDel(set_t * set, ITEM_TYPE item); +int setFirst(set_t * set, ITEM_TYPE * item); +int setNext(set_t * set, ITEM_TYPE * item); +int setDestroy(set_t * set); /* * GLX Hardware Device Driver common code @@ -73,9 +73,9 @@ int setDestroy(set_t *set); * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ @@ -83,7 +83,7 @@ int setDestroy(set_t *set); struct mem_block_t { struct mem_block_t *next; struct mem_block_t *heap; - int ofs,size; + int ofs, size; int align; unsigned int free:1; unsigned int reserved:1; @@ -109,11 +109,11 @@ static __inline__ void mmMarkReserved(PMemBlock b) b->reserved = 1; } -/* +/* * input: total size in bytes * return: a heap pointer if OK, NULL if error */ -memHeap_t *mmInit( int ofs, int size ); +memHeap_t *mmInit(int ofs, int size); /* * Allocate 'size' bytes with 2^align2 bytes alignment, @@ -125,21 +125,21 @@ memHeap_t *mmInit( int ofs, int size ); * startSearch = linear offset from start of heap to begin search * return: pointer to the allocated block, 0 if error */ -PMemBlock mmAllocMem( memHeap_t *heap, int size, int align2, int startSearch ); +PMemBlock mmAllocMem(memHeap_t * heap, int size, int align2, int startSearch); /* * Returns 1 if the block 'b' is part of the heap 'heap' */ -int mmBlockInHeap( PMemBlock heap, PMemBlock b ); +int mmBlockInHeap(PMemBlock heap, PMemBlock b); /* * Free block starts at offset * input: pointer to a block * return: 0 if OK, -1 if error */ -int mmFreeMem( PMemBlock b ); +int mmFreeMem(PMemBlock b); /* For debuging purpose. */ -void mmDumpMemInfo( memHeap_t *mmInit ); +void mmDumpMemInfo(memHeap_t * mmInit); -#endif /* __SIS_DS_H__ */ +#endif /* __SIS_DS_H__ */ diff --git a/drivers/char/drm/sis_mm.c b/drivers/char/drm/sis_mm.c index 6610c5576d2..50e32384ad9 100644 --- a/drivers/char/drm/sis_mm.c +++ b/drivers/char/drm/sis_mm.c @@ -10,11 +10,11 @@ * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: - * + * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. - * + * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL @@ -22,10 +22,10 @@ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. - * + * * Authors: * Sung-Ching Lin - * + * */ #include "drmP.h" @@ -37,25 +37,23 @@ #endif #define MAX_CONTEXT 100 -#define VIDEO_TYPE 0 +#define VIDEO_TYPE 0 #define AGP_TYPE 1 typedef struct { int used; int context; - set_t *sets[2]; /* 0 for video, 1 for AGP */ + set_t *sets[2]; /* 0 for video, 1 for AGP */ } sis_context_t; static sis_context_t global_ppriv[MAX_CONTEXT]; - static int add_alloc_set(int context, int type, unsigned int val) { int i, retval = 0; - + for (i = 0; i < MAX_CONTEXT; i++) { - if (global_ppriv[i].used && global_ppriv[i].context == context) - { + if (global_ppriv[i].used && global_ppriv[i].context == context) { retval = setAdd(global_ppriv[i].sets[type], val); break; } @@ -64,12 +62,11 @@ static int add_alloc_set(int context, int type, unsigned int val) } static int del_alloc_set(int context, int type, unsigned int val) -{ +{ int i, retval = 0; for (i = 0; i < MAX_CONTEXT; i++) { - if (global_ppriv[i].used && global_ppriv[i].context == context) - { + if (global_ppriv[i].used && global_ppriv[i].context == context) { retval = setDel(global_ppriv[i].sets[type], val); break; } @@ -77,15 +74,15 @@ static int del_alloc_set(int context, int type, unsigned int val) return retval; } -/* fb management via fb device */ +/* fb management via fb device */ #if defined(__linux__) && defined(CONFIG_FB_SIS) -static int sis_fb_init( DRM_IOCTL_ARGS ) +static int sis_fb_init(DRM_IOCTL_ARGS) { return 0; } -static int sis_fb_alloc( DRM_IOCTL_ARGS ) +static int sis_fb_alloc(DRM_IOCTL_ARGS) { drm_sis_mem_t fb; struct sis_memreq req; @@ -105,7 +102,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS ) sis_free(req.offset); retval = DRM_ERR(EINVAL); } - } else { + } else { fb.offset = 0; fb.size = 0; fb.free = 0; @@ -118,19 +115,19 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS ) return retval; } -static int sis_fb_free( DRM_IOCTL_ARGS ) +static int sis_fb_free(DRM_IOCTL_ARGS) { drm_sis_mem_t fb; int retval = 0; - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb)); + DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); if (!fb.free) return DRM_ERR(EINVAL); if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) retval = DRM_ERR(EINVAL); - sis_free((u32)fb.free); + sis_free((u32) fb.free); DRM_DEBUG("free fb, offset = %lu\n", fb.free); @@ -149,17 +146,17 @@ static int sis_fb_free( DRM_IOCTL_ARGS ) * X driver/sisfb HW- Command- * framebuffer memory DRI heap Cursor queue */ -static int sis_fb_init( DRM_IOCTL_ARGS ) +static int sis_fb_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_fb_t fb; - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *)data, sizeof(fb)); + DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_fb_t __user *) data, sizeof(fb)); if (dev_priv == NULL) { dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), - DRM_MEM_DRIVER); + DRM_MEM_DRIVER); dev_priv = dev->dev_private; if (dev_priv == NULL) return ENOMEM; @@ -175,7 +172,7 @@ static int sis_fb_init( DRM_IOCTL_ARGS ) return 0; } -static int sis_fb_alloc( DRM_IOCTL_ARGS ) +static int sis_fb_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; @@ -186,9 +183,9 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS ) if (dev_priv == NULL || dev_priv->FBHeap == NULL) return DRM_ERR(EINVAL); - + DRM_COPY_FROM_USER_IOCTL(fb, argp, sizeof(fb)); - + block = mmAllocMem(dev_priv->FBHeap, fb.size, 0, 0); if (block) { /* TODO */ @@ -196,7 +193,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS ) fb.free = (unsigned long)block; if (!add_alloc_set(fb.context, VIDEO_TYPE, fb.free)) { DRM_DEBUG("adding to allocation set fails\n"); - mmFreeMem((PMemBlock)fb.free); + mmFreeMem((PMemBlock) fb.free); retval = DRM_ERR(EINVAL); } } else { @@ -212,7 +209,7 @@ static int sis_fb_alloc( DRM_IOCTL_ARGS ) return retval; } -static int sis_fb_free( DRM_IOCTL_ARGS ) +static int sis_fb_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; @@ -221,14 +218,14 @@ static int sis_fb_free( DRM_IOCTL_ARGS ) if (dev_priv == NULL || dev_priv->FBHeap == NULL) return DRM_ERR(EINVAL); - DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *)data, sizeof(fb)); + DRM_COPY_FROM_USER_IOCTL(fb, (drm_sis_mem_t __user *) data, sizeof(fb)); - if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock)fb.free)) + if (!mmBlockInHeap(dev_priv->FBHeap, (PMemBlock) fb.free)) return DRM_ERR(EINVAL); if (!del_alloc_set(fb.context, VIDEO_TYPE, fb.free)) return DRM_ERR(EINVAL); - mmFreeMem((PMemBlock)fb.free); + mmFreeMem((PMemBlock) fb.free); DRM_DEBUG("free fb, free = 0x%lx\n", fb.free); @@ -237,9 +234,9 @@ static int sis_fb_free( DRM_IOCTL_ARGS ) #endif -/* agp memory management */ +/* agp memory management */ -static int sis_ioctl_agp_init( DRM_IOCTL_ARGS ) +static int sis_ioctl_agp_init(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; @@ -247,7 +244,7 @@ static int sis_ioctl_agp_init( DRM_IOCTL_ARGS ) if (dev_priv == NULL) { dev->dev_private = drm_calloc(1, sizeof(drm_sis_private_t), - DRM_MEM_DRIVER); + DRM_MEM_DRIVER); dev_priv = dev->dev_private; if (dev_priv == NULL) return ENOMEM; @@ -256,16 +253,17 @@ static int sis_ioctl_agp_init( DRM_IOCTL_ARGS ) if (dev_priv->AGPHeap != NULL) return DRM_ERR(EINVAL); - DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *)data, sizeof(agp)); + DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_agp_t __user *) data, + sizeof(agp)); dev_priv->AGPHeap = mmInit(agp.offset, agp.size); DRM_DEBUG("offset = %u, size = %u", agp.offset, agp.size); - + return 0; } -static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ) +static int sis_ioctl_agp_alloc(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; @@ -273,12 +271,12 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ) drm_sis_mem_t agp; PMemBlock block; int retval = 0; - + if (dev_priv == NULL || dev_priv->AGPHeap == NULL) return DRM_ERR(EINVAL); - + DRM_COPY_FROM_USER_IOCTL(agp, argp, sizeof(agp)); - + block = mmAllocMem(dev_priv->AGPHeap, agp.size, 0, 0); if (block) { /* TODO */ @@ -286,10 +284,10 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ) agp.free = (unsigned long)block; if (!add_alloc_set(agp.context, AGP_TYPE, agp.free)) { DRM_DEBUG("adding to allocation set fails\n"); - mmFreeMem((PMemBlock)agp.free); + mmFreeMem((PMemBlock) agp.free); retval = -1; } - } else { + } else { agp.offset = 0; agp.size = 0; agp.free = 0; @@ -302,7 +300,7 @@ static int sis_ioctl_agp_alloc( DRM_IOCTL_ARGS ) return retval; } -static int sis_ioctl_agp_free( DRM_IOCTL_ARGS ) +static int sis_ioctl_agp_free(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_sis_private_t *dev_priv = dev->dev_private; @@ -311,12 +309,13 @@ static int sis_ioctl_agp_free( DRM_IOCTL_ARGS ) if (dev_priv == NULL || dev_priv->AGPHeap == NULL) return DRM_ERR(EINVAL); - DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *)data, sizeof(agp)); + DRM_COPY_FROM_USER_IOCTL(agp, (drm_sis_mem_t __user *) data, + sizeof(agp)); - if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock)agp.free)) + if (!mmBlockInHeap(dev_priv->AGPHeap, (PMemBlock) agp.free)) return DRM_ERR(EINVAL); - mmFreeMem((PMemBlock)agp.free); + mmFreeMem((PMemBlock) agp.free); if (!del_alloc_set(agp.context, AGP_TYPE, agp.free)) return DRM_ERR(EINVAL); @@ -329,31 +328,30 @@ int sis_init_context(struct drm_device *dev, int context) { int i; - for (i = 0; i < MAX_CONTEXT ; i++) { + for (i = 0; i < MAX_CONTEXT; i++) { if (global_ppriv[i].used && (global_ppriv[i].context == context)) break; } if (i >= MAX_CONTEXT) { - for (i = 0; i < MAX_CONTEXT ; i++) { + for (i = 0; i < MAX_CONTEXT; i++) { if (!global_ppriv[i].used) { global_ppriv[i].context = context; global_ppriv[i].used = 1; global_ppriv[i].sets[0] = setInit(); global_ppriv[i].sets[1] = setInit(); DRM_DEBUG("init allocation set, socket=%d, " - "context = %d\n", i, context); + "context = %d\n", i, context); break; } } if ((i >= MAX_CONTEXT) || (global_ppriv[i].sets[0] == NULL) || - (global_ppriv[i].sets[1] == NULL)) - { + (global_ppriv[i].sets[1] == NULL)) { return 0; } } - + return 1; } @@ -361,7 +359,7 @@ int sis_final_context(struct drm_device *dev, int context) { int i; - for (i=0; iprimary.minor, - pci_pretty_name(dev->pdev) - ); + DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", + DRIVER_NAME, + DRIVER_MAJOR, + DRIVER_MINOR, + DRIVER_PATCHLEVEL, + DRIVER_DATE, dev->primary.minor, pci_pretty_name(dev->pdev) + ); return 0; } -static int version( drm_version_t *version ) +static int version(drm_version_t * version) { int len; version->version_major = DRIVER_MAJOR; version->version_minor = DRIVER_MINOR; version->version_patchlevel = DRIVER_PATCHLEVEL; - DRM_COPY( version->name, DRIVER_NAME ); - DRM_COPY( version->date, DRIVER_DATE ); - DRM_COPY( version->desc, DRIVER_DESC ); + DRM_COPY(version->name, DRIVER_NAME); + DRM_COPY(version->date, DRIVER_DATE); + DRM_COPY(version->desc, DRIVER_DESC); return 0; } @@ -75,18 +73,18 @@ static struct drm_driver driver = { .postinit = postinit, .version = version, .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init tdfx_init(void) @@ -102,6 +100,6 @@ static void __exit tdfx_exit(void) module_init(tdfx_init); module_exit(tdfx_exit); -MODULE_AUTHOR( DRIVER_AUTHOR ); -MODULE_DESCRIPTION( DRIVER_DESC ); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); diff --git a/drivers/char/drm/via_3d_reg.h b/drivers/char/drm/via_3d_reg.h index cf61bb514db..462375d543b 100644 --- a/drivers/char/drm/via_3d_reg.h +++ b/drivers/char/drm/via_3d_reg.h @@ -1643,7 +1643,6 @@ #define HC_HAGPBpID_STOP 0x00000002 #define HC_HAGPBpH_MASK 0x00ffffff - #define VIA_VIDEO_HEADER5 0xFE040000 #define VIA_VIDEO_HEADER6 0xFE050000 #define VIA_VIDEO_HEADER7 0xFE060000 diff --git a/drivers/char/drm/via_dma.c b/drivers/char/drm/via_dma.c index 4f60f7f4193..d4b1766608b 100644 --- a/drivers/char/drm/via_dma.c +++ b/drivers/char/drm/via_dma.c @@ -1,11 +1,11 @@ /* via_dma.c -- DMA support for the VIA Unichrome/Pro - * + * * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A. * All Rights Reserved. - * + * * Copyright 2004 The Unichrome project. * All Rights Reserved. * @@ -23,14 +23,14 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * - * Authors: - * Tungsten Graphics, - * Erdi Chen, + * Authors: + * Tungsten Graphics, + * Erdi Chen, * Thomas Hellstrom. */ @@ -61,34 +61,31 @@ dev_priv->dma_low +=8; \ } -#define via_flush_write_combine() DRM_MEMORYBARRIER() +#define via_flush_write_combine() DRM_MEMORYBARRIER() #define VIA_OUT_RING_QW(w1,w2) \ *vb++ = (w1); \ *vb++ = (w2); \ - dev_priv->dma_low += 8; + dev_priv->dma_low += 8; static void via_cmdbuf_start(drm_via_private_t * dev_priv); static void via_cmdbuf_pause(drm_via_private_t * dev_priv); static void via_cmdbuf_reset(drm_via_private_t * dev_priv); static void via_cmdbuf_rewind(drm_via_private_t * dev_priv); static int via_wait_idle(drm_via_private_t * dev_priv); -static void via_pad_cache(drm_via_private_t *dev_priv, int qwords); - +static void via_pad_cache(drm_via_private_t * dev_priv, int qwords); /* * Free space in command buffer. */ -static uint32_t -via_cmdbuf_space(drm_via_private_t *dev_priv) +static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv) { - uint32_t agp_base = dev_priv->dma_offset + - (uint32_t) dev_priv->agpAddr; + uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; - - return ((hw_addr <= dev_priv->dma_low) ? - (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : + + return ((hw_addr <= dev_priv->dma_low) ? + (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : (hw_addr - dev_priv->dma_low)); } @@ -96,15 +93,13 @@ via_cmdbuf_space(drm_via_private_t *dev_priv) * How much does the command regulator lag behind? */ -static uint32_t -via_cmdbuf_lag(drm_via_private_t *dev_priv) +static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv) { - uint32_t agp_base = dev_priv->dma_offset + - (uint32_t) dev_priv->agpAddr; + uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base; - - return ((hw_addr <= dev_priv->dma_low) ? - (dev_priv->dma_low - hw_addr) : + + return ((hw_addr <= dev_priv->dma_low) ? + (dev_priv->dma_low - hw_addr) : (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); } @@ -121,20 +116,20 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size) uint32_t count; hw_addr_ptr = dev_priv->hw_addr_ptr; cur_addr = dev_priv->dma_low; - next_addr = cur_addr + size + 512*1024; + next_addr = cur_addr + size + 512 * 1024; count = 1000000; do { - hw_addr = *hw_addr_ptr - agp_base; + hw_addr = *hw_addr_ptr - agp_base; if (count-- == 0) { - DRM_ERROR("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", - hw_addr, cur_addr, next_addr); + DRM_ERROR + ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n", + hw_addr, cur_addr, next_addr); return -1; } } while ((cur_addr < hw_addr) && (next_addr >= hw_addr)); return 0; } - /* * Checks whether buffer head has reach the end. Rewind the ring buffer * when necessary. @@ -145,7 +140,8 @@ via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size) static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv, unsigned int size) { - if ((dev_priv->dma_low + size + 4*CMDBUF_ALIGNMENT_SIZE) > dev_priv->dma_high) { + if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) > + dev_priv->dma_high) { via_cmdbuf_rewind(dev_priv); } if (via_cmdbuf_wait(dev_priv, size) != 0) { @@ -159,7 +155,7 @@ int via_dma_cleanup(drm_device_t * dev) { if (dev->dev_private) { drm_via_private_t *dev_priv = - (drm_via_private_t *) dev->dev_private; + (drm_via_private_t *) dev->dev_private; if (dev_priv->ring.virtual_start) { via_cmdbuf_reset(dev_priv); @@ -189,7 +185,7 @@ static int via_initialize(drm_device_t * dev, } if (!dev->agp || !dev->agp->base) { - DRM_ERROR("%s called with no agp memory available\n", + DRM_ERROR("%s called with no agp memory available\n", __FUNCTION__); return DRM_ERR(EFAULT); } @@ -247,10 +243,10 @@ int via_dma_init(DRM_IOCTL_ARGS) else retcode = via_dma_cleanup(dev); break; - case VIA_DMA_INITIALIZED: - retcode = (dev_priv->ring.virtual_start != NULL) ? - 0: DRM_ERR( EFAULT ); - break; + case VIA_DMA_INITIALIZED: + retcode = (dev_priv->ring.virtual_start != NULL) ? + 0 : DRM_ERR(EFAULT); + break; default: retcode = DRM_ERR(EINVAL); break; @@ -259,8 +255,6 @@ int via_dma_init(DRM_IOCTL_ARGS) return retcode; } - - static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) { drm_via_private_t *dev_priv; @@ -277,8 +271,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) if (cmd->size > VIA_PCI_BUF_SIZE) { return DRM_ERR(ENOMEM); - } - + } if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) return DRM_ERR(EFAULT); @@ -289,19 +282,19 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) * copy it to AGP memory when ready. */ - - if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 1))) { + if ((ret = + via_verify_command_stream((uint32_t *) dev_priv->pci_buf, + cmd->size, dev, 1))) { return ret; } - - + vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size); if (vb == NULL) { return DRM_ERR(EAGAIN); } memcpy(vb, dev_priv->pci_buf, cmd->size); - + dev_priv->dma_low += cmd->size; /* @@ -310,7 +303,7 @@ static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) */ if (cmd->size < 0x100) - via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3); + via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3); via_cmdbuf_pause(dev_priv); return 0; @@ -330,7 +323,7 @@ int via_flush_ioctl(DRM_IOCTL_ARGS) { DRM_DEVICE; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); return via_driver_dma_quiescent(dev); } @@ -341,7 +334,7 @@ int via_cmdbuffer(DRM_IOCTL_ARGS) drm_via_cmdbuffer_t cmdbuf; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, sizeof(cmdbuf)); @@ -356,8 +349,9 @@ int via_cmdbuffer(DRM_IOCTL_ARGS) return 0; } -extern int -via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size); +extern int +via_parse_command_stream(drm_device_t * dev, const uint32_t * buf, + unsigned int size); static int via_dispatch_pci_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd) { @@ -366,15 +360,19 @@ static int via_dispatch_pci_cmdbuffer(drm_device_t * dev, if (cmd->size > VIA_PCI_BUF_SIZE) { return DRM_ERR(ENOMEM); - } + } if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size)) return DRM_ERR(EFAULT); - - if ((ret = via_verify_command_stream((uint32_t *)dev_priv->pci_buf, cmd->size, dev, 0))) { + + if ((ret = + via_verify_command_stream((uint32_t *) dev_priv->pci_buf, + cmd->size, dev, 0))) { return ret; } - - ret = via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, cmd->size); + + ret = + via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf, + cmd->size); return ret; } @@ -384,7 +382,7 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS) drm_via_cmdbuffer_t cmdbuf; int ret; - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data, sizeof(cmdbuf)); @@ -400,17 +398,15 @@ int via_pci_cmdbuffer(DRM_IOCTL_ARGS) return 0; } - static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv, uint32_t * vb, int qw_count) { - for (; qw_count > 0; --qw_count) { + for (; qw_count > 0; --qw_count) { VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY); } return vb; } - /* * This function is used internally by ring buffer mangement code. * @@ -426,7 +422,7 @@ static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv) * modifying the pause address stored in the buffer itself. If * the regulator has already paused, restart it. */ -static int via_hook_segment(drm_via_private_t *dev_priv, +static int via_hook_segment(drm_via_private_t * dev_priv, uint32_t pause_addr_hi, uint32_t pause_addr_lo, int no_pci_fire) { @@ -434,7 +430,7 @@ static int via_hook_segment(drm_via_private_t *dev_priv, volatile uint32_t *paused_at = dev_priv->last_pause_ptr; via_flush_write_combine(); - while(! *(via_get_dma(dev_priv)-1)); + while (!*(via_get_dma(dev_priv) - 1)) ; *dev_priv->last_pause_ptr = pause_addr_lo; via_flush_write_combine(); @@ -443,55 +439,53 @@ static int via_hook_segment(drm_via_private_t *dev_priv, * Not sure it is needed. */ - while(! *dev_priv->last_pause_ptr); + while (!*dev_priv->last_pause_ptr) ; dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; - while(! *dev_priv->last_pause_ptr); - + while (!*dev_priv->last_pause_ptr) ; paused = 0; - count = 20; + count = 20; - while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--); + while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--) ; if ((count <= 8) && (count >= 0)) { uint32_t rgtr, ptr; rgtr = *(dev_priv->hw_addr_ptr); - ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + - dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 - - CMDBUF_ALIGNMENT_SIZE; + ptr = ((char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) + + dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4 - + CMDBUF_ALIGNMENT_SIZE; if (rgtr <= ptr) { - DRM_ERROR("Command regulator\npaused at count %d, address %x, " - "while current pause address is %x.\n" - "Please mail this message to " - "\n", - count, rgtr, ptr); + DRM_ERROR + ("Command regulator\npaused at count %d, address %x, " + "while current pause address is %x.\n" + "Please mail this message to " + "\n", count, + rgtr, ptr); } } - + if (paused && !no_pci_fire) { - uint32_t rgtr,ptr; + uint32_t rgtr, ptr; uint32_t ptr_low; count = 1000000; - while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) && count--); - + while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY) + && count--) ; + rgtr = *(dev_priv->hw_addr_ptr); - ptr = ((char *)paused_at - dev_priv->dma_ptr) + - dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; - + ptr = ((char *)paused_at - dev_priv->dma_ptr) + + dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; - ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ? - ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0; + ptr_low = (ptr > 3 * CMDBUF_ALIGNMENT_SIZE) ? + ptr - 3 * CMDBUF_ALIGNMENT_SIZE : 0; if (rgtr <= ptr && rgtr >= ptr_low) { VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); - } + } } return paused; } - - static int via_wait_idle(drm_via_private_t * dev_priv) { int count = 10000000; @@ -502,9 +496,8 @@ static int via_wait_idle(drm_via_private_t * dev_priv) } static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type, - uint32_t addr, uint32_t *cmd_addr_hi, - uint32_t *cmd_addr_lo, - int skip_wait) + uint32_t addr, uint32_t * cmd_addr_hi, + uint32_t * cmd_addr_lo, int skip_wait) { uint32_t agp_base; uint32_t cmd_addr, addr_lo, addr_hi; @@ -512,31 +505,26 @@ static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type, uint32_t qw_pad_count; if (!skip_wait) - via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE); + via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE); vb = via_get_dma(dev_priv); - VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | - (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); + VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) | + (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16); agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) - - ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); + ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3); - - cmd_addr = (addr) ? addr : - agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); + cmd_addr = (addr) ? addr : + agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3); addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) | (cmd_addr & HC_HAGPBpL_MASK)); addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24)); vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1); - VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, - *cmd_addr_lo = addr_lo); + VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo); return vb; } - - - static void via_cmdbuf_start(drm_via_private_t * dev_priv) { uint32_t pause_addr_lo, pause_addr_hi; @@ -545,7 +533,6 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv) uint32_t command; uint32_t agp_base; - dev_priv->dma_low = 0; agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; @@ -557,12 +544,12 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv) command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) | ((end_addr & 0xff000000) >> 16)); - dev_priv->last_pause_ptr = - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, - &pause_addr_hi, & pause_addr_lo, 1) - 1; + dev_priv->last_pause_ptr = + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, + &pause_addr_hi, &pause_addr_lo, 1) - 1; via_flush_write_combine(); - while(! *dev_priv->last_pause_ptr); + while (!*dev_priv->last_pause_ptr) ; VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); VIA_WRITE(VIA_REG_TRANSPACE, command); @@ -575,14 +562,14 @@ static void via_cmdbuf_start(drm_via_private_t * dev_priv) VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); } -static void via_pad_cache(drm_via_private_t *dev_priv, int qwords) +static void via_pad_cache(drm_via_private_t * dev_priv, int qwords) { uint32_t *vb; via_cmdbuf_wait(dev_priv, qwords + 2); vb = via_get_dma(dev_priv); - VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16); - via_align_buffer(dev_priv,vb,qwords); + VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16); + via_align_buffer(dev_priv, vb, qwords); } static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) @@ -590,10 +577,9 @@ static inline void via_dummy_bitblt(drm_via_private_t * dev_priv) uint32_t *vb = via_get_dma(dev_priv); SetReg2DAGP(0x0C, (0 | (0 << 16))); SetReg2DAGP(0x10, 0 | (0 << 16)); - SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); + SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000); } - static void via_cmdbuf_jump(drm_via_private_t * dev_priv) { uint32_t agp_base; @@ -603,11 +589,10 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv) uint32_t dma_low_save1, dma_low_save2; agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; - via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, + via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi, &jump_addr_lo, 0); - - dev_priv->dma_wrap = dev_priv->dma_low; + dev_priv->dma_wrap = dev_priv->dma_low; /* * Wrap command buffer to the beginning. @@ -619,11 +604,12 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv) } via_dummy_bitblt(dev_priv); - via_dummy_bitblt(dev_priv); + via_dummy_bitblt(dev_priv); - last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, - &pause_addr_lo, 0) -1; - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + last_pause_ptr = + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + &pause_addr_lo, 0) - 1; + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, &pause_addr_lo, 0); *last_pause_ptr = pause_addr_lo; @@ -638,23 +624,23 @@ static void via_cmdbuf_jump(drm_via_private_t * dev_priv) * does not seem to get updated immediately when a jump occurs. */ - last_pause_ptr = via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, - &pause_addr_lo, 0) -1; - via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + last_pause_ptr = + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, + &pause_addr_lo, 0) - 1; + via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi, &pause_addr_lo, 0); *last_pause_ptr = pause_addr_lo; dma_low_save2 = dev_priv->dma_low; - dev_priv->dma_low = dma_low_save1; - via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0); + dev_priv->dma_low = dma_low_save1; + via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0); dev_priv->dma_low = dma_low_save2; - via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0); + via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); } - static void via_cmdbuf_rewind(drm_via_private_t * dev_priv) { - via_cmdbuf_jump(dev_priv); + via_cmdbuf_jump(dev_priv); } static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type) @@ -662,10 +648,9 @@ static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type) uint32_t pause_addr_lo, pause_addr_hi; via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0); - via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0); + via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0); } - static void via_cmdbuf_pause(drm_via_private_t * dev_priv) { via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE); @@ -681,8 +666,7 @@ static void via_cmdbuf_reset(drm_via_private_t * dev_priv) * User interface to the space and lag functions. */ -int -via_cmdbuf_size(DRM_IOCTL_ARGS) +int via_cmdbuf_size(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_via_cmdbuf_size_t d_siz; @@ -691,7 +675,7 @@ via_cmdbuf_size(DRM_IOCTL_ARGS) drm_via_private_t *dev_priv; DRM_DEBUG("via cmdbuf_size\n"); - LOCK_TEST_WITH_RETURN( dev, filp ); + LOCK_TEST_WITH_RETURN(dev, filp); dev_priv = (drm_via_private_t *) dev->dev_private; @@ -704,12 +688,12 @@ via_cmdbuf_size(DRM_IOCTL_ARGS) DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data, sizeof(d_siz)); - count = 1000000; tmp_size = d_siz.size; - switch(d_siz.func) { + switch (d_siz.func) { case VIA_CMDBUF_SPACE: - while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) && count--) { + while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size) + && count--) { if (!d_siz.wait) { break; } @@ -720,7 +704,8 @@ via_cmdbuf_size(DRM_IOCTL_ARGS) } break; case VIA_CMDBUF_LAG: - while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) && count--) { + while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size) + && count--) { if (!d_siz.wait) { break; } diff --git a/drivers/char/drm/via_drm.h b/drivers/char/drm/via_drm.h index be346bb0a26..ebde9206115 100644 --- a/drivers/char/drm/via_drm.h +++ b/drivers/char/drm/via_drm.h @@ -149,7 +149,7 @@ typedef struct _drm_via_dma_init { enum { VIA_INIT_DMA = 0x01, VIA_CLEANUP_DMA = 0x02, - VIA_DMA_INITIALIZED = 0x03 + VIA_DMA_INITIALIZED = 0x03 } func; unsigned long offset; @@ -212,7 +212,7 @@ typedef enum { #define VIA_IRQ_FLAGS_MASK 0xF0000000 -struct drm_via_wait_irq_request{ +struct drm_via_wait_irq_request { unsigned irq; via_irq_seq_type_t type; uint32_t sequence; diff --git a/drivers/char/drm/via_drv.c b/drivers/char/drm/via_drv.c index 275eefc7922..016665e0c69 100644 --- a/drivers/char/drm/via_drv.c +++ b/drivers/char/drm/via_drv.c @@ -93,18 +93,18 @@ static struct drm_driver driver = { .ioctls = ioctls, .num_ioctls = DRM_ARRAY_SIZE(ioctls), .fops = { - .owner = THIS_MODULE, - .open = drm_open, - .release = drm_release, - .ioctl = drm_ioctl, - .mmap = drm_mmap, - .poll = drm_poll, - .fasync = drm_fasync, - }, + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .ioctl = drm_ioctl, + .mmap = drm_mmap, + .poll = drm_poll, + .fasync = drm_fasync, + }, .pci_driver = { - .name = DRIVER_NAME, - .id_table = pciidlist, - } + .name = DRIVER_NAME, + .id_table = pciidlist, + } }; static int __init via_init(void) diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h index 4eaa8b7c4c9..d902dc2f4fa 100644 --- a/drivers/char/drm/via_drv.h +++ b/drivers/char/drm/via_drv.h @@ -40,8 +40,6 @@ #define VIA_FIRE_BUF_SIZE 1024 #define VIA_NUM_IRQS 2 - - typedef struct drm_via_ring_buffer { drm_map_t map; char *virtual_start; @@ -55,7 +53,7 @@ typedef struct drm_via_irq { uint32_t enable_mask; wait_queue_head_t irq_queue; } drm_via_irq_t; - + typedef struct drm_via_private { drm_via_sarea_t *sarea_priv; drm_map_t *sarea; @@ -71,9 +69,9 @@ typedef struct drm_via_private { volatile uint32_t *last_pause_ptr; volatile uint32_t *hw_addr_ptr; drm_via_ring_buffer_t ring; - struct timeval last_vblank; - int last_vblank_valid; - unsigned usec_per_vblank; + struct timeval last_vblank; + int last_vblank_valid; + unsigned usec_per_vblank; drm_via_state_t hc_state; char pci_buf[VIA_PCI_BUF_SIZE]; const uint32_t *fire_offsets[VIA_FIRE_BUF_SIZE]; @@ -82,8 +80,8 @@ typedef struct drm_via_private { drm_via_irq_t via_irqs[VIA_NUM_IRQS]; unsigned num_irqs; maskarray_t *irq_masks; - uint32_t irq_enable_mask; - uint32_t irq_pending_mask; + uint32_t irq_enable_mask; + uint32_t irq_pending_mask; } drm_via_private_t; /* VIA MMIO register access */ @@ -110,9 +108,8 @@ extern void via_driver_irq_uninstall(drm_device_t * dev); extern int via_dma_cleanup(drm_device_t * dev); extern void via_init_command_verifier(void); extern int via_driver_dma_quiescent(drm_device_t * dev); -extern void via_init_futex(drm_via_private_t *dev_priv); -extern void via_cleanup_futex(drm_via_private_t *dev_priv); -extern void via_release_futex(drm_via_private_t *dev_priv, int context); - +extern void via_init_futex(drm_via_private_t * dev_priv); +extern void via_cleanup_futex(drm_via_private_t * dev_priv); +extern void via_release_futex(drm_via_private_t * dev_priv, int context); #endif diff --git a/drivers/char/drm/via_irq.c b/drivers/char/drm/via_irq.c index e8027f3a93b..d023add1929 100644 --- a/drivers/char/drm/via_irq.c +++ b/drivers/char/drm/via_irq.c @@ -54,23 +54,26 @@ /* * Device-specific IRQs go here. This type might need to be extended with * the register if there are multiple IRQ control registers. - * Currently we activate the HQV interrupts of Unichrome Pro group A. + * Currently we activate the HQV interrupts of Unichrome Pro group A. */ static maskarray_t via_pro_group_a_irqs[] = { - {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, 0x00000000 }, - {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, 0x00000000 }}; -static int via_num_pro_group_a = sizeof(via_pro_group_a_irqs)/sizeof(maskarray_t); - -static maskarray_t via_unichrome_irqs[] = {}; -static int via_num_unichrome = sizeof(via_unichrome_irqs)/sizeof(maskarray_t); - - -static unsigned time_diff(struct timeval *now,struct timeval *then) + {VIA_IRQ_HQV0_ENABLE, VIA_IRQ_HQV0_PENDING, 0x000003D0, 0x00008010, + 0x00000000}, + {VIA_IRQ_HQV1_ENABLE, VIA_IRQ_HQV1_PENDING, 0x000013D0, 0x00008010, + 0x00000000} +}; +static int via_num_pro_group_a = + sizeof(via_pro_group_a_irqs) / sizeof(maskarray_t); + +static maskarray_t via_unichrome_irqs[] = { }; +static int via_num_unichrome = sizeof(via_unichrome_irqs) / sizeof(maskarray_t); + +static unsigned time_diff(struct timeval *now, struct timeval *then) { - return (now->tv_usec >= then->tv_usec) ? - now->tv_usec - then->tv_usec : - 1000000 - (then->tv_usec - now->tv_usec); + return (now->tv_usec >= then->tv_usec) ? + now->tv_usec - then->tv_usec : + 1000000 - (then->tv_usec - now->tv_usec); } irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) @@ -86,38 +89,37 @@ irqreturn_t via_driver_irq_handler(DRM_IRQ_ARGS) status = VIA_READ(VIA_REG_INTERRUPT); if (status & VIA_IRQ_VBLANK_PENDING) { atomic_inc(&dev->vbl_received); - if (!(atomic_read(&dev->vbl_received) & 0x0F)) { + if (!(atomic_read(&dev->vbl_received) & 0x0F)) { do_gettimeofday(&cur_vblank); - if (dev_priv->last_vblank_valid) { - dev_priv->usec_per_vblank = - time_diff( &cur_vblank,&dev_priv->last_vblank) >> 4; + if (dev_priv->last_vblank_valid) { + dev_priv->usec_per_vblank = + time_diff(&cur_vblank, + &dev_priv->last_vblank) >> 4; } dev_priv->last_vblank = cur_vblank; dev_priv->last_vblank_valid = 1; - } - if (!(atomic_read(&dev->vbl_received) & 0xFF)) { + } + if (!(atomic_read(&dev->vbl_received) & 0xFF)) { DRM_DEBUG("US per vblank is: %u\n", - dev_priv->usec_per_vblank); + dev_priv->usec_per_vblank); } DRM_WAKEUP(&dev->vbl_queue); drm_vbl_send_signals(dev); handled = 1; } - - for (i=0; inum_irqs; ++i) { + for (i = 0; i < dev_priv->num_irqs; ++i) { if (status & cur_irq->pending_mask) { - atomic_inc( &cur_irq->irq_received ); - DRM_WAKEUP( &cur_irq->irq_queue ); + atomic_inc(&cur_irq->irq_received); + DRM_WAKEUP(&cur_irq->irq_queue); handled = 1; } cur_irq++; } - + /* Acknowlege interrupts */ VIA_WRITE(VIA_REG_INTERRUPT, status); - if (handled) return IRQ_HANDLED; else @@ -131,7 +133,7 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t * dev_priv) if (dev_priv) { /* Acknowlege interrupts */ status = VIA_READ(VIA_REG_INTERRUPT); - VIA_WRITE(VIA_REG_INTERRUPT, status | + VIA_WRITE(VIA_REG_INTERRUPT, status | dev_priv->irq_pending_mask); } } @@ -158,12 +160,12 @@ int via_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence) DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ, (((cur_vblank = atomic_read(&dev->vbl_received)) - *sequence) <= (1 << 23))); - + *sequence = cur_vblank; return ret; } -static int +static int via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence, unsigned int *sequence) { @@ -180,27 +182,29 @@ via_driver_irq_wait(drm_device_t * dev, unsigned int irq, int force_sequence, return DRM_ERR(EINVAL); } - if (irq >= dev_priv->num_irqs ) { - DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irq); + if (irq >= dev_priv->num_irqs) { + DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, + irq); return DRM_ERR(EINVAL); } - + cur_irq += irq; if (masks[irq][2] && !force_sequence) { DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, - ((VIA_READ(masks[irq][2]) & masks[irq][3]) == masks[irq][4])); + ((VIA_READ(masks[irq][2]) & masks[irq][3]) == + masks[irq][4])); cur_irq_sequence = atomic_read(&cur_irq->irq_received); } else { DRM_WAIT_ON(ret, cur_irq->irq_queue, 3 * DRM_HZ, - (((cur_irq_sequence = atomic_read(&cur_irq->irq_received)) - - *sequence) <= (1 << 23))); + (((cur_irq_sequence = + atomic_read(&cur_irq->irq_received)) - + *sequence) <= (1 << 23))); } *sequence = cur_irq_sequence; return ret; } - /* * drm_dma.h hooks */ @@ -219,29 +223,29 @@ void via_driver_irq_preinstall(drm_device_t * dev) dev_priv->irq_pending_mask = VIA_IRQ_VBLANK_PENDING; dev_priv->irq_masks = (dev_priv->pro_group_a) ? - via_pro_group_a_irqs : via_unichrome_irqs; + via_pro_group_a_irqs : via_unichrome_irqs; dev_priv->num_irqs = (dev_priv->pro_group_a) ? - via_num_pro_group_a : via_num_unichrome; - - for(i=0; i < dev_priv->num_irqs; ++i) { + via_num_pro_group_a : via_num_unichrome; + + for (i = 0; i < dev_priv->num_irqs; ++i) { atomic_set(&cur_irq->irq_received, 0); - cur_irq->enable_mask = dev_priv->irq_masks[i][0]; + cur_irq->enable_mask = dev_priv->irq_masks[i][0]; cur_irq->pending_mask = dev_priv->irq_masks[i][1]; - DRM_INIT_WAITQUEUE( &cur_irq->irq_queue ); + DRM_INIT_WAITQUEUE(&cur_irq->irq_queue); dev_priv->irq_enable_mask |= cur_irq->enable_mask; dev_priv->irq_pending_mask |= cur_irq->pending_mask; cur_irq++; - + DRM_DEBUG("Initializing IRQ %d\n", i); } - - dev_priv->last_vblank_valid = 0; + + dev_priv->last_vblank_valid = 0; // Clear VSync interrupt regs status = VIA_READ(VIA_REG_INTERRUPT); - VIA_WRITE(VIA_REG_INTERRUPT, status & + VIA_WRITE(VIA_REG_INTERRUPT, status & ~(dev_priv->irq_enable_mask)); - + /* Clear bits if they're already high */ viadrv_acknowledge_irqs(dev_priv); } @@ -262,7 +266,7 @@ void via_driver_irq_postinstall(drm_device_t * dev) VIA_WRITE8(0x83d4, 0x11); VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) | 0x30); - + } } @@ -280,7 +284,7 @@ void via_driver_irq_uninstall(drm_device_t * dev) VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); status = VIA_READ(VIA_REG_INTERRUPT); - VIA_WRITE(VIA_REG_INTERRUPT, status & + VIA_WRITE(VIA_REG_INTERRUPT, status & ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask)); } } @@ -302,7 +306,7 @@ int via_wait_irq(DRM_IOCTL_ARGS) DRM_COPY_FROM_USER_IOCTL(irqwait, argp, sizeof(irqwait)); if (irqwait.request.irq >= dev_priv->num_irqs) { - DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, + DRM_ERROR("%s Trying to wait on unknown irq %d\n", __FUNCTION__, irqwait.request.irq); return DRM_ERR(EINVAL); } @@ -320,7 +324,7 @@ int via_wait_irq(DRM_IOCTL_ARGS) } if (irqwait.request.type & VIA_IRQ_SIGNAL) { - DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n", + DRM_ERROR("%s Signals on Via IRQs not implemented yet.\n", __FUNCTION__); return DRM_ERR(EINVAL); } diff --git a/drivers/char/drm/via_map.c b/drivers/char/drm/via_map.c index bb171139e73..6bd6ac52ad1 100644 --- a/drivers/char/drm/via_map.c +++ b/drivers/char/drm/via_map.c @@ -66,7 +66,7 @@ static int via_do_init_map(drm_device_t * dev, drm_via_init_t * init) dev_priv->agpAddr = init->agpAddr; - via_init_futex( dev_priv ); + via_init_futex(dev_priv); dev_priv->pro_group_a = (dev->pdev->device == 0x3118); dev->dev_private = (void *)dev_priv; @@ -107,5 +107,3 @@ int via_map_init(DRM_IOCTL_ARGS) return -EINVAL; } - - diff --git a/drivers/char/drm/via_mm.c b/drivers/char/drm/via_mm.c index 13921f3c0ec..3baddacdff2 100644 --- a/drivers/char/drm/via_mm.c +++ b/drivers/char/drm/via_mm.c @@ -81,7 +81,8 @@ int via_agp_init(DRM_IOCTL_ARGS) AgpHeap = via_mmInit(agp.offset, agp.size); - DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset, (unsigned long)agp.size); + DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)agp.offset, + (unsigned long)agp.size); return 0; } @@ -97,7 +98,8 @@ int via_fb_init(DRM_IOCTL_ARGS) FBHeap = via_mmInit(fb.offset, fb.size); - DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset, (unsigned long)fb.size); + DRM_DEBUG("offset = %lu, size = %lu", (unsigned long)fb.offset, + (unsigned long)fb.size); return 0; } @@ -134,8 +136,8 @@ int via_init_context(struct drm_device *dev, int context) } int via_final_context(struct drm_device *dev, int context) -{ - int i; +{ + int i; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; for (i = 0; i < MAX_CONTEXT; i++) @@ -171,14 +173,13 @@ int via_final_context(struct drm_device *dev, int context) via_setDestroy(set); global_ppriv[i].used = 0; } - via_release_futex(dev_priv, context); - - + via_release_futex(dev_priv, context); + #if defined(__linux__) /* Linux specific until context tracking code gets ported to BSD */ /* Last context, perform cleanup */ if (dev->ctx_count == 1 && dev->dev_private) { - DRM_DEBUG("Last Context\n"); + DRM_DEBUG("Last Context\n"); if (dev->irq) drm_irq_uninstall(dev); diff --git a/drivers/char/drm/via_verifier.c b/drivers/char/drm/via_verifier.c index 07923b0c7a9..4ac495f297f 100644 --- a/drivers/char/drm/via_verifier.c +++ b/drivers/char/drm/via_verifier.c @@ -28,7 +28,6 @@ * be very slow. */ - #include "via_3d_reg.h" #include "drmP.h" #include "drm.h" @@ -36,7 +35,7 @@ #include "via_verifier.h" #include "via_drv.h" -typedef enum{ +typedef enum { state_command, state_header2, state_header1, @@ -45,8 +44,7 @@ typedef enum{ state_error } verifier_state_t; - -typedef enum{ +typedef enum { no_check = 0, check_for_header2, check_for_header1, @@ -74,16 +72,16 @@ typedef enum{ check_for_vertex_count, check_number_texunits, forbidden_command -}hazard_t; +} hazard_t; /* * Associates each hazard above with a possible multi-command * sequence. For example an address that is split over multiple - * commands and that needs to be checked at the first command + * commands and that needs to be checked at the first command * that does not include any part of the address. */ -static drm_via_sequence_t seqs[] = { +static drm_via_sequence_t seqs[] = { no_sequence, no_sequence, no_sequence, @@ -110,14 +108,12 @@ static drm_via_sequence_t seqs[] = { tex_address, no_sequence }; - -typedef struct{ + +typedef struct { unsigned int code; hazard_t hz; } hz_init_t; - - static hz_init_t init_table1[] = { {0xf2, check_for_header2_err}, {0xf0, check_for_header1_err}, @@ -169,8 +165,6 @@ static hz_init_t init_table1[] = { {0x7D, check_for_vertex_count} }; - - static hz_init_t init_table2[] = { {0xf2, check_for_header2_err}, {0xf0, check_for_header1_err}, @@ -235,49 +229,49 @@ static hz_init_t init_table3[] = { {0xcc, check_for_dummy}, {0x00, check_number_texunits} }; - - -static hazard_t table1[256]; -static hazard_t table2[256]; -static hazard_t table3[256]; - +static hazard_t table1[256]; +static hazard_t table2[256]; +static hazard_t table3[256]; static __inline__ int -eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) +eat_words(const uint32_t ** buf, const uint32_t * buf_end, unsigned num_words) { if ((*buf - buf_end) >= num_words) { *buf += num_words; return 0; - } + } DRM_ERROR("Illegal termination of DMA command buffer\n"); return 1; } - /* * Partially stolen from drm_memory.h */ -static __inline__ drm_map_t * -via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned long size, - drm_device_t *dev) +static __inline__ drm_map_t *via_drm_lookup_agp_map(drm_via_state_t * seq, + unsigned long offset, + unsigned long size, + drm_device_t * dev) { struct list_head *list; drm_map_list_t *r_list; drm_map_t *map = seq->map_cache; - if (map && map->offset <= offset && (offset + size) <= (map->offset + map->size)) { + if (map && map->offset <= offset + && (offset + size) <= (map->offset + map->size)) { return map; } - + list_for_each(list, &dev->maplist->head) { r_list = (drm_map_list_t *) list; map = r_list->map; if (!map) continue; - if (map->offset <= offset && (offset + size) <= (map->offset + map->size) && - !(map->flags & _DRM_RESTRICTED) && (map->type == _DRM_AGP)) { + if (map->offset <= offset + && (offset + size) <= (map->offset + map->size) + && !(map->flags & _DRM_RESTRICTED) + && (map->type == _DRM_AGP)) { seq->map_cache = map; return map; } @@ -285,54 +279,60 @@ via_drm_lookup_agp_map (drm_via_state_t *seq, unsigned long offset, unsigned lon return NULL; } - /* - * Require that all AGP texture levels reside in the same AGP map which should + * Require that all AGP texture levels reside in the same AGP map which should * be mappable by the client. This is not a big restriction. - * FIXME: To actually enforce this security policy strictly, drm_rmmap - * would have to wait for dma quiescent before removing an AGP map. + * FIXME: To actually enforce this security policy strictly, drm_rmmap + * would have to wait for dma quiescent before removing an AGP map. * The via_drm_lookup_agp_map call in reality seems to take * very little CPU time. */ - -static __inline__ int -finish_current_sequence(drm_via_state_t *cur_seq) +static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq) { - switch(cur_seq->unfinished) { + switch (cur_seq->unfinished) { case z_address: DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr); break; case dest_address: - DRM_DEBUG("Destination start address is 0x%x\n", cur_seq->d_addr); + DRM_DEBUG("Destination start address is 0x%x\n", + cur_seq->d_addr); break; case tex_address: - if (cur_seq->agp_texture) { - unsigned start = cur_seq->tex_level_lo[cur_seq->texture]; + if (cur_seq->agp_texture) { + unsigned start = + cur_seq->tex_level_lo[cur_seq->texture]; unsigned end = cur_seq->tex_level_hi[cur_seq->texture]; - unsigned long lo=~0, hi=0, tmp; + unsigned long lo = ~0, hi = 0, tmp; uint32_t *addr, *pitch, *height, tex; unsigned i; - if (end > 9) end = 9; - if (start > 9) start = 9; + if (end > 9) + end = 9; + if (start > 9) + start = 9; - addr =&(cur_seq->t_addr[tex = cur_seq->texture][start]); + addr = + &(cur_seq->t_addr[tex = cur_seq->texture][start]); pitch = &(cur_seq->pitch[tex][start]); height = &(cur_seq->height[tex][start]); - for (i=start; i<= end; ++i) { + for (i = start; i <= end; ++i) { tmp = *addr++; - if (tmp < lo) lo = tmp; + if (tmp < lo) + lo = tmp; tmp += (*height++ << *pitch++); - if (tmp > hi) hi = tmp; + if (tmp > hi) + hi = tmp; } - if (! via_drm_lookup_agp_map (cur_seq, lo, hi - lo, cur_seq->dev)) { - DRM_ERROR("AGP texture is not in allowed map\n"); + if (!via_drm_lookup_agp_map + (cur_seq, lo, hi - lo, cur_seq->dev)) { + DRM_ERROR + ("AGP texture is not in allowed map\n"); return 2; } - } + } break; default: break; @@ -341,73 +341,84 @@ finish_current_sequence(drm_via_state_t *cur_seq) return 0; } -static __inline__ int -investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) +static __inline__ int +investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t * cur_seq) { register uint32_t tmp, *tmp_addr; if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) { int ret; - if ((ret = finish_current_sequence(cur_seq))) return ret; + if ((ret = finish_current_sequence(cur_seq))) + return ret; } - switch(hz) { + switch (hz) { case check_for_header2: - if (cmd == HALCYON_HEADER2) return 1; + if (cmd == HALCYON_HEADER2) + return 1; return 0; case check_for_header1: - if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; + if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) + return 1; return 0; case check_for_header2_err: - if (cmd == HALCYON_HEADER2) return 1; + if (cmd == HALCYON_HEADER2) + return 1; DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n"); break; case check_for_header1_err: - if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1; + if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) + return 1; DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n"); break; case check_for_fire: - if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) return 1; + if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) + return 1; DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n"); break; case check_for_dummy: - if (HC_DUMMY == cmd) return 0; + if (HC_DUMMY == cmd) + return 0; DRM_ERROR("Illegal DMA HC_DUMMY command\n"); break; case check_for_dd: - if (0xdddddddd == cmd) return 0; + if (0xdddddddd == cmd) + return 0; DRM_ERROR("Illegal DMA 0xdddddddd command\n"); break; case check_z_buffer_addr0: cur_seq->unfinished = z_address; cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) | - (cmd & 0x00FFFFFF); + (cmd & 0x00FFFFFF); return 0; case check_z_buffer_addr1: cur_seq->unfinished = z_address; cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) | - ((cmd & 0xFF) << 24); + ((cmd & 0xFF) << 24); return 0; case check_z_buffer_addr_mode: cur_seq->unfinished = z_address; - if ((cmd & 0x0000C000) == 0) return 0; + if ((cmd & 0x0000C000) == 0) + return 0; DRM_ERROR("Attempt to place Z buffer in system memory\n"); return 2; case check_destination_addr0: cur_seq->unfinished = dest_address; cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) | - (cmd & 0x00FFFFFF); + (cmd & 0x00FFFFFF); return 0; case check_destination_addr1: cur_seq->unfinished = dest_address; cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) | - ((cmd & 0xFF) << 24); + ((cmd & 0xFF) << 24); return 0; case check_destination_addr_mode: cur_seq->unfinished = dest_address; - if ((cmd & 0x0000C000) == 0) return 0; - DRM_ERROR("Attempt to place 3D drawing buffer in system memory\n"); - return 2; + if ((cmd & 0x0000C000) == 0) + return 0; + DRM_ERROR + ("Attempt to place 3D drawing buffer in system memory\n"); + return 2; case check_texture_addr0: cur_seq->unfinished = tex_address; tmp = (cmd >> 24); @@ -433,9 +444,11 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) case check_texture_addr3: cur_seq->unfinished = tex_address; tmp = ((cmd >> 24) - 0x2B); - cur_seq->pitch[cur_seq->texture][tmp] = (cmd & 0x00F00000) >> 20; + cur_seq->pitch[cur_seq->texture][tmp] = + (cmd & 0x00F00000) >> 20; if (!tmp && (cmd & 0x000FFFFF)) { - DRM_ERROR("Unimplemented texture level 0 pitch mode.\n"); + DRM_ERROR + ("Unimplemented texture level 0 pitch mode.\n"); return 2; } return 0; @@ -449,7 +462,7 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) cur_seq->unfinished = tex_address; /* * Texture width. We don't care since we have the pitch. - */ + */ return 0; case check_texture_addr7: cur_seq->unfinished = tex_address; @@ -465,25 +478,26 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) cur_seq->unfinished = tex_address; tmp_addr = &(cur_seq->height[cur_seq->texture][0]); tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12); - tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8); + tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8); tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4); tmp_addr[6] = 1 << (cmd & 0x0000000F); return 0; case check_texture_addr_mode: cur_seq->unfinished = tex_address; - if ( 2 == (tmp = cmd & 0x00000003)) { - DRM_ERROR("Attempt to fetch texture from system memory.\n"); + if (2 == (tmp = cmd & 0x00000003)) { + DRM_ERROR + ("Attempt to fetch texture from system memory.\n"); return 2; } cur_seq->agp_texture = (tmp == 3); - cur_seq->tex_palette_size[cur_seq->texture] = - (cmd >> 16) & 0x000000007; + cur_seq->tex_palette_size[cur_seq->texture] = + (cmd >> 16) & 0x000000007; return 0; case check_for_vertex_count: cur_seq->vertex_count = cmd & 0x0000FFFF; return 0; case check_number_texunits: - cur_seq->multitex = (cmd >> 3) & 1; + cur_seq->multitex = (cmd >> 3) & 1; return 0; default: DRM_ERROR("Illegal DMA data: 0x%x\n", cmd); @@ -492,25 +506,27 @@ investigate_hazard( uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) return 2; } - static __inline__ int -via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end, - drm_via_state_t *cur_seq) +via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end, + drm_via_state_t * cur_seq) { - drm_via_private_t *dev_priv = (drm_via_private_t *) cur_seq->dev->dev_private; - uint32_t a_fire, bcmd , dw_count; + drm_via_private_t *dev_priv = + (drm_via_private_t *) cur_seq->dev->dev_private; + uint32_t a_fire, bcmd, dw_count; int ret = 0; int have_fire; const uint32_t *buf = *buffer; - while(buf < buf_end) { - have_fire = 0; + while (buf < buf_end) { + have_fire = 0; if ((buf_end - buf) < 2) { - DRM_ERROR("Unexpected termination of primitive list.\n"); + DRM_ERROR + ("Unexpected termination of primitive list.\n"); ret = 1; break; } - if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) break; + if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdB) + break; bcmd = *buf++; if ((*buf & HC_ACMD_MASK) != HC_ACMD_HCmdA) { DRM_ERROR("Expected Vertex List A command, got 0x%x\n", @@ -518,43 +534,56 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end, ret = 1; break; } - a_fire = *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | HC_HE3Fire_MASK; - + a_fire = + *buf++ | HC_HPLEND_MASK | HC_HPMValidN_MASK | + HC_HE3Fire_MASK; + /* * How many dwords per vertex ? - */ - + */ + if (cur_seq->agp && ((bcmd & (0xF << 11)) == 0)) { DRM_ERROR("Illegal B command vertex data for AGP.\n"); ret = 1; break; - } + } dw_count = 0; - if (bcmd & (1 << 7)) dw_count += (cur_seq->multitex) ? 2:1; - if (bcmd & (1 << 8)) dw_count += (cur_seq->multitex) ? 2:1; - if (bcmd & (1 << 9)) dw_count++; - if (bcmd & (1 << 10)) dw_count++; - if (bcmd & (1 << 11)) dw_count++; - if (bcmd & (1 << 12)) dw_count++; - if (bcmd & (1 << 13)) dw_count++; - if (bcmd & (1 << 14)) dw_count++; - - while(buf < buf_end) { + if (bcmd & (1 << 7)) + dw_count += (cur_seq->multitex) ? 2 : 1; + if (bcmd & (1 << 8)) + dw_count += (cur_seq->multitex) ? 2 : 1; + if (bcmd & (1 << 9)) + dw_count++; + if (bcmd & (1 << 10)) + dw_count++; + if (bcmd & (1 << 11)) + dw_count++; + if (bcmd & (1 << 12)) + dw_count++; + if (bcmd & (1 << 13)) + dw_count++; + if (bcmd & (1 << 14)) + dw_count++; + + while (buf < buf_end) { if (*buf == a_fire) { - if (dev_priv->num_fire_offsets >= VIA_FIRE_BUF_SIZE) { + if (dev_priv->num_fire_offsets >= + VIA_FIRE_BUF_SIZE) { DRM_ERROR("Fire offset buffer full.\n"); ret = 1; break; } - dev_priv->fire_offsets[dev_priv->num_fire_offsets++] = buf; - have_fire = 1; + dev_priv->fire_offsets[dev_priv-> + num_fire_offsets++] = + buf; + have_fire = 1; buf++; - if (buf < buf_end && *buf == a_fire) + if (buf < buf_end && *buf == a_fire) buf++; break; } - if ((*buf == HALCYON_HEADER2) || + if ((*buf == HALCYON_HEADER2) || ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) { DRM_ERROR("Missing Vertex Fire command, " "Stray Vertex Fire command or verifier " @@ -576,18 +605,14 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t *buf_end, ret = 1; break; } - } + } *buffer = buf; return ret; } - - - - static __inline__ verifier_state_t -via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, - drm_via_state_t *hc_state) +via_check_header2(uint32_t const **buffer, const uint32_t * buf_end, + drm_via_state_t * hc_state) { uint32_t cmd; int hz_mode; @@ -595,17 +620,17 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, const uint32_t *buf = *buffer; const hazard_t *hz_table; - if ((buf_end - buf) < 2) { - DRM_ERROR("Illegal termination of DMA HALCYON_HEADER2 sequence.\n"); + DRM_ERROR + ("Illegal termination of DMA HALCYON_HEADER2 sequence.\n"); return state_error; } buf++; cmd = (*buf++ & 0xFFFF0000) >> 16; - switch(cmd) { + switch (cmd) { case HC_ParaType_CmdVdata: - if (via_check_prim_list(&buf, buf_end, hc_state )) + if (via_check_prim_list(&buf, buf_end, hc_state)) return state_error; *buffer = buf; return state_command; @@ -650,13 +675,13 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, */ DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 " - "DMA subcommand: 0x%x. Previous dword: 0x%x\n", - cmd, *(buf -2)); + "DMA subcommand: 0x%x. Previous dword: 0x%x\n", + cmd, *(buf - 2)); *buffer = buf; return state_error; } - while(buf < buf_end) { + while (buf < buf_end) { cmd = *buf++; if ((hz = hz_table[cmd >> 24])) { if ((hz_mode = investigate_hazard(cmd, hz, hc_state))) { @@ -666,7 +691,7 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, } return state_error; } - } else if (hc_state->unfinished && + } else if (hc_state->unfinished && finish_current_sequence(hc_state)) { return state_error; } @@ -679,64 +704,65 @@ via_check_header2( uint32_t const **buffer, const uint32_t *buf_end, } static __inline__ verifier_state_t -via_parse_header2( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end, - int *fire_count) +via_parse_header2(drm_via_private_t * dev_priv, uint32_t const **buffer, + const uint32_t * buf_end, int *fire_count) { uint32_t cmd; const uint32_t *buf = *buffer; - const uint32_t *next_fire; + const uint32_t *next_fire; int burst = 0; next_fire = dev_priv->fire_offsets[*fire_count]; buf++; cmd = (*buf & 0xFFFF0000) >> 16; VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++); - switch(cmd) { + switch (cmd) { case HC_ParaType_CmdVdata: while ((buf < buf_end) && - (*fire_count < dev_priv->num_fire_offsets) && - (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB ) { - while(buf <= next_fire) { - VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); + (*fire_count < dev_priv->num_fire_offsets) && + (*buf & HC_ACMD_MASK) == HC_ACMD_HCmdB) { + while (buf <= next_fire) { + VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + + (burst & 63), *buf++); burst += 4; } - if ( ( buf < buf_end ) && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) + if ((buf < buf_end) + && ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD)) buf++; - if (++(*fire_count) < dev_priv->num_fire_offsets) + if (++(*fire_count) < dev_priv->num_fire_offsets) next_fire = dev_priv->fire_offsets[*fire_count]; } break; default: - while(buf < buf_end) { - - if ( *buf == HC_HEADER2 || - (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 || - (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 || - (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6 ) break; - - VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + (burst & 63), *buf++); - burst +=4; + while (buf < buf_end) { + + if (*buf == HC_HEADER2 || + (*buf & HALCYON_HEADER1MASK) == HALCYON_HEADER1 || + (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5 || + (*buf & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) + break; + + VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + + (burst & 63), *buf++); + burst += 4; } } *buffer = buf; return state_command; } - - -static __inline__ int -verify_mmio_address( uint32_t address) +static __inline__ int verify_mmio_address(uint32_t address) { - if ((address > 0x3FF) && (address < 0xC00 )) { + if ((address > 0x3FF) && (address < 0xC00)) { DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access 3D- or command burst area.\n"); return 1; } else if ((address > 0xCFF) && (address < 0x1300)) { DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access PCI DMA area.\n"); - return 1; - } else if (address > 0x13FF ) { + return 1; + } else if (address > 0x13FF) { DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access VGA registers.\n"); return 1; @@ -745,7 +771,8 @@ verify_mmio_address( uint32_t address) } static __inline__ int -verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dwords) +verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end, + uint32_t dwords) { const uint32_t *buf = *buffer; @@ -762,10 +789,9 @@ verify_video_tail( uint32_t const **buffer, const uint32_t *buf_end, uint32_t dw *buffer = buf; return 0; } - static __inline__ verifier_state_t -via_check_header1( uint32_t const **buffer, const uint32_t *buf_end ) +via_check_header1(uint32_t const **buffer, const uint32_t * buf_end) { uint32_t cmd; const uint32_t *buf = *buffer; @@ -774,21 +800,21 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end ) while (buf < buf_end) { cmd = *buf; if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) && - (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) { - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) + (cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) { + if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; DRM_ERROR("Invalid HALCYON_HEADER1 command. " "Attempt to access 3D- or command burst area.\n"); ret = state_error; break; } else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) { - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) + if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; DRM_ERROR("Invalid HALCYON_HEADER1 command. " "Attempt to access VGA registers.\n"); ret = state_error; - break; - } else { + break; + } else { buf += 2; } } @@ -797,15 +823,17 @@ via_check_header1( uint32_t const **buffer, const uint32_t *buf_end ) } static __inline__ verifier_state_t -via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) +via_parse_header1(drm_via_private_t * dev_priv, uint32_t const **buffer, + const uint32_t * buf_end) { register uint32_t cmd; const uint32_t *buf = *buffer; while (buf < buf_end) { cmd = *buf; - if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; - VIA_WRITE( (cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); + if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) + break; + VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); buf++; } *buffer = buf; @@ -813,7 +841,7 @@ via_parse_header1( drm_via_private_t *dev_priv, uint32_t const **buffer, const u } static __inline__ verifier_state_t -via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end ) +via_check_vheader5(uint32_t const **buffer, const uint32_t * buf_end) { uint32_t data; const uint32_t *buf = *buffer; @@ -836,41 +864,41 @@ via_check_vheader5( uint32_t const **buffer, const uint32_t *buf_end ) DRM_ERROR("Illegal header5 header data\n"); return state_error; } - if (eat_words(&buf, buf_end, data)) + if (eat_words(&buf, buf_end, data)) return state_error; - if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) + if ((data & 3) && verify_video_tail(&buf, buf_end, 4 - (data & 3))) return state_error; *buffer = buf; return state_command; - -} + +} static __inline__ verifier_state_t -via_parse_vheader5( drm_via_private_t *dev_priv, uint32_t const **buffer, const uint32_t *buf_end ) +via_parse_vheader5(drm_via_private_t * dev_priv, uint32_t const **buffer, + const uint32_t * buf_end) { - uint32_t addr, count, i; + uint32_t addr, count, i; const uint32_t *buf = *buffer; - + addr = *buf++ & ~VIA_VIDEOMASK; i = count = *buf; buf += 3; - while(i--) { + while (i--) { VIA_WRITE(addr, *buf++); } - if (count & 3) buf += 4 - (count & 3); + if (count & 3) + buf += 4 - (count & 3); *buffer = buf; - return state_command; -} - + return state_command; +} static __inline__ verifier_state_t -via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end ) +via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end) { uint32_t data; const uint32_t *buf = *buffer; uint32_t i; - if (buf_end - buf < 4) { DRM_ERROR("Illegal termination of video header6 command\n"); return state_error; @@ -889,7 +917,7 @@ via_check_vheader6( uint32_t const **buffer, const uint32_t *buf_end ) DRM_ERROR("Illegal termination of video header6 command\n"); return state_error; } - for (i=0; idev_private; drm_via_state_t *hc_state = &dev_priv->hc_state; drm_via_state_t saved_state = *hc_state; uint32_t cmd; - const uint32_t *buf_end = buf + ( size >> 2 ); + const uint32_t *buf_end = buf + (size >> 2); verifier_state_t state = state_command; int pro_group_a = dev_priv->pro_group_a; - + hc_state->dev = dev; hc_state->unfinished = no_sequence; hc_state->map_cache = NULL; @@ -946,38 +974,41 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t switch (state) { case state_header2: - state = via_check_header2( &buf, buf_end, hc_state ); + state = via_check_header2(&buf, buf_end, hc_state); break; case state_header1: - state = via_check_header1( &buf, buf_end ); + state = via_check_header1(&buf, buf_end); break; case state_vheader5: - state = via_check_vheader5( &buf, buf_end ); + state = via_check_vheader5(&buf, buf_end); break; case state_vheader6: - state = via_check_vheader6( &buf, buf_end ); + state = via_check_vheader6(&buf, buf_end); break; case state_command: - if (HALCYON_HEADER2 == (cmd = *buf)) + if (HALCYON_HEADER2 == (cmd = *buf)) state = state_header2; - else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) + else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) state = state_header1; - else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) + else if (pro_group_a + && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) state = state_vheader5; - else if (pro_group_a && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) + else if (pro_group_a + && (cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) state = state_vheader6; else { - DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", - cmd); + DRM_ERROR + ("Invalid / Unimplemented DMA HEADER command. 0x%x\n", + cmd); state = state_error; } break; case state_error: default: *hc_state = saved_state; - return DRM_ERR(EINVAL); + return DRM_ERR(EINVAL); } - } + } if (state == state_error) { *hc_state = saved_state; return DRM_ERR(EINVAL); @@ -985,77 +1016,81 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t return 0; } -int -via_parse_command_stream(drm_device_t *dev, const uint32_t * buf, unsigned int size) +int +via_parse_command_stream(drm_device_t * dev, const uint32_t * buf, + unsigned int size) { drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; uint32_t cmd; - const uint32_t *buf_end = buf + ( size >> 2 ); + const uint32_t *buf_end = buf + (size >> 2); verifier_state_t state = state_command; int fire_count = 0; - + while (buf < buf_end) { switch (state) { case state_header2: - state = via_parse_header2( dev_priv, &buf, buf_end, &fire_count ); + state = + via_parse_header2(dev_priv, &buf, buf_end, + &fire_count); break; case state_header1: - state = via_parse_header1( dev_priv, &buf, buf_end ); + state = via_parse_header1(dev_priv, &buf, buf_end); break; case state_vheader5: - state = via_parse_vheader5( dev_priv, &buf, buf_end ); + state = via_parse_vheader5(dev_priv, &buf, buf_end); break; case state_vheader6: - state = via_parse_vheader6( dev_priv, &buf, buf_end ); + state = via_parse_vheader6(dev_priv, &buf, buf_end); break; case state_command: - if (HALCYON_HEADER2 == (cmd = *buf)) + if (HALCYON_HEADER2 == (cmd = *buf)) state = state_header2; - else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) + else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) state = state_header1; else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER5) state = state_vheader5; else if ((cmd & VIA_VIDEOMASK) == VIA_VIDEO_HEADER6) state = state_vheader6; else { - DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n", - cmd); + DRM_ERROR + ("Invalid / Unimplemented DMA HEADER command. 0x%x\n", + cmd); state = state_error; } break; case state_error: default: - return DRM_ERR(EINVAL); + return DRM_ERR(EINVAL); } - } + } if (state == state_error) { return DRM_ERR(EINVAL); } return 0; } - - -static void +static void setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) { int i; - for(i=0; i<256; ++i) { + for (i = 0; i < 256; ++i) { table[i] = forbidden_command; } - for(i=0; isarea_priv, i); - if ( (_DRM_LOCKING_CONTEXT( *lock ) == context)) { - if (_DRM_LOCK_IS_HELD( *lock ) && (*lock & _DRM_LOCK_CONT)) { - DRM_WAKEUP( &(dev_priv->decoder_queue[i])); + for (i = 0; i < VIA_NR_XVMC_LOCKS; ++i) { + lock = (int *)XVMCLOCKPTR(dev_priv->sarea_priv, i); + if ((_DRM_LOCKING_CONTEXT(*lock) == context)) { + if (_DRM_LOCK_IS_HELD(*lock) + && (*lock & _DRM_LOCK_CONT)) { + DRM_WAKEUP(&(dev_priv->decoder_queue[i])); } *lock = 0; } - } -} + } +} -int -via_decoder_futex(DRM_IOCTL_ARGS) +int via_decoder_futex(DRM_IOCTL_ARGS) { DRM_DEVICE; drm_via_futex_t fx; @@ -95,4 +92,3 @@ via_decoder_futex(DRM_IOCTL_ARGS) } return 0; } - -- cgit v1.2.3-70-g09d2 From 13e4a9c85152a49ec10e682308581ab13b437470 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 25 Sep 2005 14:30:09 +1000 Subject: drm: cast handle to a pointer to avoid warning Andrew reported a warning on this line, just case to void *. Signed-off-by: Dave Airlie --- drivers/char/drm/drm_bufs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c index bb989ccea5a..e3d372ad007 100644 --- a/drivers/char/drm/drm_bufs.c +++ b/drivers/char/drm/drm_bufs.c @@ -309,7 +309,7 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp, if (copy_to_user(argp, maplist->map, sizeof(drm_map_t))) return -EFAULT; - if (put_user(maplist->user_token, &argp->handle)) + if (put_user((void *)maplist->user_token, &argp->handle)) return -EFAULT; return 0; } -- cgit v1.2.3-70-g09d2 From b6ce156c415544f900e031890c78eba8bc92f9b3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sun, 25 Sep 2005 15:07:24 +1000 Subject: drm: fix some lindent damage Signed-off-by: Dave Airlie --- drivers/char/drm/i810_dma.c | 42 ++++++++-------------- drivers/char/drm/i830_dma.c | 39 +++++++-------------- drivers/char/drm/i915_dma.c | 33 ++++++----------- drivers/char/drm/mga_state.c | 40 +++++++-------------- drivers/char/drm/radeon_state.c | 78 ++++++++++++++--------------------------- drivers/char/drm/savage_bci.c | 12 +++---- drivers/char/drm/sis_mm.c | 15 +++----- 7 files changed, 86 insertions(+), 173 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/i810_dma.c b/drivers/char/drm/i810_dma.c index 810625093c0..dba502373da 100644 --- a/drivers/char/drm/i810_dma.c +++ b/drivers/char/drm/i810_dma.c @@ -1346,34 +1346,20 @@ int i810_driver_dma_quiescent(drm_device_t * dev) } drm_ioctl_desc_t i810_ioctls[] = { - [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0} - , - [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1} - , - [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0} - , + [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1}, + [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0}, [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, 1, 0} }; diff --git a/drivers/char/drm/i830_dma.c b/drivers/char/drm/i830_dma.c index e1107ecb16e..dc94f191442 100644 --- a/drivers/char/drm/i830_dma.c +++ b/drivers/char/drm/i830_dma.c @@ -1544,32 +1544,19 @@ int i830_driver_dma_quiescent(drm_device_t * dev) } drm_ioctl_desc_t i830_ioctls[] = { - [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0} - , - [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0} - , + [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, 1, 0}, [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, 1, 0} }; diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c index f0bb0bdbb6e..f3aa0c37012 100644 --- a/drivers/char/drm/i915_dma.c +++ b/drivers/char/drm/i915_dma.c @@ -717,28 +717,17 @@ void i915_driver_prerelease(drm_device_t * dev, DRMFILE filp) } drm_ioctl_desc_t i915_ioctls[] = { - [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1} - , - [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0} - , - [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1} - , + [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, 1, 1}, + [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, 1, 1}, [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, 1, 0} }; diff --git a/drivers/char/drm/mga_state.c b/drivers/char/drm/mga_state.c index 15114f8aa46..ee77685069d 100644 --- a/drivers/char/drm/mga_state.c +++ b/drivers/char/drm/mga_state.c @@ -1127,33 +1127,19 @@ static int mga_wait_fence(DRM_IOCTL_ARGS) } drm_ioctl_desc_t mga_ioctls[] = { - [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0} - , - [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1} - , - + [DRM_IOCTL_NR(DRM_MGA_INIT)] = {mga_dma_init, 1, 1}, + [DRM_IOCTL_NR(DRM_MGA_FLUSH)] = {mga_dma_flush, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_RESET)] = {mga_dma_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_SWAP)] = {mga_dma_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_CLEAR)] = {mga_dma_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_VERTEX)] = {mga_dma_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_INDICES)] = {mga_dma_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_ILOAD)] = {mga_dma_iload, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_BLIT)] = {mga_dma_blit, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_GETPARAM)] = {mga_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_SET_FENCE)] = {mga_set_fence, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_WAIT_FENCE)] = {mga_wait_fence, 1, 0}, + [DRM_IOCTL_NR(DRM_MGA_DMA_BOOTSTRAP)] = {mga_dma_bootstrap, 1, 1}, }; int mga_max_ioctl = DRM_ARRAY_SIZE(mga_ioctls); diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 42e8ce4dbe9..2eae60bd340 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -3117,58 +3117,32 @@ void radeon_driver_free_filp_priv(drm_device_t * dev, drm_file_t * filp_priv) } drm_ioctl_desc_t radeon_ioctls[] = { - [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1} - , - [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0} - , - [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0} - , + [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0}, + [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0}, [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0} }; diff --git a/drivers/char/drm/savage_bci.c b/drivers/char/drm/savage_bci.c index 0ad9201af8b..6d10515795c 100644 --- a/drivers/char/drm/savage_bci.c +++ b/drivers/char/drm/savage_bci.c @@ -1090,14 +1090,10 @@ void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp) } drm_ioctl_desc_t savage_ioctls[] = { - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0} - , - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0} - , - [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0} - , + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, 1, 1}, + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, 1, 0}, + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, 1, 0}, + [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, 1, 0}, }; int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); diff --git a/drivers/char/drm/sis_mm.c b/drivers/char/drm/sis_mm.c index 50e32384ad9..a8529728fa6 100644 --- a/drivers/char/drm/sis_mm.c +++ b/drivers/char/drm/sis_mm.c @@ -403,16 +403,11 @@ int sis_final_context(struct drm_device *dev, int context) } drm_ioctl_desc_t sis_ioctls[] = { - [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, 1, 0} - , - [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_fb_free, 1, 0} - , - [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, 1, 1} - , - [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, 1, 0} - , - [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_ioctl_agp_free, 1, 0} - , + [DRM_IOCTL_NR(DRM_SIS_FB_ALLOC)] = {sis_fb_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_FB_FREE)] = {sis_fb_free, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_AGP_INIT)] = {sis_ioctl_agp_init, 1, 1}, + [DRM_IOCTL_NR(DRM_SIS_AGP_ALLOC)] = {sis_ioctl_agp_alloc, 1, 0}, + [DRM_IOCTL_NR(DRM_SIS_AGP_FREE)] = {sis_ioctl_agp_free, 1, 0}, [DRM_IOCTL_NR(DRM_SIS_FB_INIT)] = {sis_fb_init, 1, 1} }; -- cgit v1.2.3-70-g09d2 From 14cf11af6cf608eb8c23e989ddb17a715ddce109 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Mon, 26 Sep 2005 16:04:21 +1000 Subject: powerpc: Merge enough to start building in arch/powerpc. This creates the directory structure under arch/powerpc and a bunch of Kconfig files. It does a first-cut merge of arch/powerpc/mm, arch/powerpc/lib and arch/powerpc/platforms/powermac. This is enough to build a 32-bit powermac kernel with ARCH=powerpc. For now we are getting some unmerged files from arch/ppc/kernel and arch/ppc/syslib, or arch/ppc64/kernel. This makes some minor changes to files in those directories and files outside arch/powerpc. The boot directory is still not merged. That's going to be interesting. Signed-off-by: Paul Mackerras --- arch/powerpc/Kconfig | 861 ++++++ arch/powerpc/Kconfig.debug | 73 + arch/powerpc/Makefile | 222 ++ arch/powerpc/kernel/Makefile | 18 + arch/powerpc/kernel/asm-offsets.c | 262 ++ arch/powerpc/kernel/fpu.S | 133 + arch/powerpc/kernel/head.S | 1545 +++++++++++ arch/powerpc/kernel/head_44x.S | 778 ++++++ arch/powerpc/kernel/head_4xx.S | 1016 +++++++ arch/powerpc/kernel/head_64.S | 2011 ++++++++++++++ arch/powerpc/kernel/head_8xx.S | 860 ++++++ arch/powerpc/kernel/head_fsl_booke.S | 1058 ++++++++ arch/powerpc/kernel/idle_6xx.S | 233 ++ arch/powerpc/kernel/process.c | 724 +++++ arch/powerpc/kernel/semaphore.c | 135 + arch/powerpc/kernel/traps.c | 1047 ++++++++ arch/powerpc/kernel/vector.S | 197 ++ arch/powerpc/kernel/vmlinux.lds | 174 ++ arch/powerpc/kernel/vmlinux.lds.S | 172 ++ arch/powerpc/lib/Makefile | 9 + arch/powerpc/lib/checksum.S | 225 ++ arch/powerpc/lib/checksum64.S | 229 ++ arch/powerpc/lib/copy32.S | 543 ++++ arch/powerpc/lib/copypage.S | 121 + arch/powerpc/lib/copyuser.S | 576 ++++ arch/powerpc/lib/div64.S | 58 + arch/powerpc/lib/e2a.c | 108 + arch/powerpc/lib/memcpy.S | 172 ++ arch/powerpc/lib/rheap.c | 693 +++++ arch/powerpc/lib/sstep.c | 141 + arch/powerpc/lib/strcase.c | 23 + arch/powerpc/lib/string.S | 203 ++ arch/powerpc/lib/usercopy.c | 41 + arch/powerpc/mm/44x_mmu.c | 120 + arch/powerpc/mm/4xx_mmu.c | 141 + arch/powerpc/mm/Makefile | 12 + arch/powerpc/mm/fault.c | 391 +++ arch/powerpc/mm/fsl_booke_mmu.c | 237 ++ arch/powerpc/mm/hash_32.S | 618 +++++ arch/powerpc/mm/init.c | 581 ++++ arch/powerpc/mm/init64.c | 385 +++ arch/powerpc/mm/mem.c | 299 +++ arch/powerpc/mm/mem64.c | 259 ++ arch/powerpc/mm/mem_pieces.c | 163 ++ arch/powerpc/mm/mem_pieces.h | 48 + arch/powerpc/mm/mmu_context.c | 86 + arch/powerpc/mm/mmu_context64.c | 63 + arch/powerpc/mm/mmu_decl.h | 85 + arch/powerpc/mm/pgtable.c | 470 ++++ arch/powerpc/mm/pgtable64.c | 357 +++ arch/powerpc/mm/ppc_mmu.c | 296 +++ arch/powerpc/mm/tlb.c | 183 ++ arch/powerpc/platforms/4xx/Kconfig | 280 ++ arch/powerpc/platforms/85xx/Kconfig | 86 + arch/powerpc/platforms/8xx/Kconfig | 352 +++ arch/powerpc/platforms/apus/Kconfig | 130 + arch/powerpc/platforms/embedded6xx/Kconfig | 313 +++ arch/powerpc/platforms/iseries/Kconfig | 31 + arch/powerpc/platforms/powermac/Makefile | 9 + arch/powerpc/platforms/powermac/pmac.h | 31 + arch/powerpc/platforms/powermac/pmac_backlight.c | 202 ++ arch/powerpc/platforms/powermac/pmac_cache.S | 359 +++ arch/powerpc/platforms/powermac/pmac_cpufreq.c | 728 +++++ arch/powerpc/platforms/powermac/pmac_feature.c | 3062 ++++++++++++++++++++++ arch/powerpc/platforms/powermac/pmac_low_i2c.c | 523 ++++ arch/powerpc/platforms/powermac/pmac_nvram.c | 584 +++++ arch/powerpc/platforms/powermac/pmac_pci.c | 1341 ++++++++++ arch/powerpc/platforms/powermac/pmac_pic.c | 655 +++++ arch/powerpc/platforms/powermac/pmac_pic.h | 11 + arch/powerpc/platforms/powermac/pmac_setup.c | 662 +++++ arch/powerpc/platforms/powermac/pmac_sleep.S | 396 +++ arch/powerpc/platforms/powermac/pmac_smp.c | 716 +++++ arch/powerpc/platforms/powermac/pmac_time.c | 291 ++ arch/powerpc/platforms/prep/Kconfig | 22 + arch/powerpc/platforms/pseries/Kconfig | 47 + arch/powerpc/sysdev/Makefile | 1 + arch/powerpc/sysdev/mpic.c | 904 +++++++ arch/ppc/kernel/Makefile | 21 + arch/ppc/kernel/setup.c | 8 + arch/ppc/platforms/prep_setup.c | 3 - arch/ppc/syslib/Makefile | 14 + drivers/macintosh/via-pmu.c | 2 +- fs/proc/proc_misc.c | 8 - include/asm-powerpc/kdebug.h | 42 + include/asm-powerpc/kprobes.h | 67 + include/asm-powerpc/mpic.h | 279 ++ include/asm-powerpc/reg.h | 446 ++++ include/asm-powerpc/system.h | 350 +++ include/asm-ppc/smp.h | 17 +- 89 files changed, 32423 insertions(+), 25 deletions(-) create mode 100644 arch/powerpc/Kconfig create mode 100644 arch/powerpc/Kconfig.debug create mode 100644 arch/powerpc/Makefile create mode 100644 arch/powerpc/kernel/Makefile create mode 100644 arch/powerpc/kernel/asm-offsets.c create mode 100644 arch/powerpc/kernel/fpu.S create mode 100644 arch/powerpc/kernel/head.S create mode 100644 arch/powerpc/kernel/head_44x.S create mode 100644 arch/powerpc/kernel/head_4xx.S create mode 100644 arch/powerpc/kernel/head_64.S create mode 100644 arch/powerpc/kernel/head_8xx.S create mode 100644 arch/powerpc/kernel/head_fsl_booke.S create mode 100644 arch/powerpc/kernel/idle_6xx.S create mode 100644 arch/powerpc/kernel/process.c create mode 100644 arch/powerpc/kernel/semaphore.c create mode 100644 arch/powerpc/kernel/traps.c create mode 100644 arch/powerpc/kernel/vector.S create mode 100644 arch/powerpc/kernel/vmlinux.lds create mode 100644 arch/powerpc/kernel/vmlinux.lds.S create mode 100644 arch/powerpc/lib/Makefile create mode 100644 arch/powerpc/lib/checksum.S create mode 100644 arch/powerpc/lib/checksum64.S create mode 100644 arch/powerpc/lib/copy32.S create mode 100644 arch/powerpc/lib/copypage.S create mode 100644 arch/powerpc/lib/copyuser.S create mode 100644 arch/powerpc/lib/div64.S create mode 100644 arch/powerpc/lib/e2a.c create mode 100644 arch/powerpc/lib/memcpy.S create mode 100644 arch/powerpc/lib/rheap.c create mode 100644 arch/powerpc/lib/sstep.c create mode 100644 arch/powerpc/lib/strcase.c create mode 100644 arch/powerpc/lib/string.S create mode 100644 arch/powerpc/lib/usercopy.c create mode 100644 arch/powerpc/mm/44x_mmu.c create mode 100644 arch/powerpc/mm/4xx_mmu.c create mode 100644 arch/powerpc/mm/Makefile create mode 100644 arch/powerpc/mm/fault.c create mode 100644 arch/powerpc/mm/fsl_booke_mmu.c create mode 100644 arch/powerpc/mm/hash_32.S create mode 100644 arch/powerpc/mm/init.c create mode 100644 arch/powerpc/mm/init64.c create mode 100644 arch/powerpc/mm/mem.c create mode 100644 arch/powerpc/mm/mem64.c create mode 100644 arch/powerpc/mm/mem_pieces.c create mode 100644 arch/powerpc/mm/mem_pieces.h create mode 100644 arch/powerpc/mm/mmu_context.c create mode 100644 arch/powerpc/mm/mmu_context64.c create mode 100644 arch/powerpc/mm/mmu_decl.h create mode 100644 arch/powerpc/mm/pgtable.c create mode 100644 arch/powerpc/mm/pgtable64.c create mode 100644 arch/powerpc/mm/ppc_mmu.c create mode 100644 arch/powerpc/mm/tlb.c create mode 100644 arch/powerpc/platforms/4xx/Kconfig create mode 100644 arch/powerpc/platforms/85xx/Kconfig create mode 100644 arch/powerpc/platforms/8xx/Kconfig create mode 100644 arch/powerpc/platforms/apus/Kconfig create mode 100644 arch/powerpc/platforms/embedded6xx/Kconfig create mode 100644 arch/powerpc/platforms/iseries/Kconfig create mode 100644 arch/powerpc/platforms/powermac/Makefile create mode 100644 arch/powerpc/platforms/powermac/pmac.h create mode 100644 arch/powerpc/platforms/powermac/pmac_backlight.c create mode 100644 arch/powerpc/platforms/powermac/pmac_cache.S create mode 100644 arch/powerpc/platforms/powermac/pmac_cpufreq.c create mode 100644 arch/powerpc/platforms/powermac/pmac_feature.c create mode 100644 arch/powerpc/platforms/powermac/pmac_low_i2c.c create mode 100644 arch/powerpc/platforms/powermac/pmac_nvram.c create mode 100644 arch/powerpc/platforms/powermac/pmac_pci.c create mode 100644 arch/powerpc/platforms/powermac/pmac_pic.c create mode 100644 arch/powerpc/platforms/powermac/pmac_pic.h create mode 100644 arch/powerpc/platforms/powermac/pmac_setup.c create mode 100644 arch/powerpc/platforms/powermac/pmac_sleep.S create mode 100644 arch/powerpc/platforms/powermac/pmac_smp.c create mode 100644 arch/powerpc/platforms/powermac/pmac_time.c create mode 100644 arch/powerpc/platforms/prep/Kconfig create mode 100644 arch/powerpc/platforms/pseries/Kconfig create mode 100644 arch/powerpc/sysdev/Makefile create mode 100644 arch/powerpc/sysdev/mpic.c create mode 100644 include/asm-powerpc/kdebug.h create mode 100644 include/asm-powerpc/kprobes.h create mode 100644 include/asm-powerpc/mpic.h create mode 100644 include/asm-powerpc/reg.h create mode 100644 include/asm-powerpc/system.h (limited to 'drivers') diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig new file mode 100644 index 00000000000..edfac467b9e --- /dev/null +++ b/arch/powerpc/Kconfig @@ -0,0 +1,861 @@ +# For a description of the syntax of this configuration file, +# see Documentation/kbuild/kconfig-language.txt. +# + +mainmenu "Linux/PowerPC Kernel Configuration" + +config PPC64 + bool "64-bit kernel" + default n + help + This option selects whether a 32-bit or a 64-bit kernel + will be built. + +config PPC32 + bool + default y if !PPC64 + +config 64BIT + bool + default y if PPC64 + +config PPC_MERGE + def_bool y + +config MMU + bool + default y + +config UID16 + bool + +config GENERIC_HARDIRQS + bool + default y + +config RWSEM_GENERIC_SPINLOCK + bool + +config RWSEM_XCHGADD_ALGORITHM + bool + default y + +config GENERIC_CALIBRATE_DELAY + bool + default y + +config PPC + bool + default y + +config EARLY_PRINTK + bool + default y if PPC64 + +config COMPAT + bool + default y if PPC64 + +config SYSVIPC_COMPAT + bool + depends on COMPAT && SYSVIPC + default y + +# All PPC32s use generic nvram driver through ppc_md +config GENERIC_NVRAM + bool + default y if PPC32 + +config SCHED_NO_NO_OMIT_FRAME_POINTER + bool + default y + +config ARCH_MAY_HAVE_PC_FDC + bool + default y + +menu "Processor support" +choice + prompt "Processor Type" + depends on PPC32 + default 6xx + +config 6xx + bool "6xx/7xx/74xx" + select PPC_FPU + help + There are four families of PowerPC chips supported. The more common + types (601, 603, 604, 740, 750, 7400), the Motorola embedded + versions (821, 823, 850, 855, 860, 52xx, 82xx, 83xx), the AMCC + embedded versions (403 and 405) and the high end 64 bit Power + processors (POWER 3, POWER4, and IBM PPC970 also known as G5). + + Unless you are building a kernel for one of the embedded processor + systems, 64 bit IBM RS/6000 or an Apple G5, choose 6xx. + Note that the kernel runs in 32-bit mode even on 64-bit chips. + +config PPC_52xx + bool "Freescale 52xx" + +config PPC_82xx + bool "Freescale 82xx" + +config PPC_83xx + bool "Freescale 83xx" + +config 40x + bool "AMCC 40x" + +config 44x + bool "AMCC 44x" + +config PPC64BRIDGE + select PPC_FPU + bool "POWER3, POWER4 and PPC970 (G5)" + +config 8xx + bool "Freescale 8xx" + +config E200 + bool "Freescale e200" + +config E500 + bool "Freescale e500" +endchoice + +config POWER4_ONLY + bool "Optimize for POWER4" + depends on PPC64 || PPC64BRIDGE + default n + ---help--- + Cause the compiler to optimize for POWER4/POWER5/PPC970 processors. + The resulting binary will not work on POWER3 or RS64 processors + when compiled with binutils 2.15 or later. + +config POWER3 + bool + depends on PPC64 || PPC64BRIDGE + default y if !POWER4_ONLY + +config POWER4 + depends on PPC64 || PPC64BRIDGE + def_bool y + +config PPC_FPU + bool + default y if PPC64 + +config BOOKE + bool + depends on E200 || E500 + default y + +config FSL_BOOKE + bool + depends on E200 || E500 + default y + +config PTE_64BIT + bool + depends on 44x || E500 + default y if 44x + default y if E500 && PHYS_64BIT + +config PHYS_64BIT + bool 'Large physical address support' if E500 + depends on 44x || E500 + default y if 44x + ---help--- + This option enables kernel support for larger than 32-bit physical + addresses. This features is not be available on all e500 cores. + + If in doubt, say N here. + +config ALTIVEC + bool "AltiVec Support" + depends on 6xx || POWER4 + ---help--- + This option enables kernel support for the Altivec extensions to the + PowerPC processor. The kernel currently supports saving and restoring + altivec registers, and turning on the 'altivec enable' bit so user + processes can execute altivec instructions. + + This option is only usefully if you have a processor that supports + altivec (G4, otherwise known as 74xx series), but does not have + any affect on a non-altivec cpu (it does, however add code to the + kernel). + + If in doubt, say Y here. + +config SPE + bool "SPE Support" + depends on E200 || E500 + ---help--- + This option enables kernel support for the Signal Processing + Extensions (SPE) to the PowerPC processor. The kernel currently + supports saving and restoring SPE registers, and turning on the + 'spe enable' bit so user processes can execute SPE instructions. + + This option is only useful if you have a processor that supports + SPE (e500, otherwise known as 85xx series), but does not have any + effect on a non-spe cpu (it does, however add code to the kernel). + + If in doubt, say Y here. + +config PPC_STD_MMU + bool + depends on 6xx || POWER3 || POWER4 || PPC64 + default y + +config PPC_STD_MMU_32 + def_bool y + depends on PPC_STD_MMU && PPC32 + +config SMP + depends on PPC_STD_MMU + bool "Symmetric multi-processing support" + ---help--- + This enables support for systems with more than one CPU. If you have + a system with only one CPU, say N. If you have a system with more + than one CPU, say Y. Note that the kernel does not currently + support SMP machines with 603/603e/603ev or PPC750 ("G3") processors + since they have inadequate hardware support for multiprocessor + operation. + + If you say N here, the kernel will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor machine. If + you say Y here, the kernel will run on single-processor machines. + On a single-processor machine, the kernel will run faster if you say + N here. + + If you don't know what to do here, say N. + +config NR_CPUS + int "Maximum number of CPUs (2-32)" + range 2 128 + depends on SMP + default "32" if PPC64 + default "4" + +config NOT_COHERENT_CACHE + bool + depends on 4xx || 8xx || E200 + default y +endmenu + +source "init/Kconfig" + +menu "Platform support" + depends on PPC64 || 6xx + +choice + prompt "Machine type" + default PPC_MULTIPLATFORM + +config PPC_MULTIPLATFORM + bool "Generic desktop/server/laptop" + help + Select this option if configuring for an IBM pSeries or + RS/6000 machine, an Apple machine, or a PReP, CHRP, + Maple or Cell-based machine. + +config PPC_ISERIES + bool "IBM Legacy iSeries" + depends on PPC64 + +config EMBEDDED6xx + bool "Embedded 6xx/7xx/7xxx-based board" + depends on PPC32 + +config APUS + bool "Amiga-APUS" + depends on PPC32 && BROKEN + help + Select APUS if configuring for a PowerUP Amiga. + More information is available at: + . +endchoice + +config PPC_PSERIES + depends on PPC_MULTIPLATFORM && PPC64 + bool " IBM pSeries & new (POWER5-based) iSeries" + default y + +config PPC_CHRP + bool " Common Hardware Reference Platform (CHRP) based machines" + depends on PPC_MULTIPLATFORM && PPC32 + default y + +config PPC_PMAC + bool " Apple PowerMac based machines" + depends on PPC_MULTIPLATFORM + default y + +config PPC_PMAC64 + bool + depends on PPC_PMAC && POWER4 + default y + +config PPC_PREP + bool " PowerPC Reference Platform (PReP) based machines" + depends on PPC_MULTIPLATFORM && PPC32 + default y + +config PPC_MAPLE + depends on PPC_MULTIPLATFORM && PPC64 + bool " Maple 970FX Evaluation Board" + select U3_DART + select MPIC_BROKEN_U3 + default n + help + This option enables support for the Maple 970FX Evaluation Board. + For more informations, refer to + +config PPC_BPA + bool " Broadband Processor Architecture" + depends on PPC_MULTIPLATFORM && PPC64 + +config PPC_OF + bool + depends on PPC_MULTIPLATFORM # for now + default y + +config XICS + depends on PPC_PSERIES + bool + default y + +config U3_DART + bool + depends on PPC_MULTIPLATFORM && PPC64 + default n + +config MPIC + depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE + bool + default y + +config MPIC_BROKEN_U3 + bool + depends on PPC_MAPLE + default y + +config BPA_IIC + depends on PPC_BPA + bool + default y + +config IBMVIO + depends on PPC_PSERIES || PPC_ISERIES + bool + default y + +source "drivers/cpufreq/Kconfig" + +config CPU_FREQ_PMAC + bool "Support for Apple PowerBooks" + depends on CPU_FREQ && ADB_PMU && PPC32 + select CPU_FREQ_TABLE + help + This adds support for frequency switching on Apple PowerBooks, + this currently includes some models of iBook & Titanium + PowerBook. + +config PPC601_SYNC_FIX + bool "Workarounds for PPC601 bugs" + depends on 6xx && (PPC_PREP || PPC_PMAC) + help + Some versions of the PPC601 (the first PowerPC chip) have bugs which + mean that extra synchronization instructions are required near + certain instructions, typically those that make major changes to the + CPU state. These extra instructions reduce performance slightly. + If you say N here, these extra instructions will not be included, + resulting in a kernel which will run faster but may not run at all + on some systems with the PPC601 chip. + + If in doubt, say Y here. + +config TAU + bool "Thermal Management Support" + depends on 6xx + help + G3 and G4 processors have an on-chip temperature sensor called the + 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die + temperature within 2-4 degrees Celsius. This option shows the current + on-die temperature in /proc/cpuinfo if the cpu supports it. + + Unfortunately, on some chip revisions, this sensor is very inaccurate + and in some cases, does not work at all, so don't assume the cpu + temp is actually what /proc/cpuinfo says it is. + +config TAU_INT + bool "Interrupt driven TAU driver (DANGEROUS)" + depends on TAU + ---help--- + The TAU supports an interrupt driven mode which causes an interrupt + whenever the temperature goes out of range. This is the fastest way + to get notified the temp has exceeded a range. With this option off, + a timer is used to re-check the temperature periodically. + + However, on some cpus it appears that the TAU interrupt hardware + is buggy and can cause a situation which would lead unexplained hard + lockups. + + Unless you are extending the TAU driver, or enjoy kernel/hardware + debugging, leave this option off. + +config TAU_AVERAGE + bool "Average high and low temp" + depends on TAU + ---help--- + The TAU hardware can compare the temperature to an upper and lower + bound. The default behavior is to show both the upper and lower + bound in /proc/cpuinfo. If the range is large, the temperature is + either changing a lot, or the TAU hardware is broken (likely on some + G4's). If the range is small (around 4 degrees), the temperature is + relatively stable. If you say Y here, a single temperature value, + halfway between the upper and lower bounds, will be reported in + /proc/cpuinfo. + + If in doubt, say N here. +endmenu + +source arch/powerpc/platforms/embedded6xx/Kconfig +source arch/powerpc/platforms/4xx/Kconfig +source arch/powerpc/platforms/85xx/Kconfig +source arch/powerpc/platforms/8xx/Kconfig + +menu "Kernel options" + +config HIGHMEM + bool "High memory support" + depends on PPC32 + +source kernel/Kconfig.hz +source kernel/Kconfig.preempt +source "fs/Kconfig.binfmt" + +# We optimistically allocate largepages from the VM, so make the limit +# large enough (16MB). This badly named config option is actually +# max order + 1 +config FORCE_MAX_ZONEORDER + int + depends on PPC64 + default "13" + +config MATH_EMULATION + bool "Math emulation" + depends on 4xx || 8xx || E200 || E500 + ---help--- + Some PowerPC chips designed for embedded applications do not have + a floating-point unit and therefore do not implement the + floating-point instructions in the PowerPC instruction set. If you + say Y here, the kernel will include code to emulate a floating-point + unit, which will allow programs that use floating-point + instructions to run. + +config IOMMU_VMERGE + bool "Enable IOMMU virtual merging (EXPERIMENTAL)" + depends on EXPERIMENTAL && PPC64 + default n + help + Cause IO segments sent to a device for DMA to be merged virtually + by the IOMMU when they happen to have been allocated contiguously. + This doesn't add pressure to the IOMMU allocator. However, some + drivers don't support getting large merged segments coming back + from *_map_sg(). Say Y if you know the drivers you are using are + properly handling this case. + +config HOTPLUG_CPU + bool "Support for enabling/disabling CPUs" + depends on SMP && HOTPLUG && EXPERIMENTAL && (PPC_PSERIES || PPC_PMAC) + ---help--- + Say Y here to be able to disable and re-enable individual + CPUs at runtime on SMP machines. + + Say N if you are unsure. + +config KEXEC + bool "kexec system call (EXPERIMENTAL)" + depends on PPC_MULTIPLATFORM && EXPERIMENTAL + help + kexec is a system call that implements the ability to shutdown your + current kernel, and to start another kernel. It is like a reboot + but it is indepedent of the system firmware. And like a reboot + you can start any kernel with it, not just Linux. + + The name comes from the similiarity to the exec system call. + + It is an ongoing process to be certain the hardware in a machine + is properly shutdown, so do not be surprised if this code does not + initially work for you. It may help to enable device hotplugging + support. As of this writing the exact hardware interface is + strongly in flux, so no good recommendation can be made. + +config EMBEDDEDBOOT + bool + depends on 8xx || 8260 + default y + +config PC_KEYBOARD + bool "PC PS/2 style Keyboard" + depends on 4xx || CPM2 + +config PPCBUG_NVRAM + bool "Enable reading PPCBUG NVRAM during boot" if PPLUS || LOPEC + default y if PPC_PREP + +config IRQ_ALL_CPUS + bool "Distribute interrupts on all CPUs by default" + depends on SMP && !MV64360 + help + This option gives the kernel permission to distribute IRQs across + multiple CPUs. Saying N here will route all IRQs to the first + CPU. Generally saying Y is safe, although some problems have been + reported with SMP Power Macintoshes with this option enabled. + +source "arch/powerpc/platforms/pseries/Kconfig" + +config ARCH_SELECT_MEMORY_MODEL + def_bool y + depends on PPC64 + +config ARCH_FLATMEM_ENABLE + def_bool y + depends on PPC64 && !NUMA + +config ARCH_DISCONTIGMEM_ENABLE + def_bool y + depends on SMP && PPC_PSERIES + +config ARCH_DISCONTIGMEM_DEFAULT + def_bool y + depends on ARCH_DISCONTIGMEM_ENABLE + +config ARCH_FLATMEM_ENABLE + def_bool y + depends on PPC64 + +config ARCH_SPARSEMEM_ENABLE + def_bool y + depends on ARCH_DISCONTIGMEM_ENABLE + +source "mm/Kconfig" + +config HAVE_ARCH_EARLY_PFN_TO_NID + def_bool y + depends on NEED_MULTIPLE_NODES + +# Some NUMA nodes have memory ranges that span +# other nodes. Even though a pfn is valid and +# between a node's start and end pfns, it may not +# reside on that node. +# +# This is a relatively temporary hack that should +# be able to go away when sparsemem is fully in +# place + +config NODES_SPAN_OTHER_NODES + def_bool y + depends on NEED_MULTIPLE_NODES + +config NUMA + bool "NUMA support" + default y if DISCONTIGMEM || SPARSEMEM + +config SCHED_SMT + bool "SMT (Hyperthreading) scheduler support" + depends on PPC64 && SMP + default off + help + SMT scheduler support improves the CPU scheduler's decision making + when dealing with POWER5 cpus at a cost of slightly increased + overhead in some places. If unsure say N here. + +config PROC_DEVICETREE + bool "Support for Open Firmware device tree in /proc" + depends on PPC_OF && PROC_FS + help + This option adds a device-tree directory under /proc which contains + an image of the device tree that the kernel copies from Open + Firmware. If unsure, say Y here. + +source "arch/powerpc/platforms/prep/Kconfig" + +config CMDLINE_BOOL + bool "Default bootloader kernel arguments" + depends on !PPC_ISERIES + +config CMDLINE + string "Initial kernel command string" + depends on CMDLINE_BOOL + default "console=ttyS0,9600 console=tty0 root=/dev/sda2" + help + On some platforms, there is currently no way for the boot loader to + pass arguments to the kernel. For these platforms, you can supply + some command-line options at build time by entering them here. In + most cases you will need to specify the root device here. + +if !44x || BROKEN +source kernel/power/Kconfig +endif + +config SECCOMP + bool "Enable seccomp to safely compute untrusted bytecode" + depends on PROC_FS + default y + help + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via /proc//seccomp, it cannot be disabled + and the task is only allowed to execute a few safe syscalls + defined by each seccomp mode. + + If unsure, say Y. Only embedded should say N here. + +endmenu + +config ISA_DMA_API + bool + default y + +menu "Bus options" + +config ISA + bool "Support for ISA-bus hardware" + depends on PPC_PREP || PPC_CHRP + help + Find out whether you have ISA slots on your motherboard. ISA is the + name of a bus system, i.e. the way the CPU talks to the other stuff + inside your box. If you have an Apple machine, say N here; if you + have an IBM RS/6000 or pSeries machine or a PReP machine, say Y. If + you have an embedded board, consult your board documentation. + +config GENERIC_ISA_DMA + bool + depends on PPC64 || POWER4 || 6xx && !CPM2 + default y + +config EISA + bool + +config SBUS + bool + +# Yes MCA RS/6000s exist but Linux-PPC does not currently support any +config MCA + bool + +config PCI + bool "PCI support" if 40x || CPM2 || 83xx || 85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) + default y if !40x && !CPM2 && !8xx && !APUS && !83xx && !85xx + default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS + default PCI_QSPAN if !4xx && !CPM2 && 8xx + help + Find out whether your system includes a PCI bus. PCI is the name of + a bus system, i.e. the way the CPU talks to the other stuff inside + your box. If you say Y here, the kernel will include drivers and + infrastructure code to support PCI bus devices. + +config PCI_DOMAINS + bool + default PCI + +config MPC83xx_PCI2 + bool " Supprt for 2nd PCI host controller" + depends on PCI && MPC834x + default y if MPC834x_SYS + +config PCI_QSPAN + bool "QSpan PCI" + depends on !4xx && !CPM2 && 8xx + help + Say Y here if you have a system based on a Motorola 8xx-series + embedded processor with a QSPAN PCI interface, otherwise say N. + +config PCI_8260 + bool + depends on PCI && 8260 + default y + +config 8260_PCI9 + bool " Enable workaround for MPC826x erratum PCI 9" + depends on PCI_8260 && !ADS8272 + default y + +choice + prompt " IDMA channel for PCI 9 workaround" + depends on 8260_PCI9 + +config 8260_PCI9_IDMA1 + bool "IDMA1" + +config 8260_PCI9_IDMA2 + bool "IDMA2" + +config 8260_PCI9_IDMA3 + bool "IDMA3" + +config 8260_PCI9_IDMA4 + bool "IDMA4" + +endchoice + +source "drivers/pci/Kconfig" + +source "drivers/pcmcia/Kconfig" + +source "drivers/pci/hotplug/Kconfig" + +endmenu + +menu "Advanced setup" + depends on PPC32 + +config ADVANCED_OPTIONS + bool "Prompt for advanced kernel configuration options" + help + This option will enable prompting for a variety of advanced kernel + configuration options. These options can cause the kernel to not + work if they are set incorrectly, but can be used to optimize certain + aspects of kernel memory management. + + Unless you know what you are doing, say N here. + +comment "Default settings for advanced configuration options are used" + depends on !ADVANCED_OPTIONS + +config HIGHMEM_START_BOOL + bool "Set high memory pool address" + depends on ADVANCED_OPTIONS && HIGHMEM + help + This option allows you to set the base address of the kernel virtual + area used to map high memory pages. This can be useful in + optimizing the layout of kernel virtual memory. + + Say N here unless you know what you are doing. + +config HIGHMEM_START + hex "Virtual start address of high memory pool" if HIGHMEM_START_BOOL + default "0xfe000000" + +config LOWMEM_SIZE_BOOL + bool "Set maximum low memory" + depends on ADVANCED_OPTIONS + help + This option allows you to set the maximum amount of memory which + will be used as "low memory", that is, memory which the kernel can + access directly, without having to set up a kernel virtual mapping. + This can be useful in optimizing the layout of kernel virtual + memory. + + Say N here unless you know what you are doing. + +config LOWMEM_SIZE + hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL + default "0x30000000" + +config KERNEL_START_BOOL + bool "Set custom kernel base address" + depends on ADVANCED_OPTIONS + help + This option allows you to set the kernel virtual address at which + the kernel will map low memory (the kernel image will be linked at + this address). This can be useful in optimizing the virtual memory + layout of the system. + + Say N here unless you know what you are doing. + +config KERNEL_START + hex "Virtual address of kernel base" if KERNEL_START_BOOL + default "0xc0000000" + +config TASK_SIZE_BOOL + bool "Set custom user task size" + depends on ADVANCED_OPTIONS + help + This option allows you to set the amount of virtual address space + allocated to user tasks. This can be useful in optimizing the + virtual memory layout of the system. + + Say N here unless you know what you are doing. + +config TASK_SIZE + hex "Size of user task space" if TASK_SIZE_BOOL + default "0x80000000" + +config CONSISTENT_START_BOOL + bool "Set custom consistent memory pool address" + depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE + help + This option allows you to set the base virtual address + of the the consistent memory pool. This pool of virtual + memory is used to make consistent memory allocations. + +config CONSISTENT_START + hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL + default "0xff100000" if NOT_COHERENT_CACHE + +config CONSISTENT_SIZE_BOOL + bool "Set custom consistent memory pool size" + depends on ADVANCED_OPTIONS && NOT_COHERENT_CACHE + help + This option allows you to set the size of the the + consistent memory pool. This pool of virtual memory + is used to make consistent memory allocations. + +config CONSISTENT_SIZE + hex "Size of consistent memory pool" if CONSISTENT_SIZE_BOOL + default "0x00200000" if NOT_COHERENT_CACHE + +config BOOT_LOAD_BOOL + bool "Set the boot link/load address" + depends on ADVANCED_OPTIONS && !PPC_MULTIPLATFORM + help + This option allows you to set the initial load address of the zImage + or zImage.initrd file. This can be useful if you are on a board + which has a small amount of memory. + + Say N here unless you know what you are doing. + +config BOOT_LOAD + hex "Link/load address for booting" if BOOT_LOAD_BOOL + default "0x00400000" if 40x || 8xx || 8260 + default "0x01000000" if 44x + default "0x00800000" + +config PIN_TLB + bool "Pinned Kernel TLBs (860 ONLY)" + depends on ADVANCED_OPTIONS && 8xx +endmenu + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +# XXX source "arch/ppc/8xx_io/Kconfig" + +# XXX source "arch/ppc/8260_io/Kconfig" + +source "arch/powerpc/platforms/iseries/Kconfig" + +source "lib/Kconfig" + +source "arch/powerpc/oprofile/Kconfig" + +source "arch/powerpc/Kconfig.debug" + +source "security/Kconfig" + +config KEYS_COMPAT + bool + depends on COMPAT && KEYS + default y + +source "crypto/Kconfig" diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug new file mode 100644 index 00000000000..61653cb60c4 --- /dev/null +++ b/arch/powerpc/Kconfig.debug @@ -0,0 +1,73 @@ +menu "Kernel hacking" + +source "lib/Kconfig.debug" + +config KGDB + bool "Include kgdb kernel debugger" + depends on DEBUG_KERNEL && (BROKEN || PPC_GEN550 || 4xx) + select DEBUG_INFO + help + Include in-kernel hooks for kgdb, the Linux kernel source level + debugger. See for more information. + Unless you are intending to debug the kernel, say N here. + +choice + prompt "Serial Port" + depends on KGDB + default KGDB_TTYS1 + +config KGDB_TTYS0 + bool "ttyS0" + +config KGDB_TTYS1 + bool "ttyS1" + +config KGDB_TTYS2 + bool "ttyS2" + +config KGDB_TTYS3 + bool "ttyS3" + +endchoice + +config KGDB_CONSOLE + bool "Enable serial console thru kgdb port" + depends on KGDB && 8xx || CPM2 + help + If you enable this, all serial console messages will be sent + over the gdb stub. + If unsure, say N. + +config XMON + bool "Include xmon kernel debugger" + depends on DEBUG_KERNEL + help + Include in-kernel hooks for the xmon kernel monitor/debugger. + Unless you are intending to debug the kernel, say N here. + +config BDI_SWITCH + bool "Include BDI-2000 user context switcher" + depends on DEBUG_KERNEL + help + Include in-kernel support for the Abatron BDI2000 debugger. + Unless you are intending to debug the kernel with one of these + machines, say N here. + +config BOOTX_TEXT + bool "Support for early boot text console (BootX or OpenFirmware only)" + depends PPC_OF + help + Say Y here to see progress messages from the boot firmware in text + mode. Requires either BootX or Open Firmware. + +config SERIAL_TEXT_DEBUG + bool "Support for early boot texts over serial port" + depends on 4xx || LOPEC || MV64X60 || PPLUS || PRPMC800 || \ + PPC_GEN550 || PPC_MPC52xx + +config PPC_OCP + bool + depends on IBM_OCP || XILINX_OCP + default y + +endmenu diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile new file mode 100644 index 00000000000..8a65e112211 --- /dev/null +++ b/arch/powerpc/Makefile @@ -0,0 +1,222 @@ +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. Remember to do have actions +# for "archclean" and "archdep" for cleaning up and making dependencies for +# this architecture. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1994 by Linus Torvalds +# Changes for PPC by Gary Thomas +# Rewritten by Cort Dougan and Paul Mackerras +# + +# This must match PAGE_OFFSET in include/asm-powerpc/page.h. +KERNELLOAD := $(CONFIG_KERNEL_START) + +HAS_BIARCH := $(call cc-option-yn, -m32) + +ifeq ($(CONFIG_PPC64),y) +SZ := 64 + +# Set default 32 bits cross compilers for vdso and boot wrapper +CROSS32_COMPILE ?= + +CROSS32CC := $(CROSS32_COMPILE)gcc +CROSS32AS := $(CROSS32_COMPILE)as +CROSS32LD := $(CROSS32_COMPILE)ld +CROSS32OBJCOPY := $(CROSS32_COMPILE)objcopy + +ifeq ($(HAS_BIARCH),y) +ifeq ($(CROSS32_COMPILE),) +CROSS32CC := $(CC) -m32 +CROSS32AS := $(AS) -a32 +CROSS32LD := $(LD) -m elf32ppc +CROSS32OBJCOPY := $(OBJCOPY) +endif +endif + +export CROSS32CC CROSS32AS CROSS32LD CROSS32OBJCOPY + +new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi) + +ifeq ($(new_nm),y) +NM := $(NM) --synthetic +endif + +else +SZ := 32 +endif + +ifeq ($(HAS_BIARCH),y) +override AS += -a$(SZ) +override LD += -m elf$(SZ)ppc +override CC += -m$(SZ) +endif + +LDFLAGS_vmlinux := -Ttext $(KERNELLOAD) -Bstatic -e $(KERNELLOAD) + +# The -Iarch/$(ARCH)/include is temporary while we are merging +CPPFLAGS += -Iarch/$(ARCH) -Iarch/$(ARCH)/include +AFLAGS += -Iarch/$(ARCH) +CFLAGS += -Iarch/$(ARCH) -msoft-float -pipe +ifeq ($(CONFIG_PPC64),y) +CFLAGS += -mminimal-toc -mtraceback=none -mcall-aixdesc +else +CFLAGS += -ffixed-r2 -mmultiple +endif +CPP = $(CC) -E $(CFLAGS) +# Temporary hack until we have migrated to asm-powerpc +LINUXINCLUDE += -Iarch/$(ARCH)/include + +CHECKFLAGS += -m$(SZ) -D__powerpc__ -D__powerpc$(SZ)__ + +ifeq ($(CONFIG_PPC64),y) +GCC_VERSION := $(call cc-version) +GCC_BROKEN_VEC := $(shell if [ $(GCC_VERSION) -lt 0400 ] ; then echo "y"; fi) + +ifeq ($(CONFIG_POWER4_ONLY),y) +ifeq ($(CONFIG_ALTIVEC),y) +ifeq ($(GCC_BROKEN_VEC),y) + CFLAGS += $(call cc-option,-mcpu=970) +else + CFLAGS += $(call cc-option,-mcpu=power4) +endif +else + CFLAGS += $(call cc-option,-mcpu=power4) +endif +else + CFLAGS += $(call cc-option,-mtune=power4) +endif +endif + +# Enable unit-at-a-time mode when possible. It shrinks the +# kernel considerably. +CFLAGS += $(call cc-option,-funit-at-a-time) + +ifndef CONFIG_FSL_BOOKE +CFLAGS += -mstring +endif + +cpu-as-$(CONFIG_PPC64BRIDGE) += -Wa,-mppc64bridge +cpu-as-$(CONFIG_4xx) += -Wa,-m405 +cpu-as-$(CONFIG_6xx) += -Wa,-maltivec +cpu-as-$(CONFIG_POWER4) += -Wa,-maltivec +cpu-as-$(CONFIG_E500) += -Wa,-me500 +cpu-as-$(CONFIG_E200) += -Wa,-me200 + +AFLAGS += $(cpu-as-y) +CFLAGS += $(cpu-as-y) + +# Default to the common case. +KBUILD_DEFCONFIG := common_defconfig + +head-y := arch/powerpc/kernel/head.o +head-$(CONFIG_PPC64) := arch/powerpc/kernel/head_64.o +head-$(CONFIG_8xx) := arch/powerpc/kernel/head_8xx.o +head-$(CONFIG_4xx) := arch/powerpc/kernel/head_4xx.o +head-$(CONFIG_44x) := arch/powerpc/kernel/head_44x.o +head-$(CONFIG_FSL_BOOKE) := arch/powerpc/kernel/head_fsl_booke.o + +ifeq ($(CONFIG_PPC32),y) +head-$(CONFIG_6xx) += arch/powerpc/kernel/idle_6xx.o +head-$(CONFIG_POWER4) += arch/powerpc/kernel/idle_power4.o +head-$(CONFIG_PPC_FPU) += arch/powerpc/kernel/fpu.o +endif + +core-y += arch/powerpc/kernel/ \ + arch/powerpc/mm/ \ + arch/powerpc/lib/ \ + arch/powerpc/sysdev/ +core-$(CONFIG_PPC32) += arch/ppc/kernel/ \ + arch/ppc/syslib/ +core-$(CONFIG_PPC64) += arch/ppc64/kernel/ +core-$(CONFIG_PPC_PMAC) += arch/powerpc/platforms/powermac/ +core-$(CONFIG_4xx) += arch/ppc/platforms/4xx/ +core-$(CONFIG_83xx) += arch/ppc/platforms/83xx/ +core-$(CONFIG_85xx) += arch/ppc/platforms/85xx/ +core-$(CONFIG_MATH_EMULATION) += arch/ppc/math-emu/ +core-$(CONFIG_XMON) += arch/powerpc/xmon/ +core-$(CONFIG_APUS) += arch/ppc/amiga/ +drivers-$(CONFIG_8xx) += arch/ppc/8xx_io/ +drivers-$(CONFIG_4xx) += arch/ppc/4xx_io/ +drivers-$(CONFIG_CPM2) += arch/ppc/8260_io/ + +drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/ + +BOOT_TARGETS = zImage zImage.initrd znetboot znetboot.initrd vmlinux.sm + +.PHONY: $(BOOT_TARGETS) + +all: uImage zImage + +CPPFLAGS_vmlinux.lds := -Upowerpc + +# All the instructions talk about "make bzImage". +bzImage: zImage + +boot := arch/$(ARCH)/boot + +$(BOOT_TARGETS): vmlinux + $(Q)$(MAKE) $(build)=$(boot) $@ + +uImage: vmlinux + $(Q)$(MAKE) $(build)=$(boot)/images $(boot)/images/$@ + +define archhelp + @echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/images/zImage.*)' + @echo ' uImage - Create a bootable image for U-Boot / PPCBoot' + @echo ' install - Install kernel using' + @echo ' (your) ~/bin/installkernel or' + @echo ' (distribution) /sbin/installkernel or' + @echo ' install to $$(INSTALL_PATH) and run lilo' + @echo ' *_defconfig - Select default config from arch/$(ARCH)/ppc/configs' +endef + +archclean: + $(Q)$(MAKE) $(clean)=arch/ppc/boot + # Temporary hack until we have migrated to asm-powerpc + $(Q)rm -rf arch/$(ARCH)/include + +archprepare: checkbin + +# Temporary hack until we have migrated to asm-powerpc +ifeq ($(CONFIG_PPC64),y) +include/asm: arch/$(ARCH)/include/asm +arch/$(ARCH)/include/asm: + $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi + $(Q)ln -fsn $(srctree)/include/asm-ppc64 arch/$(ARCH)/include/asm +else +include/asm: arch/$(ARCH)/include/asm +arch/$(ARCH)/include/asm: + $(Q)if [ ! -d arch/$(ARCH)/include ]; then mkdir -p arch/$(ARCH)/include; fi + $(Q)ln -fsn $(srctree)/include/asm-ppc arch/$(ARCH)/include/asm +endif + +# Use the file '.tmp_gas_check' for binutils tests, as gas won't output +# to stdout and these checks are run even on install targets. +TOUT := .tmp_gas_check +# Ensure this is binutils 2.12.1 (or 2.12.90.0.7) or later for altivec +# instructions. +# gcc-3.4 and binutils-2.14 are a fatal combination. +GCC_VERSION := $(call cc-version) + +checkbin: + @if test "$(GCC_VERSION)" = "0304" ; then \ + if ! /bin/echo mftb 5 | $(AS) -v -mppc -many -o $(TOUT) >/dev/null 2>&1 ; then \ + echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build '; \ + echo 'correctly with gcc-3.4 and your version of binutils.'; \ + echo '*** Please upgrade your binutils or downgrade your gcc'; \ + false; \ + fi ; \ + fi + @if ! /bin/echo dssall | $(AS) -many -o $(TOUT) >/dev/null 2>&1 ; then \ + echo -n '*** ${VERSION}.${PATCHLEVEL} kernels no longer build ' ; \ + echo 'correctly with old versions of binutils.' ; \ + echo '*** Please upgrade your binutils to 2.12.1 or newer' ; \ + false ; \ + fi + +CLEAN_FILES += $(TOUT) + diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile new file mode 100644 index 00000000000..62c4a51a23d --- /dev/null +++ b/arch/powerpc/kernel/Makefile @@ -0,0 +1,18 @@ +# +# Makefile for the linux kernel. +# + +extra-$(CONFIG_PPC_STD_MMU) := head.o +extra_$(CONFIG_PPC64) := head_64.o +extra-$(CONFIG_40x) := head_4xx.o +extra-$(CONFIG_44x) := head_44x.o +extra-$(CONFIG_FSL_BOOKE) := head_fsl_booke.o +extra-$(CONFIG_8xx) := head_8xx.o +extra-$(CONFIG_6xx) += idle_6xx.o +extra-$(CONFIG_POWER4) += idle_power4.o +extra-$(CONFIG_PPC_FPU) += fpu.o +extra-y += vmlinux.lds + +obj-y := semaphore.o traps.o process.o + +obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c new file mode 100644 index 00000000000..16cf0b7ee2b --- /dev/null +++ b/arch/powerpc/kernel/asm-offsets.c @@ -0,0 +1,262 @@ +/* + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#ifdef CONFIG_PPC64 +#include +#include +#include +#include +#include +#include +#include +#endif + +#define DEFINE(sym, val) \ + asm volatile("\n->" #sym " %0 " #val : : "i" (val)) + +#define BLANK() asm volatile("\n->" : : ) + +int main(void) +{ + /* thread struct on stack */ + DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); + DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); + DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); +#ifdef CONFIG_PPC32 + DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags)); +#endif +#ifdef CONFIG_PPC64 + DEFINE(TI_SC_NOERR, offsetof(struct thread_info, syscall_noerror)); + DEFINE(THREAD_SHIFT, THREAD_SHIFT); +#endif + DEFINE(THREAD_SIZE, THREAD_SIZE); + + /* task_struct->thread */ + DEFINE(THREAD, offsetof(struct task_struct, thread)); + DEFINE(THREAD_INFO, offsetof(struct task_struct, thread_info)); + DEFINE(MM, offsetof(struct task_struct, mm)); + DEFINE(PTRACE, offsetof(struct task_struct, ptrace)); + DEFINE(KSP, offsetof(struct thread_struct, ksp)); + DEFINE(PGDIR, offsetof(struct thread_struct, pgdir)); + DEFINE(LAST_SYSCALL, offsetof(struct thread_struct, last_syscall)); + DEFINE(PT_REGS, offsetof(struct thread_struct, regs)); + DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode)); + DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0])); + DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr)); +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) + DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); + DEFINE(PT_PTRACED, PT_PTRACED); +#endif +#ifdef CONFIG_PPC64 + DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid)); +#endif + +#ifdef CONFIG_ALTIVEC + DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0])); + DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave)); + DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr)); + DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr)); +#endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_SPE + DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0])); + DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc)); + DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr)); + DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe)); +#endif /* CONFIG_SPE */ + /* Interrupt register frame */ + DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD); +#ifndef CONFIG_PPC64 + DEFINE(INT_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); +#else + DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); + + /* 288 = # of volatile regs, int & fp, for leaf routines */ + /* which do not stack a frame. See the PPC64 ABI. */ + DEFINE(INT_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 288); +#endif + /* in fact we only use gpr0 - gpr9 and gpr20 - gpr23 */ + DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0])); + DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1])); + DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2])); + DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3])); + DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4])); + DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5])); + DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6])); + DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7])); + DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8])); + DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9])); + DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10])); + DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11])); + DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12])); + DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13])); + DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14])); + DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15])); + DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16])); + DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17])); + DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18])); + DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19])); + DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20])); + DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21])); + DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22])); + DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23])); + DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24])); + DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25])); + DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26])); + DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27])); + DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28])); + DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29])); + DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30])); + DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31])); + /* + * Note: these symbols include _ because they overlap with special + * register names + */ + DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip)); + DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr)); + DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr)); + DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link)); + DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr)); + DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq)); + DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer)); + DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); + DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); + /* The PowerPC 400-class & Book-E processors have neither the DAR nor the DSISR + * SPRs. Hence, we overload them to hold the similar DEAR and ESR SPRs + * for such processors. For critical interrupts we use them to + * hold SRR0 and SRR1. + */ + DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); + DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); + DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3)); + DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result)); + DEFINE(TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); + DEFINE(CLONE_VM, CLONE_VM); + DEFINE(CLONE_UNTRACED, CLONE_UNTRACED); + DEFINE(MM_PGD, offsetof(struct mm_struct, pgd)); + + /* About the CPU features table */ + DEFINE(CPU_SPEC_ENTRY_SIZE, sizeof(struct cpu_spec)); + DEFINE(CPU_SPEC_PVR_MASK, offsetof(struct cpu_spec, pvr_mask)); + DEFINE(CPU_SPEC_PVR_VALUE, offsetof(struct cpu_spec, pvr_value)); + DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); + DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); + +#ifdef CONFIG_PPC64 + DEFINE(MM, offsetof(struct task_struct, mm)); + DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context)); + + DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size)); + DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size)); + DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page)); + DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size)); + DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size)); + DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page)); + DEFINE(PLATFORM, offsetof(struct systemcfg, platform)); + + /* paca */ + DEFINE(PACA_SIZE, sizeof(struct paca_struct)); + DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index)); + DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start)); + DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack)); + DEFINE(PACACURRENT, offsetof(struct paca_struct, __current)); + DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr)); + DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real)); + DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr)); + DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr)); + DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1)); + DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc)); + DEFINE(PACAPROCENABLED, offsetof(struct paca_struct, proc_enabled)); + DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); + DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); + DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); +#ifdef CONFIG_HUGETLB_PAGE + DEFINE(PACALOWHTLBAREAS, offsetof(struct paca_struct, context.low_htlb_areas)); + DEFINE(PACAHIGHHTLBAREAS, offsetof(struct paca_struct, context.high_htlb_areas)); +#endif /* CONFIG_HUGETLB_PAGE */ + DEFINE(PACADEFAULTDECR, offsetof(struct paca_struct, default_decr)); + DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); + DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); + DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb)); + DEFINE(PACA_EXDSI, offsetof(struct paca_struct, exdsi)); + DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); + DEFINE(PACALPPACA, offsetof(struct paca_struct, lppaca)); + DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); + DEFINE(LPPACASRR0, offsetof(struct lppaca, saved_srr0)); + DEFINE(LPPACASRR1, offsetof(struct lppaca, saved_srr1)); + DEFINE(LPPACAANYINT, offsetof(struct lppaca, int_dword.any_int)); + DEFINE(LPPACADECRINT, offsetof(struct lppaca, int_dword.fields.decr_int)); + + /* RTAS */ + DEFINE(RTASBASE, offsetof(struct rtas_t, base)); + DEFINE(RTASENTRY, offsetof(struct rtas_t, entry)); + + DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); + DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe)); + + /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */ + DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); + DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); + + /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */ + DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)); + DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8); + + /* systemcfg offsets for use by vdso */ + DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct systemcfg, tb_orig_stamp)); + DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct systemcfg, tb_ticks_per_sec)); + DEFINE(CFG_TB_TO_XS, offsetof(struct systemcfg, tb_to_xs)); + DEFINE(CFG_STAMP_XSEC, offsetof(struct systemcfg, stamp_xsec)); + DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct systemcfg, tb_update_count)); + DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct systemcfg, tz_minuteswest)); + DEFINE(CFG_TZ_DSTTIME, offsetof(struct systemcfg, tz_dsttime)); + DEFINE(CFG_SYSCALL_MAP32, offsetof(struct systemcfg, syscall_map_32)); + DEFINE(CFG_SYSCALL_MAP64, offsetof(struct systemcfg, syscall_map_64)); + + /* timeval/timezone offsets for use by vdso */ + DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec)); + DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec)); + DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec)); + DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec)); + DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); + DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); +#endif + + DEFINE(pbe_address, offsetof(struct pbe, address)); + DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); + DEFINE(pbe_next, offsetof(struct pbe, next)); + + DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); + return 0; +} diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S new file mode 100644 index 00000000000..665d7d34304 --- /dev/null +++ b/arch/powerpc/kernel/fpu.S @@ -0,0 +1,133 @@ +/* + * FPU support code, moved here from head.S so that it can be used + * by chips which use other head-whatever.S files. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This task wants to use the FPU now. + * On UP, disable FP for the task which had the FPU previously, + * and save its floating-point registers in its thread_struct. + * Load up this task's FP registers from its thread_struct, + * enable the FPU for the current task and return to the task. + */ + .globl load_up_fpu +load_up_fpu: + mfmsr r5 + ori r5,r5,MSR_FP +#ifdef CONFIG_PPC64BRIDGE + clrldi r5,r5,1 /* turn off 64-bit mode */ +#endif /* CONFIG_PPC64BRIDGE */ + SYNC + MTMSRD(r5) /* enable use of fpu now */ + isync +/* + * For SMP, we don't do lazy FPU switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_fpu in switch_to. + */ +#ifndef CONFIG_SMP + tophys(r6,0) /* get __pa constant */ + addis r3,r6,last_task_used_math@ha + lwz r4,last_task_used_math@l(r3) + cmpwi 0,r4,0 + beq 1f + add r4,r4,r6 + addi r4,r4,THREAD /* want last_task_used_math->thread */ + SAVE_32FPRS(0, r4) + mffs fr0 + stfd fr0,THREAD_FPSCR-4(r4) + lwz r5,PT_REGS(r4) + add r5,r5,r6 + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r10,MSR_FP|MSR_FE0|MSR_FE1 + andc r4,r4,r10 /* disable FP for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /* enable use of FP after return */ + mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ + lwz r4,THREAD_FPEXC_MODE(r5) + ori r9,r9,MSR_FP /* enable FP for current */ + or r9,r9,r4 + lfd fr0,THREAD_FPSCR-4(r5) + mtfsf 0xff,fr0 + REST_32FPRS(0, r5) +#ifndef CONFIG_SMP + subi r4,r5,THREAD + sub r4,r4,r6 + stw r4,last_task_used_math@l(r3) +#endif /* CONFIG_SMP */ + /* restore registers and return */ + /* we haven't used ctr or xer or lr */ + b fast_exception_return + +/* + * FP unavailable trap from kernel - print a message, but let + * the task use FP in the kernel until it returns to user mode. + */ + .globl KernelFP +KernelFP: + lwz r3,_MSR(r1) + ori r3,r3,MSR_FP + stw r3,_MSR(r1) /* enable use of FP after return */ + lis r3,86f@h + ori r3,r3,86f@l + mr r4,r2 /* current */ + lwz r5,_NIP(r1) + bl printk + b ret_from_except +86: .string "floating point used in kernel (task=%p, pc=%x)\n" + .align 4,0 + +/* + * giveup_fpu(tsk) + * Disable FP for the task given as the argument, + * and save the floating-point registers in its thread_struct. + * Enables the FPU for use in the kernel on return. + */ + .globl giveup_fpu +giveup_fpu: + mfmsr r5 + ori r5,r5,MSR_FP + SYNC_601 + ISYNC_601 + MTMSRD(r5) /* enable use of fpu now */ + SYNC_601 + isync + cmpwi 0,r3,0 + beqlr- /* if no previous owner, done */ + addi r3,r3,THREAD /* want THREAD of task */ + lwz r5,PT_REGS(r3) + cmpwi 0,r5,0 + SAVE_32FPRS(0, r3) + mffs fr0 + stfd fr0,THREAD_FPSCR-4(r3) + beq 1f + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r3,MSR_FP|MSR_FE0|MSR_FE1 + andc r4,r4,r3 /* disable FP for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#ifndef CONFIG_SMP + li r5,0 + lis r4,last_task_used_math@ha + stw r5,last_task_used_math@l(r4) +#endif /* CONFIG_SMP */ + blr diff --git a/arch/powerpc/kernel/head.S b/arch/powerpc/kernel/head.S new file mode 100644 index 00000000000..d05509f197d --- /dev/null +++ b/arch/powerpc/kernel/head.S @@ -0,0 +1,1545 @@ +/* + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * This file contains the low-level support and setup for the + * PowerPC platform, including trap and interrupt dispatch. + * (The PPC 8xx embedded CPUs use head_8xx.S instead.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_APUS +#include +#endif + +#ifdef CONFIG_PPC64BRIDGE +#define LOAD_BAT(n, reg, RA, RB) \ + ld RA,(n*32)+0(reg); \ + ld RB,(n*32)+8(reg); \ + mtspr SPRN_IBAT##n##U,RA; \ + mtspr SPRN_IBAT##n##L,RB; \ + ld RA,(n*32)+16(reg); \ + ld RB,(n*32)+24(reg); \ + mtspr SPRN_DBAT##n##U,RA; \ + mtspr SPRN_DBAT##n##L,RB; \ + +#else /* CONFIG_PPC64BRIDGE */ + +/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ +#define LOAD_BAT(n, reg, RA, RB) \ + /* see the comment for clear_bats() -- Cort */ \ + li RA,0; \ + mtspr SPRN_IBAT##n##U,RA; \ + mtspr SPRN_DBAT##n##U,RA; \ + lwz RA,(n*16)+0(reg); \ + lwz RB,(n*16)+4(reg); \ + mtspr SPRN_IBAT##n##U,RA; \ + mtspr SPRN_IBAT##n##L,RB; \ + beq 1f; \ + lwz RA,(n*16)+8(reg); \ + lwz RB,(n*16)+12(reg); \ + mtspr SPRN_DBAT##n##U,RA; \ + mtspr SPRN_DBAT##n##L,RB; \ +1: +#endif /* CONFIG_PPC64BRIDGE */ + + .text + .stabs "arch/ppc/kernel/",N_SO,0,0,0f + .stabs "head.S",N_SO,0,0,0f +0: + .globl _stext +_stext: + +/* + * _start is defined this way because the XCOFF loader in the OpenFirmware + * on the powermac expects the entry point to be a procedure descriptor. + */ + .text + .globl _start +_start: + /* + * These are here for legacy reasons, the kernel used to + * need to look like a coff function entry for the pmac + * but we're always started by some kind of bootloader now. + * -- Cort + */ + nop /* used by __secondary_hold on prep (mtx) and chrp smp */ + nop /* used by __secondary_hold on prep (mtx) and chrp smp */ + nop + +/* PMAC + * Enter here with the kernel text, data and bss loaded starting at + * 0, running with virtual == physical mapping. + * r5 points to the prom entry point (the client interface handler + * address). Address translation is turned on, with the prom + * managing the hash table. Interrupts are disabled. The stack + * pointer (r1) points to just below the end of the half-meg region + * from 0x380000 - 0x400000, which is mapped in already. + * + * If we are booted from MacOS via BootX, we enter with the kernel + * image loaded somewhere, and the following values in registers: + * r3: 'BooX' (0x426f6f58) + * r4: virtual address of boot_infos_t + * r5: 0 + * + * APUS + * r3: 'APUS' + * r4: physical address of memory base + * Linux/m68k style BootInfo structure at &_end. + * + * PREP + * This is jumped to on prep systems right after the kernel is relocated + * to its proper place in memory by the boot loader. The expected layout + * of the regs is: + * r3: ptr to residual data + * r4: initrd_start or if no initrd then 0 + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + * + * This just gets a minimal mmu environment setup so we can call + * start_here() to do the real work. + * -- Cort + */ + + .globl __start +__start: +/* + * We have to do any OF calls before we map ourselves to KERNELBASE, + * because OF may have I/O devices mapped into that area + * (particularly on CHRP). + */ + mr r31,r3 /* save parameters */ + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + li r24,0 /* cpu # */ + +/* + * early_init() does the early machine identification and does + * the necessary low-level setup and clears the BSS + * -- Cort + */ + bl early_init + +/* + * On POWER4, we first need to tweak some CPU configuration registers + * like real mode cache inhibit or exception base + */ +#ifdef CONFIG_POWER4 + bl __970_cpu_preinit +#endif /* CONFIG_POWER4 */ + +#ifdef CONFIG_APUS +/* On APUS the __va/__pa constants need to be set to the correct + * values before continuing. + */ + mr r4,r30 + bl fix_mem_constants +#endif /* CONFIG_APUS */ + +/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains + * the physical address we are running at, returned by early_init() + */ + bl mmu_off +__after_mmu_off: +#ifndef CONFIG_POWER4 + bl clear_bats + bl flush_tlbs + + bl initial_bats +#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) + bl setup_disp_bat +#endif +#else /* CONFIG_POWER4 */ + bl reloc_offset + bl initial_mm_power4 +#endif /* CONFIG_POWER4 */ + +/* + * Call setup_cpu for CPU 0 and initialize 6xx Idle + */ + bl reloc_offset + li r24,0 /* cpu# */ + bl call_setup_cpu /* Call setup_cpu for this CPU */ +#ifdef CONFIG_6xx + bl reloc_offset + bl init_idle_6xx +#endif /* CONFIG_6xx */ +#ifdef CONFIG_POWER4 + bl reloc_offset + bl init_idle_power4 +#endif /* CONFIG_POWER4 */ + + +#ifndef CONFIG_APUS +/* + * We need to run with _start at physical address 0. + * On CHRP, we are loaded at 0x10000 since OF on CHRP uses + * the exception vectors at 0 (and therefore this copy + * overwrites OF's exception vectors with our own). + * If the MMU is already turned on, we copy stuff to KERNELBASE, + * otherwise we copy it to 0. + */ + bl reloc_offset + mr r26,r3 + addis r4,r3,KERNELBASE@h /* current address of _start */ + cmpwi 0,r4,0 /* are we already running at 0? */ + bne relocate_kernel +#endif /* CONFIG_APUS */ +/* + * we now have the 1st 16M of ram mapped with the bats. + * prep needs the mmu to be turned on here, but pmac already has it on. + * this shouldn't bother the pmac since it just gets turned on again + * as we jump to our code at KERNELBASE. -- Cort + * Actually no, pmac doesn't have it on any more. BootX enters with MMU + * off, and in other cases, we now turn it off before changing BATs above. + */ +turn_on_mmu: + mfmsr r0 + ori r0,r0,MSR_DR|MSR_IR + mtspr SPRN_SRR1,r0 + lis r0,start_here@h + ori r0,r0,start_here@l + mtspr SPRN_SRR0,r0 + SYNC + RFI /* enables MMU */ + +/* + * We need __secondary_hold as a place to hold the other cpus on + * an SMP machine, even when we are running a UP kernel. + */ + . = 0xc0 /* for prep bootloader */ + li r3,1 /* MTX only has 1 cpu */ + .globl __secondary_hold +__secondary_hold: + /* tell the master we're here */ + stw r3,4(0) +#ifdef CONFIG_SMP +100: lwz r4,0(0) + /* wait until we're told to start */ + cmpw 0,r4,r3 + bne 100b + /* our cpu # was at addr 0 - go */ + mr r24,r3 /* cpu # */ + b __secondary_start +#else + b . +#endif /* CONFIG_SMP */ + +/* + * Exception entry code. This code runs with address translation + * turned off, i.e. using physical addresses. + * We assume sprg3 has the physical address of the current + * task's thread_struct. + */ +#define EXCEPTION_PROLOG \ + mtspr SPRN_SPRG0,r10; \ + mtspr SPRN_SPRG1,r11; \ + mfcr r10; \ + EXCEPTION_PROLOG_1; \ + EXCEPTION_PROLOG_2 + +#define EXCEPTION_PROLOG_1 \ + mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ + andi. r11,r11,MSR_PR; \ + tophys(r11,r1); /* use tophys(r1) if kernel */ \ + beq 1f; \ + mfspr r11,SPRN_SPRG3; \ + lwz r11,THREAD_INFO-THREAD(r11); \ + addi r11,r11,THREAD_SIZE; \ + tophys(r11,r11); \ +1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ + + +#define EXCEPTION_PROLOG_2 \ + CLR_TOP32(r11); \ + stw r10,_CCR(r11); /* save registers */ \ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mfspr r10,SPRN_SPRG0; \ + stw r10,GPR10(r11); \ + mfspr r12,SPRN_SPRG1; \ + stw r12,GPR11(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r12,SPRN_SRR0; \ + mfspr r9,SPRN_SRR1; \ + stw r1,GPR1(r11); \ + stw r1,0(r11); \ + tovirt(r1,r11); /* set new kernel sp */ \ + li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ + MTMSRD(r10); /* (except for mach check in rtas) */ \ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + +/* + * Note: code which follows this uses cr0.eq (set if from kernel), + * r11, r12 (SRR0), and r9 (SRR1). + * + * Note2: once we have set r1 we are in a position to take exceptions + * again, and we could thus set MSR:RI at that point. + */ + +/* + * Exception vectors. + */ +#define EXCEPTION(n, label, hdlr, xfer) \ + . = n; \ +label: \ + EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + xfer(n, hdlr) + +#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ + li r10,trap; \ + stw r10,TRAP(r11); \ + li r10,MSR_KERNEL; \ + copyee(r10, r9); \ + bl tfer; \ +i##n: \ + .long hdlr; \ + .long ret + +#define COPY_EE(d, s) rlwimi d,s,0,16,16 +#define NOCOPY(d, s) + +#define EXC_XFER_STD(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ + ret_from_except) + +#define EXC_XFER_EE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_EE_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ + ret_from_except) + +/* System reset */ +/* core99 pmac starts the seconary here by changing the vector, and + putting it back to what it was (UnknownException) when done. */ +#if defined(CONFIG_GEMINI) && defined(CONFIG_SMP) + . = 0x100 + b __secondary_start_gemini +#else + EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD) +#endif + +/* Machine check */ +/* + * On CHRP, this is complicated by the fact that we could get a + * machine check inside RTAS, and we have no guarantee that certain + * critical registers will have the values we expect. The set of + * registers that might have bad values includes all the GPRs + * and all the BATs. We indicate that we are in RTAS by putting + * a non-zero value, the address of the exception frame to use, + * in SPRG2. The machine check handler checks SPRG2 and uses its + * value if it is non-zero. If we ever needed to free up SPRG2, + * we could use a field in the thread_info or thread_struct instead. + * (Other exception handlers assume that r1 is a valid kernel stack + * pointer when we take an exception from supervisor mode.) + * -- paulus. + */ + . = 0x200 + mtspr SPRN_SPRG0,r10 + mtspr SPRN_SPRG1,r11 + mfcr r10 +#ifdef CONFIG_PPC_CHRP + mfspr r11,SPRN_SPRG2 + cmpwi 0,r11,0 + bne 7f +#endif /* CONFIG_PPC_CHRP */ + EXCEPTION_PROLOG_1 +7: EXCEPTION_PROLOG_2 + addi r3,r1,STACK_FRAME_OVERHEAD +#ifdef CONFIG_PPC_CHRP + mfspr r4,SPRN_SPRG2 + cmpwi cr1,r4,0 + bne cr1,1f +#endif + EXC_XFER_STD(0x200, MachineCheckException) +#ifdef CONFIG_PPC_CHRP +1: b machine_check_in_rtas +#endif + +/* Data access exception. */ + . = 0x300 +#ifdef CONFIG_PPC64BRIDGE + b DataAccess +DataAccessCont: +#else +DataAccess: + EXCEPTION_PROLOG +#endif /* CONFIG_PPC64BRIDGE */ + mfspr r10,SPRN_DSISR + andis. r0,r10,0xa470 /* weird error? */ + bne 1f /* if not, try to put a PTE */ + mfspr r4,SPRN_DAR /* into the hash table */ + rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ + bl hash_page +1: stw r10,_DSISR(r11) + mr r5,r10 + mfspr r4,SPRN_DAR + EXC_XFER_EE_LITE(0x300, handle_page_fault) + +#ifdef CONFIG_PPC64BRIDGE +/* SLB fault on data access. */ + . = 0x380 + b DataSegment +#endif /* CONFIG_PPC64BRIDGE */ + +/* Instruction access exception. */ + . = 0x400 +#ifdef CONFIG_PPC64BRIDGE + b InstructionAccess +InstructionAccessCont: +#else +InstructionAccess: + EXCEPTION_PROLOG +#endif /* CONFIG_PPC64BRIDGE */ + andis. r0,r9,0x4000 /* no pte found? */ + beq 1f /* if so, try to put a PTE */ + li r3,0 /* into the hash table */ + mr r4,r12 /* SRR0 is fault address */ + bl hash_page +1: mr r4,r12 + mr r5,r9 + EXC_XFER_EE_LITE(0x400, handle_page_fault) + +#ifdef CONFIG_PPC64BRIDGE +/* SLB fault on instruction access. */ + . = 0x480 + b InstructionSegment +#endif /* CONFIG_PPC64BRIDGE */ + +/* External interrupt */ + EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) + +/* Alignment exception */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,SPRN_DAR + stw r4,_DAR(r11) + mfspr r5,SPRN_DSISR + stw r5,_DSISR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE(0x600, AlignmentException) + +/* Program check exception */ + EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_STD) + +/* Floating-point unavailable */ + . = 0x800 +FPUnavailable: + EXCEPTION_PROLOG + bne load_up_fpu /* if from user, just load it up */ + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE_LITE(0x800, KernelFP) + +/* Decrementer */ + EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) + + EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE) + EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE) + +/* System call */ + . = 0xc00 +SystemCall: + EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0xc00, DoSyscall) + +/* Single step - not used on 601 */ + EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_STD) + EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE) + +/* + * The Altivec unavailable trap is at 0x0f20. Foo. + * We effectively remap it to 0x3000. + * We include an altivec unavailable exception vector even if + * not configured for Altivec, so that you can't panic a + * non-altivec kernel running on a machine with altivec just + * by executing an altivec instruction. + */ + . = 0xf00 + b Trap_0f + + . = 0xf20 + b AltiVecUnavailable + +Trap_0f: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE(0xf00, UnknownException) + +/* + * Handle TLB miss for instruction on 603/603e. + * Note: we get an alternate set of r0 - r3 to use automatically. + */ + . = 0x1000 +InstructionTLBMiss: +/* + * r0: stored ctr + * r1: linux style pte ( later becomes ppc hardware pte ) + * r2: ptr to linux-style pte + * r3: scratch + */ + mfctr r0 + /* Get PTE (linux-style) and check access */ + mfspr r3,SPRN_IMISS + lis r1,KERNELBASE@h /* check if kernel address */ + cmplw 0,r3,r1 + mfspr r2,SPRN_SPRG3 + li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ + lwz r2,PGDIR(r2) + blt+ 112f + lis r2,swapper_pg_dir@ha /* if kernel address, use */ + addi r2,r2,swapper_pg_dir@l /* kernel page table */ + mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ +112: tophys(r2,r2) + rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ + lwz r2,0(r2) /* get pmd entry */ + rlwinm. r2,r2,0,0,19 /* extract address of pte page */ + beq- InstructionAddressInvalid /* return if no mapping */ + rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ + lwz r3,0(r2) /* get linux-style pte */ + andc. r1,r1,r3 /* check access & ~permission */ + bne- InstructionAddressInvalid /* return if access not permitted */ + ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ + /* + * NOTE! We are assuming this is not an SMP system, otherwise + * we would need to update the pte atomically with lwarx/stwcx. + */ + stw r3,0(r2) /* update PTE (accessed bit) */ + /* Convert linux-style PTE to low word of PPC-style PTE */ + rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ + rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ + and r1,r1,r2 /* writable if _RW and _DIRTY */ + rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ + rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ + ori r1,r1,0xe14 /* clear out reserved bits and M */ + andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ + mtspr SPRN_RPA,r1 + mfspr r3,SPRN_IMISS + tlbli r3 + mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r3 + rfi +InstructionAddressInvalid: + mfspr r3,SPRN_SRR1 + rlwinm r1,r3,9,6,6 /* Get load/store bit */ + + addis r1,r1,0x2000 + mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ + mtctr r0 /* Restore CTR */ + andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ + or r2,r2,r1 + mtspr SPRN_SRR1,r2 + mfspr r1,SPRN_IMISS /* Get failing address */ + rlwinm. r2,r2,0,31,31 /* Check for little endian access */ + rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ + xor r1,r1,r2 + mtspr SPRN_DAR,r1 /* Set fault address */ + mfmsr r0 /* Restore "normal" registers */ + xoris r0,r0,MSR_TGPR>>16 + mtcrf 0x80,r3 /* Restore CR0 */ + mtmsr r0 + b InstructionAccess + +/* + * Handle TLB miss for DATA Load operation on 603/603e + */ + . = 0x1100 +DataLoadTLBMiss: +/* + * r0: stored ctr + * r1: linux style pte ( later becomes ppc hardware pte ) + * r2: ptr to linux-style pte + * r3: scratch + */ + mfctr r0 + /* Get PTE (linux-style) and check access */ + mfspr r3,SPRN_DMISS + lis r1,KERNELBASE@h /* check if kernel address */ + cmplw 0,r3,r1 + mfspr r2,SPRN_SPRG3 + li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ + lwz r2,PGDIR(r2) + blt+ 112f + lis r2,swapper_pg_dir@ha /* if kernel address, use */ + addi r2,r2,swapper_pg_dir@l /* kernel page table */ + mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ +112: tophys(r2,r2) + rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ + lwz r2,0(r2) /* get pmd entry */ + rlwinm. r2,r2,0,0,19 /* extract address of pte page */ + beq- DataAddressInvalid /* return if no mapping */ + rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ + lwz r3,0(r2) /* get linux-style pte */ + andc. r1,r1,r3 /* check access & ~permission */ + bne- DataAddressInvalid /* return if access not permitted */ + ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ + /* + * NOTE! We are assuming this is not an SMP system, otherwise + * we would need to update the pte atomically with lwarx/stwcx. + */ + stw r3,0(r2) /* update PTE (accessed bit) */ + /* Convert linux-style PTE to low word of PPC-style PTE */ + rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ + rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ + and r1,r1,r2 /* writable if _RW and _DIRTY */ + rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ + rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ + ori r1,r1,0xe14 /* clear out reserved bits and M */ + andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ + mtspr SPRN_RPA,r1 + mfspr r3,SPRN_DMISS + tlbld r3 + mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r3 + rfi +DataAddressInvalid: + mfspr r3,SPRN_SRR1 + rlwinm r1,r3,9,6,6 /* Get load/store bit */ + addis r1,r1,0x2000 + mtspr SPRN_DSISR,r1 + mtctr r0 /* Restore CTR */ + andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ + mtspr SPRN_SRR1,r2 + mfspr r1,SPRN_DMISS /* Get failing address */ + rlwinm. r2,r2,0,31,31 /* Check for little endian access */ + beq 20f /* Jump if big endian */ + xori r1,r1,3 +20: mtspr SPRN_DAR,r1 /* Set fault address */ + mfmsr r0 /* Restore "normal" registers */ + xoris r0,r0,MSR_TGPR>>16 + mtcrf 0x80,r3 /* Restore CR0 */ + mtmsr r0 + b DataAccess + +/* + * Handle TLB miss for DATA Store on 603/603e + */ + . = 0x1200 +DataStoreTLBMiss: +/* + * r0: stored ctr + * r1: linux style pte ( later becomes ppc hardware pte ) + * r2: ptr to linux-style pte + * r3: scratch + */ + mfctr r0 + /* Get PTE (linux-style) and check access */ + mfspr r3,SPRN_DMISS + lis r1,KERNELBASE@h /* check if kernel address */ + cmplw 0,r3,r1 + mfspr r2,SPRN_SPRG3 + li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ + lwz r2,PGDIR(r2) + blt+ 112f + lis r2,swapper_pg_dir@ha /* if kernel address, use */ + addi r2,r2,swapper_pg_dir@l /* kernel page table */ + mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ + rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ +112: tophys(r2,r2) + rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ + lwz r2,0(r2) /* get pmd entry */ + rlwinm. r2,r2,0,0,19 /* extract address of pte page */ + beq- DataAddressInvalid /* return if no mapping */ + rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ + lwz r3,0(r2) /* get linux-style pte */ + andc. r1,r1,r3 /* check access & ~permission */ + bne- DataAddressInvalid /* return if access not permitted */ + ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY + /* + * NOTE! We are assuming this is not an SMP system, otherwise + * we would need to update the pte atomically with lwarx/stwcx. + */ + stw r3,0(r2) /* update PTE (accessed/dirty bits) */ + /* Convert linux-style PTE to low word of PPC-style PTE */ + rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ + li r1,0xe15 /* clear out reserved bits and M */ + andc r1,r3,r1 /* PP = user? 2: 0 */ + mtspr SPRN_RPA,r1 + mfspr r3,SPRN_DMISS + tlbld r3 + mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ + mtcrf 0x80,r3 + rfi + +#ifndef CONFIG_ALTIVEC +#define AltivecAssistException UnknownException +#endif + + EXCEPTION(0x1300, Trap_13, InstructionBreakpoint, EXC_XFER_EE) + EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) + EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE) +#ifdef CONFIG_POWER4 + EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1700, Trap_17, AltivecAssistException, EXC_XFER_EE) + EXCEPTION(0x1800, Trap_18, TAUException, EXC_XFER_STD) +#else /* !CONFIG_POWER4 */ + EXCEPTION(0x1600, Trap_16, AltivecAssistException, EXC_XFER_EE) + EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) + EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE) +#endif /* CONFIG_POWER4 */ + EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) + EXCEPTION(0x2100, Trap_21, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2200, Trap_22, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2300, Trap_23, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2400, Trap_24, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2500, Trap_25, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2600, Trap_26, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2700, Trap_27, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2800, Trap_28, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2900, Trap_29, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2a00, Trap_2a, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2b00, Trap_2b, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2c00, Trap_2c, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2d00, Trap_2d, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2e00, Trap_2e, UnknownException, EXC_XFER_EE) + EXCEPTION(0x2f00, MOLTrampoline, UnknownException, EXC_XFER_EE_LITE) + + .globl mol_trampoline + .set mol_trampoline, i0x2f00 + + . = 0x3000 + +AltiVecUnavailable: + EXCEPTION_PROLOG +#ifdef CONFIG_ALTIVEC + bne load_up_altivec /* if from user, just load it up */ +#endif /* CONFIG_ALTIVEC */ + EXC_XFER_EE_LITE(0xf20, AltivecUnavailException) + +#ifdef CONFIG_PPC64BRIDGE +DataAccess: + EXCEPTION_PROLOG + b DataAccessCont + +InstructionAccess: + EXCEPTION_PROLOG + b InstructionAccessCont + +DataSegment: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + mfspr r4,SPRN_DAR + stw r4,_DAR(r11) + EXC_XFER_STD(0x380, UnknownException) + +InstructionSegment: + EXCEPTION_PROLOG + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_STD(0x480, UnknownException) +#endif /* CONFIG_PPC64BRIDGE */ + +#ifdef CONFIG_ALTIVEC +/* Note that the AltiVec support is closely modeled after the FP + * support. Changes to one are likely to be applicable to the + * other! */ +load_up_altivec: +/* + * Disable AltiVec for the task which had AltiVec previously, + * and save its AltiVec registers in its thread_struct. + * Enables AltiVec for use in the kernel on return. + * On SMP we know the AltiVec units are free, since we give it up every + * switch. -- Kumar + */ + mfmsr r5 + oris r5,r5,MSR_VEC@h + MTMSRD(r5) /* enable use of AltiVec now */ + isync +/* + * For SMP, we don't do lazy AltiVec switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_altivec in switch_to. + */ +#ifndef CONFIG_SMP + tophys(r6,0) + addis r3,r6,last_task_used_altivec@ha + lwz r4,last_task_used_altivec@l(r3) + cmpwi 0,r4,0 + beq 1f + add r4,r4,r6 + addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ + SAVE_32VRS(0,r10,r4) + mfvscr vr0 + li r10,THREAD_VSCR + stvx vr0,r10,r4 + lwz r5,PT_REGS(r4) + add r5,r5,r6 + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r10,MSR_VEC@h + andc r4,r4,r10 /* disable altivec for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /* enable use of AltiVec after return */ + oris r9,r9,MSR_VEC@h + mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ + li r4,1 + li r10,THREAD_VSCR + stw r4,THREAD_USED_VR(r5) + lvx vr0,r10,r5 + mtvscr vr0 + REST_32VRS(0,r10,r5) +#ifndef CONFIG_SMP + subi r4,r5,THREAD + sub r4,r4,r6 + stw r4,last_task_used_altivec@l(r3) +#endif /* CONFIG_SMP */ + /* restore registers and return */ + /* we haven't used ctr or xer or lr */ + b fast_exception_return + +/* + * AltiVec unavailable trap from kernel - print a message, but let + * the task use AltiVec in the kernel until it returns to user mode. + */ +KernelAltiVec: + lwz r3,_MSR(r1) + oris r3,r3,MSR_VEC@h + stw r3,_MSR(r1) /* enable use of AltiVec after return */ + lis r3,87f@h + ori r3,r3,87f@l + mr r4,r2 /* current */ + lwz r5,_NIP(r1) + bl printk + b ret_from_except +87: .string "AltiVec used in kernel (task=%p, pc=%x) \n" + .align 4,0 + +/* + * giveup_altivec(tsk) + * Disable AltiVec for the task given as the argument, + * and save the AltiVec registers in its thread_struct. + * Enables AltiVec for use in the kernel on return. + */ + + .globl giveup_altivec +giveup_altivec: + mfmsr r5 + oris r5,r5,MSR_VEC@h + SYNC + MTMSRD(r5) /* enable use of AltiVec now */ + isync + cmpwi 0,r3,0 + beqlr- /* if no previous owner, done */ + addi r3,r3,THREAD /* want THREAD of task */ + lwz r5,PT_REGS(r3) + cmpwi 0,r5,0 + SAVE_32VRS(0, r4, r3) + mfvscr vr0 + li r4,THREAD_VSCR + stvx vr0,r4,r3 + beq 1f + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r3,MSR_VEC@h + andc r4,r4,r3 /* disable AltiVec for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#ifndef CONFIG_SMP + li r5,0 + lis r4,last_task_used_altivec@ha + stw r5,last_task_used_altivec@l(r4) +#endif /* CONFIG_SMP */ + blr +#endif /* CONFIG_ALTIVEC */ + +/* + * This code is jumped to from the startup code to copy + * the kernel image to physical address 0. + */ +relocate_kernel: + addis r9,r26,klimit@ha /* fetch klimit */ + lwz r25,klimit@l(r9) + addis r25,r25,-KERNELBASE@h + li r3,0 /* Destination base address */ + li r6,0 /* Destination offset */ + li r5,0x4000 /* # bytes of memory to copy */ + bl copy_and_flush /* copy the first 0x4000 bytes */ + addi r0,r3,4f@l /* jump to the address of 4f */ + mtctr r0 /* in copy and do the rest. */ + bctr /* jump to the copy */ +4: mr r5,r25 + bl copy_and_flush /* copy the rest */ + b turn_on_mmu + +/* + * Copy routine used to copy the kernel to start at physical address 0 + * and flush and invalidate the caches as needed. + * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset + * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. + */ +copy_and_flush: + addi r5,r5,-4 + addi r6,r6,-4 +4: li r0,L1_CACHE_LINE_SIZE/4 + mtctr r0 +3: addi r6,r6,4 /* copy a cache line */ + lwzx r0,r6,r4 + stwx r0,r6,r3 + bdnz 3b + dcbst r6,r3 /* write it to memory */ + sync + icbi r6,r3 /* flush the icache line */ + cmplw 0,r6,r5 + blt 4b + sync /* additional sync needed on g4 */ + isync + addi r5,r5,4 + addi r6,r6,4 + blr + +#ifdef CONFIG_APUS +/* + * On APUS the physical base address of the kernel is not known at compile + * time, which means the __pa/__va constants used are incorrect. In the + * __init section is recorded the virtual addresses of instructions using + * these constants, so all that has to be done is fix these before + * continuing the kernel boot. + * + * r4 = The physical address of the kernel base. + */ +fix_mem_constants: + mr r10,r4 + addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */ + neg r11,r10 /* phys_to_virt constant */ + + lis r12,__vtop_table_begin@h + ori r12,r12,__vtop_table_begin@l + add r12,r12,r10 /* table begin phys address */ + lis r13,__vtop_table_end@h + ori r13,r13,__vtop_table_end@l + add r13,r13,r10 /* table end phys address */ + subi r12,r12,4 + subi r13,r13,4 +1: lwzu r14,4(r12) /* virt address of instruction */ + add r14,r14,r10 /* phys address of instruction */ + lwz r15,0(r14) /* instruction, now insert top */ + rlwimi r15,r10,16,16,31 /* half of vp const in low half */ + stw r15,0(r14) /* of instruction and restore. */ + dcbst r0,r14 /* write it to memory */ + sync + icbi r0,r14 /* flush the icache line */ + cmpw r12,r13 + bne 1b + sync /* additional sync needed on g4 */ + isync + +/* + * Map the memory where the exception handlers will + * be copied to when hash constants have been patched. + */ +#ifdef CONFIG_APUS_FAST_EXCEPT + lis r8,0xfff0 +#else + lis r8,0 +#endif + ori r8,r8,0x2 /* 128KB, supervisor */ + mtspr SPRN_DBAT3U,r8 + mtspr SPRN_DBAT3L,r8 + + lis r12,__ptov_table_begin@h + ori r12,r12,__ptov_table_begin@l + add r12,r12,r10 /* table begin phys address */ + lis r13,__ptov_table_end@h + ori r13,r13,__ptov_table_end@l + add r13,r13,r10 /* table end phys address */ + subi r12,r12,4 + subi r13,r13,4 +1: lwzu r14,4(r12) /* virt address of instruction */ + add r14,r14,r10 /* phys address of instruction */ + lwz r15,0(r14) /* instruction, now insert top */ + rlwimi r15,r11,16,16,31 /* half of pv const in low half*/ + stw r15,0(r14) /* of instruction and restore. */ + dcbst r0,r14 /* write it to memory */ + sync + icbi r0,r14 /* flush the icache line */ + cmpw r12,r13 + bne 1b + + sync /* additional sync needed on g4 */ + isync /* No speculative loading until now */ + blr + +/*********************************************************************** + * Please note that on APUS the exception handlers are located at the + * physical address 0xfff0000. For this reason, the exception handlers + * cannot use relative branches to access the code below. + ***********************************************************************/ +#endif /* CONFIG_APUS */ + +#ifdef CONFIG_SMP +#ifdef CONFIG_GEMINI + .globl __secondary_start_gemini +__secondary_start_gemini: + mfspr r4,SPRN_HID0 + ori r4,r4,HID0_ICFI + li r3,0 + ori r3,r3,HID0_ICE + andc r4,r4,r3 + mtspr SPRN_HID0,r4 + sync + b __secondary_start +#endif /* CONFIG_GEMINI */ + + .globl __secondary_start_pmac_0 +__secondary_start_pmac_0: + /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ + li r24,0 + b 1f + li r24,1 + b 1f + li r24,2 + b 1f + li r24,3 +1: + /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 + set to map the 0xf0000000 - 0xffffffff region */ + mfmsr r0 + rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ + SYNC + mtmsr r0 + isync + + .globl __secondary_start +__secondary_start: +#ifdef CONFIG_PPC64BRIDGE + mfmsr r0 + clrldi r0,r0,1 /* make sure it's in 32-bit mode */ + SYNC + MTMSRD(r0) + isync +#endif + /* Copy some CPU settings from CPU 0 */ + bl __restore_cpu_setup + + lis r3,-KERNELBASE@h + mr r4,r24 + bl identify_cpu + bl call_setup_cpu /* Call setup_cpu for this CPU */ +#ifdef CONFIG_6xx + lis r3,-KERNELBASE@h + bl init_idle_6xx +#endif /* CONFIG_6xx */ +#ifdef CONFIG_POWER4 + lis r3,-KERNELBASE@h + bl init_idle_power4 +#endif /* CONFIG_POWER4 */ + + /* get current_thread_info and current */ + lis r1,secondary_ti@ha + tophys(r1,r1) + lwz r1,secondary_ti@l(r1) + tophys(r2,r1) + lwz r2,TI_TASK(r2) + + /* stack */ + addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD + li r0,0 + tophys(r3,r1) + stw r0,0(r3) + + /* load up the MMU */ + bl load_up_mmu + + /* ptr to phys current thread */ + tophys(r4,r2) + addi r4,r4,THREAD /* phys address of our thread_struct */ + CLR_TOP32(r4) + mtspr SPRN_SPRG3,r4 + li r3,0 + mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ + + /* enable MMU and jump to start_secondary */ + li r4,MSR_KERNEL + FIX_SRR1(r4,r5) + lis r3,start_secondary@h + ori r3,r3,start_secondary@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + SYNC + RFI +#endif /* CONFIG_SMP */ + +/* + * Those generic dummy functions are kept for CPUs not + * included in CONFIG_6xx + */ +_GLOBAL(__setup_cpu_power3) + blr +_GLOBAL(__setup_cpu_generic) + blr + +#if !defined(CONFIG_6xx) && !defined(CONFIG_POWER4) +_GLOBAL(__save_cpu_setup) + blr +_GLOBAL(__restore_cpu_setup) + blr +#endif /* !defined(CONFIG_6xx) && !defined(CONFIG_POWER4) */ + + +/* + * Load stuff into the MMU. Intended to be called with + * IR=0 and DR=0. + */ +load_up_mmu: + sync /* Force all PTE updates to finish */ + isync + tlbia /* Clear all TLB entries */ + sync /* wait for tlbia/tlbie to finish */ + TLBSYNC /* ... on all CPUs */ + /* Load the SDR1 register (hash table base & size) */ + lis r6,_SDR1@ha + tophys(r6,r6) + lwz r6,_SDR1@l(r6) + mtspr SPRN_SDR1,r6 +#ifdef CONFIG_PPC64BRIDGE + /* clear the ASR so we only use the pseudo-segment registers. */ + li r6,0 + mtasr r6 +#endif /* CONFIG_PPC64BRIDGE */ + li r0,16 /* load up segment register values */ + mtctr r0 /* for context 0 */ + lis r3,0x2000 /* Ku = 1, VSID = 0 */ + li r4,0 +3: mtsrin r3,r4 + addi r3,r3,0x111 /* increment VSID */ + addis r4,r4,0x1000 /* address of next segment */ + bdnz 3b +#ifndef CONFIG_POWER4 +/* Load the BAT registers with the values set up by MMU_init. + MMU_init takes care of whether we're on a 601 or not. */ + mfpvr r3 + srwi r3,r3,16 + cmpwi r3,1 + lis r3,BATS@ha + addi r3,r3,BATS@l + tophys(r3,r3) + LOAD_BAT(0,r3,r4,r5) + LOAD_BAT(1,r3,r4,r5) + LOAD_BAT(2,r3,r4,r5) + LOAD_BAT(3,r3,r4,r5) +#endif /* CONFIG_POWER4 */ + blr + +/* + * This is where the main kernel code starts. + */ +start_here: + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + /* Set up for using our exception vectors */ + /* ptr to phys current thread */ + tophys(r4,r2) + addi r4,r4,THREAD /* init task's THREAD */ + CLR_TOP32(r4) + mtspr SPRN_SPRG3,r4 + li r3,0 + mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ + + /* stack */ + lis r1,init_thread_union@ha + addi r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) +/* + * Do early bootinfo parsing, platform-specific initialization, + * and set up the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + +#ifdef CONFIG_APUS + /* Copy exception code to exception vector base on APUS. */ + lis r4,KERNELBASE@h +#ifdef CONFIG_APUS_FAST_EXCEPT + lis r3,0xfff0 /* Copy to 0xfff00000 */ +#else + lis r3,0 /* Copy to 0x00000000 */ +#endif + li r5,0x4000 /* # bytes of memory to copy */ + li r6,0 + bl copy_and_flush /* copy the first 0x4000 bytes */ +#endif /* CONFIG_APUS */ + +/* + * Go back to running unmapped so we can load up new values + * for SDR1 (hash table pointer) and the segment registers + * and change to using our exception vectors. + */ + lis r4,2f@h + ori r4,r4,2f@l + tophys(r4,r4) + li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) + FIX_SRR1(r3,r5) + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + SYNC + RFI +/* Load up the kernel context */ +2: bl load_up_mmu + +#ifdef CONFIG_BDI_SWITCH + /* Add helper information for the Abatron bdiGDB debugger. + * We do this here because we know the mmu is disabled, and + * will be enabled for real in just a few instructions. + */ + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r5, 0xf0(r0) /* This much match your Abatron config */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + tophys(r5, r5) + stw r6, 0(r5) +#endif /* CONFIG_BDI_SWITCH */ + +/* Now turn on the MMU for real! */ + li r4,MSR_KERNEL + FIX_SRR1(r4,r5) + lis r3,start_kernel@h + ori r3,r3,start_kernel@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + SYNC + RFI + +/* + * Set up the segment registers for a new context. + */ +_GLOBAL(set_context) + mulli r3,r3,897 /* multiply context by skew factor */ + rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ + addis r3,r3,0x6000 /* Set Ks, Ku bits */ + li r0,NUM_USER_SEGMENTS + mtctr r0 + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is passed as second argument. + */ + lis r5, KERNELBASE@h + lwz r5, 0xf0(r5) + stw r4, 0x4(r5) +#endif + li r4,0 + isync +3: +#ifdef CONFIG_PPC64BRIDGE + slbie r4 +#endif /* CONFIG_PPC64BRIDGE */ + mtsrin r3,r4 + addi r3,r3,0x111 /* next VSID */ + rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ + addis r4,r4,0x1000 /* address of next segment */ + bdnz 3b + sync + isync + blr + +/* + * An undocumented "feature" of 604e requires that the v bit + * be cleared before changing BAT values. + * + * Also, newer IBM firmware does not clear bat3 and 4 so + * this makes sure it's done. + * -- Cort + */ +clear_bats: + li r10,0 + mfspr r9,SPRN_PVR + rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ + cmpwi r9, 1 + beq 1f + + mtspr SPRN_DBAT0U,r10 + mtspr SPRN_DBAT0L,r10 + mtspr SPRN_DBAT1U,r10 + mtspr SPRN_DBAT1L,r10 + mtspr SPRN_DBAT2U,r10 + mtspr SPRN_DBAT2L,r10 + mtspr SPRN_DBAT3U,r10 + mtspr SPRN_DBAT3L,r10 +1: + mtspr SPRN_IBAT0U,r10 + mtspr SPRN_IBAT0L,r10 + mtspr SPRN_IBAT1U,r10 + mtspr SPRN_IBAT1L,r10 + mtspr SPRN_IBAT2U,r10 + mtspr SPRN_IBAT2L,r10 + mtspr SPRN_IBAT3U,r10 + mtspr SPRN_IBAT3L,r10 +BEGIN_FTR_SECTION + /* Here's a tweak: at this point, CPU setup have + * not been called yet, so HIGH_BAT_EN may not be + * set in HID0 for the 745x processors. However, it + * seems that doesn't affect our ability to actually + * write to these SPRs. + */ + mtspr SPRN_DBAT4U,r10 + mtspr SPRN_DBAT4L,r10 + mtspr SPRN_DBAT5U,r10 + mtspr SPRN_DBAT5L,r10 + mtspr SPRN_DBAT6U,r10 + mtspr SPRN_DBAT6L,r10 + mtspr SPRN_DBAT7U,r10 + mtspr SPRN_DBAT7L,r10 + mtspr SPRN_IBAT4U,r10 + mtspr SPRN_IBAT4L,r10 + mtspr SPRN_IBAT5U,r10 + mtspr SPRN_IBAT5L,r10 + mtspr SPRN_IBAT6U,r10 + mtspr SPRN_IBAT6L,r10 + mtspr SPRN_IBAT7U,r10 + mtspr SPRN_IBAT7L,r10 +END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) + blr + +flush_tlbs: + lis r10, 0x40 +1: addic. r10, r10, -0x1000 + tlbie r10 + blt 1b + sync + blr + +mmu_off: + addi r4, r3, __after_mmu_off - _start + mfmsr r3 + andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ + beqlr + andc r3,r3,r0 + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + sync + RFI + +#ifndef CONFIG_POWER4 +/* + * Use the first pair of BAT registers to map the 1st 16MB + * of RAM to KERNELBASE. From this point on we can't safely + * call OF any more. + */ +initial_bats: + lis r11,KERNELBASE@h +#ifndef CONFIG_PPC64BRIDGE + mfspr r9,SPRN_PVR + rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ + cmpwi 0,r9,1 + bne 4f + ori r11,r11,4 /* set up BAT registers for 601 */ + li r8,0x7f /* valid, block length = 8MB */ + oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ + oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ + mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ + mtspr SPRN_IBAT0L,r8 /* lower BAT register */ + mtspr SPRN_IBAT1U,r9 + mtspr SPRN_IBAT1L,r10 + isync + blr +#endif /* CONFIG_PPC64BRIDGE */ + +4: tophys(r8,r11) +#ifdef CONFIG_SMP + ori r8,r8,0x12 /* R/W access, M=1 */ +#else + ori r8,r8,2 /* R/W access */ +#endif /* CONFIG_SMP */ +#ifdef CONFIG_APUS + ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */ +#else + ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ +#endif /* CONFIG_APUS */ + +#ifdef CONFIG_PPC64BRIDGE + /* clear out the high 32 bits in the BAT */ + clrldi r11,r11,32 + clrldi r8,r8,32 +#endif /* CONFIG_PPC64BRIDGE */ + mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ + mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ + mtspr SPRN_IBAT0L,r8 + mtspr SPRN_IBAT0U,r11 + isync + blr + +#if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) +setup_disp_bat: + /* + * setup the display bat prepared for us in prom.c + */ + mflr r8 + bl reloc_offset + mtlr r8 + addis r8,r3,disp_BAT@ha + addi r8,r8,disp_BAT@l + lwz r11,0(r8) + lwz r8,4(r8) + mfspr r9,SPRN_PVR + rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ + cmpwi 0,r9,1 + beq 1f + mtspr SPRN_DBAT3L,r8 + mtspr SPRN_DBAT3U,r11 + blr +1: mtspr SPRN_IBAT3L,r8 + mtspr SPRN_IBAT3U,r11 + blr + +#endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */ + +#else /* CONFIG_POWER4 */ +/* + * Load up the SDR1 and segment register values now + * since we don't have the BATs. + * Also make sure we are running in 32-bit mode. + */ + +initial_mm_power4: + addis r14,r3,_SDR1@ha /* get the value from _SDR1 */ + lwz r14,_SDR1@l(r14) /* assume hash table below 4GB */ + mtspr SPRN_SDR1,r14 + slbia + lis r4,0x2000 /* set pseudo-segment reg 12 */ + ori r5,r4,0x0ccc + mtsr 12,r5 +#if 0 + ori r5,r4,0x0888 /* set pseudo-segment reg 8 */ + mtsr 8,r5 /* (for access to serial port) */ +#endif +#ifdef CONFIG_BOOTX_TEXT + ori r5,r4,0x0999 /* set pseudo-segment reg 9 */ + mtsr 9,r5 /* (for access to screen) */ +#endif + mfmsr r0 + clrldi r0,r0,1 + sync + mtmsr r0 + isync + blr + +#endif /* CONFIG_POWER4 */ + +#ifdef CONFIG_8260 +/* Jump into the system reset for the rom. + * We first disable the MMU, and then jump to the ROM reset address. + * + * r3 is the board info structure, r4 is the location for starting. + * I use this for building a small kernel that can load other kernels, + * rather than trying to write or rely on a rom monitor that can tftp load. + */ + .globl m8260_gorom +m8260_gorom: + mfmsr r0 + rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ + sync + mtmsr r0 + sync + mfspr r11, SPRN_HID0 + lis r10, 0 + ori r10,r10,HID0_ICE|HID0_DCE + andc r11, r11, r10 + mtspr SPRN_HID0, r11 + isync + li r5, MSR_ME|MSR_RI + lis r6,2f@h + addis r6,r6,-KERNELBASE@h + ori r6,r6,2f@l + mtspr SPRN_SRR0,r6 + mtspr SPRN_SRR1,r5 + isync + sync + rfi +2: + mtlr r4 + blr +#endif + + +/* + * We put a few things here that have to be page-aligned. + * This stuff goes at the beginning of the data segment, + * which is page-aligned. + */ + .data + .globl sdata +sdata: + .globl empty_zero_page +empty_zero_page: + .space 4096 + + .globl swapper_pg_dir +swapper_pg_dir: + .space 4096 + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * Used to pass parameters into the kernel like root=/dev/sda1, etc. + */ + .globl cmd_line +cmd_line: + .space 512 + + .globl intercept_table +intercept_table: + .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 + .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 + .long 0, 0, 0, i0x1300, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 + .long 0, 0, 0, 0, 0, 0, 0, 0 + +/* Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S new file mode 100644 index 00000000000..599245b0407 --- /dev/null +++ b/arch/powerpc/kernel/head_44x.S @@ -0,0 +1,778 @@ +/* + * arch/ppc/kernel/head_44x.S + * + * Kernel execution entry point code. + * + * Copyright (c) 1995-1996 Gary Thomas + * Initial PowerPC version. + * Copyright (c) 1996 Cort Dougan + * Rewritten for PReP + * Copyright (c) 1996 Paul Mackerras + * Low-level exception handers, MMU support, and rewrite. + * Copyright (c) 1997 Dan Malek + * PowerPC 8xx modifications. + * Copyright (c) 1998-1999 TiVo, Inc. + * PowerPC 403GCX modifications. + * Copyright (c) 1999 Grant Erickson + * PowerPC 403GCX/405GP modifications. + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * PowerPC 403GCX/405GP modifications. + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or source@mvista.com + * debbie_chu@mvista.com + * Copyright 2002-2005 MontaVista Software, Inc. + * PowerPC 44x support, Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "head_booke.h" + + +/* As with the other PowerPC ports, it is expected that when code + * execution begins here, the following registers contain valid, yet + * optional, information: + * + * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) + * r4 - Starting address of the init RAM disk + * r5 - Ending address of the init RAM disk + * r6 - Start of kernel command line string (e.g. "mem=128") + * r7 - End of kernel command line string + * + */ + .text +_GLOBAL(_stext) +_GLOBAL(_start) + /* + * Reserve a word at a fixed location to store the address + * of abatron_pteptrs + */ + nop +/* + * Save parameters we are passed + */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + li r24,0 /* CPU number */ + +/* + * Set up the initial MMU state + * + * We are still executing code at the virtual address + * mappings set by the firmware for the base of RAM. + * + * We first invalidate all TLB entries but the one + * we are running from. We then load the KERNELBASE + * mappings so we can begin to use kernel addresses + * natively and so the interrupt vector locations are + * permanently pinned (necessary since Book E + * implementations always have translation enabled). + * + * TODO: Use the known TLB entry we are running from to + * determine which physical region we are located + * in. This can be used to determine where in RAM + * (on a shared CPU system) or PCI memory space + * (on a DRAMless system) we are located. + * For now, we assume a perfect world which means + * we are located at the base of DRAM (physical 0). + */ + +/* + * Search TLB for entry that we are currently using. + * Invalidate all entries but the one we are using. + */ + /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */ + mfspr r3,SPRN_PID /* Get PID */ + mfmsr r4 /* Get MSR */ + andi. r4,r4,MSR_IS@l /* TS=1? */ + beq wmmucr /* If not, leave STS=0 */ + oris r3,r3,PPC44x_MMUCR_STS@h /* Set STS=1 */ +wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */ + sync + + bl invstr /* Find our address */ +invstr: mflr r5 /* Make it accessible */ + tlbsx r23,0,r5 /* Find entry we are in */ + li r4,0 /* Start at TLB entry 0 */ + li r3,0 /* Set PAGEID inval value */ +1: cmpw r23,r4 /* Is this our entry? */ + beq skpinv /* If so, skip the inval */ + tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */ +skpinv: addi r4,r4,1 /* Increment */ + cmpwi r4,64 /* Are we done? */ + bne 1b /* If not, repeat */ + isync /* If so, context change */ + +/* + * Configure and load pinned entry into TLB slot 63. + */ + + lis r3,KERNELBASE@h /* Load the kernel virtual address */ + ori r3,r3,KERNELBASE@l + + /* Kernel is at the base of RAM */ + li r4, 0 /* Load the kernel physical address */ + + /* Load the kernel PID = 0 */ + li r0,0 + mtspr SPRN_PID,r0 + sync + + /* Initialize MMUCR */ + li r5,0 + mtspr SPRN_MMUCR,r5 + sync + + /* pageid fields */ + clrrwi r3,r3,10 /* Mask off the effective page number */ + ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M + + /* xlat fields */ + clrrwi r4,r4,10 /* Mask off the real page number */ + /* ERPN is 0 for first 4GB page */ + + /* attrib fields */ + /* Added guarded bit to protect against speculative loads/stores */ + li r5,0 + ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G) + + li r0,63 /* TLB slot 63 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + + /* Force context change */ + mfmsr r0 + mtspr SPRN_SRR1, r0 + lis r0,3f@h + ori r0,r0,3f@l + mtspr SPRN_SRR0,r0 + sync + rfi + + /* If necessary, invalidate original entry we used */ +3: cmpwi r23,63 + beq 4f + li r6,0 + tlbwe r6,r23,PPC44x_TLB_PAGEID + isync + +4: +#ifdef CONFIG_SERIAL_TEXT_DEBUG + /* + * Add temporary UART mapping for early debug. + * We can map UART registers wherever we want as long as they don't + * interfere with other system mappings (e.g. with pinned entries). + * For an example of how we handle this - see ocotea.h. --ebs + */ + /* pageid fields */ + lis r3,UART0_IO_BASE@h + ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_4K + + /* xlat fields */ + lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ +#ifndef CONFIG_440EP + ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#endif + + /* attrib fields */ + li r5,0 + ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_I | PPC44x_TLB_G) + + li r0,0 /* TLB slot 0 */ + + tlbwe r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */ + tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */ + tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */ + + /* Force context change */ + isync +#endif /* CONFIG_SERIAL_TEXT_DEBUG */ + + /* Establish the interrupt vector offsets */ + SET_IVOR(0, CriticalInput); + SET_IVOR(1, MachineCheck); + SET_IVOR(2, DataStorage); + SET_IVOR(3, InstructionStorage); + SET_IVOR(4, ExternalInput); + SET_IVOR(5, Alignment); + SET_IVOR(6, Program); + SET_IVOR(7, FloatingPointUnavailable); + SET_IVOR(8, SystemCall); + SET_IVOR(9, AuxillaryProcessorUnavailable); + SET_IVOR(10, Decrementer); + SET_IVOR(11, FixedIntervalTimer); + SET_IVOR(12, WatchdogTimer); + SET_IVOR(13, DataTLBError); + SET_IVOR(14, InstructionTLBError); + SET_IVOR(15, Debug); + + /* Establish the interrupt vector base */ + lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ + mtspr SPRN_IVPR,r4 + +#ifdef CONFIG_440EP + /* Clear DAPUIB flag in CCR0 (enable APU between CPU and FPU) */ + mfspr r2,SPRN_CCR0 + lis r3,0xffef + ori r3,r3,0xffff + and r2,r2,r3 + mtspr SPRN_CCR0,r2 + isync +#endif + + /* + * This is where the main kernel code starts. + */ + + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + + /* ptr to current thread */ + addi r4,r2,THREAD /* init task's THREAD */ + mtspr SPRN_SPRG3,r4 + + /* stack */ + lis r1,init_thread_union@h + ori r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) + + bl early_init + +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + + /* Setup PTE pointers for the Abatron bdiGDB */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + lis r4, KERNELBASE@h + ori r4, r4, KERNELBASE@l + stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ + stw r6, 0(r5) + + /* Let's move on */ + lis r4,start_kernel@h + ori r4,r4,start_kernel@l + lis r3,MSR_KERNEL@h + ori r3,r3,MSR_KERNEL@l + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi /* change context and jump to start_kernel */ + +/* + * Interrupt vector entry code + * + * The Book E MMUs are always on so we don't need to handle + * interrupts in real mode as with previous PPC processors. In + * this case we handle interrupts in the kernel virtual address + * space. + * + * Interrupt vectors are dynamically placed relative to the + * interrupt prefix as determined by the address of interrupt_base. + * The interrupt vectors offsets are programmed using the labels + * for each interrupt vector entry. + * + * Interrupt vectors must be aligned on a 16 byte boundary. + * We align on a 32 byte cache line boundary for good measure. + */ + +interrupt_base: + /* Critical Input Interrupt */ + CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) + + /* Machine Check Interrupt */ +#ifdef CONFIG_440A + MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) +#else + CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) +#endif + + /* Data Storage Interrupt */ + START_EXCEPTION(DataStorage) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + + /* + * Check if it was a store fault, if not then bail + * because a user tried to access a kernel or + * read-protected page. Otherwise, get the + * offending address and handle it. + */ + mfspr r10, SPRN_ESR + andis. r10, r10, ESR_ST@h + beq 2f + + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + + mfspr r12,SPRN_MMUCR + rlwinm r12,r12,0,0,23 /* Clear TID */ + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) + + /* Load PID into MMUCR TID */ + mfspr r12,SPRN_MMUCR /* Get MMUCR */ + mfspr r13,SPRN_PID /* Get PID */ + rlwimi r12,r13,0,24,31 /* Set TID */ + +4: + mtspr SPRN_MMUCR,r12 + + rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r11, r12, r11 /* Get pgd/pmd entry */ + rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ + lwz r11, 4(r12) /* Get pte entry */ + + andi. r13, r11, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail if not */ + + /* Update 'changed'. + */ + ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + stw r11, 4(r12) /* Update Linux page table */ + + li r13, PPC44x_TLB_SR@l /* Set SR */ + rlwimi r13, r11, 29, 29, 29 /* SX = _PAGE_HWEXEC */ + rlwimi r13, r11, 0, 30, 30 /* SW = _PAGE_RW */ + rlwimi r13, r11, 29, 28, 28 /* UR = _PAGE_USER */ + rlwimi r12, r11, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ + rlwimi r12, r11, 29, 30, 30 /* (_PAGE_USER>>3)->r12 */ + and r12, r12, r11 /* HWEXEC/RW & USER */ + rlwimi r13, r12, 0, 26, 26 /* UX = HWEXEC & USER */ + rlwimi r13, r12, 3, 27, 27 /* UW = RW & USER */ + + rlwimi r11,r13,0,26,31 /* Insert static perms */ + + rlwinm r11,r11,0,20,15 /* Clear U0-U3 */ + + /* find the TLB index that caused the fault. It has to be here. */ + tlbsx r10, 0, r10 + + tlbwe r11, r10, PPC44x_TLB_ATTRIB /* Write ATTRIB */ + + /* Done...restore registers and get out of here. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + rfi /* Force context change */ + +2: + /* + * The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b data_access + + /* Instruction Storage Interrupt */ + INSTRUCTION_STORAGE_EXCEPTION + + /* External Input Interrupt */ + EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) + + /* Alignment Interrupt */ + ALIGNMENT_EXCEPTION + + /* Program Interrupt */ + PROGRAM_EXCEPTION + + /* Floating Point Unavailable Interrupt */ +#ifdef CONFIG_PPC_FPU + FP_UNAVAILABLE_EXCEPTION +#else + EXCEPTION(0x2010, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) +#endif + + /* System Call Interrupt */ + START_EXCEPTION(SystemCall) + NORMAL_EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0x0c00, DoSyscall) + + /* Auxillary Processor Unavailable Interrupt */ + EXCEPTION(0x2020, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE) + + /* Decrementer Interrupt */ + DECREMENTER_EXCEPTION + + /* Fixed Internal Timer Interrupt */ + /* TODO: Add FIT support */ + EXCEPTION(0x1010, FixedIntervalTimer, UnknownException, EXC_XFER_EE) + + /* Watchdog Timer Interrupt */ + /* TODO: Add watchdog support */ +#ifdef CONFIG_BOOKE_WDT + CRITICAL_EXCEPTION(0x1020, WatchdogTimer, WatchdogException) +#else + CRITICAL_EXCEPTION(0x1020, WatchdogTimer, UnknownException) +#endif + + /* Data TLB Error Interrupt */ + START_EXCEPTION(DataTLBError) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + + mfspr r12,SPRN_MMUCR + rlwinm r12,r12,0,0,23 /* Clear TID */ + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) + + /* Load PID into MMUCR TID */ + mfspr r12,SPRN_MMUCR + mfspr r13,SPRN_PID /* Get PID */ + rlwimi r12,r13,0,24,31 /* Set TID */ + +4: + mtspr SPRN_MMUCR,r12 + + rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r11, r12, r11 /* Get pgd/pmd entry */ + rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ + lwz r11, 4(r12) /* Get pte entry */ + andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + + ori r11, r11, _PAGE_ACCESSED + stw r11, 4(r12) + + /* Jump to common tlb load */ + b finish_tlb_load + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b data_access + + /* Instruction TLB Error Interrupt */ + /* + * Nearly the same as above, except we get our + * information from different registers and bailout + * to a different point. + */ + START_EXCEPTION(InstructionTLBError) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + mfspr r10, SPRN_SRR0 /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + + mfspr r12,SPRN_MMUCR + rlwinm r12,r12,0,0,23 /* Clear TID */ + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) + + /* Load PID into MMUCR TID */ + mfspr r12,SPRN_MMUCR + mfspr r13,SPRN_PID /* Get PID */ + rlwimi r12,r13,0,24,31 /* Set TID */ + +4: + mtspr SPRN_MMUCR,r12 + + rlwinm r12, r10, 13, 19, 29 /* Compute pgdir/pmd offset */ + lwzx r11, r12, r11 /* Get pgd/pmd entry */ + rlwinm. r12, r11, 0, 0, 20 /* Extract pt base address */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 23, 20, 28 /* Compute pte address */ + lwz r11, 4(r12) /* Get pte entry */ + andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + + ori r11, r11, _PAGE_ACCESSED + stw r11, 4(r12) + + /* Jump to common TLB load point */ + b finish_tlb_load + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b InstructionStorage + + /* Debug Interrupt */ + DEBUG_EXCEPTION + +/* + * Local functions + */ + /* + * Data TLB exceptions will bail out to this point + * if they can't resolve the lightweight TLB fault. + */ +data_access: + NORMAL_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ + stw r5,_ESR(r11) + mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ + EXC_XFER_EE_LITE(0x0300, handle_page_fault) + +/* + + * Both the instruction and data TLB miss get to this + * point to load the TLB. + * r10 - EA of fault + * r11 - available to use + * r12 - Pointer to the 64-bit PTE + * r13 - available to use + * MMUCR - loaded with proper value when we get here + * Upon exit, we reload everything and RFI. + */ +finish_tlb_load: + /* + * We set execute, because we don't have the granularity to + * properly set this at the page level (Linux problem). + * If shared is set, we cause a zero PID->TID load. + * Many of these bits are software only. Bits we don't set + * here we (properly should) assume have the appropriate value. + */ + + /* Load the next available TLB index */ + lis r13, tlb_44x_index@ha + lwz r13, tlb_44x_index@l(r13) + /* Load the TLB high watermark */ + lis r11, tlb_44x_hwater@ha + lwz r11, tlb_44x_hwater@l(r11) + + /* Increment, rollover, and store TLB index */ + addi r13, r13, 1 + cmpw 0, r13, r11 /* reserve entries */ + ble 7f + li r13, 0 +7: + /* Store the next available TLB index */ + lis r11, tlb_44x_index@ha + stw r13, tlb_44x_index@l(r11) + + lwz r11, 0(r12) /* Get MS word of PTE */ + lwz r12, 4(r12) /* Get LS word of PTE */ + rlwimi r11, r12, 0, 0 , 19 /* Insert RPN */ + tlbwe r11, r13, PPC44x_TLB_XLAT /* Write XLAT */ + + /* + * Create PAGEID. This is the faulting address, + * page size, and valid flag. + */ + li r11, PPC44x_TLB_VALID | PPC44x_TLB_4K + rlwimi r10, r11, 0, 20, 31 /* Insert valid and page size */ + tlbwe r10, r13, PPC44x_TLB_PAGEID /* Write PAGEID */ + + li r10, PPC44x_TLB_SR@l /* Set SR */ + rlwimi r10, r12, 0, 30, 30 /* Set SW = _PAGE_RW */ + rlwimi r10, r12, 29, 29, 29 /* SX = _PAGE_HWEXEC */ + rlwimi r10, r12, 29, 28, 28 /* UR = _PAGE_USER */ + rlwimi r11, r12, 31, 26, 26 /* (_PAGE_USER>>1)->r12 */ + and r11, r12, r11 /* HWEXEC & USER */ + rlwimi r10, r11, 0, 26, 26 /* UX = HWEXEC & USER */ + + rlwimi r12, r10, 0, 26, 31 /* Insert static perms */ + rlwinm r12, r12, 0, 20, 15 /* Clear U0-U3 */ + tlbwe r12, r13, PPC44x_TLB_ATTRIB /* Write ATTRIB */ + + /* Done...restore registers and get out of here. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + rfi /* Force context change */ + +/* + * Global functions + */ + +/* + * extern void giveup_altivec(struct task_struct *prev) + * + * The 44x core does not have an AltiVec unit. + */ +_GLOBAL(giveup_altivec) + blr + +/* + * extern void giveup_fpu(struct task_struct *prev) + * + * The 44x core does not have an FPU. + */ +#ifndef CONFIG_PPC_FPU +_GLOBAL(giveup_fpu) + blr +#endif + +/* + * extern void abort(void) + * + * At present, this routine just applies a system reset. + */ +_GLOBAL(abort) + mfspr r13,SPRN_DBCR0 + oris r13,r13,DBCR0_RST_SYSTEM@h + mtspr SPRN_DBCR0,r13 + +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is the second parameter. + */ + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r4, 0x4(r5) +#endif + mtspr SPRN_PID,r3 + isync /* Force context change */ + blr + +/* + * We put a few things here that have to be page-aligned. This stuff + * goes at the beginning of the data segment, which is page-aligned. + */ + .data +_GLOBAL(sdata) +_GLOBAL(empty_zero_page) + .space 4096 + +/* + * To support >32-bit physical addresses, we use an 8KB pgdir. + */ +_GLOBAL(swapper_pg_dir) + .space 8192 + +/* Reserved 4k for the critical exception stack & 4k for the machine + * check stack per CPU for kernel mode exceptions */ + .section .bss + .align 12 +exception_stack_bottom: + .space BOOKE_EXCEPTION_STACK_SIZE +_GLOBAL(exception_stack_top) + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * which is used to pass parameters into the kernel like root=/dev/sda1, etc. + */ +_GLOBAL(cmd_line) + .space 512 + +/* + * Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 + + diff --git a/arch/powerpc/kernel/head_4xx.S b/arch/powerpc/kernel/head_4xx.S new file mode 100644 index 00000000000..8562b807b37 --- /dev/null +++ b/arch/powerpc/kernel/head_4xx.S @@ -0,0 +1,1016 @@ +/* + * Copyright (c) 1995-1996 Gary Thomas + * Initial PowerPC version. + * Copyright (c) 1996 Cort Dougan + * Rewritten for PReP + * Copyright (c) 1996 Paul Mackerras + * Low-level exception handers, MMU support, and rewrite. + * Copyright (c) 1997 Dan Malek + * PowerPC 8xx modifications. + * Copyright (c) 1998-1999 TiVo, Inc. + * PowerPC 403GCX modifications. + * Copyright (c) 1999 Grant Erickson + * PowerPC 403GCX/405GP modifications. + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * PowerPC 403GCX/405GP modifications. + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or source@mvista.com + * debbie_chu@mvista.com + * + * + * Module name: head_4xx.S + * + * Description: + * Kernel execution entry point code. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* As with the other PowerPC ports, it is expected that when code + * execution begins here, the following registers contain valid, yet + * optional, information: + * + * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) + * r4 - Starting address of the init RAM disk + * r5 - Ending address of the init RAM disk + * r6 - Start of kernel command line string (e.g. "mem=96m") + * r7 - End of kernel command line string + * + * This is all going to change RSN when we add bi_recs....... -- Dan + */ + .text +_GLOBAL(_stext) +_GLOBAL(_start) + + /* Save parameters we are passed. + */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + + /* We have to turn on the MMU right away so we get cache modes + * set correctly. + */ + bl initial_mmu + +/* We now have the lower 16 Meg mapped into TLB entries, and the caches + * ready to work. + */ +turn_on_mmu: + lis r0,MSR_KERNEL@h + ori r0,r0,MSR_KERNEL@l + mtspr SPRN_SRR1,r0 + lis r0,start_here@h + ori r0,r0,start_here@l + mtspr SPRN_SRR0,r0 + SYNC + rfi /* enables MMU */ + b . /* prevent prefetch past rfi */ + +/* + * This area is used for temporarily saving registers during the + * critical exception prolog. + */ + . = 0xc0 +crit_save: +_GLOBAL(crit_r10) + .space 4 +_GLOBAL(crit_r11) + .space 4 + +/* + * Exception vector entry code. This code runs with address translation + * turned off (i.e. using physical addresses). We assume SPRG3 has the + * physical address of the current task thread_struct. + * Note that we have to have decremented r1 before we write to any fields + * of the exception frame, since a critical interrupt could occur at any + * time, and it will write to the area immediately below the current r1. + */ +#define NORMAL_EXCEPTION_PROLOG \ + mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ + mtspr SPRN_SPRG1,r11; \ + mtspr SPRN_SPRG2,r1; \ + mfcr r10; /* save CR in r10 for now */\ + mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ + andi. r11,r11,MSR_PR; \ + beq 1f; \ + mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ + lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ + addi r1,r1,THREAD_SIZE; \ +1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ + tophys(r11,r1); \ + stw r10,_CCR(r11); /* save various registers */\ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mfspr r10,SPRN_SPRG0; \ + stw r10,GPR10(r11); \ + mfspr r12,SPRN_SPRG1; \ + stw r12,GPR11(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r10,SPRN_SPRG2; \ + mfspr r12,SPRN_SRR0; \ + stw r10,GPR1(r11); \ + mfspr r9,SPRN_SRR1; \ + stw r10,0(r11); \ + rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + +/* + * Exception prolog for critical exceptions. This is a little different + * from the normal exception prolog above since a critical exception + * can potentially occur at any point during normal exception processing. + * Thus we cannot use the same SPRG registers as the normal prolog above. + * Instead we use a couple of words of memory at low physical addresses. + * This is OK since we don't support SMP on these processors. + */ +#define CRITICAL_EXCEPTION_PROLOG \ + stw r10,crit_r10@l(0); /* save two registers to work with */\ + stw r11,crit_r11@l(0); \ + mfcr r10; /* save CR in r10 for now */\ + mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ + andi. r11,r11,MSR_PR; \ + lis r11,critical_stack_top@h; \ + ori r11,r11,critical_stack_top@l; \ + beq 1f; \ + /* COMING FROM USER MODE */ \ + mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ + lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ + addi r11,r11,THREAD_SIZE; \ +1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ + tophys(r11,r11); \ + stw r10,_CCR(r11); /* save various registers */\ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ + stw r12,_DEAR(r11); /* since they may have had stuff */\ + mfspr r9,SPRN_ESR; /* in them at the point where the */\ + stw r9,_ESR(r11); /* exception was taken */\ + mfspr r12,SPRN_SRR2; \ + stw r1,GPR1(r11); \ + mfspr r9,SPRN_SRR3; \ + stw r1,0(r11); \ + tovirt(r1,r11); \ + rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + + /* + * State at this point: + * r9 saved in stack frame, now saved SRR3 & ~MSR_WE + * r10 saved in crit_r10 and in stack frame, trashed + * r11 saved in crit_r11 and in stack frame, + * now phys stack/exception frame pointer + * r12 saved in stack frame, now saved SRR2 + * CR saved in stack frame, CR0.EQ = !SRR3.PR + * LR, DEAR, ESR in stack frame + * r1 saved in stack frame, now virt stack/excframe pointer + * r0, r3-r8 saved in stack frame + */ + +/* + * Exception vectors. + */ +#define START_EXCEPTION(n, label) \ + . = n; \ +label: + +#define EXCEPTION(n, label, hdlr, xfer) \ + START_EXCEPTION(n, label); \ + NORMAL_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + xfer(n, hdlr) + +#define CRITICAL_EXCEPTION(n, label, hdlr) \ + START_EXCEPTION(n, label); \ + CRITICAL_EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ + NOCOPY, crit_transfer_to_handler, \ + ret_from_crit_exc) + +#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ + li r10,trap; \ + stw r10,TRAP(r11); \ + lis r10,msr@h; \ + ori r10,r10,msr@l; \ + copyee(r10, r9); \ + bl tfer; \ + .long hdlr; \ + .long ret + +#define COPY_EE(d, s) rlwimi d,s,0,16,16 +#define NOCOPY(d, s) + +#define EXC_XFER_STD(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ + ret_from_except) + +#define EXC_XFER_EE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_EE_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ + ret_from_except) + + +/* + * 0x0100 - Critical Interrupt Exception + */ + CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, UnknownException) + +/* + * 0x0200 - Machine Check Exception + */ + CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) + +/* + * 0x0300 - Data Storage Exception + * This happens for just a few reasons. U0 set (but we don't do that), + * or zone protection fault (user violation, write to protected page). + * If this is just an update of modified status, we do that quickly + * and exit. Otherwise, we call heavywight functions to do the work. + */ + START_EXCEPTION(0x0300, DataStorage) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + + /* First, check if it was a zone fault (which means a user + * tried to access a kernel or read-protected page - always + * a SEGV). All other faults here must be stores, so no + * need to check ESR_DST as well. */ + mfspr r10, SPRN_ESR + andis. r10, r10, ESR_DIZ@h + bne 2f + + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r11, 0(r11) /* Get L1 entry */ + rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + + andi. r9, r11, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail if not */ + + /* Update 'changed'. + */ + ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + stw r11, 0(r12) /* Update Linux page table */ + + /* Most of the Linux PTE is ready to load into the TLB LO. + * We set ZSEL, where only the LS-bit determines user access. + * We set execute, because we don't have the granularity to + * properly set this at the page level (Linux problem). + * If shared is set, we cause a zero PID->TID load. + * Many of these bits are software only. Bits we don't set + * here we (properly should) assume have the appropriate value. + */ + li r12, 0x0ce2 + andc r11, r11, r12 /* Make sure 20, 21 are zero */ + + /* find the TLB index that caused the fault. It has to be here. + */ + tlbsx r9, 0, r10 + + tlbwe r11, r9, TLB_DATA /* Load TLB LO */ + + /* Done...restore registers and get out of here. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + PPC405_ERR77_SYNC + rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b DataAccess + +/* + * 0x0400 - Instruction Storage Exception + * This is caused by a fetch from non-execute or guarded pages. + */ + START_EXCEPTION(0x0400, InstructionAccess) + NORMAL_EXCEPTION_PROLOG + mr r4,r12 /* Pass SRR0 as arg2 */ + li r5,0 /* Pass zero as arg3 */ + EXC_XFER_EE_LITE(0x400, handle_page_fault) + +/* 0x0500 - External Interrupt Exception */ + EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) + +/* 0x0600 - Alignment Exception */ + START_EXCEPTION(0x0600, Alignment) + NORMAL_EXCEPTION_PROLOG + mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ + stw r4,_DEAR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE(0x600, AlignmentException) + +/* 0x0700 - Program Exception */ + START_EXCEPTION(0x0700, ProgramCheck) + NORMAL_EXCEPTION_PROLOG + mfspr r4,SPRN_ESR /* Grab the ESR and save it */ + stw r4,_ESR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_STD(0x700, ProgramCheckException) + + EXCEPTION(0x0800, Trap_08, UnknownException, EXC_XFER_EE) + EXCEPTION(0x0900, Trap_09, UnknownException, EXC_XFER_EE) + EXCEPTION(0x0A00, Trap_0A, UnknownException, EXC_XFER_EE) + EXCEPTION(0x0B00, Trap_0B, UnknownException, EXC_XFER_EE) + +/* 0x0C00 - System Call Exception */ + START_EXCEPTION(0x0C00, SystemCall) + NORMAL_EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0xc00, DoSyscall) + + EXCEPTION(0x0D00, Trap_0D, UnknownException, EXC_XFER_EE) + EXCEPTION(0x0E00, Trap_0E, UnknownException, EXC_XFER_EE) + EXCEPTION(0x0F00, Trap_0F, UnknownException, EXC_XFER_EE) + +/* 0x1000 - Programmable Interval Timer (PIT) Exception */ + START_EXCEPTION(0x1000, Decrementer) + NORMAL_EXCEPTION_PROLOG + lis r0,TSR_PIS@h + mtspr SPRN_TSR,r0 /* Clear the PIT exception */ + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_LITE(0x1000, timer_interrupt) + +#if 0 +/* NOTE: + * FIT and WDT handlers are not implemented yet. + */ + +/* 0x1010 - Fixed Interval Timer (FIT) Exception +*/ + STND_EXCEPTION(0x1010, FITException, UnknownException) + +/* 0x1020 - Watchdog Timer (WDT) Exception +*/ +#ifdef CONFIG_BOOKE_WDT + CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException) +#else + CRITICAL_EXCEPTION(0x1020, WDTException, UnknownException) +#endif +#endif + +/* 0x1100 - Data TLB Miss Exception + * As the name implies, translation is not in the MMU, so search the + * page tables and fix it. The only purpose of this function is to + * load TLB entries from the page table if they exist. + */ + START_EXCEPTION(0x1100, DTLBMiss) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r12, 0(r11) /* Get L1 entry */ + andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + andi. r9, r11, _PAGE_PRESENT + beq 5f + + ori r11, r11, _PAGE_ACCESSED + stw r11, 0(r12) + + /* Create TLB tag. This is the faulting address plus a static + * set of bits. These are size, valid, E, U0. + */ + li r12, 0x00c0 + rlwimi r10, r12, 0, 20, 31 + + b finish_tlb_load + +2: /* Check for possible large-page pmd entry */ + rlwinm. r9, r12, 2, 22, 24 + beq 5f + + /* Create TLB tag. This is the faulting address, plus a static + * set of bits (valid, E, U0) plus the size from the PMD. + */ + ori r9, r9, 0x40 + rlwimi r10, r9, 0, 20, 31 + mr r11, r12 + + b finish_tlb_load + +5: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b DataAccess + +/* 0x1200 - Instruction TLB Miss Exception + * Nearly the same as above, except we get our information from different + * registers and bailout to a different point. + */ + START_EXCEPTION(0x1200, ITLBMiss) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 +#ifdef CONFIG_403GCX + stw r12, 0(r0) + stw r9, 4(r0) + mfcr r11 + mfspr r12, SPRN_PID + stw r11, 8(r0) + stw r12, 12(r0) +#else + mtspr SPRN_SPRG4, r12 + mtspr SPRN_SPRG5, r9 + mfcr r11 + mfspr r12, SPRN_PID + mtspr SPRN_SPRG7, r11 + mtspr SPRN_SPRG6, r12 +#endif + mfspr r10, SPRN_SRR0 /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + cmplw r10, r11 + blt+ 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + li r9, 0 + mtspr SPRN_PID, r9 /* TLB will have 0 TID */ + b 4f + + /* Get the PGD for the current thread. + */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + tophys(r11, r11) + rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ + lwz r12, 0(r11) /* Get L1 entry */ + andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ + beq 2f /* Bail if no table */ + + rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ + lwz r11, 0(r12) /* Get Linux PTE */ + andi. r9, r11, _PAGE_PRESENT + beq 5f + + ori r11, r11, _PAGE_ACCESSED + stw r11, 0(r12) + + /* Create TLB tag. This is the faulting address plus a static + * set of bits. These are size, valid, E, U0. + */ + li r12, 0x00c0 + rlwimi r10, r12, 0, 20, 31 + + b finish_tlb_load + +2: /* Check for possible large-page pmd entry */ + rlwinm. r9, r12, 2, 22, 24 + beq 5f + + /* Create TLB tag. This is the faulting address, plus a static + * set of bits (valid, E, U0) plus the size from the PMD. + */ + ori r9, r9, 0x40 + rlwimi r10, r9, 0, 20, 31 + mr r11, r12 + + b finish_tlb_load + +5: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b InstructionAccess + + EXCEPTION(0x1300, Trap_13, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1400, Trap_14, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE) +#ifdef CONFIG_IBM405_ERR51 + /* 405GP errata 51 */ + START_EXCEPTION(0x1700, Trap_17) + b DTLBMiss +#else + EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE) +#endif + EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1A00, Trap_1A, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1B00, Trap_1B, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1C00, Trap_1C, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1D00, Trap_1D, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1E00, Trap_1E, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1F00, Trap_1F, UnknownException, EXC_XFER_EE) + +/* Check for a single step debug exception while in an exception + * handler before state has been saved. This is to catch the case + * where an instruction that we are trying to single step causes + * an exception (eg ITLB/DTLB miss) and thus the first instruction of + * the exception handler generates a single step debug exception. + * + * If we get a debug trap on the first instruction of an exception handler, + * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is + * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). + * The exception handler was handling a non-critical interrupt, so it will + * save (and later restore) the MSR via SPRN_SRR1, which will still have + * the MSR_DE bit set. + */ + /* 0x2000 - Debug Exception */ + START_EXCEPTION(0x2000, DebugTrap) + CRITICAL_EXCEPTION_PROLOG + + /* + * If this is a single step or branch-taken exception in an + * exception entry sequence, it was probably meant to apply to + * the code where the exception occurred (since exception entry + * doesn't turn off DE automatically). We simulate the effect + * of turning off DE on entry to an exception handler by turning + * off DE in the SRR3 value and clearing the debug status. + */ + mfspr r10,SPRN_DBSR /* check single-step/branch taken */ + andis. r10,r10,DBSR_IC@h + beq+ 2f + + andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ + beq 1f /* branch and fix it up */ + + mfspr r10,SPRN_SRR2 /* Faulting instruction address */ + cmplwi r10,0x2100 + bgt+ 2f /* address above exception vectors */ + + /* here it looks like we got an inappropriate debug exception. */ +1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ + lis r10,DBSR_IC@h /* clear the IC event */ + mtspr SPRN_DBSR,r10 + /* restore state and get out */ + lwz r10,_CCR(r11) + lwz r0,GPR0(r11) + lwz r1,GPR1(r11) + mtcrf 0x80,r10 + mtspr SPRN_SRR2,r12 + mtspr SPRN_SRR3,r9 + lwz r9,GPR9(r11) + lwz r12,GPR12(r11) + lwz r10,crit_r10@l(0) + lwz r11,crit_r11@l(0) + PPC405_ERR77_SYNC + rfci + b . + + /* continue normal handling for a critical exception... */ +2: mfspr r4,SPRN_DBSR + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_TEMPLATE(DebugException, 0x2002, \ + (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ + NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) + +/* + * The other Data TLB exceptions bail out to this point + * if they can't resolve the lightweight TLB fault. + */ +DataAccess: + NORMAL_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ + stw r5,_ESR(r11) + mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ + EXC_XFER_EE_LITE(0x300, handle_page_fault) + +/* Other PowerPC processors, namely those derived from the 6xx-series + * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. + * However, for the 4xx-series processors these are neither defined nor + * reserved. + */ + + /* Damn, I came up one instruction too many to fit into the + * exception space :-). Both the instruction and data TLB + * miss get to this point to load the TLB. + * r10 - TLB_TAG value + * r11 - Linux PTE + * r12, r9 - avilable to use + * PID - loaded with proper value when we get here + * Upon exit, we reload everything and RFI. + * Actually, it will fit now, but oh well.....a common place + * to load the TLB. + */ +tlb_4xx_index: + .long 0 +finish_tlb_load: + /* load the next available TLB index. + */ + lwz r9, tlb_4xx_index@l(0) + addi r9, r9, 1 + andi. r9, r9, (PPC4XX_TLB_SIZE-1) + stw r9, tlb_4xx_index@l(0) + +6: + /* + * Clear out the software-only bits in the PTE to generate the + * TLB_DATA value. These are the bottom 2 bits of the RPM, the + * top 3 bits of the zone field, and M. + */ + li r12, 0x0ce2 + andc r11, r11, r12 + + tlbwe r11, r9, TLB_DATA /* Load TLB LO */ + tlbwe r10, r9, TLB_TAG /* Load TLB HI */ + + /* Done...restore registers and get out of here. + */ +#ifdef CONFIG_403GCX + lwz r12, 12(r0) + lwz r11, 8(r0) + mtspr SPRN_PID, r12 + mtcr r11 + lwz r9, 4(r0) + lwz r12, 0(r0) +#else + mfspr r12, SPRN_SPRG6 + mfspr r11, SPRN_SPRG7 + mtspr SPRN_PID, r12 + mtcr r11 + mfspr r9, SPRN_SPRG5 + mfspr r12, SPRN_SPRG4 +#endif + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + PPC405_ERR77_SYNC + rfi /* Should sync shadow TLBs */ + b . /* prevent prefetch past rfi */ + +/* extern void giveup_fpu(struct task_struct *prev) + * + * The PowerPC 4xx family of processors do not have an FPU, so this just + * returns. + */ +_GLOBAL(giveup_fpu) + blr + +/* This is where the main kernel code starts. + */ +start_here: + + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + + /* ptr to phys current thread */ + tophys(r4,r2) + addi r4,r4,THREAD /* init task's THREAD */ + mtspr SPRN_SPRG3,r4 + + /* stack */ + lis r1,init_thread_union@ha + addi r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) + + bl early_init /* We have to do this with MMU on */ + +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + +/* Go back to running unmapped so we can load up new values + * and change to using our exception vectors. + * On the 4xx, all we have to do is invalidate the TLB to clear + * the old 16M byte TLB mappings. + */ + lis r4,2f@h + ori r4,r4,2f@l + tophys(r4,r4) + lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h + ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi + b . /* prevent prefetch past rfi */ + +/* Load up the kernel context */ +2: + sync /* Flush to memory before changing TLB */ + tlbia + isync /* Flush shadow TLBs */ + + /* set up the PTE pointers for the Abatron bdiGDB. + */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r5, 0xf0(r0) /* Must match your Abatron config file */ + tophys(r5,r5) + stw r6, 0(r5) + +/* Now turn on the MMU for real! */ + lis r4,MSR_KERNEL@h + ori r4,r4,MSR_KERNEL@l + lis r3,start_kernel@h + ori r3,r3,start_kernel@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + rfi /* enable MMU and jump to start_kernel */ + b . /* prevent prefetch past rfi */ + +/* Set up the initial MMU state so we can do the first level of + * kernel initialization. This maps the first 16 MBytes of memory 1:1 + * virtual to physical and more importantly sets the cache mode. + */ +initial_mmu: + tlbia /* Invalidate all TLB entries */ + isync + + /* We should still be executing code at physical address 0x0000xxxx + * at this point. However, start_here is at virtual address + * 0xC000xxxx. So, set up a TLB mapping to cover this once + * translation is enabled. + */ + + lis r3,KERNELBASE@h /* Load the kernel virtual address */ + ori r3,r3,KERNELBASE@l + tophys(r4,r3) /* Load the kernel physical address */ + + iccci r0,r3 /* Invalidate the i-cache before use */ + + /* Load the kernel PID. + */ + li r0,0 + mtspr SPRN_PID,r0 + sync + + /* Configure and load two entries into TLB slots 62 and 63. + * In case we are pinning TLBs, these are reserved in by the + * other TLB functions. If not reserving, then it doesn't + * matter where they are loaded. + */ + clrrwi r4,r4,10 /* Mask off the real page number */ + ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ + + clrrwi r3,r3,10 /* Mask off the effective page number */ + ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) + + li r0,63 /* TLB slot 63 */ + + tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ + tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ + +#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE) + + /* Load a TLB entry for the UART, so that ppc4xx_progress() can use + * the UARTs nice and early. We use a 4k real==virtual mapping. */ + + lis r3,SERIAL_DEBUG_IO_BASE@h + ori r3,r3,SERIAL_DEBUG_IO_BASE@l + mr r4,r3 + clrrwi r4,r4,12 + ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) + + clrrwi r3,r3,12 + ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) + + li r0,0 /* TLB slot 0 */ + tlbwe r4,r0,TLB_DATA + tlbwe r3,r0,TLB_TAG +#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */ + + isync + + /* Establish the exception vector base + */ + lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ + tophys(r0,r4) /* Use the physical address */ + mtspr SPRN_EVPR,r0 + + blr + +_GLOBAL(abort) + mfspr r13,SPRN_DBCR0 + oris r13,r13,DBCR0_RST_SYSTEM@h + mtspr SPRN_DBCR0,r13 + +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is the second parameter. + */ + lis r5, KERNELBASE@h + lwz r5, 0xf0(r5) + stw r4, 0x4(r5) +#endif + sync + mtspr SPRN_PID,r3 + isync /* Need an isync to flush shadow */ + /* TLBs after changing PID */ + blr + +/* We put a few things here that have to be page-aligned. This stuff + * goes at the beginning of the data segment, which is page-aligned. + */ + .data +_GLOBAL(sdata) +_GLOBAL(empty_zero_page) + .space 4096 +_GLOBAL(swapper_pg_dir) + .space 4096 + + +/* Stack for handling critical exceptions from kernel mode */ + .section .bss + .align 12 +exception_stack_bottom: + .space 4096 +critical_stack_top: +_GLOBAL(exception_stack_top) + +/* This space gets a copy of optional info passed to us by the bootstrap + * which is used to pass parameters into the kernel like root=/dev/sda1, etc. + */ +_GLOBAL(cmd_line) + .space 512 + +/* Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S new file mode 100644 index 00000000000..22a5ee07e1e --- /dev/null +++ b/arch/powerpc/kernel/head_64.S @@ -0,0 +1,2011 @@ +/* + * arch/ppc64/kernel/head.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and + * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com + * + * This file contains the low-level support and setup for the + * PowerPC-64 platform, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PPC_ISERIES +#define DO_SOFT_DISABLE +#endif + +/* + * We layout physical memory as follows: + * 0x0000 - 0x00ff : Secondary processor spin code + * 0x0100 - 0x2fff : pSeries Interrupt prologs + * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs + * 0x6000 - 0x6fff : Initial (CPU0) segment table + * 0x7000 - 0x7fff : FWNMI data area + * 0x8000 - : Early init and support code + */ + +/* + * SPRG Usage + * + * Register Definition + * + * SPRG0 reserved for hypervisor + * SPRG1 temp - used to save gpr + * SPRG2 temp - used to save gpr + * SPRG3 virt addr of paca + */ + +/* + * Entering into this code we make the following assumptions: + * For pSeries: + * 1. The MMU is off & open firmware is running in real mode. + * 2. The kernel is entered at __start + * + * For iSeries: + * 1. The MMU is on (as it always is for iSeries) + * 2. The kernel is entered at system_reset_iSeries + */ + + .text + .globl _stext +_stext: +#ifdef CONFIG_PPC_MULTIPLATFORM +_GLOBAL(__start) + /* NOP this out unconditionally */ +BEGIN_FTR_SECTION + b .__start_initialization_multiplatform +END_FTR_SECTION(0, 1) +#endif /* CONFIG_PPC_MULTIPLATFORM */ + + /* Catch branch to 0 in real mode */ + trap + +#ifdef CONFIG_PPC_ISERIES + /* + * At offset 0x20, there is a pointer to iSeries LPAR data. + * This is required by the hypervisor + */ + . = 0x20 + .llong hvReleaseData-KERNELBASE + + /* + * At offset 0x28 and 0x30 are offsets to the mschunks_map + * array (used by the iSeries LPAR debugger to do translation + * between physical addresses and absolute addresses) and + * to the pidhash table (also used by the debugger) + */ + .llong mschunks_map-KERNELBASE + .llong 0 /* pidhash-KERNELBASE SFRXXX */ + + /* Offset 0x38 - Pointer to start of embedded System.map */ + .globl embedded_sysmap_start +embedded_sysmap_start: + .llong 0 + /* Offset 0x40 - Pointer to end of embedded System.map */ + .globl embedded_sysmap_end +embedded_sysmap_end: + .llong 0 + +#endif /* CONFIG_PPC_ISERIES */ + + /* Secondary processors spin on this value until it goes to 1. */ + .globl __secondary_hold_spinloop +__secondary_hold_spinloop: + .llong 0x0 + + /* Secondary processors write this value with their cpu # */ + /* after they enter the spin loop immediately below. */ + .globl __secondary_hold_acknowledge +__secondary_hold_acknowledge: + .llong 0x0 + + . = 0x60 +/* + * The following code is used on pSeries to hold secondary processors + * in a spin loop after they have been freed from OpenFirmware, but + * before the bulk of the kernel has been relocated. This code + * is relocated to physical address 0x60 before prom_init is run. + * All of it must fit below the first exception vector at 0x100. + */ +_GLOBAL(__secondary_hold) + mfmsr r24 + ori r24,r24,MSR_RI + mtmsrd r24 /* RI on */ + + /* Grab our linux cpu number */ + mr r24,r3 + + /* Tell the master cpu we're here */ + /* Relocation is off & we are located at an address less */ + /* than 0x100, so only need to grab low order offset. */ + std r24,__secondary_hold_acknowledge@l(0) + sync + + /* All secondary cpus wait here until told to start. */ +100: ld r4,__secondary_hold_spinloop@l(0) + cmpdi 0,r4,1 + bne 100b + +#ifdef CONFIG_HMT + b .hmt_init +#else +#ifdef CONFIG_SMP + mr r3,r24 + b .pSeries_secondary_smp_init +#else + BUG_OPCODE +#endif +#endif + +/* This value is used to mark exception frames on the stack. */ + .section ".toc","aw" +exception_marker: + .tc ID_72656773_68657265[TC],0x7265677368657265 + .text + +/* + * The following macros define the code that appears as + * the prologue to each of the exception handlers. They + * are split into two parts to allow a single kernel binary + * to be used for pSeries and iSeries. + * LOL. One day... - paulus + */ + +/* + * We make as much of the exception code common between native + * exception handlers (including pSeries LPAR) and iSeries LPAR + * implementations as possible. + */ + +/* + * This is the start of the interrupt handlers for pSeries + * This code runs with relocation off. + */ +#define EX_R9 0 +#define EX_R10 8 +#define EX_R11 16 +#define EX_R12 24 +#define EX_R13 32 +#define EX_SRR0 40 +#define EX_R3 40 /* SLB miss saves R3, but not SRR0 */ +#define EX_DAR 48 +#define EX_LR 48 /* SLB miss saves LR, but not DAR */ +#define EX_DSISR 56 +#define EX_CCR 60 + +#define EXCEPTION_PROLOG_PSERIES(area, label) \ + mfspr r13,SPRG3; /* get paca address into r13 */ \ + std r9,area+EX_R9(r13); /* save r9 - r12 */ \ + std r10,area+EX_R10(r13); \ + std r11,area+EX_R11(r13); \ + std r12,area+EX_R12(r13); \ + mfspr r9,SPRG1; \ + std r9,area+EX_R13(r13); \ + mfcr r9; \ + clrrdi r12,r13,32; /* get high part of &label */ \ + mfmsr r10; \ + mfspr r11,SRR0; /* save SRR0 */ \ + ori r12,r12,(label)@l; /* virt addr of handler */ \ + ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ + mtspr SRR0,r12; \ + mfspr r12,SRR1; /* and SRR1 */ \ + mtspr SRR1,r10; \ + rfid; \ + b . /* prevent speculative execution */ + +/* + * This is the start of the interrupt handlers for iSeries + * This code runs with relocation on. + */ +#define EXCEPTION_PROLOG_ISERIES_1(area) \ + mfspr r13,SPRG3; /* get paca address into r13 */ \ + std r9,area+EX_R9(r13); /* save r9 - r12 */ \ + std r10,area+EX_R10(r13); \ + std r11,area+EX_R11(r13); \ + std r12,area+EX_R12(r13); \ + mfspr r9,SPRG1; \ + std r9,area+EX_R13(r13); \ + mfcr r9 + +#define EXCEPTION_PROLOG_ISERIES_2 \ + mfmsr r10; \ + ld r11,PACALPPACA+LPPACASRR0(r13); \ + ld r12,PACALPPACA+LPPACASRR1(r13); \ + ori r10,r10,MSR_RI; \ + mtmsrd r10,1 + +/* + * The common exception prolog is used for all except a few exceptions + * such as a segment miss on a kernel address. We have to be prepared + * to take another exception from the point where we first touch the + * kernel stack onwards. + * + * On entry r13 points to the paca, r9-r13 are saved in the paca, + * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and + * SRR1, and relocation is on. + */ +#define EXCEPTION_PROLOG_COMMON(n, area) \ + andi. r10,r12,MSR_PR; /* See if coming from user */ \ + mr r10,r1; /* Save r1 */ \ + subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ + beq- 1f; \ + ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ +1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ + bge- cr1,bad_stack; /* abort if it is */ \ + std r9,_CCR(r1); /* save CR in stackframe */ \ + std r11,_NIP(r1); /* save SRR0 in stackframe */ \ + std r12,_MSR(r1); /* save SRR1 in stackframe */ \ + std r10,0(r1); /* make stack chain pointer */ \ + std r0,GPR0(r1); /* save r0 in stackframe */ \ + std r10,GPR1(r1); /* save r1 in stackframe */ \ + std r2,GPR2(r1); /* save r2 in stackframe */ \ + SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ + SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ + ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ + ld r10,area+EX_R10(r13); \ + std r9,GPR9(r1); \ + std r10,GPR10(r1); \ + ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ + ld r10,area+EX_R12(r13); \ + ld r11,area+EX_R13(r13); \ + std r9,GPR11(r1); \ + std r10,GPR12(r1); \ + std r11,GPR13(r1); \ + ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ + mflr r9; /* save LR in stackframe */ \ + std r9,_LINK(r1); \ + mfctr r10; /* save CTR in stackframe */ \ + std r10,_CTR(r1); \ + mfspr r11,XER; /* save XER in stackframe */ \ + std r11,_XER(r1); \ + li r9,(n)+1; \ + std r9,_TRAP(r1); /* set trap number */ \ + li r10,0; \ + ld r11,exception_marker@toc(r2); \ + std r10,RESULT(r1); /* clear regs->result */ \ + std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ + +/* + * Exception vectors. + */ +#define STD_EXCEPTION_PSERIES(n, label) \ + . = n; \ + .globl label##_pSeries; \ +label##_pSeries: \ + HMT_MEDIUM; \ + mtspr SPRG1,r13; /* save r13 */ \ + RUNLATCH_ON(r13); \ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) + +#define STD_EXCEPTION_ISERIES(n, label, area) \ + .globl label##_iSeries; \ +label##_iSeries: \ + HMT_MEDIUM; \ + mtspr SPRG1,r13; /* save r13 */ \ + RUNLATCH_ON(r13); \ + EXCEPTION_PROLOG_ISERIES_1(area); \ + EXCEPTION_PROLOG_ISERIES_2; \ + b label##_common + +#define MASKABLE_EXCEPTION_ISERIES(n, label) \ + .globl label##_iSeries; \ +label##_iSeries: \ + HMT_MEDIUM; \ + mtspr SPRG1,r13; /* save r13 */ \ + RUNLATCH_ON(r13); \ + EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ + lbz r10,PACAPROCENABLED(r13); \ + cmpwi 0,r10,0; \ + beq- label##_iSeries_masked; \ + EXCEPTION_PROLOG_ISERIES_2; \ + b label##_common; \ + +#ifdef DO_SOFT_DISABLE +#define DISABLE_INTS \ + lbz r10,PACAPROCENABLED(r13); \ + li r11,0; \ + std r10,SOFTE(r1); \ + mfmsr r10; \ + stb r11,PACAPROCENABLED(r13); \ + ori r10,r10,MSR_EE; \ + mtmsrd r10,1 + +#define ENABLE_INTS \ + lbz r10,PACAPROCENABLED(r13); \ + mfmsr r11; \ + std r10,SOFTE(r1); \ + ori r11,r11,MSR_EE; \ + mtmsrd r11,1 + +#else /* hard enable/disable interrupts */ +#define DISABLE_INTS + +#define ENABLE_INTS \ + ld r12,_MSR(r1); \ + mfmsr r11; \ + rlwimi r11,r12,0,MSR_EE; \ + mtmsrd r11,1 + +#endif + +#define STD_EXCEPTION_COMMON(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + DISABLE_INTS; \ + bl .save_nvgprs; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except + +#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ + .align 7; \ + .globl label##_common; \ +label##_common: \ + EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ + DISABLE_INTS; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + bl hdlr; \ + b .ret_from_except_lite + +/* + * Start of pSeries system interrupt routines + */ + . = 0x100 + .globl __start_interrupts +__start_interrupts: + + STD_EXCEPTION_PSERIES(0x100, system_reset) + + . = 0x200 +_machine_check_pSeries: + HMT_MEDIUM + mtspr SPRG1,r13 /* save r13 */ + RUNLATCH_ON(r13) + EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) + + . = 0x300 + .globl data_access_pSeries +data_access_pSeries: + HMT_MEDIUM + mtspr SPRG1,r13 +BEGIN_FTR_SECTION + mtspr SPRG2,r12 + mfspr r13,DAR + mfspr r12,DSISR + srdi r13,r13,60 + rlwimi r13,r12,16,0x20 + mfcr r12 + cmpwi r13,0x2c + beq .do_stab_bolted_pSeries + mtcrf 0x80,r12 + mfspr r12,SPRG2 +END_FTR_SECTION_IFCLR(CPU_FTR_SLB) + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) + + . = 0x380 + .globl data_access_slb_pSeries +data_access_slb_pSeries: + HMT_MEDIUM + mtspr SPRG1,r13 + RUNLATCH_ON(r13) + mfspr r13,SPRG3 /* get paca address into r13 */ + std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ + std r10,PACA_EXSLB+EX_R10(r13) + std r11,PACA_EXSLB+EX_R11(r13) + std r12,PACA_EXSLB+EX_R12(r13) + std r3,PACA_EXSLB+EX_R3(r13) + mfspr r9,SPRG1 + std r9,PACA_EXSLB+EX_R13(r13) + mfcr r9 + mfspr r12,SRR1 /* and SRR1 */ + mfspr r3,DAR + b .do_slb_miss /* Rel. branch works in real mode */ + + STD_EXCEPTION_PSERIES(0x400, instruction_access) + + . = 0x480 + .globl instruction_access_slb_pSeries +instruction_access_slb_pSeries: + HMT_MEDIUM + mtspr SPRG1,r13 + RUNLATCH_ON(r13) + mfspr r13,SPRG3 /* get paca address into r13 */ + std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ + std r10,PACA_EXSLB+EX_R10(r13) + std r11,PACA_EXSLB+EX_R11(r13) + std r12,PACA_EXSLB+EX_R12(r13) + std r3,PACA_EXSLB+EX_R3(r13) + mfspr r9,SPRG1 + std r9,PACA_EXSLB+EX_R13(r13) + mfcr r9 + mfspr r12,SRR1 /* and SRR1 */ + mfspr r3,SRR0 /* SRR0 is faulting address */ + b .do_slb_miss /* Rel. branch works in real mode */ + + STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) + STD_EXCEPTION_PSERIES(0x600, alignment) + STD_EXCEPTION_PSERIES(0x700, program_check) + STD_EXCEPTION_PSERIES(0x800, fp_unavailable) + STD_EXCEPTION_PSERIES(0x900, decrementer) + STD_EXCEPTION_PSERIES(0xa00, trap_0a) + STD_EXCEPTION_PSERIES(0xb00, trap_0b) + + . = 0xc00 + .globl system_call_pSeries +system_call_pSeries: + HMT_MEDIUM + RUNLATCH_ON(r9) + mr r9,r13 + mfmsr r10 + mfspr r13,SPRG3 + mfspr r11,SRR0 + clrrdi r12,r13,32 + oris r12,r12,system_call_common@h + ori r12,r12,system_call_common@l + mtspr SRR0,r12 + ori r10,r10,MSR_IR|MSR_DR|MSR_RI + mfspr r12,SRR1 + mtspr SRR1,r10 + rfid + b . /* prevent speculative execution */ + + STD_EXCEPTION_PSERIES(0xd00, single_step) + STD_EXCEPTION_PSERIES(0xe00, trap_0e) + + /* We need to deal with the Altivec unavailable exception + * here which is at 0xf20, thus in the middle of the + * prolog code of the PerformanceMonitor one. A little + * trickery is thus necessary + */ + . = 0xf00 + b performance_monitor_pSeries + + STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) + + STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) + STD_EXCEPTION_PSERIES(0x1700, altivec_assist) + + . = 0x3000 + +/*** pSeries interrupt support ***/ + + /* moved from 0xf00 */ + STD_EXCEPTION_PSERIES(., performance_monitor) + + .align 7 +_GLOBAL(do_stab_bolted_pSeries) + mtcrf 0x80,r12 + mfspr r12,SPRG2 + EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) + +/* + * Vectors for the FWNMI option. Share common code. + */ + .globl system_reset_fwnmi +system_reset_fwnmi: + HMT_MEDIUM + mtspr SPRG1,r13 /* save r13 */ + RUNLATCH_ON(r13) + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) + + .globl machine_check_fwnmi +machine_check_fwnmi: + HMT_MEDIUM + mtspr SPRG1,r13 /* save r13 */ + RUNLATCH_ON(r13) + EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) + +#ifdef CONFIG_PPC_ISERIES +/*** ISeries-LPAR interrupt handlers ***/ + + STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) + + .globl data_access_iSeries +data_access_iSeries: + mtspr SPRG1,r13 +BEGIN_FTR_SECTION + mtspr SPRG2,r12 + mfspr r13,DAR + mfspr r12,DSISR + srdi r13,r13,60 + rlwimi r13,r12,16,0x20 + mfcr r12 + cmpwi r13,0x2c + beq .do_stab_bolted_iSeries + mtcrf 0x80,r12 + mfspr r12,SPRG2 +END_FTR_SECTION_IFCLR(CPU_FTR_SLB) + EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) + EXCEPTION_PROLOG_ISERIES_2 + b data_access_common + +.do_stab_bolted_iSeries: + mtcrf 0x80,r12 + mfspr r12,SPRG2 + EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) + EXCEPTION_PROLOG_ISERIES_2 + b .do_stab_bolted + + .globl data_access_slb_iSeries +data_access_slb_iSeries: + mtspr SPRG1,r13 /* save r13 */ + EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) + std r3,PACA_EXSLB+EX_R3(r13) + ld r12,PACALPPACA+LPPACASRR1(r13) + mfspr r3,DAR + b .do_slb_miss + + STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) + + .globl instruction_access_slb_iSeries +instruction_access_slb_iSeries: + mtspr SPRG1,r13 /* save r13 */ + EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) + std r3,PACA_EXSLB+EX_R3(r13) + ld r12,PACALPPACA+LPPACASRR1(r13) + ld r3,PACALPPACA+LPPACASRR0(r13) + b .do_slb_miss + + MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) + STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) + STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) + STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) + MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) + STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) + STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) + + .globl system_call_iSeries +system_call_iSeries: + mr r9,r13 + mfspr r13,SPRG3 + EXCEPTION_PROLOG_ISERIES_2 + b system_call_common + + STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) + STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) + STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) + + .globl system_reset_iSeries +system_reset_iSeries: + mfspr r13,SPRG3 /* Get paca address */ + mfmsr r24 + ori r24,r24,MSR_RI + mtmsrd r24 /* RI on */ + lhz r24,PACAPACAINDEX(r13) /* Get processor # */ + cmpwi 0,r24,0 /* Are we processor 0? */ + beq .__start_initialization_iSeries /* Start up the first processor */ + mfspr r4,SPRN_CTRLF + li r5,CTRL_RUNLATCH /* Turn off the run light */ + andc r4,r4,r5 + mtspr SPRN_CTRLT,r4 + +1: + HMT_LOW +#ifdef CONFIG_SMP + lbz r23,PACAPROCSTART(r13) /* Test if this processor + * should start */ + sync + LOADADDR(r3,current_set) + sldi r28,r24,3 /* get current_set[cpu#] */ + ldx r3,r3,r28 + addi r1,r3,THREAD_SIZE + subi r1,r1,STACK_FRAME_OVERHEAD + + cmpwi 0,r23,0 + beq iSeries_secondary_smp_loop /* Loop until told to go */ + bne .__secondary_start /* Loop until told to go */ +iSeries_secondary_smp_loop: + /* Let the Hypervisor know we are alive */ + /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ + lis r3,0x8002 + rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ +#else /* CONFIG_SMP */ + /* Yield the processor. This is required for non-SMP kernels + which are running on multi-threaded machines. */ + lis r3,0x8000 + rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ + addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ + li r4,0 /* "yield timed" */ + li r5,-1 /* "yield forever" */ +#endif /* CONFIG_SMP */ + li r0,-1 /* r0=-1 indicates a Hypervisor call */ + sc /* Invoke the hypervisor via a system call */ + mfspr r13,SPRG3 /* Put r13 back ???? */ + b 1b /* If SMP not configured, secondaries + * loop forever */ + + .globl decrementer_iSeries_masked +decrementer_iSeries_masked: + li r11,1 + stb r11,PACALPPACA+LPPACADECRINT(r13) + lwz r12,PACADEFAULTDECR(r13) + mtspr SPRN_DEC,r12 + /* fall through */ + + .globl hardware_interrupt_iSeries_masked +hardware_interrupt_iSeries_masked: + mtcrf 0x80,r9 /* Restore regs */ + ld r11,PACALPPACA+LPPACASRR0(r13) + ld r12,PACALPPACA+LPPACASRR1(r13) + mtspr SRR0,r11 + mtspr SRR1,r12 + ld r9,PACA_EXGEN+EX_R9(r13) + ld r10,PACA_EXGEN+EX_R10(r13) + ld r11,PACA_EXGEN+EX_R11(r13) + ld r12,PACA_EXGEN+EX_R12(r13) + ld r13,PACA_EXGEN+EX_R13(r13) + rfid + b . /* prevent speculative execution */ +#endif /* CONFIG_PPC_ISERIES */ + +/*** Common interrupt handlers ***/ + + STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) + + /* + * Machine check is different because we use a different + * save area: PACA_EXMC instead of PACA_EXGEN. + */ + .align 7 + .globl machine_check_common +machine_check_common: + EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) + DISABLE_INTS + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + bl .machine_check_exception + b .ret_from_except + + STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) + STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) + STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) + STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) + STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) + STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) + STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) +#ifdef CONFIG_ALTIVEC + STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) +#else + STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) +#endif + +/* + * Here we have detected that the kernel stack pointer is bad. + * R9 contains the saved CR, r13 points to the paca, + * r10 contains the (bad) kernel stack pointer, + * r11 and r12 contain the saved SRR0 and SRR1. + * We switch to using an emergency stack, save the registers there, + * and call kernel_bad_stack(), which panics. + */ +bad_stack: + ld r1,PACAEMERGSP(r13) + subi r1,r1,64+INT_FRAME_SIZE + std r9,_CCR(r1) + std r10,GPR1(r1) + std r11,_NIP(r1) + std r12,_MSR(r1) + mfspr r11,DAR + mfspr r12,DSISR + std r11,_DAR(r1) + std r12,_DSISR(r1) + mflr r10 + mfctr r11 + mfxer r12 + std r10,_LINK(r1) + std r11,_CTR(r1) + std r12,_XER(r1) + SAVE_GPR(0,r1) + SAVE_GPR(2,r1) + SAVE_4GPRS(3,r1) + SAVE_2GPRS(7,r1) + SAVE_10GPRS(12,r1) + SAVE_10GPRS(22,r1) + addi r11,r1,INT_FRAME_SIZE + std r11,0(r1) + li r12,0 + std r12,0(r11) + ld r2,PACATOC(r13) +1: addi r3,r1,STACK_FRAME_OVERHEAD + bl .kernel_bad_stack + b 1b + +/* + * Return from an exception with minimal checks. + * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. + * If interrupts have been enabled, or anything has been + * done that might have changed the scheduling status of + * any task or sent any task a signal, you should use + * ret_from_except or ret_from_except_lite instead of this. + */ +fast_exception_return: + ld r12,_MSR(r1) + ld r11,_NIP(r1) + andi. r3,r12,MSR_RI /* check if RI is set */ + beq- unrecov_fer + ld r3,_CCR(r1) + ld r4,_LINK(r1) + ld r5,_CTR(r1) + ld r6,_XER(r1) + mtcr r3 + mtlr r4 + mtctr r5 + mtxer r6 + REST_GPR(0, r1) + REST_8GPRS(2, r1) + + mfmsr r10 + clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ + mtmsrd r10,1 + + mtspr SRR1,r12 + mtspr SRR0,r11 + REST_4GPRS(10, r1) + ld r1,GPR1(r1) + rfid + b . /* prevent speculative execution */ + +unrecov_fer: + bl .save_nvgprs +1: addi r3,r1,STACK_FRAME_OVERHEAD + bl .unrecoverable_exception + b 1b + +/* + * Here r13 points to the paca, r9 contains the saved CR, + * SRR0 and SRR1 are saved in r11 and r12, + * r9 - r13 are saved in paca->exgen. + */ + .align 7 + .globl data_access_common +data_access_common: + RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ + mfspr r10,DAR + std r10,PACA_EXGEN+EX_DAR(r13) + mfspr r10,DSISR + stw r10,PACA_EXGEN+EX_DSISR(r13) + EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) + ld r3,PACA_EXGEN+EX_DAR(r13) + lwz r4,PACA_EXGEN+EX_DSISR(r13) + li r5,0x300 + b .do_hash_page /* Try to handle as hpte fault */ + + .align 7 + .globl instruction_access_common +instruction_access_common: + EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) + ld r3,_NIP(r1) + andis. r4,r12,0x5820 + li r5,0x400 + b .do_hash_page /* Try to handle as hpte fault */ + + .align 7 + .globl hardware_interrupt_common + .globl hardware_interrupt_entry +hardware_interrupt_common: + EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) +hardware_interrupt_entry: + DISABLE_INTS + addi r3,r1,STACK_FRAME_OVERHEAD + bl .do_IRQ + b .ret_from_except_lite + + .align 7 + .globl alignment_common +alignment_common: + mfspr r10,DAR + std r10,PACA_EXGEN+EX_DAR(r13) + mfspr r10,DSISR + stw r10,PACA_EXGEN+EX_DSISR(r13) + EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) + ld r3,PACA_EXGEN+EX_DAR(r13) + lwz r4,PACA_EXGEN+EX_DSISR(r13) + std r3,_DAR(r1) + std r4,_DSISR(r1) + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + ENABLE_INTS + bl .alignment_exception + b .ret_from_except + + .align 7 + .globl program_check_common +program_check_common: + EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + ENABLE_INTS + bl .program_check_exception + b .ret_from_except + + .align 7 + .globl fp_unavailable_common +fp_unavailable_common: + EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) + bne .load_up_fpu /* if from user, just load it up */ + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + ENABLE_INTS + bl .kernel_fp_unavailable_exception + BUG_OPCODE + +/* + * load_up_fpu(unused, unused, tsk) + * Disable FP for the task which had the FPU previously, + * and save its floating-point registers in its thread_struct. + * Enables the FPU for use in the kernel on return. + * On SMP we know the fpu is free, since we give it up every + * switch (ie, no lazy save of the FP registers). + * On entry: r13 == 'current' && last_task_used_math != 'current' + */ +_STATIC(load_up_fpu) + mfmsr r5 /* grab the current MSR */ + ori r5,r5,MSR_FP + mtmsrd r5 /* enable use of fpu now */ + isync +/* + * For SMP, we don't do lazy FPU switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_fpu in switch_to. + * + */ +#ifndef CONFIG_SMP + ld r3,last_task_used_math@got(r2) + ld r4,0(r3) + cmpdi 0,r4,0 + beq 1f + /* Save FP state to last_task_used_math's THREAD struct */ + addi r4,r4,THREAD + SAVE_32FPRS(0, r4) + mffs fr0 + stfd fr0,THREAD_FPSCR(r4) + /* Disable FP for last_task_used_math */ + ld r5,PT_REGS(r4) + ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) + li r6,MSR_FP|MSR_FE0|MSR_FE1 + andc r4,r4,r6 + std r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /* enable use of FP after return */ + ld r4,PACACURRENT(r13) + addi r5,r4,THREAD /* Get THREAD */ + ld r4,THREAD_FPEXC_MODE(r5) + ori r12,r12,MSR_FP + or r12,r12,r4 + std r12,_MSR(r1) + lfd fr0,THREAD_FPSCR(r5) + mtfsf 0xff,fr0 + REST_32FPRS(0, r5) +#ifndef CONFIG_SMP + /* Update last_task_used_math to 'current' */ + subi r4,r5,THREAD /* Back to 'current' */ + std r4,0(r3) +#endif /* CONFIG_SMP */ + /* restore registers and return */ + b fast_exception_return + + .align 7 + .globl altivec_unavailable_common +altivec_unavailable_common: + EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) +#ifdef CONFIG_ALTIVEC +BEGIN_FTR_SECTION + bne .load_up_altivec /* if from user, just load it up */ +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) +#endif + bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + ENABLE_INTS + bl .altivec_unavailable_exception + b .ret_from_except + +#ifdef CONFIG_ALTIVEC +/* + * load_up_altivec(unused, unused, tsk) + * Disable VMX for the task which had it previously, + * and save its vector registers in its thread_struct. + * Enables the VMX for use in the kernel on return. + * On SMP we know the VMX is free, since we give it up every + * switch (ie, no lazy save of the vector registers). + * On entry: r13 == 'current' && last_task_used_altivec != 'current' + */ +_STATIC(load_up_altivec) + mfmsr r5 /* grab the current MSR */ + oris r5,r5,MSR_VEC@h + mtmsrd r5 /* enable use of VMX now */ + isync + +/* + * For SMP, we don't do lazy VMX switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_altvec in switch_to. + * VRSAVE isn't dealt with here, that is done in the normal context + * switch code. Note that we could rely on vrsave value to eventually + * avoid saving all of the VREGs here... + */ +#ifndef CONFIG_SMP + ld r3,last_task_used_altivec@got(r2) + ld r4,0(r3) + cmpdi 0,r4,0 + beq 1f + /* Save VMX state to last_task_used_altivec's THREAD struct */ + addi r4,r4,THREAD + SAVE_32VRS(0,r5,r4) + mfvscr vr0 + li r10,THREAD_VSCR + stvx vr0,r10,r4 + /* Disable VMX for last_task_used_altivec */ + ld r5,PT_REGS(r4) + ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r6,MSR_VEC@h + andc r4,r4,r6 + std r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /* Hack: if we get an altivec unavailable trap with VRSAVE + * set to all zeros, we assume this is a broken application + * that fails to set it properly, and thus we switch it to + * all 1's + */ + mfspr r4,SPRN_VRSAVE + cmpdi 0,r4,0 + bne+ 1f + li r4,-1 + mtspr SPRN_VRSAVE,r4 +1: + /* enable use of VMX after return */ + ld r4,PACACURRENT(r13) + addi r5,r4,THREAD /* Get THREAD */ + oris r12,r12,MSR_VEC@h + std r12,_MSR(r1) + li r4,1 + li r10,THREAD_VSCR + stw r4,THREAD_USED_VR(r5) + lvx vr0,r10,r5 + mtvscr vr0 + REST_32VRS(0,r4,r5) +#ifndef CONFIG_SMP + /* Update last_task_used_math to 'current' */ + subi r4,r5,THREAD /* Back to 'current' */ + std r4,0(r3) +#endif /* CONFIG_SMP */ + /* restore registers and return */ + b fast_exception_return +#endif /* CONFIG_ALTIVEC */ + +/* + * Hash table stuff + */ + .align 7 +_GLOBAL(do_hash_page) + std r3,_DAR(r1) + std r4,_DSISR(r1) + + andis. r0,r4,0xa450 /* weird error? */ + bne- .handle_page_fault /* if not, try to insert a HPTE */ +BEGIN_FTR_SECTION + andis. r0,r4,0x0020 /* Is it a segment table fault? */ + bne- .do_ste_alloc /* If so handle it */ +END_FTR_SECTION_IFCLR(CPU_FTR_SLB) + + /* + * We need to set the _PAGE_USER bit if MSR_PR is set or if we are + * accessing a userspace segment (even from the kernel). We assume + * kernel addresses always have the high bit set. + */ + rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ + rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ + orc r0,r12,r0 /* MSR_PR | ~high_bit */ + rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ + ori r4,r4,1 /* add _PAGE_PRESENT */ + rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ + + /* + * On iSeries, we soft-disable interrupts here, then + * hard-enable interrupts so that the hash_page code can spin on + * the hash_table_lock without problems on a shared processor. + */ + DISABLE_INTS + + /* + * r3 contains the faulting address + * r4 contains the required access permissions + * r5 contains the trap number + * + * at return r3 = 0 for success + */ + bl .hash_page /* build HPTE if possible */ + cmpdi r3,0 /* see if hash_page succeeded */ + +#ifdef DO_SOFT_DISABLE + /* + * If we had interrupts soft-enabled at the point where the + * DSI/ISI occurred, and an interrupt came in during hash_page, + * handle it now. + * We jump to ret_from_except_lite rather than fast_exception_return + * because ret_from_except_lite will check for and handle pending + * interrupts if necessary. + */ + beq .ret_from_except_lite + /* For a hash failure, we don't bother re-enabling interrupts */ + ble- 12f + + /* + * hash_page couldn't handle it, set soft interrupt enable back + * to what it was before the trap. Note that .local_irq_restore + * handles any interrupts pending at this point. + */ + ld r3,SOFTE(r1) + bl .local_irq_restore + b 11f +#else + beq fast_exception_return /* Return from exception on success */ + ble- 12f /* Failure return from hash_page */ + + /* fall through */ +#endif + +/* Here we have a page fault that hash_page can't handle. */ +_GLOBAL(handle_page_fault) + ENABLE_INTS +11: ld r4,_DAR(r1) + ld r5,_DSISR(r1) + addi r3,r1,STACK_FRAME_OVERHEAD + bl .do_page_fault + cmpdi r3,0 + beq+ .ret_from_except_lite + bl .save_nvgprs + mr r5,r3 + addi r3,r1,STACK_FRAME_OVERHEAD + lwz r4,_DAR(r1) + bl .bad_page_fault + b .ret_from_except + +/* We have a page fault that hash_page could handle but HV refused + * the PTE insertion + */ +12: bl .save_nvgprs + addi r3,r1,STACK_FRAME_OVERHEAD + lwz r4,_DAR(r1) + bl .low_hash_fault + b .ret_from_except + + /* here we have a segment miss */ +_GLOBAL(do_ste_alloc) + bl .ste_allocate /* try to insert stab entry */ + cmpdi r3,0 + beq+ fast_exception_return + b .handle_page_fault + +/* + * r13 points to the PACA, r9 contains the saved CR, + * r11 and r12 contain the saved SRR0 and SRR1. + * r9 - r13 are saved in paca->exslb. + * We assume we aren't going to take any exceptions during this procedure. + * We assume (DAR >> 60) == 0xc. + */ + .align 7 +_GLOBAL(do_stab_bolted) + stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ + std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ + + /* Hash to the primary group */ + ld r10,PACASTABVIRT(r13) + mfspr r11,DAR + srdi r11,r11,28 + rldimi r10,r11,7,52 /* r10 = first ste of the group */ + + /* Calculate VSID */ + /* This is a kernel address, so protovsid = ESID */ + ASM_VSID_SCRAMBLE(r11, r9) + rldic r9,r11,12,16 /* r9 = vsid << 12 */ + + /* Search the primary group for a free entry */ +1: ld r11,0(r10) /* Test valid bit of the current ste */ + andi. r11,r11,0x80 + beq 2f + addi r10,r10,16 + andi. r11,r10,0x70 + bne 1b + + /* Stick for only searching the primary group for now. */ + /* At least for now, we use a very simple random castout scheme */ + /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ + mftb r11 + rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ + ori r11,r11,0x10 + + /* r10 currently points to an ste one past the group of interest */ + /* make it point to the randomly selected entry */ + subi r10,r10,128 + or r10,r10,r11 /* r10 is the entry to invalidate */ + + isync /* mark the entry invalid */ + ld r11,0(r10) + rldicl r11,r11,56,1 /* clear the valid bit */ + rotldi r11,r11,8 + std r11,0(r10) + sync + + clrrdi r11,r11,28 /* Get the esid part of the ste */ + slbie r11 + +2: std r9,8(r10) /* Store the vsid part of the ste */ + eieio + + mfspr r11,DAR /* Get the new esid */ + clrrdi r11,r11,28 /* Permits a full 32b of ESID */ + ori r11,r11,0x90 /* Turn on valid and kp */ + std r11,0(r10) /* Put new entry back into the stab */ + + sync + + /* All done -- return from exception. */ + lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ + ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ + + andi. r10,r12,MSR_RI + beq- unrecov_slb + + mtcrf 0x80,r9 /* restore CR */ + + mfmsr r10 + clrrdi r10,r10,2 + mtmsrd r10,1 + + mtspr SRR0,r11 + mtspr SRR1,r12 + ld r9,PACA_EXSLB+EX_R9(r13) + ld r10,PACA_EXSLB+EX_R10(r13) + ld r11,PACA_EXSLB+EX_R11(r13) + ld r12,PACA_EXSLB+EX_R12(r13) + ld r13,PACA_EXSLB+EX_R13(r13) + rfid + b . /* prevent speculative execution */ + +/* + * r13 points to the PACA, r9 contains the saved CR, + * r11 and r12 contain the saved SRR0 and SRR1. + * r3 has the faulting address + * r9 - r13 are saved in paca->exslb. + * r3 is saved in paca->slb_r3 + * We assume we aren't going to take any exceptions during this procedure. + */ +_GLOBAL(do_slb_miss) + mflr r10 + + stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ + std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ + + bl .slb_allocate /* handle it */ + + /* All done -- return from exception. */ + + ld r10,PACA_EXSLB+EX_LR(r13) + ld r3,PACA_EXSLB+EX_R3(r13) + lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ +#ifdef CONFIG_PPC_ISERIES + ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */ +#endif /* CONFIG_PPC_ISERIES */ + + mtlr r10 + + andi. r10,r12,MSR_RI /* check for unrecoverable exception */ + beq- unrecov_slb + +.machine push +.machine "power4" + mtcrf 0x80,r9 + mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ +.machine pop + +#ifdef CONFIG_PPC_ISERIES + mtspr SRR0,r11 + mtspr SRR1,r12 +#endif /* CONFIG_PPC_ISERIES */ + ld r9,PACA_EXSLB+EX_R9(r13) + ld r10,PACA_EXSLB+EX_R10(r13) + ld r11,PACA_EXSLB+EX_R11(r13) + ld r12,PACA_EXSLB+EX_R12(r13) + ld r13,PACA_EXSLB+EX_R13(r13) + rfid + b . /* prevent speculative execution */ + +unrecov_slb: + EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) + DISABLE_INTS + bl .save_nvgprs +1: addi r3,r1,STACK_FRAME_OVERHEAD + bl .unrecoverable_exception + b 1b + +/* + * Space for CPU0's segment table. + * + * On iSeries, the hypervisor must fill in at least one entry before + * we get control (with relocate on). The address is give to the hv + * as a page number (see xLparMap in LparData.c), so this must be at a + * fixed address (the linker can't compute (u64)&initial_stab >> + * PAGE_SHIFT). + */ + . = STAB0_PHYS_ADDR /* 0x6000 */ + .globl initial_stab +initial_stab: + .space 4096 + +/* + * Data area reserved for FWNMI option. + * This address (0x7000) is fixed by the RPA. + */ + .= 0x7000 + .globl fwnmi_data_area +fwnmi_data_area: + + /* iSeries does not use the FWNMI stuff, so it is safe to put + * this here, even if we later allow kernels that will boot on + * both pSeries and iSeries */ +#ifdef CONFIG_PPC_ISERIES + . = LPARMAP_PHYS +#include "lparmap.s" +/* + * This ".text" is here for old compilers that generate a trailing + * .note section when compiling .c files to .s + */ + .text +#endif /* CONFIG_PPC_ISERIES */ + + . = 0x8000 + +/* + * On pSeries, secondary processors spin in the following code. + * At entry, r3 = this processor's number (physical cpu id) + */ +_GLOBAL(pSeries_secondary_smp_init) + mr r24,r3 + + /* turn on 64-bit mode */ + bl .enable_64b_mode + isync + + /* Copy some CPU settings from CPU 0 */ + bl .__restore_cpu_setup + + /* Set up a paca value for this processor. Since we have the + * physical cpu id in r24, we need to search the pacas to find + * which logical id maps to our physical one. + */ + LOADADDR(r13, paca) /* Get base vaddr of paca array */ + li r5,0 /* logical cpu id */ +1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ + cmpw r6,r24 /* Compare to our id */ + beq 2f + addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ + addi r5,r5,1 + cmpwi r5,NR_CPUS + blt 1b + + mr r3,r24 /* not found, copy phys to r3 */ + b .kexec_wait /* next kernel might do better */ + +2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ + /* From now on, r24 is expected to be logical cpuid */ + mr r24,r5 +3: HMT_LOW + lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ + /* start. */ + sync + + /* Create a temp kernel stack for use before relocation is on. */ + ld r1,PACAEMERGSP(r13) + subi r1,r1,STACK_FRAME_OVERHEAD + + cmpwi 0,r23,0 +#ifdef CONFIG_SMP + bne .__secondary_start +#endif + b 3b /* Loop until told to go */ + +#ifdef CONFIG_PPC_ISERIES +_STATIC(__start_initialization_iSeries) + /* Clear out the BSS */ + LOADADDR(r11,__bss_stop) + LOADADDR(r8,__bss_start) + sub r11,r11,r8 /* bss size */ + addi r11,r11,7 /* round up to an even double word */ + rldicl. r11,r11,61,3 /* shift right by 3 */ + beq 4f + addi r8,r8,-8 + li r0,0 + mtctr r11 /* zero this many doublewords */ +3: stdu r0,8(r8) + bdnz 3b +4: + LOADADDR(r1,init_thread_union) + addi r1,r1,THREAD_SIZE + li r0,0 + stdu r0,-STACK_FRAME_OVERHEAD(r1) + + LOADADDR(r3,cpu_specs) + LOADADDR(r4,cur_cpu_spec) + li r5,0 + bl .identify_cpu + + LOADADDR(r2,__toc_start) + addi r2,r2,0x4000 + addi r2,r2,0x4000 + + bl .iSeries_early_setup + + /* relocation is on at this point */ + + b .start_here_common +#endif /* CONFIG_PPC_ISERIES */ + +#ifdef CONFIG_PPC_MULTIPLATFORM + +_STATIC(__mmu_off) + mfmsr r3 + andi. r0,r3,MSR_IR|MSR_DR + beqlr + andc r3,r3,r0 + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + sync + rfid + b . /* prevent speculative execution */ + + +/* + * Here is our main kernel entry point. We support currently 2 kind of entries + * depending on the value of r5. + * + * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content + * in r3...r7 + * + * r5 == NULL -> kexec style entry. r3 is a physical pointer to the + * DT block, r4 is a physical pointer to the kernel itself + * + */ +_GLOBAL(__start_initialization_multiplatform) + /* + * Are we booted from a PROM Of-type client-interface ? + */ + cmpldi cr0,r5,0 + bne .__boot_from_prom /* yes -> prom */ + + /* Save parameters */ + mr r31,r3 + mr r30,r4 + + /* Make sure we are running in 64 bits mode */ + bl .enable_64b_mode + + /* Setup some critical 970 SPRs before switching MMU off */ + bl .__970_cpu_preinit + + /* cpu # */ + li r24,0 + + /* Switch off MMU if not already */ + LOADADDR(r4, .__after_prom_start - KERNELBASE) + add r4,r4,r30 + bl .__mmu_off + b .__after_prom_start + +_STATIC(__boot_from_prom) + /* Save parameters */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + + /* Make sure we are running in 64 bits mode */ + bl .enable_64b_mode + + /* put a relocation offset into r3 */ + bl .reloc_offset + + LOADADDR(r2,__toc_start) + addi r2,r2,0x4000 + addi r2,r2,0x4000 + + /* Relocate the TOC from a virt addr to a real addr */ + sub r2,r2,r3 + + /* Restore parameters */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + + /* Do all of the interaction with OF client interface */ + bl .prom_init + /* We never return */ + trap + +/* + * At this point, r3 contains the physical address we are running at, + * returned by prom_init() + */ +_STATIC(__after_prom_start) + +/* + * We need to run with __start at physical address 0. + * This will leave some code in the first 256B of + * real memory, which are reserved for software use. + * The remainder of the first page is loaded with the fixed + * interrupt vectors. The next two pages are filled with + * unknown exception placeholders. + * + * Note: This process overwrites the OF exception vectors. + * r26 == relocation offset + * r27 == KERNELBASE + */ + bl .reloc_offset + mr r26,r3 + SET_REG_TO_CONST(r27,KERNELBASE) + + li r3,0 /* target addr */ + + // XXX FIXME: Use phys returned by OF (r30) + sub r4,r27,r26 /* source addr */ + /* current address of _start */ + /* i.e. where we are running */ + /* the source addr */ + + LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */ + sub r5,r5,r27 + + li r6,0x100 /* Start offset, the first 0x100 */ + /* bytes were copied earlier. */ + + bl .copy_and_flush /* copy the first n bytes */ + /* this includes the code being */ + /* executed here. */ + + LOADADDR(r0, 4f) /* Jump to the copy of this code */ + mtctr r0 /* that we just made/relocated */ + bctr + +4: LOADADDR(r5,klimit) + sub r5,r5,r26 + ld r5,0(r5) /* get the value of klimit */ + sub r5,r5,r27 + bl .copy_and_flush /* copy the rest */ + b .start_here_multiplatform + +#endif /* CONFIG_PPC_MULTIPLATFORM */ + +/* + * Copy routine used to copy the kernel to start at physical address 0 + * and flush and invalidate the caches as needed. + * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset + * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. + * + * Note: this routine *only* clobbers r0, r6 and lr + */ +_GLOBAL(copy_and_flush) + addi r5,r5,-8 + addi r6,r6,-8 +4: li r0,16 /* Use the least common */ + /* denominator cache line */ + /* size. This results in */ + /* extra cache line flushes */ + /* but operation is correct. */ + /* Can't get cache line size */ + /* from NACA as it is being */ + /* moved too. */ + + mtctr r0 /* put # words/line in ctr */ +3: addi r6,r6,8 /* copy a cache line */ + ldx r0,r6,r4 + stdx r0,r6,r3 + bdnz 3b + dcbst r6,r3 /* write it to memory */ + sync + icbi r6,r3 /* flush the icache line */ + cmpld 0,r6,r5 + blt 4b + sync + addi r5,r5,8 + addi r6,r6,8 + blr + +.align 8 +copy_to_here: + +#ifdef CONFIG_SMP +#ifdef CONFIG_PPC_PMAC +/* + * On PowerMac, secondary processors starts from the reset vector, which + * is temporarily turned into a call to one of the functions below. + */ + .section ".text"; + .align 2 ; + + .globl pmac_secondary_start_1 +pmac_secondary_start_1: + li r24, 1 + b .pmac_secondary_start + + .globl pmac_secondary_start_2 +pmac_secondary_start_2: + li r24, 2 + b .pmac_secondary_start + + .globl pmac_secondary_start_3 +pmac_secondary_start_3: + li r24, 3 + b .pmac_secondary_start + +_GLOBAL(pmac_secondary_start) + /* turn on 64-bit mode */ + bl .enable_64b_mode + isync + + /* Copy some CPU settings from CPU 0 */ + bl .__restore_cpu_setup + + /* pSeries do that early though I don't think we really need it */ + mfmsr r3 + ori r3,r3,MSR_RI + mtmsrd r3 /* RI on */ + + /* Set up a paca value for this processor. */ + LOADADDR(r4, paca) /* Get base vaddr of paca array */ + mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ + add r13,r13,r4 /* for this processor. */ + mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ + + /* Create a temp kernel stack for use before relocation is on. */ + ld r1,PACAEMERGSP(r13) + subi r1,r1,STACK_FRAME_OVERHEAD + + b .__secondary_start + +#endif /* CONFIG_PPC_PMAC */ + +/* + * This function is called after the master CPU has released the + * secondary processors. The execution environment is relocation off. + * The paca for this processor has the following fields initialized at + * this point: + * 1. Processor number + * 2. Segment table pointer (virtual address) + * On entry the following are set: + * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries + * r24 = cpu# (in Linux terms) + * r13 = paca virtual address + * SPRG3 = paca virtual address + */ +_GLOBAL(__secondary_start) + + HMT_MEDIUM /* Set thread priority to MEDIUM */ + + ld r2,PACATOC(r13) + li r6,0 + stb r6,PACAPROCENABLED(r13) + +#ifndef CONFIG_PPC_ISERIES + /* Initialize the page table pointer register. */ + LOADADDR(r6,_SDR1) + ld r6,0(r6) /* get the value of _SDR1 */ + mtspr SDR1,r6 /* set the htab location */ +#endif + /* Initialize the first segment table (or SLB) entry */ + ld r3,PACASTABVIRT(r13) /* get addr of segment table */ + bl .stab_initialize + + /* Initialize the kernel stack. Just a repeat for iSeries. */ + LOADADDR(r3,current_set) + sldi r28,r24,3 /* get current_set[cpu#] */ + ldx r1,r3,r28 + addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD + std r1,PACAKSAVE(r13) + + ld r3,PACASTABREAL(r13) /* get raddr of segment table */ + ori r4,r3,1 /* turn on valid bit */ + +#ifdef CONFIG_PPC_ISERIES + li r0,-1 /* hypervisor call */ + li r3,1 + sldi r3,r3,63 /* 0x8000000000000000 */ + ori r3,r3,4 /* 0x8000000000000004 */ + sc /* HvCall_setASR */ +#else + /* set the ASR */ + ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ + ld r3,0(r3) + lwz r3,PLATFORM(r3) /* r3 = platform flags */ + andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ + beq 98f /* branch if result is 0 */ + mfspr r3,PVR + srwi r3,r3,16 + cmpwi r3,0x37 /* SStar */ + beq 97f + cmpwi r3,0x36 /* IStar */ + beq 97f + cmpwi r3,0x34 /* Pulsar */ + bne 98f +97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ + HVSC /* Invoking hcall */ + b 99f +98: /* !(rpa hypervisor) || !(star) */ + mtasr r4 /* set the stab location */ +99: +#endif + li r7,0 + mtlr r7 + + /* enable MMU and jump to start_secondary */ + LOADADDR(r3,.start_secondary_prolog) + SET_REG_TO_CONST(r4, MSR_KERNEL) +#ifdef DO_SOFT_DISABLE + ori r4,r4,MSR_EE +#endif + mtspr SRR0,r3 + mtspr SRR1,r4 + rfid + b . /* prevent speculative execution */ + +/* + * Running with relocation on at this point. All we want to do is + * zero the stack back-chain pointer before going into C code. + */ +_GLOBAL(start_secondary_prolog) + li r3,0 + std r3,0(r1) /* Zero the stack frame pointer */ + bl .start_secondary +#endif + +/* + * This subroutine clobbers r11 and r12 + */ +_GLOBAL(enable_64b_mode) + mfmsr r11 /* grab the current MSR */ + li r12,1 + rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) + or r11,r11,r12 + li r12,1 + rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) + or r11,r11,r12 + mtmsrd r11 + isync + blr + +#ifdef CONFIG_PPC_MULTIPLATFORM +/* + * This is where the main kernel code starts. + */ +_STATIC(start_here_multiplatform) + /* get a new offset, now that the kernel has moved. */ + bl .reloc_offset + mr r26,r3 + + /* Clear out the BSS. It may have been done in prom_init, + * already but that's irrelevant since prom_init will soon + * be detached from the kernel completely. Besides, we need + * to clear it now for kexec-style entry. + */ + LOADADDR(r11,__bss_stop) + LOADADDR(r8,__bss_start) + sub r11,r11,r8 /* bss size */ + addi r11,r11,7 /* round up to an even double word */ + rldicl. r11,r11,61,3 /* shift right by 3 */ + beq 4f + addi r8,r8,-8 + li r0,0 + mtctr r11 /* zero this many doublewords */ +3: stdu r0,8(r8) + bdnz 3b +4: + + mfmsr r6 + ori r6,r6,MSR_RI + mtmsrd r6 /* RI on */ + +#ifdef CONFIG_HMT + /* Start up the second thread on cpu 0 */ + mfspr r3,PVR + srwi r3,r3,16 + cmpwi r3,0x34 /* Pulsar */ + beq 90f + cmpwi r3,0x36 /* Icestar */ + beq 90f + cmpwi r3,0x37 /* SStar */ + beq 90f + b 91f /* HMT not supported */ +90: li r3,0 + bl .hmt_start_secondary +91: +#endif + + /* The following gets the stack and TOC set up with the regs */ + /* pointing to the real addr of the kernel stack. This is */ + /* all done to support the C function call below which sets */ + /* up the htab. This is done because we have relocated the */ + /* kernel but are still running in real mode. */ + + LOADADDR(r3,init_thread_union) + sub r3,r3,r26 + + /* set up a stack pointer (physical address) */ + addi r1,r3,THREAD_SIZE + li r0,0 + stdu r0,-STACK_FRAME_OVERHEAD(r1) + + /* set up the TOC (physical address) */ + LOADADDR(r2,__toc_start) + addi r2,r2,0x4000 + addi r2,r2,0x4000 + sub r2,r2,r26 + + LOADADDR(r3,cpu_specs) + sub r3,r3,r26 + LOADADDR(r4,cur_cpu_spec) + sub r4,r4,r26 + mr r5,r26 + bl .identify_cpu + + /* Save some low level config HIDs of CPU0 to be copied to + * other CPUs later on, or used for suspend/resume + */ + bl .__save_cpu_setup + sync + + /* Setup a valid physical PACA pointer in SPRG3 for early_setup + * note that boot_cpuid can always be 0 nowadays since there is + * nowhere it can be initialized differently before we reach this + * code + */ + LOADADDR(r27, boot_cpuid) + sub r27,r27,r26 + lwz r27,0(r27) + + LOADADDR(r24, paca) /* Get base vaddr of paca array */ + mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ + add r13,r13,r24 /* for this processor. */ + sub r13,r13,r26 /* convert to physical addr */ + mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */ + + /* Do very early kernel initializations, including initial hash table, + * stab and slb setup before we turn on relocation. */ + + /* Restore parameters passed from prom_init/kexec */ + mr r3,r31 + bl .early_setup + + /* set the ASR */ + ld r3,PACASTABREAL(r13) + ori r4,r3,1 /* turn on valid bit */ + ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ + ld r3,0(r3) + lwz r3,PLATFORM(r3) /* r3 = platform flags */ + andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ + beq 98f /* branch if result is 0 */ + mfspr r3,PVR + srwi r3,r3,16 + cmpwi r3,0x37 /* SStar */ + beq 97f + cmpwi r3,0x36 /* IStar */ + beq 97f + cmpwi r3,0x34 /* Pulsar */ + bne 98f +97: li r3,H_SET_ASR /* hcall = H_SET_ASR */ + HVSC /* Invoking hcall */ + b 99f +98: /* !(rpa hypervisor) || !(star) */ + mtasr r4 /* set the stab location */ +99: + /* Set SDR1 (hash table pointer) */ + ld r3,systemcfg@got(r2) /* r3 = ptr to systemcfg */ + ld r3,0(r3) + lwz r3,PLATFORM(r3) /* r3 = platform flags */ + /* Test if bit 0 is set (LPAR bit) */ + andi. r3,r3,PLATFORM_LPAR + bne 98f /* branch if result is !0 */ + LOADADDR(r6,_SDR1) /* Only if NOT LPAR */ + sub r6,r6,r26 + ld r6,0(r6) /* get the value of _SDR1 */ + mtspr SDR1,r6 /* set the htab location */ +98: + LOADADDR(r3,.start_here_common) + SET_REG_TO_CONST(r4, MSR_KERNEL) + mtspr SRR0,r3 + mtspr SRR1,r4 + rfid + b . /* prevent speculative execution */ +#endif /* CONFIG_PPC_MULTIPLATFORM */ + + /* This is where all platforms converge execution */ +_STATIC(start_here_common) + /* relocation is on at this point */ + + /* The following code sets up the SP and TOC now that we are */ + /* running with translation enabled. */ + + LOADADDR(r3,init_thread_union) + + /* set up the stack */ + addi r1,r3,THREAD_SIZE + li r0,0 + stdu r0,-STACK_FRAME_OVERHEAD(r1) + + /* Apply the CPUs-specific fixups (nop out sections not relevant + * to this CPU + */ + li r3,0 + bl .do_cpu_ftr_fixups + + LOADADDR(r26, boot_cpuid) + lwz r26,0(r26) + + LOADADDR(r24, paca) /* Get base vaddr of paca array */ + mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ + add r13,r13,r24 /* for this processor. */ + mtspr SPRG3,r13 + + /* ptr to current */ + LOADADDR(r4,init_task) + std r4,PACACURRENT(r13) + + /* Load the TOC */ + ld r2,PACATOC(r13) + std r1,PACAKSAVE(r13) + + bl .setup_system + + /* Load up the kernel context */ +5: +#ifdef DO_SOFT_DISABLE + li r5,0 + stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ + mfmsr r5 + ori r5,r5,MSR_EE /* Hard Enabled */ + mtmsrd r5 +#endif + + bl .start_kernel + +_GLOBAL(hmt_init) +#ifdef CONFIG_HMT + LOADADDR(r5, hmt_thread_data) + mfspr r7,PVR + srwi r7,r7,16 + cmpwi r7,0x34 /* Pulsar */ + beq 90f + cmpwi r7,0x36 /* Icestar */ + beq 91f + cmpwi r7,0x37 /* SStar */ + beq 91f + b 101f +90: mfspr r6,PIR + andi. r6,r6,0x1f + b 92f +91: mfspr r6,PIR + andi. r6,r6,0x3ff +92: sldi r4,r24,3 + stwx r6,r5,r4 + bl .hmt_start_secondary + b 101f + +__hmt_secondary_hold: + LOADADDR(r5, hmt_thread_data) + clrldi r5,r5,4 + li r7,0 + mfspr r6,PIR + mfspr r8,PVR + srwi r8,r8,16 + cmpwi r8,0x34 + bne 93f + andi. r6,r6,0x1f + b 103f +93: andi. r6,r6,0x3f + +103: lwzx r8,r5,r7 + cmpw r8,r6 + beq 104f + addi r7,r7,8 + b 103b + +104: addi r7,r7,4 + lwzx r9,r5,r7 + mr r24,r9 +101: +#endif + mr r3,r24 + b .pSeries_secondary_smp_init + +#ifdef CONFIG_HMT +_GLOBAL(hmt_start_secondary) + LOADADDR(r4,__hmt_secondary_hold) + clrldi r4,r4,4 + mtspr NIADORM, r4 + mfspr r4, MSRDORM + li r5, -65 + and r4, r4, r5 + mtspr MSRDORM, r4 + lis r4,0xffef + ori r4,r4,0x7403 + mtspr TSC, r4 + li r4,0x1f4 + mtspr TST, r4 + mfspr r4, HID0 + ori r4, r4, 0x1 + mtspr HID0, r4 + mfspr r4, SPRN_CTRLF + oris r4, r4, 0x40 + mtspr SPRN_CTRLT, r4 + blr +#endif + +#if defined(CONFIG_KEXEC) || (defined(CONFIG_SMP) && !defined(CONFIG_PPC_ISERIES)) +_GLOBAL(smp_release_cpus) + /* All secondary cpus are spinning on a common + * spinloop, release them all now so they can start + * to spin on their individual paca spinloops. + * For non SMP kernels, the secondary cpus never + * get out of the common spinloop. + */ + li r3,1 + LOADADDR(r5,__secondary_hold_spinloop) + std r3,0(r5) + sync + blr +#endif /* CONFIG_SMP && !CONFIG_PPC_ISERIES */ + + +/* + * We put a few things here that have to be page-aligned. + * This stuff goes at the beginning of the bss, which is page-aligned. + */ + .section ".bss" + + .align PAGE_SHIFT + + .globl empty_zero_page +empty_zero_page: + .space PAGE_SIZE + + .globl swapper_pg_dir +swapper_pg_dir: + .space PAGE_SIZE + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * Used to pass parameters into the kernel like root=/dev/sda1, etc. + */ + .globl cmd_line +cmd_line: + .space COMMAND_LINE_SIZE diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S new file mode 100644 index 00000000000..cb1a3a54a02 --- /dev/null +++ b/arch/powerpc/kernel/head_8xx.S @@ -0,0 +1,860 @@ +/* + * arch/ppc/kernel/except_8xx.S + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * MPC8xx modifications by Dan Malek + * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). + * + * This file contains low-level support and setup for PowerPC 8xx + * embedded processors, including trap and interrupt dispatch. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Macro to make the code more readable. */ +#ifdef CONFIG_8xx_CPU6 +#define DO_8xx_CPU6(val, reg) \ + li reg, val; \ + stw reg, 12(r0); \ + lwz reg, 12(r0); +#else +#define DO_8xx_CPU6(val, reg) +#endif + .text + .globl _stext +_stext: + .text + .globl _start +_start: + +/* MPC8xx + * This port was done on an MBX board with an 860. Right now I only + * support an ELF compressed (zImage) boot from EPPC-Bug because the + * code there loads up some registers before calling us: + * r3: ptr to board info data + * r4: initrd_start or if no initrd then 0 + * r5: initrd_end - unused if r4 is 0 + * r6: Start of command line string + * r7: End of command line string + * + * I decided to use conditional compilation instead of checking PVR and + * adding more processor specific branches around code I don't need. + * Since this is an embedded processor, I also appreciate any memory + * savings I can get. + * + * The MPC8xx does not have any BATs, but it supports large page sizes. + * We first initialize the MMU to support 8M byte pages, then load one + * entry into each of the instruction and data TLBs to map the first + * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to + * the "internal" processor registers before MMU_init is called. + * + * The TLB code currently contains a major hack. Since I use the condition + * code register, I have to save and restore it. I am out of registers, so + * I just store it in memory location 0 (the TLB handlers are not reentrant). + * To avoid making any decisions, I need to use the "segment" valid bit + * in the first level table, but that would require many changes to the + * Linux page directory/table functions that I don't want to do right now. + * + * I used to use SPRG2 for a temporary register in the TLB handler, but it + * has since been put to other uses. I now use a hack to save a register + * and the CCR at memory location 0.....Someday I'll fix this..... + * -- Dan + */ + .globl __start +__start: + mr r31,r3 /* save parameters */ + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + + /* We have to turn on the MMU right away so we get cache modes + * set correctly. + */ + bl initial_mmu + +/* We now have the lower 8 Meg mapped into TLB entries, and the caches + * ready to work. + */ + +turn_on_mmu: + mfmsr r0 + ori r0,r0,MSR_DR|MSR_IR + mtspr SPRN_SRR1,r0 + lis r0,start_here@h + ori r0,r0,start_here@l + mtspr SPRN_SRR0,r0 + SYNC + rfi /* enables MMU */ + +/* + * Exception entry code. This code runs with address translation + * turned off, i.e. using physical addresses. + * We assume sprg3 has the physical address of the current + * task's thread_struct. + */ +#define EXCEPTION_PROLOG \ + mtspr SPRN_SPRG0,r10; \ + mtspr SPRN_SPRG1,r11; \ + mfcr r10; \ + EXCEPTION_PROLOG_1; \ + EXCEPTION_PROLOG_2 + +#define EXCEPTION_PROLOG_1 \ + mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ + andi. r11,r11,MSR_PR; \ + tophys(r11,r1); /* use tophys(r1) if kernel */ \ + beq 1f; \ + mfspr r11,SPRN_SPRG3; \ + lwz r11,THREAD_INFO-THREAD(r11); \ + addi r11,r11,THREAD_SIZE; \ + tophys(r11,r11); \ +1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ + + +#define EXCEPTION_PROLOG_2 \ + CLR_TOP32(r11); \ + stw r10,_CCR(r11); /* save registers */ \ + stw r12,GPR12(r11); \ + stw r9,GPR9(r11); \ + mfspr r10,SPRN_SPRG0; \ + stw r10,GPR10(r11); \ + mfspr r12,SPRN_SPRG1; \ + stw r12,GPR11(r11); \ + mflr r10; \ + stw r10,_LINK(r11); \ + mfspr r12,SPRN_SRR0; \ + mfspr r9,SPRN_SRR1; \ + stw r1,GPR1(r11); \ + stw r1,0(r11); \ + tovirt(r1,r11); /* set new kernel sp */ \ + li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ + MTMSRD(r10); /* (except for mach check in rtas) */ \ + stw r0,GPR0(r11); \ + SAVE_4GPRS(3, r11); \ + SAVE_2GPRS(7, r11) + +/* + * Note: code which follows this uses cr0.eq (set if from kernel), + * r11, r12 (SRR0), and r9 (SRR1). + * + * Note2: once we have set r1 we are in a position to take exceptions + * again, and we could thus set MSR:RI at that point. + */ + +/* + * Exception vectors. + */ +#define EXCEPTION(n, label, hdlr, xfer) \ + . = n; \ +label: \ + EXCEPTION_PROLOG; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + xfer(n, hdlr) + +#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ + li r10,trap; \ + stw r10,TRAP(r11); \ + li r10,MSR_KERNEL; \ + copyee(r10, r9); \ + bl tfer; \ +i##n: \ + .long hdlr; \ + .long ret + +#define COPY_EE(d, s) rlwimi d,s,0,16,16 +#define NOCOPY(d, s) + +#define EXC_XFER_STD(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ + ret_from_except) + +#define EXC_XFER_EE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ + ret_from_except_full) + +#define EXC_XFER_EE_LITE(n, hdlr) \ + EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ + ret_from_except) + +/* System reset */ + EXCEPTION(0x100, Reset, UnknownException, EXC_XFER_STD) + +/* Machine check */ + . = 0x200 +MachineCheck: + EXCEPTION_PROLOG + mfspr r4,SPRN_DAR + stw r4,_DAR(r11) + mfspr r5,SPRN_DSISR + stw r5,_DSISR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_STD(0x200, MachineCheckException) + +/* Data access exception. + * This is "never generated" by the MPC8xx. We jump to it for other + * translation errors. + */ + . = 0x300 +DataAccess: + EXCEPTION_PROLOG + mfspr r10,SPRN_DSISR + stw r10,_DSISR(r11) + mr r5,r10 + mfspr r4,SPRN_DAR + EXC_XFER_EE_LITE(0x300, handle_page_fault) + +/* Instruction access exception. + * This is "never generated" by the MPC8xx. We jump to it for other + * translation errors. + */ + . = 0x400 +InstructionAccess: + EXCEPTION_PROLOG + mr r4,r12 + mr r5,r9 + EXC_XFER_EE_LITE(0x400, handle_page_fault) + +/* External interrupt */ + EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) + +/* Alignment exception */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG + mfspr r4,SPRN_DAR + stw r4,_DAR(r11) + mfspr r5,SPRN_DSISR + stw r5,_DSISR(r11) + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE(0x600, AlignmentException) + +/* Program check exception */ + EXCEPTION(0x700, ProgramCheck, ProgramCheckException, EXC_XFER_STD) + +/* No FPU on MPC8xx. This exception is not supposed to happen. +*/ + EXCEPTION(0x800, FPUnavailable, UnknownException, EXC_XFER_STD) + +/* Decrementer */ + EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) + + EXCEPTION(0xa00, Trap_0a, UnknownException, EXC_XFER_EE) + EXCEPTION(0xb00, Trap_0b, UnknownException, EXC_XFER_EE) + +/* System call */ + . = 0xc00 +SystemCall: + EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0xc00, DoSyscall) + +/* Single step - not used on 601 */ + EXCEPTION(0xd00, SingleStep, SingleStepException, EXC_XFER_STD) + EXCEPTION(0xe00, Trap_0e, UnknownException, EXC_XFER_EE) + EXCEPTION(0xf00, Trap_0f, UnknownException, EXC_XFER_EE) + +/* On the MPC8xx, this is a software emulation interrupt. It occurs + * for all unimplemented and illegal instructions. + */ + EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) + + . = 0x1100 +/* + * For the MPC8xx, this is a software tablewalk to load the instruction + * TLB. It is modelled after the example in the Motorola manual. The task + * switch loads the M_TWB register with the pointer to the first level table. + * If we discover there is no second level table (value is zero) or if there + * is an invalid pte, we load that into the TLB, which causes another fault + * into the TLB Error interrupt where we can handle such problems. + * We have to use the MD_xxx registers for the tablewalk because the + * equivalent MI_xxx registers only perform the attribute functions. + */ +InstructionTLBMiss: +#ifdef CONFIG_8xx_CPU6 + stw r3, 8(r0) +#endif + DO_8xx_CPU6(0x3f80, r3) + mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ + mfcr r10 + stw r10, 0(r0) + stw r11, 4(r0) + mfspr r10, SPRN_SRR0 /* Get effective address of fault */ + DO_8xx_CPU6(0x3780, r3) + mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ + mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ + beq 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + rlwimi r10, r11, 0, 2, 19 +3: + lwz r11, 0(r10) /* Get the level 1 entry */ + rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ + beq 2f /* If zero, don't try to find a pte */ + + /* We have a pte table, so load the MI_TWC with the attributes + * for this "segment." + */ + ori r11,r11,1 /* Set valid bit */ + DO_8xx_CPU6(0x2b80, r3) + mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ + mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ + lwz r10, 0(r11) /* Get the pte */ + + ori r10, r10, _PAGE_ACCESSED + stw r10, 0(r11) + + /* The Linux PTE won't go exactly into the MMU TLB. + * Software indicator bits 21, 22 and 28 must be clear. + * Software indicator bits 24, 25, 26, and 27 must be + * set. All other Linux PTE bits control the behavior + * of the MMU. + */ +2: li r11, 0x00f0 + rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + DO_8xx_CPU6(0x2d80, r3) + mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ + + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + rfi + + . = 0x1200 +DataStoreTLBMiss: +#ifdef CONFIG_8xx_CPU6 + stw r3, 8(r0) +#endif + DO_8xx_CPU6(0x3f80, r3) + mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ + mfcr r10 + stw r10, 0(r0) + stw r11, 4(r0) + mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andi. r11, r10, 0x0800 + beq 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + rlwimi r10, r11, 0, 2, 19 +3: + lwz r11, 0(r10) /* Get the level 1 entry */ + rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ + beq 2f /* If zero, don't try to find a pte */ + + /* We have a pte table, so load fetch the pte from the table. + */ + ori r11, r11, 1 /* Set valid bit in physical L2 page */ + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ + mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ + lwz r10, 0(r10) /* Get the pte */ + + /* Insert the Guarded flag into the TWC from the Linux PTE. + * It is bit 27 of both the Linux PTE and the TWC (at least + * I got that right :-). It will be better when we can put + * this into the Linux pgd/pmd and load it in the operation + * above. + */ + rlwimi r11, r10, 0, 27, 27 + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11 + + mfspr r11, SPRN_MD_TWC /* get the pte address again */ + ori r10, r10, _PAGE_ACCESSED + stw r10, 0(r11) + + /* The Linux PTE won't go exactly into the MMU TLB. + * Software indicator bits 21, 22 and 28 must be clear. + * Software indicator bits 24, 25, 26, and 27 must be + * set. All other Linux PTE bits control the behavior + * of the MMU. + */ +2: li r11, 0x00f0 + rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + DO_8xx_CPU6(0x3d80, r3) + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ + + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + rfi + +/* This is an instruction TLB error on the MPC8xx. This could be due + * to many reasons, such as executing guarded memory or illegal instruction + * addresses. There is nothing to do but handle a big time error fault. + */ + . = 0x1300 +InstructionTLBError: + b InstructionAccess + +/* This is the data TLB error on the MPC8xx. This could be due to + * many reasons, including a dirty update to a pte. We can catch that + * one here, but anything else is an error. First, we track down the + * Linux pte. If it is valid, write access is allowed, but the + * page dirty bit is not set, we will set it and reload the TLB. For + * any other case, we bail out to a higher level function that can + * handle it. + */ + . = 0x1400 +DataTLBError: +#ifdef CONFIG_8xx_CPU6 + stw r3, 8(r0) +#endif + DO_8xx_CPU6(0x3f80, r3) + mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ + mfcr r10 + stw r10, 0(r0) + stw r11, 4(r0) + + /* First, make sure this was a store operation. + */ + mfspr r10, SPRN_DSISR + andis. r11, r10, 0x0200 /* If set, indicates store op */ + beq 2f + + /* The EA of a data TLB miss is automatically stored in the MD_EPN + * register. The EA of a data TLB error is automatically stored in + * the DAR, but not the MD_EPN register. We must copy the 20 most + * significant bits of the EA from the DAR to MD_EPN before we + * start walking the page tables. We also need to copy the CASID + * value from the M_CASID register. + * Addendum: The EA of a data TLB error is _supposed_ to be stored + * in DAR, but it seems that this doesn't happen in some cases, such + * as when the error is due to a dcbi instruction to a page with a + * TLB that doesn't have the changed bit set. In such cases, there + * does not appear to be any way to recover the EA of the error + * since it is neither in DAR nor MD_EPN. As a workaround, the + * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs + * are initialized in mapin_ram(). This will avoid the problem, + * assuming we only use the dcbi instruction on kernel addresses. + */ + mfspr r10, SPRN_DAR + rlwinm r11, r10, 0, 0, 19 + ori r11, r11, MD_EVALID + mfspr r10, SPRN_M_CASID + rlwimi r11, r10, 0, 28, 31 + DO_8xx_CPU6(0x3780, r3) + mtspr SPRN_MD_EPN, r11 + + mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + andi. r11, r10, 0x0800 + beq 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + rlwimi r10, r11, 0, 2, 19 +3: + lwz r11, 0(r10) /* Get the level 1 entry */ + rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ + beq 2f /* If zero, bail */ + + /* We have a pte table, so fetch the pte from the table. + */ + ori r11, r11, 1 /* Set valid bit in physical L2 page */ + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ + mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ + lwz r10, 0(r11) /* Get the pte */ + + andi. r11, r10, _PAGE_RW /* Is it writeable? */ + beq 2f /* Bail out if not */ + + /* Update 'changed', among others. + */ + ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + mfspr r11, SPRN_MD_TWC /* Get pte address again */ + stw r10, 0(r11) /* and update pte in table */ + + /* The Linux PTE won't go exactly into the MMU TLB. + * Software indicator bits 21, 22 and 28 must be clear. + * Software indicator bits 24, 25, 26, and 27 must be + * set. All other Linux PTE bits control the behavior + * of the MMU. + */ + li r11, 0x00f0 + rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ + DO_8xx_CPU6(0x3d80, r3) + mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ + + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + rfi +2: + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcr r11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + b DataAccess + + EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1a00, Trap_1a, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1b00, Trap_1b, UnknownException, EXC_XFER_EE) + +/* On the MPC8xx, these next four traps are used for development + * support of breakpoints and such. Someday I will get around to + * using them. + */ + EXCEPTION(0x1c00, Trap_1c, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1d00, Trap_1d, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1e00, Trap_1e, UnknownException, EXC_XFER_EE) + EXCEPTION(0x1f00, Trap_1f, UnknownException, EXC_XFER_EE) + + . = 0x2000 + + .globl giveup_fpu +giveup_fpu: + blr + +/* + * This is where the main kernel code starts. + */ +start_here: + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + + /* ptr to phys current thread */ + tophys(r4,r2) + addi r4,r4,THREAD /* init task's THREAD */ + mtspr SPRN_SPRG3,r4 + li r3,0 + mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ + + /* stack */ + lis r1,init_thread_union@ha + addi r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) + + bl early_init /* We have to do this with MMU on */ + +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + +/* + * Go back to running unmapped so we can load up new values + * and change to using our exception vectors. + * On the 8xx, all we have to do is invalidate the TLB to clear + * the old 8M byte TLB mappings and load the page table base register. + */ + /* The right way to do this would be to track it down through + * init's THREAD like the context switch code does, but this is + * easier......until someone changes init's static structures. + */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + tophys(r6,r6) +#ifdef CONFIG_8xx_CPU6 + lis r4, cpu6_errata_word@h + ori r4, r4, cpu6_errata_word@l + li r3, 0x3980 + stw r3, 12(r4) + lwz r3, 12(r4) +#endif + mtspr SPRN_M_TWB, r6 + lis r4,2f@h + ori r4,r4,2f@l + tophys(r4,r4) + li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi +/* Load up the kernel context */ +2: + SYNC /* Force all PTE updates to finish */ + tlbia /* Clear all TLB entries */ + sync /* wait for tlbia/tlbie to finish */ + TLBSYNC /* ... on all CPUs */ + + /* set up the PTE pointers for the Abatron bdiGDB. + */ + tovirt(r6,r6) + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r5, 0xf0(r0) /* Must match your Abatron config file */ + tophys(r5,r5) + stw r6, 0(r5) + +/* Now turn on the MMU for real! */ + li r4,MSR_KERNEL + lis r3,start_kernel@h + ori r3,r3,start_kernel@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r4 + rfi /* enable MMU and jump to start_kernel */ + +/* Set up the initial MMU state so we can do the first level of + * kernel initialization. This maps the first 8 MBytes of memory 1:1 + * virtual to physical. Also, set the cache mode since that is defined + * by TLB entries and perform any additional mapping (like of the IMMR). + * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, + * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by + * these mappings is mapped by page tables. + */ +initial_mmu: + tlbia /* Invalidate all TLB entries */ +#ifdef CONFIG_PIN_TLB + lis r8, MI_RSV4I@h + ori r8, r8, 0x1c00 +#else + li r8, 0 +#endif + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ + +#ifdef CONFIG_PIN_TLB + lis r10, (MD_RSV4I | MD_RESETVAL)@h + ori r10, r10, 0x1c00 + mr r8, r10 +#else + lis r10, MD_RESETVAL@h +#endif +#ifndef CONFIG_8xx_COPYBACK + oris r10, r10, MD_WTDEF@h +#endif + mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ + + /* Now map the lower 8 Meg into the TLBs. For this quick hack, + * we can load the instruction and data TLB registers with the + * same values. + */ + lis r8, KERNELBASE@h /* Create vaddr for TLB */ + ori r8, r8, MI_EVALID /* Mark it valid */ + mtspr SPRN_MI_EPN, r8 + mtspr SPRN_MD_EPN, r8 + li r8, MI_PS8MEG /* Set 8M byte page */ + ori r8, r8, MI_SVALID /* Make it valid */ + mtspr SPRN_MI_TWC, r8 + mtspr SPRN_MD_TWC, r8 + li r8, MI_BOOTINIT /* Create RPN for address 0 */ + mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ + mtspr SPRN_MD_RPN, r8 + lis r8, MI_Kp@h /* Set the protection mode */ + mtspr SPRN_MI_AP, r8 + mtspr SPRN_MD_AP, r8 + + /* Map another 8 MByte at the IMMR to get the processor + * internal registers (among other things). + */ +#ifdef CONFIG_PIN_TLB + addi r10, r10, 0x0100 + mtspr SPRN_MD_CTR, r10 +#endif + mfspr r9, 638 /* Get current IMMR */ + andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ + + mr r8, r9 /* Create vaddr for TLB */ + ori r8, r8, MD_EVALID /* Mark it valid */ + mtspr SPRN_MD_EPN, r8 + li r8, MD_PS8MEG /* Set 8M byte page */ + ori r8, r8, MD_SVALID /* Make it valid */ + mtspr SPRN_MD_TWC, r8 + mr r8, r9 /* Create paddr for TLB */ + ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ + mtspr SPRN_MD_RPN, r8 + +#ifdef CONFIG_PIN_TLB + /* Map two more 8M kernel data pages. + */ + addi r10, r10, 0x0100 + mtspr SPRN_MD_CTR, r10 + + lis r8, KERNELBASE@h /* Create vaddr for TLB */ + addis r8, r8, 0x0080 /* Add 8M */ + ori r8, r8, MI_EVALID /* Mark it valid */ + mtspr SPRN_MD_EPN, r8 + li r9, MI_PS8MEG /* Set 8M byte page */ + ori r9, r9, MI_SVALID /* Make it valid */ + mtspr SPRN_MD_TWC, r9 + li r11, MI_BOOTINIT /* Create RPN for address 0 */ + addis r11, r11, 0x0080 /* Add 8M */ + mtspr SPRN_MD_RPN, r8 + + addis r8, r8, 0x0080 /* Add 8M */ + mtspr SPRN_MD_EPN, r8 + mtspr SPRN_MD_TWC, r9 + addis r11, r11, 0x0080 /* Add 8M */ + mtspr SPRN_MD_RPN, r8 +#endif + + /* Since the cache is enabled according to the information we + * just loaded into the TLB, invalidate and enable the caches here. + * We should probably check/set other modes....later. + */ + lis r8, IDC_INVALL@h + mtspr SPRN_IC_CST, r8 + mtspr SPRN_DC_CST, r8 + lis r8, IDC_ENABLE@h + mtspr SPRN_IC_CST, r8 +#ifdef CONFIG_8xx_COPYBACK + mtspr SPRN_DC_CST, r8 +#else + /* For a debug option, I left this here to easily enable + * the write through cache mode + */ + lis r8, DC_SFWT@h + mtspr SPRN_DC_CST, r8 + lis r8, IDC_ENABLE@h + mtspr SPRN_DC_CST, r8 +#endif + blr + + +/* + * Set up to use a given MMU context. + * r3 is context number, r4 is PGD pointer. + * + * We place the physical address of the new task page directory loaded + * into the MMU base register, and set the ASID compare register with + * the new "context." + */ +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is passed as second argument. + */ + lis r5, KERNELBASE@h + lwz r5, 0xf0(r5) + stw r4, 0x4(r5) +#endif + +#ifdef CONFIG_8xx_CPU6 + lis r6, cpu6_errata_word@h + ori r6, r6, cpu6_errata_word@l + tophys (r4, r4) + li r7, 0x3980 + stw r7, 12(r6) + lwz r7, 12(r6) + mtspr SPRN_M_TWB, r4 /* Update MMU base address */ + li r7, 0x3380 + stw r7, 12(r6) + lwz r7, 12(r6) + mtspr SPRN_M_CASID, r3 /* Update context */ +#else + mtspr SPRN_M_CASID,r3 /* Update context */ + tophys (r4, r4) + mtspr SPRN_M_TWB, r4 /* and pgd */ +#endif + SYNC + blr + +#ifdef CONFIG_8xx_CPU6 +/* It's here because it is unique to the 8xx. + * It is important we get called with interrupts disabled. I used to + * do that, but it appears that all code that calls this already had + * interrupt disabled. + */ + .globl set_dec_cpu6 +set_dec_cpu6: + lis r7, cpu6_errata_word@h + ori r7, r7, cpu6_errata_word@l + li r4, 0x2c00 + stw r4, 8(r7) + lwz r4, 8(r7) + mtspr 22, r3 /* Update Decrementer */ + SYNC + blr +#endif + +/* + * We put a few things here that have to be page-aligned. + * This stuff goes at the beginning of the data segment, + * which is page-aligned. + */ + .data + .globl sdata +sdata: + .globl empty_zero_page +empty_zero_page: + .space 4096 + + .globl swapper_pg_dir +swapper_pg_dir: + .space 4096 + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * Used to pass parameters into the kernel like root=/dev/sda1, etc. + */ + .globl cmd_line +cmd_line: + .space 512 + +/* Room for two PTE table poiners, usually the kernel and current user + * pointer to their respective root page table (pgdir). + */ +abatron_pteptrs: + .space 8 + +#ifdef CONFIG_8xx_CPU6 + .globl cpu6_errata_word +cpu6_errata_word: + .space 16 +#endif + diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S new file mode 100644 index 00000000000..eba5a5f8ff0 --- /dev/null +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -0,0 +1,1058 @@ +/* + * arch/ppc/kernel/head_fsl_booke.S + * + * Kernel execution entry point code. + * + * Copyright (c) 1995-1996 Gary Thomas + * Initial PowerPC version. + * Copyright (c) 1996 Cort Dougan + * Rewritten for PReP + * Copyright (c) 1996 Paul Mackerras + * Low-level exception handers, MMU support, and rewrite. + * Copyright (c) 1997 Dan Malek + * PowerPC 8xx modifications. + * Copyright (c) 1998-1999 TiVo, Inc. + * PowerPC 403GCX modifications. + * Copyright (c) 1999 Grant Erickson + * PowerPC 403GCX/405GP modifications. + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * PowerPC 403GCX/405GP modifications. + * Author: MontaVista Software, Inc. + * frank_rowand@mvista.com or source@mvista.com + * debbie_chu@mvista.com + * Copyright 2002-2004 MontaVista Software, Inc. + * PowerPC 44x support, Matt Porter + * Copyright 2004 Freescale Semiconductor, Inc + * PowerPC e500 modifications, Kumar Gala + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "head_booke.h" + +/* As with the other PowerPC ports, it is expected that when code + * execution begins here, the following registers contain valid, yet + * optional, information: + * + * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) + * r4 - Starting address of the init RAM disk + * r5 - Ending address of the init RAM disk + * r6 - Start of kernel command line string (e.g. "mem=128") + * r7 - End of kernel command line string + * + */ + .text +_GLOBAL(_stext) +_GLOBAL(_start) + /* + * Reserve a word at a fixed location to store the address + * of abatron_pteptrs + */ + nop +/* + * Save parameters we are passed + */ + mr r31,r3 + mr r30,r4 + mr r29,r5 + mr r28,r6 + mr r27,r7 + li r24,0 /* CPU number */ + +/* We try to not make any assumptions about how the boot loader + * setup or used the TLBs. We invalidate all mappings from the + * boot loader and load a single entry in TLB1[0] to map the + * first 16M of kernel memory. Any boot info passed from the + * bootloader needs to live in this first 16M. + * + * Requirement on bootloader: + * - The page we're executing in needs to reside in TLB1 and + * have IPROT=1. If not an invalidate broadcast could + * evict the entry we're currently executing in. + * + * r3 = Index of TLB1 were executing in + * r4 = Current MSR[IS] + * r5 = Index of TLB1 temp mapping + * + * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] + * if needed + */ + +/* 1. Find the index of the entry we're executing in */ + bl invstr /* Find our address */ +invstr: mflr r6 /* Make it accessible */ + mfmsr r7 + rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ + mfspr r7, SPRN_PID0 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ +#ifndef CONFIG_E200 + mfspr r7,SPRN_MAS1 + andis. r7,r7,MAS1_VALID@h + bne match_TLB + mfspr r7,SPRN_PID1 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ + mfspr r7,SPRN_MAS1 + andis. r7,r7,MAS1_VALID@h + bne match_TLB + mfspr r7, SPRN_PID2 + slwi r7,r7,16 + or r7,r7,r4 + mtspr SPRN_MAS6,r7 + tlbsx 0,r6 /* Fall through, we had to match */ +#endif +match_TLB: + mfspr r7,SPRN_MAS0 + rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ + + mfspr r7,SPRN_MAS1 /* Insure IPROT set */ + oris r7,r7,MAS1_IPROT@h + mtspr SPRN_MAS1,r7 + tlbwe + +/* 2. Invalidate all entries except the entry we're executing in */ + mfspr r9,SPRN_TLB1CFG + andi. r9,r9,0xfff + li r6,0 /* Set Entry counter to 0 */ +1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ + mtspr SPRN_MAS0,r7 + tlbre + mfspr r7,SPRN_MAS1 + rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ + cmpw r3,r6 + beq skpinv /* Dont update the current execution TLB */ + mtspr SPRN_MAS1,r7 + tlbwe + isync +skpinv: addi r6,r6,1 /* Increment */ + cmpw r6,r9 /* Are we done? */ + bne 1b /* If not, repeat */ + + /* Invalidate TLB0 */ + li r6,0x04 + tlbivax 0,r6 +#ifdef CONFIG_SMP + tlbsync +#endif + /* Invalidate TLB1 */ + li r6,0x0c + tlbivax 0,r6 +#ifdef CONFIG_SMP + tlbsync +#endif + msync + +/* 3. Setup a temp mapping and jump to it */ + andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ + addi r5, r5, 0x1 + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ + mtspr SPRN_MAS0,r7 + tlbre + + /* Just modify the entry ID and EPN for the temp mapping */ + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ + mtspr SPRN_MAS0,r7 + xori r6,r4,1 /* Setup TMP mapping in the other Address space */ + slwi r6,r6,12 + oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h + ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l + mtspr SPRN_MAS1,r6 + mfspr r6,SPRN_MAS2 + li r7,0 /* temp EPN = 0 */ + rlwimi r7,r6,0,20,31 + mtspr SPRN_MAS2,r7 + tlbwe + + xori r6,r4,1 + slwi r6,r6,5 /* setup new context with other address space */ + bl 1f /* Find our address */ +1: mflr r9 + rlwimi r7,r9,0,20,31 + addi r7,r7,24 + mtspr SPRN_SRR0,r7 + mtspr SPRN_SRR1,r6 + rfi + +/* 4. Clear out PIDs & Search info */ + li r6,0 + mtspr SPRN_PID0,r6 +#ifndef CONFIG_E200 + mtspr SPRN_PID1,r6 + mtspr SPRN_PID2,r6 +#endif + mtspr SPRN_MAS6,r6 + +/* 5. Invalidate mapping we started in */ + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ + mtspr SPRN_MAS0,r7 + tlbre + li r6,0 + mtspr SPRN_MAS1,r6 + tlbwe + /* Invalidate TLB1 */ + li r9,0x0c + tlbivax 0,r9 +#ifdef CONFIG_SMP + tlbsync +#endif + msync + +/* 6. Setup KERNELBASE mapping in TLB1[0] */ + lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ + mtspr SPRN_MAS0,r6 + lis r6,(MAS1_VALID|MAS1_IPROT)@h + ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l + mtspr SPRN_MAS1,r6 + li r7,0 + lis r6,KERNELBASE@h + ori r6,r6,KERNELBASE@l + rlwimi r6,r7,0,20,31 + mtspr SPRN_MAS2,r6 + li r7,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r7 + tlbwe + +/* 7. Jump to KERNELBASE mapping */ + lis r7,MSR_KERNEL@h + ori r7,r7,MSR_KERNEL@l + bl 1f /* Find our address */ +1: mflr r9 + rlwimi r6,r9,0,20,31 + addi r6,r6,24 + mtspr SPRN_SRR0,r6 + mtspr SPRN_SRR1,r7 + rfi /* start execution out of TLB1[0] entry */ + +/* 8. Clear out the temp mapping */ + lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ + rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ + mtspr SPRN_MAS0,r7 + tlbre + mtspr SPRN_MAS1,r8 + tlbwe + /* Invalidate TLB1 */ + li r9,0x0c + tlbivax 0,r9 +#ifdef CONFIG_SMP + tlbsync +#endif + msync + + /* Establish the interrupt vector offsets */ + SET_IVOR(0, CriticalInput); + SET_IVOR(1, MachineCheck); + SET_IVOR(2, DataStorage); + SET_IVOR(3, InstructionStorage); + SET_IVOR(4, ExternalInput); + SET_IVOR(5, Alignment); + SET_IVOR(6, Program); + SET_IVOR(7, FloatingPointUnavailable); + SET_IVOR(8, SystemCall); + SET_IVOR(9, AuxillaryProcessorUnavailable); + SET_IVOR(10, Decrementer); + SET_IVOR(11, FixedIntervalTimer); + SET_IVOR(12, WatchdogTimer); + SET_IVOR(13, DataTLBError); + SET_IVOR(14, InstructionTLBError); + SET_IVOR(15, Debug); + SET_IVOR(32, SPEUnavailable); + SET_IVOR(33, SPEFloatingPointData); + SET_IVOR(34, SPEFloatingPointRound); +#ifndef CONFIG_E200 + SET_IVOR(35, PerformanceMonitor); +#endif + + /* Establish the interrupt vector base */ + lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ + mtspr SPRN_IVPR,r4 + + /* Setup the defaults for TLB entries */ + li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l +#ifdef CONFIG_E200 + oris r2,r2,MAS4_TLBSELD(1)@h +#endif + mtspr SPRN_MAS4, r2 + +#if 0 + /* Enable DOZE */ + mfspr r2,SPRN_HID0 + oris r2,r2,HID0_DOZE@h + mtspr SPRN_HID0, r2 +#endif +#ifdef CONFIG_E200 + /* enable dedicated debug exception handling resources (Debug APU) */ + mfspr r2,SPRN_HID0 + ori r2,r2,HID0_DAPUEN@l + mtspr SPRN_HID0,r2 +#endif + +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + lis r2,DBCR0_IDM@h + mtspr SPRN_DBCR0,r2 + /* clear any residual debug events */ + li r2,-1 + mtspr SPRN_DBSR,r2 +#endif + + /* + * This is where the main kernel code starts. + */ + + /* ptr to current */ + lis r2,init_task@h + ori r2,r2,init_task@l + + /* ptr to current thread */ + addi r4,r2,THREAD /* init task's THREAD */ + mtspr SPRN_SPRG3,r4 + + /* stack */ + lis r1,init_thread_union@h + ori r1,r1,init_thread_union@l + li r0,0 + stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) + + bl early_init + + mfspr r3,SPRN_TLB1CFG + andi. r3,r3,0xfff + lis r4,num_tlbcam_entries@ha + stw r3,num_tlbcam_entries@l(r4) +/* + * Decide what sort of machine this is and initialize the MMU. + */ + mr r3,r31 + mr r4,r30 + mr r5,r29 + mr r6,r28 + mr r7,r27 + bl machine_init + bl MMU_init + + /* Setup PTE pointers for the Abatron bdiGDB */ + lis r6, swapper_pg_dir@h + ori r6, r6, swapper_pg_dir@l + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + lis r4, KERNELBASE@h + ori r4, r4, KERNELBASE@l + stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ + stw r6, 0(r5) + + /* Let's move on */ + lis r4,start_kernel@h + ori r4,r4,start_kernel@l + lis r3,MSR_KERNEL@h + ori r3,r3,MSR_KERNEL@l + mtspr SPRN_SRR0,r4 + mtspr SPRN_SRR1,r3 + rfi /* change context and jump to start_kernel */ + +/* Macros to hide the PTE size differences + * + * FIND_PTE -- walks the page tables given EA & pgdir pointer + * r10 -- EA of fault + * r11 -- PGDIR pointer + * r12 -- free + * label 2: is the bailout case + * + * if we find the pte (fall through): + * r11 is low pte word + * r12 is pointer to the pte + */ +#ifdef CONFIG_PTE_64BIT +#define PTE_FLAGS_OFFSET 4 +#define FIND_PTE \ + rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ + lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ + rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ + beq 2f; /* Bail if no table */ \ + rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ + lwz r11, 4(r12); /* Get pte entry */ +#else +#define PTE_FLAGS_OFFSET 0 +#define FIND_PTE \ + rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ + lwz r11, 0(r11); /* Get L1 entry */ \ + rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ + beq 2f; /* Bail if no table */ \ + rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ + lwz r11, 0(r12); /* Get Linux PTE */ +#endif + +/* + * Interrupt vector entry code + * + * The Book E MMUs are always on so we don't need to handle + * interrupts in real mode as with previous PPC processors. In + * this case we handle interrupts in the kernel virtual address + * space. + * + * Interrupt vectors are dynamically placed relative to the + * interrupt prefix as determined by the address of interrupt_base. + * The interrupt vectors offsets are programmed using the labels + * for each interrupt vector entry. + * + * Interrupt vectors must be aligned on a 16 byte boundary. + * We align on a 32 byte cache line boundary for good measure. + */ + +interrupt_base: + /* Critical Input Interrupt */ + CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) + + /* Machine Check Interrupt */ +#ifdef CONFIG_E200 + /* no RFMCI, MCSRRs on E200 */ + CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) +#else + MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) +#endif + + /* Data Storage Interrupt */ + START_EXCEPTION(DataStorage) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + + /* + * Check if it was a store fault, if not then bail + * because a user tried to access a kernel or + * read-protected page. Otherwise, get the + * offending address and handle it. + */ + mfspr r10, SPRN_ESR + andis. r10, r10, ESR_ST@h + beq 2f + + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + ori r11, r11, TASK_SIZE@l + cmplw 0, r10, r11 + bge 2f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) +4: + FIND_PTE + + /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */ + andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE + cmpwi 0, r13, _PAGE_RW|_PAGE_USER + bne 2f /* Bail if not */ + + /* Update 'changed'. */ + ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE + stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */ + + /* MAS2 not updated as the entry does exist in the tlb, this + fault taken to detect state transition (eg: COW -> DIRTY) + */ + andi. r11, r11, _PAGE_HWEXEC + rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */ + ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */ + + /* update search PID in MAS6, AS = 0 */ + mfspr r12, SPRN_PID0 + slwi r12, r12, 16 + mtspr SPRN_MAS6, r12 + + /* find the TLB index that caused the fault. It has to be here. */ + tlbsx 0, r10 + + /* only update the perm bits, assume the RPN is fine */ + mfspr r12, SPRN_MAS3 + rlwimi r12, r11, 0, 20, 31 + mtspr SPRN_MAS3,r12 + tlbwe + + /* Done...restore registers and get out of here. */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + rfi /* Force context change */ + +2: + /* + * The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b data_access + + /* Instruction Storage Interrupt */ + INSTRUCTION_STORAGE_EXCEPTION + + /* External Input Interrupt */ + EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) + + /* Alignment Interrupt */ + ALIGNMENT_EXCEPTION + + /* Program Interrupt */ + PROGRAM_EXCEPTION + + /* Floating Point Unavailable Interrupt */ +#ifdef CONFIG_PPC_FPU + FP_UNAVAILABLE_EXCEPTION +#else +#ifdef CONFIG_E200 + /* E200 treats 'normal' floating point instructions as FP Unavail exception */ + EXCEPTION(0x0800, FloatingPointUnavailable, ProgramCheckException, EXC_XFER_EE) +#else + EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) +#endif +#endif + + /* System Call Interrupt */ + START_EXCEPTION(SystemCall) + NORMAL_EXCEPTION_PROLOG + EXC_XFER_EE_LITE(0x0c00, DoSyscall) + + /* Auxillary Processor Unavailable Interrupt */ + EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE) + + /* Decrementer Interrupt */ + DECREMENTER_EXCEPTION + + /* Fixed Internal Timer Interrupt */ + /* TODO: Add FIT support */ + EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE) + + /* Watchdog Timer Interrupt */ +#ifdef CONFIG_BOOKE_WDT + CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) +#else + CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException) +#endif + + /* Data TLB Error Interrupt */ + START_EXCEPTION(DataTLBError) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + mfspr r10, SPRN_DEAR /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + ori r11, r11, TASK_SIZE@l + cmplw 5, r10, r11 + blt 5, 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + + mfspr r12,SPRN_MAS1 /* Set TID to 0 */ + rlwinm r12,r12,0,16,1 + mtspr SPRN_MAS1,r12 + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) + +4: + FIND_PTE + andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + +#ifdef CONFIG_PTE_64BIT + lwz r13, 0(r12) +#endif + ori r11, r11, _PAGE_ACCESSED + stw r11, PTE_FLAGS_OFFSET(r12) + + /* Jump to common tlb load */ + b finish_tlb_load +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b data_access + + /* Instruction TLB Error Interrupt */ + /* + * Nearly the same as above, except we get our + * information from different registers and bailout + * to a different point. + */ + START_EXCEPTION(InstructionTLBError) + mtspr SPRN_SPRG0, r10 /* Save some working registers */ + mtspr SPRN_SPRG1, r11 + mtspr SPRN_SPRG4W, r12 + mtspr SPRN_SPRG5W, r13 + mfcr r11 + mtspr SPRN_SPRG7W, r11 + mfspr r10, SPRN_SRR0 /* Get faulting address */ + + /* If we are faulting a kernel address, we have to use the + * kernel page tables. + */ + lis r11, TASK_SIZE@h + ori r11, r11, TASK_SIZE@l + cmplw 5, r10, r11 + blt 5, 3f + lis r11, swapper_pg_dir@h + ori r11, r11, swapper_pg_dir@l + + mfspr r12,SPRN_MAS1 /* Set TID to 0 */ + rlwinm r12,r12,0,16,1 + mtspr SPRN_MAS1,r12 + + b 4f + + /* Get the PGD for the current thread */ +3: + mfspr r11,SPRN_SPRG3 + lwz r11,PGDIR(r11) + +4: + FIND_PTE + andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ + beq 2f /* Bail if not present */ + +#ifdef CONFIG_PTE_64BIT + lwz r13, 0(r12) +#endif + ori r11, r11, _PAGE_ACCESSED + stw r11, PTE_FLAGS_OFFSET(r12) + + /* Jump to common TLB load point */ + b finish_tlb_load + +2: + /* The bailout. Restore registers to pre-exception conditions + * and call the heavyweights to help us out. + */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + b InstructionStorage + +#ifdef CONFIG_SPE + /* SPE Unavailable */ + START_EXCEPTION(SPEUnavailable) + NORMAL_EXCEPTION_PROLOG + bne load_up_spe + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE_LITE(0x2010, KernelSPE) +#else + EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE) +#endif /* CONFIG_SPE */ + + /* SPE Floating Point Data */ +#ifdef CONFIG_SPE + EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); +#else + EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE) +#endif /* CONFIG_SPE */ + + /* SPE Floating Point Round */ + EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE) + + /* Performance Monitor */ + EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD) + + + /* Debug Interrupt */ + DEBUG_EXCEPTION + +/* + * Local functions + */ + + /* + * Data TLB exceptions will bail out to this point + * if they can't resolve the lightweight TLB fault. + */ +data_access: + NORMAL_EXCEPTION_PROLOG + mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ + stw r5,_ESR(r11) + mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ + andis. r10,r5,(ESR_ILK|ESR_DLK)@h + bne 1f + EXC_XFER_EE_LITE(0x0300, handle_page_fault) +1: + addi r3,r1,STACK_FRAME_OVERHEAD + EXC_XFER_EE_LITE(0x0300, CacheLockingException) + +/* + + * Both the instruction and data TLB miss get to this + * point to load the TLB. + * r10 - EA of fault + * r11 - TLB (info from Linux PTE) + * r12, r13 - available to use + * CR5 - results of addr < TASK_SIZE + * MAS0, MAS1 - loaded with proper value when we get here + * MAS2, MAS3 - will need additional info from Linux PTE + * Upon exit, we reload everything and RFI. + */ +finish_tlb_load: + /* + * We set execute, because we don't have the granularity to + * properly set this at the page level (Linux problem). + * Many of these bits are software only. Bits we don't set + * here we (properly should) assume have the appropriate value. + */ + + mfspr r12, SPRN_MAS2 +#ifdef CONFIG_PTE_64BIT + rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */ +#else + rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ +#endif + mtspr SPRN_MAS2, r12 + + bge 5, 1f + + /* is user addr */ + andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC) + andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ + srwi r10, r12, 1 + or r12, r12, r10 /* Copy user perms into supervisor */ + iseleq r12, 0, r12 + b 2f + + /* is kernel addr */ +1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */ + ori r12, r12, (MAS3_SX | MAS3_SR) + +#ifdef CONFIG_PTE_64BIT +2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ + rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ + mtspr SPRN_MAS3, r12 +BEGIN_FTR_SECTION + srwi r10, r13, 8 /* grab RPN[8:31] */ + mtspr SPRN_MAS7, r10 +END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) +#else +2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ + mtspr SPRN_MAS3, r11 +#endif +#ifdef CONFIG_E200 + /* Round robin TLB1 entries assignment */ + mfspr r12, SPRN_MAS0 + + /* Extract TLB1CFG(NENTRY) */ + mfspr r11, SPRN_TLB1CFG + andi. r11, r11, 0xfff + + /* Extract MAS0(NV) */ + andi. r13, r12, 0xfff + addi r13, r13, 1 + cmpw 0, r13, r11 + addi r12, r12, 1 + + /* check if we need to wrap */ + blt 7f + + /* wrap back to first free tlbcam entry */ + lis r13, tlbcam_index@ha + lwz r13, tlbcam_index@l(r13) + rlwimi r12, r13, 0, 20, 31 +7: + mtspr SPRN_MAS0,r12 +#endif /* CONFIG_E200 */ + + tlbwe + + /* Done...restore registers and get out of here. */ + mfspr r11, SPRN_SPRG7R + mtcr r11 + mfspr r13, SPRN_SPRG5R + mfspr r12, SPRN_SPRG4R + mfspr r11, SPRN_SPRG1 + mfspr r10, SPRN_SPRG0 + rfi /* Force context change */ + +#ifdef CONFIG_SPE +/* Note that the SPE support is closely modeled after the AltiVec + * support. Changes to one are likely to be applicable to the + * other! */ +load_up_spe: +/* + * Disable SPE for the task which had SPE previously, + * and save its SPE registers in its thread_struct. + * Enables SPE for use in the kernel on return. + * On SMP we know the SPE units are free, since we give it up every + * switch. -- Kumar + */ + mfmsr r5 + oris r5,r5,MSR_SPE@h + mtmsr r5 /* enable use of SPE now */ + isync +/* + * For SMP, we don't do lazy SPE switching because it just gets too + * horrendously complex, especially when a task switches from one CPU + * to another. Instead we call giveup_spe in switch_to. + */ +#ifndef CONFIG_SMP + lis r3,last_task_used_spe@ha + lwz r4,last_task_used_spe@l(r3) + cmpi 0,r4,0 + beq 1f + addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ + SAVE_32EVRS(0,r10,r4) + evxor evr10, evr10, evr10 /* clear out evr10 */ + evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ + li r5,THREAD_ACC + evstddx evr10, r4, r5 /* save off accumulator */ + lwz r5,PT_REGS(r4) + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r10,MSR_SPE@h + andc r4,r4,r10 /* disable SPE for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#endif /* CONFIG_SMP */ + /* enable use of SPE after return */ + oris r9,r9,MSR_SPE@h + mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ + li r4,1 + li r10,THREAD_ACC + stw r4,THREAD_USED_SPE(r5) + evlddx evr4,r10,r5 + evmra evr4,evr4 + REST_32EVRS(0,r10,r5) +#ifndef CONFIG_SMP + subi r4,r5,THREAD + stw r4,last_task_used_spe@l(r3) +#endif /* CONFIG_SMP */ + /* restore registers and return */ +2: REST_4GPRS(3, r11) + lwz r10,_CCR(r11) + REST_GPR(1, r11) + mtcr r10 + lwz r10,_LINK(r11) + mtlr r10 + REST_GPR(10, r11) + mtspr SPRN_SRR1,r9 + mtspr SPRN_SRR0,r12 + REST_GPR(9, r11) + REST_GPR(12, r11) + lwz r11,GPR11(r11) + SYNC + rfi + +/* + * SPE unavailable trap from kernel - print a message, but let + * the task use SPE in the kernel until it returns to user mode. + */ +KernelSPE: + lwz r3,_MSR(r1) + oris r3,r3,MSR_SPE@h + stw r3,_MSR(r1) /* enable use of SPE after return */ + lis r3,87f@h + ori r3,r3,87f@l + mr r4,r2 /* current */ + lwz r5,_NIP(r1) + bl printk + b ret_from_except +87: .string "SPE used in kernel (task=%p, pc=%x) \n" + .align 4,0 + +#endif /* CONFIG_SPE */ + +/* + * Global functions + */ + +/* + * extern void loadcam_entry(unsigned int index) + * + * Load TLBCAM[index] entry in to the L2 CAM MMU + */ +_GLOBAL(loadcam_entry) + lis r4,TLBCAM@ha + addi r4,r4,TLBCAM@l + mulli r5,r3,20 + add r3,r5,r4 + lwz r4,0(r3) + mtspr SPRN_MAS0,r4 + lwz r4,4(r3) + mtspr SPRN_MAS1,r4 + lwz r4,8(r3) + mtspr SPRN_MAS2,r4 + lwz r4,12(r3) + mtspr SPRN_MAS3,r4 + tlbwe + isync + blr + +/* + * extern void giveup_altivec(struct task_struct *prev) + * + * The e500 core does not have an AltiVec unit. + */ +_GLOBAL(giveup_altivec) + blr + +#ifdef CONFIG_SPE +/* + * extern void giveup_spe(struct task_struct *prev) + * + */ +_GLOBAL(giveup_spe) + mfmsr r5 + oris r5,r5,MSR_SPE@h + SYNC + mtmsr r5 /* enable use of SPE now */ + isync + cmpi 0,r3,0 + beqlr- /* if no previous owner, done */ + addi r3,r3,THREAD /* want THREAD of task */ + lwz r5,PT_REGS(r3) + cmpi 0,r5,0 + SAVE_32EVRS(0, r4, r3) + evxor evr6, evr6, evr6 /* clear out evr6 */ + evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ + li r4,THREAD_ACC + evstddx evr6, r4, r3 /* save off accumulator */ + mfspr r6,SPRN_SPEFSCR + stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ + beq 1f + lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) + lis r3,MSR_SPE@h + andc r4,r4,r3 /* disable SPE for previous task */ + stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) +1: +#ifndef CONFIG_SMP + li r5,0 + lis r4,last_task_used_spe@ha + stw r5,last_task_used_spe@l(r4) +#endif /* CONFIG_SMP */ + blr +#endif /* CONFIG_SPE */ + +/* + * extern void giveup_fpu(struct task_struct *prev) + * + * Not all FSL Book-E cores have an FPU + */ +#ifndef CONFIG_PPC_FPU +_GLOBAL(giveup_fpu) + blr +#endif + +/* + * extern void abort(void) + * + * At present, this routine just applies a system reset. + */ +_GLOBAL(abort) + li r13,0 + mtspr SPRN_DBCR0,r13 /* disable all debug events */ + mfmsr r13 + ori r13,r13,MSR_DE@l /* Enable Debug Events */ + mtmsr r13 + mfspr r13,SPRN_DBCR0 + lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h + mtspr SPRN_DBCR0,r13 + +_GLOBAL(set_context) + +#ifdef CONFIG_BDI_SWITCH + /* Context switch the PTE pointer for the Abatron BDI2000. + * The PGDIR is the second parameter. + */ + lis r5, abatron_pteptrs@h + ori r5, r5, abatron_pteptrs@l + stw r4, 0x4(r5) +#endif + mtspr SPRN_PID,r3 + isync /* Force context change */ + blr + +/* + * We put a few things here that have to be page-aligned. This stuff + * goes at the beginning of the data segment, which is page-aligned. + */ + .data +_GLOBAL(sdata) +_GLOBAL(empty_zero_page) + .space 4096 +_GLOBAL(swapper_pg_dir) + .space 4096 + +/* Reserved 4k for the critical exception stack & 4k for the machine + * check stack per CPU for kernel mode exceptions */ + .section .bss + .align 12 +exception_stack_bottom: + .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS +_GLOBAL(exception_stack_top) + +/* + * This space gets a copy of optional info passed to us by the bootstrap + * which is used to pass parameters into the kernel like root=/dev/sda1, etc. + */ +_GLOBAL(cmd_line) + .space 512 + +/* + * Room for two PTE pointers, usually the kernel and current user pointers + * to their respective root page table. + */ +abatron_pteptrs: + .space 8 + diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S new file mode 100644 index 00000000000..1a2194cf682 --- /dev/null +++ b/arch/powerpc/kernel/idle_6xx.S @@ -0,0 +1,233 @@ +/* + * This file contains the power_save function for 6xx & 7xxx CPUs + * rewritten in assembler + * + * Warning ! This code assumes that if your machine has a 750fx + * it will have PLL 1 set to low speed mode (used during NAP/DOZE). + * if this is not the case some additional changes will have to + * be done to check a runtime var (a bit like powersave-nap) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG + + .text + +/* + * Init idle, called at early CPU setup time from head.S for each CPU + * Make sure no rest of NAP mode remains in HID0, save default + * values for some CPU specific registers. Called with r24 + * containing CPU number and r3 reloc offset + */ +_GLOBAL(init_idle_6xx) +BEGIN_FTR_SECTION + mfspr r4,SPRN_HID0 + rlwinm r4,r4,0,10,8 /* Clear NAP */ + mtspr SPRN_HID0, r4 + b 1f +END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) + blr +1: + slwi r5,r24,2 + add r5,r5,r3 +BEGIN_FTR_SECTION + mfspr r4,SPRN_MSSCR0 + addis r6,r5, nap_save_msscr0@ha + stw r4,nap_save_msscr0@l(r6) +END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) +BEGIN_FTR_SECTION + mfspr r4,SPRN_HID1 + addis r6,r5,nap_save_hid1@ha + stw r4,nap_save_hid1@l(r6) +END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) + blr + +/* + * Here is the power_save_6xx function. This could eventually be + * split into several functions & changing the function pointer + * depending on the various features. + */ +_GLOBAL(ppc6xx_idle) + /* Check if we can nap or doze, put HID0 mask in r3 + */ + lis r3, 0 +BEGIN_FTR_SECTION + lis r3,HID0_DOZE@h +END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) +BEGIN_FTR_SECTION + /* We must dynamically check for the NAP feature as it + * can be cleared by CPU init after the fixups are done + */ + lis r4,cur_cpu_spec@ha + lwz r4,cur_cpu_spec@l(r4) + lwz r4,CPU_SPEC_FEATURES(r4) + andi. r0,r4,CPU_FTR_CAN_NAP + beq 1f + /* Now check if user or arch enabled NAP mode */ + lis r4,powersave_nap@ha + lwz r4,powersave_nap@l(r4) + cmpwi 0,r4,0 + beq 1f + lis r3,HID0_NAP@h +1: +END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) + cmpwi 0,r3,0 + beqlr + + /* Clear MSR:EE */ + mfmsr r7 + rlwinm r0,r7,0,17,15 + mtmsr r0 + + /* Check current_thread_info()->flags */ + rlwinm r4,r1,0,0,18 + lwz r4,TI_FLAGS(r4) + andi. r0,r4,_TIF_NEED_RESCHED + beq 1f + mtmsr r7 /* out of line this ? */ + blr +1: + /* Some pre-nap cleanups needed on some CPUs */ + andis. r0,r3,HID0_NAP@h + beq 2f +BEGIN_FTR_SECTION + /* Disable L2 prefetch on some 745x and try to ensure + * L2 prefetch engines are idle. As explained by errata + * text, we can't be sure they are, we just hope very hard + * that well be enough (sic !). At least I noticed Apple + * doesn't even bother doing the dcbf's here... + */ + mfspr r4,SPRN_MSSCR0 + rlwinm r4,r4,0,0,29 + sync + mtspr SPRN_MSSCR0,r4 + sync + isync + lis r4,KERNELBASE@h + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 +END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) +#ifdef DEBUG + lis r6,nap_enter_count@ha + lwz r4,nap_enter_count@l(r6) + addi r4,r4,1 + stw r4,nap_enter_count@l(r6) +#endif +2: +BEGIN_FTR_SECTION + /* Go to low speed mode on some 750FX */ + lis r4,powersave_lowspeed@ha + lwz r4,powersave_lowspeed@l(r4) + cmpwi 0,r4,0 + beq 1f + mfspr r4,SPRN_HID1 + oris r4,r4,0x0001 + mtspr SPRN_HID1,r4 +1: +END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) + + /* Go to NAP or DOZE now */ + mfspr r4,SPRN_HID0 + lis r5,(HID0_NAP|HID0_SLEEP)@h +BEGIN_FTR_SECTION + oris r5,r5,HID0_DOZE@h +END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) + andc r4,r4,r5 + or r4,r4,r3 +BEGIN_FTR_SECTION + oris r4,r4,HID0_DPM@h /* that should be done once for all */ +END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM) + mtspr SPRN_HID0,r4 +BEGIN_FTR_SECTION + DSSALL + sync +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) + ori r7,r7,MSR_EE /* Could be ommited (already set) */ + oris r7,r7,MSR_POW@h + sync + isync + mtmsr r7 + isync + sync + blr + +/* + * Return from NAP/DOZE mode, restore some CPU specific registers, + * we are called with DR/IR still off and r2 containing physical + * address of current. + */ +_GLOBAL(power_save_6xx_restore) + mfspr r11,SPRN_HID0 + rlwinm. r11,r11,0,10,8 /* Clear NAP & copy NAP bit !state to cr1 EQ */ + cror 4*cr1+eq,4*cr0+eq,4*cr0+eq +BEGIN_FTR_SECTION + rlwinm r11,r11,0,9,7 /* Clear DOZE */ +END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) + mtspr SPRN_HID0, r11 + +#ifdef DEBUG + beq cr1,1f + lis r11,(nap_return_count-KERNELBASE)@ha + lwz r9,nap_return_count@l(r11) + addi r9,r9,1 + stw r9,nap_return_count@l(r11) +1: +#endif + + rlwinm r9,r1,0,0,18 + tophys(r9,r9) + lwz r11,TI_CPU(r9) + slwi r11,r11,2 + /* Todo make sure all these are in the same page + * and load r22 (@ha part + CPU offset) only once + */ +BEGIN_FTR_SECTION + beq cr1,1f + addis r9,r11,(nap_save_msscr0-KERNELBASE)@ha + lwz r9,nap_save_msscr0@l(r9) + mtspr SPRN_MSSCR0, r9 + sync + isync +1: +END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR) +BEGIN_FTR_SECTION + addis r9,r11,(nap_save_hid1-KERNELBASE)@ha + lwz r9,nap_save_hid1@l(r9) + mtspr SPRN_HID1, r9 +END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX) + b transfer_to_handler_cont + + .data + +_GLOBAL(nap_save_msscr0) + .space 4*NR_CPUS + +_GLOBAL(nap_save_hid1) + .space 4*NR_CPUS + +_GLOBAL(powersave_nap) + .long 0 +_GLOBAL(powersave_lowspeed) + .long 0 + +#ifdef DEBUG +_GLOBAL(nap_enter_count) + .space 4 +_GLOBAL(nap_return_count) + .space 4 +#endif diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c new file mode 100644 index 00000000000..f5a9d2a84fa --- /dev/null +++ b/arch/powerpc/kernel/process.c @@ -0,0 +1,724 @@ +/* + * arch/ppc/kernel/process.c + * + * Derived from "arch/i386/kernel/process.c" + * Copyright (C) 1995 Linus Torvalds + * + * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and + * Paul Mackerras (paulus@cs.anu.edu.au) + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +extern unsigned long _get_SP(void); + +#ifndef CONFIG_SMP +struct task_struct *last_task_used_math = NULL; +struct task_struct *last_task_used_altivec = NULL; +struct task_struct *last_task_used_spe = NULL; +#endif + +static struct fs_struct init_fs = INIT_FS; +static struct files_struct init_files = INIT_FILES; +static struct signal_struct init_signals = INIT_SIGNALS(init_signals); +static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); +struct mm_struct init_mm = INIT_MM(init_mm); +EXPORT_SYMBOL(init_mm); + +/* this is 8kB-aligned so we can get to the thread_info struct + at the base of it from the stack pointer with 1 integer instruction. */ +union thread_union init_thread_union + __attribute__((__section__(".data.init_task"))) = +{ INIT_THREAD_INFO(init_task) }; + +/* initial task structure */ +struct task_struct init_task = INIT_TASK(init_task); +EXPORT_SYMBOL(init_task); + +/* only used to get secondary processor up */ +struct task_struct *current_set[NR_CPUS] = {&init_task, }; + +/* + * Make sure the floating-point register state in the + * the thread_struct is up to date for task tsk. + */ +void flush_fp_to_thread(struct task_struct *tsk) +{ + if (tsk->thread.regs) { + /* + * We need to disable preemption here because if we didn't, + * another process could get scheduled after the regs->msr + * test but before we have finished saving the FP registers + * to the thread_struct. That process could take over the + * FPU, and then when we get scheduled again we would store + * bogus values for the remaining FP registers. + */ + preempt_disable(); + if (tsk->thread.regs->msr & MSR_FP) { +#ifdef CONFIG_SMP + /* + * This should only ever be called for current or + * for a stopped child process. Since we save away + * the FP register state on context switch on SMP, + * there is something wrong if a stopped child appears + * to still have its FP state in the CPU registers. + */ + BUG_ON(tsk != current); +#endif + giveup_fpu(current); + } + preempt_enable(); + } +} + +void enable_kernel_fp(void) +{ + WARN_ON(preemptible()); + +#ifdef CONFIG_SMP + if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) + giveup_fpu(current); + else + giveup_fpu(NULL); /* just enables FP for kernel */ +#else + giveup_fpu(last_task_used_math); +#endif /* CONFIG_SMP */ +} +EXPORT_SYMBOL(enable_kernel_fp); + +int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs) +{ + if (!tsk->thread.regs) + return 0; + flush_fp_to_thread(current); + + memcpy(fpregs, &tsk->thread.fpr[0], sizeof(*fpregs)); + + return 1; +} + +#ifdef CONFIG_ALTIVEC +void enable_kernel_altivec(void) +{ + WARN_ON(preemptible()); + +#ifdef CONFIG_SMP + if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) + giveup_altivec(current); + else + giveup_altivec(NULL); /* just enable AltiVec for kernel - force */ +#else + giveup_altivec(last_task_used_altivec); +#endif /* CONFIG_SMP */ +} +EXPORT_SYMBOL(enable_kernel_altivec); + +/* + * Make sure the VMX/Altivec register state in the + * the thread_struct is up to date for task tsk. + */ +void flush_altivec_to_thread(struct task_struct *tsk) +{ + if (tsk->thread.regs) { + preempt_disable(); + if (tsk->thread.regs->msr & MSR_VEC) { +#ifdef CONFIG_SMP + BUG_ON(tsk != current); +#endif + giveup_altivec(current); + } + preempt_enable(); + } +} + +int dump_task_altivec(struct pt_regs *regs, elf_vrregset_t *vrregs) +{ + flush_altivec_to_thread(current); + memcpy(vrregs, ¤t->thread.vr[0], sizeof(*vrregs)); + return 1; +} +#endif /* CONFIG_ALTIVEC */ + +#ifdef CONFIG_SPE + +void enable_kernel_spe(void) +{ + WARN_ON(preemptible()); + +#ifdef CONFIG_SMP + if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) + giveup_spe(current); + else + giveup_spe(NULL); /* just enable SPE for kernel - force */ +#else + giveup_spe(last_task_used_spe); +#endif /* __SMP __ */ +} +EXPORT_SYMBOL(enable_kernel_spe); + +void flush_spe_to_thread(struct task_struct *tsk) +{ + if (tsk->thread.regs) { + preempt_disable(); + if (tsk->thread.regs->msr & MSR_SPE) { +#ifdef CONFIG_SMP + BUG_ON(tsk != current); +#endif + giveup_spe(current); + } + preempt_enable(); + } +} + +int dump_spe(struct pt_regs *regs, elf_vrregset_t *evrregs) +{ + flush_spe_to_thread(current); + /* We copy u32 evr[32] + u64 acc + u32 spefscr -> 35 */ + memcpy(evrregs, ¤t->thread.evr[0], sizeof(u32) * 35); + return 1; +} +#endif /* CONFIG_SPE */ + +static void set_dabr_spr(unsigned long val) +{ + mtspr(SPRN_DABR, val); +} + +int set_dabr(unsigned long dabr) +{ + int ret = 0; + +#ifdef CONFIG_PPC64 + if (firmware_has_feature(FW_FEATURE_XDABR)) { + /* We want to catch accesses from kernel and userspace */ + unsigned long flags = H_DABRX_KERNEL|H_DABRX_USER; + ret = plpar_set_xdabr(dabr, flags); + } else if (firmware_has_feature(FW_FEATURE_DABR)) { + ret = plpar_set_dabr(dabr); + } else +#endif + set_dabr_spr(dabr); + + return ret; +} + +static DEFINE_PER_CPU(unsigned long, current_dabr); + +struct task_struct *__switch_to(struct task_struct *prev, + struct task_struct *new) +{ + struct thread_struct *new_thread, *old_thread; + unsigned long flags; + struct task_struct *last; + +#ifdef CONFIG_SMP + /* avoid complexity of lazy save/restore of fpu + * by just saving it every time we switch out if + * this task used the fpu during the last quantum. + * + * If it tries to use the fpu again, it'll trap and + * reload its fp regs. So we don't have to do a restore + * every switch, just a save. + * -- Cort + */ + if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) + giveup_fpu(prev); +#ifdef CONFIG_ALTIVEC + /* + * If the previous thread used altivec in the last quantum + * (thus changing altivec regs) then save them. + * We used to check the VRSAVE register but not all apps + * set it, so we don't rely on it now (and in fact we need + * to save & restore VSCR even if VRSAVE == 0). -- paulus + * + * On SMP we always save/restore altivec regs just to avoid the + * complexity of changing processors. + * -- Cort + */ + if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) + giveup_altivec(prev); + /* Avoid the trap. On smp this this never happens since + * we don't set last_task_used_altivec -- Cort + */ + if (new->thread.regs && last_task_used_altivec == new) + new->thread.regs->msr |= MSR_VEC; +#endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_SPE + /* + * If the previous thread used spe in the last quantum + * (thus changing spe regs) then save them. + * + * On SMP we always save/restore spe regs just to avoid the + * complexity of changing processors. + */ + if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) + giveup_spe(prev); + /* Avoid the trap. On smp this this never happens since + * we don't set last_task_used_spe + */ + if (new->thread.regs && last_task_used_spe == new) + new->thread.regs->msr |= MSR_SPE; +#endif /* CONFIG_SPE */ +#endif /* CONFIG_SMP */ + +#ifdef CONFIG_PPC64 /* for now */ + if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr)) { + set_dabr(new->thread.dabr); + __get_cpu_var(current_dabr) = new->thread.dabr; + } +#endif + + new_thread = &new->thread; + old_thread = ¤t->thread; + local_irq_save(flags); + last = _switch(old_thread, new_thread); + + local_irq_restore(flags); + + return last; +} + +void show_regs(struct pt_regs * regs) +{ + int i, trap; + + printk("NIP: %08lX LR: %08lX SP: %08lX REGS: %p TRAP: %04lx %s\n", + regs->nip, regs->link, regs->gpr[1], regs, regs->trap, + print_tainted()); + printk("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, + regs->msr&MSR_IR ? 1 : 0, + regs->msr&MSR_DR ? 1 : 0); + trap = TRAP(regs); + if (trap == 0x300 || trap == 0x600) + printk("DAR: %08lX, DSISR: %08lX\n", regs->dar, regs->dsisr); + printk("TASK = %p[%d] '%s' THREAD: %p\n", + current, current->pid, current->comm, current->thread_info); + printk("Last syscall: %ld ", current->thread.last_syscall); + +#ifdef CONFIG_SMP + printk(" CPU: %d", smp_processor_id()); +#endif /* CONFIG_SMP */ + + for (i = 0; i < 32; i++) { + long r; + if ((i % 8) == 0) + printk("\n" KERN_INFO "GPR%02d: ", i); + if (__get_user(r, ®s->gpr[i])) + break; + printk("%08lX ", r); + if (i == 12 && !FULL_REGS(regs)) + break; + } + printk("\n"); +#ifdef CONFIG_KALLSYMS + /* + * Lookup NIP late so we have the best change of getting the + * above info out without failing + */ + printk("NIP [%08lx] ", regs->nip); + print_symbol("%s\n", regs->nip); + printk("LR [%08lx] ", regs->link); + print_symbol("%s\n", regs->link); +#endif + show_stack(current, (unsigned long *) regs->gpr[1]); +} + +void exit_thread(void) +{ +#ifndef CONFIG_SMP + if (last_task_used_math == current) + last_task_used_math = NULL; +#ifdef CONFIG_ALTIVEC + if (last_task_used_altivec == current) + last_task_used_altivec = NULL; +#endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_SPE + if (last_task_used_spe == current) + last_task_used_spe = NULL; +#endif +#endif /* CONFIG_SMP */ +} + +void flush_thread(void) +{ +#ifndef CONFIG_SMP + if (last_task_used_math == current) + last_task_used_math = NULL; +#ifdef CONFIG_ALTIVEC + if (last_task_used_altivec == current) + last_task_used_altivec = NULL; +#endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_SPE + if (last_task_used_spe == current) + last_task_used_spe = NULL; +#endif +#endif /* CONFIG_SMP */ + +#ifdef CONFIG_PPC64 /* for now */ + if (current->thread.dabr) { + current->thread.dabr = 0; + set_dabr(0); + } +#endif +} + +void +release_thread(struct task_struct *t) +{ +} + +/* + * This gets called before we allocate a new thread and copy + * the current task into it. + */ +void prepare_to_copy(struct task_struct *tsk) +{ + flush_fp_to_thread(current); + flush_altivec_to_thread(current); + flush_spe_to_thread(current); +} + +/* + * Copy a thread.. + */ +int +copy_thread(int nr, unsigned long clone_flags, unsigned long usp, + unsigned long unused, + struct task_struct *p, struct pt_regs *regs) +{ + struct pt_regs *childregs, *kregs; + extern void ret_from_fork(void); + unsigned long sp = (unsigned long)p->thread_info + THREAD_SIZE; + unsigned long childframe; + + CHECK_FULL_REGS(regs); + /* Copy registers */ + sp -= sizeof(struct pt_regs); + childregs = (struct pt_regs *) sp; + *childregs = *regs; + if ((childregs->msr & MSR_PR) == 0) { + /* for kernel thread, set `current' and stackptr in new task */ + childregs->gpr[1] = sp + sizeof(struct pt_regs); + childregs->gpr[2] = (unsigned long) p; + p->thread.regs = NULL; /* no user register state */ + } else { + childregs->gpr[1] = usp; + p->thread.regs = childregs; + if (clone_flags & CLONE_SETTLS) + childregs->gpr[2] = childregs->gpr[6]; + } + childregs->gpr[3] = 0; /* Result from fork() */ + sp -= STACK_FRAME_OVERHEAD; + childframe = sp; + + /* + * The way this works is that at some point in the future + * some task will call _switch to switch to the new task. + * That will pop off the stack frame created below and start + * the new task running at ret_from_fork. The new task will + * do some house keeping and then return from the fork or clone + * system call, using the stack frame created above. + */ + sp -= sizeof(struct pt_regs); + kregs = (struct pt_regs *) sp; + sp -= STACK_FRAME_OVERHEAD; + p->thread.ksp = sp; + kregs->nip = (unsigned long)ret_from_fork; + + p->thread.last_syscall = -1; + + return 0; +} + +/* + * Set up a thread for executing a new program + */ +void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp) +{ + set_fs(USER_DS); + memset(regs->gpr, 0, sizeof(regs->gpr)); + regs->ctr = 0; + regs->link = 0; + regs->xer = 0; + regs->ccr = 0; + regs->mq = 0; + regs->nip = nip; + regs->gpr[1] = sp; + regs->msr = MSR_USER; +#ifndef CONFIG_SMP + if (last_task_used_math == current) + last_task_used_math = NULL; +#ifdef CONFIG_ALTIVEC + if (last_task_used_altivec == current) + last_task_used_altivec = NULL; +#endif +#ifdef CONFIG_SPE + if (last_task_used_spe == current) + last_task_used_spe = NULL; +#endif +#endif /* CONFIG_SMP */ + memset(current->thread.fpr, 0, sizeof(current->thread.fpr)); + current->thread.fpscr = 0; +#ifdef CONFIG_ALTIVEC + memset(current->thread.vr, 0, sizeof(current->thread.vr)); + memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr)); + current->thread.vrsave = 0; + current->thread.used_vr = 0; +#endif /* CONFIG_ALTIVEC */ +#ifdef CONFIG_SPE + memset(current->thread.evr, 0, sizeof(current->thread.evr)); + current->thread.acc = 0; + current->thread.spefscr = 0; + current->thread.used_spe = 0; +#endif /* CONFIG_SPE */ +} + +#define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ + | PR_FP_EXC_RES | PR_FP_EXC_INV) + +int set_fpexc_mode(struct task_struct *tsk, unsigned int val) +{ + struct pt_regs *regs = tsk->thread.regs; + + /* This is a bit hairy. If we are an SPE enabled processor + * (have embedded fp) we store the IEEE exception enable flags in + * fpexc_mode. fpexc_mode is also used for setting FP exception + * mode (asyn, precise, disabled) for 'Classic' FP. */ + if (val & PR_FP_EXC_SW_ENABLE) { +#ifdef CONFIG_SPE + tsk->thread.fpexc_mode = val & + (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); +#else + return -EINVAL; +#endif + } else { + /* on a CONFIG_SPE this does not hurt us. The bits that + * __pack_fe01 use do not overlap with bits used for + * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits + * on CONFIG_SPE implementations are reserved so writing to + * them does not change anything */ + if (val > PR_FP_EXC_PRECISE) + return -EINVAL; + tsk->thread.fpexc_mode = __pack_fe01(val); + if (regs != NULL && (regs->msr & MSR_FP) != 0) + regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) + | tsk->thread.fpexc_mode; + } + return 0; +} + +int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) +{ + unsigned int val; + + if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) +#ifdef CONFIG_SPE + val = tsk->thread.fpexc_mode; +#else + return -EINVAL; +#endif + else + val = __unpack_fe01(tsk->thread.fpexc_mode); + return put_user(val, (unsigned int __user *) adr); +} + +int sys_clone(unsigned long clone_flags, unsigned long usp, + int __user *parent_tidp, void __user *child_threadptr, + int __user *child_tidp, int p6, + struct pt_regs *regs) +{ + CHECK_FULL_REGS(regs); + if (usp == 0) + usp = regs->gpr[1]; /* stack pointer for child */ + return do_fork(clone_flags, usp, regs, 0, parent_tidp, child_tidp); +} + +int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3, + unsigned long p4, unsigned long p5, unsigned long p6, + struct pt_regs *regs) +{ + CHECK_FULL_REGS(regs); + return do_fork(SIGCHLD, regs->gpr[1], regs, 0, NULL, NULL); +} + +int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3, + unsigned long p4, unsigned long p5, unsigned long p6, + struct pt_regs *regs) +{ + CHECK_FULL_REGS(regs); + return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->gpr[1], + regs, 0, NULL, NULL); +} + +int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + struct pt_regs *regs) +{ + int error; + char * filename; + + filename = getname((char __user *) a0); + error = PTR_ERR(filename); + if (IS_ERR(filename)) + goto out; + flush_fp_to_thread(current); + flush_altivec_to_thread(current); + flush_spe_to_thread(current); + if (error == 0) { + task_lock(current); + current->ptrace &= ~PT_DTRACE; + task_unlock(current); + } + putname(filename); +out: + return error; +} + +static int validate_sp(unsigned long sp, struct task_struct *p, + unsigned long nbytes) +{ + unsigned long stack_page = (unsigned long)p->thread_info; + + if (sp >= stack_page + sizeof(struct thread_struct) + && sp <= stack_page + THREAD_SIZE - nbytes) + return 1; + +#ifdef CONFIG_IRQSTACKS + stack_page = (unsigned long) hardirq_ctx[task_cpu(p)]; + if (sp >= stack_page + sizeof(struct thread_struct) + && sp <= stack_page + THREAD_SIZE - nbytes) + return 1; + + stack_page = (unsigned long) softirq_ctx[task_cpu(p)]; + if (sp >= stack_page + sizeof(struct thread_struct) + && sp <= stack_page + THREAD_SIZE - nbytes) + return 1; +#endif + + return 0; +} + +void dump_stack(void) +{ + show_stack(current, NULL); +} + +EXPORT_SYMBOL(dump_stack); + +void show_stack(struct task_struct *tsk, unsigned long *stack) +{ + unsigned long sp, stack_top, prev_sp, ret; + int count = 0; + unsigned long next_exc = 0; + struct pt_regs *regs; + extern char ret_from_except, ret_from_except_full, ret_from_syscall; + + sp = (unsigned long) stack; + if (tsk == NULL) + tsk = current; + if (sp == 0) { + if (tsk == current) + asm("mr %0,1" : "=r" (sp)); + else + sp = tsk->thread.ksp; + } + + prev_sp = (unsigned long) (tsk->thread_info + 1); + stack_top = (unsigned long) tsk->thread_info + THREAD_SIZE; + while (count < 16 && sp > prev_sp && sp < stack_top && (sp & 3) == 0) { + if (count == 0) { + printk("Call trace:"); +#ifdef CONFIG_KALLSYMS + printk("\n"); +#endif + } else { + if (next_exc) { + ret = next_exc; + next_exc = 0; + } else + ret = *(unsigned long *)(sp + 4); + printk(" [%08lx] ", ret); +#ifdef CONFIG_KALLSYMS + print_symbol("%s", ret); + printk("\n"); +#endif + if (ret == (unsigned long) &ret_from_except + || ret == (unsigned long) &ret_from_except_full + || ret == (unsigned long) &ret_from_syscall) { + /* sp + 16 points to an exception frame */ + regs = (struct pt_regs *) (sp + 16); + if (sp + 16 + sizeof(*regs) <= stack_top) + next_exc = regs->nip; + } + } + ++count; + sp = *(unsigned long *)sp; + } +#ifndef CONFIG_KALLSYMS + if (count > 0) + printk("\n"); +#endif +} + +unsigned long get_wchan(struct task_struct *p) +{ + unsigned long ip, sp; + int count = 0; + + if (!p || p == current || p->state == TASK_RUNNING) + return 0; + + sp = p->thread.ksp; + if (!validate_sp(sp, p, 16)) + return 0; + + do { + sp = *(unsigned long *)sp; + if (!validate_sp(sp, p, 16)) + return 0; + if (count > 0) { + ip = *(unsigned long *)(sp + 4); + if (!in_sched_functions(ip)) + return ip; + } + } while (count++ < 16); + return 0; +} +EXPORT_SYMBOL(get_wchan); diff --git a/arch/powerpc/kernel/semaphore.c b/arch/powerpc/kernel/semaphore.c new file mode 100644 index 00000000000..2f8c3c95139 --- /dev/null +++ b/arch/powerpc/kernel/semaphore.c @@ -0,0 +1,135 @@ +/* + * PowerPC-specific semaphore code. + * + * Copyright (C) 1999 Cort Dougan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * April 2001 - Reworked by Paul Mackerras + * to eliminate the SMP races in the old version between the updates + * of `count' and `waking'. Now we use negative `count' values to + * indicate that some process(es) are waiting for the semaphore. + */ + +#include +#include +#include + +#include +#include +#include + +/* + * Atomically update sem->count. + * This does the equivalent of the following: + * + * old_count = sem->count; + * tmp = MAX(old_count, 0) + incr; + * sem->count = tmp; + * return old_count; + */ +static inline int __sem_update_count(struct semaphore *sem, int incr) +{ + int old_count, tmp; + + __asm__ __volatile__("\n" +"1: lwarx %0,0,%3\n" +" srawi %1,%0,31\n" +" andc %1,%0,%1\n" +" add %1,%1,%4\n" + PPC405_ERR77(0,%3) +" stwcx. %1,0,%3\n" +" bne 1b" + : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) + : "r" (&sem->count), "r" (incr), "m" (sem->count) + : "cc"); + + return old_count; +} + +void __up(struct semaphore *sem) +{ + /* + * Note that we incremented count in up() before we came here, + * but that was ineffective since the result was <= 0, and + * any negative value of count is equivalent to 0. + * This ends up setting count to 1, unless count is now > 0 + * (i.e. because some other cpu has called up() in the meantime), + * in which case we just increment count. + */ + __sem_update_count(sem, 1); + wake_up(&sem->wait); +} +EXPORT_SYMBOL(__up); + +/* + * Note that when we come in to __down or __down_interruptible, + * we have already decremented count, but that decrement was + * ineffective since the result was < 0, and any negative value + * of count is equivalent to 0. + * Thus it is only when we decrement count from some value > 0 + * that we have actually got the semaphore. + */ +void __sched __down(struct semaphore *sem) +{ + struct task_struct *tsk = current; + DECLARE_WAITQUEUE(wait, tsk); + + __set_task_state(tsk, TASK_UNINTERRUPTIBLE); + add_wait_queue_exclusive(&sem->wait, &wait); + + /* + * Try to get the semaphore. If the count is > 0, then we've + * got the semaphore; we decrement count and exit the loop. + * If the count is 0 or negative, we set it to -1, indicating + * that we are asleep, and then sleep. + */ + while (__sem_update_count(sem, -1) <= 0) { + schedule(); + set_task_state(tsk, TASK_UNINTERRUPTIBLE); + } + remove_wait_queue(&sem->wait, &wait); + __set_task_state(tsk, TASK_RUNNING); + + /* + * If there are any more sleepers, wake one of them up so + * that it can either get the semaphore, or set count to -1 + * indicating that there are still processes sleeping. + */ + wake_up(&sem->wait); +} +EXPORT_SYMBOL(__down); + +int __sched __down_interruptible(struct semaphore * sem) +{ + int retval = 0; + struct task_struct *tsk = current; + DECLARE_WAITQUEUE(wait, tsk); + + __set_task_state(tsk, TASK_INTERRUPTIBLE); + add_wait_queue_exclusive(&sem->wait, &wait); + + while (__sem_update_count(sem, -1) <= 0) { + if (signal_pending(current)) { + /* + * A signal is pending - give up trying. + * Set sem->count to 0 if it is negative, + * since we are no longer sleeping. + */ + __sem_update_count(sem, 0); + retval = -EINTR; + break; + } + schedule(); + set_task_state(tsk, TASK_INTERRUPTIBLE); + } + remove_wait_queue(&sem->wait, &wait); + __set_task_state(tsk, TASK_RUNNING); + + wake_up(&sem->wait); + return retval; +} +EXPORT_SYMBOL(__down_interruptible); diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c new file mode 100644 index 00000000000..c7afbbba0f3 --- /dev/null +++ b/arch/powerpc/kernel/traps.c @@ -0,0 +1,1047 @@ +/* + * arch/powerpc/kernel/traps.c + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Modified by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras (paulus@samba.org) + */ + +/* + * This file handles the architecture-dependent parts of hardware exceptions + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PMAC_BACKLIGHT +#include +#endif +#include + +#ifdef CONFIG_DEBUGGER +int (*__debugger)(struct pt_regs *regs); +int (*__debugger_ipi)(struct pt_regs *regs); +int (*__debugger_bpt)(struct pt_regs *regs); +int (*__debugger_sstep)(struct pt_regs *regs); +int (*__debugger_iabr_match)(struct pt_regs *regs); +int (*__debugger_dabr_match)(struct pt_regs *regs); +int (*__debugger_fault_handler)(struct pt_regs *regs); + +EXPORT_SYMBOL(__debugger); +EXPORT_SYMBOL(__debugger_ipi); +EXPORT_SYMBOL(__debugger_bpt); +EXPORT_SYMBOL(__debugger_sstep); +EXPORT_SYMBOL(__debugger_iabr_match); +EXPORT_SYMBOL(__debugger_dabr_match); +EXPORT_SYMBOL(__debugger_fault_handler); +#endif + +struct notifier_block *powerpc_die_chain; +static DEFINE_SPINLOCK(die_notifier_lock); + +int register_die_notifier(struct notifier_block *nb) +{ + int err = 0; + unsigned long flags; + + spin_lock_irqsave(&die_notifier_lock, flags); + err = notifier_chain_register(&powerpc_die_chain, nb); + spin_unlock_irqrestore(&die_notifier_lock, flags); + return err; +} + +/* + * Trap & Exception support + */ + +static DEFINE_SPINLOCK(die_lock); + +int die(const char *str, struct pt_regs *regs, long err) +{ + static int die_counter; + int nl = 0; + + if (debugger(regs)) + return 1; + + console_verbose(); + spin_lock_irq(&die_lock); + bust_spinlocks(1); +#ifdef CONFIG_PMAC_BACKLIGHT + if (_machine == _MACH_Pmac) { + set_backlight_enable(1); + set_backlight_level(BACKLIGHT_MAX); + } +#endif + printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); +#ifdef CONFIG_PREEMPT + printk("PREEMPT "); + nl = 1; +#endif +#ifdef CONFIG_SMP + printk("SMP NR_CPUS=%d ", NR_CPUS); + nl = 1; +#endif +#ifdef CONFIG_DEBUG_PAGEALLOC + printk("DEBUG_PAGEALLOC "); + nl = 1; +#endif +#ifdef CONFIG_NUMA + printk("NUMA "); + nl = 1; +#endif +#ifdef CONFIG_PPC64 + switch (systemcfg->platform) { + case PLATFORM_PSERIES: + printk("PSERIES "); + nl = 1; + break; + case PLATFORM_PSERIES_LPAR: + printk("PSERIES LPAR "); + nl = 1; + break; + case PLATFORM_ISERIES_LPAR: + printk("ISERIES LPAR "); + nl = 1; + break; + case PLATFORM_POWERMAC: + printk("POWERMAC "); + nl = 1; + break; + case PLATFORM_BPA: + printk("BPA "); + nl = 1; + break; + } +#endif + if (nl) + printk("\n"); + print_modules(); + show_regs(regs); + bust_spinlocks(0); + spin_unlock_irq(&die_lock); + + if (in_interrupt()) + panic("Fatal exception in interrupt"); + + if (panic_on_oops) { + panic("Fatal exception"); + } + do_exit(err); + + return 0; +} + +void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) +{ + siginfo_t info; + + if (!user_mode(regs)) { + if (die("Exception in kernel mode", regs, signr)) + return; + } + + memset(&info, 0, sizeof(info)); + info.si_signo = signr; + info.si_code = code; + info.si_addr = (void __user *) addr; + force_sig_info(signr, &info, current); + + /* + * Init gets no signals that it doesn't have a handler for. + * That's all very well, but if it has caused a synchronous + * exception and we ignore the resulting signal, it will just + * generate the same exception over and over again and we get + * nowhere. Better to kill it and let the kernel panic. + */ + if (current->pid == 1) { + __sighandler_t handler; + + spin_lock_irq(¤t->sighand->siglock); + handler = current->sighand->action[signr-1].sa.sa_handler; + spin_unlock_irq(¤t->sighand->siglock); + if (handler == SIG_DFL) { + /* init has generated a synchronous exception + and it doesn't have a handler for the signal */ + printk(KERN_CRIT "init has generated signal %d " + "but has no handler for it\n", signr); + do_exit(signr); + } + } +} + +#ifdef CONFIG_PPC64 +void system_reset_exception(struct pt_regs *regs) +{ + /* See if any machine dependent calls */ + if (ppc_md.system_reset_exception) + ppc_md.system_reset_exception(regs); + + die("System Reset", regs, SIGABRT); + + /* Must die if the interrupt is not recoverable */ + if (!(regs->msr & MSR_RI)) + panic("Unrecoverable System Reset"); + + /* What should we do here? We could issue a shutdown or hard reset. */ +} +#endif + +/* + * I/O accesses can cause machine checks on powermacs. + * Check if the NIP corresponds to the address of a sync + * instruction for which there is an entry in the exception + * table. + * Note that the 601 only takes a machine check on TEA + * (transfer error ack) signal assertion, and does not + * set any of the top 16 bits of SRR1. + * -- paulus. + */ +static inline int check_io_access(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC_PMAC + unsigned long msr = regs->msr; + const struct exception_table_entry *entry; + unsigned int *nip = (unsigned int *)regs->nip; + + if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) + && (entry = search_exception_tables(regs->nip)) != NULL) { + /* + * Check that it's a sync instruction, or somewhere + * in the twi; isync; nop sequence that inb/inw/inl uses. + * As the address is in the exception table + * we should be able to read the instr there. + * For the debug message, we look at the preceding + * load or store. + */ + if (*nip == 0x60000000) /* nop */ + nip -= 2; + else if (*nip == 0x4c00012c) /* isync */ + --nip; + if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { + /* sync or twi */ + unsigned int rb; + + --nip; + rb = (*nip >> 11) & 0x1f; + printk(KERN_DEBUG "%s bad port %lx at %p\n", + (*nip & 0x100)? "OUT to": "IN from", + regs->gpr[rb] - _IO_BASE, nip); + regs->msr |= MSR_RI; + regs->nip = entry->fixup; + return 1; + } + } +#endif /* CONFIG_PPC_PMAC */ + return 0; +} + +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) +/* On 4xx, the reason for the machine check or program exception + is in the ESR. */ +#define get_reason(regs) ((regs)->dsisr) +#ifndef CONFIG_FSL_BOOKE +#define get_mc_reason(regs) ((regs)->dsisr) +#else +#define get_mc_reason(regs) (mfspr(SPRN_MCSR)) +#endif +#define REASON_FP ESR_FP +#define REASON_ILLEGAL (ESR_PIL | ESR_PUO) +#define REASON_PRIVILEGED ESR_PPR +#define REASON_TRAP ESR_PTR + +/* single-step stuff */ +#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) +#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) + +#else +/* On non-4xx, the reason for the machine check or program + exception is in the MSR. */ +#define get_reason(regs) ((regs)->msr) +#define get_mc_reason(regs) ((regs)->msr) +#define REASON_FP 0x100000 +#define REASON_ILLEGAL 0x80000 +#define REASON_PRIVILEGED 0x40000 +#define REASON_TRAP 0x20000 + +#define single_stepping(regs) ((regs)->msr & MSR_SE) +#define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) +#endif + +/* + * This is "fall-back" implementation for configurations + * which don't provide platform-specific machine check info + */ +void __attribute__ ((weak)) +platform_machine_check(struct pt_regs *regs) +{ +} + +void MachineCheckException(struct pt_regs *regs) +{ +#ifdef CONFIG_PPC64 + int recover = 0; + + /* See if any machine dependent calls */ + if (ppc_md.machine_check_exception) + recover = ppc_md.machine_check_exception(regs); + + if (recover) + return; +#else + unsigned long reason = get_mc_reason(regs); + + if (user_mode(regs)) { + regs->msr |= MSR_RI; + _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); + return; + } + +#if defined(CONFIG_8xx) && defined(CONFIG_PCI) + /* the qspan pci read routines can cause machine checks -- Cort */ + bad_page_fault(regs, regs->dar, SIGBUS); + return; +#endif + + if (debugger_fault_handler(regs)) { + regs->msr |= MSR_RI; + return; + } + + if (check_io_access(regs)) + return; + +#if defined(CONFIG_4xx) && !defined(CONFIG_440A) + if (reason & ESR_IMCP) { + printk("Instruction"); + mtspr(SPRN_ESR, reason & ~ESR_IMCP); + } else + printk("Data"); + printk(" machine check in kernel mode.\n"); +#elif defined(CONFIG_440A) + printk("Machine check in kernel mode.\n"); + if (reason & ESR_IMCP){ + printk("Instruction Synchronous Machine Check exception\n"); + mtspr(SPRN_ESR, reason & ~ESR_IMCP); + } + else { + u32 mcsr = mfspr(SPRN_MCSR); + if (mcsr & MCSR_IB) + printk("Instruction Read PLB Error\n"); + if (mcsr & MCSR_DRB) + printk("Data Read PLB Error\n"); + if (mcsr & MCSR_DWB) + printk("Data Write PLB Error\n"); + if (mcsr & MCSR_TLBP) + printk("TLB Parity Error\n"); + if (mcsr & MCSR_ICP){ + flush_instruction_cache(); + printk("I-Cache Parity Error\n"); + } + if (mcsr & MCSR_DCSP) + printk("D-Cache Search Parity Error\n"); + if (mcsr & MCSR_DCFP) + printk("D-Cache Flush Parity Error\n"); + if (mcsr & MCSR_IMPE) + printk("Machine Check exception is imprecise\n"); + + /* Clear MCSR */ + mtspr(SPRN_MCSR, mcsr); + } +#elif defined (CONFIG_E500) + printk("Machine check in kernel mode.\n"); + printk("Caused by (from MCSR=%lx): ", reason); + + if (reason & MCSR_MCP) + printk("Machine Check Signal\n"); + if (reason & MCSR_ICPERR) + printk("Instruction Cache Parity Error\n"); + if (reason & MCSR_DCP_PERR) + printk("Data Cache Push Parity Error\n"); + if (reason & MCSR_DCPERR) + printk("Data Cache Parity Error\n"); + if (reason & MCSR_GL_CI) + printk("Guarded Load or Cache-Inhibited stwcx.\n"); + if (reason & MCSR_BUS_IAERR) + printk("Bus - Instruction Address Error\n"); + if (reason & MCSR_BUS_RAERR) + printk("Bus - Read Address Error\n"); + if (reason & MCSR_BUS_WAERR) + printk("Bus - Write Address Error\n"); + if (reason & MCSR_BUS_IBERR) + printk("Bus - Instruction Data Error\n"); + if (reason & MCSR_BUS_RBERR) + printk("Bus - Read Data Bus Error\n"); + if (reason & MCSR_BUS_WBERR) + printk("Bus - Read Data Bus Error\n"); + if (reason & MCSR_BUS_IPERR) + printk("Bus - Instruction Parity Error\n"); + if (reason & MCSR_BUS_RPERR) + printk("Bus - Read Parity Error\n"); +#elif defined (CONFIG_E200) + printk("Machine check in kernel mode.\n"); + printk("Caused by (from MCSR=%lx): ", reason); + + if (reason & MCSR_MCP) + printk("Machine Check Signal\n"); + if (reason & MCSR_CP_PERR) + printk("Cache Push Parity Error\n"); + if (reason & MCSR_CPERR) + printk("Cache Parity Error\n"); + if (reason & MCSR_EXCP_ERR) + printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); + if (reason & MCSR_BUS_IRERR) + printk("Bus - Read Bus Error on instruction fetch\n"); + if (reason & MCSR_BUS_DRERR) + printk("Bus - Read Bus Error on data load\n"); + if (reason & MCSR_BUS_WRERR) + printk("Bus - Write Bus Error on buffered store or cache line push\n"); +#else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ + printk("Machine check in kernel mode.\n"); + printk("Caused by (from SRR1=%lx): ", reason); + switch (reason & 0x601F0000) { + case 0x80000: + printk("Machine check signal\n"); + break; + case 0: /* for 601 */ + case 0x40000: + case 0x140000: /* 7450 MSS error and TEA */ + printk("Transfer error ack signal\n"); + break; + case 0x20000: + printk("Data parity error signal\n"); + break; + case 0x10000: + printk("Address parity error signal\n"); + break; + case 0x20000000: + printk("L1 Data Cache error\n"); + break; + case 0x40000000: + printk("L1 Instruction Cache error\n"); + break; + case 0x00100000: + printk("L2 data cache parity error\n"); + break; + default: + printk("Unknown values in msr\n"); + } +#endif /* CONFIG_4xx */ + + /* + * Optional platform-provided routine to print out + * additional info, e.g. bus error registers. + */ + platform_machine_check(regs); +#endif /* CONFIG_PPC64 */ + + if (debugger_fault_handler(regs)) + return; + die("Machine check", regs, SIGBUS); + + /* Must die if the interrupt is not recoverable */ + if (!(regs->msr & MSR_RI)) + panic("Unrecoverable Machine check"); +} + +void SMIException(struct pt_regs *regs) +{ + die("System Management Interrupt", regs, SIGABRT); +} + +void UnknownException(struct pt_regs *regs) +{ + printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + + _exception(SIGTRAP, regs, 0, 0); +} + +void InstructionBreakpoint(struct pt_regs *regs) +{ + if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, + 5, SIGTRAP) == NOTIFY_STOP) + return; + if (debugger_iabr_match(regs)) + return; + _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); +} + +void RunModeException(struct pt_regs *regs) +{ + _exception(SIGTRAP, regs, 0, 0); +} + +void SingleStepException(struct pt_regs *regs) +{ + regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ + + if (notify_die(DIE_SSTEP, "single_step", regs, 5, + 5, SIGTRAP) == NOTIFY_STOP) + return; + if (debugger_sstep(regs)) + return; + + _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); +} + +/* + * After we have successfully emulated an instruction, we have to + * check if the instruction was being single-stepped, and if so, + * pretend we got a single-step exception. This was pointed out + * by Kumar Gala. -- paulus + */ +static void emulate_single_step(struct pt_regs *regs) +{ + if (single_stepping(regs)) { + clear_single_step(regs); + _exception(SIGTRAP, regs, TRAP_TRACE, 0); + } +} + +/* Illegal instruction emulation support. Originally written to + * provide the PVR to user applications using the mfspr rd, PVR. + * Return non-zero if we can't emulate, or -EFAULT if the associated + * memory access caused an access fault. Return zero on success. + * + * There are a couple of ways to do this, either "decode" the instruction + * or directly match lots of bits. In this case, matching lots of + * bits is faster and easier. + * + */ +#define INST_MFSPR_PVR 0x7c1f42a6 +#define INST_MFSPR_PVR_MASK 0xfc1fffff + +#define INST_DCBA 0x7c0005ec +#define INST_DCBA_MASK 0x7c0007fe + +#define INST_MCRXR 0x7c000400 +#define INST_MCRXR_MASK 0x7c0007fe + +#define INST_STRING 0x7c00042a +#define INST_STRING_MASK 0x7c0007fe +#define INST_STRING_GEN_MASK 0x7c00067e +#define INST_LSWI 0x7c0004aa +#define INST_LSWX 0x7c00042a +#define INST_STSWI 0x7c0005aa +#define INST_STSWX 0x7c00052a + +static int emulate_string_inst(struct pt_regs *regs, u32 instword) +{ + u8 rT = (instword >> 21) & 0x1f; + u8 rA = (instword >> 16) & 0x1f; + u8 NB_RB = (instword >> 11) & 0x1f; + u32 num_bytes; + unsigned long EA; + int pos = 0; + + /* Early out if we are an invalid form of lswx */ + if ((instword & INST_STRING_MASK) == INST_LSWX) + if ((rT == rA) || (rT == NB_RB)) + return -EINVAL; + + EA = (rA == 0) ? 0 : regs->gpr[rA]; + + switch (instword & INST_STRING_MASK) { + case INST_LSWX: + case INST_STSWX: + EA += NB_RB; + num_bytes = regs->xer & 0x7f; + break; + case INST_LSWI: + case INST_STSWI: + num_bytes = (NB_RB == 0) ? 32 : NB_RB; + break; + default: + return -EINVAL; + } + + while (num_bytes != 0) + { + u8 val; + u32 shift = 8 * (3 - (pos & 0x3)); + + switch ((instword & INST_STRING_MASK)) { + case INST_LSWX: + case INST_LSWI: + if (get_user(val, (u8 __user *)EA)) + return -EFAULT; + /* first time updating this reg, + * zero it out */ + if (pos == 0) + regs->gpr[rT] = 0; + regs->gpr[rT] |= val << shift; + break; + case INST_STSWI: + case INST_STSWX: + val = regs->gpr[rT] >> shift; + if (put_user(val, (u8 __user *)EA)) + return -EFAULT; + break; + } + /* move EA to next address */ + EA += 1; + num_bytes--; + + /* manage our position within the register */ + if (++pos == 4) { + pos = 0; + if (++rT == 32) + rT = 0; + } + } + + return 0; +} + +static int emulate_instruction(struct pt_regs *regs) +{ + u32 instword; + u32 rd; + + if (!user_mode(regs)) + return -EINVAL; + CHECK_FULL_REGS(regs); + + if (get_user(instword, (u32 __user *)(regs->nip))) + return -EFAULT; + + /* Emulate the mfspr rD, PVR. */ + if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) { + rd = (instword >> 21) & 0x1f; + regs->gpr[rd] = mfspr(SPRN_PVR); + return 0; + } + + /* Emulating the dcba insn is just a no-op. */ + if ((instword & INST_DCBA_MASK) == INST_DCBA) + return 0; + + /* Emulate the mcrxr insn. */ + if ((instword & INST_MCRXR_MASK) == INST_MCRXR) { + int shift = (instword >> 21) & 0x1c; + unsigned long msk = 0xf0000000UL >> shift; + + regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); + regs->xer &= ~0xf0000000UL; + return 0; + } + + /* Emulate load/store string insn. */ + if ((instword & INST_STRING_GEN_MASK) == INST_STRING) + return emulate_string_inst(regs, instword); + + return -EINVAL; +} + +/* + * Look through the list of trap instructions that are used for BUG(), + * BUG_ON() and WARN_ON() and see if we hit one. At this point we know + * that the exception was caused by a trap instruction of some kind. + * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0 + * otherwise. + */ +extern struct bug_entry __start___bug_table[], __stop___bug_table[]; + +#ifndef CONFIG_MODULES +#define module_find_bug(x) NULL +#endif + +struct bug_entry *find_bug(unsigned long bugaddr) +{ + struct bug_entry *bug; + + for (bug = __start___bug_table; bug < __stop___bug_table; ++bug) + if (bugaddr == bug->bug_addr) + return bug; + return module_find_bug(bugaddr); +} + +int check_bug_trap(struct pt_regs *regs) +{ + struct bug_entry *bug; + unsigned long addr; + + if (regs->msr & MSR_PR) + return 0; /* not in kernel */ + addr = regs->nip; /* address of trap instruction */ + if (addr < PAGE_OFFSET) + return 0; + bug = find_bug(regs->nip); + if (bug == NULL) + return 0; + if (bug->line & BUG_WARNING_TRAP) { + /* this is a WARN_ON rather than BUG/BUG_ON */ +#ifdef CONFIG_XMON + xmon_printf(KERN_ERR "Badness in %s at %s:%d\n", + bug->function, bug->file, + bug->line & ~BUG_WARNING_TRAP); +#endif /* CONFIG_XMON */ + printk(KERN_ERR "Badness in %s at %s:%d\n", + bug->function, bug->file, + bug->line & ~BUG_WARNING_TRAP); + dump_stack(); + return 1; + } +#ifdef CONFIG_XMON + xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n", + bug->function, bug->file, bug->line); + xmon(regs); +#endif /* CONFIG_XMON */ + printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n", + bug->function, bug->file, bug->line); + + return 0; +} + +void ProgramCheckException(struct pt_regs *regs) +{ + unsigned int reason = get_reason(regs); + extern int do_mathemu(struct pt_regs *regs); + +#ifdef CONFIG_MATH_EMULATION + /* (reason & REASON_ILLEGAL) would be the obvious thing here, + * but there seems to be a hardware bug on the 405GP (RevD) + * that means ESR is sometimes set incorrectly - either to + * ESR_DST (!?) or 0. In the process of chasing this with the + * hardware people - not sure if it can happen on any illegal + * instruction or only on FP instructions, whether there is a + * pattern to occurences etc. -dgibson 31/Mar/2003 */ + if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) { + emulate_single_step(regs); + return; + } +#endif /* CONFIG_MATH_EMULATION */ + + if (reason & REASON_FP) { + /* IEEE FP exception */ + int code = 0; + u32 fpscr; + + /* We must make sure the FP state is consistent with + * our MSR_FP in regs + */ + preempt_disable(); + if (regs->msr & MSR_FP) + giveup_fpu(current); + preempt_enable(); + + fpscr = current->thread.fpscr; + fpscr &= fpscr << 22; /* mask summary bits with enables */ + if (fpscr & FPSCR_VX) + code = FPE_FLTINV; + else if (fpscr & FPSCR_OX) + code = FPE_FLTOVF; + else if (fpscr & FPSCR_UX) + code = FPE_FLTUND; + else if (fpscr & FPSCR_ZX) + code = FPE_FLTDIV; + else if (fpscr & FPSCR_XX) + code = FPE_FLTRES; + _exception(SIGFPE, regs, code, regs->nip); + return; + } + + if (reason & REASON_TRAP) { + /* trap exception */ + if (debugger_bpt(regs)) + return; + if (check_bug_trap(regs)) { + regs->nip += 4; + return; + } + _exception(SIGTRAP, regs, TRAP_BRKPT, 0); + return; + } + + /* Try to emulate it if we should. */ + if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { + switch (emulate_instruction(regs)) { + case 0: + regs->nip += 4; + emulate_single_step(regs); + return; + case -EFAULT: + _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); + return; + } + } + + if (reason & REASON_PRIVILEGED) + _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); + else + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); +} + +void AlignmentException(struct pt_regs *regs) +{ + int fixed; + + fixed = fix_alignment(regs); + + if (fixed == 1) { + regs->nip += 4; /* skip over emulated instruction */ + emulate_single_step(regs); + return; + } + + /* Operand address was bad */ + if (fixed == -EFAULT) { + if (user_mode(regs)) + _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar); + else + /* Search exception table */ + bad_page_fault(regs, regs->dar, SIGSEGV); + return; + } + _exception(SIGBUS, regs, BUS_ADRALN, regs->dar); +} + +void StackOverflow(struct pt_regs *regs) +{ + printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", + current, regs->gpr[1]); + debugger(regs); + show_regs(regs); + panic("kernel stack overflow"); +} + +void nonrecoverable_exception(struct pt_regs *regs) +{ + printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", + regs->nip, regs->msr); + debugger(regs); + die("nonrecoverable exception", regs, SIGKILL); +} + +void trace_syscall(struct pt_regs *regs) +{ + printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", + current, current->pid, regs->nip, regs->link, regs->gpr[0], + regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); +} + +#ifdef CONFIG_8xx +void SoftwareEmulation(struct pt_regs *regs) +{ + extern int do_mathemu(struct pt_regs *); + extern int Soft_emulate_8xx(struct pt_regs *); + int errcode; + + CHECK_FULL_REGS(regs); + + if (!user_mode(regs)) { + debugger(regs); + die("Kernel Mode Software FPU Emulation", regs, SIGFPE); + } + +#ifdef CONFIG_MATH_EMULATION + errcode = do_mathemu(regs); +#else + errcode = Soft_emulate_8xx(regs); +#endif + if (errcode) { + if (errcode > 0) + _exception(SIGFPE, regs, 0, 0); + else if (errcode == -EFAULT) + _exception(SIGSEGV, regs, 0, 0); + else + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); + } else + emulate_single_step(regs); +} +#endif /* CONFIG_8xx */ + +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + +void DebugException(struct pt_regs *regs, unsigned long debug_status) +{ + if (debug_status & DBSR_IC) { /* instruction completion */ + regs->msr &= ~MSR_DE; + if (user_mode(regs)) { + current->thread.dbcr0 &= ~DBCR0_IC; + } else { + /* Disable instruction completion */ + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); + /* Clear the instruction completion event */ + mtspr(SPRN_DBSR, DBSR_IC); + if (debugger_sstep(regs)) + return; + } + _exception(SIGTRAP, regs, TRAP_TRACE, 0); + } +} +#endif /* CONFIG_4xx || CONFIG_BOOKE */ + +#if !defined(CONFIG_TAU_INT) +void TAUException(struct pt_regs *regs) +{ + printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", + regs->nip, regs->msr, regs->trap, print_tainted()); +} +#endif /* CONFIG_INT_TAU */ + +void AltivecUnavailException(struct pt_regs *regs) +{ + static int kernel_altivec_count; + +#ifndef CONFIG_ALTIVEC + if (user_mode(regs)) { + /* A user program has executed an altivec instruction, + but this kernel doesn't support altivec. */ + _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); + return; + } +#endif + /* The kernel has executed an altivec instruction without + first enabling altivec. Whinge but let it do it. */ + if (++kernel_altivec_count < 10) + printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n", + current, regs->nip); + regs->msr |= MSR_VEC; +} + +#ifdef CONFIG_ALTIVEC +void AltivecAssistException(struct pt_regs *regs) +{ + int err; + + preempt_disable(); + if (regs->msr & MSR_VEC) + giveup_altivec(current); + preempt_enable(); + if (!user_mode(regs)) { + printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" + " at %lx\n", regs->nip); + die("Kernel Altivec assist exception", regs, SIGILL); + } + + err = emulate_altivec(regs); + if (err == 0) { + regs->nip += 4; /* skip emulated instruction */ + emulate_single_step(regs); + return; + } + + if (err == -EFAULT) { + /* got an error reading the instruction */ + _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); + } else { + /* didn't recognize the instruction */ + /* XXX quick hack for now: set the non-Java bit in the VSCR */ + if (printk_ratelimit()) + printk(KERN_ERR "Unrecognized altivec instruction " + "in %s at %lx\n", current->comm, regs->nip); + current->thread.vscr.u[3] |= 0x10000; + } +} +#endif /* CONFIG_ALTIVEC */ + +#ifdef CONFIG_E500 +void PerformanceMonitorException(struct pt_regs *regs) +{ + perf_irq(regs); +} +#endif + +#ifdef CONFIG_FSL_BOOKE +void CacheLockingException(struct pt_regs *regs, unsigned long address, + unsigned long error_code) +{ + /* We treat cache locking instructions from the user + * as priv ops, in the future we could try to do + * something smarter + */ + if (error_code & (ESR_DLK|ESR_ILK)) + _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); + return; +} +#endif /* CONFIG_FSL_BOOKE */ + +#ifdef CONFIG_SPE +void SPEFloatingPointException(struct pt_regs *regs) +{ + unsigned long spefscr; + int fpexc_mode; + int code = 0; + + spefscr = current->thread.spefscr; + fpexc_mode = current->thread.fpexc_mode; + + /* Hardware does not neccessarily set sticky + * underflow/overflow/invalid flags */ + if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { + code = FPE_FLTOVF; + spefscr |= SPEFSCR_FOVFS; + } + else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { + code = FPE_FLTUND; + spefscr |= SPEFSCR_FUNFS; + } + else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) + code = FPE_FLTDIV; + else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { + code = FPE_FLTINV; + spefscr |= SPEFSCR_FINVS; + } + else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) + code = FPE_FLTRES; + + current->thread.spefscr = spefscr; + + _exception(SIGFPE, regs, code, regs->nip); + return; +} +#endif + +#ifdef CONFIG_BOOKE_WDT +/* + * Default handler for a Watchdog exception, + * spins until a reboot occurs + */ +void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) +{ + /* Generic WatchdogHandler, implement your own */ + mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); + return; +} + +void WatchdogException(struct pt_regs *regs) +{ + printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); + WatchdogHandler(regs); +} +#endif + +void __init trap_init(void) +{ +} diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S new file mode 100644 index 00000000000..12cb90bc209 --- /dev/null +++ b/arch/powerpc/kernel/vector.S @@ -0,0 +1,197 @@ +#include +#include +#include + +/* + * The routines below are in assembler so we can closely control the + * usage of floating-point registers. These routines must be called + * with preempt disabled. + */ +#ifdef CONFIG_PPC32 + .data +fpzero: + .long 0 +fpone: + .long 0x3f800000 /* 1.0 in single-precision FP */ +fphalf: + .long 0x3f000000 /* 0.5 in single-precision FP */ + +#define LDCONST(fr, name) \ + lis r11,name@ha; \ + lfs fr,name@l(r11) +#else + + .section ".toc","aw" +fpzero: + .tc FD_0_0[TC],0 +fpone: + .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */ +fphalf: + .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */ + +#define LDCONST(fr, name) \ + lfd fr,name@toc(r2) +#endif + + .text +/* + * Internal routine to enable floating point and set FPSCR to 0. + * Don't call it from C; it doesn't use the normal calling convention. + */ +fpenable: +#ifdef CONFIG_PPC32 + stwu r1,-64(r1) +#else + stdu r1,-64(r1) +#endif + mfmsr r10 + ori r11,r10,MSR_FP + mtmsr r11 + isync + stfd fr0,24(r1) + stfd fr1,16(r1) + stfd fr31,8(r1) + LDCONST(fr1, fpzero) + mffs fr31 + mtfsf 0xff,fr1 + blr + +fpdisable: + mtlr r12 + mtfsf 0xff,fr31 + lfd fr31,8(r1) + lfd fr1,16(r1) + lfd fr0,24(r1) + mtmsr r10 + isync + addi r1,r1,64 + blr + +/* + * Vector add, floating point. + */ +_GLOBAL(vaddfp) + mflr r12 + bl fpenable + li r0,4 + mtctr r0 + li r6,0 +1: lfsx fr0,r4,r6 + lfsx fr1,r5,r6 + fadds fr0,fr0,fr1 + stfsx fr0,r3,r6 + addi r6,r6,4 + bdnz 1b + b fpdisable + +/* + * Vector subtract, floating point. + */ +_GLOBAL(vsubfp) + mflr r12 + bl fpenable + li r0,4 + mtctr r0 + li r6,0 +1: lfsx fr0,r4,r6 + lfsx fr1,r5,r6 + fsubs fr0,fr0,fr1 + stfsx fr0,r3,r6 + addi r6,r6,4 + bdnz 1b + b fpdisable + +/* + * Vector multiply and add, floating point. + */ +_GLOBAL(vmaddfp) + mflr r12 + bl fpenable + stfd fr2,32(r1) + li r0,4 + mtctr r0 + li r7,0 +1: lfsx fr0,r4,r7 + lfsx fr1,r5,r7 + lfsx fr2,r6,r7 + fmadds fr0,fr0,fr2,fr1 + stfsx fr0,r3,r7 + addi r7,r7,4 + bdnz 1b + lfd fr2,32(r1) + b fpdisable + +/* + * Vector negative multiply and subtract, floating point. + */ +_GLOBAL(vnmsubfp) + mflr r12 + bl fpenable + stfd fr2,32(r1) + li r0,4 + mtctr r0 + li r7,0 +1: lfsx fr0,r4,r7 + lfsx fr1,r5,r7 + lfsx fr2,r6,r7 + fnmsubs fr0,fr0,fr2,fr1 + stfsx fr0,r3,r7 + addi r7,r7,4 + bdnz 1b + lfd fr2,32(r1) + b fpdisable + +/* + * Vector reciprocal estimate. We just compute 1.0/x. + * r3 -> destination, r4 -> source. + */ +_GLOBAL(vrefp) + mflr r12 + bl fpenable + li r0,4 + LDCONST(fr1, fpone) + mtctr r0 + li r6,0 +1: lfsx fr0,r4,r6 + fdivs fr0,fr1,fr0 + stfsx fr0,r3,r6 + addi r6,r6,4 + bdnz 1b + b fpdisable + +/* + * Vector reciprocal square-root estimate, floating point. + * We use the frsqrte instruction for the initial estimate followed + * by 2 iterations of Newton-Raphson to get sufficient accuracy. + * r3 -> destination, r4 -> source. + */ +_GLOBAL(vrsqrtefp) + mflr r12 + bl fpenable + stfd fr2,32(r1) + stfd fr3,40(r1) + stfd fr4,48(r1) + stfd fr5,56(r1) + li r0,4 + LDCONST(fr4, fpone) + LDCONST(fr5, fphalf) + mtctr r0 + li r6,0 +1: lfsx fr0,r4,r6 + frsqrte fr1,fr0 /* r = frsqrte(s) */ + fmuls fr3,fr1,fr0 /* r * s */ + fmuls fr2,fr1,fr5 /* r * 0.5 */ + fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */ + fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */ + fmuls fr3,fr1,fr0 /* r * s */ + fmuls fr2,fr1,fr5 /* r * 0.5 */ + fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */ + fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */ + stfsx fr1,r3,r6 + addi r6,r6,4 + bdnz 1b + lfd fr5,56(r1) + lfd fr4,48(r1) + lfd fr3,40(r1) + lfd fr2,32(r1) + b fpdisable diff --git a/arch/powerpc/kernel/vmlinux.lds b/arch/powerpc/kernel/vmlinux.lds new file mode 100644 index 00000000000..d62c288a81d --- /dev/null +++ b/arch/powerpc/kernel/vmlinux.lds @@ -0,0 +1,174 @@ +/* Align . to a 8 byte boundary equals to maximum function alignment. */ +/* sched.text is aling to function alignment to secure we have same + * address even at second ld pass when generating System.map */ +/* spinlock.text is aling to function alignment to secure we have same + * address even at second ld pass when generating System.map */ + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to + the beginning of the section so we begin them at 0. */ + /* Stabs debugging sections. */ +OUTPUT_ARCH(powerpc:common) +jiffies = jiffies_64 + 4; +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } +/* .init : { *(.init) } =0*/ + .plt : { *(.plt) } + .text : + { + *(.text) + . = ALIGN(8); __sched_text_start = .; *(.sched.text) __sched_text_end = .; + . = ALIGN(8); __lock_text_start = .; *(.spinlock.text) __lock_text_end = .; + *(.fixup) + *(.got1) + __got2_start = .; + *(.got2) + __got2_end = .; + } + _etext = .; + PROVIDE (etext = .); + .rodata : AT(ADDR(.rodata) - 0) { *(.rodata) *(.rodata.*) *(__vermagic) } .rodata1 : AT(ADDR(.rodata1) - 0) { *(.rodata1) } .pci_fixup : AT(ADDR(.pci_fixup) - 0) { __start_pci_fixups_early = .; *(.pci_fixup_early) __end_pci_fixups_early = .; __start_pci_fixups_header = .; *(.pci_fixup_header) __end_pci_fixups_header = .; __start_pci_fixups_final = .; *(.pci_fixup_final) __end_pci_fixups_final = .; __start_pci_fixups_enable = .; *(.pci_fixup_enable) __end_pci_fixups_enable = .; } __ksymtab : AT(ADDR(__ksymtab) - 0) { __start___ksymtab = .; *(__ksymtab) __stop___ksymtab = .; } __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - 0) { __start___ksymtab_gpl = .; *(__ksymtab_gpl) __stop___ksymtab_gpl = .; } __kcrctab : AT(ADDR(__kcrctab) - 0) { __start___kcrctab = .; *(__kcrctab) __stop___kcrctab = .; } __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - 0) { __start___kcrctab_gpl = .; *(__kcrctab_gpl) __stop___kcrctab_gpl = .; } __ksymtab_strings : AT(ADDR(__ksymtab_strings) - 0) { *(__ksymtab_strings) } __param : AT(ADDR(__param) - 0) { __start___param = .; *(__param) __stop___param = .; } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + .fixup : { *(.fixup) } + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + __bug_table : { + __start___bug_table = .; + *(__bug_table) + __stop___bug_table = .; + } + /* Read-write section, merged into data segment: */ + . = ALIGN(4096); + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.got.plt) *(.got) + *(.dynamic) + CONSTRUCTORS + } + + . = ALIGN(4096); + __nosave_begin = .; + .data_nosave : { *(.data.nosave) } + . = ALIGN(4096); + __nosave_end = .; + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + _edata = .; + PROVIDE (edata = .); + + . = ALIGN(8192); + .data.init_task : { *(.data.init_task) } + + . = ALIGN(4096); + __init_begin = .; + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + /* .exit.text is discarded at runtime, not link time, + to deal with references from __bug_table */ + .exit.text : { *(.exit.text) } + .init.data : { + *(.init.data); + __vtop_table_begin = .; + *(.vtop_fixup); + __vtop_table_end = .; + __ptov_table_begin = .; + *(.ptov_fixup); + __ptov_table_end = .; + } + . = ALIGN(16); + __setup_start = .; + .init.setup : { *(.init.setup) } + __setup_end = .; + __initcall_start = .; + .initcall.init : { + *(.initcall1.init) + *(.initcall2.init) + *(.initcall3.init) + *(.initcall4.init) + *(.initcall5.init) + *(.initcall6.init) + *(.initcall7.init) + } + __initcall_end = .; + + __con_initcall_start = .; + .con_initcall.init : { *(.con_initcall.init) } + __con_initcall_end = .; + + .security_initcall.init : AT(ADDR(.security_initcall.init) - 0) { __security_initcall_start = .; *(.security_initcall.init) __security_initcall_end = .; } + + __start___ftr_fixup = .; + __ftr_fixup : { *(__ftr_fixup) } + __stop___ftr_fixup = .; + + . = ALIGN(32); + __per_cpu_start = .; + .data.percpu : { *(.data.percpu) } + __per_cpu_end = .; + + . = ALIGN(4096); + __initramfs_start = .; + .init.ramfs : { *(.init.ramfs) } + __initramfs_end = .; + + . = ALIGN(4096); + __init_end = .; + + . = ALIGN(4096); + _sextratext = .; + _eextratext = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_stop = .; + + _end = . ; + PROVIDE (end = .); + + /* Sections to be discarded. */ + /DISCARD/ : { + *(.exitcall.exit) + *(.exit.data) + } +} diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S new file mode 100644 index 00000000000..09c6525cfa6 --- /dev/null +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -0,0 +1,172 @@ +#include + +OUTPUT_ARCH(powerpc:common) +jiffies = jiffies_64 + 4; +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } +/* .init : { *(.init) } =0*/ + .plt : { *(.plt) } + .text : + { + *(.text) + SCHED_TEXT + LOCK_TEXT + *(.fixup) + *(.got1) + __got2_start = .; + *(.got2) + __got2_end = .; + } + _etext = .; + PROVIDE (etext = .); + + RODATA + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + .fixup : { *(.fixup) } + + __ex_table : { + __start___ex_table = .; + *(__ex_table) + __stop___ex_table = .; + } + + __bug_table : { + __start___bug_table = .; + *(__bug_table) + __stop___bug_table = .; + } + + /* Read-write section, merged into data segment: */ + . = ALIGN(4096); + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.got.plt) *(.got) + *(.dynamic) + CONSTRUCTORS + } + + . = ALIGN(4096); + __nosave_begin = .; + .data_nosave : { *(.data.nosave) } + . = ALIGN(4096); + __nosave_end = .; + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + _edata = .; + PROVIDE (edata = .); + + . = ALIGN(8192); + .data.init_task : { *(.data.init_task) } + + . = ALIGN(4096); + __init_begin = .; + .init.text : { + _sinittext = .; + *(.init.text) + _einittext = .; + } + /* .exit.text is discarded at runtime, not link time, + to deal with references from __bug_table */ + .exit.text : { *(.exit.text) } + .init.data : { + *(.init.data); + __vtop_table_begin = .; + *(.vtop_fixup); + __vtop_table_end = .; + __ptov_table_begin = .; + *(.ptov_fixup); + __ptov_table_end = .; + } + . = ALIGN(16); + __setup_start = .; + .init.setup : { *(.init.setup) } + __setup_end = .; + __initcall_start = .; + .initcall.init : { + *(.initcall1.init) + *(.initcall2.init) + *(.initcall3.init) + *(.initcall4.init) + *(.initcall5.init) + *(.initcall6.init) + *(.initcall7.init) + } + __initcall_end = .; + + __con_initcall_start = .; + .con_initcall.init : { *(.con_initcall.init) } + __con_initcall_end = .; + + SECURITY_INIT + + __start___ftr_fixup = .; + __ftr_fixup : { *(__ftr_fixup) } + __stop___ftr_fixup = .; + + . = ALIGN(32); + __per_cpu_start = .; + .data.percpu : { *(.data.percpu) } + __per_cpu_end = .; + + . = ALIGN(4096); + __initramfs_start = .; + .init.ramfs : { *(.init.ramfs) } + __initramfs_end = .; + + . = ALIGN(4096); + __init_end = .; + + . = ALIGN(4096); + _sextratext = .; + _eextratext = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + __bss_stop = .; + + _end = . ; + PROVIDE (end = .); + + /* Sections to be discarded. */ + /DISCARD/ : { + *(.exitcall.exit) + *(.exit.data) + } +} diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile new file mode 100644 index 00000000000..347f9798e43 --- /dev/null +++ b/arch/powerpc/lib/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for ppc-specific library files.. +# + +obj-y := strcase.o string.o +obj-$(CONFIG_PPC32) += div64.o copy32.o checksum.o +obj-$(CONFIG_PPC64) += copypage.o copyuser.o memcpy.o usercopy.o \ + sstep.o checksum64.o +obj-$(CONFIG_PPC_ISERIES) += e2a.o diff --git a/arch/powerpc/lib/checksum.S b/arch/powerpc/lib/checksum.S new file mode 100644 index 00000000000..7874e8a8045 --- /dev/null +++ b/arch/powerpc/lib/checksum.S @@ -0,0 +1,225 @@ +/* + * This file contains assembly-language implementations + * of IP-style 1's complement checksum routines. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au). + */ + +#include +#include +#include +#include + + .text + +/* + * ip_fast_csum(buf, len) -- Optimized for IP header + * len is in words and is always >= 5. + */ +_GLOBAL(ip_fast_csum) + lwz r0,0(r3) + lwzu r5,4(r3) + addic. r4,r4,-2 + addc r0,r0,r5 + mtctr r4 + blelr- +1: lwzu r4,4(r3) + adde r0,r0,r4 + bdnz 1b + addze r0,r0 /* add in final carry */ + rlwinm r3,r0,16,0,31 /* fold two halves together */ + add r3,r0,r3 + not r3,r3 + srwi r3,r3,16 + blr + +/* + * Compute checksum of TCP or UDP pseudo-header: + * csum_tcpudp_magic(saddr, daddr, len, proto, sum) + */ +_GLOBAL(csum_tcpudp_magic) + rlwimi r5,r6,16,0,15 /* put proto in upper half of len */ + addc r0,r3,r4 /* add 4 32-bit words together */ + adde r0,r0,r5 + adde r0,r0,r7 + addze r0,r0 /* add in final carry */ + rlwinm r3,r0,16,0,31 /* fold two halves together */ + add r3,r0,r3 + not r3,r3 + srwi r3,r3,16 + blr + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * csum_partial(buff, len, sum) + */ +_GLOBAL(csum_partial) + addic r0,r5,0 + subi r3,r3,4 + srwi. r6,r4,2 + beq 3f /* if we're doing < 4 bytes */ + andi. r5,r3,2 /* Align buffer to longword boundary */ + beq+ 1f + lhz r5,4(r3) /* do 2 bytes to get aligned */ + addi r3,r3,2 + subi r4,r4,2 + addc r0,r0,r5 + srwi. r6,r4,2 /* # words to do */ + beq 3f +1: mtctr r6 +2: lwzu r5,4(r3) /* the bdnz has zero overhead, so it should */ + adde r0,r0,r5 /* be unnecessary to unroll this loop */ + bdnz 2b + andi. r4,r4,3 +3: cmpwi 0,r4,2 + blt+ 4f + lhz r5,4(r3) + addi r3,r3,2 + subi r4,r4,2 + adde r0,r0,r5 +4: cmpwi 0,r4,1 + bne+ 5f + lbz r5,4(r3) + slwi r5,r5,8 /* Upper byte of word */ + adde r0,r0,r5 +5: addze r3,r0 /* add in final carry */ + blr + +/* + * Computes the checksum of a memory block at src, length len, + * and adds in "sum" (32-bit), while copying the block to dst. + * If an access exception occurs on src or dst, it stores -EFAULT + * to *src_err or *dst_err respectively, and (for an error on + * src) zeroes the rest of dst. + * + * csum_partial_copy_generic(src, dst, len, sum, src_err, dst_err) + */ +_GLOBAL(csum_partial_copy_generic) + addic r0,r6,0 + subi r3,r3,4 + subi r4,r4,4 + srwi. r6,r5,2 + beq 3f /* if we're doing < 4 bytes */ + andi. r9,r4,2 /* Align dst to longword boundary */ + beq+ 1f +81: lhz r6,4(r3) /* do 2 bytes to get aligned */ + addi r3,r3,2 + subi r5,r5,2 +91: sth r6,4(r4) + addi r4,r4,2 + addc r0,r0,r6 + srwi. r6,r5,2 /* # words to do */ + beq 3f +1: srwi. r6,r5,4 /* # groups of 4 words to do */ + beq 10f + mtctr r6 +71: lwz r6,4(r3) +72: lwz r9,8(r3) +73: lwz r10,12(r3) +74: lwzu r11,16(r3) + adde r0,r0,r6 +75: stw r6,4(r4) + adde r0,r0,r9 +76: stw r9,8(r4) + adde r0,r0,r10 +77: stw r10,12(r4) + adde r0,r0,r11 +78: stwu r11,16(r4) + bdnz 71b +10: rlwinm. r6,r5,30,30,31 /* # words left to do */ + beq 13f + mtctr r6 +82: lwzu r9,4(r3) +92: stwu r9,4(r4) + adde r0,r0,r9 + bdnz 82b +13: andi. r5,r5,3 +3: cmpwi 0,r5,2 + blt+ 4f +83: lhz r6,4(r3) + addi r3,r3,2 + subi r5,r5,2 +93: sth r6,4(r4) + addi r4,r4,2 + adde r0,r0,r6 +4: cmpwi 0,r5,1 + bne+ 5f +84: lbz r6,4(r3) +94: stb r6,4(r4) + slwi r6,r6,8 /* Upper byte of word */ + adde r0,r0,r6 +5: addze r3,r0 /* add in final carry */ + blr + +/* These shouldn't go in the fixup section, since that would + cause the ex_table addresses to get out of order. */ + +src_error_4: + mfctr r6 /* update # bytes remaining from ctr */ + rlwimi r5,r6,4,0,27 + b 79f +src_error_1: + li r6,0 + subi r5,r5,2 +95: sth r6,4(r4) + addi r4,r4,2 +79: srwi. r6,r5,2 + beq 3f + mtctr r6 +src_error_2: + li r6,0 +96: stwu r6,4(r4) + bdnz 96b +3: andi. r5,r5,3 + beq src_error +src_error_3: + li r6,0 + mtctr r5 + addi r4,r4,3 +97: stbu r6,1(r4) + bdnz 97b +src_error: + cmpwi 0,r7,0 + beq 1f + li r6,-EFAULT + stw r6,0(r7) +1: addze r3,r0 + blr + +dst_error: + cmpwi 0,r8,0 + beq 1f + li r6,-EFAULT + stw r6,0(r8) +1: addze r3,r0 + blr + +.section __ex_table,"a" + .long 81b,src_error_1 + .long 91b,dst_error + .long 71b,src_error_4 + .long 72b,src_error_4 + .long 73b,src_error_4 + .long 74b,src_error_4 + .long 75b,dst_error + .long 76b,dst_error + .long 77b,dst_error + .long 78b,dst_error + .long 82b,src_error_2 + .long 92b,dst_error + .long 83b,src_error_3 + .long 93b,dst_error + .long 84b,src_error_3 + .long 94b,dst_error + .long 95b,dst_error + .long 96b,dst_error + .long 97b,dst_error diff --git a/arch/powerpc/lib/checksum64.S b/arch/powerpc/lib/checksum64.S new file mode 100644 index 00000000000..ef96c6c58ef --- /dev/null +++ b/arch/powerpc/lib/checksum64.S @@ -0,0 +1,229 @@ +/* + * This file contains assembly-language implementations + * of IP-style 1's complement checksum routines. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Severely hacked about by Paul Mackerras (paulus@cs.anu.edu.au). + */ + +#include +#include +#include +#include + +/* + * ip_fast_csum(r3=buf, r4=len) -- Optimized for IP header + * len is in words and is always >= 5. + * + * In practice len == 5, but this is not guaranteed. So this code does not + * attempt to use doubleword instructions. + */ +_GLOBAL(ip_fast_csum) + lwz r0,0(r3) + lwzu r5,4(r3) + addic. r4,r4,-2 + addc r0,r0,r5 + mtctr r4 + blelr- +1: lwzu r4,4(r3) + adde r0,r0,r4 + bdnz 1b + addze r0,r0 /* add in final carry */ + rldicl r4,r0,32,0 /* fold two 32-bit halves together */ + add r0,r0,r4 + srdi r0,r0,32 + rlwinm r3,r0,16,0,31 /* fold two halves together */ + add r3,r0,r3 + not r3,r3 + srwi r3,r3,16 + blr + +/* + * Compute checksum of TCP or UDP pseudo-header: + * csum_tcpudp_magic(r3=saddr, r4=daddr, r5=len, r6=proto, r7=sum) + * No real gain trying to do this specially for 64 bit, but + * the 32 bit addition may spill into the upper bits of + * the doubleword so we still must fold it down from 64. + */ +_GLOBAL(csum_tcpudp_magic) + rlwimi r5,r6,16,0,15 /* put proto in upper half of len */ + addc r0,r3,r4 /* add 4 32-bit words together */ + adde r0,r0,r5 + adde r0,r0,r7 + rldicl r4,r0,32,0 /* fold 64 bit value */ + add r0,r4,r0 + srdi r0,r0,32 + rlwinm r3,r0,16,0,31 /* fold two halves together */ + add r3,r0,r3 + not r3,r3 + srwi r3,r3,16 + blr + +/* + * Computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit). + * + * This code assumes at least halfword alignment, though the length + * can be any number of bytes. The sum is accumulated in r5. + * + * csum_partial(r3=buff, r4=len, r5=sum) + */ +_GLOBAL(csum_partial) + subi r3,r3,8 /* we'll offset by 8 for the loads */ + srdi. r6,r4,3 /* divide by 8 for doubleword count */ + addic r5,r5,0 /* clear carry */ + beq 3f /* if we're doing < 8 bytes */ + andi. r0,r3,2 /* aligned on a word boundary already? */ + beq+ 1f + lhz r6,8(r3) /* do 2 bytes to get aligned */ + addi r3,r3,2 + subi r4,r4,2 + addc r5,r5,r6 + srdi. r6,r4,3 /* recompute number of doublewords */ + beq 3f /* any left? */ +1: mtctr r6 +2: ldu r6,8(r3) /* main sum loop */ + adde r5,r5,r6 + bdnz 2b + andi. r4,r4,7 /* compute bytes left to sum after doublewords */ +3: cmpwi 0,r4,4 /* is at least a full word left? */ + blt 4f + lwz r6,8(r3) /* sum this word */ + addi r3,r3,4 + subi r4,r4,4 + adde r5,r5,r6 +4: cmpwi 0,r4,2 /* is at least a halfword left? */ + blt+ 5f + lhz r6,8(r3) /* sum this halfword */ + addi r3,r3,2 + subi r4,r4,2 + adde r5,r5,r6 +5: cmpwi 0,r4,1 /* is at least a byte left? */ + bne+ 6f + lbz r6,8(r3) /* sum this byte */ + slwi r6,r6,8 /* this byte is assumed to be the upper byte of a halfword */ + adde r5,r5,r6 +6: addze r5,r5 /* add in final carry */ + rldicl r4,r5,32,0 /* fold two 32-bit halves together */ + add r3,r4,r5 + srdi r3,r3,32 + blr + +/* + * Computes the checksum of a memory block at src, length len, + * and adds in "sum" (32-bit), while copying the block to dst. + * If an access exception occurs on src or dst, it stores -EFAULT + * to *src_err or *dst_err respectively, and (for an error on + * src) zeroes the rest of dst. + * + * This code needs to be reworked to take advantage of 64 bit sum+copy. + * However, due to tokenring halfword alignment problems this will be very + * tricky. For now we'll leave it until we instrument it somehow. + * + * csum_partial_copy_generic(r3=src, r4=dst, r5=len, r6=sum, r7=src_err, r8=dst_err) + */ +_GLOBAL(csum_partial_copy_generic) + addic r0,r6,0 + subi r3,r3,4 + subi r4,r4,4 + srwi. r6,r5,2 + beq 3f /* if we're doing < 4 bytes */ + andi. r9,r4,2 /* Align dst to longword boundary */ + beq+ 1f +81: lhz r6,4(r3) /* do 2 bytes to get aligned */ + addi r3,r3,2 + subi r5,r5,2 +91: sth r6,4(r4) + addi r4,r4,2 + addc r0,r0,r6 + srwi. r6,r5,2 /* # words to do */ + beq 3f +1: mtctr r6 +82: lwzu r6,4(r3) /* the bdnz has zero overhead, so it should */ +92: stwu r6,4(r4) /* be unnecessary to unroll this loop */ + adde r0,r0,r6 + bdnz 82b + andi. r5,r5,3 +3: cmpwi 0,r5,2 + blt+ 4f +83: lhz r6,4(r3) + addi r3,r3,2 + subi r5,r5,2 +93: sth r6,4(r4) + addi r4,r4,2 + adde r0,r0,r6 +4: cmpwi 0,r5,1 + bne+ 5f +84: lbz r6,4(r3) +94: stb r6,4(r4) + slwi r6,r6,8 /* Upper byte of word */ + adde r0,r0,r6 +5: addze r3,r0 /* add in final carry (unlikely with 64-bit regs) */ + rldicl r4,r3,32,0 /* fold 64 bit value */ + add r3,r4,r3 + srdi r3,r3,32 + blr + +/* These shouldn't go in the fixup section, since that would + cause the ex_table addresses to get out of order. */ + + .globl src_error_1 +src_error_1: + li r6,0 + subi r5,r5,2 +95: sth r6,4(r4) + addi r4,r4,2 + srwi. r6,r5,2 + beq 3f + mtctr r6 + .globl src_error_2 +src_error_2: + li r6,0 +96: stwu r6,4(r4) + bdnz 96b +3: andi. r5,r5,3 + beq src_error + .globl src_error_3 +src_error_3: + li r6,0 + mtctr r5 + addi r4,r4,3 +97: stbu r6,1(r4) + bdnz 97b + .globl src_error +src_error: + cmpdi 0,r7,0 + beq 1f + li r6,-EFAULT + stw r6,0(r7) +1: addze r3,r0 + blr + + .globl dst_error +dst_error: + cmpdi 0,r8,0 + beq 1f + li r6,-EFAULT + stw r6,0(r8) +1: addze r3,r0 + blr + +.section __ex_table,"a" + .align 3 + .llong 81b,src_error_1 + .llong 91b,dst_error + .llong 82b,src_error_2 + .llong 92b,dst_error + .llong 83b,src_error_3 + .llong 93b,dst_error + .llong 84b,src_error_3 + .llong 94b,dst_error + .llong 95b,dst_error + .llong 96b,dst_error + .llong 97b,dst_error diff --git a/arch/powerpc/lib/copy32.S b/arch/powerpc/lib/copy32.S new file mode 100644 index 00000000000..420a912198a --- /dev/null +++ b/arch/powerpc/lib/copy32.S @@ -0,0 +1,543 @@ +/* + * Memory copy functions for 32-bit PowerPC. + * + * Copyright (C) 1996-2005 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include + +#define COPY_16_BYTES \ + lwz r7,4(r4); \ + lwz r8,8(r4); \ + lwz r9,12(r4); \ + lwzu r10,16(r4); \ + stw r7,4(r6); \ + stw r8,8(r6); \ + stw r9,12(r6); \ + stwu r10,16(r6) + +#define COPY_16_BYTES_WITHEX(n) \ +8 ## n ## 0: \ + lwz r7,4(r4); \ +8 ## n ## 1: \ + lwz r8,8(r4); \ +8 ## n ## 2: \ + lwz r9,12(r4); \ +8 ## n ## 3: \ + lwzu r10,16(r4); \ +8 ## n ## 4: \ + stw r7,4(r6); \ +8 ## n ## 5: \ + stw r8,8(r6); \ +8 ## n ## 6: \ + stw r9,12(r6); \ +8 ## n ## 7: \ + stwu r10,16(r6) + +#define COPY_16_BYTES_EXCODE(n) \ +9 ## n ## 0: \ + addi r5,r5,-(16 * n); \ + b 104f; \ +9 ## n ## 1: \ + addi r5,r5,-(16 * n); \ + b 105f; \ +.section __ex_table,"a"; \ + .align 2; \ + .long 8 ## n ## 0b,9 ## n ## 0b; \ + .long 8 ## n ## 1b,9 ## n ## 0b; \ + .long 8 ## n ## 2b,9 ## n ## 0b; \ + .long 8 ## n ## 3b,9 ## n ## 0b; \ + .long 8 ## n ## 4b,9 ## n ## 1b; \ + .long 8 ## n ## 5b,9 ## n ## 1b; \ + .long 8 ## n ## 6b,9 ## n ## 1b; \ + .long 8 ## n ## 7b,9 ## n ## 1b; \ + .text + + .text + .stabs "arch/powerpc/lib/",N_SO,0,0,0f + .stabs "copy32.S",N_SO,0,0,0f +0: + +CACHELINE_BYTES = L1_CACHE_LINE_SIZE +LG_CACHELINE_BYTES = LG_L1_CACHE_LINE_SIZE +CACHELINE_MASK = (L1_CACHE_LINE_SIZE-1) + +/* + * Use dcbz on the complete cache lines in the destination + * to set them to zero. This requires that the destination + * area is cacheable. -- paulus + */ +_GLOBAL(cacheable_memzero) + mr r5,r4 + li r4,0 + addi r6,r3,-4 + cmplwi 0,r5,4 + blt 7f + stwu r4,4(r6) + beqlr + andi. r0,r6,3 + add r5,r0,r5 + subf r6,r0,r6 + clrlwi r7,r6,32-LG_CACHELINE_BYTES + add r8,r7,r5 + srwi r9,r8,LG_CACHELINE_BYTES + addic. r9,r9,-1 /* total number of complete cachelines */ + ble 2f + xori r0,r7,CACHELINE_MASK & ~3 + srwi. r0,r0,2 + beq 3f + mtctr r0 +4: stwu r4,4(r6) + bdnz 4b +3: mtctr r9 + li r7,4 +#if !defined(CONFIG_8xx) +10: dcbz r7,r6 +#else +10: stw r4, 4(r6) + stw r4, 8(r6) + stw r4, 12(r6) + stw r4, 16(r6) +#if CACHE_LINE_SIZE >= 32 + stw r4, 20(r6) + stw r4, 24(r6) + stw r4, 28(r6) + stw r4, 32(r6) +#endif /* CACHE_LINE_SIZE */ +#endif + addi r6,r6,CACHELINE_BYTES + bdnz 10b + clrlwi r5,r8,32-LG_CACHELINE_BYTES + addi r5,r5,4 +2: srwi r0,r5,2 + mtctr r0 + bdz 6f +1: stwu r4,4(r6) + bdnz 1b +6: andi. r5,r5,3 +7: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r6,3 +8: stbu r4,1(r6) + bdnz 8b + blr + +_GLOBAL(memset) + rlwimi r4,r4,8,16,23 + rlwimi r4,r4,16,0,15 + addi r6,r3,-4 + cmplwi 0,r5,4 + blt 7f + stwu r4,4(r6) + beqlr + andi. r0,r6,3 + add r5,r0,r5 + subf r6,r0,r6 + srwi r0,r5,2 + mtctr r0 + bdz 6f +1: stwu r4,4(r6) + bdnz 1b +6: andi. r5,r5,3 +7: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r6,3 +8: stbu r4,1(r6) + bdnz 8b + blr + +/* + * This version uses dcbz on the complete cache lines in the + * destination area to reduce memory traffic. This requires that + * the destination area is cacheable. + * We only use this version if the source and dest don't overlap. + * -- paulus. + */ +_GLOBAL(cacheable_memcpy) + add r7,r3,r5 /* test if the src & dst overlap */ + add r8,r4,r5 + cmplw 0,r4,r7 + cmplw 1,r3,r8 + crand 0,0,4 /* cr0.lt &= cr1.lt */ + blt memcpy /* if regions overlap */ + + addi r4,r4,-4 + addi r6,r3,-4 + neg r0,r3 + andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */ + beq 58f + + cmplw 0,r5,r0 /* is this more than total to do? */ + blt 63f /* if not much to do */ + andi. r8,r0,3 /* get it word-aligned first */ + subf r5,r0,r5 + mtctr r8 + beq+ 61f +70: lbz r9,4(r4) /* do some bytes */ + stb r9,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 70b +61: srwi. r0,r0,2 + mtctr r0 + beq 58f +72: lwzu r9,4(r4) /* do some words */ + stwu r9,4(r6) + bdnz 72b + +58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */ + clrlwi r5,r5,32-LG_CACHELINE_BYTES + li r11,4 + mtctr r0 + beq 63f +53: +#if !defined(CONFIG_8xx) + dcbz r11,r6 +#endif + COPY_16_BYTES +#if L1_CACHE_LINE_SIZE >= 32 + COPY_16_BYTES +#if L1_CACHE_LINE_SIZE >= 64 + COPY_16_BYTES + COPY_16_BYTES +#if L1_CACHE_LINE_SIZE >= 128 + COPY_16_BYTES + COPY_16_BYTES + COPY_16_BYTES + COPY_16_BYTES +#endif +#endif +#endif + bdnz 53b + +63: srwi. r0,r5,2 + mtctr r0 + beq 64f +30: lwzu r0,4(r4) + stwu r0,4(r6) + bdnz 30b + +64: andi. r0,r5,3 + mtctr r0 + beq+ 65f +40: lbz r0,4(r4) + stb r0,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 40b +65: blr + +_GLOBAL(memmove) + cmplw 0,r3,r4 + bgt backwards_memcpy + /* fall through */ + +_GLOBAL(memcpy) + srwi. r7,r5,3 + addi r6,r3,-4 + addi r4,r4,-4 + beq 2f /* if less than 8 bytes to do */ + andi. r0,r6,3 /* get dest word aligned */ + mtctr r7 + bne 5f +1: lwz r7,4(r4) + lwzu r8,8(r4) + stw r7,4(r6) + stwu r8,8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,4(r4) + addi r5,r5,-4 + stwu r0,4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r4,r4,3 + addi r6,r6,3 +4: lbzu r0,1(r4) + stbu r0,1(r6) + bdnz 4b + blr +5: subfic r0,r0,4 + mtctr r0 +6: lbz r7,4(r4) + addi r4,r4,1 + stb r7,4(r6) + addi r6,r6,1 + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + +_GLOBAL(backwards_memcpy) + rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ + add r6,r3,r5 + add r4,r4,r5 + beq 2f + andi. r0,r6,3 + mtctr r7 + bne 5f +1: lwz r7,-4(r4) + lwzu r8,-8(r4) + stw r7,-4(r6) + stwu r8,-8(r6) + bdnz 1b + andi. r5,r5,7 +2: cmplwi 0,r5,4 + blt 3f + lwzu r0,-4(r4) + subi r5,r5,4 + stwu r0,-4(r6) +3: cmpwi 0,r5,0 + beqlr + mtctr r5 +4: lbzu r0,-1(r4) + stbu r0,-1(r6) + bdnz 4b + blr +5: mtctr r0 +6: lbzu r7,-1(r4) + stbu r7,-1(r6) + bdnz 6b + subf r5,r0,r5 + rlwinm. r7,r5,32-3,3,31 + beq 2b + mtctr r7 + b 1b + +_GLOBAL(__copy_tofrom_user) + addi r4,r4,-4 + addi r6,r3,-4 + neg r0,r3 + andi. r0,r0,CACHELINE_MASK /* # bytes to start of cache line */ + beq 58f + + cmplw 0,r5,r0 /* is this more than total to do? */ + blt 63f /* if not much to do */ + andi. r8,r0,3 /* get it word-aligned first */ + mtctr r8 + beq+ 61f +70: lbz r9,4(r4) /* do some bytes */ +71: stb r9,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 70b +61: subf r5,r0,r5 + srwi. r0,r0,2 + mtctr r0 + beq 58f +72: lwzu r9,4(r4) /* do some words */ +73: stwu r9,4(r6) + bdnz 72b + + .section __ex_table,"a" + .align 2 + .long 70b,100f + .long 71b,101f + .long 72b,102f + .long 73b,103f + .text + +58: srwi. r0,r5,LG_CACHELINE_BYTES /* # complete cachelines */ + clrlwi r5,r5,32-LG_CACHELINE_BYTES + li r11,4 + beq 63f + +#ifdef CONFIG_8xx + /* Don't use prefetch on 8xx */ + mtctr r0 + li r0,0 +53: COPY_16_BYTES_WITHEX(0) + bdnz 53b + +#else /* not CONFIG_8xx */ + /* Here we decide how far ahead to prefetch the source */ + li r3,4 + cmpwi r0,1 + li r7,0 + ble 114f + li r7,1 +#if MAX_COPY_PREFETCH > 1 + /* Heuristically, for large transfers we prefetch + MAX_COPY_PREFETCH cachelines ahead. For small transfers + we prefetch 1 cacheline ahead. */ + cmpwi r0,MAX_COPY_PREFETCH + ble 112f + li r7,MAX_COPY_PREFETCH +112: mtctr r7 +111: dcbt r3,r4 + addi r3,r3,CACHELINE_BYTES + bdnz 111b +#else + dcbt r3,r4 + addi r3,r3,CACHELINE_BYTES +#endif /* MAX_COPY_PREFETCH > 1 */ + +114: subf r8,r7,r0 + mr r0,r7 + mtctr r8 + +53: dcbt r3,r4 +54: dcbz r11,r6 + .section __ex_table,"a" + .align 2 + .long 54b,105f + .text +/* the main body of the cacheline loop */ + COPY_16_BYTES_WITHEX(0) +#if L1_CACHE_LINE_SIZE >= 32 + COPY_16_BYTES_WITHEX(1) +#if L1_CACHE_LINE_SIZE >= 64 + COPY_16_BYTES_WITHEX(2) + COPY_16_BYTES_WITHEX(3) +#if L1_CACHE_LINE_SIZE >= 128 + COPY_16_BYTES_WITHEX(4) + COPY_16_BYTES_WITHEX(5) + COPY_16_BYTES_WITHEX(6) + COPY_16_BYTES_WITHEX(7) +#endif +#endif +#endif + bdnz 53b + cmpwi r0,0 + li r3,4 + li r7,0 + bne 114b +#endif /* CONFIG_8xx */ + +63: srwi. r0,r5,2 + mtctr r0 + beq 64f +30: lwzu r0,4(r4) +31: stwu r0,4(r6) + bdnz 30b + +64: andi. r0,r5,3 + mtctr r0 + beq+ 65f +40: lbz r0,4(r4) +41: stb r0,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 40b +65: li r3,0 + blr + +/* read fault, initial single-byte copy */ +100: li r9,0 + b 90f +/* write fault, initial single-byte copy */ +101: li r9,1 +90: subf r5,r8,r5 + li r3,0 + b 99f +/* read fault, initial word copy */ +102: li r9,0 + b 91f +/* write fault, initial word copy */ +103: li r9,1 +91: li r3,2 + b 99f + +/* + * this stuff handles faults in the cacheline loop and branches to either + * 104f (if in read part) or 105f (if in write part), after updating r5 + */ + COPY_16_BYTES_EXCODE(0) +#if L1_CACHE_LINE_SIZE >= 32 + COPY_16_BYTES_EXCODE(1) +#if L1_CACHE_LINE_SIZE >= 64 + COPY_16_BYTES_EXCODE(2) + COPY_16_BYTES_EXCODE(3) +#if L1_CACHE_LINE_SIZE >= 128 + COPY_16_BYTES_EXCODE(4) + COPY_16_BYTES_EXCODE(5) + COPY_16_BYTES_EXCODE(6) + COPY_16_BYTES_EXCODE(7) +#endif +#endif +#endif + +/* read fault in cacheline loop */ +104: li r9,0 + b 92f +/* fault on dcbz (effectively a write fault) */ +/* or write fault in cacheline loop */ +105: li r9,1 +92: li r3,LG_CACHELINE_BYTES + mfctr r8 + add r0,r0,r8 + b 106f +/* read fault in final word loop */ +108: li r9,0 + b 93f +/* write fault in final word loop */ +109: li r9,1 +93: andi. r5,r5,3 + li r3,2 + b 99f +/* read fault in final byte loop */ +110: li r9,0 + b 94f +/* write fault in final byte loop */ +111: li r9,1 +94: li r5,0 + li r3,0 +/* + * At this stage the number of bytes not copied is + * r5 + (ctr << r3), and r9 is 0 for read or 1 for write. + */ +99: mfctr r0 +106: slw r3,r0,r3 + add. r3,r3,r5 + beq 120f /* shouldn't happen */ + cmpwi 0,r9,0 + bne 120f +/* for a read fault, first try to continue the copy one byte at a time */ + mtctr r3 +130: lbz r0,4(r4) +131: stb r0,4(r6) + addi r4,r4,1 + addi r6,r6,1 + bdnz 130b +/* then clear out the destination: r3 bytes starting at 4(r6) */ +132: mfctr r3 + srwi. r0,r3,2 + li r9,0 + mtctr r0 + beq 113f +112: stwu r9,4(r6) + bdnz 112b +113: andi. r0,r3,3 + mtctr r0 + beq 120f +114: stb r9,4(r6) + addi r6,r6,1 + bdnz 114b +120: blr + + .section __ex_table,"a" + .align 2 + .long 30b,108b + .long 31b,109b + .long 40b,110b + .long 41b,111b + .long 130b,132b + .long 131b,120b + .long 112b,120b + .long 114b,120b + .text diff --git a/arch/powerpc/lib/copypage.S b/arch/powerpc/lib/copypage.S new file mode 100644 index 00000000000..733d61618bb --- /dev/null +++ b/arch/powerpc/lib/copypage.S @@ -0,0 +1,121 @@ +/* + * arch/ppc64/lib/copypage.S + * + * Copyright (C) 2002 Paul Mackerras, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +_GLOBAL(copy_page) + std r31,-8(1) + std r30,-16(1) + std r29,-24(1) + std r28,-32(1) + std r27,-40(1) + std r26,-48(1) + std r25,-56(1) + std r24,-64(1) + std r23,-72(1) + std r22,-80(1) + std r21,-88(1) + std r20,-96(1) + li r5,4096/32 - 1 + addi r3,r3,-8 + li r12,5 +0: addi r5,r5,-24 + mtctr r12 + ld r22,640(4) + ld r21,512(4) + ld r20,384(4) + ld r11,256(4) + ld r9,128(4) + ld r7,0(4) + ld r25,648(4) + ld r24,520(4) + ld r23,392(4) + ld r10,264(4) + ld r8,136(4) + ldu r6,8(4) + cmpwi r5,24 +1: std r22,648(3) + std r21,520(3) + std r20,392(3) + std r11,264(3) + std r9,136(3) + std r7,8(3) + ld r28,648(4) + ld r27,520(4) + ld r26,392(4) + ld r31,264(4) + ld r30,136(4) + ld r29,8(4) + std r25,656(3) + std r24,528(3) + std r23,400(3) + std r10,272(3) + std r8,144(3) + std r6,16(3) + ld r22,656(4) + ld r21,528(4) + ld r20,400(4) + ld r11,272(4) + ld r9,144(4) + ld r7,16(4) + std r28,664(3) + std r27,536(3) + std r26,408(3) + std r31,280(3) + std r30,152(3) + stdu r29,24(3) + ld r25,664(4) + ld r24,536(4) + ld r23,408(4) + ld r10,280(4) + ld r8,152(4) + ldu r6,24(4) + bdnz 1b + std r22,648(3) + std r21,520(3) + std r20,392(3) + std r11,264(3) + std r9,136(3) + std r7,8(3) + addi r4,r4,640 + addi r3,r3,648 + bge 0b + mtctr r5 + ld r7,0(4) + ld r8,8(4) + ldu r9,16(4) +3: ld r10,8(4) + std r7,8(3) + ld r7,16(4) + std r8,16(3) + ld r8,24(4) + std r9,24(3) + ldu r9,32(4) + stdu r10,32(3) + bdnz 3b +4: ld r10,8(4) + std r7,8(3) + std r8,16(3) + std r9,24(3) + std r10,32(3) +9: ld r20,-96(1) + ld r21,-88(1) + ld r22,-80(1) + ld r23,-72(1) + ld r24,-64(1) + ld r25,-56(1) + ld r26,-48(1) + ld r27,-40(1) + ld r28,-32(1) + ld r29,-24(1) + ld r30,-16(1) + ld r31,-8(1) + blr diff --git a/arch/powerpc/lib/copyuser.S b/arch/powerpc/lib/copyuser.S new file mode 100644 index 00000000000..a0b3fbbd6fb --- /dev/null +++ b/arch/powerpc/lib/copyuser.S @@ -0,0 +1,576 @@ +/* + * arch/ppc64/lib/copyuser.S + * + * Copyright (C) 2002 Paul Mackerras, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + + .align 7 +_GLOBAL(__copy_tofrom_user) + /* first check for a whole page copy on a page boundary */ + cmpldi cr1,r5,16 + cmpdi cr6,r5,4096 + or r0,r3,r4 + neg r6,r3 /* LS 3 bits = # bytes to 8-byte dest bdry */ + andi. r0,r0,4095 + std r3,-24(r1) + crand cr0*4+2,cr0*4+2,cr6*4+2 + std r4,-16(r1) + std r5,-8(r1) + dcbt 0,r4 + beq .Lcopy_page + andi. r6,r6,7 + mtcrf 0x01,r5 + blt cr1,.Lshort_copy + bne .Ldst_unaligned +.Ldst_aligned: + andi. r0,r4,7 + addi r3,r3,-16 + bne .Lsrc_unaligned + srdi r7,r5,4 +20: ld r9,0(r4) + addi r4,r4,-8 + mtctr r7 + andi. r5,r5,7 + bf cr7*4+0,22f + addi r3,r3,8 + addi r4,r4,8 + mr r8,r9 + blt cr1,72f +21: ld r9,8(r4) +70: std r8,8(r3) +22: ldu r8,16(r4) +71: stdu r9,16(r3) + bdnz 21b +72: std r8,8(r3) + beq+ 3f + addi r3,r3,16 +23: ld r9,8(r4) +.Ldo_tail: + bf cr7*4+1,1f + rotldi r9,r9,32 +73: stw r9,0(r3) + addi r3,r3,4 +1: bf cr7*4+2,2f + rotldi r9,r9,16 +74: sth r9,0(r3) + addi r3,r3,2 +2: bf cr7*4+3,3f + rotldi r9,r9,8 +75: stb r9,0(r3) +3: li r3,0 + blr + +.Lsrc_unaligned: + srdi r6,r5,3 + addi r5,r5,-16 + subf r4,r0,r4 + srdi r7,r5,4 + sldi r10,r0,3 + cmpldi cr6,r6,3 + andi. r5,r5,7 + mtctr r7 + subfic r11,r10,64 + add r5,r5,r0 + bt cr7*4+0,28f + +24: ld r9,0(r4) /* 3+2n loads, 2+2n stores */ +25: ld r0,8(r4) + sld r6,r9,r10 +26: ldu r9,16(r4) + srd r7,r0,r11 + sld r8,r0,r10 + or r7,r7,r6 + blt cr6,79f +27: ld r0,8(r4) + b 2f + +28: ld r0,0(r4) /* 4+2n loads, 3+2n stores */ +29: ldu r9,8(r4) + sld r8,r0,r10 + addi r3,r3,-8 + blt cr6,5f +30: ld r0,8(r4) + srd r12,r9,r11 + sld r6,r9,r10 +31: ldu r9,16(r4) + or r12,r8,r12 + srd r7,r0,r11 + sld r8,r0,r10 + addi r3,r3,16 + beq cr6,78f + +1: or r7,r7,r6 +32: ld r0,8(r4) +76: std r12,8(r3) +2: srd r12,r9,r11 + sld r6,r9,r10 +33: ldu r9,16(r4) + or r12,r8,r12 +77: stdu r7,16(r3) + srd r7,r0,r11 + sld r8,r0,r10 + bdnz 1b + +78: std r12,8(r3) + or r7,r7,r6 +79: std r7,16(r3) +5: srd r12,r9,r11 + or r12,r8,r12 +80: std r12,24(r3) + bne 6f + li r3,0 + blr +6: cmpwi cr1,r5,8 + addi r3,r3,32 + sld r9,r9,r10 + ble cr1,.Ldo_tail +34: ld r0,8(r4) + srd r7,r0,r11 + or r9,r7,r9 + b .Ldo_tail + +.Ldst_unaligned: + mtcrf 0x01,r6 /* put #bytes to 8B bdry into cr7 */ + subf r5,r6,r5 + li r7,0 + cmpldi r1,r5,16 + bf cr7*4+3,1f +35: lbz r0,0(r4) +81: stb r0,0(r3) + addi r7,r7,1 +1: bf cr7*4+2,2f +36: lhzx r0,r7,r4 +82: sthx r0,r7,r3 + addi r7,r7,2 +2: bf cr7*4+1,3f +37: lwzx r0,r7,r4 +83: stwx r0,r7,r3 +3: mtcrf 0x01,r5 + add r4,r6,r4 + add r3,r6,r3 + b .Ldst_aligned + +.Lshort_copy: + bf cr7*4+0,1f +38: lwz r0,0(r4) +39: lwz r9,4(r4) + addi r4,r4,8 +84: stw r0,0(r3) +85: stw r9,4(r3) + addi r3,r3,8 +1: bf cr7*4+1,2f +40: lwz r0,0(r4) + addi r4,r4,4 +86: stw r0,0(r3) + addi r3,r3,4 +2: bf cr7*4+2,3f +41: lhz r0,0(r4) + addi r4,r4,2 +87: sth r0,0(r3) + addi r3,r3,2 +3: bf cr7*4+3,4f +42: lbz r0,0(r4) +88: stb r0,0(r3) +4: li r3,0 + blr + +/* + * exception handlers follow + * we have to return the number of bytes not copied + * for an exception on a load, we set the rest of the destination to 0 + */ + +136: +137: + add r3,r3,r7 + b 1f +130: +131: + addi r3,r3,8 +120: +122: +124: +125: +126: +127: +128: +129: +133: + addi r3,r3,8 +121: +132: + addi r3,r3,8 +123: +134: +135: +138: +139: +140: +141: +142: + +/* + * here we have had a fault on a load and r3 points to the first + * unmodified byte of the destination + */ +1: ld r6,-24(r1) + ld r4,-16(r1) + ld r5,-8(r1) + subf r6,r6,r3 + add r4,r4,r6 + subf r5,r6,r5 /* #bytes left to go */ + +/* + * first see if we can copy any more bytes before hitting another exception + */ + mtctr r5 +43: lbz r0,0(r4) + addi r4,r4,1 +89: stb r0,0(r3) + addi r3,r3,1 + bdnz 43b + li r3,0 /* huh? all copied successfully this time? */ + blr + +/* + * here we have trapped again, need to clear ctr bytes starting at r3 + */ +143: mfctr r5 + li r0,0 + mr r4,r3 + mr r3,r5 /* return the number of bytes not copied */ +1: andi. r9,r4,7 + beq 3f +90: stb r0,0(r4) + addic. r5,r5,-1 + addi r4,r4,1 + bne 1b + blr +3: cmpldi cr1,r5,8 + srdi r9,r5,3 + andi. r5,r5,7 + blt cr1,93f + mtctr r9 +91: std r0,0(r4) + addi r4,r4,8 + bdnz 91b +93: beqlr + mtctr r5 +92: stb r0,0(r4) + addi r4,r4,1 + bdnz 92b + blr + +/* + * exception handlers for stores: we just need to work + * out how many bytes weren't copied + */ +182: +183: + add r3,r3,r7 + b 1f +180: + addi r3,r3,8 +171: +177: + addi r3,r3,8 +170: +172: +176: +178: + addi r3,r3,4 +185: + addi r3,r3,4 +173: +174: +175: +179: +181: +184: +186: +187: +188: +189: +1: + ld r6,-24(r1) + ld r5,-8(r1) + add r6,r6,r5 + subf r3,r3,r6 /* #bytes not copied */ +190: +191: +192: + blr /* #bytes not copied in r3 */ + + .section __ex_table,"a" + .align 3 + .llong 20b,120b + .llong 21b,121b + .llong 70b,170b + .llong 22b,122b + .llong 71b,171b + .llong 72b,172b + .llong 23b,123b + .llong 73b,173b + .llong 74b,174b + .llong 75b,175b + .llong 24b,124b + .llong 25b,125b + .llong 26b,126b + .llong 27b,127b + .llong 28b,128b + .llong 29b,129b + .llong 30b,130b + .llong 31b,131b + .llong 32b,132b + .llong 76b,176b + .llong 33b,133b + .llong 77b,177b + .llong 78b,178b + .llong 79b,179b + .llong 80b,180b + .llong 34b,134b + .llong 35b,135b + .llong 81b,181b + .llong 36b,136b + .llong 82b,182b + .llong 37b,137b + .llong 83b,183b + .llong 38b,138b + .llong 39b,139b + .llong 84b,184b + .llong 85b,185b + .llong 40b,140b + .llong 86b,186b + .llong 41b,141b + .llong 87b,187b + .llong 42b,142b + .llong 88b,188b + .llong 43b,143b + .llong 89b,189b + .llong 90b,190b + .llong 91b,191b + .llong 92b,192b + + .text + +/* + * Routine to copy a whole page of data, optimized for POWER4. + * On POWER4 it is more than 50% faster than the simple loop + * above (following the .Ldst_aligned label) but it runs slightly + * slower on POWER3. + */ +.Lcopy_page: + std r31,-32(1) + std r30,-40(1) + std r29,-48(1) + std r28,-56(1) + std r27,-64(1) + std r26,-72(1) + std r25,-80(1) + std r24,-88(1) + std r23,-96(1) + std r22,-104(1) + std r21,-112(1) + std r20,-120(1) + li r5,4096/32 - 1 + addi r3,r3,-8 + li r0,5 +0: addi r5,r5,-24 + mtctr r0 +20: ld r22,640(4) +21: ld r21,512(4) +22: ld r20,384(4) +23: ld r11,256(4) +24: ld r9,128(4) +25: ld r7,0(4) +26: ld r25,648(4) +27: ld r24,520(4) +28: ld r23,392(4) +29: ld r10,264(4) +30: ld r8,136(4) +31: ldu r6,8(4) + cmpwi r5,24 +1: +32: std r22,648(3) +33: std r21,520(3) +34: std r20,392(3) +35: std r11,264(3) +36: std r9,136(3) +37: std r7,8(3) +38: ld r28,648(4) +39: ld r27,520(4) +40: ld r26,392(4) +41: ld r31,264(4) +42: ld r30,136(4) +43: ld r29,8(4) +44: std r25,656(3) +45: std r24,528(3) +46: std r23,400(3) +47: std r10,272(3) +48: std r8,144(3) +49: std r6,16(3) +50: ld r22,656(4) +51: ld r21,528(4) +52: ld r20,400(4) +53: ld r11,272(4) +54: ld r9,144(4) +55: ld r7,16(4) +56: std r28,664(3) +57: std r27,536(3) +58: std r26,408(3) +59: std r31,280(3) +60: std r30,152(3) +61: stdu r29,24(3) +62: ld r25,664(4) +63: ld r24,536(4) +64: ld r23,408(4) +65: ld r10,280(4) +66: ld r8,152(4) +67: ldu r6,24(4) + bdnz 1b +68: std r22,648(3) +69: std r21,520(3) +70: std r20,392(3) +71: std r11,264(3) +72: std r9,136(3) +73: std r7,8(3) +74: addi r4,r4,640 +75: addi r3,r3,648 + bge 0b + mtctr r5 +76: ld r7,0(4) +77: ld r8,8(4) +78: ldu r9,16(4) +3: +79: ld r10,8(4) +80: std r7,8(3) +81: ld r7,16(4) +82: std r8,16(3) +83: ld r8,24(4) +84: std r9,24(3) +85: ldu r9,32(4) +86: stdu r10,32(3) + bdnz 3b +4: +87: ld r10,8(4) +88: std r7,8(3) +89: std r8,16(3) +90: std r9,24(3) +91: std r10,32(3) +9: ld r20,-120(1) + ld r21,-112(1) + ld r22,-104(1) + ld r23,-96(1) + ld r24,-88(1) + ld r25,-80(1) + ld r26,-72(1) + ld r27,-64(1) + ld r28,-56(1) + ld r29,-48(1) + ld r30,-40(1) + ld r31,-32(1) + li r3,0 + blr + +/* + * on an exception, reset to the beginning and jump back into the + * standard __copy_tofrom_user + */ +100: ld r20,-120(1) + ld r21,-112(1) + ld r22,-104(1) + ld r23,-96(1) + ld r24,-88(1) + ld r25,-80(1) + ld r26,-72(1) + ld r27,-64(1) + ld r28,-56(1) + ld r29,-48(1) + ld r30,-40(1) + ld r31,-32(1) + ld r3,-24(r1) + ld r4,-16(r1) + li r5,4096 + b .Ldst_aligned + + .section __ex_table,"a" + .align 3 + .llong 20b,100b + .llong 21b,100b + .llong 22b,100b + .llong 23b,100b + .llong 24b,100b + .llong 25b,100b + .llong 26b,100b + .llong 27b,100b + .llong 28b,100b + .llong 29b,100b + .llong 30b,100b + .llong 31b,100b + .llong 32b,100b + .llong 33b,100b + .llong 34b,100b + .llong 35b,100b + .llong 36b,100b + .llong 37b,100b + .llong 38b,100b + .llong 39b,100b + .llong 40b,100b + .llong 41b,100b + .llong 42b,100b + .llong 43b,100b + .llong 44b,100b + .llong 45b,100b + .llong 46b,100b + .llong 47b,100b + .llong 48b,100b + .llong 49b,100b + .llong 50b,100b + .llong 51b,100b + .llong 52b,100b + .llong 53b,100b + .llong 54b,100b + .llong 55b,100b + .llong 56b,100b + .llong 57b,100b + .llong 58b,100b + .llong 59b,100b + .llong 60b,100b + .llong 61b,100b + .llong 62b,100b + .llong 63b,100b + .llong 64b,100b + .llong 65b,100b + .llong 66b,100b + .llong 67b,100b + .llong 68b,100b + .llong 69b,100b + .llong 70b,100b + .llong 71b,100b + .llong 72b,100b + .llong 73b,100b + .llong 74b,100b + .llong 75b,100b + .llong 76b,100b + .llong 77b,100b + .llong 78b,100b + .llong 79b,100b + .llong 80b,100b + .llong 81b,100b + .llong 82b,100b + .llong 83b,100b + .llong 84b,100b + .llong 85b,100b + .llong 86b,100b + .llong 87b,100b + .llong 88b,100b + .llong 89b,100b + .llong 90b,100b + .llong 91b,100b diff --git a/arch/powerpc/lib/div64.S b/arch/powerpc/lib/div64.S new file mode 100644 index 00000000000..3527569e992 --- /dev/null +++ b/arch/powerpc/lib/div64.S @@ -0,0 +1,58 @@ +/* + * Divide a 64-bit unsigned number by a 32-bit unsigned number. + * This routine assumes that the top 32 bits of the dividend are + * non-zero to start with. + * On entry, r3 points to the dividend, which get overwritten with + * the 64-bit quotient, and r4 contains the divisor. + * On exit, r3 contains the remainder. + * + * Copyright (C) 2002 Paul Mackerras, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +_GLOBAL(__div64_32) + lwz r5,0(r3) # get the dividend into r5/r6 + lwz r6,4(r3) + cmplw r5,r4 + li r7,0 + li r8,0 + blt 1f + divwu r7,r5,r4 # if dividend.hi >= divisor, + mullw r0,r7,r4 # quotient.hi = dividend.hi / divisor + subf. r5,r0,r5 # dividend.hi %= divisor + beq 3f +1: mr r11,r5 # here dividend.hi != 0 + andis. r0,r5,0xc000 + bne 2f + cntlzw r0,r5 # we are shifting the dividend right + li r10,-1 # to make it < 2^32, and shifting + srw r10,r10,r0 # the divisor right the same amount, + add r9,r4,r10 # rounding up (so the estimate cannot + andc r11,r6,r10 # ever be too large, only too small) + andc r9,r9,r10 + or r11,r5,r11 + rotlw r9,r9,r0 + rotlw r11,r11,r0 + divwu r11,r11,r9 # then we divide the shifted quantities +2: mullw r10,r11,r4 # to get an estimate of the quotient, + mulhwu r9,r11,r4 # multiply the estimate by the divisor, + subfc r6,r10,r6 # take the product from the divisor, + add r8,r8,r11 # and add the estimate to the accumulated + subfe. r5,r9,r5 # quotient + bne 1b +3: cmplw r6,r4 + blt 4f + divwu r0,r6,r4 # perform the remaining 32-bit division + mullw r10,r0,r4 # and get the remainder + add r8,r8,r0 + subf r6,r10,r6 +4: stw r7,0(r3) # return the quotient in *r3 + stw r8,4(r3) + mr r3,r6 # return the remainder in r3 + blr diff --git a/arch/powerpc/lib/e2a.c b/arch/powerpc/lib/e2a.c new file mode 100644 index 00000000000..d2b83488792 --- /dev/null +++ b/arch/powerpc/lib/e2a.c @@ -0,0 +1,108 @@ +/* + * arch/ppc64/lib/e2a.c + * + * EBCDIC to ASCII conversion + * + * This function moved here from arch/ppc64/kernel/viopath.c + * + * (C) Copyright 2000-2004 IBM Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) anyu later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include + +unsigned char e2a(unsigned char x) +{ + switch (x) { + case 0xF0: + return '0'; + case 0xF1: + return '1'; + case 0xF2: + return '2'; + case 0xF3: + return '3'; + case 0xF4: + return '4'; + case 0xF5: + return '5'; + case 0xF6: + return '6'; + case 0xF7: + return '7'; + case 0xF8: + return '8'; + case 0xF9: + return '9'; + case 0xC1: + return 'A'; + case 0xC2: + return 'B'; + case 0xC3: + return 'C'; + case 0xC4: + return 'D'; + case 0xC5: + return 'E'; + case 0xC6: + return 'F'; + case 0xC7: + return 'G'; + case 0xC8: + return 'H'; + case 0xC9: + return 'I'; + case 0xD1: + return 'J'; + case 0xD2: + return 'K'; + case 0xD3: + return 'L'; + case 0xD4: + return 'M'; + case 0xD5: + return 'N'; + case 0xD6: + return 'O'; + case 0xD7: + return 'P'; + case 0xD8: + return 'Q'; + case 0xD9: + return 'R'; + case 0xE2: + return 'S'; + case 0xE3: + return 'T'; + case 0xE4: + return 'U'; + case 0xE5: + return 'V'; + case 0xE6: + return 'W'; + case 0xE7: + return 'X'; + case 0xE8: + return 'Y'; + case 0xE9: + return 'Z'; + } + return ' '; +} +EXPORT_SYMBOL(e2a); + + diff --git a/arch/powerpc/lib/memcpy.S b/arch/powerpc/lib/memcpy.S new file mode 100644 index 00000000000..9ccacdf5bcb --- /dev/null +++ b/arch/powerpc/lib/memcpy.S @@ -0,0 +1,172 @@ +/* + * arch/ppc64/lib/memcpy.S + * + * Copyright (C) 2002 Paul Mackerras, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + + .align 7 +_GLOBAL(memcpy) + mtcrf 0x01,r5 + cmpldi cr1,r5,16 + neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry + andi. r6,r6,7 + dcbt 0,r4 + blt cr1,.Lshort_copy + bne .Ldst_unaligned +.Ldst_aligned: + andi. r0,r4,7 + addi r3,r3,-16 + bne .Lsrc_unaligned + srdi r7,r5,4 + ld r9,0(r4) + addi r4,r4,-8 + mtctr r7 + andi. r5,r5,7 + bf cr7*4+0,2f + addi r3,r3,8 + addi r4,r4,8 + mr r8,r9 + blt cr1,3f +1: ld r9,8(r4) + std r8,8(r3) +2: ldu r8,16(r4) + stdu r9,16(r3) + bdnz 1b +3: std r8,8(r3) + beqlr + addi r3,r3,16 + ld r9,8(r4) +.Ldo_tail: + bf cr7*4+1,1f + rotldi r9,r9,32 + stw r9,0(r3) + addi r3,r3,4 +1: bf cr7*4+2,2f + rotldi r9,r9,16 + sth r9,0(r3) + addi r3,r3,2 +2: bf cr7*4+3,3f + rotldi r9,r9,8 + stb r9,0(r3) +3: blr + +.Lsrc_unaligned: + srdi r6,r5,3 + addi r5,r5,-16 + subf r4,r0,r4 + srdi r7,r5,4 + sldi r10,r0,3 + cmpdi cr6,r6,3 + andi. r5,r5,7 + mtctr r7 + subfic r11,r10,64 + add r5,r5,r0 + + bt cr7*4+0,0f + + ld r9,0(r4) # 3+2n loads, 2+2n stores + ld r0,8(r4) + sld r6,r9,r10 + ldu r9,16(r4) + srd r7,r0,r11 + sld r8,r0,r10 + or r7,r7,r6 + blt cr6,4f + ld r0,8(r4) + # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12 + b 2f + +0: ld r0,0(r4) # 4+2n loads, 3+2n stores + ldu r9,8(r4) + sld r8,r0,r10 + addi r3,r3,-8 + blt cr6,5f + ld r0,8(r4) + srd r12,r9,r11 + sld r6,r9,r10 + ldu r9,16(r4) + or r12,r8,r12 + srd r7,r0,r11 + sld r8,r0,r10 + addi r3,r3,16 + beq cr6,3f + + # d0=(s0<<|s1>>) in r12, s1<< in r6, s2>> in r7, s2<< in r8, s3 in r9 +1: or r7,r7,r6 + ld r0,8(r4) + std r12,8(r3) +2: srd r12,r9,r11 + sld r6,r9,r10 + ldu r9,16(r4) + or r12,r8,r12 + stdu r7,16(r3) + srd r7,r0,r11 + sld r8,r0,r10 + bdnz 1b + +3: std r12,8(r3) + or r7,r7,r6 +4: std r7,16(r3) +5: srd r12,r9,r11 + or r12,r8,r12 + std r12,24(r3) + beqlr + cmpwi cr1,r5,8 + addi r3,r3,32 + sld r9,r9,r10 + ble cr1,.Ldo_tail + ld r0,8(r4) + srd r7,r0,r11 + or r9,r7,r9 + b .Ldo_tail + +.Ldst_unaligned: + mtcrf 0x01,r6 # put #bytes to 8B bdry into cr7 + subf r5,r6,r5 + li r7,0 + cmpldi r1,r5,16 + bf cr7*4+3,1f + lbz r0,0(r4) + stb r0,0(r3) + addi r7,r7,1 +1: bf cr7*4+2,2f + lhzx r0,r7,r4 + sthx r0,r7,r3 + addi r7,r7,2 +2: bf cr7*4+1,3f + lwzx r0,r7,r4 + stwx r0,r7,r3 +3: mtcrf 0x01,r5 + add r4,r6,r4 + add r3,r6,r3 + b .Ldst_aligned + +.Lshort_copy: + bf cr7*4+0,1f + lwz r0,0(r4) + lwz r9,4(r4) + addi r4,r4,8 + stw r0,0(r3) + stw r9,4(r3) + addi r3,r3,8 +1: bf cr7*4+1,2f + lwz r0,0(r4) + addi r4,r4,4 + stw r0,0(r3) + addi r3,r3,4 +2: bf cr7*4+2,3f + lhz r0,0(r4) + addi r4,r4,2 + sth r0,0(r3) + addi r3,r3,2 +3: bf cr7*4+3,4f + lbz r0,0(r4) + stb r0,0(r3) +4: blr diff --git a/arch/powerpc/lib/rheap.c b/arch/powerpc/lib/rheap.c new file mode 100644 index 00000000000..42c5de2c898 --- /dev/null +++ b/arch/powerpc/lib/rheap.c @@ -0,0 +1,693 @@ +/* + * arch/ppc/syslib/rheap.c + * + * A Remote Heap. Remote means that we don't touch the memory that the + * heap points to. Normal heap implementations use the memory they manage + * to place their list. We cannot do that because the memory we manage may + * have special properties, for example it is uncachable or of different + * endianess. + * + * Author: Pantelis Antoniou + * + * 2004 (c) INTRACOM S.A. Greece. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include +#include +#include + +#include + +/* + * Fixup a list_head, needed when copying lists. If the pointers fall + * between s and e, apply the delta. This assumes that + * sizeof(struct list_head *) == sizeof(unsigned long *). + */ +static inline void fixup(unsigned long s, unsigned long e, int d, + struct list_head *l) +{ + unsigned long *pp; + + pp = (unsigned long *)&l->next; + if (*pp >= s && *pp < e) + *pp += d; + + pp = (unsigned long *)&l->prev; + if (*pp >= s && *pp < e) + *pp += d; +} + +/* Grow the allocated blocks */ +static int grow(rh_info_t * info, int max_blocks) +{ + rh_block_t *block, *blk; + int i, new_blocks; + int delta; + unsigned long blks, blke; + + if (max_blocks <= info->max_blocks) + return -EINVAL; + + new_blocks = max_blocks - info->max_blocks; + + block = kmalloc(sizeof(rh_block_t) * max_blocks, GFP_KERNEL); + if (block == NULL) + return -ENOMEM; + + if (info->max_blocks > 0) { + + /* copy old block area */ + memcpy(block, info->block, + sizeof(rh_block_t) * info->max_blocks); + + delta = (char *)block - (char *)info->block; + + /* and fixup list pointers */ + blks = (unsigned long)info->block; + blke = (unsigned long)(info->block + info->max_blocks); + + for (i = 0, blk = block; i < info->max_blocks; i++, blk++) + fixup(blks, blke, delta, &blk->list); + + fixup(blks, blke, delta, &info->empty_list); + fixup(blks, blke, delta, &info->free_list); + fixup(blks, blke, delta, &info->taken_list); + + /* free the old allocated memory */ + if ((info->flags & RHIF_STATIC_BLOCK) == 0) + kfree(info->block); + } + + info->block = block; + info->empty_slots += new_blocks; + info->max_blocks = max_blocks; + info->flags &= ~RHIF_STATIC_BLOCK; + + /* add all new blocks to the free list */ + for (i = 0, blk = block + info->max_blocks; i < new_blocks; i++, blk++) + list_add(&blk->list, &info->empty_list); + + return 0; +} + +/* + * Assure at least the required amount of empty slots. If this function + * causes a grow in the block area then all pointers kept to the block + * area are invalid! + */ +static int assure_empty(rh_info_t * info, int slots) +{ + int max_blocks; + + /* This function is not meant to be used to grow uncontrollably */ + if (slots >= 4) + return -EINVAL; + + /* Enough space */ + if (info->empty_slots >= slots) + return 0; + + /* Next 16 sized block */ + max_blocks = ((info->max_blocks + slots) + 15) & ~15; + + return grow(info, max_blocks); +} + +static rh_block_t *get_slot(rh_info_t * info) +{ + rh_block_t *blk; + + /* If no more free slots, and failure to extend. */ + /* XXX: You should have called assure_empty before */ + if (info->empty_slots == 0) { + printk(KERN_ERR "rh: out of slots; crash is imminent.\n"); + return NULL; + } + + /* Get empty slot to use */ + blk = list_entry(info->empty_list.next, rh_block_t, list); + list_del_init(&blk->list); + info->empty_slots--; + + /* Initialize */ + blk->start = NULL; + blk->size = 0; + blk->owner = NULL; + + return blk; +} + +static inline void release_slot(rh_info_t * info, rh_block_t * blk) +{ + list_add(&blk->list, &info->empty_list); + info->empty_slots++; +} + +static void attach_free_block(rh_info_t * info, rh_block_t * blkn) +{ + rh_block_t *blk; + rh_block_t *before; + rh_block_t *after; + rh_block_t *next; + int size; + unsigned long s, e, bs, be; + struct list_head *l; + + /* We assume that they are aligned properly */ + size = blkn->size; + s = (unsigned long)blkn->start; + e = s + size; + + /* Find the blocks immediately before and after the given one + * (if any) */ + before = NULL; + after = NULL; + next = NULL; + + list_for_each(l, &info->free_list) { + blk = list_entry(l, rh_block_t, list); + + bs = (unsigned long)blk->start; + be = bs + blk->size; + + if (next == NULL && s >= bs) + next = blk; + + if (be == s) + before = blk; + + if (e == bs) + after = blk; + + /* If both are not null, break now */ + if (before != NULL && after != NULL) + break; + } + + /* Now check if they are really adjacent */ + if (before != NULL && s != (unsigned long)before->start + before->size) + before = NULL; + + if (after != NULL && e != (unsigned long)after->start) + after = NULL; + + /* No coalescing; list insert and return */ + if (before == NULL && after == NULL) { + + if (next != NULL) + list_add(&blkn->list, &next->list); + else + list_add(&blkn->list, &info->free_list); + + return; + } + + /* We don't need it anymore */ + release_slot(info, blkn); + + /* Grow the before block */ + if (before != NULL && after == NULL) { + before->size += size; + return; + } + + /* Grow the after block backwards */ + if (before == NULL && after != NULL) { + after->start = (int8_t *)after->start - size; + after->size += size; + return; + } + + /* Grow the before block, and release the after block */ + before->size += size + after->size; + list_del(&after->list); + release_slot(info, after); +} + +static void attach_taken_block(rh_info_t * info, rh_block_t * blkn) +{ + rh_block_t *blk; + struct list_head *l; + + /* Find the block immediately before the given one (if any) */ + list_for_each(l, &info->taken_list) { + blk = list_entry(l, rh_block_t, list); + if (blk->start > blkn->start) { + list_add_tail(&blkn->list, &blk->list); + return; + } + } + + list_add_tail(&blkn->list, &info->taken_list); +} + +/* + * Create a remote heap dynamically. Note that no memory for the blocks + * are allocated. It will upon the first allocation + */ +rh_info_t *rh_create(unsigned int alignment) +{ + rh_info_t *info; + + /* Alignment must be a power of two */ + if ((alignment & (alignment - 1)) != 0) + return ERR_PTR(-EINVAL); + + info = kmalloc(sizeof(*info), GFP_KERNEL); + if (info == NULL) + return ERR_PTR(-ENOMEM); + + info->alignment = alignment; + + /* Initially everything as empty */ + info->block = NULL; + info->max_blocks = 0; + info->empty_slots = 0; + info->flags = 0; + + INIT_LIST_HEAD(&info->empty_list); + INIT_LIST_HEAD(&info->free_list); + INIT_LIST_HEAD(&info->taken_list); + + return info; +} + +/* + * Destroy a dynamically created remote heap. Deallocate only if the areas + * are not static + */ +void rh_destroy(rh_info_t * info) +{ + if ((info->flags & RHIF_STATIC_BLOCK) == 0 && info->block != NULL) + kfree(info->block); + + if ((info->flags & RHIF_STATIC_INFO) == 0) + kfree(info); +} + +/* + * Initialize in place a remote heap info block. This is needed to support + * operation very early in the startup of the kernel, when it is not yet safe + * to call kmalloc. + */ +void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks, + rh_block_t * block) +{ + int i; + rh_block_t *blk; + + /* Alignment must be a power of two */ + if ((alignment & (alignment - 1)) != 0) + return; + + info->alignment = alignment; + + /* Initially everything as empty */ + info->block = block; + info->max_blocks = max_blocks; + info->empty_slots = max_blocks; + info->flags = RHIF_STATIC_INFO | RHIF_STATIC_BLOCK; + + INIT_LIST_HEAD(&info->empty_list); + INIT_LIST_HEAD(&info->free_list); + INIT_LIST_HEAD(&info->taken_list); + + /* Add all new blocks to the free list */ + for (i = 0, blk = block; i < max_blocks; i++, blk++) + list_add(&blk->list, &info->empty_list); +} + +/* Attach a free memory region, coalesces regions if adjuscent */ +int rh_attach_region(rh_info_t * info, void *start, int size) +{ + rh_block_t *blk; + unsigned long s, e, m; + int r; + + /* The region must be aligned */ + s = (unsigned long)start; + e = s + size; + m = info->alignment - 1; + + /* Round start up */ + s = (s + m) & ~m; + + /* Round end down */ + e = e & ~m; + + /* Take final values */ + start = (void *)s; + size = (int)(e - s); + + /* Grow the blocks, if needed */ + r = assure_empty(info, 1); + if (r < 0) + return r; + + blk = get_slot(info); + blk->start = start; + blk->size = size; + blk->owner = NULL; + + attach_free_block(info, blk); + + return 0; +} + +/* Detatch given address range, splits free block if needed. */ +void *rh_detach_region(rh_info_t * info, void *start, int size) +{ + struct list_head *l; + rh_block_t *blk, *newblk; + unsigned long s, e, m, bs, be; + + /* Validate size */ + if (size <= 0) + return ERR_PTR(-EINVAL); + + /* The region must be aligned */ + s = (unsigned long)start; + e = s + size; + m = info->alignment - 1; + + /* Round start up */ + s = (s + m) & ~m; + + /* Round end down */ + e = e & ~m; + + if (assure_empty(info, 1) < 0) + return ERR_PTR(-ENOMEM); + + blk = NULL; + list_for_each(l, &info->free_list) { + blk = list_entry(l, rh_block_t, list); + /* The range must lie entirely inside one free block */ + bs = (unsigned long)blk->start; + be = (unsigned long)blk->start + blk->size; + if (s >= bs && e <= be) + break; + blk = NULL; + } + + if (blk == NULL) + return ERR_PTR(-ENOMEM); + + /* Perfect fit */ + if (bs == s && be == e) { + /* Delete from free list, release slot */ + list_del(&blk->list); + release_slot(info, blk); + return (void *)s; + } + + /* blk still in free list, with updated start and/or size */ + if (bs == s || be == e) { + if (bs == s) + blk->start = (int8_t *)blk->start + size; + blk->size -= size; + + } else { + /* The front free fragment */ + blk->size = s - bs; + + /* the back free fragment */ + newblk = get_slot(info); + newblk->start = (void *)e; + newblk->size = be - e; + + list_add(&newblk->list, &blk->list); + } + + return (void *)s; +} + +void *rh_alloc(rh_info_t * info, int size, const char *owner) +{ + struct list_head *l; + rh_block_t *blk; + rh_block_t *newblk; + void *start; + + /* Validate size */ + if (size <= 0) + return ERR_PTR(-EINVAL); + + /* Align to configured alignment */ + size = (size + (info->alignment - 1)) & ~(info->alignment - 1); + + if (assure_empty(info, 1) < 0) + return ERR_PTR(-ENOMEM); + + blk = NULL; + list_for_each(l, &info->free_list) { + blk = list_entry(l, rh_block_t, list); + if (size <= blk->size) + break; + blk = NULL; + } + + if (blk == NULL) + return ERR_PTR(-ENOMEM); + + /* Just fits */ + if (blk->size == size) { + /* Move from free list to taken list */ + list_del(&blk->list); + blk->owner = owner; + start = blk->start; + + attach_taken_block(info, blk); + + return start; + } + + newblk = get_slot(info); + newblk->start = blk->start; + newblk->size = size; + newblk->owner = owner; + + /* blk still in free list, with updated start, size */ + blk->start = (int8_t *)blk->start + size; + blk->size -= size; + + start = newblk->start; + + attach_taken_block(info, newblk); + + return start; +} + +/* allocate at precisely the given address */ +void *rh_alloc_fixed(rh_info_t * info, void *start, int size, const char *owner) +{ + struct list_head *l; + rh_block_t *blk, *newblk1, *newblk2; + unsigned long s, e, m, bs, be; + + /* Validate size */ + if (size <= 0) + return ERR_PTR(-EINVAL); + + /* The region must be aligned */ + s = (unsigned long)start; + e = s + size; + m = info->alignment - 1; + + /* Round start up */ + s = (s + m) & ~m; + + /* Round end down */ + e = e & ~m; + + if (assure_empty(info, 2) < 0) + return ERR_PTR(-ENOMEM); + + blk = NULL; + list_for_each(l, &info->free_list) { + blk = list_entry(l, rh_block_t, list); + /* The range must lie entirely inside one free block */ + bs = (unsigned long)blk->start; + be = (unsigned long)blk->start + blk->size; + if (s >= bs && e <= be) + break; + } + + if (blk == NULL) + return ERR_PTR(-ENOMEM); + + /* Perfect fit */ + if (bs == s && be == e) { + /* Move from free list to taken list */ + list_del(&blk->list); + blk->owner = owner; + + start = blk->start; + attach_taken_block(info, blk); + + return start; + + } + + /* blk still in free list, with updated start and/or size */ + if (bs == s || be == e) { + if (bs == s) + blk->start = (int8_t *)blk->start + size; + blk->size -= size; + + } else { + /* The front free fragment */ + blk->size = s - bs; + + /* The back free fragment */ + newblk2 = get_slot(info); + newblk2->start = (void *)e; + newblk2->size = be - e; + + list_add(&newblk2->list, &blk->list); + } + + newblk1 = get_slot(info); + newblk1->start = (void *)s; + newblk1->size = e - s; + newblk1->owner = owner; + + start = newblk1->start; + attach_taken_block(info, newblk1); + + return start; +} + +int rh_free(rh_info_t * info, void *start) +{ + rh_block_t *blk, *blk2; + struct list_head *l; + int size; + + /* Linear search for block */ + blk = NULL; + list_for_each(l, &info->taken_list) { + blk2 = list_entry(l, rh_block_t, list); + if (start < blk2->start) + break; + blk = blk2; + } + + if (blk == NULL || start > (blk->start + blk->size)) + return -EINVAL; + + /* Remove from taken list */ + list_del(&blk->list); + + /* Get size of freed block */ + size = blk->size; + attach_free_block(info, blk); + + return size; +} + +int rh_get_stats(rh_info_t * info, int what, int max_stats, rh_stats_t * stats) +{ + rh_block_t *blk; + struct list_head *l; + struct list_head *h; + int nr; + + switch (what) { + + case RHGS_FREE: + h = &info->free_list; + break; + + case RHGS_TAKEN: + h = &info->taken_list; + break; + + default: + return -EINVAL; + } + + /* Linear search for block */ + nr = 0; + list_for_each(l, h) { + blk = list_entry(l, rh_block_t, list); + if (stats != NULL && nr < max_stats) { + stats->start = blk->start; + stats->size = blk->size; + stats->owner = blk->owner; + stats++; + } + nr++; + } + + return nr; +} + +int rh_set_owner(rh_info_t * info, void *start, const char *owner) +{ + rh_block_t *blk, *blk2; + struct list_head *l; + int size; + + /* Linear search for block */ + blk = NULL; + list_for_each(l, &info->taken_list) { + blk2 = list_entry(l, rh_block_t, list); + if (start < blk2->start) + break; + blk = blk2; + } + + if (blk == NULL || start > (blk->start + blk->size)) + return -EINVAL; + + blk->owner = owner; + size = blk->size; + + return size; +} + +void rh_dump(rh_info_t * info) +{ + static rh_stats_t st[32]; /* XXX maximum 32 blocks */ + int maxnr; + int i, nr; + + maxnr = sizeof(st) / sizeof(st[0]); + + printk(KERN_INFO + "info @0x%p (%d slots empty / %d max)\n", + info, info->empty_slots, info->max_blocks); + + printk(KERN_INFO " Free:\n"); + nr = rh_get_stats(info, RHGS_FREE, maxnr, st); + if (nr > maxnr) + nr = maxnr; + for (i = 0; i < nr; i++) + printk(KERN_INFO + " 0x%p-0x%p (%u)\n", + st[i].start, (int8_t *) st[i].start + st[i].size, + st[i].size); + printk(KERN_INFO "\n"); + + printk(KERN_INFO " Taken:\n"); + nr = rh_get_stats(info, RHGS_TAKEN, maxnr, st); + if (nr > maxnr) + nr = maxnr; + for (i = 0; i < nr; i++) + printk(KERN_INFO + " 0x%p-0x%p (%u) %s\n", + st[i].start, (int8_t *) st[i].start + st[i].size, + st[i].size, st[i].owner != NULL ? st[i].owner : ""); + printk(KERN_INFO "\n"); +} + +void rh_dump_blk(rh_info_t * info, rh_block_t * blk) +{ + printk(KERN_INFO + "blk @0x%p: 0x%p-0x%p (%u)\n", + blk, blk->start, (int8_t *) blk->start + blk->size, blk->size); +} diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c new file mode 100644 index 00000000000..e79123d1485 --- /dev/null +++ b/arch/powerpc/lib/sstep.c @@ -0,0 +1,141 @@ +/* + * Single-step support. + * + * Copyright (C) 2004 Paul Mackerras , IBM + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include + +extern char system_call_common[]; + +/* Bits in SRR1 that are copied from MSR */ +#define MSR_MASK 0xffffffff87c0ffff + +/* + * Determine whether a conditional branch instruction would branch. + */ +static int branch_taken(unsigned int instr, struct pt_regs *regs) +{ + unsigned int bo = (instr >> 21) & 0x1f; + unsigned int bi; + + if ((bo & 4) == 0) { + /* decrement counter */ + --regs->ctr; + if (((bo >> 1) & 1) ^ (regs->ctr == 0)) + return 0; + } + if ((bo & 0x10) == 0) { + /* check bit from CR */ + bi = (instr >> 16) & 0x1f; + if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) + return 0; + } + return 1; +} + +/* + * Emulate instructions that cause a transfer of control. + * Returns 1 if the step was emulated, 0 if not, + * or -1 if the instruction is one that should not be stepped, + * such as an rfid, or a mtmsrd that would clear MSR_RI. + */ +int emulate_step(struct pt_regs *regs, unsigned int instr) +{ + unsigned int opcode, rd; + unsigned long int imm; + + opcode = instr >> 26; + switch (opcode) { + case 16: /* bc */ + imm = (signed short)(instr & 0xfffc); + if ((instr & 2) == 0) + imm += regs->nip; + regs->nip += 4; + if ((regs->msr & MSR_SF) == 0) + regs->nip &= 0xffffffffUL; + if (instr & 1) + regs->link = regs->nip; + if (branch_taken(instr, regs)) + regs->nip = imm; + return 1; + case 17: /* sc */ + /* + * N.B. this uses knowledge about how the syscall + * entry code works. If that is changed, this will + * need to be changed also. + */ + regs->gpr[9] = regs->gpr[13]; + regs->gpr[11] = regs->nip + 4; + regs->gpr[12] = regs->msr & MSR_MASK; + regs->gpr[13] = (unsigned long) get_paca(); + regs->nip = (unsigned long) &system_call_common; + regs->msr = MSR_KERNEL; + return 1; + case 18: /* b */ + imm = instr & 0x03fffffc; + if (imm & 0x02000000) + imm -= 0x04000000; + if ((instr & 2) == 0) + imm += regs->nip; + if (instr & 1) { + regs->link = regs->nip + 4; + if ((regs->msr & MSR_SF) == 0) + regs->link &= 0xffffffffUL; + } + if ((regs->msr & MSR_SF) == 0) + imm &= 0xffffffffUL; + regs->nip = imm; + return 1; + case 19: + switch (instr & 0x7fe) { + case 0x20: /* bclr */ + case 0x420: /* bcctr */ + imm = (instr & 0x400)? regs->ctr: regs->link; + regs->nip += 4; + if ((regs->msr & MSR_SF) == 0) { + regs->nip &= 0xffffffffUL; + imm &= 0xffffffffUL; + } + if (instr & 1) + regs->link = regs->nip; + if (branch_taken(instr, regs)) + regs->nip = imm; + return 1; + case 0x24: /* rfid, scary */ + return -1; + } + case 31: + rd = (instr >> 21) & 0x1f; + switch (instr & 0x7fe) { + case 0xa6: /* mfmsr */ + regs->gpr[rd] = regs->msr & MSR_MASK; + regs->nip += 4; + if ((regs->msr & MSR_SF) == 0) + regs->nip &= 0xffffffffUL; + return 1; + case 0x164: /* mtmsrd */ + /* only MSR_EE and MSR_RI get changed if bit 15 set */ + /* mtmsrd doesn't change MSR_HV and MSR_ME */ + imm = (instr & 0x10000)? 0x8002: 0xefffffffffffefffUL; + imm = (regs->msr & MSR_MASK & ~imm) + | (regs->gpr[rd] & imm); + if ((imm & MSR_RI) == 0) + /* can't step mtmsrd that would clear MSR_RI */ + return -1; + regs->msr = imm; + regs->nip += 4; + if ((imm & MSR_SF) == 0) + regs->nip &= 0xffffffffUL; + return 1; + } + } + return 0; +} diff --git a/arch/powerpc/lib/strcase.c b/arch/powerpc/lib/strcase.c new file mode 100644 index 00000000000..36b521091bb --- /dev/null +++ b/arch/powerpc/lib/strcase.c @@ -0,0 +1,23 @@ +#include + +int strcasecmp(const char *s1, const char *s2) +{ + int c1, c2; + + do { + c1 = tolower(*s1++); + c2 = tolower(*s2++); + } while (c1 == c2 && c1 != 0); + return c1 - c2; +} + +int strncasecmp(const char *s1, const char *s2, int n) +{ + int c1, c2; + + do { + c1 = tolower(*s1++); + c2 = tolower(*s2++); + } while ((--n > 0) && c1 == c2 && c1 != 0); + return c1 - c2; +} diff --git a/arch/powerpc/lib/string.S b/arch/powerpc/lib/string.S new file mode 100644 index 00000000000..15d40e9ef8b --- /dev/null +++ b/arch/powerpc/lib/string.S @@ -0,0 +1,203 @@ +/* + * String handling functions for PowerPC. + * + * Copyright (C) 1996 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include + + .text + .stabs "arch/powerpc/lib/",N_SO,0,0,0f + .stabs "string.S",N_SO,0,0,0f +0: + + .section __ex_table,"a" +#ifdef CONFIG_PPC64 + .align 3 +#define EXTBL .llong +#else + .align 2 +#define EXTBL .long +#endif + .text + +_GLOBAL(strcpy) + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + +/* This clears out any unused part of the destination buffer, + just as the libc version does. -- paulus */ +_GLOBAL(strncpy) + cmpwi 0,r5,0 + beqlr + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r6) + bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ + bnelr /* if we didn't hit a null char, we're done */ + mfctr r5 + cmpwi 0,r5,0 /* any space left in destination buffer? */ + beqlr /* we know r0 == 0 here */ +2: stbu r0,1(r6) /* clear it out if so */ + bdnz 2b + blr + +_GLOBAL(strcat) + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r0,1(r5) + cmpwi 0,r0,0 + bne 1b + addi r5,r5,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r5) + bne 1b + blr + +_GLOBAL(strcmp) + addi r5,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r5) + cmpwi 1,r3,0 + lbzu r0,1(r4) + subf. r3,r0,r3 + beqlr 1 + beq 1b + blr + +_GLOBAL(strlen) + addi r4,r3,-1 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + bne 1b + subf r3,r3,r4 + blr + +_GLOBAL(memcmp) + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r6,r3,-1 + addi r4,r4,-1 +1: lbzu r3,1(r6) + lbzu r0,1(r4) + subf. r3,r0,r3 + bdnzt 2,1b + blr +2: li r3,0 + blr + +_GLOBAL(memchr) + cmpwi 0,r5,0 + ble- 2f + mtctr r5 + addi r3,r3,-1 +1: lbzu r0,1(r3) + cmpw 0,r0,r4 + bdnzf 2,1b + beqlr +2: li r3,0 + blr + +_GLOBAL(__clear_user) + addi r6,r3,-4 + li r3,0 + li r5,0 + cmplwi 0,r4,4 + blt 7f + /* clear a single word */ +11: stwu r5,4(r6) + beqlr + /* clear word sized chunks */ + andi. r0,r6,3 + add r4,r0,r4 + subf r6,r0,r6 + srwi r0,r4,2 + andi. r4,r4,3 + mtctr r0 + bdz 7f +1: stwu r5,4(r6) + bdnz 1b + /* clear byte sized chunks */ +7: cmpwi 0,r4,0 + beqlr + mtctr r4 + addi r6,r6,3 +8: stbu r5,1(r6) + bdnz 8b + blr +90: mr r3,r4 + blr +91: mfctr r3 + slwi r3,r3,2 + add r3,r3,r4 + blr +92: mfctr r3 + blr + + .section __ex_table,"a" + EXTBL 11b,90b + EXTBL 1b,91b + EXTBL 8b,92b + .text + +_GLOBAL(__strncpy_from_user) + addi r6,r3,-1 + addi r4,r4,-1 + cmpwi 0,r5,0 + beq 2f + mtctr r5 +1: lbzu r0,1(r4) + cmpwi 0,r0,0 + stbu r0,1(r6) + bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ + beq 3f +2: addi r6,r6,1 +3: subf r3,r3,r6 + blr +99: li r3,-EFAULT + blr + + .section __ex_table,"a" + EXTBL 1b,99b + .text + +/* r3 = str, r4 = len (> 0), r5 = top (highest addr) */ +_GLOBAL(__strnlen_user) + addi r7,r3,-1 + subf r6,r7,r5 /* top+1 - str */ + cmplw 0,r4,r6 + bge 0f + mr r6,r4 +0: mtctr r6 /* ctr = min(len, top - str) */ +1: lbzu r0,1(r7) /* get next byte */ + cmpwi 0,r0,0 + bdnzf 2,1b /* loop if --ctr != 0 && byte != 0 */ + addi r7,r7,1 + subf r3,r3,r7 /* number of bytes we have looked at */ + beqlr /* return if we found a 0 byte */ + cmpw 0,r3,r4 /* did we look at all len bytes? */ + blt 99f /* if not, must have hit top */ + addi r3,r4,1 /* return len + 1 to indicate no null found */ + blr +99: li r3,0 /* bad address, return 0 */ + blr + + .section __ex_table,"a" + EXTBL 1b,99b diff --git a/arch/powerpc/lib/usercopy.c b/arch/powerpc/lib/usercopy.c new file mode 100644 index 00000000000..5eea6f3c1e0 --- /dev/null +++ b/arch/powerpc/lib/usercopy.c @@ -0,0 +1,41 @@ +/* + * Functions which are too large to be inlined. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +unsigned long copy_from_user(void *to, const void __user *from, unsigned long n) +{ + if (likely(access_ok(VERIFY_READ, from, n))) + n = __copy_from_user(to, from, n); + else + memset(to, 0, n); + return n; +} + +unsigned long copy_to_user(void __user *to, const void *from, unsigned long n) +{ + if (likely(access_ok(VERIFY_WRITE, to, n))) + n = __copy_to_user(to, from, n); + return n; +} + +unsigned long copy_in_user(void __user *to, const void __user *from, + unsigned long n) +{ + might_sleep(); + if (likely(access_ok(VERIFY_READ, from, n) && + access_ok(VERIFY_WRITE, to, n))) + n =__copy_tofrom_user(to, from, n); + return n; +} + +EXPORT_SYMBOL(copy_from_user); +EXPORT_SYMBOL(copy_to_user); +EXPORT_SYMBOL(copy_in_user); + diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c new file mode 100644 index 00000000000..3d79ce281b6 --- /dev/null +++ b/arch/powerpc/mm/44x_mmu.c @@ -0,0 +1,120 @@ +/* + * Modifications by Matt Porter (mporter@mvista.com) to support + * PPC44x Book E processors. + * + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mmu_decl.h" + +extern char etext[], _stext[]; + +/* Used by the 44x TLB replacement exception handler. + * Just needed it declared someplace. + */ +unsigned int tlb_44x_index = 0; +unsigned int tlb_44x_hwater = 62; + +/* + * "Pins" a 256MB TLB entry in AS0 for kernel lowmem + */ +static void __init +ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys) +{ + unsigned long attrib = 0; + + __asm__ __volatile__("\ + clrrwi %2,%2,10\n\ + ori %2,%2,%4\n\ + clrrwi %1,%1,10\n\ + li %0,0\n\ + ori %0,%0,%5\n\ + tlbwe %2,%3,%6\n\ + tlbwe %1,%3,%7\n\ + tlbwe %0,%3,%8" + : + : "r" (attrib), "r" (phys), "r" (virt), "r" (slot), + "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M), + "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G), + "i" (PPC44x_TLB_PAGEID), + "i" (PPC44x_TLB_XLAT), + "i" (PPC44x_TLB_ATTRIB)); +} + +/* + * MMU_init_hw does the chip-specific initialization of the MMU hardware. + */ +void __init MMU_init_hw(void) +{ + flush_instruction_cache(); +} + +unsigned long __init mmu_mapin_ram(void) +{ + unsigned int pinned_tlbs = 1; + int i; + + /* Determine number of entries necessary to cover lowmem */ + pinned_tlbs = (unsigned int) + (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT); + + /* Write upper watermark to save location */ + tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs; + + /* If necessary, set additional pinned TLBs */ + if (pinned_tlbs > 1) + for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { + unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE; + ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); + } + + return total_lowmem; +} diff --git a/arch/powerpc/mm/4xx_mmu.c b/arch/powerpc/mm/4xx_mmu.c new file mode 100644 index 00000000000..b7bcbc232f3 --- /dev/null +++ b/arch/powerpc/mm/4xx_mmu.c @@ -0,0 +1,141 @@ +/* + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mmu_decl.h" + +extern int __map_without_ltlbs; +/* + * MMU_init_hw does the chip-specific initialization of the MMU hardware. + */ +void __init MMU_init_hw(void) +{ + /* + * The Zone Protection Register (ZPR) defines how protection will + * be applied to every page which is a member of a given zone. At + * present, we utilize only two of the 4xx's zones. + * The zone index bits (of ZSEL) in the PTE are used for software + * indicators, except the LSB. For user access, zone 1 is used, + * for kernel access, zone 0 is used. We set all but zone 1 + * to zero, allowing only kernel access as indicated in the PTE. + * For zone 1, we set a 01 binary (a value of 10 will not work) + * to allow user access as indicated in the PTE. This also allows + * kernel access as indicated in the PTE. + */ + + mtspr(SPRN_ZPR, 0x10000000); + + flush_instruction_cache(); + + /* + * Set up the real-mode cache parameters for the exception vector + * handlers (which are run in real-mode). + */ + + mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ + + /* + * Cache instruction and data space where the exception + * vectors and the kernel live in real-mode. + */ + + mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ + mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ +} + +#define LARGE_PAGE_SIZE_16M (1<<24) +#define LARGE_PAGE_SIZE_4M (1<<22) + +unsigned long __init mmu_mapin_ram(void) +{ + unsigned long v, s; + phys_addr_t p; + + v = KERNELBASE; + p = PPC_MEMSTART; + s = 0; + + if (__map_without_ltlbs) { + return s; + } + + while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) { + pmd_t *pmdp; + unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE; + + spin_lock(&init_mm.page_table_lock); + pmdp = pmd_offset(pgd_offset_k(v), v); + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + pmd_val(*pmdp++) = val; + spin_unlock(&init_mm.page_table_lock); + + v += LARGE_PAGE_SIZE_16M; + p += LARGE_PAGE_SIZE_16M; + s += LARGE_PAGE_SIZE_16M; + } + + while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) { + pmd_t *pmdp; + unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE; + + spin_lock(&init_mm.page_table_lock); + pmdp = pmd_offset(pgd_offset_k(v), v); + pmd_val(*pmdp) = val; + spin_unlock(&init_mm.page_table_lock); + + v += LARGE_PAGE_SIZE_4M; + p += LARGE_PAGE_SIZE_4M; + s += LARGE_PAGE_SIZE_4M; + } + + return s; +} diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile new file mode 100644 index 00000000000..9f52c26acd8 --- /dev/null +++ b/arch/powerpc/mm/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for the linux ppc-specific parts of the memory manager. +# + +obj-y := fault.o mem.o +obj-$(CONFIG_PPC32) += init.o pgtable.o mmu_context.o \ + mem_pieces.o tlb.o +obj-$(CONFIG_PPC64) += init64.o pgtable64.o mmu_context64.o +obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu.o hash_32.o +obj-$(CONFIG_40x) += 4xx_mmu.o +obj-$(CONFIG_44x) += 44x_mmu.o +obj-$(CONFIG_FSL_BOOKE) += fsl_booke_mmu.o diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c new file mode 100644 index 00000000000..3df641fa789 --- /dev/null +++ b/arch/powerpc/mm/fault.c @@ -0,0 +1,391 @@ +/* + * arch/ppc/mm/fault.c + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Derived from "arch/i386/mm/fault.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Modified by Cort Dougan and Paul Mackerras. + * + * Modified for PPC64 by Dave Engebretsen (engebret@ibm.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Check whether the instruction at regs->nip is a store using + * an update addressing form which will update r1. + */ +static int store_updates_sp(struct pt_regs *regs) +{ + unsigned int inst; + + if (get_user(inst, (unsigned int __user *)regs->nip)) + return 0; + /* check for 1 in the rA field */ + if (((inst >> 16) & 0x1f) != 1) + return 0; + /* check major opcode */ + switch (inst >> 26) { + case 37: /* stwu */ + case 39: /* stbu */ + case 45: /* sthu */ + case 53: /* stfsu */ + case 55: /* stfdu */ + return 1; + case 62: /* std or stdu */ + return (inst & 3) == 1; + case 31: + /* check minor opcode */ + switch ((inst >> 1) & 0x3ff) { + case 181: /* stdux */ + case 183: /* stwux */ + case 247: /* stbux */ + case 439: /* sthux */ + case 695: /* stfsux */ + case 759: /* stfdux */ + return 1; + } + } + return 0; +} + +static void do_dabr(struct pt_regs *regs, unsigned long error_code) +{ + siginfo_t info; + + if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, + 11, SIGSEGV) == NOTIFY_STOP) + return; + + if (debugger_dabr_match(regs)) + return; + + /* Clear the DABR */ + set_dabr(0); + + /* Deliver the signal to userspace */ + info.si_signo = SIGTRAP; + info.si_errno = 0; + info.si_code = TRAP_HWBKPT; + info.si_addr = (void __user *)regs->nip; + force_sig_info(SIGTRAP, &info, current); +} + +/* + * For 600- and 800-family processors, the error_code parameter is DSISR + * for a data fault, SRR1 for an instruction fault. For 400-family processors + * the error_code parameter is ESR for a data fault, 0 for an instruction + * fault. + * For 64-bit processors, the error_code parameter is + * - DSISR for a non-SLB data access fault, + * - SRR1 & 0x08000000 for a non-SLB instruction access fault + * - 0 any SLB fault. + * + * The return value is 0 if the fault was handled, or the signal + * number if this is a kernel fault that can't be handled here. + */ +int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address, + unsigned long error_code) +{ + struct vm_area_struct * vma; + struct mm_struct *mm = current->mm; + siginfo_t info; + int code = SEGV_MAPERR; + int is_write = 0; + int trap = TRAP(regs); + int is_exec = trap == 0x400; + +#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) + /* + * Fortunately the bit assignments in SRR1 for an instruction + * fault and DSISR for a data fault are mostly the same for the + * bits we are interested in. But there are some bits which + * indicate errors in DSISR but can validly be set in SRR1. + */ + if (trap == 0x400) + error_code &= 0x48200000; + else + is_write = error_code & DSISR_ISSTORE; +#else + is_write = error_code & ESR_DST; +#endif /* CONFIG_4xx || CONFIG_BOOKE */ + + if (notify_die(DIE_PAGE_FAULT, "page_fault", regs, error_code, + 11, SIGSEGV) == NOTIFY_STOP) + return 0; + + if (trap == 0x300) { + if (debugger_fault_handler(regs)) + return 0; + } + + /* On a kernel SLB miss we can only check for a valid exception entry */ + if (!user_mode(regs) && (address >= TASK_SIZE)) + return SIGSEGV; + +#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) + if (error_code & DSISR_DABRMATCH) { + /* DABR match */ + do_dabr(regs, error_code); + return 0; + } +#endif /* !(CONFIG_4xx || CONFIG_BOOKE)*/ + + if (in_atomic() || mm == NULL) { + if (!user_mode(regs)) + return SIGSEGV; + /* in_atomic() in user mode is really bad, + as is current->mm == NULL. */ + printk(KERN_EMERG "Page fault in user mode with" + "in_atomic() = %d mm = %p\n", in_atomic(), mm); + printk(KERN_EMERG "NIP = %lx MSR = %lx\n", + regs->nip, regs->msr); + die("Weird page fault", regs, SIGSEGV); + } + + /* When running in the kernel we expect faults to occur only to + * addresses in user space. All other faults represent errors in the + * kernel and should generate an OOPS. Unfortunatly, in the case of an + * erroneous fault occuring in a code path which already holds mmap_sem + * we will deadlock attempting to validate the fault against the + * address space. Luckily the kernel only validly references user + * space from well defined areas of code, which are listed in the + * exceptions table. + * + * As the vast majority of faults will be valid we will only perform + * the source reference check when there is a possibilty of a deadlock. + * Attempt to lock the address space, if we cannot we then validate the + * source. If this is invalid we can skip the address space check, + * thus avoiding the deadlock. + */ + if (!down_read_trylock(&mm->mmap_sem)) { + if (!user_mode(regs) && !search_exception_tables(regs->nip)) + goto bad_area_nosemaphore; + + down_read(&mm->mmap_sem); + } + + vma = find_vma(mm, address); + if (!vma) + goto bad_area; + if (vma->vm_start <= address) + goto good_area; + if (!(vma->vm_flags & VM_GROWSDOWN)) + goto bad_area; + + /* + * N.B. The POWER/Open ABI allows programs to access up to + * 288 bytes below the stack pointer. + * The kernel signal delivery code writes up to about 1.5kB + * below the stack pointer (r1) before decrementing it. + * The exec code can write slightly over 640kB to the stack + * before setting the user r1. Thus we allow the stack to + * expand to 1MB without further checks. + */ + if (address + 0x100000 < vma->vm_end) { + /* get user regs even if this fault is in kernel mode */ + struct pt_regs *uregs = current->thread.regs; + if (uregs == NULL) + goto bad_area; + + /* + * A user-mode access to an address a long way below + * the stack pointer is only valid if the instruction + * is one which would update the stack pointer to the + * address accessed if the instruction completed, + * i.e. either stwu rs,n(r1) or stwux rs,r1,rb + * (or the byte, halfword, float or double forms). + * + * If we don't check this then any write to the area + * between the last mapped region and the stack will + * expand the stack rather than segfaulting. + */ + if (address + 2048 < uregs->gpr[1] + && (!user_mode(regs) || !store_updates_sp(regs))) + goto bad_area; + } + if (expand_stack(vma, address)) + goto bad_area; + +good_area: + code = SEGV_ACCERR; +#if defined(CONFIG_6xx) + if (error_code & 0x95700000) + /* an error such as lwarx to I/O controller space, + address matching DABR, eciwx, etc. */ + goto bad_area; +#endif /* CONFIG_6xx */ +#if defined(CONFIG_8xx) + /* The MPC8xx seems to always set 0x80000000, which is + * "undefined". Of those that can be set, this is the only + * one which seems bad. + */ + if (error_code & 0x10000000) + /* Guarded storage error. */ + goto bad_area; +#endif /* CONFIG_8xx */ + + if (is_exec) { +#ifdef CONFIG_PPC64 + /* protection fault */ + if (error_code & DSISR_PROTFAULT) + goto bad_area; + if (!(vma->vm_flags & VM_EXEC)) + goto bad_area; +#endif +#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) + pte_t *ptep; + + /* Since 4xx/Book-E supports per-page execute permission, + * we lazily flush dcache to icache. */ + ptep = NULL; + if (get_pteptr(mm, address, &ptep) && pte_present(*ptep)) { + struct page *page = pte_page(*ptep); + + if (! test_bit(PG_arch_1, &page->flags)) { + flush_dcache_icache_page(page); + set_bit(PG_arch_1, &page->flags); + } + pte_update(ptep, 0, _PAGE_HWEXEC); + _tlbie(address); + pte_unmap(ptep); + up_read(&mm->mmap_sem); + return 0; + } + if (ptep != NULL) + pte_unmap(ptep); +#endif + /* a write */ + } else if (is_write) { + if (!(vma->vm_flags & VM_WRITE)) + goto bad_area; + /* a read */ + } else { + /* protection fault */ + if (error_code & 0x08000000) + goto bad_area; + if (!(vma->vm_flags & (VM_READ | VM_EXEC))) + goto bad_area; + } + + /* + * If for any reason at all we couldn't handle the fault, + * make sure we exit gracefully rather than endlessly redo + * the fault. + */ + survive: + switch (handle_mm_fault(mm, vma, address, is_write)) { + + case VM_FAULT_MINOR: + current->min_flt++; + break; + case VM_FAULT_MAJOR: + current->maj_flt++; + break; + case VM_FAULT_SIGBUS: + goto do_sigbus; + case VM_FAULT_OOM: + goto out_of_memory; + default: + BUG(); + } + + up_read(&mm->mmap_sem); + return 0; + +bad_area: + up_read(&mm->mmap_sem); + +bad_area_nosemaphore: + /* User mode accesses cause a SIGSEGV */ + if (user_mode(regs)) { + _exception(SIGSEGV, regs, code, address); + return 0; + } + + if (is_exec && (error_code & DSISR_PROTFAULT) + && printk_ratelimit()) + printk(KERN_CRIT "kernel tried to execute NX-protected" + " page (%lx) - exploit attempt? (uid: %d)\n", + address, current->uid); + + return SIGSEGV; + +/* + * We ran out of memory, or some other thing happened to us that made + * us unable to handle the page fault gracefully. + */ +out_of_memory: + up_read(&mm->mmap_sem); + if (current->pid == 1) { + yield(); + down_read(&mm->mmap_sem); + goto survive; + } + printk("VM: killing process %s\n", current->comm); + if (user_mode(regs)) + do_exit(SIGKILL); + return SIGKILL; + +do_sigbus: + up_read(&mm->mmap_sem); + if (user_mode(regs)) { + info.si_signo = SIGBUS; + info.si_errno = 0; + info.si_code = BUS_ADRERR; + info.si_addr = (void __user *)address; + force_sig_info(SIGBUS, &info, current); + return 0; + } + return SIGBUS; +} + +/* + * bad_page_fault is called when we have a bad access from the kernel. + * It is called from the DSI and ISI handlers in head.S and from some + * of the procedures in traps.c. + */ +void bad_page_fault(struct pt_regs *regs, unsigned long address, int sig) +{ + const struct exception_table_entry *entry; + + /* Are we prepared to handle this fault? */ + if ((entry = search_exception_tables(regs->nip)) != NULL) { + regs->nip = entry->fixup; + return; + } + + /* kernel has accessed a bad area */ + die("Kernel access of bad area", regs, sig); +} diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c new file mode 100644 index 00000000000..af9ca0eb6d5 --- /dev/null +++ b/arch/powerpc/mm/fsl_booke_mmu.c @@ -0,0 +1,237 @@ +/* + * Modifications by Kumar Gala (kumar.gala@freescale.com) to support + * E500 Book E processors. + * + * Copyright 2004 Freescale Semiconductor, Inc + * + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern void loadcam_entry(unsigned int index); +unsigned int tlbcam_index; +unsigned int num_tlbcam_entries; +static unsigned long __cam0, __cam1, __cam2; +extern unsigned long total_lowmem; +extern unsigned long __max_low_memory; +#define MAX_LOW_MEM CONFIG_LOWMEM_SIZE + +#define NUM_TLBCAMS (16) + +struct tlbcam { + u32 MAS0; + u32 MAS1; + u32 MAS2; + u32 MAS3; + u32 MAS7; +} TLBCAM[NUM_TLBCAMS]; + +struct tlbcamrange { + unsigned long start; + unsigned long limit; + phys_addr_t phys; +} tlbcam_addrs[NUM_TLBCAMS]; + +extern unsigned int tlbcam_index; + +/* + * Return PA for this VA if it is mapped by a CAM, or 0 + */ +unsigned long v_mapped_by_tlbcam(unsigned long va) +{ + int b; + for (b = 0; b < tlbcam_index; ++b) + if (va >= tlbcam_addrs[b].start && va < tlbcam_addrs[b].limit) + return tlbcam_addrs[b].phys + (va - tlbcam_addrs[b].start); + return 0; +} + +/* + * Return VA for a given PA or 0 if not mapped + */ +unsigned long p_mapped_by_tlbcam(unsigned long pa) +{ + int b; + for (b = 0; b < tlbcam_index; ++b) + if (pa >= tlbcam_addrs[b].phys + && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start) + +tlbcam_addrs[b].phys) + return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys); + return 0; +} + +/* + * Set up one of the I/D BAT (block address translation) register pairs. + * The parameters are not checked; in particular size must be a power + * of 4 between 4k and 256M. + */ +void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned int size, int flags, unsigned int pid) +{ + unsigned int tsize, lz; + + asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size)); + tsize = (21 - lz) / 2; + +#ifdef CONFIG_SMP + if ((flags & _PAGE_NO_CACHE) == 0) + flags |= _PAGE_COHERENT; +#endif + + TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1); + TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); + TLBCAM[index].MAS2 = virt & PAGE_MASK; + + TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0; + TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0; + TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0; + TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0; + TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0; + + TLBCAM[index].MAS3 = (phys & PAGE_MASK) | MAS3_SX | MAS3_SR; + TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_SW : 0); + +#ifndef CONFIG_KGDB /* want user access for breakpoints */ + if (flags & _PAGE_USER) { + TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; + TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); + } +#else + TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; + TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); +#endif + + tlbcam_addrs[index].start = virt; + tlbcam_addrs[index].limit = virt + size - 1; + tlbcam_addrs[index].phys = phys; + + loadcam_entry(index); +} + +void invalidate_tlbcam_entry(int index) +{ + TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index); + TLBCAM[index].MAS1 = ~MAS1_VALID; + + loadcam_entry(index); +} + +void __init cam_mapin_ram(unsigned long cam0, unsigned long cam1, + unsigned long cam2) +{ + settlbcam(0, KERNELBASE, PPC_MEMSTART, cam0, _PAGE_KERNEL, 0); + tlbcam_index++; + if (cam1) { + tlbcam_index++; + settlbcam(1, KERNELBASE+cam0, PPC_MEMSTART+cam0, cam1, _PAGE_KERNEL, 0); + } + if (cam2) { + tlbcam_index++; + settlbcam(2, KERNELBASE+cam0+cam1, PPC_MEMSTART+cam0+cam1, cam2, _PAGE_KERNEL, 0); + } +} + +/* + * MMU_init_hw does the chip-specific initialization of the MMU hardware. + */ +void __init MMU_init_hw(void) +{ + flush_instruction_cache(); +} + +unsigned long __init mmu_mapin_ram(void) +{ + cam_mapin_ram(__cam0, __cam1, __cam2); + + return __cam0 + __cam1 + __cam2; +} + + +void __init +adjust_total_lowmem(void) +{ + unsigned long max_low_mem = MAX_LOW_MEM; + unsigned long cam_max = 0x10000000; + unsigned long ram; + + /* adjust CAM size to max_low_mem */ + if (max_low_mem < cam_max) + cam_max = max_low_mem; + + /* adjust lowmem size to max_low_mem */ + if (max_low_mem < total_lowmem) + ram = max_low_mem; + else + ram = total_lowmem; + + /* Calculate CAM values */ + __cam0 = 1UL << 2 * (__ilog2(ram) / 2); + if (__cam0 > cam_max) + __cam0 = cam_max; + ram -= __cam0; + if (ram) { + __cam1 = 1UL << 2 * (__ilog2(ram) / 2); + if (__cam1 > cam_max) + __cam1 = cam_max; + ram -= __cam1; + } + if (ram) { + __cam2 = 1UL << 2 * (__ilog2(ram) / 2); + if (__cam2 > cam_max) + __cam2 = cam_max; + ram -= __cam2; + } + + printk(KERN_INFO "Memory CAM mapping: CAM0=%ldMb, CAM1=%ldMb," + " CAM2=%ldMb residual: %ldMb\n", + __cam0 >> 20, __cam1 >> 20, __cam2 >> 20, + (total_lowmem - __cam0 - __cam1 - __cam2) >> 20); + __max_low_memory = max_low_mem = __cam0 + __cam1 + __cam2; +} diff --git a/arch/powerpc/mm/hash_32.S b/arch/powerpc/mm/hash_32.S new file mode 100644 index 00000000000..57278a8dd13 --- /dev/null +++ b/arch/powerpc/mm/hash_32.S @@ -0,0 +1,618 @@ +/* + * arch/ppc/kernel/hashtable.S + * + * $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $ + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP + * Copyright (C) 1996 Cort Dougan + * Adapted for Power Macintosh by Paul Mackerras. + * Low-level exception handlers and MMU support + * rewritten by Paul Mackerras. + * Copyright (C) 1996 Paul Mackerras. + * + * This file contains low-level assembler routines for managing + * the PowerPC MMU hash table. (PPC 8xx processors don't use a + * hash table, so this file is not used on them.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SMP + .comm mmu_hash_lock,4 +#endif /* CONFIG_SMP */ + +/* + * Sync CPUs with hash_page taking & releasing the hash + * table lock + */ +#ifdef CONFIG_SMP + .text +_GLOBAL(hash_page_sync) + lis r8,mmu_hash_lock@h + ori r8,r8,mmu_hash_lock@l + lis r0,0x0fff + b 10f +11: lwz r6,0(r8) + cmpwi 0,r6,0 + bne 11b +10: lwarx r6,0,r8 + cmpwi 0,r6,0 + bne- 11b + stwcx. r0,0,r8 + bne- 10b + isync + eieio + li r0,0 + stw r0,0(r8) + blr +#endif + +/* + * Load a PTE into the hash table, if possible. + * The address is in r4, and r3 contains an access flag: + * _PAGE_RW (0x400) if a write. + * r9 contains the SRR1 value, from which we use the MSR_PR bit. + * SPRG3 contains the physical address of the current task's thread. + * + * Returns to the caller if the access is illegal or there is no + * mapping for the address. Otherwise it places an appropriate PTE + * in the hash table and returns from the exception. + * Uses r0, r3 - r8, ctr, lr. + */ + .text +_GLOBAL(hash_page) +#ifdef CONFIG_PPC64BRIDGE + mfmsr r0 + clrldi r0,r0,1 /* make sure it's in 32-bit mode */ + MTMSRD(r0) + isync +#endif + tophys(r7,0) /* gets -KERNELBASE into r7 */ +#ifdef CONFIG_SMP + addis r8,r7,mmu_hash_lock@h + ori r8,r8,mmu_hash_lock@l + lis r0,0x0fff + b 10f +11: lwz r6,0(r8) + cmpwi 0,r6,0 + bne 11b +10: lwarx r6,0,r8 + cmpwi 0,r6,0 + bne- 11b + stwcx. r0,0,r8 + bne- 10b + isync +#endif + /* Get PTE (linux-style) and check access */ + lis r0,KERNELBASE@h /* check if kernel address */ + cmplw 0,r4,r0 + mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */ + ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ + lwz r5,PGDIR(r8) /* virt page-table root */ + blt+ 112f /* assume user more likely */ + lis r5,swapper_pg_dir@ha /* if kernel address, use */ + addi r5,r5,swapper_pg_dir@l /* kernel page table */ + rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ +112: add r5,r5,r7 /* convert to phys addr */ + rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ + lwz r8,0(r5) /* get pmd entry */ + rlwinm. r8,r8,0,0,19 /* extract address of pte page */ +#ifdef CONFIG_SMP + beq- hash_page_out /* return if no mapping */ +#else + /* XXX it seems like the 601 will give a machine fault on the + rfi if its alignment is wrong (bottom 4 bits of address are + 8 or 0xc) and we have had a not-taken conditional branch + to the address following the rfi. */ + beqlr- +#endif + rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ + rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ + ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE + + /* + * Update the linux PTE atomically. We do the lwarx up-front + * because almost always, there won't be a permission violation + * and there won't already be an HPTE, and thus we will have + * to update the PTE to set _PAGE_HASHPTE. -- paulus. + */ +retry: + lwarx r6,0,r8 /* get linux-style pte */ + andc. r5,r3,r6 /* check access & ~permission */ +#ifdef CONFIG_SMP + bne- hash_page_out /* return if access not permitted */ +#else + bnelr- +#endif + or r5,r0,r6 /* set accessed/dirty bits */ + stwcx. r5,0,r8 /* attempt to update PTE */ + bne- retry /* retry if someone got there first */ + + mfsrin r3,r4 /* get segment reg for segment */ + mfctr r0 + stw r0,_CTR(r11) + bl create_hpte /* add the hash table entry */ + +#ifdef CONFIG_SMP + eieio + addis r8,r7,mmu_hash_lock@ha + li r0,0 + stw r0,mmu_hash_lock@l(r8) +#endif + + /* Return from the exception */ + lwz r5,_CTR(r11) + mtctr r5 + lwz r0,GPR0(r11) + lwz r7,GPR7(r11) + lwz r8,GPR8(r11) + b fast_exception_return + +#ifdef CONFIG_SMP +hash_page_out: + eieio + addis r8,r7,mmu_hash_lock@ha + li r0,0 + stw r0,mmu_hash_lock@l(r8) + blr +#endif /* CONFIG_SMP */ + +/* + * Add an entry for a particular page to the hash table. + * + * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) + * + * We assume any necessary modifications to the pte (e.g. setting + * the accessed bit) have already been done and that there is actually + * a hash table in use (i.e. we're not on a 603). + */ +_GLOBAL(add_hash_page) + mflr r0 + stw r0,4(r1) + + /* Convert context and va to VSID */ + mulli r3,r3,897*16 /* multiply context by context skew */ + rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ + mulli r0,r0,0x111 /* multiply by ESID skew */ + add r3,r3,r0 /* note create_hpte trims to 24 bits */ + +#ifdef CONFIG_SMP + rlwinm r8,r1,0,0,18 /* use cpu number to make tag */ + lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */ + oris r8,r8,12 +#endif /* CONFIG_SMP */ + + /* + * We disable interrupts here, even on UP, because we don't + * want to race with hash_page, and because we want the + * _PAGE_HASHPTE bit to be a reliable indication of whether + * the HPTE exists (or at least whether one did once). + * We also turn off the MMU for data accesses so that we + * we can't take a hash table miss (assuming the code is + * covered by a BAT). -- paulus + */ + mfmsr r10 + SYNC + rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ + rlwinm r0,r0,0,28,26 /* clear MSR_DR */ + mtmsr r0 + SYNC_601 + isync + + tophys(r7,0) + +#ifdef CONFIG_SMP + addis r9,r7,mmu_hash_lock@ha + addi r9,r9,mmu_hash_lock@l +10: lwarx r0,0,r9 /* take the mmu_hash_lock */ + cmpi 0,r0,0 + bne- 11f + stwcx. r8,0,r9 + beq+ 12f +11: lwz r0,0(r9) + cmpi 0,r0,0 + beq 10b + b 11b +12: isync +#endif + + /* + * Fetch the linux pte and test and set _PAGE_HASHPTE atomically. + * If _PAGE_HASHPTE was already set, we don't replace the existing + * HPTE, so we just unlock and return. + */ + mr r8,r5 + rlwimi r8,r4,22,20,29 +1: lwarx r6,0,r8 + andi. r0,r6,_PAGE_HASHPTE + bne 9f /* if HASHPTE already set, done */ + ori r5,r6,_PAGE_HASHPTE + stwcx. r5,0,r8 + bne- 1b + + bl create_hpte + +9: +#ifdef CONFIG_SMP + eieio + li r0,0 + stw r0,0(r9) /* clear mmu_hash_lock */ +#endif + + /* reenable interrupts and DR */ + mtmsr r10 + SYNC_601 + isync + + lwz r0,4(r1) + mtlr r0 + blr + +/* + * This routine adds a hardware PTE to the hash table. + * It is designed to be called with the MMU either on or off. + * r3 contains the VSID, r4 contains the virtual address, + * r5 contains the linux PTE, r6 contains the old value of the + * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the + * offset to be added to addresses (0 if the MMU is on, + * -KERNELBASE if it is off). + * On SMP, the caller should have the mmu_hash_lock held. + * We assume that the caller has (or will) set the _PAGE_HASHPTE + * bit in the linux PTE in memory. The value passed in r6 should + * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set + * this routine will skip the search for an existing HPTE. + * This procedure modifies r0, r3 - r6, r8, cr0. + * -- paulus. + * + * For speed, 4 of the instructions get patched once the size and + * physical address of the hash table are known. These definitions + * of Hash_base and Hash_bits below are just an example. + */ +Hash_base = 0xc0180000 +Hash_bits = 12 /* e.g. 256kB hash table */ +Hash_msk = (((1 << Hash_bits) - 1) * 64) + +#ifndef CONFIG_PPC64BRIDGE +/* defines for the PTE format for 32-bit PPCs */ +#define PTE_SIZE 8 +#define PTEG_SIZE 64 +#define LG_PTEG_SIZE 6 +#define LDPTEu lwzu +#define STPTE stw +#define CMPPTE cmpw +#define PTE_H 0x40 +#define PTE_V 0x80000000 +#define TST_V(r) rlwinm. r,r,0,0,0 +#define SET_V(r) oris r,r,PTE_V@h +#define CLR_V(r,t) rlwinm r,r,0,1,31 + +#else +/* defines for the PTE format for 64-bit PPCs */ +#define PTE_SIZE 16 +#define PTEG_SIZE 128 +#define LG_PTEG_SIZE 7 +#define LDPTEu ldu +#define STPTE std +#define CMPPTE cmpd +#define PTE_H 2 +#define PTE_V 1 +#define TST_V(r) andi. r,r,PTE_V +#define SET_V(r) ori r,r,PTE_V +#define CLR_V(r,t) li t,PTE_V; andc r,r,t +#endif /* CONFIG_PPC64BRIDGE */ + +#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) +#define HASH_RIGHT 31-LG_PTEG_SIZE + +_GLOBAL(create_hpte) + /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ + rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */ + rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ + and r8,r8,r0 /* writable if _RW & _DIRTY */ + rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ + rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ + ori r8,r8,0xe14 /* clear out reserved bits and M */ + andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ +BEGIN_FTR_SECTION + ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */ +END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT) + + /* Construct the high word of the PPC-style PTE (r5) */ +#ifndef CONFIG_PPC64BRIDGE + rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ + rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ +#else /* CONFIG_PPC64BRIDGE */ + clrlwi r3,r3,8 /* reduce vsid to 24 bits */ + sldi r5,r3,12 /* shift vsid into position */ + rlwimi r5,r4,16,20,24 /* put in API (abbrev page index) */ +#endif /* CONFIG_PPC64BRIDGE */ + SET_V(r5) /* set V (valid) bit */ + + /* Get the address of the primary PTE group in the hash table (r3) */ +_GLOBAL(hash_page_patch_A) + addis r0,r7,Hash_base@h /* base address of hash table */ + rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ + rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ + xor r3,r3,r0 /* make primary hash */ + li r0,8 /* PTEs/group */ + + /* + * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search + * if it is clear, meaning that the HPTE isn't there already... + */ + andi. r6,r6,_PAGE_HASHPTE + beq+ 10f /* no PTE: go look for an empty slot */ + tlbie r4 + + addis r4,r7,htab_hash_searches@ha + lwz r6,htab_hash_searches@l(r4) + addi r6,r6,1 /* count how many searches we do */ + stw r6,htab_hash_searches@l(r4) + + /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ + mtctr r0 + addi r4,r3,-PTE_SIZE +1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ + CMPPTE 0,r6,r5 + bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ + beq+ found_slot + + /* Search the secondary PTEG for a matching PTE */ + ori r5,r5,PTE_H /* set H (secondary hash) bit */ +_GLOBAL(hash_page_patch_B) + xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ + xori r4,r4,(-PTEG_SIZE & 0xffff) + addi r4,r4,-PTE_SIZE + mtctr r0 +2: LDPTEu r6,PTE_SIZE(r4) + CMPPTE 0,r6,r5 + bdnzf 2,2b + beq+ found_slot + xori r5,r5,PTE_H /* clear H bit again */ + + /* Search the primary PTEG for an empty slot */ +10: mtctr r0 + addi r4,r3,-PTE_SIZE /* search primary PTEG */ +1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */ + TST_V(r6) /* test valid bit */ + bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ + beq+ found_empty + + /* update counter of times that the primary PTEG is full */ + addis r4,r7,primary_pteg_full@ha + lwz r6,primary_pteg_full@l(r4) + addi r6,r6,1 + stw r6,primary_pteg_full@l(r4) + + /* Search the secondary PTEG for an empty slot */ + ori r5,r5,PTE_H /* set H (secondary hash) bit */ +_GLOBAL(hash_page_patch_C) + xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ + xori r4,r4,(-PTEG_SIZE & 0xffff) + addi r4,r4,-PTE_SIZE + mtctr r0 +2: LDPTEu r6,PTE_SIZE(r4) + TST_V(r6) + bdnzf 2,2b + beq+ found_empty + xori r5,r5,PTE_H /* clear H bit again */ + + /* + * Choose an arbitrary slot in the primary PTEG to overwrite. + * Since both the primary and secondary PTEGs are full, and we + * have no information that the PTEs in the primary PTEG are + * more important or useful than those in the secondary PTEG, + * and we know there is a definite (although small) speed + * advantage to putting the PTE in the primary PTEG, we always + * put the PTE in the primary PTEG. + */ + addis r4,r7,next_slot@ha + lwz r6,next_slot@l(r4) + addi r6,r6,PTE_SIZE + andi. r6,r6,7*PTE_SIZE + stw r6,next_slot@l(r4) + add r4,r3,r6 + +#ifndef CONFIG_SMP + /* Store PTE in PTEG */ +found_empty: + STPTE r5,0(r4) +found_slot: + STPTE r8,PTE_SIZE/2(r4) + +#else /* CONFIG_SMP */ +/* + * Between the tlbie above and updating the hash table entry below, + * another CPU could read the hash table entry and put it in its TLB. + * There are 3 cases: + * 1. using an empty slot + * 2. updating an earlier entry to change permissions (i.e. enable write) + * 3. taking over the PTE for an unrelated address + * + * In each case it doesn't really matter if the other CPUs have the old + * PTE in their TLB. So we don't need to bother with another tlbie here, + * which is convenient as we've overwritten the register that had the + * address. :-) The tlbie above is mainly to make sure that this CPU comes + * and gets the new PTE from the hash table. + * + * We do however have to make sure that the PTE is never in an invalid + * state with the V bit set. + */ +found_empty: +found_slot: + CLR_V(r5,r0) /* clear V (valid) bit in PTE */ + STPTE r5,0(r4) + sync + TLBSYNC + STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ + sync + SET_V(r5) + STPTE r5,0(r4) /* finally set V bit in PTE */ +#endif /* CONFIG_SMP */ + + sync /* make sure pte updates get to memory */ + blr + + .comm next_slot,4 + .comm primary_pteg_full,4 + .comm htab_hash_searches,4 + +/* + * Flush the entry for a particular page from the hash table. + * + * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, + * int count) + * + * We assume that there is a hash table in use (Hash != 0). + */ +_GLOBAL(flush_hash_pages) + tophys(r7,0) + + /* + * We disable interrupts here, even on UP, because we want + * the _PAGE_HASHPTE bit to be a reliable indication of + * whether the HPTE exists (or at least whether one did once). + * We also turn off the MMU for data accesses so that we + * we can't take a hash table miss (assuming the code is + * covered by a BAT). -- paulus + */ + mfmsr r10 + SYNC + rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ + rlwinm r0,r0,0,28,26 /* clear MSR_DR */ + mtmsr r0 + SYNC_601 + isync + + /* First find a PTE in the range that has _PAGE_HASHPTE set */ + rlwimi r5,r4,22,20,29 +1: lwz r0,0(r5) + cmpwi cr1,r6,1 + andi. r0,r0,_PAGE_HASHPTE + bne 2f + ble cr1,19f + addi r4,r4,0x1000 + addi r5,r5,4 + addi r6,r6,-1 + b 1b + + /* Convert context and va to VSID */ +2: mulli r3,r3,897*16 /* multiply context by context skew */ + rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ + mulli r0,r0,0x111 /* multiply by ESID skew */ + add r3,r3,r0 /* note code below trims to 24 bits */ + + /* Construct the high word of the PPC-style PTE (r11) */ +#ifndef CONFIG_PPC64BRIDGE + rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ + rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ +#else /* CONFIG_PPC64BRIDGE */ + clrlwi r3,r3,8 /* reduce vsid to 24 bits */ + sldi r11,r3,12 /* shift vsid into position */ + rlwimi r11,r4,16,20,24 /* put in API (abbrev page index) */ +#endif /* CONFIG_PPC64BRIDGE */ + SET_V(r11) /* set V (valid) bit */ + +#ifdef CONFIG_SMP + addis r9,r7,mmu_hash_lock@ha + addi r9,r9,mmu_hash_lock@l + rlwinm r8,r1,0,0,18 + add r8,r8,r7 + lwz r8,TI_CPU(r8) + oris r8,r8,9 +10: lwarx r0,0,r9 + cmpi 0,r0,0 + bne- 11f + stwcx. r8,0,r9 + beq+ 12f +11: lwz r0,0(r9) + cmpi 0,r0,0 + beq 10b + b 11b +12: isync +#endif + + /* + * Check the _PAGE_HASHPTE bit in the linux PTE. If it is + * already clear, we're done (for this pte). If not, + * clear it (atomically) and proceed. -- paulus. + */ +33: lwarx r8,0,r5 /* fetch the pte */ + andi. r0,r8,_PAGE_HASHPTE + beq 8f /* done if HASHPTE is already clear */ + rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ + stwcx. r8,0,r5 /* update the pte */ + bne- 33b + + /* Get the address of the primary PTE group in the hash table (r3) */ +_GLOBAL(flush_hash_patch_A) + addis r8,r7,Hash_base@h /* base address of hash table */ + rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ + rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ + xor r8,r0,r8 /* make primary hash */ + + /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ + li r0,8 /* PTEs/group */ + mtctr r0 + addi r12,r8,-PTE_SIZE +1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */ + CMPPTE 0,r0,r11 + bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ + beq+ 3f + + /* Search the secondary PTEG for a matching PTE */ + ori r11,r11,PTE_H /* set H (secondary hash) bit */ + li r0,8 /* PTEs/group */ +_GLOBAL(flush_hash_patch_B) + xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ + xori r12,r12,(-PTEG_SIZE & 0xffff) + addi r12,r12,-PTE_SIZE + mtctr r0 +2: LDPTEu r0,PTE_SIZE(r12) + CMPPTE 0,r0,r11 + bdnzf 2,2b + xori r11,r11,PTE_H /* clear H again */ + bne- 4f /* should rarely fail to find it */ + +3: li r0,0 + STPTE r0,0(r12) /* invalidate entry */ +4: sync + tlbie r4 /* in hw tlb too */ + sync + +8: ble cr1,9f /* if all ptes checked */ +81: addi r6,r6,-1 + addi r5,r5,4 /* advance to next pte */ + addi r4,r4,0x1000 + lwz r0,0(r5) /* check next pte */ + cmpwi cr1,r6,1 + andi. r0,r0,_PAGE_HASHPTE + bne 33b + bgt cr1,81b + +9: +#ifdef CONFIG_SMP + TLBSYNC + li r0,0 + stw r0,0(r9) /* clear mmu_hash_lock */ +#endif + +19: mtmsr r10 + SYNC_601 + isync + blr diff --git a/arch/powerpc/mm/init.c b/arch/powerpc/mm/init.c new file mode 100644 index 00000000000..f4d983a6e52 --- /dev/null +++ b/arch/powerpc/mm/init.c @@ -0,0 +1,581 @@ +/* + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com) + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mem_pieces.h" +#include "mmu_decl.h" + +#if defined(CONFIG_KERNEL_START_BOOL) || defined(CONFIG_LOWMEM_SIZE_BOOL) +/* The ammount of lowmem must be within 0xF0000000 - KERNELBASE. */ +#if (CONFIG_LOWMEM_SIZE > (0xF0000000 - KERNELBASE)) +#error "You must adjust CONFIG_LOWMEM_SIZE or CONFIG_START_KERNEL" +#endif +#endif +#define MAX_LOW_MEM CONFIG_LOWMEM_SIZE + +DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); + +unsigned long total_memory; +unsigned long total_lowmem; + +unsigned long ppc_memstart; +unsigned long ppc_memoffset = PAGE_OFFSET; + +int mem_init_done; +int init_bootmem_done; +int boot_mapsize; +#ifdef CONFIG_PPC_PMAC +unsigned long agp_special_page; +#endif + +extern char _end[]; +extern char etext[], _stext[]; +extern char __init_begin, __init_end; + +#ifdef CONFIG_HIGHMEM +pte_t *kmap_pte; +pgprot_t kmap_prot; + +EXPORT_SYMBOL(kmap_prot); +EXPORT_SYMBOL(kmap_pte); +#endif + +void MMU_init(void); +void set_phys_avail(unsigned long total_ram); + +/* XXX should be in current.h -- paulus */ +extern struct task_struct *current_set[NR_CPUS]; + +char *klimit = _end; +struct mem_pieces phys_avail; +struct device_node *memory_node; + +/* + * this tells the system to map all of ram with the segregs + * (i.e. page tables) instead of the bats. + * -- Cort + */ +int __map_without_bats; +int __map_without_ltlbs; + +/* max amount of RAM to use */ +unsigned long __max_memory; +/* max amount of low RAM to map in */ +unsigned long __max_low_memory = MAX_LOW_MEM; + +/* + * Read in a property describing some pieces of memory. + */ +static int __init get_mem_prop(char *name, struct mem_pieces *mp) +{ + struct reg_property *rp; + int i, s; + unsigned int *ip; + int nac = prom_n_addr_cells(memory_node); + int nsc = prom_n_size_cells(memory_node); + + ip = (unsigned int *) get_property(memory_node, name, &s); + if (ip == NULL) { + printk(KERN_ERR "error: couldn't get %s property on /memory\n", + name); + return 0; + } + s /= (nsc + nac) * 4; + rp = mp->regions; + for (i = 0; i < s; ++i, ip += nac+nsc) { + if (nac >= 2 && ip[nac-2] != 0) + continue; + rp->address = ip[nac-1]; + if (nsc >= 2 && ip[nac+nsc-2] != 0) + rp->size = ~0U; + else + rp->size = ip[nac+nsc-1]; + ++rp; + } + mp->n_regions = rp - mp->regions; + + /* Make sure the pieces are sorted. */ + mem_pieces_sort(mp); + mem_pieces_coalesce(mp); + return 1; +} + +/* + * Collect information about physical RAM and which pieces are + * already in use from the device tree. + */ +unsigned long __init find_end_of_memory(void) +{ + unsigned long a, total; + struct mem_pieces phys_mem; + + /* + * Find out where physical memory is, and check that it + * starts at 0 and is contiguous. It seems that RAM is + * always physically contiguous on Power Macintoshes. + * + * Supporting discontiguous physical memory isn't hard, + * it just makes the virtual <-> physical mapping functions + * more complicated (or else you end up wasting space + * in mem_map). + */ + memory_node = find_devices("memory"); + if (memory_node == NULL || !get_mem_prop("reg", &phys_mem) + || phys_mem.n_regions == 0) + panic("No RAM??"); + a = phys_mem.regions[0].address; + if (a != 0) + panic("RAM doesn't start at physical address 0"); + total = phys_mem.regions[0].size; + + if (phys_mem.n_regions > 1) { + printk("RAM starting at 0x%x is not contiguous\n", + phys_mem.regions[1].address); + printk("Using RAM from 0 to 0x%lx\n", total-1); + } + + return total; +} + +/* + * Check for command-line options that affect what MMU_init will do. + */ +void MMU_setup(void) +{ + /* Check for nobats option (used in mapin_ram). */ + if (strstr(cmd_line, "nobats")) { + __map_without_bats = 1; + } + + if (strstr(cmd_line, "noltlbs")) { + __map_without_ltlbs = 1; + } + + /* Look for mem= option on command line */ + if (strstr(cmd_line, "mem=")) { + char *p, *q; + unsigned long maxmem = 0; + + for (q = cmd_line; (p = strstr(q, "mem=")) != 0; ) { + q = p + 4; + if (p > cmd_line && p[-1] != ' ') + continue; + maxmem = simple_strtoul(q, &q, 0); + if (*q == 'k' || *q == 'K') { + maxmem <<= 10; + ++q; + } else if (*q == 'm' || *q == 'M') { + maxmem <<= 20; + ++q; + } + } + __max_memory = maxmem; + } +} + +/* + * MMU_init sets up the basic memory mappings for the kernel, + * including both RAM and possibly some I/O regions, + * and sets up the page tables and the MMU hardware ready to go. + */ +void __init MMU_init(void) +{ + if (ppc_md.progress) + ppc_md.progress("MMU:enter", 0x111); + + /* parse args from command line */ + MMU_setup(); + + /* + * Figure out how much memory we have, how much + * is lowmem, and how much is highmem. If we were + * passed the total memory size from the bootloader, + * just use it. + */ + if (boot_mem_size) + total_memory = boot_mem_size; + else + total_memory = ppc_md.find_end_of_memory(); + + if (__max_memory && total_memory > __max_memory) + total_memory = __max_memory; + total_lowmem = total_memory; +#ifdef CONFIG_FSL_BOOKE + /* Freescale Book-E parts expect lowmem to be mapped by fixed TLB + * entries, so we need to adjust lowmem to match the amount we can map + * in the fixed entries */ + adjust_total_lowmem(); +#endif /* CONFIG_FSL_BOOKE */ + if (total_lowmem > __max_low_memory) { + total_lowmem = __max_low_memory; +#ifndef CONFIG_HIGHMEM + total_memory = total_lowmem; +#endif /* CONFIG_HIGHMEM */ + } + set_phys_avail(total_lowmem); + + /* Initialize the MMU hardware */ + if (ppc_md.progress) + ppc_md.progress("MMU:hw init", 0x300); + MMU_init_hw(); + + /* Map in all of RAM starting at KERNELBASE */ + if (ppc_md.progress) + ppc_md.progress("MMU:mapin", 0x301); + mapin_ram(); + +#ifdef CONFIG_HIGHMEM + ioremap_base = PKMAP_BASE; +#else + ioremap_base = 0xfe000000UL; /* for now, could be 0xfffff000 */ +#endif /* CONFIG_HIGHMEM */ + ioremap_bot = ioremap_base; + + /* Map in I/O resources */ + if (ppc_md.progress) + ppc_md.progress("MMU:setio", 0x302); + if (ppc_md.setup_io_mappings) + ppc_md.setup_io_mappings(); + + /* Initialize the context management stuff */ + mmu_context_init(); + + if (ppc_md.progress) + ppc_md.progress("MMU:exit", 0x211); + +#ifdef CONFIG_BOOTX_TEXT + /* By default, we are no longer mapped */ + boot_text_mapped = 0; + /* Must be done last, or ppc_md.progress will die. */ + map_boot_text(); +#endif +} + +/* This is only called until mem_init is done. */ +void __init *early_get_page(void) +{ + void *p; + + if (init_bootmem_done) { + p = alloc_bootmem_pages(PAGE_SIZE); + } else { + p = mem_pieces_find(PAGE_SIZE, PAGE_SIZE); + } + return p; +} + +/* Free up now-unused memory */ +static void free_sec(unsigned long start, unsigned long end, const char *name) +{ + unsigned long cnt = 0; + + while (start < end) { + ClearPageReserved(virt_to_page(start)); + set_page_count(virt_to_page(start), 1); + free_page(start); + cnt++; + start += PAGE_SIZE; + } + if (cnt) { + printk(" %ldk %s", cnt << (PAGE_SHIFT - 10), name); + totalram_pages += cnt; + } +} + +void free_initmem(void) +{ +#define FREESEC(TYPE) \ + free_sec((unsigned long)(&__ ## TYPE ## _begin), \ + (unsigned long)(&__ ## TYPE ## _end), \ + #TYPE); + + printk ("Freeing unused kernel memory:"); + FREESEC(init); + printk("\n"); + ppc_md.progress = NULL; +#undef FREESEC +} + +#ifdef CONFIG_BLK_DEV_INITRD +void free_initrd_mem(unsigned long start, unsigned long end) +{ + if (start < end) + printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); + for (; start < end; start += PAGE_SIZE) { + ClearPageReserved(virt_to_page(start)); + set_page_count(virt_to_page(start), 1); + free_page(start); + totalram_pages++; + } +} +#endif + +/* + * Initialize the bootmem system and give it all the memory we + * have available. + */ +void __init do_init_bootmem(void) +{ + unsigned long start, size; + int i; + + /* + * Find an area to use for the bootmem bitmap. + * We look for the first area which is at least + * 128kB in length (128kB is enough for a bitmap + * for 4GB of memory, using 4kB pages), plus 1 page + * (in case the address isn't page-aligned). + */ + start = 0; + size = 0; + for (i = 0; i < phys_avail.n_regions; ++i) { + unsigned long a = phys_avail.regions[i].address; + unsigned long s = phys_avail.regions[i].size; + if (s <= size) + continue; + start = a; + size = s; + if (s >= 33 * PAGE_SIZE) + break; + } + start = PAGE_ALIGN(start); + + min_low_pfn = start >> PAGE_SHIFT; + max_low_pfn = (PPC_MEMSTART + total_lowmem) >> PAGE_SHIFT; + max_pfn = (PPC_MEMSTART + total_memory) >> PAGE_SHIFT; + boot_mapsize = init_bootmem_node(&contig_page_data, min_low_pfn, + PPC_MEMSTART >> PAGE_SHIFT, + max_low_pfn); + + /* remove the bootmem bitmap from the available memory */ + mem_pieces_remove(&phys_avail, start, boot_mapsize, 1); + + /* add everything in phys_avail into the bootmem map */ + for (i = 0; i < phys_avail.n_regions; ++i) + free_bootmem(phys_avail.regions[i].address, + phys_avail.regions[i].size); + + init_bootmem_done = 1; +} + +/* + * paging_init() sets up the page tables - in fact we've already done this. + */ +void __init paging_init(void) +{ + unsigned long zones_size[MAX_NR_ZONES], i; + +#ifdef CONFIG_HIGHMEM + map_page(PKMAP_BASE, 0, 0); /* XXX gross */ + pkmap_page_table = pte_offset_kernel(pmd_offset(pgd_offset_k + (PKMAP_BASE), PKMAP_BASE), PKMAP_BASE); + map_page(KMAP_FIX_BEGIN, 0, 0); /* XXX gross */ + kmap_pte = pte_offset_kernel(pmd_offset(pgd_offset_k + (KMAP_FIX_BEGIN), KMAP_FIX_BEGIN), KMAP_FIX_BEGIN); + kmap_prot = PAGE_KERNEL; +#endif /* CONFIG_HIGHMEM */ + + /* + * All pages are DMA-able so we put them all in the DMA zone. + */ + zones_size[ZONE_DMA] = total_lowmem >> PAGE_SHIFT; + for (i = 1; i < MAX_NR_ZONES; i++) + zones_size[i] = 0; + +#ifdef CONFIG_HIGHMEM + zones_size[ZONE_HIGHMEM] = (total_memory - total_lowmem) >> PAGE_SHIFT; +#endif /* CONFIG_HIGHMEM */ + + free_area_init(zones_size); +} + +void __init mem_init(void) +{ + unsigned long addr; + int codepages = 0; + int datapages = 0; + int initpages = 0; +#ifdef CONFIG_HIGHMEM + unsigned long highmem_mapnr; + + highmem_mapnr = total_lowmem >> PAGE_SHIFT; +#endif /* CONFIG_HIGHMEM */ + max_mapnr = total_memory >> PAGE_SHIFT; + + high_memory = (void *) __va(PPC_MEMSTART + total_lowmem); + num_physpages = max_mapnr; /* RAM is assumed contiguous */ + + totalram_pages += free_all_bootmem(); + +#ifdef CONFIG_BLK_DEV_INITRD + /* if we are booted from BootX with an initial ramdisk, + make sure the ramdisk pages aren't reserved. */ + if (initrd_start) { + for (addr = initrd_start; addr < initrd_end; addr += PAGE_SIZE) + ClearPageReserved(virt_to_page(addr)); + } +#endif /* CONFIG_BLK_DEV_INITRD */ + +#ifdef CONFIG_PPC_OF + /* mark the RTAS pages as reserved */ + if ( rtas_data ) + for (addr = (ulong)__va(rtas_data); + addr < PAGE_ALIGN((ulong)__va(rtas_data)+rtas_size) ; + addr += PAGE_SIZE) + SetPageReserved(virt_to_page(addr)); +#endif +#ifdef CONFIG_PPC_PMAC + if (agp_special_page) + SetPageReserved(virt_to_page(agp_special_page)); +#endif + for (addr = PAGE_OFFSET; addr < (unsigned long)high_memory; + addr += PAGE_SIZE) { + if (!PageReserved(virt_to_page(addr))) + continue; + if (addr < (ulong) etext) + codepages++; + else if (addr >= (unsigned long)&__init_begin + && addr < (unsigned long)&__init_end) + initpages++; + else if (addr < (ulong) klimit) + datapages++; + } + +#ifdef CONFIG_HIGHMEM + { + unsigned long pfn; + + for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) { + struct page *page = mem_map + pfn; + + ClearPageReserved(page); + set_page_count(page, 1); + __free_page(page); + totalhigh_pages++; + } + totalram_pages += totalhigh_pages; + } +#endif /* CONFIG_HIGHMEM */ + + printk("Memory: %luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n", + (unsigned long)nr_free_pages()<< (PAGE_SHIFT-10), + codepages<< (PAGE_SHIFT-10), datapages<< (PAGE_SHIFT-10), + initpages<< (PAGE_SHIFT-10), + (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); + +#ifdef CONFIG_PPC_PMAC + if (agp_special_page) + printk(KERN_INFO "AGP special page: 0x%08lx\n", agp_special_page); +#endif + + mem_init_done = 1; +} + +/* + * Set phys_avail to the amount of physical memory, + * less the kernel text/data/bss. + */ +void __init +set_phys_avail(unsigned long total_memory) +{ + unsigned long kstart, ksize; + + /* + * Initially, available physical memory is equivalent to all + * physical memory. + */ + + phys_avail.regions[0].address = PPC_MEMSTART; + phys_avail.regions[0].size = total_memory; + phys_avail.n_regions = 1; + + /* + * Map out the kernel text/data/bss from the available physical + * memory. + */ + + kstart = __pa(_stext); /* should be 0 */ + ksize = PAGE_ALIGN(klimit - _stext); + + mem_pieces_remove(&phys_avail, kstart, ksize, 0); + mem_pieces_remove(&phys_avail, 0, 0x4000, 0); + +#if defined(CONFIG_BLK_DEV_INITRD) + /* Remove the init RAM disk from the available memory. */ + if (initrd_start) { + mem_pieces_remove(&phys_avail, __pa(initrd_start), + initrd_end - initrd_start, 1); + } +#endif /* CONFIG_BLK_DEV_INITRD */ +#ifdef CONFIG_PPC_OF + /* remove the RTAS pages from the available memory */ + if (rtas_data) + mem_pieces_remove(&phys_avail, rtas_data, rtas_size, 1); +#endif +#ifdef CONFIG_PPC_PMAC + /* Because of some uninorth weirdness, we need a page of + * memory as high as possible (it must be outside of the + * bus address seen as the AGP aperture). It will be used + * by the r128 DRM driver + * + * FIXME: We need to make sure that page doesn't overlap any of the\ + * above. This could be done by improving mem_pieces_find to be able + * to do a backward search from the end of the list. + */ + if (_machine == _MACH_Pmac && find_devices("uni-north-agp")) { + agp_special_page = (total_memory - PAGE_SIZE); + mem_pieces_remove(&phys_avail, agp_special_page, PAGE_SIZE, 0); + agp_special_page = (unsigned long)__va(agp_special_page); + } +#endif /* CONFIG_PPC_PMAC */ +} + +/* Mark some memory as reserved by removing it from phys_avail. */ +void __init reserve_phys_mem(unsigned long start, unsigned long size) +{ + mem_pieces_remove(&phys_avail, start, size, 1); +} diff --git a/arch/powerpc/mm/init64.c b/arch/powerpc/mm/init64.c new file mode 100644 index 00000000000..81f6745b31e --- /dev/null +++ b/arch/powerpc/mm/init64.c @@ -0,0 +1,385 @@ +/* + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Dave Engebretsen + * Rework for PPC64 port. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if PGTABLE_RANGE > USER_VSID_RANGE +#warning Limited user VSID range means pagetable space is wasted +#endif + +#if (TASK_SIZE_USER64 < PGTABLE_RANGE) && (TASK_SIZE_USER64 < USER_VSID_RANGE) +#warning TASK_SIZE is smaller than it needs to be. +#endif + +int mem_init_done; +unsigned long ioremap_bot = IMALLOC_BASE; +static unsigned long phbs_io_bot = PHBS_IO_BASE; + +extern pgd_t swapper_pg_dir[]; +extern struct task_struct *current_set[NR_CPUS]; + +unsigned long klimit = (unsigned long)_end; + +unsigned long _SDR1=0; +unsigned long _ASR=0; + +/* max amount of RAM to use */ +unsigned long __max_memory; + +/* info on what we think the IO hole is */ +unsigned long io_hole_start; +unsigned long io_hole_size; + +/* + * Do very early mm setup. + */ +void __init mm_init_ppc64(void) +{ +#ifndef CONFIG_PPC_ISERIES + unsigned long i; +#endif + + ppc64_boot_msg(0x100, "MM Init"); + + /* This is the story of the IO hole... please, keep seated, + * unfortunately, we are out of oxygen masks at the moment. + * So we need some rough way to tell where your big IO hole + * is. On pmac, it's between 2G and 4G, on POWER3, it's around + * that area as well, on POWER4 we don't have one, etc... + * We need that as a "hint" when sizing the TCE table on POWER3 + * So far, the simplest way that seem work well enough for us it + * to just assume that the first discontinuity in our physical + * RAM layout is the IO hole. That may not be correct in the future + * (and isn't on iSeries but then we don't care ;) + */ + +#ifndef CONFIG_PPC_ISERIES + for (i = 1; i < lmb.memory.cnt; i++) { + unsigned long base, prevbase, prevsize; + + prevbase = lmb.memory.region[i-1].base; + prevsize = lmb.memory.region[i-1].size; + base = lmb.memory.region[i].base; + if (base > (prevbase + prevsize)) { + io_hole_start = prevbase + prevsize; + io_hole_size = base - (prevbase + prevsize); + break; + } + } +#endif /* CONFIG_PPC_ISERIES */ + if (io_hole_start) + printk("IO Hole assumed to be %lx -> %lx\n", + io_hole_start, io_hole_start + io_hole_size - 1); + + ppc64_boot_msg(0x100, "MM Init Done"); +} + +void free_initmem(void) +{ + unsigned long addr; + + addr = (unsigned long)__init_begin; + for (; addr < (unsigned long)__init_end; addr += PAGE_SIZE) { + memset((void *)addr, 0xcc, PAGE_SIZE); + ClearPageReserved(virt_to_page(addr)); + set_page_count(virt_to_page(addr), 1); + free_page(addr); + totalram_pages++; + } + printk ("Freeing unused kernel memory: %luk freed\n", + ((unsigned long)__init_end - (unsigned long)__init_begin) >> 10); +} + +#ifdef CONFIG_BLK_DEV_INITRD +void free_initrd_mem(unsigned long start, unsigned long end) +{ + if (start < end) + printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); + for (; start < end; start += PAGE_SIZE) { + ClearPageReserved(virt_to_page(start)); + set_page_count(virt_to_page(start), 1); + free_page(start); + totalram_pages++; + } +} +#endif + +/* + * Initialize the bootmem system and give it all the memory we + * have available. + */ +#ifndef CONFIG_NEED_MULTIPLE_NODES +void __init do_init_bootmem(void) +{ + unsigned long i; + unsigned long start, bootmap_pages; + unsigned long total_pages = lmb_end_of_DRAM() >> PAGE_SHIFT; + int boot_mapsize; + + /* + * Find an area to use for the bootmem bitmap. Calculate the size of + * bitmap required as (Total Memory) / PAGE_SIZE / BITS_PER_BYTE. + * Add 1 additional page in case the address isn't page-aligned. + */ + bootmap_pages = bootmem_bootmap_pages(total_pages); + + start = lmb_alloc(bootmap_pages<> PAGE_SHIFT, total_pages); + + max_pfn = max_low_pfn; + + /* Add all physical memory to the bootmem map, mark each area + * present. + */ + for (i=0; i < lmb.memory.cnt; i++) + free_bootmem(lmb.memory.region[i].base, + lmb_size_bytes(&lmb.memory, i)); + + /* reserve the sections we're already using */ + for (i=0; i < lmb.reserved.cnt; i++) + reserve_bootmem(lmb.reserved.region[i].base, + lmb_size_bytes(&lmb.reserved, i)); + + for (i=0; i < lmb.memory.cnt; i++) + memory_present(0, lmb_start_pfn(&lmb.memory, i), + lmb_end_pfn(&lmb.memory, i)); +} + +/* + * paging_init() sets up the page tables - in fact we've already done this. + */ +void __init paging_init(void) +{ + unsigned long zones_size[MAX_NR_ZONES]; + unsigned long zholes_size[MAX_NR_ZONES]; + unsigned long total_ram = lmb_phys_mem_size(); + unsigned long top_of_ram = lmb_end_of_DRAM(); + + printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", + top_of_ram, total_ram); + printk(KERN_INFO "Memory hole size: %ldMB\n", + (top_of_ram - total_ram) >> 20); + /* + * All pages are DMA-able so we put them all in the DMA zone. + */ + memset(zones_size, 0, sizeof(zones_size)); + memset(zholes_size, 0, sizeof(zholes_size)); + + zones_size[ZONE_DMA] = top_of_ram >> PAGE_SHIFT; + zholes_size[ZONE_DMA] = (top_of_ram - total_ram) >> PAGE_SHIFT; + + free_area_init_node(0, NODE_DATA(0), zones_size, + __pa(PAGE_OFFSET) >> PAGE_SHIFT, zholes_size); +} +#endif /* ! CONFIG_NEED_MULTIPLE_NODES */ + +static struct kcore_list kcore_vmem; + +static int __init setup_kcore(void) +{ + int i; + + for (i=0; i < lmb.memory.cnt; i++) { + unsigned long base, size; + struct kcore_list *kcore_mem; + + base = lmb.memory.region[i].base; + size = lmb.memory.region[i].size; + + /* GFP_ATOMIC to avoid might_sleep warnings during boot */ + kcore_mem = kmalloc(sizeof(struct kcore_list), GFP_ATOMIC); + if (!kcore_mem) + panic("mem_init: kmalloc failed\n"); + + kclist_add(kcore_mem, __va(base), size); + } + + kclist_add(&kcore_vmem, (void *)VMALLOC_START, VMALLOC_END-VMALLOC_START); + + return 0; +} +module_init(setup_kcore); + +void __init mem_init(void) +{ +#ifdef CONFIG_NEED_MULTIPLE_NODES + int nid; +#endif + pg_data_t *pgdat; + unsigned long i; + struct page *page; + unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize; + + num_physpages = max_low_pfn; /* RAM is assumed contiguous */ + high_memory = (void *) __va(max_low_pfn * PAGE_SIZE); + +#ifdef CONFIG_NEED_MULTIPLE_NODES + for_each_online_node(nid) { + if (NODE_DATA(nid)->node_spanned_pages != 0) { + printk("freeing bootmem node %x\n", nid); + totalram_pages += + free_all_bootmem_node(NODE_DATA(nid)); + } + } +#else + max_mapnr = num_physpages; + totalram_pages += free_all_bootmem(); +#endif + + for_each_pgdat(pgdat) { + for (i = 0; i < pgdat->node_spanned_pages; i++) { + page = pgdat_page_nr(pgdat, i); + if (PageReserved(page)) + reservedpages++; + } + } + + codesize = (unsigned long)&_etext - (unsigned long)&_stext; + initsize = (unsigned long)&__init_end - (unsigned long)&__init_begin; + datasize = (unsigned long)&_edata - (unsigned long)&__init_end; + bsssize = (unsigned long)&__bss_stop - (unsigned long)&__bss_start; + + printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, " + "%luk reserved, %luk data, %luk bss, %luk init)\n", + (unsigned long)nr_free_pages() << (PAGE_SHIFT-10), + num_physpages << (PAGE_SHIFT-10), + codesize >> 10, + reservedpages << (PAGE_SHIFT-10), + datasize >> 10, + bsssize >> 10, + initsize >> 10); + + mem_init_done = 1; + + /* Initialize the vDSO */ + vdso_init(); +} + +void __iomem * reserve_phb_iospace(unsigned long size) +{ + void __iomem *virt_addr; + + if (phbs_io_bot >= IMALLOC_BASE) + panic("reserve_phb_iospace(): phb io space overflow\n"); + + virt_addr = (void __iomem *) phbs_io_bot; + phbs_io_bot += size; + + return virt_addr; +} + +static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags) +{ + memset(addr, 0, kmem_cache_size(cache)); +} + +static const int pgtable_cache_size[2] = { + PTE_TABLE_SIZE, PMD_TABLE_SIZE +}; +static const char *pgtable_cache_name[ARRAY_SIZE(pgtable_cache_size)] = { + "pgd_pte_cache", "pud_pmd_cache", +}; + +kmem_cache_t *pgtable_cache[ARRAY_SIZE(pgtable_cache_size)]; + +void pgtable_cache_init(void) +{ + int i; + + BUILD_BUG_ON(PTE_TABLE_SIZE != pgtable_cache_size[PTE_CACHE_NUM]); + BUILD_BUG_ON(PMD_TABLE_SIZE != pgtable_cache_size[PMD_CACHE_NUM]); + BUILD_BUG_ON(PUD_TABLE_SIZE != pgtable_cache_size[PUD_CACHE_NUM]); + BUILD_BUG_ON(PGD_TABLE_SIZE != pgtable_cache_size[PGD_CACHE_NUM]); + + for (i = 0; i < ARRAY_SIZE(pgtable_cache_size); i++) { + int size = pgtable_cache_size[i]; + const char *name = pgtable_cache_name[i]; + + pgtable_cache[i] = kmem_cache_create(name, + size, size, + SLAB_HWCACHE_ALIGN + | SLAB_MUST_HWCACHE_ALIGN, + zero_ctor, + NULL); + if (! pgtable_cache[i]) + panic("pgtable_cache_init(): could not create %s!\n", + name); + } +} + +pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, + unsigned long size, pgprot_t vma_prot) +{ + if (ppc_md.phys_mem_access_prot) + return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot); + + if (!page_is_ram(addr >> PAGE_SHIFT)) + vma_prot = __pgprot(pgprot_val(vma_prot) + | _PAGE_GUARDED | _PAGE_NO_CACHE); + return vma_prot; +} +EXPORT_SYMBOL(phys_mem_access_prot); diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c new file mode 100644 index 00000000000..345db08e5d2 --- /dev/null +++ b/arch/powerpc/mm/mem.c @@ -0,0 +1,299 @@ +/* + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com) + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mem_pieces.h" +#include "mmu_decl.h" + +#ifndef CPU_FTR_COHERENT_ICACHE +#define CPU_FTR_COHERENT_ICACHE 0 /* XXX for now */ +#define CPU_FTR_NOEXECUTE 0 +#endif + +/* + * This is called by /dev/mem to know if a given address has to + * be mapped non-cacheable or not + */ +int page_is_ram(unsigned long pfn) +{ + unsigned long paddr = (pfn << PAGE_SHIFT); + +#ifndef CONFIG_PPC64 /* XXX for now */ + return paddr < __pa(high_memory); +#else + int i; + for (i=0; i < lmb.memory.cnt; i++) { + unsigned long base; + + base = lmb.memory.region[i].base; + + if ((paddr >= base) && + (paddr < (base + lmb.memory.region[i].size))) { + return 1; + } + } + + return 0; +#endif +} +EXPORT_SYMBOL(page_is_ram); + +pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, + unsigned long size, pgprot_t vma_prot) +{ + if (ppc_md.phys_mem_access_prot) + return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot); + + if (!page_is_ram(addr >> PAGE_SHIFT)) + vma_prot = __pgprot(pgprot_val(vma_prot) + | _PAGE_GUARDED | _PAGE_NO_CACHE); + return vma_prot; +} +EXPORT_SYMBOL(phys_mem_access_prot); + +void show_mem(void) +{ + unsigned long total = 0, reserved = 0; + unsigned long shared = 0, cached = 0; + unsigned long highmem = 0; + struct page *page; + pg_data_t *pgdat; + unsigned long i; + + printk("Mem-info:\n"); + show_free_areas(); + printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); + for_each_pgdat(pgdat) { + for (i = 0; i < pgdat->node_spanned_pages; i++) { + page = pgdat_page_nr(pgdat, i); + total++; + if (PageHighMem(page)) + highmem++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (page_count(page)) + shared += page_count(page) - 1; + } + } + printk("%ld pages of RAM\n", total); +#ifdef CONFIG_HIGHMEM + printk("%ld pages of HIGHMEM\n", highmem); +#endif + printk("%ld reserved pages\n", reserved); + printk("%ld pages shared\n", shared); + printk("%ld pages swap cached\n", cached); +} + +/* + * This is called when a page has been modified by the kernel. + * It just marks the page as not i-cache clean. We do the i-cache + * flush later when the page is given to a user process, if necessary. + */ +void flush_dcache_page(struct page *page) +{ + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &page->flags)) + clear_bit(PG_arch_1, &page->flags); +} +EXPORT_SYMBOL(flush_dcache_page); + +void flush_dcache_icache_page(struct page *page) +{ +#ifdef CONFIG_BOOKE + void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE); + __flush_dcache_icache(start); + kunmap_atomic(start, KM_PPC_SYNC_ICACHE); +#elif defined(CONFIG_8xx) + /* On 8xx there is no need to kmap since highmem is not supported */ + __flush_dcache_icache(page_address(page)); +#else + __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT); +#endif + +} +void clear_user_page(void *page, unsigned long vaddr, struct page *pg) +{ + clear_page(page); + + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + /* + * We shouldnt have to do this, but some versions of glibc + * require it (ld.so assumes zero filled pages are icache clean) + * - Anton + */ + + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &pg->flags)) + clear_bit(PG_arch_1, &pg->flags); +} +EXPORT_SYMBOL(clear_user_page); + +void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, + struct page *pg) +{ + copy_page(vto, vfrom); + + /* + * We should be able to use the following optimisation, however + * there are two problems. + * Firstly a bug in some versions of binutils meant PLT sections + * were not marked executable. + * Secondly the first word in the GOT section is blrl, used + * to establish the GOT address. Until recently the GOT was + * not marked executable. + * - Anton + */ +#if 0 + if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0)) + return; +#endif + + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &pg->flags)) + clear_bit(PG_arch_1, &pg->flags); +} + +void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len) +{ + unsigned long maddr; + + maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK); + flush_icache_range(maddr, maddr + len); + kunmap(page); +} +EXPORT_SYMBOL(flush_icache_user_range); + +/* + * This is called at the end of handling a user page fault, when the + * fault has been handled by updating a PTE in the linux page tables. + * We use it to preload an HPTE into the hash table corresponding to + * the updated linux PTE. + * + * This must always be called with the mm->page_table_lock held + */ +void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, + pte_t pte) +{ + /* handle i-cache coherency */ + unsigned long pfn = pte_pfn(pte); +#ifdef CONFIG_PPC32 + pmd_t *pmd; +#else + unsigned long vsid; + void *pgdir; + pte_t *ptep; + int local = 0; + cpumask_t tmp; + unsigned long flags; +#endif + + /* handle i-cache coherency */ + if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE) && + !cpu_has_feature(CPU_FTR_NOEXECUTE) && + pfn_valid(pfn)) { + struct page *page = pfn_to_page(pfn); + if (!PageReserved(page) + && !test_bit(PG_arch_1, &page->flags)) { + if (vma->vm_mm == current->active_mm) { +#ifdef CONFIG_8xx + /* On 8xx, cache control instructions (particularly + * "dcbst" from flush_dcache_icache) fault as write + * operation if there is an unpopulated TLB entry + * for the address in question. To workaround that, + * we invalidate the TLB here, thus avoiding dcbst + * misbehaviour. + */ + _tlbie(address); +#endif + __flush_dcache_icache((void *) address); + } else + flush_dcache_icache_page(page); + set_bit(PG_arch_1, &page->flags); + } + } + +#ifdef CONFIG_PPC_STD_MMU + /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ + if (!pte_young(pte) || address >= TASK_SIZE) + return; +#ifdef CONFIG_PPC32 + if (Hash == 0) + return; + pmd = pmd_offset(pgd_offset(vma->vm_mm, address), address); + if (!pmd_none(*pmd)) + add_hash_page(vma->vm_mm->context, address, pmd_val(*pmd)); +#else + pgdir = vma->vm_mm->pgd; + if (pgdir == NULL) + return; + + ptep = find_linux_pte(pgdir, ea); + if (!ptep) + return; + + vsid = get_vsid(vma->vm_mm->context.id, ea); + + local_irq_save(flags); + tmp = cpumask_of_cpu(smp_processor_id()); + if (cpus_equal(vma->vm_mm->cpu_vm_mask, tmp)) + local = 1; + + __hash_page(ea, pte_val(pte) & (_PAGE_USER|_PAGE_RW), vsid, ptep, + 0x300, local); + local_irq_restore(flags); +#endif +#endif +} diff --git a/arch/powerpc/mm/mem64.c b/arch/powerpc/mm/mem64.c new file mode 100644 index 00000000000..ef765a84433 --- /dev/null +++ b/arch/powerpc/mm/mem64.c @@ -0,0 +1,259 @@ +/* + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Dave Engebretsen + * Rework for PPC64 port. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * This is called by /dev/mem to know if a given address has to + * be mapped non-cacheable or not + */ +int page_is_ram(unsigned long pfn) +{ + int i; + unsigned long paddr = (pfn << PAGE_SHIFT); + + for (i=0; i < lmb.memory.cnt; i++) { + unsigned long base; + + base = lmb.memory.region[i].base; + + if ((paddr >= base) && + (paddr < (base + lmb.memory.region[i].size))) { + return 1; + } + } + + return 0; +} +EXPORT_SYMBOL(page_is_ram); + +pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, + unsigned long size, pgprot_t vma_prot) +{ + if (ppc_md.phys_mem_access_prot) + return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot); + + if (!page_is_ram(addr >> PAGE_SHIFT)) + vma_prot = __pgprot(pgprot_val(vma_prot) + | _PAGE_GUARDED | _PAGE_NO_CACHE); + return vma_prot; +} +EXPORT_SYMBOL(phys_mem_access_prot); + +void show_mem(void) +{ + unsigned long total = 0, reserved = 0; + unsigned long shared = 0, cached = 0; + struct page *page; + pg_data_t *pgdat; + unsigned long i; + + printk("Mem-info:\n"); + show_free_areas(); + printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10)); + for_each_pgdat(pgdat) { + for (i = 0; i < pgdat->node_spanned_pages; i++) { + page = pgdat_page_nr(pgdat, i); + total++; + if (PageReserved(page)) + reserved++; + else if (PageSwapCache(page)) + cached++; + else if (page_count(page)) + shared += page_count(page) - 1; + } + } + printk("%ld pages of RAM\n", total); + printk("%ld reserved pages\n", reserved); + printk("%ld pages shared\n", shared); + printk("%ld pages swap cached\n", cached); +} + +/* + * This is called when a page has been modified by the kernel. + * It just marks the page as not i-cache clean. We do the i-cache + * flush later when the page is given to a user process, if necessary. + */ +void flush_dcache_page(struct page *page) +{ + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &page->flags)) + clear_bit(PG_arch_1, &page->flags); +} +EXPORT_SYMBOL(flush_dcache_page); + +void clear_user_page(void *page, unsigned long vaddr, struct page *pg) +{ + clear_page(page); + + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + /* + * We shouldnt have to do this, but some versions of glibc + * require it (ld.so assumes zero filled pages are icache clean) + * - Anton + */ + + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &pg->flags)) + clear_bit(PG_arch_1, &pg->flags); +} +EXPORT_SYMBOL(clear_user_page); + +void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, + struct page *pg) +{ + copy_page(vto, vfrom); + + /* + * We should be able to use the following optimisation, however + * there are two problems. + * Firstly a bug in some versions of binutils meant PLT sections + * were not marked executable. + * Secondly the first word in the GOT section is blrl, used + * to establish the GOT address. Until recently the GOT was + * not marked executable. + * - Anton + */ +#if 0 + if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0)) + return; +#endif + + if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) + return; + + /* avoid an atomic op if possible */ + if (test_bit(PG_arch_1, &pg->flags)) + clear_bit(PG_arch_1, &pg->flags); +} + +void flush_icache_user_range(struct vm_area_struct *vma, struct page *page, + unsigned long addr, int len) +{ + unsigned long maddr; + + maddr = (unsigned long)page_address(page) + (addr & ~PAGE_MASK); + flush_icache_range(maddr, maddr + len); +} +EXPORT_SYMBOL(flush_icache_user_range); + +/* + * This is called at the end of handling a user page fault, when the + * fault has been handled by updating a PTE in the linux page tables. + * We use it to preload an HPTE into the hash table corresponding to + * the updated linux PTE. + * + * This must always be called with the mm->page_table_lock held + */ +void update_mmu_cache(struct vm_area_struct *vma, unsigned long ea, + pte_t pte) +{ + unsigned long vsid; + void *pgdir; + pte_t *ptep; + int local = 0; + cpumask_t tmp; + unsigned long flags; + + /* handle i-cache coherency */ + if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE) && + !cpu_has_feature(CPU_FTR_NOEXECUTE)) { + unsigned long pfn = pte_pfn(pte); + if (pfn_valid(pfn)) { + struct page *page = pfn_to_page(pfn); + if (!PageReserved(page) + && !test_bit(PG_arch_1, &page->flags)) { + __flush_dcache_icache(page_address(page)); + set_bit(PG_arch_1, &page->flags); + } + } + } + + /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ + if (!pte_young(pte)) + return; + + pgdir = vma->vm_mm->pgd; + if (pgdir == NULL) + return; + + ptep = find_linux_pte(pgdir, ea); + if (!ptep) + return; + + vsid = get_vsid(vma->vm_mm->context.id, ea); + + local_irq_save(flags); + tmp = cpumask_of_cpu(smp_processor_id()); + if (cpus_equal(vma->vm_mm->cpu_vm_mask, tmp)) + local = 1; + + __hash_page(ea, pte_val(pte) & (_PAGE_USER|_PAGE_RW), vsid, ptep, + 0x300, local); + local_irq_restore(flags); +} diff --git a/arch/powerpc/mm/mem_pieces.c b/arch/powerpc/mm/mem_pieces.c new file mode 100644 index 00000000000..3d639052017 --- /dev/null +++ b/arch/powerpc/mm/mem_pieces.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 1996 Paul Mackerras + * Changes to accommodate Power Macintoshes. + * Cort Dougan + * Rewrites. + * Grant Erickson + * General rework and split from mm/init.c. + * + * Module name: mem_pieces.c + * + * Description: + * Routines and data structures for manipulating and representing + * phyiscal memory extents (i.e. address/length pairs). + * + */ + +#include +#include +#include +#include +#include + +#include "mem_pieces.h" + +extern struct mem_pieces phys_avail; + +static void mem_pieces_print(struct mem_pieces *); + +/* + * Scan a region for a piece of a given size with the required alignment. + */ +void __init * +mem_pieces_find(unsigned int size, unsigned int align) +{ + int i; + unsigned a, e; + struct mem_pieces *mp = &phys_avail; + + for (i = 0; i < mp->n_regions; ++i) { + a = mp->regions[i].address; + e = a + mp->regions[i].size; + a = (a + align - 1) & -align; + if (a + size <= e) { + mem_pieces_remove(mp, a, size, 1); + return (void *) __va(a); + } + } + panic("Couldn't find %u bytes at %u alignment\n", size, align); + + return NULL; +} + +/* + * Remove some memory from an array of pieces + */ +void __init +mem_pieces_remove(struct mem_pieces *mp, unsigned int start, unsigned int size, + int must_exist) +{ + int i, j; + unsigned int end, rs, re; + struct reg_property *rp; + + end = start + size; + for (i = 0, rp = mp->regions; i < mp->n_regions; ++i, ++rp) { + if (end > rp->address && start < rp->address + rp->size) + break; + } + if (i >= mp->n_regions) { + if (must_exist) + printk("mem_pieces_remove: [%x,%x) not in any region\n", + start, end); + return; + } + for (; i < mp->n_regions && end > rp->address; ++i, ++rp) { + rs = rp->address; + re = rs + rp->size; + if (must_exist && (start < rs || end > re)) { + printk("mem_pieces_remove: bad overlap [%x,%x) with", + start, end); + mem_pieces_print(mp); + must_exist = 0; + } + if (start > rs) { + rp->size = start - rs; + if (end < re) { + /* need to split this entry */ + if (mp->n_regions >= MEM_PIECES_MAX) + panic("eek... mem_pieces overflow"); + for (j = mp->n_regions; j > i + 1; --j) + mp->regions[j] = mp->regions[j-1]; + ++mp->n_regions; + rp[1].address = end; + rp[1].size = re - end; + } + } else { + if (end < re) { + rp->address = end; + rp->size = re - end; + } else { + /* need to delete this entry */ + for (j = i; j < mp->n_regions - 1; ++j) + mp->regions[j] = mp->regions[j+1]; + --mp->n_regions; + --i; + --rp; + } + } + } +} + +static void __init +mem_pieces_print(struct mem_pieces *mp) +{ + int i; + + for (i = 0; i < mp->n_regions; ++i) + printk(" [%x, %x)", mp->regions[i].address, + mp->regions[i].address + mp->regions[i].size); + printk("\n"); +} + +void __init +mem_pieces_sort(struct mem_pieces *mp) +{ + unsigned long a, s; + int i, j; + + for (i = 1; i < mp->n_regions; ++i) { + a = mp->regions[i].address; + s = mp->regions[i].size; + for (j = i - 1; j >= 0; --j) { + if (a >= mp->regions[j].address) + break; + mp->regions[j+1] = mp->regions[j]; + } + mp->regions[j+1].address = a; + mp->regions[j+1].size = s; + } +} + +void __init +mem_pieces_coalesce(struct mem_pieces *mp) +{ + unsigned long a, s, ns; + int i, j, d; + + d = 0; + for (i = 0; i < mp->n_regions; i = j) { + a = mp->regions[i].address; + s = mp->regions[i].size; + for (j = i + 1; j < mp->n_regions + && mp->regions[j].address - a <= s; ++j) { + ns = mp->regions[j].address + mp->regions[j].size - a; + if (ns > s) + s = ns; + } + mp->regions[d].address = a; + mp->regions[d].size = s; + ++d; + } + mp->n_regions = d; +} diff --git a/arch/powerpc/mm/mem_pieces.h b/arch/powerpc/mm/mem_pieces.h new file mode 100644 index 00000000000..e2b700dc7f1 --- /dev/null +++ b/arch/powerpc/mm/mem_pieces.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 1996 Paul Mackerras + * Changes to accommodate Power Macintoshes. + * Cort Dougan + * Rewrites. + * Grant Erickson + * General rework and split from mm/init.c. + * + * Module name: mem_pieces.h + * + * Description: + * Routines and data structures for manipulating and representing + * phyiscal memory extents (i.e. address/length pairs). + * + */ + +#ifndef __MEM_PIECES_H__ +#define __MEM_PIECES_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Type Definitions */ + +#define MEM_PIECES_MAX 32 + +struct mem_pieces { + int n_regions; + struct reg_property regions[MEM_PIECES_MAX]; +}; + +/* Function Prototypes */ + +extern void *mem_pieces_find(unsigned int size, unsigned int align); +extern void mem_pieces_remove(struct mem_pieces *mp, unsigned int start, + unsigned int size, int must_exist); +extern void mem_pieces_coalesce(struct mem_pieces *mp); +extern void mem_pieces_sort(struct mem_pieces *mp); + +#ifdef __cplusplus +} +#endif + +#endif /* __MEM_PIECES_H__ */ diff --git a/arch/powerpc/mm/mmu_context.c b/arch/powerpc/mm/mmu_context.c new file mode 100644 index 00000000000..a8816e0f6a8 --- /dev/null +++ b/arch/powerpc/mm/mmu_context.c @@ -0,0 +1,86 @@ +/* + * This file contains the routines for handling the MMU on those + * PowerPC implementations where the MMU substantially follows the + * architecture specification. This includes the 6xx, 7xx, 7xxx, + * 8260, and POWER3 implementations but excludes the 8xx and 4xx. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include + +#include +#include + +mm_context_t next_mmu_context; +unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1]; +#ifdef FEW_CONTEXTS +atomic_t nr_free_contexts; +struct mm_struct *context_mm[LAST_CONTEXT+1]; +void steal_context(void); +#endif /* FEW_CONTEXTS */ + +/* + * Initialize the context management stuff. + */ +void __init +mmu_context_init(void) +{ + /* + * Some processors have too few contexts to reserve one for + * init_mm, and require using context 0 for a normal task. + * Other processors reserve the use of context zero for the kernel. + * This code assumes FIRST_CONTEXT < 32. + */ + context_map[0] = (1 << FIRST_CONTEXT) - 1; + next_mmu_context = FIRST_CONTEXT; +#ifdef FEW_CONTEXTS + atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1); +#endif /* FEW_CONTEXTS */ +} + +#ifdef FEW_CONTEXTS +/* + * Steal a context from a task that has one at the moment. + * This is only used on 8xx and 4xx and we presently assume that + * they don't do SMP. If they do then this will have to check + * whether the MM we steal is in use. + * We also assume that this is only used on systems that don't + * use an MMU hash table - this is true for 8xx and 4xx. + * This isn't an LRU system, it just frees up each context in + * turn (sort-of pseudo-random replacement :). This would be the + * place to implement an LRU scheme if anyone was motivated to do it. + * -- paulus + */ +void +steal_context(void) +{ + struct mm_struct *mm; + + /* free up context `next_mmu_context' */ + /* if we shouldn't free context 0, don't... */ + if (next_mmu_context < FIRST_CONTEXT) + next_mmu_context = FIRST_CONTEXT; + mm = context_mm[next_mmu_context]; + flush_tlb_mm(mm); + destroy_context(mm); +} +#endif /* FEW_CONTEXTS */ diff --git a/arch/powerpc/mm/mmu_context64.c b/arch/powerpc/mm/mmu_context64.c new file mode 100644 index 00000000000..714a84dd8d5 --- /dev/null +++ b/arch/powerpc/mm/mmu_context64.c @@ -0,0 +1,63 @@ +/* + * MMU context allocation for 64-bit kernels. + * + * Copyright (C) 2004 Anton Blanchard, IBM Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(mmu_context_lock); +static DEFINE_IDR(mmu_context_idr); + +int init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + int index; + int err; + +again: + if (!idr_pre_get(&mmu_context_idr, GFP_KERNEL)) + return -ENOMEM; + + spin_lock(&mmu_context_lock); + err = idr_get_new_above(&mmu_context_idr, NULL, 1, &index); + spin_unlock(&mmu_context_lock); + + if (err == -EAGAIN) + goto again; + else if (err) + return err; + + if (index > MAX_CONTEXT) { + idr_remove(&mmu_context_idr, index); + return -ENOMEM; + } + + mm->context.id = index; + + return 0; +} + +void destroy_context(struct mm_struct *mm) +{ + spin_lock(&mmu_context_lock); + idr_remove(&mmu_context_idr, mm->context.id); + spin_unlock(&mmu_context_lock); + + mm->context.id = NO_CONTEXT; +} diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h new file mode 100644 index 00000000000..540f3292b22 --- /dev/null +++ b/arch/powerpc/mm/mmu_decl.h @@ -0,0 +1,85 @@ +/* + * Declarations of procedures and variables shared between files + * in arch/ppc/mm/. + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ +#include +#include + +extern void mapin_ram(void); +extern int map_page(unsigned long va, phys_addr_t pa, int flags); +extern void setbat(int index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); +extern void reserve_phys_mem(unsigned long start, unsigned long size); +extern void settlbcam(int index, unsigned long virt, phys_addr_t phys, + unsigned int size, int flags, unsigned int pid); +extern void invalidate_tlbcam_entry(int index); + +extern int __map_without_bats; +extern unsigned long ioremap_base; +extern unsigned long ioremap_bot; +extern unsigned int rtas_data, rtas_size; + +extern unsigned long total_memory; +extern unsigned long total_lowmem; +extern int mem_init_done; + +extern PTE *Hash, *Hash_end; +extern unsigned long Hash_size, Hash_mask; + +extern unsigned int num_tlbcam_entries; + +/* ...and now those things that may be slightly different between processor + * architectures. -- Dan + */ +#if defined(CONFIG_8xx) +#define flush_HPTE(X, va, pg) _tlbie(va) +#define MMU_init_hw() do { } while(0) +#define mmu_mapin_ram() (0UL) + +#elif defined(CONFIG_4xx) +#define flush_HPTE(X, va, pg) _tlbie(va) +extern void MMU_init_hw(void); +extern unsigned long mmu_mapin_ram(void); + +#elif defined(CONFIG_FSL_BOOKE) +#define flush_HPTE(X, va, pg) _tlbie(va) +extern void MMU_init_hw(void); +extern unsigned long mmu_mapin_ram(void); +extern void adjust_total_lowmem(void); + +#else +/* anything except 4xx or 8xx */ +extern void MMU_init_hw(void); +extern unsigned long mmu_mapin_ram(void); + +/* Be careful....this needs to be updated if we ever encounter 603 SMPs, + * which includes all new 82xx processors. We need tlbie/tlbsync here + * in that case (I think). -- Dan. + */ +static inline void flush_HPTE(unsigned context, unsigned long va, + unsigned long pdval) +{ + if ((Hash != 0) && + cpu_has_feature(CPU_FTR_HPTE_TABLE)) + flush_hash_pages(0, va, pdval, 1); + else + _tlbie(va); +} +#endif diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c new file mode 100644 index 00000000000..81a3d7446d3 --- /dev/null +++ b/arch/powerpc/mm/pgtable.c @@ -0,0 +1,470 @@ +/* + * This file contains the routines setting up the linux page tables. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "mmu_decl.h" + +unsigned long ioremap_base; +unsigned long ioremap_bot; +int io_bat_index; + +#if defined(CONFIG_6xx) || defined(CONFIG_POWER3) +#define HAVE_BATS 1 +#endif + +#if defined(CONFIG_FSL_BOOKE) +#define HAVE_TLBCAM 1 +#endif + +extern char etext[], _stext[]; + +#ifdef CONFIG_SMP +extern void hash_page_sync(void); +#endif + +#ifdef HAVE_BATS +extern unsigned long v_mapped_by_bats(unsigned long va); +extern unsigned long p_mapped_by_bats(unsigned long pa); +void setbat(int index, unsigned long virt, unsigned long phys, + unsigned int size, int flags); + +#else /* !HAVE_BATS */ +#define v_mapped_by_bats(x) (0UL) +#define p_mapped_by_bats(x) (0UL) +#endif /* HAVE_BATS */ + +#ifdef HAVE_TLBCAM +extern unsigned int tlbcam_index; +extern unsigned long v_mapped_by_tlbcam(unsigned long va); +extern unsigned long p_mapped_by_tlbcam(unsigned long pa); +#else /* !HAVE_TLBCAM */ +#define v_mapped_by_tlbcam(x) (0UL) +#define p_mapped_by_tlbcam(x) (0UL) +#endif /* HAVE_TLBCAM */ + +#ifdef CONFIG_PTE_64BIT +/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */ +#define PGDIR_ORDER 1 +#else +#define PGDIR_ORDER 0 +#endif + +pgd_t *pgd_alloc(struct mm_struct *mm) +{ + pgd_t *ret; + + ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGDIR_ORDER); + return ret; +} + +void pgd_free(pgd_t *pgd) +{ + free_pages((unsigned long)pgd, PGDIR_ORDER); +} + +pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) +{ + pte_t *pte; + extern int mem_init_done; + extern void *early_get_page(void); + + if (mem_init_done) { + pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); + } else { + pte = (pte_t *)early_get_page(); + if (pte) + clear_page(pte); + } + return pte; +} + +struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address) +{ + struct page *ptepage; + +#ifdef CONFIG_HIGHPTE + int flags = GFP_KERNEL | __GFP_HIGHMEM | __GFP_REPEAT; +#else + int flags = GFP_KERNEL | __GFP_REPEAT; +#endif + + ptepage = alloc_pages(flags, 0); + if (ptepage) + clear_highpage(ptepage); + return ptepage; +} + +void pte_free_kernel(pte_t *pte) +{ +#ifdef CONFIG_SMP + hash_page_sync(); +#endif + free_page((unsigned long)pte); +} + +void pte_free(struct page *ptepage) +{ +#ifdef CONFIG_SMP + hash_page_sync(); +#endif + __free_page(ptepage); +} + +#ifndef CONFIG_PHYS_64BIT +void __iomem * +ioremap(phys_addr_t addr, unsigned long size) +{ + return __ioremap(addr, size, _PAGE_NO_CACHE); +} +#else /* CONFIG_PHYS_64BIT */ +void __iomem * +ioremap64(unsigned long long addr, unsigned long size) +{ + return __ioremap(addr, size, _PAGE_NO_CACHE); +} + +void __iomem * +ioremap(phys_addr_t addr, unsigned long size) +{ + phys_addr_t addr64 = fixup_bigphys_addr(addr, size); + + return ioremap64(addr64, size); +} +#endif /* CONFIG_PHYS_64BIT */ + +void __iomem * +__ioremap(phys_addr_t addr, unsigned long size, unsigned long flags) +{ + unsigned long v, i; + phys_addr_t p; + int err; + + /* + * Choose an address to map it to. + * Once the vmalloc system is running, we use it. + * Before then, we use space going down from ioremap_base + * (ioremap_bot records where we're up to). + */ + p = addr & PAGE_MASK; + size = PAGE_ALIGN(addr + size) - p; + + /* + * If the address lies within the first 16 MB, assume it's in ISA + * memory space + */ + if (p < 16*1024*1024) + p += _ISA_MEM_BASE; + + /* + * Don't allow anybody to remap normal RAM that we're using. + * mem_init() sets high_memory so only do the check after that. + */ + if ( mem_init_done && (p < virt_to_phys(high_memory)) ) + { + printk("__ioremap(): phys addr "PHYS_FMT" is RAM lr %p\n", p, + __builtin_return_address(0)); + return NULL; + } + + if (size == 0) + return NULL; + + /* + * Is it already mapped? Perhaps overlapped by a previous + * BAT mapping. If the whole area is mapped then we're done, + * otherwise remap it since we want to keep the virt addrs for + * each request contiguous. + * + * We make the assumption here that if the bottom and top + * of the range we want are mapped then it's mapped to the + * same virt address (and this is contiguous). + * -- Cort + */ + if ((v = p_mapped_by_bats(p)) /*&& p_mapped_by_bats(p+size-1)*/ ) + goto out; + + if ((v = p_mapped_by_tlbcam(p))) + goto out; + + if (mem_init_done) { + struct vm_struct *area; + area = get_vm_area(size, VM_IOREMAP); + if (area == 0) + return NULL; + v = (unsigned long) area->addr; + } else { + v = (ioremap_bot -= size); + } + + if ((flags & _PAGE_PRESENT) == 0) + flags |= _PAGE_KERNEL; + if (flags & _PAGE_NO_CACHE) + flags |= _PAGE_GUARDED; + + /* + * Should check if it is a candidate for a BAT mapping + */ + + err = 0; + for (i = 0; i < size && err == 0; i += PAGE_SIZE) + err = map_page(v+i, p+i, flags); + if (err) { + if (mem_init_done) + vunmap((void *)v); + return NULL; + } + +out: + return (void __iomem *) (v + ((unsigned long)addr & ~PAGE_MASK)); +} + +void iounmap(volatile void __iomem *addr) +{ + /* + * If mapped by BATs then there is nothing to do. + * Calling vfree() generates a benign warning. + */ + if (v_mapped_by_bats((unsigned long)addr)) return; + + if (addr > high_memory && (unsigned long) addr < ioremap_bot) + vunmap((void *) (PAGE_MASK & (unsigned long)addr)); +} + +void __iomem *ioport_map(unsigned long port, unsigned int len) +{ + return (void __iomem *) (port + _IO_BASE); +} + +void ioport_unmap(void __iomem *addr) +{ + /* Nothing to do */ +} +EXPORT_SYMBOL(ioport_map); +EXPORT_SYMBOL(ioport_unmap); + +int +map_page(unsigned long va, phys_addr_t pa, int flags) +{ + pmd_t *pd; + pte_t *pg; + int err = -ENOMEM; + + spin_lock(&init_mm.page_table_lock); + /* Use upper 10 bits of VA to index the first level map */ + pd = pmd_offset(pgd_offset_k(va), va); + /* Use middle 10 bits of VA to index the second-level map */ + pg = pte_alloc_kernel(&init_mm, pd, va); + if (pg != 0) { + err = 0; + set_pte_at(&init_mm, va, pg, pfn_pte(pa >> PAGE_SHIFT, __pgprot(flags))); + if (mem_init_done) + flush_HPTE(0, va, pmd_val(*pd)); + } + spin_unlock(&init_mm.page_table_lock); + return err; +} + +/* + * Map in all of physical memory starting at KERNELBASE. + */ +void __init mapin_ram(void) +{ + unsigned long v, p, s, f; + + s = mmu_mapin_ram(); + v = KERNELBASE + s; + p = PPC_MEMSTART + s; + for (; s < total_lowmem; s += PAGE_SIZE) { + if ((char *) v >= _stext && (char *) v < etext) + f = _PAGE_RAM_TEXT; + else + f = _PAGE_RAM; + map_page(v, p, f); + v += PAGE_SIZE; + p += PAGE_SIZE; + } +} + +/* is x a power of 2? */ +#define is_power_of_2(x) ((x) != 0 && (((x) & ((x) - 1)) == 0)) + +/* is x a power of 4? */ +#define is_power_of_4(x) ((x) != 0 && (((x) & (x-1)) == 0) && (ffs(x) & 1)) + +/* + * Set up a mapping for a block of I/O. + * virt, phys, size must all be page-aligned. + * This should only be called before ioremap is called. + */ +void __init io_block_mapping(unsigned long virt, phys_addr_t phys, + unsigned int size, int flags) +{ + int i; + + if (virt > KERNELBASE && virt < ioremap_bot) + ioremap_bot = ioremap_base = virt; + +#ifdef HAVE_BATS + /* + * Use a BAT for this if possible... + */ + if (io_bat_index < 2 && is_power_of_2(size) + && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) { + setbat(io_bat_index, virt, phys, size, flags); + ++io_bat_index; + return; + } +#endif /* HAVE_BATS */ + +#ifdef HAVE_TLBCAM + /* + * Use a CAM for this if possible... + */ + if (tlbcam_index < num_tlbcam_entries && is_power_of_4(size) + && (virt & (size - 1)) == 0 && (phys & (size - 1)) == 0) { + settlbcam(tlbcam_index, virt, phys, size, flags, 0); + ++tlbcam_index; + return; + } +#endif /* HAVE_TLBCAM */ + + /* No BATs available, put it in the page tables. */ + for (i = 0; i < size; i += PAGE_SIZE) + map_page(virt + i, phys + i, flags); +} + +/* Scan the real Linux page tables and return a PTE pointer for + * a virtual address in a context. + * Returns true (1) if PTE was found, zero otherwise. The pointer to + * the PTE pointer is unmodified if PTE is not found. + */ +int +get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep) +{ + pgd_t *pgd; + pmd_t *pmd; + pte_t *pte; + int retval = 0; + + pgd = pgd_offset(mm, addr & PAGE_MASK); + if (pgd) { + pmd = pmd_offset(pgd, addr & PAGE_MASK); + if (pmd_present(*pmd)) { + pte = pte_offset_map(pmd, addr & PAGE_MASK); + if (pte) { + retval = 1; + *ptep = pte; + /* XXX caller needs to do pte_unmap, yuck */ + } + } + } + return(retval); +} + +/* Find physical address for this virtual address. Normally used by + * I/O functions, but anyone can call it. + */ +unsigned long iopa(unsigned long addr) +{ + unsigned long pa; + + /* I don't know why this won't work on PMacs or CHRP. It + * appears there is some bug, or there is some implicit + * mapping done not properly represented by BATs or in page + * tables.......I am actively working on resolving this, but + * can't hold up other stuff. -- Dan + */ + pte_t *pte; + struct mm_struct *mm; + + /* Check the BATs */ + pa = v_mapped_by_bats(addr); + if (pa) + return pa; + + /* Allow mapping of user addresses (within the thread) + * for DMA if necessary. + */ + if (addr < TASK_SIZE) + mm = current->mm; + else + mm = &init_mm; + + pa = 0; + if (get_pteptr(mm, addr, &pte)) { + pa = (pte_val(*pte) & PAGE_MASK) | (addr & ~PAGE_MASK); + pte_unmap(pte); + } + + return(pa); +} + +/* This is will find the virtual address for a physical one.... + * Swiped from APUS, could be dangerous :-). + * This is only a placeholder until I really find a way to make this + * work. -- Dan + */ +unsigned long +mm_ptov (unsigned long paddr) +{ + unsigned long ret; +#if 0 + if (paddr < 16*1024*1024) + ret = ZTWO_VADDR(paddr); + else { + int i; + + for (i = 0; i < kmap_chunk_count;){ + unsigned long phys = kmap_chunks[i++]; + unsigned long size = kmap_chunks[i++]; + unsigned long virt = kmap_chunks[i++]; + if (paddr >= phys + && paddr < (phys + size)){ + ret = virt + paddr - phys; + goto exit; + } + } + + ret = (unsigned long) __va(paddr); + } +exit: +#ifdef DEBUGPV + printk ("PTOV(%lx)=%lx\n", paddr, ret); +#endif +#else + ret = (unsigned long)paddr + KERNELBASE; +#endif + return ret; +} + diff --git a/arch/powerpc/mm/pgtable64.c b/arch/powerpc/mm/pgtable64.c new file mode 100644 index 00000000000..724f97e5dee --- /dev/null +++ b/arch/powerpc/mm/pgtable64.c @@ -0,0 +1,357 @@ +/* + * This file contains ioremap and related functions for 64-bit machines. + * + * Derived from arch/ppc64/mm/init.c + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@samba.org) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Dave Engebretsen + * Rework for PPC64 port. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if PGTABLE_RANGE > USER_VSID_RANGE +#warning Limited user VSID range means pagetable space is wasted +#endif + +#if (TASK_SIZE_USER64 < PGTABLE_RANGE) && (TASK_SIZE_USER64 < USER_VSID_RANGE) +#warning TASK_SIZE is smaller than it needs to be. +#endif + +int mem_init_done; +unsigned long ioremap_bot = IMALLOC_BASE; +static unsigned long phbs_io_bot = PHBS_IO_BASE; + +extern pgd_t swapper_pg_dir[]; +extern struct task_struct *current_set[NR_CPUS]; + +unsigned long klimit = (unsigned long)_end; + +/* max amount of RAM to use */ +unsigned long __max_memory; + +/* info on what we think the IO hole is */ +unsigned long io_hole_start; +unsigned long io_hole_size; + +#ifdef CONFIG_PPC_ISERIES + +void __iomem *ioremap(unsigned long addr, unsigned long size) +{ + return (void __iomem *)addr; +} + +extern void __iomem *__ioremap(unsigned long addr, unsigned long size, + unsigned long flags) +{ + return (void __iomem *)addr; +} + +void iounmap(volatile void __iomem *addr) +{ + return; +} + +#else + +/* + * map_io_page currently only called by __ioremap + * map_io_page adds an entry to the ioremap page table + * and adds an entry to the HPT, possibly bolting it + */ +static int map_io_page(unsigned long ea, unsigned long pa, int flags) +{ + pgd_t *pgdp; + pud_t *pudp; + pmd_t *pmdp; + pte_t *ptep; + unsigned long vsid; + + if (mem_init_done) { + spin_lock(&init_mm.page_table_lock); + pgdp = pgd_offset_k(ea); + pudp = pud_alloc(&init_mm, pgdp, ea); + if (!pudp) + return -ENOMEM; + pmdp = pmd_alloc(&init_mm, pudp, ea); + if (!pmdp) + return -ENOMEM; + ptep = pte_alloc_kernel(&init_mm, pmdp, ea); + if (!ptep) + return -ENOMEM; + set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, + __pgprot(flags))); + spin_unlock(&init_mm.page_table_lock); + } else { + unsigned long va, vpn, hash, hpteg; + + /* + * If the mm subsystem is not fully up, we cannot create a + * linux page table entry for this mapping. Simply bolt an + * entry in the hardware page table. + */ + vsid = get_kernel_vsid(ea); + va = (vsid << 28) | (ea & 0xFFFFFFF); + vpn = va >> PAGE_SHIFT; + + hash = hpt_hash(vpn, 0); + + hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP); + + /* Panic if a pte grpup is full */ + if (ppc_md.hpte_insert(hpteg, va, pa >> PAGE_SHIFT, + HPTE_V_BOLTED, + _PAGE_NO_CACHE|_PAGE_GUARDED|PP_RWXX) + == -1) { + panic("map_io_page: could not insert mapping"); + } + } + return 0; +} + + +static void __iomem * __ioremap_com(unsigned long addr, unsigned long pa, + unsigned long ea, unsigned long size, + unsigned long flags) +{ + unsigned long i; + + if ((flags & _PAGE_PRESENT) == 0) + flags |= pgprot_val(PAGE_KERNEL); + + for (i = 0; i < size; i += PAGE_SIZE) + if (map_io_page(ea+i, pa+i, flags)) + return NULL; + + return (void __iomem *) (ea + (addr & ~PAGE_MASK)); +} + + +void __iomem * +ioremap(unsigned long addr, unsigned long size) +{ + return __ioremap(addr, size, _PAGE_NO_CACHE | _PAGE_GUARDED); +} + +void __iomem * __ioremap(unsigned long addr, unsigned long size, + unsigned long flags) +{ + unsigned long pa, ea; + void __iomem *ret; + + /* + * Choose an address to map it to. + * Once the imalloc system is running, we use it. + * Before that, we map using addresses going + * up from ioremap_bot. imalloc will use + * the addresses from ioremap_bot through + * IMALLOC_END + * + */ + pa = addr & PAGE_MASK; + size = PAGE_ALIGN(addr + size) - pa; + + if (size == 0) + return NULL; + + if (mem_init_done) { + struct vm_struct *area; + area = im_get_free_area(size); + if (area == NULL) + return NULL; + ea = (unsigned long)(area->addr); + ret = __ioremap_com(addr, pa, ea, size, flags); + if (!ret) + im_free(area->addr); + } else { + ea = ioremap_bot; + ret = __ioremap_com(addr, pa, ea, size, flags); + if (ret) + ioremap_bot += size; + } + return ret; +} + +#define IS_PAGE_ALIGNED(_val) ((_val) == ((_val) & PAGE_MASK)) + +int __ioremap_explicit(unsigned long pa, unsigned long ea, + unsigned long size, unsigned long flags) +{ + struct vm_struct *area; + void __iomem *ret; + + /* For now, require page-aligned values for pa, ea, and size */ + if (!IS_PAGE_ALIGNED(pa) || !IS_PAGE_ALIGNED(ea) || + !IS_PAGE_ALIGNED(size)) { + printk(KERN_ERR "unaligned value in %s\n", __FUNCTION__); + return 1; + } + + if (!mem_init_done) { + /* Two things to consider in this case: + * 1) No records will be kept (imalloc, etc) that the region + * has been remapped + * 2) It won't be easy to iounmap() the region later (because + * of 1) + */ + ; + } else { + area = im_get_area(ea, size, + IM_REGION_UNUSED|IM_REGION_SUBSET|IM_REGION_EXISTS); + if (area == NULL) { + /* Expected when PHB-dlpar is in play */ + return 1; + } + if (ea != (unsigned long) area->addr) { + printk(KERN_ERR "unexpected addr return from " + "im_get_area\n"); + return 1; + } + } + + ret = __ioremap_com(pa, pa, ea, size, flags); + if (ret == NULL) { + printk(KERN_ERR "ioremap_explicit() allocation failure !\n"); + return 1; + } + if (ret != (void *) ea) { + printk(KERN_ERR "__ioremap_com() returned unexpected addr\n"); + return 1; + } + + return 0; +} + +/* + * Unmap an IO region and remove it from imalloc'd list. + * Access to IO memory should be serialized by driver. + * This code is modeled after vmalloc code - unmap_vm_area() + * + * XXX what about calls before mem_init_done (ie python_countermeasures()) + */ +void iounmap(volatile void __iomem *token) +{ + void *addr; + + if (!mem_init_done) + return; + + addr = (void *) ((unsigned long __force) token & PAGE_MASK); + + im_free(addr); +} + +static int iounmap_subset_regions(unsigned long addr, unsigned long size) +{ + struct vm_struct *area; + + /* Check whether subsets of this region exist */ + area = im_get_area(addr, size, IM_REGION_SUPERSET); + if (area == NULL) + return 1; + + while (area) { + iounmap((void __iomem *) area->addr); + area = im_get_area(addr, size, + IM_REGION_SUPERSET); + } + + return 0; +} + +int iounmap_explicit(volatile void __iomem *start, unsigned long size) +{ + struct vm_struct *area; + unsigned long addr; + int rc; + + addr = (unsigned long __force) start & PAGE_MASK; + + /* Verify that the region either exists or is a subset of an existing + * region. In the latter case, split the parent region to create + * the exact region + */ + area = im_get_area(addr, size, + IM_REGION_EXISTS | IM_REGION_SUBSET); + if (area == NULL) { + /* Determine whether subset regions exist. If so, unmap */ + rc = iounmap_subset_regions(addr, size); + if (rc) { + printk(KERN_ERR + "%s() cannot unmap nonexistent range 0x%lx\n", + __FUNCTION__, addr); + return 1; + } + } else { + iounmap((void __iomem *) area->addr); + } + /* + * FIXME! This can't be right: + iounmap(area->addr); + * Maybe it should be "iounmap(area);" + */ + return 0; +} + +#endif + +EXPORT_SYMBOL(ioremap); +EXPORT_SYMBOL(__ioremap); +EXPORT_SYMBOL(iounmap); diff --git a/arch/powerpc/mm/ppc_mmu.c b/arch/powerpc/mm/ppc_mmu.c new file mode 100644 index 00000000000..9a381ed5eb2 --- /dev/null +++ b/arch/powerpc/mm/ppc_mmu.c @@ -0,0 +1,296 @@ +/* + * This file contains the routines for handling the MMU on those + * PowerPC implementations where the MMU substantially follows the + * architecture specification. This includes the 6xx, 7xx, 7xxx, + * 8260, and POWER3 implementations but excludes the 8xx and 4xx. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "mmu_decl.h" +#include "mem_pieces.h" + +PTE *Hash, *Hash_end; +unsigned long Hash_size, Hash_mask; +unsigned long _SDR1; + +union ubat { /* BAT register values to be loaded */ + BAT bat; +#ifdef CONFIG_PPC64BRIDGE + u64 word[2]; +#else + u32 word[2]; +#endif +} BATS[4][2]; /* 4 pairs of IBAT, DBAT */ + +struct batrange { /* stores address ranges mapped by BATs */ + unsigned long start; + unsigned long limit; + unsigned long phys; +} bat_addrs[4]; + +/* + * Return PA for this VA if it is mapped by a BAT, or 0 + */ +unsigned long v_mapped_by_bats(unsigned long va) +{ + int b; + for (b = 0; b < 4; ++b) + if (va >= bat_addrs[b].start && va < bat_addrs[b].limit) + return bat_addrs[b].phys + (va - bat_addrs[b].start); + return 0; +} + +/* + * Return VA for a given PA or 0 if not mapped + */ +unsigned long p_mapped_by_bats(unsigned long pa) +{ + int b; + for (b = 0; b < 4; ++b) + if (pa >= bat_addrs[b].phys + && pa < (bat_addrs[b].limit-bat_addrs[b].start) + +bat_addrs[b].phys) + return bat_addrs[b].start+(pa-bat_addrs[b].phys); + return 0; +} + +unsigned long __init mmu_mapin_ram(void) +{ +#ifdef CONFIG_POWER4 + return 0; +#else + unsigned long tot, bl, done; + unsigned long max_size = (256<<20); + unsigned long align; + + if (__map_without_bats) + return 0; + + /* Set up BAT2 and if necessary BAT3 to cover RAM. */ + + /* Make sure we don't map a block larger than the + smallest alignment of the physical address. */ + /* alignment of PPC_MEMSTART */ + align = ~(PPC_MEMSTART-1) & PPC_MEMSTART; + /* set BAT block size to MIN(max_size, align) */ + if (align && align < max_size) + max_size = align; + + tot = total_lowmem; + for (bl = 128<<10; bl < max_size; bl <<= 1) { + if (bl * 2 > tot) + break; + } + + setbat(2, KERNELBASE, PPC_MEMSTART, bl, _PAGE_RAM); + done = (unsigned long)bat_addrs[2].limit - KERNELBASE + 1; + if ((done < tot) && !bat_addrs[3].limit) { + /* use BAT3 to cover a bit more */ + tot -= done; + for (bl = 128<<10; bl < max_size; bl <<= 1) + if (bl * 2 > tot) + break; + setbat(3, KERNELBASE+done, PPC_MEMSTART+done, bl, _PAGE_RAM); + done = (unsigned long)bat_addrs[3].limit - KERNELBASE + 1; + } + + return done; +#endif +} + +/* + * Set up one of the I/D BAT (block address translation) register pairs. + * The parameters are not checked; in particular size must be a power + * of 2 between 128k and 256M. + */ +void __init setbat(int index, unsigned long virt, unsigned long phys, + unsigned int size, int flags) +{ + unsigned int bl; + int wimgxpp; + union ubat *bat = BATS[index]; + + if (((flags & _PAGE_NO_CACHE) == 0) && + cpu_has_feature(CPU_FTR_NEED_COHERENT)) + flags |= _PAGE_COHERENT; + + bl = (size >> 17) - 1; + if (PVR_VER(mfspr(SPRN_PVR)) != 1) { + /* 603, 604, etc. */ + /* Do DBAT first */ + wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE + | _PAGE_COHERENT | _PAGE_GUARDED); + wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX; + bat[1].word[0] = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */ + bat[1].word[1] = phys | wimgxpp; +#ifndef CONFIG_KGDB /* want user access for breakpoints */ + if (flags & _PAGE_USER) +#endif + bat[1].bat.batu.vp = 1; + if (flags & _PAGE_GUARDED) { + /* G bit must be zero in IBATs */ + bat[0].word[0] = bat[0].word[1] = 0; + } else { + /* make IBAT same as DBAT */ + bat[0] = bat[1]; + } + } else { + /* 601 cpu */ + if (bl > BL_8M) + bl = BL_8M; + wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE + | _PAGE_COHERENT); + wimgxpp |= (flags & _PAGE_RW)? + ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX; + bat->word[0] = virt | wimgxpp | 4; /* Ks=0, Ku=1 */ + bat->word[1] = phys | bl | 0x40; /* V=1 */ + } + + bat_addrs[index].start = virt; + bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1; + bat_addrs[index].phys = phys; +} + +/* + * Initialize the hash table and patch the instructions in hashtable.S. + */ +void __init MMU_init_hw(void) +{ + unsigned int hmask, mb, mb2; + unsigned int n_hpteg, lg_n_hpteg; + + extern unsigned int hash_page_patch_A[]; + extern unsigned int hash_page_patch_B[], hash_page_patch_C[]; + extern unsigned int hash_page[]; + extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[]; + + if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) { + /* + * Put a blr (procedure return) instruction at the + * start of hash_page, since we can still get DSI + * exceptions on a 603. + */ + hash_page[0] = 0x4e800020; + flush_icache_range((unsigned long) &hash_page[0], + (unsigned long) &hash_page[1]); + return; + } + + if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105); + +#ifdef CONFIG_PPC64BRIDGE +#define LG_HPTEG_SIZE 7 /* 128 bytes per HPTEG */ +#define SDR1_LOW_BITS (lg_n_hpteg - 11) +#define MIN_N_HPTEG 2048 /* min 256kB hash table */ +#else +#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */ +#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10) +#define MIN_N_HPTEG 1024 /* min 64kB hash table */ +#endif + +#ifdef CONFIG_POWER4 + /* The hash table has already been allocated and initialized + in prom.c */ + n_hpteg = Hash_size >> LG_HPTEG_SIZE; + lg_n_hpteg = __ilog2(n_hpteg); + + /* Remove the hash table from the available memory */ + if (Hash) + reserve_phys_mem(__pa(Hash), Hash_size); + +#else /* CONFIG_POWER4 */ + /* + * Allow 1 HPTE (1/8 HPTEG) for each page of memory. + * This is less than the recommended amount, but then + * Linux ain't AIX. + */ + n_hpteg = total_memory / (PAGE_SIZE * 8); + if (n_hpteg < MIN_N_HPTEG) + n_hpteg = MIN_N_HPTEG; + lg_n_hpteg = __ilog2(n_hpteg); + if (n_hpteg & (n_hpteg - 1)) { + ++lg_n_hpteg; /* round up if not power of 2 */ + n_hpteg = 1 << lg_n_hpteg; + } + Hash_size = n_hpteg << LG_HPTEG_SIZE; + + /* + * Find some memory for the hash table. + */ + if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322); + Hash = mem_pieces_find(Hash_size, Hash_size); + cacheable_memzero(Hash, Hash_size); + _SDR1 = __pa(Hash) | SDR1_LOW_BITS; +#endif /* CONFIG_POWER4 */ + + Hash_end = (PTE *) ((unsigned long)Hash + Hash_size); + + printk("Total memory = %ldMB; using %ldkB for hash table (at %p)\n", + total_memory >> 20, Hash_size >> 10, Hash); + + + /* + * Patch up the instructions in hashtable.S:create_hpte + */ + if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345); + Hash_mask = n_hpteg - 1; + hmask = Hash_mask >> (16 - LG_HPTEG_SIZE); + mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg; + if (lg_n_hpteg > 16) + mb2 = 16 - LG_HPTEG_SIZE; + + hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff) + | ((unsigned int)(Hash) >> 16); + hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6); + hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6); + hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask; + hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask; + + /* + * Ensure that the locations we've patched have been written + * out from the data cache and invalidated in the instruction + * cache, on those machines with split caches. + */ + flush_icache_range((unsigned long) &hash_page_patch_A[0], + (unsigned long) &hash_page_patch_C[1]); + + /* + * Patch up the instructions in hashtable.S:flush_hash_page + */ + flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff) + | ((unsigned int)(Hash) >> 16); + flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6); + flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6); + flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask; + flush_icache_range((unsigned long) &flush_hash_patch_A[0], + (unsigned long) &flush_hash_patch_B[1]); + + if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205); +} diff --git a/arch/powerpc/mm/tlb.c b/arch/powerpc/mm/tlb.c new file mode 100644 index 00000000000..6c3dc3c44c8 --- /dev/null +++ b/arch/powerpc/mm/tlb.c @@ -0,0 +1,183 @@ +/* + * This file contains the routines for TLB flushing. + * On machines where the MMU uses a hash table to store virtual to + * physical translations, these routines flush entries from the + * hash table also. + * -- paulus + * + * Derived from arch/ppc/mm/init.c: + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au) + * and Cort Dougan (PReP) (cort@cs.nmt.edu) + * Copyright (C) 1996 Paul Mackerras + * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). + * + * Derived from "arch/i386/mm/init.c" + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "mmu_decl.h" + +/* + * Called when unmapping pages to flush entries from the TLB/hash table. + */ +void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, unsigned long addr) +{ + unsigned long ptephys; + + if (Hash != 0) { + ptephys = __pa(ptep) & PAGE_MASK; + flush_hash_pages(mm->context, addr, ptephys, 1); + } +} + +/* + * Called by ptep_set_access_flags, must flush on CPUs for which the + * DSI handler can't just "fixup" the TLB on a write fault + */ +void flush_tlb_page_nohash(struct vm_area_struct *vma, unsigned long addr) +{ + if (Hash != 0) + return; + _tlbie(addr); +} + +/* + * Called at the end of a mmu_gather operation to make sure the + * TLB flush is completely done. + */ +void tlb_flush(struct mmu_gather *tlb) +{ + if (Hash == 0) { + /* + * 603 needs to flush the whole TLB here since + * it doesn't use a hash table. + */ + _tlbia(); + } +} + +/* + * TLB flushing: + * + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(vma, start, end) flushes a range of pages + * - flush_tlb_kernel_range(start, end) flushes kernel pages + * + * since the hardware hash table functions as an extension of the + * tlb as far as the linux tables are concerned, flush it too. + * -- Cort + */ + +/* + * 750 SMP is a Bad Idea because the 750 doesn't broadcast all + * the cache operations on the bus. Hence we need to use an IPI + * to get the other CPU(s) to invalidate their TLBs. + */ +#ifdef CONFIG_SMP_750 +#define FINISH_FLUSH smp_send_tlb_invalidate(0) +#else +#define FINISH_FLUSH do { } while (0) +#endif + +static void flush_range(struct mm_struct *mm, unsigned long start, + unsigned long end) +{ + pmd_t *pmd; + unsigned long pmd_end; + int count; + unsigned int ctx = mm->context; + + if (Hash == 0) { + _tlbia(); + return; + } + start &= PAGE_MASK; + if (start >= end) + return; + end = (end - 1) | ~PAGE_MASK; + pmd = pmd_offset(pgd_offset(mm, start), start); + for (;;) { + pmd_end = ((start + PGDIR_SIZE) & PGDIR_MASK) - 1; + if (pmd_end > end) + pmd_end = end; + if (!pmd_none(*pmd)) { + count = ((pmd_end - start) >> PAGE_SHIFT) + 1; + flush_hash_pages(ctx, start, pmd_val(*pmd), count); + } + if (pmd_end == end) + break; + start = pmd_end + 1; + ++pmd; + } +} + +/* + * Flush kernel TLB entries in the given range + */ +void flush_tlb_kernel_range(unsigned long start, unsigned long end) +{ + flush_range(&init_mm, start, end); + FINISH_FLUSH; +} + +/* + * Flush all the (user) entries for the address space described by mm. + */ +void flush_tlb_mm(struct mm_struct *mm) +{ + struct vm_area_struct *mp; + + if (Hash == 0) { + _tlbia(); + return; + } + + for (mp = mm->mmap; mp != NULL; mp = mp->vm_next) + flush_range(mp->vm_mm, mp->vm_start, mp->vm_end); + FINISH_FLUSH; +} + +void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) +{ + struct mm_struct *mm; + pmd_t *pmd; + + if (Hash == 0) { + _tlbie(vmaddr); + return; + } + mm = (vmaddr < TASK_SIZE)? vma->vm_mm: &init_mm; + pmd = pmd_offset(pgd_offset(mm, vmaddr), vmaddr); + if (!pmd_none(*pmd)) + flush_hash_pages(mm->context, vmaddr, pmd_val(*pmd), 1); + FINISH_FLUSH; +} + +/* + * For each address in the range, find the pte for the address + * and check _PAGE_HASHPTE bit; if it is set, find and destroy + * the corresponding HPTE. + */ +void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end) +{ + flush_range(vma->vm_mm, start, end); + FINISH_FLUSH; +} diff --git a/arch/powerpc/platforms/4xx/Kconfig b/arch/powerpc/platforms/4xx/Kconfig new file mode 100644 index 00000000000..ed39d6a3d22 --- /dev/null +++ b/arch/powerpc/platforms/4xx/Kconfig @@ -0,0 +1,280 @@ +config 4xx + bool + depends on 40x || 44x + default y + +config WANT_EARLY_SERIAL + bool + select SERIAL_8250 + default n + +menu "AMCC 4xx options" + depends on 4xx + +choice + prompt "Machine Type" + depends on 40x + default WALNUT + +config BUBINGA + bool "Bubinga" + select WANT_EARLY_SERIAL + help + This option enables support for the IBM 405EP evaluation board. + +config CPCI405 + bool "CPCI405" + help + This option enables support for the CPCI405 board. + +config EP405 + bool "EP405/EP405PC" + help + This option enables support for the EP405/EP405PC boards. + +config REDWOOD_5 + bool "Redwood-5" + help + This option enables support for the IBM STB04 evaluation board. + +config REDWOOD_6 + bool "Redwood-6" + help + This option enables support for the IBM STBx25xx evaluation board. + +config SYCAMORE + bool "Sycamore" + help + This option enables support for the IBM PPC405GPr evaluation board. + +config WALNUT + bool "Walnut" + help + This option enables support for the IBM PPC405GP evaluation board. + +config XILINX_ML300 + bool "Xilinx-ML300" + help + This option enables support for the Xilinx ML300 evaluation board. + +endchoice + +choice + prompt "Machine Type" + depends on 44x + default EBONY + +config BAMBOO + bool "Bamboo" + select WANT_EARLY_SERIAL + help + This option enables support for the IBM PPC440EP evaluation board. + +config EBONY + bool "Ebony" + select WANT_EARLY_SERIAL + help + This option enables support for the IBM PPC440GP evaluation board. + +config LUAN + bool "Luan" + select WANT_EARLY_SERIAL + help + This option enables support for the IBM PPC440SP evaluation board. + +config OCOTEA + bool "Ocotea" + select WANT_EARLY_SERIAL + help + This option enables support for the IBM PPC440GX evaluation board. + +endchoice + +config EP405PC + bool "EP405PC Support" + depends on EP405 + + +# It's often necessary to know the specific 4xx processor type. +# Fortunately, it is impled (so far) from the board type, so we +# don't need to ask more redundant questions. +config NP405H + bool + depends on ASH + default y + +config 440EP + bool + depends on BAMBOO + select PPC_FPU + default y + +config 440GP + bool + depends on EBONY + default y + +config 440GX + bool + depends on OCOTEA + default y + +config 440SP + bool + depends on LUAN + default y + +config 440 + bool + depends on 440GP || 440SP || 440EP + default y + +config 440A + bool + depends on 440GX + default y + +config IBM440EP_ERR42 + bool + depends on 440EP + default y + +# All 405-based cores up until the 405GPR and 405EP have this errata. +config IBM405_ERR77 + bool + depends on 40x && !403GCX && !405GPR && !405EP + default y + +# All 40x-based cores, up until the 405GPR and 405EP have this errata. +config IBM405_ERR51 + bool + depends on 40x && !405GPR && !405EP + default y + +config BOOKE + bool + depends on 44x + default y + +config IBM_OCP + bool + depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT + default y + +config XILINX_OCP + bool + depends on XILINX_ML300 + default y + +config IBM_EMAC4 + bool + depends on 440GX || 440SP + default y + +config BIOS_FIXUP + bool + depends on BUBINGA || EP405 || SYCAMORE || WALNUT + default y + +# OAK doesn't exist but wanted to keep this around for any future 403GCX boards +config 403GCX + bool + depends OAK + default y + +config 405EP + bool + depends on BUBINGA + default y + +config 405GP + bool + depends on CPCI405 || EP405 || WALNUT + default y + +config 405GPR + bool + depends on SYCAMORE + default y + +config VIRTEX_II_PRO + bool + depends on XILINX_ML300 + default y + +config STB03xxx + bool + depends on REDWOOD_5 || REDWOOD_6 + default y + +config EMBEDDEDBOOT + bool + depends on EP405 || XILINX_ML300 + default y + +config IBM_OPENBIOS + bool + depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT + default y + +config PPC4xx_DMA + bool "PPC4xx DMA controller support" + depends on 4xx + +config PPC4xx_EDMA + bool + depends on !STB03xxx && PPC4xx_DMA + default y + +config PPC_GEN550 + bool + depends on 4xx + default y + +choice + prompt "TTYS0 device and default console" + depends on 40x + default UART0_TTYS0 + +config UART0_TTYS0 + bool "UART0" + +config UART0_TTYS1 + bool "UART1" + +endchoice + +config SERIAL_SICC + bool "SICC Serial port support" + depends on STB03xxx + +config UART1_DFLT_CONSOLE + bool + depends on SERIAL_SICC && UART0_TTYS1 + default y + +config SERIAL_SICC_CONSOLE + bool + depends on SERIAL_SICC && UART0_TTYS1 + default y +endmenu + + +menu "IBM 40x options" + depends on 40x + +config SERIAL_SICC + bool "SICC Serial port" + depends on STB03xxx + +config UART1_DFLT_CONSOLE + bool + depends on SERIAL_SICC && UART0_TTYS1 + default y + +config SERIAL_SICC_CONSOLE + bool + depends on SERIAL_SICC && UART0_TTYS1 + default y + +endmenu diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig new file mode 100644 index 00000000000..c5bc2821d99 --- /dev/null +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -0,0 +1,86 @@ +config 85xx + bool + depends on E500 + default y + +config PPC_INDIRECT_PCI_BE + bool + depends on 85xx + default y + +menu "Freescale 85xx options" + depends on E500 + +choice + prompt "Machine Type" + depends on 85xx + default MPC8540_ADS + +config MPC8540_ADS + bool "Freescale MPC8540 ADS" + help + This option enables support for the MPC 8540 ADS evaluation board. + +config MPC8548_CDS + bool "Freescale MPC8548 CDS" + help + This option enablese support for the MPC8548 CDS evaluation board. + +config MPC8555_CDS + bool "Freescale MPC8555 CDS" + help + This option enablese support for the MPC8555 CDS evaluation board. + +config MPC8560_ADS + bool "Freescale MPC8560 ADS" + help + This option enables support for the MPC 8560 ADS evaluation board. + +config SBC8560 + bool "WindRiver PowerQUICC III SBC8560" + help + This option enables support for the WindRiver PowerQUICC III + SBC8560 board. + +config STX_GP3 + bool "Silicon Turnkey Express GP3" + help + This option enables support for the Silicon Turnkey Express GP3 + board. + +endchoice + +# It's often necessary to know the specific 85xx processor type. +# Fortunately, it is implied (so far) from the board type, so we +# don't need to ask more redundant questions. +config MPC8540 + bool + depends on MPC8540_ADS + default y + +config MPC8548 + bool + depends on MPC8548_CDS + default y + +config MPC8555 + bool + depends on MPC8555_CDS + default y + +config MPC8560 + bool + depends on SBC8560 || MPC8560_ADS || STX_GP3 + default y + +config 85xx_PCI2 + bool "Supprt for 2nd PCI host controller" + depends on MPC8555_CDS + default y + +config PPC_GEN550 + bool + depends on MPC8540 || SBC8560 || MPC8555 + default y + +endmenu diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig new file mode 100644 index 00000000000..c8c0ba3cf8e --- /dev/null +++ b/arch/powerpc/platforms/8xx/Kconfig @@ -0,0 +1,352 @@ +config FADS + bool + +choice + prompt "8xx Machine Type" + depends on 8xx + default RPXLITE + +config RPXLITE + bool "RPX-Lite" + ---help--- + Single-board computers based around the PowerPC MPC8xx chips and + intended for embedded applications. The following types are + supported: + + RPX-Lite: + Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823. + + RPX-Classic: + Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on + the MPC 860 + + BSE-IP: + Bright Star Engineering ip-Engine. + + TQM823L: + TQM850L: + TQM855L: + TQM860L: + MPC8xx based family of mini modules, half credit card size, + up to 64 MB of RAM, 8 MB Flash, (Fast) Ethernet, 2 x serial ports, + 2 x CAN bus interface, ... + Manufacturer: TQ Components, www.tq-group.de + Date of Release: October (?) 1999 + End of Life: not yet :-) + URL: + - module: + - starter kit: + - images: + + FPS850L: + FingerPrint Sensor System (based on TQM850L) + Manufacturer: IKENDI AG, + Date of Release: November 1999 + End of life: end 2000 ? + URL: see TQM850L + + IVMS8: + MPC860 based board used in the "Integrated Voice Mail System", + Small Version (8 voice channels) + Manufacturer: Speech Design, + Date of Release: December 2000 (?) + End of life: - + URL: + + IVML24: + MPC860 based board used in the "Integrated Voice Mail System", + Large Version (24 voice channels) + Manufacturer: Speech Design, + Date of Release: March 2001 (?) + End of life: - + URL: + + HERMES: + Hermes-Pro ISDN/LAN router with integrated 8 x hub + Manufacturer: Multidata Gesellschaft fur Datentechnik und Informatik + + Date of Release: 2000 (?) + End of life: - + URL: + + IP860: + VMEBus IP (Industry Pack) carrier board with MPC860 + Manufacturer: MicroSys GmbH, + Date of Release: ? + End of life: - + URL: + + PCU_E: + PCU = Peripheral Controller Unit, Extended + Manufacturer: Siemens AG, ICN (Information and Communication Networks) + + Date of Release: April 2001 + End of life: August 2001 + URL: n. a. + +config RPXCLASSIC + bool "RPX-Classic" + help + The RPX-Classic is a single-board computer based on the Motorola + MPC860. It features 16MB of DRAM and a variable amount of flash, + I2C EEPROM, thermal monitoring, a PCMCIA slot, a DIP switch and two + LEDs. Variants with Ethernet ports exist. Say Y here to support it + directly. + +config BSEIP + bool "BSE-IP" + help + Say Y here to support the Bright Star Engineering ipEngine SBC. + This is a credit-card-sized device featuring a MPC823 processor, + 26MB DRAM, 4MB flash, Ethernet, a 16K-gate FPGA, USB, an LCD/video + controller, and two RS232 ports. + +config MPC8XXFADS + bool "FADS" + select FADS + +config MPC86XADS + bool "MPC86XADS" + help + MPC86x Application Development System by Freescale Semiconductor. + The MPC86xADS is meant to serve as a platform for s/w and h/w + development around the MPC86X processor families. + select FADS + +config MPC885ADS + bool "MPC885ADS" + help + Freescale Semiconductor MPC885 Application Development System (ADS). + Also known as DUET. + The MPC885ADS is meant to serve as a platform for s/w and h/w + development around the MPC885 processor family. + +config TQM823L + bool "TQM823L" + help + Say Y here to support the TQM823L, one of an MPC8xx-based family of + mini SBCs (half credit-card size) from TQ Components first released + in late 1999. Technical references are at + , and + , and an image at + . + +config TQM850L + bool "TQM850L" + help + Say Y here to support the TQM850L, one of an MPC8xx-based family of + mini SBCs (half credit-card size) from TQ Components first released + in late 1999. Technical references are at + , and + , and an image at + . + +config TQM855L + bool "TQM855L" + help + Say Y here to support the TQM855L, one of an MPC8xx-based family of + mini SBCs (half credit-card size) from TQ Components first released + in late 1999. Technical references are at + , and + , and an image at + . + +config TQM860L + bool "TQM860L" + help + Say Y here to support the TQM860L, one of an MPC8xx-based family of + mini SBCs (half credit-card size) from TQ Components first released + in late 1999. Technical references are at + , and + , and an image at + . + +config FPS850L + bool "FPS850L" + +config IVMS8 + bool "IVMS8" + help + Say Y here to support the Integrated Voice-Mail Small 8-channel SBC + from Speech Design, released March 2001. The manufacturer's website + is at . + +config IVML24 + bool "IVML24" + help + Say Y here to support the Integrated Voice-Mail Large 24-channel SBC + from Speech Design, released March 2001. The manufacturer's website + is at . + +config HERMES_PRO + bool "HERMES" + +config IP860 + bool "IP860" + +config LWMON + bool "LWMON" + +config PCU_E + bool "PCU_E" + +config CCM + bool "CCM" + +config LANTEC + bool "LANTEC" + +config MBX + bool "MBX" + help + MBX is a line of Motorola single-board computer based around the + MPC821 and MPC860 processors, and intended for embedded-controller + applications. Say Y here to support these boards directly. + +config WINCEPT + bool "WinCept" + help + The Wincept 100/110 is a Motorola single-board computer based on the + MPC821 PowerPC, introduced in 1998 and designed to be used in + thin-client machines. Say Y to support it directly. + +endchoice + +# +# MPC8xx Communication options +# + +menu "MPC8xx CPM Options" + depends on 8xx + +config SCC_ENET + bool "CPM SCC Ethernet" + depends on NET_ETHERNET + help + Enable Ethernet support via the Motorola MPC8xx serial + communications controller. + +choice + prompt "SCC used for Ethernet" + depends on SCC_ENET + default SCC1_ENET + +config SCC1_ENET + bool "SCC1" + help + Use MPC8xx serial communications controller 1 to drive Ethernet + (default). + +config SCC2_ENET + bool "SCC2" + help + Use MPC8xx serial communications controller 2 to drive Ethernet. + +config SCC3_ENET + bool "SCC3" + help + Use MPC8xx serial communications controller 3 to drive Ethernet. + +endchoice + +config FEC_ENET + bool "860T FEC Ethernet" + depends on NET_ETHERNET + help + Enable Ethernet support via the Fast Ethernet Controller (FCC) on + the Motorola MPC8260. + +config USE_MDIO + bool "Use MDIO for PHY configuration" + depends on FEC_ENET + help + On some boards the hardware configuration of the ethernet PHY can be + used without any software interaction over the MDIO interface, so + all MII code can be omitted. Say N here if unsure or if you don't + need link status reports. + +config FEC_AM79C874 + bool "Support AMD79C874 PHY" + depends on USE_MDIO + +config FEC_LXT970 + bool "Support LXT970 PHY" + depends on USE_MDIO + +config FEC_LXT971 + bool "Support LXT971 PHY" + depends on USE_MDIO + +config FEC_QS6612 + bool "Support QS6612 PHY" + depends on USE_MDIO + +config ENET_BIG_BUFFERS + bool "Use Big CPM Ethernet Buffers" + depends on SCC_ENET || FEC_ENET + help + Allocate large buffers for MPC8xx Ethernet. Increases throughput + and decreases the likelihood of dropped packets, but costs memory. + +config HTDMSOUND + bool "Embedded Planet HIOX Audio" + depends on SOUND=y + +# This doesn't really belong here, but it is convenient to ask +# 8xx specific questions. +comment "Generic MPC8xx Options" + +config 8xx_COPYBACK + bool "Copy-Back Data Cache (else Writethrough)" + help + Saying Y here will cause the cache on an MPC8xx processor to be used + in Copy-Back mode. If you say N here, it is used in Writethrough + mode. + + If in doubt, say Y here. + +config 8xx_CPU6 + bool "CPU6 Silicon Errata (860 Pre Rev. C)" + help + MPC860 CPUs, prior to Rev C have some bugs in the silicon, which + require workarounds for Linux (and most other OSes to work). If you + get a BUG() very early in boot, this might fix the problem. For + more details read the document entitled "MPC860 Family Device Errata + Reference" on Motorola's website. This option also incurs a + performance hit. + + If in doubt, say N here. + +choice + prompt "Microcode patch selection" + default NO_UCODE_PATCH + help + Help not implemented yet, coming soon. + +config NO_UCODE_PATCH + bool "None" + +config USB_SOF_UCODE_PATCH + bool "USB SOF patch" + help + Help not implemented yet, coming soon. + +config I2C_SPI_UCODE_PATCH + bool "I2C/SPI relocation patch" + help + Help not implemented yet, coming soon. + +config I2C_SPI_SMC1_UCODE_PATCH + bool "I2C/SPI/SMC1 relocation patch" + help + Help not implemented yet, coming soon. + +endchoice + +config UCODE_PATCH + bool + default y + depends on !NO_UCODE_PATCH + +endmenu + diff --git a/arch/powerpc/platforms/apus/Kconfig b/arch/powerpc/platforms/apus/Kconfig new file mode 100644 index 00000000000..6bde3bffed8 --- /dev/null +++ b/arch/powerpc/platforms/apus/Kconfig @@ -0,0 +1,130 @@ + +config AMIGA + bool + depends on APUS + default y + help + This option enables support for the Amiga series of computers. + +config ZORRO + bool + depends on APUS + default y + help + This enables support for the Zorro bus in the Amiga. If you have + expansion cards in your Amiga that conform to the Amiga + AutoConfig(tm) specification, say Y, otherwise N. Note that even + expansion cards that do not fit in the Zorro slots but fit in e.g. + the CPU slot may fall in this category, so you have to say Y to let + Linux use these. + +config ABSTRACT_CONSOLE + bool + depends on APUS + default y + +config APUS_FAST_EXCEPT + bool + depends on APUS + default y + +config AMIGA_PCMCIA + bool "Amiga 1200/600 PCMCIA support" + depends on APUS && EXPERIMENTAL + help + Include support in the kernel for pcmcia on Amiga 1200 and Amiga + 600. If you intend to use pcmcia cards say Y; otherwise say N. + +config AMIGA_BUILTIN_SERIAL + tristate "Amiga builtin serial support" + depends on APUS + help + If you want to use your Amiga's built-in serial port in Linux, + answer Y. + + To compile this driver as a module, choose M here. + +config GVPIOEXT + tristate "GVP IO-Extender support" + depends on APUS + help + If you want to use a GVP IO-Extender serial card in Linux, say Y. + Otherwise, say N. + +config GVPIOEXT_LP + tristate "GVP IO-Extender parallel printer support" + depends on GVPIOEXT + help + Say Y to enable driving a printer from the parallel port on your + GVP IO-Extender card, N otherwise. + +config GVPIOEXT_PLIP + tristate "GVP IO-Extender PLIP support" + depends on GVPIOEXT + help + Say Y to enable doing IP over the parallel port on your GVP + IO-Extender card, N otherwise. + +config MULTIFACE_III_TTY + tristate "Multiface Card III serial support" + depends on APUS + help + If you want to use a Multiface III card's serial port in Linux, + answer Y. + + To compile this driver as a module, choose M here. + +config A2232 + tristate "Commodore A2232 serial support (EXPERIMENTAL)" + depends on EXPERIMENTAL && APUS + ---help--- + This option supports the 2232 7-port serial card shipped with the + Amiga 2000 and other Zorro-bus machines, dating from 1989. At + a max of 19,200 bps, the ports are served by a 6551 ACIA UART chip + each, plus a 8520 CIA, and a master 6502 CPU and buffer as well. The + ports were connected with 8 pin DIN connectors on the card bracket, + for which 8 pin to DB25 adapters were supplied. The card also had + jumpers internally to toggle various pinning configurations. + + This driver can be built as a module; but then "generic_serial" + will also be built as a module. This has to be loaded before + "ser_a2232". If you want to do this, answer M here. + +config WHIPPET_SERIAL + tristate "Hisoft Whippet PCMCIA serial support" + depends on AMIGA_PCMCIA + help + HiSoft has a web page at , but there + is no listing for the Whippet in their Amiga section. + +config APNE + tristate "PCMCIA NE2000 support" + depends on AMIGA_PCMCIA + help + If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise, + say N. + + To compile this driver as a module, choose M here: the + module will be called apne. + +config SERIAL_CONSOLE + bool "Support for serial port console" + depends on APUS && (AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y) + +config HEARTBEAT + bool "Use power LED as a heartbeat" + depends on APUS + help + Use the power-on LED on your machine as a load meter. The exact + behavior is platform-dependent, but normally the flash frequency is + a hyperbolic function of the 5-minute load average. + +config PROC_HARDWARE + bool "/proc/hardware support" + depends on APUS + +source "drivers/zorro/Kconfig" + +config PCI_PERMEDIA + bool "PCI for Permedia2" + depends on !4xx && !8xx && APUS diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig new file mode 100644 index 00000000000..4f355143059 --- /dev/null +++ b/arch/powerpc/platforms/embedded6xx/Kconfig @@ -0,0 +1,313 @@ +choice + prompt "Machine Type" + depends on EMBEDDED6xx + +config APUS + bool "Amiga-APUS" + depends on BROKEN + help + Select APUS if configuring for a PowerUP Amiga. + More information is available at: + . + +config KATANA + bool "Artesyn-Katana" + help + Select KATANA if configuring an Artesyn KATANA 750i or 3750 + cPCI board. + +config WILLOW + bool "Cogent-Willow" + +config CPCI690 + bool "Force-CPCI690" + help + Select CPCI690 if configuring a Force CPCI690 cPCI board. + +config POWERPMC250 + bool "Force-PowerPMC250" + +config CHESTNUT + bool "IBM 750FX Eval board or 750GX Eval board" + help + Select CHESTNUT if configuring an IBM 750FX Eval Board or a + IBM 750GX Eval board. + +config SPRUCE + bool "IBM-Spruce" + +config HDPU + bool "Sky-HDPU" + help + Select HDPU if configuring a Sky Computers Compute Blade. + +config HDPU_FEATURES + depends HDPU + tristate "HDPU-Features" + help + Select to enable HDPU enhanced features. + +config EV64260 + bool "Marvell-EV64260BP" + help + Select EV64260 if configuring a Marvell (formerly Galileo) + EV64260BP Evaluation platform. + +config LOPEC + bool "Motorola-LoPEC" + +config MVME5100 + bool "Motorola-MVME5100" + +config PPLUS + bool "Motorola-PowerPlus" + +config PRPMC750 + bool "Motorola-PrPMC750" + +config PRPMC800 + bool "Motorola-PrPMC800" + +config SANDPOINT + bool "Motorola-Sandpoint" + help + Select SANDPOINT if configuring for a Motorola Sandpoint X3 + (any flavor). + +config RADSTONE_PPC7D + bool "Radstone Technology PPC7D board" + +config PAL4 + bool "SBS-Palomar4" + +config GEMINI + bool "Synergy-Gemini" + depends on BROKEN + help + Select Gemini if configuring for a Synergy Microsystems' Gemini + series Single Board Computer. More information is available at: + . + +config EST8260 + bool "EST8260" + ---help--- + The EST8260 is a single-board computer manufactured by Wind River + Systems, Inc. (formerly Embedded Support Tools Corp.) and based on + the MPC8260. Wind River Systems has a website at + , but the EST8260 cannot be found on it + and has probably been discontinued or rebadged. + +config SBC82xx + bool "SBC82xx" + ---help--- + SBC PowerQUICC II, single-board computer with MPC82xx CPU + Manufacturer: Wind River Systems, Inc. + Date of Release: May 2003 + End of Life: - + URL: + +config SBS8260 + bool "SBS8260" + +config RPX8260 + bool "RPXSUPER" + +config TQM8260 + bool "TQM8260" + ---help--- + MPC8260 based module, little larger than credit card, + up to 128 MB global + 64 MB local RAM, 32 MB Flash, + 32 kB EEPROM, 256 kB L@ Cache, 10baseT + 100baseT Ethernet, + 2 x serial ports, ... + Manufacturer: TQ Components, www.tq-group.de + Date of Release: June 2001 + End of Life: not yet :-) + URL: + +config ADS8272 + bool "ADS8272" + +config PQ2FADS + bool "Freescale-PQ2FADS" + help + Select PQ2FADS if you wish to configure for a Freescale + PQ2FADS board (-VR or -ZU). + +config LITE5200 + bool "Freescale LITE5200 / (IceCube)" + select PPC_MPC52xx + help + Support for the LITE5200 dev board for the MPC5200 from Freescale. + This is for the LITE5200 version 2.0 board. Don't know if it changes + much but it's only been tested on this board version. I think this + board is also known as IceCube. + +config MPC834x_SYS + bool "Freescale MPC834x SYS" + help + This option enables support for the MPC 834x SYS evaluation board. + + Be aware that PCI buses can only function when SYS board is plugged + into the PIB (Platform IO Board) board from Freescale which provide + 3 PCI slots. The PIBs PCI initialization is the bootloader's + responsiblilty. + +config EV64360 + bool "Marvell-EV64360BP" + help + Select EV64360 if configuring a Marvell EV64360BP Evaluation + platform. +endchoice + +config PQ2ADS + bool + depends on ADS8272 + default y + +config TQM8xxL + bool + depends on 8xx && (TQM823L || TQM850L || FPS850L || TQM855L || TQM860L) + default y + +config PPC_MPC52xx + bool + +config 8260 + bool "CPM2 Support" if WILLOW + depends on 6xx + default y if TQM8260 || RPX8260 || EST8260 || SBS8260 || SBC82xx || PQ2FADS + help + The MPC8260 is a typical embedded CPU made by Motorola. Selecting + this option means that you wish to build a kernel for a machine with + an 8260 class CPU. + +config 8272 + bool + depends on 6xx + default y if ADS8272 + select 8260 + help + The MPC8272 CPM has a different internal dpram setup than other CPM2 + devices + +config 83xx + bool + default y if MPC834x_SYS + +config MPC834x + bool + default y if MPC834x_SYS + +config CPM2 + bool + depends on 8260 || MPC8560 || MPC8555 + default y + help + The CPM2 (Communications Processor Module) is a coprocessor on + embedded CPUs made by Motorola. Selecting this option means that + you wish to build a kernel for a machine with a CPM2 coprocessor + on it (826x, 827x, 8560). + +config PPC_GEN550 + bool + depends on SANDPOINT || SPRUCE || PPLUS || \ + PRPMC750 || PRPMC800 || LOPEC || \ + (EV64260 && !SERIAL_MPSC) || CHESTNUT || RADSTONE_PPC7D || \ + 83xx + default y + +config FORCE + bool + depends on 6xx && POWERPMC250 + default y + +config GT64260 + bool + depends on EV64260 || CPCI690 + default y + +config MV64360 # Really MV64360 & MV64460 + bool + depends on CHESTNUT || KATANA || RADSTONE_PPC7D || HDPU || EV64360 + default y + +config MV64X60 + bool + depends on (GT64260 || MV64360) + default y + +menu "Set bridge options" + depends on MV64X60 + +config NOT_COHERENT_CACHE + bool "Turn off Cache Coherency" + default n + help + Some 64x60 bridges lock up when trying to enforce cache coherency. + When this option is selected, cache coherency will be turned off. + Note that this can cause other problems (e.g., stale data being + speculatively loaded via a cached mapping). Use at your own risk. + +config MV64X60_BASE + hex "Set bridge base used by firmware" + default "0xf1000000" + help + A firmware can leave the base address of the bridge's registers at + a non-standard location. If so, set this value to reflect the + address of that non-standard location. + +config MV64X60_NEW_BASE + hex "Set bridge base used by kernel" + default "0xf1000000" + help + If the current base address of the bridge's registers is not where + you want it, set this value to the address that you want it moved to. + +endmenu + +config NONMONARCH_SUPPORT + bool "Enable Non-Monarch Support" + depends on PRPMC800 + +config HARRIER + bool + depends on PRPMC800 + default y + +config EPIC_SERIAL_MODE + bool + depends on 6xx && (LOPEC || SANDPOINT) + default y + +config MPC10X_BRIDGE + bool + depends on POWERPMC250 || LOPEC || SANDPOINT + default y + +config MPC10X_OPENPIC + bool + depends on POWERPMC250 || LOPEC || SANDPOINT + default y + +config MPC10X_STORE_GATHERING + bool "Enable MPC10x store gathering" + depends on MPC10X_BRIDGE + +config SANDPOINT_ENABLE_UART1 + bool "Enable DUART mode on Sandpoint" + depends on SANDPOINT + help + If this option is enabled then the MPC824x processor will run + in DUART mode instead of UART mode. + +config HARRIER_STORE_GATHERING + bool "Enable Harrier store gathering" + depends on HARRIER + +config MVME5100_IPMC761_PRESENT + bool "MVME5100 configured with an IPMC761" + depends on MVME5100 + +config SPRUCE_BAUD_33M + bool "Spruce baud clock support" + depends on SPRUCE diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig new file mode 100644 index 00000000000..3d957a30c8c --- /dev/null +++ b/arch/powerpc/platforms/iseries/Kconfig @@ -0,0 +1,31 @@ + +menu "iSeries device drivers" + depends on PPC_ISERIES + +config VIOCONS + tristate "iSeries Virtual Console Support" + +config VIODASD + tristate "iSeries Virtual I/O disk support" + help + If you are running on an iSeries system and you want to use + virtual disks created and managed by OS/400, say Y. + +config VIOCD + tristate "iSeries Virtual I/O CD support" + help + If you are running Linux on an IBM iSeries system and you want to + read a CD drive owned by OS/400, say Y here. + +config VIOTAPE + tristate "iSeries Virtual Tape Support" + help + If you are running Linux on an iSeries system and you want Linux + to read and/or write a tape drive owned by OS/400, say Y here. + +endmenu + +config VIOPATH + bool + depends on VIOCONS || VIODASD || VIOCD || VIOTAPE || VETH + default y diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile new file mode 100644 index 00000000000..37b7341396e --- /dev/null +++ b/arch/powerpc/platforms/powermac/Makefile @@ -0,0 +1,9 @@ +obj-$(CONFIG_PPC_PMAC) += pmac_pic.o pmac_setup.o pmac_time.o \ + pmac_feature.o pmac_pci.o pmac_sleep.o \ + pmac_low_i2c.o pmac_cache.o +obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o +obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o +ifeq ($(CONFIG_PPC_PMAC),y) +obj-$(CONFIG_NVRAM) += pmac_nvram.o +obj-$(CONFIG_SMP) += pmac_smp.o +endif diff --git a/arch/powerpc/platforms/powermac/pmac.h b/arch/powerpc/platforms/powermac/pmac.h new file mode 100644 index 00000000000..40e1c5030f7 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac.h @@ -0,0 +1,31 @@ +#ifndef __PMAC_H__ +#define __PMAC_H__ + +#include +#include + +/* + * Declaration for the various functions exported by the + * pmac_* files. Mostly for use by pmac_setup + */ + +extern void pmac_get_boot_time(struct rtc_time *tm); +extern void pmac_get_rtc_time(struct rtc_time *tm); +extern int pmac_set_rtc_time(struct rtc_time *tm); +extern void pmac_read_rtc_time(void); +extern void pmac_calibrate_decr(void); + +extern void pmac_pcibios_fixup(void); +extern void pmac_pci_init(void); +extern void pmac_setup_pci_dma(void); +extern void pmac_check_ht_link(void); + +extern void pmac_setup_smp(void); + +extern unsigned long pmac_ide_get_base(int index); +extern void pmac_ide_init_hwif_ports(hw_regs_t *hw, + unsigned long data_port, unsigned long ctrl_port, int *irq); + +extern void pmac_nvram_init(void); + +#endif /* __PMAC_H__ */ diff --git a/arch/powerpc/platforms/powermac/pmac_backlight.c b/arch/powerpc/platforms/powermac/pmac_backlight.c new file mode 100644 index 00000000000..8be2f7d071f --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_backlight.c @@ -0,0 +1,202 @@ +/* + * Miscellaneous procedures for dealing with the PowerMac hardware. + * Contains support for the backlight. + * + * Copyright (C) 2000 Benjamin Herrenschmidt + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +static struct backlight_controller *backlighter; +static void* backlighter_data; +static int backlight_autosave; +static int backlight_level = BACKLIGHT_MAX; +static int backlight_enabled = 1; +static int backlight_req_level = -1; +static int backlight_req_enable = -1; + +static void backlight_callback(void *); +static DECLARE_WORK(backlight_work, backlight_callback, NULL); + +void register_backlight_controller(struct backlight_controller *ctrler, + void *data, char *type) +{ + struct device_node* bk_node; + char *prop; + int valid = 0; + + /* There's already a matching controller, bail out */ + if (backlighter != NULL) + return; + + bk_node = find_devices("backlight"); + +#ifdef CONFIG_ADB_PMU + /* Special case for the old PowerBook since I can't test on it */ + backlight_autosave = machine_is_compatible("AAPL,3400/2400") + || machine_is_compatible("AAPL,3500"); + if ((backlight_autosave + || machine_is_compatible("AAPL,PowerBook1998") + || machine_is_compatible("PowerBook1,1")) + && !strcmp(type, "pmu")) + valid = 1; +#endif + if (bk_node) { + prop = get_property(bk_node, "backlight-control", NULL); + if (prop && !strncmp(prop, type, strlen(type))) + valid = 1; + } + if (!valid) + return; + backlighter = ctrler; + backlighter_data = data; + + if (bk_node && !backlight_autosave) + prop = get_property(bk_node, "bklt", NULL); + else + prop = NULL; + if (prop) { + backlight_level = ((*prop)+1) >> 1; + if (backlight_level > BACKLIGHT_MAX) + backlight_level = BACKLIGHT_MAX; + } + +#ifdef CONFIG_ADB_PMU + if (backlight_autosave) { + struct adb_request req; + pmu_request(&req, NULL, 2, 0xd9, 0); + while (!req.complete) + pmu_poll(); + backlight_level = req.reply[0] >> 4; + } +#endif + acquire_console_sem(); + if (!backlighter->set_enable(1, backlight_level, data)) + backlight_enabled = 1; + release_console_sem(); + + printk(KERN_INFO "Registered \"%s\" backlight controller," + "level: %d/15\n", type, backlight_level); +} +EXPORT_SYMBOL(register_backlight_controller); + +void unregister_backlight_controller(struct backlight_controller + *ctrler, void *data) +{ + /* We keep the current backlight level (for now) */ + if (ctrler == backlighter && data == backlighter_data) + backlighter = NULL; +} +EXPORT_SYMBOL(unregister_backlight_controller); + +static int __set_backlight_enable(int enable) +{ + int rc; + + if (!backlighter) + return -ENODEV; + acquire_console_sem(); + rc = backlighter->set_enable(enable, backlight_level, + backlighter_data); + if (!rc) + backlight_enabled = enable; + release_console_sem(); + return rc; +} +int set_backlight_enable(int enable) +{ + if (!backlighter) + return -ENODEV; + backlight_req_enable = enable; + schedule_work(&backlight_work); + return 0; +} + +EXPORT_SYMBOL(set_backlight_enable); + +int get_backlight_enable(void) +{ + if (!backlighter) + return -ENODEV; + return backlight_enabled; +} +EXPORT_SYMBOL(get_backlight_enable); + +static int __set_backlight_level(int level) +{ + int rc = 0; + + if (!backlighter) + return -ENODEV; + if (level < BACKLIGHT_MIN) + level = BACKLIGHT_OFF; + if (level > BACKLIGHT_MAX) + level = BACKLIGHT_MAX; + acquire_console_sem(); + if (backlight_enabled) + rc = backlighter->set_level(level, backlighter_data); + if (!rc) + backlight_level = level; + release_console_sem(); + if (!rc && !backlight_autosave) { + level <<=1; + if (level & 0x10) + level |= 0x01; + // -- todo: save to property "bklt" + } + return rc; +} +int set_backlight_level(int level) +{ + if (!backlighter) + return -ENODEV; + backlight_req_level = level; + schedule_work(&backlight_work); + return 0; +} + +EXPORT_SYMBOL(set_backlight_level); + +int get_backlight_level(void) +{ + if (!backlighter) + return -ENODEV; + return backlight_level; +} +EXPORT_SYMBOL(get_backlight_level); + +static void backlight_callback(void *dummy) +{ + int level, enable; + + do { + level = backlight_req_level; + enable = backlight_req_enable; + mb(); + + if (level >= 0) + __set_backlight_level(level); + if (enable >= 0) + __set_backlight_enable(enable); + } while(cmpxchg(&backlight_req_level, level, -1) != level || + cmpxchg(&backlight_req_enable, enable, -1) != enable); +} diff --git a/arch/powerpc/platforms/powermac/pmac_cache.S b/arch/powerpc/platforms/powermac/pmac_cache.S new file mode 100644 index 00000000000..fb977de6b70 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_cache.S @@ -0,0 +1,359 @@ +/* + * This file contains low-level cache management functions + * used for sleep and CPU speed changes on Apple machines. + * (In fact the only thing that is Apple-specific is that we assume + * that we can read from ROM at physical address 0xfff00000.) + * + * Copyright (C) 2004 Paul Mackerras (paulus@samba.org) and + * Benjamin Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include + +/* + * Flush and disable all data caches (dL1, L2, L3). This is used + * when going to sleep, when doing a PMU based cpufreq transition, + * or when "offlining" a CPU on SMP machines. This code is over + * paranoid, but I've had enough issues with various CPU revs and + * bugs that I decided it was worth beeing over cautious + */ + +_GLOBAL(flush_disable_caches) +#ifndef CONFIG_6xx + blr +#else +BEGIN_FTR_SECTION + b flush_disable_745x +END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) +BEGIN_FTR_SECTION + b flush_disable_75x +END_FTR_SECTION_IFSET(CPU_FTR_L2CR) + b __flush_disable_L1 + +/* This is the code for G3 and 74[01]0 */ +flush_disable_75x: + mflr r10 + + /* Turn off EE and DR in MSR */ + mfmsr r11 + rlwinm r0,r11,0,~MSR_EE + rlwinm r0,r0,0,~MSR_DR + sync + mtmsr r0 + isync + + /* Stop DST streams */ +BEGIN_FTR_SECTION + DSSALL + sync +END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) + + /* Stop DPM */ + mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */ + rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */ + sync + mtspr SPRN_HID0,r4 /* Disable DPM */ + sync + + /* Disp-flush L1. We have a weird problem here that I never + * totally figured out. On 750FX, using the ROM for the flush + * results in a non-working flush. We use that workaround for + * now until I finally understand what's going on. --BenH + */ + + /* ROM base by default */ + lis r4,0xfff0 + mfpvr r3 + srwi r3,r3,16 + cmplwi cr0,r3,0x7000 + bne+ 1f + /* RAM base on 750FX */ + li r4,0 +1: li r4,0x4000 + mtctr r4 +1: lwz r0,0(r4) + addi r4,r4,32 + bdnz 1b + sync + isync + + /* Disable / invalidate / enable L1 data */ + mfspr r3,SPRN_HID0 + rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE) + mtspr SPRN_HID0,r3 + sync + isync + ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI) + sync + isync + mtspr SPRN_HID0,r3 + xori r3,r3,(HID0_DCI|HID0_ICFI) + mtspr SPRN_HID0,r3 + sync + + /* Get the current enable bit of the L2CR into r4 */ + mfspr r5,SPRN_L2CR + /* Set to data-only (pre-745x bit) */ + oris r3,r5,L2CR_L2DO@h + b 2f + /* When disabling L2, code must be in L1 */ + .balign 32 +1: mtspr SPRN_L2CR,r3 +3: sync + isync + b 1f +2: b 3f +3: sync + isync + b 1b +1: /* disp-flush L2. The interesting thing here is that the L2 can be + * up to 2Mb ... so using the ROM, we'll end up wrapping back to memory + * but that is probbaly fine. We disp-flush over 4Mb to be safe + */ + lis r4,2 + mtctr r4 + lis r4,0xfff0 +1: lwz r0,0(r4) + addi r4,r4,32 + bdnz 1b + sync + isync + lis r4,2 + mtctr r4 + lis r4,0xfff0 +1: dcbf 0,r4 + addi r4,r4,32 + bdnz 1b + sync + isync + + /* now disable L2 */ + rlwinm r5,r5,0,~L2CR_L2E + b 2f + /* When disabling L2, code must be in L1 */ + .balign 32 +1: mtspr SPRN_L2CR,r5 +3: sync + isync + b 1f +2: b 3f +3: sync + isync + b 1b +1: sync + isync + /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */ + oris r4,r5,L2CR_L2I@h + mtspr SPRN_L2CR,r4 + sync + isync + + /* Wait for the invalidation to complete */ +1: mfspr r3,SPRN_L2CR + rlwinm. r0,r3,0,31,31 + bne 1b + + /* Clear L2I */ + xoris r4,r4,L2CR_L2I@h + sync + mtspr SPRN_L2CR,r4 + sync + + /* now disable the L1 data cache */ + mfspr r0,SPRN_HID0 + rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE) + mtspr SPRN_HID0,r0 + sync + isync + + /* Restore HID0[DPM] to whatever it was before */ + sync + mfspr r0,SPRN_HID0 + rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */ + mtspr SPRN_HID0,r0 + sync + + /* restore DR and EE */ + sync + mtmsr r11 + isync + + mtlr r10 + blr + +/* This code is for 745x processors */ +flush_disable_745x: + /* Turn off EE and DR in MSR */ + mfmsr r11 + rlwinm r0,r11,0,~MSR_EE + rlwinm r0,r0,0,~MSR_DR + sync + mtmsr r0 + isync + + /* Stop prefetch streams */ + DSSALL + sync + + /* Disable L2 prefetching */ + mfspr r0,SPRN_MSSCR0 + rlwinm r0,r0,0,0,29 + mtspr SPRN_MSSCR0,r0 + sync + isync + lis r4,0 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + dcbf 0,r4 + + /* Due to a bug with the HW flush on some CPU revs, we occasionally + * experience data corruption. I'm adding a displacement flush along + * with a dcbf loop over a few Mb to "help". The problem isn't totally + * fixed by this in theory, but at least, in practice, I couldn't reproduce + * it even with a big hammer... + */ + + lis r4,0x0002 + mtctr r4 + li r4,0 +1: + lwz r0,0(r4) + addi r4,r4,32 /* Go to start of next cache line */ + bdnz 1b + isync + + /* Now, flush the first 4MB of memory */ + lis r4,0x0002 + mtctr r4 + li r4,0 + sync +1: + dcbf 0,r4 + addi r4,r4,32 /* Go to start of next cache line */ + bdnz 1b + + /* Flush and disable the L1 data cache */ + mfspr r6,SPRN_LDSTCR + lis r3,0xfff0 /* read from ROM for displacement flush */ + li r4,0xfe /* start with only way 0 unlocked */ + li r5,128 /* 128 lines in each way */ +1: mtctr r5 + rlwimi r6,r4,0,24,31 + mtspr SPRN_LDSTCR,r6 + sync + isync +2: lwz r0,0(r3) /* touch each cache line */ + addi r3,r3,32 + bdnz 2b + rlwinm r4,r4,1,24,30 /* move on to the next way */ + ori r4,r4,1 + cmpwi r4,0xff /* all done? */ + bne 1b + /* now unlock the L1 data cache */ + li r4,0 + rlwimi r6,r4,0,24,31 + sync + mtspr SPRN_LDSTCR,r6 + sync + isync + + /* Flush the L2 cache using the hardware assist */ + mfspr r3,SPRN_L2CR + cmpwi r3,0 /* check if it is enabled first */ + bge 4f + oris r0,r3,(L2CR_L2IO_745x|L2CR_L2DO_745x)@h + b 2f + /* When disabling/locking L2, code must be in L1 */ + .balign 32 +1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */ +3: sync + isync + b 1f +2: b 3f +3: sync + isync + b 1b +1: sync + isync + ori r0,r3,L2CR_L2HWF_745x + sync + mtspr SPRN_L2CR,r0 /* set the hardware flush bit */ +3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */ + andi. r0,r0,L2CR_L2HWF_745x + bne 3b + sync + rlwinm r3,r3,0,~L2CR_L2E + b 2f + /* When disabling L2, code must be in L1 */ + .balign 32 +1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */ +3: sync + isync + b 1f +2: b 3f +3: sync + isync + b 1b +1: sync + isync + oris r4,r3,L2CR_L2I@h + mtspr SPRN_L2CR,r4 + sync + isync +1: mfspr r4,SPRN_L2CR + andis. r0,r4,L2CR_L2I@h + bne 1b + sync + +BEGIN_FTR_SECTION + /* Flush the L3 cache using the hardware assist */ +4: mfspr r3,SPRN_L3CR + cmpwi r3,0 /* check if it is enabled */ + bge 6f + oris r0,r3,L3CR_L3IO@h + ori r0,r0,L3CR_L3DO + sync + mtspr SPRN_L3CR,r0 /* lock the L3 cache */ + sync + isync + ori r0,r0,L3CR_L3HWF + sync + mtspr SPRN_L3CR,r0 /* set the hardware flush bit */ +5: mfspr r0,SPRN_L3CR /* wait for it to go to zero */ + andi. r0,r0,L3CR_L3HWF + bne 5b + rlwinm r3,r3,0,~L3CR_L3E + sync + mtspr SPRN_L3CR,r3 /* disable the L3 cache */ + sync + ori r4,r3,L3CR_L3I + mtspr SPRN_L3CR,r4 +1: mfspr r4,SPRN_L3CR + andi. r0,r4,L3CR_L3I + bne 1b + sync +END_FTR_SECTION_IFSET(CPU_FTR_L3CR) + +6: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */ + rlwinm r0,r0,0,~HID0_DCE + mtspr SPRN_HID0,r0 + sync + isync + mtmsr r11 /* restore DR and EE */ + isync + blr +#endif /* CONFIG_6xx */ diff --git a/arch/powerpc/platforms/powermac/pmac_cpufreq.c b/arch/powerpc/platforms/powermac/pmac_cpufreq.c new file mode 100644 index 00000000000..6d32d99402b --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_cpufreq.c @@ -0,0 +1,728 @@ +/* + * arch/ppc/platforms/pmac_cpufreq.c + * + * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt + * Copyright (C) 2004 John Steele Scott + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * TODO: Need a big cleanup here. Basically, we need to have different + * cpufreq_driver structures for the different type of HW instead of the + * current mess. We also need to better deal with the detection of the + * type of machine. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* WARNING !!! This will cause calibrate_delay() to be called, + * but this is an __init function ! So you MUST go edit + * init/main.c to make it non-init before enabling DEBUG_FREQ + */ +#undef DEBUG_FREQ + +/* + * There is a problem with the core cpufreq code on SMP kernels, + * it won't recalculate the Bogomips properly + */ +#ifdef CONFIG_SMP +#warning "WARNING, CPUFREQ not recommended on SMP kernels" +#endif + +extern void low_choose_7447a_dfs(int dfs); +extern void low_choose_750fx_pll(int pll); +extern void low_sleep_handler(void); + +/* + * Currently, PowerMac cpufreq supports only high & low frequencies + * that are set by the firmware + */ +static unsigned int low_freq; +static unsigned int hi_freq; +static unsigned int cur_freq; +static unsigned int sleep_freq; + +/* + * Different models uses different mecanisms to switch the frequency + */ +static int (*set_speed_proc)(int low_speed); +static unsigned int (*get_speed_proc)(void); + +/* + * Some definitions used by the various speedprocs + */ +static u32 voltage_gpio; +static u32 frequency_gpio; +static u32 slew_done_gpio; +static int no_schedule; +static int has_cpu_l2lve; +static int is_pmu_based; + +/* There are only two frequency states for each processor. Values + * are in kHz for the time being. + */ +#define CPUFREQ_HIGH 0 +#define CPUFREQ_LOW 1 + +static struct cpufreq_frequency_table pmac_cpu_freqs[] = { + {CPUFREQ_HIGH, 0}, + {CPUFREQ_LOW, 0}, + {0, CPUFREQ_TABLE_END}, +}; + +static struct freq_attr* pmac_cpu_freqs_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + +static inline void local_delay(unsigned long ms) +{ + if (no_schedule) + mdelay(ms); + else + msleep(ms); +} + +static inline void wakeup_decrementer(void) +{ + set_dec(tb_ticks_per_jiffy); + /* No currently-supported powerbook has a 601, + * so use get_tbl, not native + */ + last_jiffy_stamp(0) = tb_last_stamp = get_tbl(); +} + +#ifdef DEBUG_FREQ +static inline void debug_calc_bogomips(void) +{ + /* This will cause a recalc of bogomips and display the + * result. We backup/restore the value to avoid affecting the + * core cpufreq framework's own calculation. + */ + extern void calibrate_delay(void); + + unsigned long save_lpj = loops_per_jiffy; + calibrate_delay(); + loops_per_jiffy = save_lpj; +} +#endif /* DEBUG_FREQ */ + +/* Switch CPU speed under 750FX CPU control + */ +static int cpu_750fx_cpu_speed(int low_speed) +{ + u32 hid2; + + if (low_speed == 0) { + /* ramping up, set voltage first */ + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); + /* Make sure we sleep for at least 1ms */ + local_delay(10); + + /* tweak L2 for high voltage */ + if (has_cpu_l2lve) { + hid2 = mfspr(SPRN_HID2); + hid2 &= ~0x2000; + mtspr(SPRN_HID2, hid2); + } + } +#ifdef CONFIG_6xx + low_choose_750fx_pll(low_speed); +#endif + if (low_speed == 1) { + /* tweak L2 for low voltage */ + if (has_cpu_l2lve) { + hid2 = mfspr(SPRN_HID2); + hid2 |= 0x2000; + mtspr(SPRN_HID2, hid2); + } + + /* ramping down, set voltage last */ + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); + local_delay(10); + } + + return 0; +} + +static unsigned int cpu_750fx_get_cpu_speed(void) +{ + if (mfspr(SPRN_HID1) & HID1_PS) + return low_freq; + else + return hi_freq; +} + +/* Switch CPU speed using DFS */ +static int dfs_set_cpu_speed(int low_speed) +{ + if (low_speed == 0) { + /* ramping up, set voltage first */ + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); + /* Make sure we sleep for at least 1ms */ + local_delay(1); + } + + /* set frequency */ +#ifdef CONFIG_6xx + low_choose_7447a_dfs(low_speed); +#endif + udelay(100); + + if (low_speed == 1) { + /* ramping down, set voltage last */ + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); + local_delay(1); + } + + return 0; +} + +static unsigned int dfs_get_cpu_speed(void) +{ + if (mfspr(SPRN_HID1) & HID1_DFS) + return low_freq; + else + return hi_freq; +} + + +/* Switch CPU speed using slewing GPIOs + */ +static int gpios_set_cpu_speed(int low_speed) +{ + int gpio, timeout = 0; + + /* If ramping up, set voltage first */ + if (low_speed == 0) { + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05); + /* Delay is way too big but it's ok, we schedule */ + local_delay(10); + } + + /* Set frequency */ + gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0); + if (low_speed == ((gpio & 0x01) == 0)) + goto skip; + + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio, + low_speed ? 0x04 : 0x05); + udelay(200); + do { + if (++timeout > 100) + break; + local_delay(1); + gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0); + } while((gpio & 0x02) == 0); + skip: + /* If ramping down, set voltage last */ + if (low_speed == 1) { + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04); + /* Delay is way too big but it's ok, we schedule */ + local_delay(10); + } + +#ifdef DEBUG_FREQ + debug_calc_bogomips(); +#endif + + return 0; +} + +/* Switch CPU speed under PMU control + */ +static int pmu_set_cpu_speed(int low_speed) +{ + struct adb_request req; + unsigned long save_l2cr; + unsigned long save_l3cr; + unsigned int pic_prio; + unsigned long flags; + + preempt_disable(); + +#ifdef DEBUG_FREQ + printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1)); +#endif + pmu_suspend(); + + /* Disable all interrupt sources on openpic */ + pic_prio = mpic_cpu_get_priority(); + mpic_cpu_set_priority(0xf); + + /* Make sure the decrementer won't interrupt us */ + asm volatile("mtdec %0" : : "r" (0x7fffffff)); + /* Make sure any pending DEC interrupt occuring while we did + * the above didn't re-enable the DEC */ + mb(); + asm volatile("mtdec %0" : : "r" (0x7fffffff)); + + /* We can now disable MSR_EE */ + local_irq_save(flags); + + /* Giveup the FPU & vec */ + enable_kernel_fp(); + +#ifdef CONFIG_ALTIVEC + if (cpu_has_feature(CPU_FTR_ALTIVEC)) + enable_kernel_altivec(); +#endif /* CONFIG_ALTIVEC */ + + /* Save & disable L2 and L3 caches */ + save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ + save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ + + /* Send the new speed command. My assumption is that this command + * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep + */ + pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed); + while (!req.complete) + pmu_poll(); + + /* Prepare the northbridge for the speed transition */ + pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1); + + /* Call low level code to backup CPU state and recover from + * hardware reset + */ + low_sleep_handler(); + + /* Restore the northbridge */ + pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0); + + /* Restore L2 cache */ + if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0) + _set_L2CR(save_l2cr); + /* Restore L3 cache */ + if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0) + _set_L3CR(save_l3cr); + + /* Restore userland MMU context */ + set_context(current->active_mm->context, current->active_mm->pgd); + +#ifdef DEBUG_FREQ + printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1)); +#endif + + /* Restore low level PMU operations */ + pmu_unlock(); + + /* Restore decrementer */ + wakeup_decrementer(); + + /* Restore interrupts */ + mpic_cpu_set_priority(pic_prio); + + /* Let interrupts flow again ... */ + local_irq_restore(flags); + +#ifdef DEBUG_FREQ + debug_calc_bogomips(); +#endif + + pmu_resume(); + + preempt_enable(); + + return 0; +} + +static int do_set_cpu_speed(int speed_mode, int notify) +{ + struct cpufreq_freqs freqs; + unsigned long l3cr; + static unsigned long prev_l3cr; + + freqs.old = cur_freq; + freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq; + freqs.cpu = smp_processor_id(); + + if (freqs.old == freqs.new) + return 0; + + if (notify) + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); + if (speed_mode == CPUFREQ_LOW && + cpu_has_feature(CPU_FTR_L3CR)) { + l3cr = _get_L3CR(); + if (l3cr & L3CR_L3E) { + prev_l3cr = l3cr; + _set_L3CR(0); + } + } + set_speed_proc(speed_mode == CPUFREQ_LOW); + if (speed_mode == CPUFREQ_HIGH && + cpu_has_feature(CPU_FTR_L3CR)) { + l3cr = _get_L3CR(); + if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr) + _set_L3CR(prev_l3cr); + } + if (notify) + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); + cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq; + + return 0; +} + +static unsigned int pmac_cpufreq_get_speed(unsigned int cpu) +{ + return cur_freq; +} + +static int pmac_cpufreq_verify(struct cpufreq_policy *policy) +{ + return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs); +} + +static int pmac_cpufreq_target( struct cpufreq_policy *policy, + unsigned int target_freq, + unsigned int relation) +{ + unsigned int newstate = 0; + + if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs, + target_freq, relation, &newstate)) + return -EINVAL; + + return do_set_cpu_speed(newstate, 1); +} + +unsigned int pmac_get_one_cpufreq(int i) +{ + /* Supports only one CPU for now */ + return (i == 0) ? cur_freq : 0; +} + +static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy) +{ + if (policy->cpu != 0) + return -ENODEV; + + policy->governor = CPUFREQ_DEFAULT_GOVERNOR; + policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + policy->cur = cur_freq; + + cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu); + return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs); +} + +static u32 read_gpio(struct device_node *np) +{ + u32 *reg = (u32 *)get_property(np, "reg", NULL); + u32 offset; + + if (reg == NULL) + return 0; + /* That works for all keylargos but shall be fixed properly + * some day... The problem is that it seems we can't rely + * on the "reg" property of the GPIO nodes, they are either + * relative to the base of KeyLargo or to the base of the + * GPIO space, and the device-tree doesn't help. + */ + offset = *reg; + if (offset < KEYLARGO_GPIO_LEVELS0) + offset += KEYLARGO_GPIO_LEVELS0; + return offset; +} + +static int pmac_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg) +{ + /* Ok, this could be made a bit smarter, but let's be robust for now. We + * always force a speed change to high speed before sleep, to make sure + * we have appropriate voltage and/or bus speed for the wakeup process, + * and to make sure our loops_per_jiffies are "good enough", that is will + * not cause too short delays if we sleep in low speed and wake in high + * speed.. + */ + no_schedule = 1; + sleep_freq = cur_freq; + if (cur_freq == low_freq && !is_pmu_based) + do_set_cpu_speed(CPUFREQ_HIGH, 0); + return 0; +} + +static int pmac_cpufreq_resume(struct cpufreq_policy *policy) +{ + /* If we resume, first check if we have a get() function */ + if (get_speed_proc) + cur_freq = get_speed_proc(); + else + cur_freq = 0; + + /* We don't, hrm... we don't really know our speed here, best + * is that we force a switch to whatever it was, which is + * probably high speed due to our suspend() routine + */ + do_set_cpu_speed(sleep_freq == low_freq ? + CPUFREQ_LOW : CPUFREQ_HIGH, 0); + + no_schedule = 0; + return 0; +} + +static struct cpufreq_driver pmac_cpufreq_driver = { + .verify = pmac_cpufreq_verify, + .target = pmac_cpufreq_target, + .get = pmac_cpufreq_get_speed, + .init = pmac_cpufreq_cpu_init, + .suspend = pmac_cpufreq_suspend, + .resume = pmac_cpufreq_resume, + .flags = CPUFREQ_PM_NO_WARN, + .attr = pmac_cpu_freqs_attr, + .name = "powermac", + .owner = THIS_MODULE, +}; + + +static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode) +{ + struct device_node *volt_gpio_np = of_find_node_by_name(NULL, + "voltage-gpio"); + struct device_node *freq_gpio_np = of_find_node_by_name(NULL, + "frequency-gpio"); + struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL, + "slewing-done"); + u32 *value; + + /* + * Check to see if it's GPIO driven or PMU only + * + * The way we extract the GPIO address is slightly hackish, but it + * works well enough for now. We need to abstract the whole GPIO + * stuff sooner or later anyway + */ + + if (volt_gpio_np) + voltage_gpio = read_gpio(volt_gpio_np); + if (freq_gpio_np) + frequency_gpio = read_gpio(freq_gpio_np); + if (slew_done_gpio_np) + slew_done_gpio = read_gpio(slew_done_gpio_np); + + /* If we use the frequency GPIOs, calculate the min/max speeds based + * on the bus frequencies + */ + if (frequency_gpio && slew_done_gpio) { + int lenp, rc; + u32 *freqs, *ratio; + + freqs = (u32 *)get_property(cpunode, "bus-frequencies", &lenp); + lenp /= sizeof(u32); + if (freqs == NULL || lenp != 2) { + printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n"); + return 1; + } + ratio = (u32 *)get_property(cpunode, "processor-to-bus-ratio*2", NULL); + if (ratio == NULL) { + printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n"); + return 1; + } + + /* Get the min/max bus frequencies */ + low_freq = min(freqs[0], freqs[1]); + hi_freq = max(freqs[0], freqs[1]); + + /* Grrrr.. It _seems_ that the device-tree is lying on the low bus + * frequency, it claims it to be around 84Mhz on some models while + * it appears to be approx. 101Mhz on all. Let's hack around here... + * fortunately, we don't need to be too precise + */ + if (low_freq < 98000000) + low_freq = 101000000; + + /* Convert those to CPU core clocks */ + low_freq = (low_freq * (*ratio)) / 2000; + hi_freq = (hi_freq * (*ratio)) / 2000; + + /* Now we get the frequencies, we read the GPIO to see what is out current + * speed + */ + rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0); + cur_freq = (rc & 0x01) ? hi_freq : low_freq; + + set_speed_proc = gpios_set_cpu_speed; + return 1; + } + + /* If we use the PMU, look for the min & max frequencies in the + * device-tree + */ + value = (u32 *)get_property(cpunode, "min-clock-frequency", NULL); + if (!value) + return 1; + low_freq = (*value) / 1000; + /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree + * here */ + if (low_freq < 100000) + low_freq *= 10; + + value = (u32 *)get_property(cpunode, "max-clock-frequency", NULL); + if (!value) + return 1; + hi_freq = (*value) / 1000; + set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; + + return 0; +} + +static int pmac_cpufreq_init_7447A(struct device_node *cpunode) +{ + struct device_node *volt_gpio_np; + + if (get_property(cpunode, "dynamic-power-step", NULL) == NULL) + return 1; + + volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select"); + if (volt_gpio_np) + voltage_gpio = read_gpio(volt_gpio_np); + if (!voltage_gpio){ + printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n"); + return 1; + } + + /* OF only reports the high frequency */ + hi_freq = cur_freq; + low_freq = cur_freq/2; + + /* Read actual frequency from CPU */ + cur_freq = dfs_get_cpu_speed(); + set_speed_proc = dfs_set_cpu_speed; + get_speed_proc = dfs_get_cpu_speed; + + return 0; +} + +static int pmac_cpufreq_init_750FX(struct device_node *cpunode) +{ + struct device_node *volt_gpio_np; + u32 pvr, *value; + + if (get_property(cpunode, "dynamic-power-step", NULL) == NULL) + return 1; + + hi_freq = cur_freq; + value = (u32 *)get_property(cpunode, "reduced-clock-frequency", NULL); + if (!value) + return 1; + low_freq = (*value) / 1000; + + volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select"); + if (volt_gpio_np) + voltage_gpio = read_gpio(volt_gpio_np); + + pvr = mfspr(SPRN_PVR); + has_cpu_l2lve = !((pvr & 0xf00) == 0x100); + + set_speed_proc = cpu_750fx_cpu_speed; + get_speed_proc = cpu_750fx_get_cpu_speed; + cur_freq = cpu_750fx_get_cpu_speed(); + + return 0; +} + +/* Currently, we support the following machines: + * + * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz) + * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz) + * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz) + * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz) + * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz) + * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage) + * - Recent MacRISC3 laptops + * - All new machines with 7447A CPUs + */ +static int __init pmac_cpufreq_setup(void) +{ + struct device_node *cpunode; + u32 *value; + + if (strstr(cmd_line, "nocpufreq")) + return 0; + + /* Assume only one CPU */ + cpunode = find_type_devices("cpu"); + if (!cpunode) + goto out; + + /* Get current cpu clock freq */ + value = (u32 *)get_property(cpunode, "clock-frequency", NULL); + if (!value) + goto out; + cur_freq = (*value) / 1000; + + /* Check for 7447A based MacRISC3 */ + if (machine_is_compatible("MacRISC3") && + get_property(cpunode, "dynamic-power-step", NULL) && + PVR_VER(mfspr(SPRN_PVR)) == 0x8003) { + pmac_cpufreq_init_7447A(cpunode); + /* Check for other MacRISC3 machines */ + } else if (machine_is_compatible("PowerBook3,4") || + machine_is_compatible("PowerBook3,5") || + machine_is_compatible("MacRISC3")) { + pmac_cpufreq_init_MacRISC3(cpunode); + /* Else check for iBook2 500/600 */ + } else if (machine_is_compatible("PowerBook4,1")) { + hi_freq = cur_freq; + low_freq = 400000; + set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; + } + /* Else check for TiPb 400 & 500 */ + else if (machine_is_compatible("PowerBook3,2")) { + /* We only know about the 400 MHz and the 500Mhz model + * they both have 300 MHz as low frequency + */ + if (cur_freq < 350000 || cur_freq > 550000) + goto out; + hi_freq = cur_freq; + low_freq = 300000; + set_speed_proc = pmu_set_cpu_speed; + is_pmu_based = 1; + } + /* Else check for 750FX */ + else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000) + pmac_cpufreq_init_750FX(cpunode); +out: + if (set_speed_proc == NULL) + return -ENODEV; + + pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq; + pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq; + + printk(KERN_INFO "Registering PowerMac CPU frequency driver\n"); + printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n", + low_freq/1000, hi_freq/1000, cur_freq/1000); + + return cpufreq_register_driver(&pmac_cpufreq_driver); +} + +module_init(pmac_cpufreq_setup); + diff --git a/arch/powerpc/platforms/powermac/pmac_feature.c b/arch/powerpc/platforms/powermac/pmac_feature.c new file mode 100644 index 00000000000..2cba670c71b --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_feature.c @@ -0,0 +1,3062 @@ +/* + * arch/ppc/platforms/pmac_feature.c + * + * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au) + * Ben. Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * TODO: + * + * - Replace mdelay with some schedule loop if possible + * - Shorten some obfuscated delays on some routines (like modem + * power) + * - Refcount some clocks (see darwin) + * - Split split split... + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef DEBUG_FEATURE + +#ifdef DEBUG_FEATURE +#define DBG(fmt...) printk(KERN_DEBUG fmt) +#else +#define DBG(fmt...) +#endif + +#ifdef CONFIG_6xx +extern int powersave_lowspeed; +#endif + +extern int powersave_nap; +extern struct device_node *k2_skiplist[2]; + + +/* + * We use a single global lock to protect accesses. Each driver has + * to take care of its own locking + */ +static DEFINE_SPINLOCK(feature_lock); + +#define LOCK(flags) spin_lock_irqsave(&feature_lock, flags); +#define UNLOCK(flags) spin_unlock_irqrestore(&feature_lock, flags); + + +/* + * Instance of some macio stuffs + */ +struct macio_chip macio_chips[MAX_MACIO_CHIPS]; + +struct macio_chip *macio_find(struct device_node *child, int type) +{ + while(child) { + int i; + + for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++) + if (child == macio_chips[i].of_node && + (!type || macio_chips[i].type == type)) + return &macio_chips[i]; + child = child->parent; + } + return NULL; +} +EXPORT_SYMBOL_GPL(macio_find); + +static const char *macio_names[] = +{ + "Unknown", + "Grand Central", + "OHare", + "OHareII", + "Heathrow", + "Gatwick", + "Paddington", + "Keylargo", + "Pangea", + "Intrepid", + "K2" +}; + + + +/* + * Uninorth reg. access. Note that Uni-N regs are big endian + */ + +#define UN_REG(r) (uninorth_base + ((r) >> 2)) +#define UN_IN(r) (in_be32(UN_REG(r))) +#define UN_OUT(r,v) (out_be32(UN_REG(r), (v))) +#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v))) +#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v))) + +static struct device_node *uninorth_node; +static u32 __iomem *uninorth_base; +static u32 uninorth_rev; +static int uninorth_u3; +static void __iomem *u3_ht; + +/* + * For each motherboard family, we have a table of functions pointers + * that handle the various features. + */ + +typedef long (*feature_call)(struct device_node *node, long param, long value); + +struct feature_table_entry { + unsigned int selector; + feature_call function; +}; + +struct pmac_mb_def +{ + const char* model_string; + const char* model_name; + int model_id; + struct feature_table_entry* features; + unsigned long board_flags; +}; +static struct pmac_mb_def pmac_mb; + +/* + * Here are the chip specific feature functions + */ + +static inline int simple_feature_tweak(struct device_node *node, int type, + int reg, u32 mask, int value) +{ + struct macio_chip* macio; + unsigned long flags; + + macio = macio_find(node, type); + if (!macio) + return -ENODEV; + LOCK(flags); + if (value) + MACIO_BIS(reg, mask); + else + MACIO_BIC(reg, mask); + (void)MACIO_IN32(reg); + UNLOCK(flags); + + return 0; +} + +#ifndef CONFIG_POWER4 + +static long ohare_htw_scc_enable(struct device_node *node, long param, + long value) +{ + struct macio_chip* macio; + unsigned long chan_mask; + unsigned long fcr; + unsigned long flags; + int htw, trans; + unsigned long rmask; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + if (!strcmp(node->name, "ch-a")) + chan_mask = MACIO_FLAG_SCCA_ON; + else if (!strcmp(node->name, "ch-b")) + chan_mask = MACIO_FLAG_SCCB_ON; + else + return -ENODEV; + + htw = (macio->type == macio_heathrow || macio->type == macio_paddington + || macio->type == macio_gatwick); + /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */ + trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && + pmac_mb.model_id != PMAC_TYPE_YIKES); + if (value) { +#ifdef CONFIG_ADB_PMU + if ((param & 0xfff) == PMAC_SCC_IRDA) + pmu_enable_irled(1); +#endif /* CONFIG_ADB_PMU */ + LOCK(flags); + fcr = MACIO_IN32(OHARE_FCR); + /* Check if scc cell need enabling */ + if (!(fcr & OH_SCC_ENABLE)) { + fcr |= OH_SCC_ENABLE; + if (htw) { + /* Side effect: this will also power up the + * modem, but it's too messy to figure out on which + * ports this controls the tranceiver and on which + * it controls the modem + */ + if (trans) + fcr &= ~HRW_SCC_TRANS_EN_N; + MACIO_OUT32(OHARE_FCR, fcr); + fcr |= (rmask = HRW_RESET_SCC); + MACIO_OUT32(OHARE_FCR, fcr); + } else { + fcr |= (rmask = OH_SCC_RESET); + MACIO_OUT32(OHARE_FCR, fcr); + } + UNLOCK(flags); + (void)MACIO_IN32(OHARE_FCR); + mdelay(15); + LOCK(flags); + fcr &= ~rmask; + MACIO_OUT32(OHARE_FCR, fcr); + } + if (chan_mask & MACIO_FLAG_SCCA_ON) + fcr |= OH_SCCA_IO; + if (chan_mask & MACIO_FLAG_SCCB_ON) + fcr |= OH_SCCB_IO; + MACIO_OUT32(OHARE_FCR, fcr); + macio->flags |= chan_mask; + UNLOCK(flags); + if (param & PMAC_SCC_FLAG_XMON) + macio->flags |= MACIO_FLAG_SCC_LOCKED; + } else { + if (macio->flags & MACIO_FLAG_SCC_LOCKED) + return -EPERM; + LOCK(flags); + fcr = MACIO_IN32(OHARE_FCR); + if (chan_mask & MACIO_FLAG_SCCA_ON) + fcr &= ~OH_SCCA_IO; + if (chan_mask & MACIO_FLAG_SCCB_ON) + fcr &= ~OH_SCCB_IO; + MACIO_OUT32(OHARE_FCR, fcr); + if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { + fcr &= ~OH_SCC_ENABLE; + if (htw && trans) + fcr |= HRW_SCC_TRANS_EN_N; + MACIO_OUT32(OHARE_FCR, fcr); + } + macio->flags &= ~(chan_mask); + UNLOCK(flags); + mdelay(10); +#ifdef CONFIG_ADB_PMU + if ((param & 0xfff) == PMAC_SCC_IRDA) + pmu_enable_irled(0); +#endif /* CONFIG_ADB_PMU */ + } + return 0; +} + +static long ohare_floppy_enable(struct device_node *node, long param, + long value) +{ + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_FLOPPY_ENABLE, value); +} + +static long ohare_mesh_enable(struct device_node *node, long param, long value) +{ + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_MESH_ENABLE, value); +} + +static long ohare_ide_enable(struct device_node *node, long param, long value) +{ + switch(param) { + case 0: + /* For some reason, setting the bit in set_initial_features() + * doesn't stick. I'm still investigating... --BenH. + */ + if (value) + simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_IOBUS_ENABLE, 1); + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_IDE0_ENABLE, value); + case 1: + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_BAY_IDE_ENABLE, value); + default: + return -ENODEV; + } +} + +static long ohare_ide_reset(struct device_node *node, long param, long value) +{ + switch(param) { + case 0: + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_IDE0_RESET_N, !value); + case 1: + return simple_feature_tweak(node, macio_ohare, + OHARE_FCR, OH_IDE1_RESET_N, !value); + default: + return -ENODEV; + } +} + +static long ohare_sleep_state(struct device_node *node, long param, long value) +{ + struct macio_chip* macio = &macio_chips[0]; + + if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) + return -EPERM; + if (value == 1) { + MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE); + } else if (value == 0) { + MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); + } + + return 0; +} + +static long heathrow_modem_enable(struct device_node *node, long param, + long value) +{ + struct macio_chip* macio; + u8 gpio; + unsigned long flags; + + macio = macio_find(node, macio_unknown); + if (!macio) + return -ENODEV; + gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1; + if (!value) { + LOCK(flags); + MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); + UNLOCK(flags); + (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); + mdelay(250); + } + if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && + pmac_mb.model_id != PMAC_TYPE_YIKES) { + LOCK(flags); + if (value) + MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); + else + MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); + UNLOCK(flags); + (void)MACIO_IN32(HEATHROW_FCR); + mdelay(250); + } + if (value) { + LOCK(flags); + MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); + (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); + (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); + (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); + } + return 0; +} + +static long heathrow_floppy_enable(struct device_node *node, long param, + long value) +{ + return simple_feature_tweak(node, macio_unknown, + HEATHROW_FCR, + HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE, + value); +} + +static long heathrow_mesh_enable(struct device_node *node, long param, + long value) +{ + struct macio_chip* macio; + unsigned long flags; + + macio = macio_find(node, macio_unknown); + if (!macio) + return -ENODEV; + LOCK(flags); + /* Set clear mesh cell enable */ + if (value) + MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE); + else + MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE); + (void)MACIO_IN32(HEATHROW_FCR); + udelay(10); + /* Set/Clear termination power */ + if (value) + MACIO_BIC(HEATHROW_MBCR, 0x04000000); + else + MACIO_BIS(HEATHROW_MBCR, 0x04000000); + (void)MACIO_IN32(HEATHROW_MBCR); + udelay(10); + UNLOCK(flags); + + return 0; +} + +static long heathrow_ide_enable(struct device_node *node, long param, + long value) +{ + switch(param) { + case 0: + return simple_feature_tweak(node, macio_unknown, + HEATHROW_FCR, HRW_IDE0_ENABLE, value); + case 1: + return simple_feature_tweak(node, macio_unknown, + HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value); + default: + return -ENODEV; + } +} + +static long heathrow_ide_reset(struct device_node *node, long param, + long value) +{ + switch(param) { + case 0: + return simple_feature_tweak(node, macio_unknown, + HEATHROW_FCR, HRW_IDE0_RESET_N, !value); + case 1: + return simple_feature_tweak(node, macio_unknown, + HEATHROW_FCR, HRW_IDE1_RESET_N, !value); + default: + return -ENODEV; + } +} + +static long heathrow_bmac_enable(struct device_node *node, long param, + long value) +{ + struct macio_chip* macio; + unsigned long flags; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + if (value) { + LOCK(flags); + MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); + MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET); + UNLOCK(flags); + (void)MACIO_IN32(HEATHROW_FCR); + mdelay(10); + LOCK(flags); + MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET); + UNLOCK(flags); + (void)MACIO_IN32(HEATHROW_FCR); + mdelay(10); + } else { + LOCK(flags); + MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); + UNLOCK(flags); + } + return 0; +} + +static long heathrow_sound_enable(struct device_node *node, long param, + long value) +{ + struct macio_chip* macio; + unsigned long flags; + + /* B&W G3 and Yikes don't support that properly (the + * sound appear to never come back after beeing shut down). + */ + if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE || + pmac_mb.model_id == PMAC_TYPE_YIKES) + return 0; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + if (value) { + LOCK(flags); + MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); + MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); + UNLOCK(flags); + (void)MACIO_IN32(HEATHROW_FCR); + } else { + LOCK(flags); + MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); + MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); + UNLOCK(flags); + } + return 0; +} + +static u32 save_fcr[6]; +static u32 save_mbcr; +static u32 save_gpio_levels[2]; +static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT]; +static u8 save_gpio_normal[KEYLARGO_GPIO_CNT]; +static u32 save_unin_clock_ctl; +static struct dbdma_regs save_dbdma[13]; +static struct dbdma_regs save_alt_dbdma[13]; + +static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save) +{ + int i; + + /* Save state & config of DBDMA channels */ + for (i = 0; i < 13; i++) { + volatile struct dbdma_regs __iomem * chan = (void __iomem *) + (macio->base + ((0x8000+i*0x100)>>2)); + save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi); + save[i].cmdptr = in_le32(&chan->cmdptr); + save[i].intr_sel = in_le32(&chan->intr_sel); + save[i].br_sel = in_le32(&chan->br_sel); + save[i].wait_sel = in_le32(&chan->wait_sel); + } +} + +static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save) +{ + int i; + + /* Save state & config of DBDMA channels */ + for (i = 0; i < 13; i++) { + volatile struct dbdma_regs __iomem * chan = (void __iomem *) + (macio->base + ((0x8000+i*0x100)>>2)); + out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); + while (in_le32(&chan->status) & ACTIVE) + mb(); + out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi); + out_le32(&chan->cmdptr, save[i].cmdptr); + out_le32(&chan->intr_sel, save[i].intr_sel); + out_le32(&chan->br_sel, save[i].br_sel); + out_le32(&chan->wait_sel, save[i].wait_sel); + } +} + +static void heathrow_sleep(struct macio_chip *macio, int secondary) +{ + if (secondary) { + dbdma_save(macio, save_alt_dbdma); + save_fcr[2] = MACIO_IN32(0x38); + save_fcr[3] = MACIO_IN32(0x3c); + } else { + dbdma_save(macio, save_dbdma); + save_fcr[0] = MACIO_IN32(0x38); + save_fcr[1] = MACIO_IN32(0x3c); + save_mbcr = MACIO_IN32(0x34); + /* Make sure sound is shut down */ + MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); + MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); + /* This seems to be necessary as well or the fan + * keeps coming up and battery drains fast */ + MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE); + MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N); + /* Make sure eth is down even if module or sleep + * won't work properly */ + MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET); + } + /* Make sure modem is shut down */ + MACIO_OUT8(HRW_GPIO_MODEM_RESET, + MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1); + MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); + MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE); + + /* Let things settle */ + (void)MACIO_IN32(HEATHROW_FCR); +} + +static void heathrow_wakeup(struct macio_chip *macio, int secondary) +{ + if (secondary) { + MACIO_OUT32(0x38, save_fcr[2]); + (void)MACIO_IN32(0x38); + mdelay(1); + MACIO_OUT32(0x3c, save_fcr[3]); + (void)MACIO_IN32(0x38); + mdelay(10); + dbdma_restore(macio, save_alt_dbdma); + } else { + MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE); + (void)MACIO_IN32(0x38); + mdelay(1); + MACIO_OUT32(0x3c, save_fcr[1]); + (void)MACIO_IN32(0x38); + mdelay(1); + MACIO_OUT32(0x34, save_mbcr); + (void)MACIO_IN32(0x38); + mdelay(10); + dbdma_restore(macio, save_dbdma); + } +} + +static long heathrow_sleep_state(struct device_node *node, long param, + long value) +{ + if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) + return -EPERM; + if (value == 1) { + if (macio_chips[1].type == macio_gatwick) + heathrow_sleep(&macio_chips[0], 1); + heathrow_sleep(&macio_chips[0], 0); + } else if (value == 0) { + heathrow_wakeup(&macio_chips[0], 0); + if (macio_chips[1].type == macio_gatwick) + heathrow_wakeup(&macio_chips[0], 1); + } + return 0; +} + +static long core99_scc_enable(struct device_node *node, long param, long value) +{ + struct macio_chip* macio; + unsigned long flags; + unsigned long chan_mask; + u32 fcr; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + if (!strcmp(node->name, "ch-a")) + chan_mask = MACIO_FLAG_SCCA_ON; + else if (!strcmp(node->name, "ch-b")) + chan_mask = MACIO_FLAG_SCCB_ON; + else + return -ENODEV; + + if (value) { + int need_reset_scc = 0; + int need_reset_irda = 0; + + LOCK(flags); + fcr = MACIO_IN32(KEYLARGO_FCR0); + /* Check if scc cell need enabling */ + if (!(fcr & KL0_SCC_CELL_ENABLE)) { + fcr |= KL0_SCC_CELL_ENABLE; + need_reset_scc = 1; + } + if (chan_mask & MACIO_FLAG_SCCA_ON) { + fcr |= KL0_SCCA_ENABLE; + /* Don't enable line drivers for I2S modem */ + if ((param & 0xfff) == PMAC_SCC_I2S1) + fcr &= ~KL0_SCC_A_INTF_ENABLE; + else + fcr |= KL0_SCC_A_INTF_ENABLE; + } + if (chan_mask & MACIO_FLAG_SCCB_ON) { + fcr |= KL0_SCCB_ENABLE; + /* Perform irda specific inits */ + if ((param & 0xfff) == PMAC_SCC_IRDA) { + fcr &= ~KL0_SCC_B_INTF_ENABLE; + fcr |= KL0_IRDA_ENABLE; + fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; + fcr |= KL0_IRDA_SOURCE1_SEL; + fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); + fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); + need_reset_irda = 1; + } else + fcr |= KL0_SCC_B_INTF_ENABLE; + } + MACIO_OUT32(KEYLARGO_FCR0, fcr); + macio->flags |= chan_mask; + if (need_reset_scc) { + MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET); + (void)MACIO_IN32(KEYLARGO_FCR0); + UNLOCK(flags); + mdelay(15); + LOCK(flags); + MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET); + } + if (need_reset_irda) { + MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET); + (void)MACIO_IN32(KEYLARGO_FCR0); + UNLOCK(flags); + mdelay(15); + LOCK(flags); + MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET); + } + UNLOCK(flags); + if (param & PMAC_SCC_FLAG_XMON) + macio->flags |= MACIO_FLAG_SCC_LOCKED; + } else { + if (macio->flags & MACIO_FLAG_SCC_LOCKED) + return -EPERM; + LOCK(flags); + fcr = MACIO_IN32(KEYLARGO_FCR0); + if (chan_mask & MACIO_FLAG_SCCA_ON) + fcr &= ~KL0_SCCA_ENABLE; + if (chan_mask & MACIO_FLAG_SCCB_ON) { + fcr &= ~KL0_SCCB_ENABLE; + /* Perform irda specific clears */ + if ((param & 0xfff) == PMAC_SCC_IRDA) { + fcr &= ~KL0_IRDA_ENABLE; + fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); + fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); + fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); + } + } + MACIO_OUT32(KEYLARGO_FCR0, fcr); + if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { + fcr &= ~KL0_SCC_CELL_ENABLE; + MACIO_OUT32(KEYLARGO_FCR0, fcr); + } + macio->flags &= ~(chan_mask); + UNLOCK(flags); + mdelay(10); + } + return 0; +} + +static long +core99_modem_enable(struct device_node *node, long param, long value) +{ + struct macio_chip* macio; + u8 gpio; + unsigned long flags; + + /* Hack for internal USB modem */ + if (node == NULL) { + if (macio_chips[0].type != macio_keylargo) + return -ENODEV; + node = macio_chips[0].of_node; + } + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); + gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; + gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; + + if (!value) { + LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); + UNLOCK(flags); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + mdelay(250); + } + LOCK(flags); + if (value) { + MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); + UNLOCK(flags); + (void)MACIO_IN32(KEYLARGO_FCR2); + mdelay(250); + } else { + MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); + UNLOCK(flags); + } + if (value) { + LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); + } + return 0; +} + +static long +pangea_modem_enable(struct device_node *node, long param, long value) +{ + struct macio_chip* macio; + u8 gpio; + unsigned long flags; + + /* Hack for internal USB modem */ + if (node == NULL) { + if (macio_chips[0].type != macio_pangea && + macio_chips[0].type != macio_intrepid) + return -ENODEV; + node = macio_chips[0].of_node; + } + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); + gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; + gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; + + if (!value) { + LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); + UNLOCK(flags); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + mdelay(250); + } + LOCK(flags); + if (value) { + MACIO_OUT8(KL_GPIO_MODEM_POWER, + KEYLARGO_GPIO_OUTPUT_ENABLE); + UNLOCK(flags); + (void)MACIO_IN32(KEYLARGO_FCR2); + mdelay(250); + } else { + MACIO_OUT8(KL_GPIO_MODEM_POWER, + KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); + UNLOCK(flags); + } + if (value) { + LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); LOCK(flags); + MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); + (void)MACIO_IN8(KL_GPIO_MODEM_RESET); + UNLOCK(flags); mdelay(250); + } + return 0; +} + +static long +core99_ata100_enable(struct device_node *node, long value) +{ + unsigned long flags; + struct pci_dev *pdev = NULL; + u8 pbus, pid; + + if (uninorth_rev < 0x24) + return -ENODEV; + + LOCK(flags); + if (value) + UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); + else + UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); + (void)UN_IN(UNI_N_CLOCK_CNTL); + UNLOCK(flags); + udelay(20); + + if (value) { + if (pci_device_from_OF_node(node, &pbus, &pid) == 0) + pdev = pci_find_slot(pbus, pid); + if (pdev == NULL) + return 0; + pci_enable_device(pdev); + pci_set_master(pdev); + } + return 0; +} + +static long +core99_ide_enable(struct device_node *node, long param, long value) +{ + /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2 + * based ata-100 + */ + switch(param) { + case 0: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value); + case 1: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value); + case 2: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_UIDE_ENABLE, value); + case 3: + return core99_ata100_enable(node, value); + default: + return -ENODEV; + } +} + +static long +core99_ide_reset(struct device_node *node, long param, long value) +{ + switch(param) { + case 0: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value); + case 1: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value); + case 2: + return simple_feature_tweak(node, macio_unknown, + KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value); + default: + return -ENODEV; + } +} + +static long +core99_gmac_enable(struct device_node *node, long param, long value) +{ + unsigned long flags; + + LOCK(flags); + if (value) + UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); + else + UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); + (void)UN_IN(UNI_N_CLOCK_CNTL); + UNLOCK(flags); + udelay(20); + + return 0; +} + +static long +core99_gmac_phy_reset(struct device_node *node, long param, long value) +{ + unsigned long flags; + struct macio_chip *macio; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + + LOCK(flags); + MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); + (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); + UNLOCK(flags); + mdelay(10); + LOCK(flags); + MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ + KEYLARGO_GPIO_OUTOUT_DATA); + UNLOCK(flags); + mdelay(10); + + return 0; +} + +static long +core99_sound_chip_enable(struct device_node *node, long param, long value) +{ + struct macio_chip* macio; + unsigned long flags; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + + /* Do a better probe code, screamer G4 desktops & + * iMacs can do that too, add a recalibrate in + * the driver as well + */ + if (pmac_mb.model_id == PMAC_TYPE_PISMO || + pmac_mb.model_id == PMAC_TYPE_TITANIUM) { + LOCK(flags); + if (value) + MACIO_OUT8(KL_GPIO_SOUND_POWER, + KEYLARGO_GPIO_OUTPUT_ENABLE | + KEYLARGO_GPIO_OUTOUT_DATA); + else + MACIO_OUT8(KL_GPIO_SOUND_POWER, + KEYLARGO_GPIO_OUTPUT_ENABLE); + (void)MACIO_IN8(KL_GPIO_SOUND_POWER); + UNLOCK(flags); + } + return 0; +} + +static long +core99_airport_enable(struct device_node *node, long param, long value) +{ + struct macio_chip* macio; + unsigned long flags; + int state; + + macio = macio_find(node, 0); + if (!macio) + return -ENODEV; + + /* Hint: we allow passing of macio itself for the sake of the + * sleep code + */ + if (node != macio->of_node && + (!node->parent || node->parent != macio->of_node)) + return -ENODEV; + state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0; + if (value == state) + return 0; + if (value) { + /* This code is a reproduction of OF enable-cardslot + * and init-wireless methods, slightly hacked until + * I got it working. + */ + LOCK(flags); + MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5); + (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); + UNLOCK(flags); + mdelay(10); + LOCK(flags); + MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4); + (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); + UNLOCK(flags); + + mdelay(10); + + LOCK(flags); + MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); + (void)MACIO_IN32(KEYLARGO_FCR2); + udelay(10); + MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0); + (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb); + udelay(10); + MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28); + (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa); + udelay(10); + MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28); + (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd); + udelay(10); + MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28); + (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd); + udelay(10); + MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28); + (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe); + UNLOCK(flags); + udelay(10); + MACIO_OUT32(0x1c000, 0); + mdelay(1); + MACIO_OUT8(0x1a3e0, 0x41); + (void)MACIO_IN8(0x1a3e0); + udelay(10); + LOCK(flags); + MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16); + (void)MACIO_IN32(KEYLARGO_FCR2); + UNLOCK(flags); + mdelay(100); + + macio->flags |= MACIO_FLAG_AIRPORT_ON; + } else { + LOCK(flags); + MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); + (void)MACIO_IN32(KEYLARGO_FCR2); + MACIO_OUT8(KL_GPIO_AIRPORT_0, 0); + MACIO_OUT8(KL_GPIO_AIRPORT_1, 0); + MACIO_OUT8(KL_GPIO_AIRPORT_2, 0); + MACIO_OUT8(KL_GPIO_AIRPORT_3, 0); + MACIO_OUT8(KL_GPIO_AIRPORT_4, 0); + (void)MACIO_IN8(KL_GPIO_AIRPORT_4); + UNLOCK(flags); + + macio->flags &= ~MACIO_FLAG_AIRPORT_ON; + } + return 0; +} + +#ifdef CONFIG_SMP +static long +core99_reset_cpu(struct device_node *node, long param, long value) +{ + unsigned int reset_io = 0; + unsigned long flags; + struct macio_chip *macio; + struct device_node *np; + const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0, + KL_GPIO_RESET_CPU1, + KL_GPIO_RESET_CPU2, + KL_GPIO_RESET_CPU3 }; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo) + return -ENODEV; + + np = find_path_device("/cpus"); + if (np == NULL) + return -ENODEV; + for (np = np->child; np != NULL; np = np->sibling) { + u32 *num = (u32 *)get_property(np, "reg", NULL); + u32 *rst = (u32 *)get_property(np, "soft-reset", NULL); + if (num == NULL || rst == NULL) + continue; + if (param == *num) { + reset_io = *rst; + break; + } + } + if (np == NULL || reset_io == 0) + reset_io = dflt_reset_lines[param]; + + LOCK(flags); + MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); + (void)MACIO_IN8(reset_io); + udelay(1); + MACIO_OUT8(reset_io, 0); + (void)MACIO_IN8(reset_io); + UNLOCK(flags); + + return 0; +} +#endif /* CONFIG_SMP */ + +static long +core99_usb_enable(struct device_node *node, long param, long value) +{ + struct macio_chip *macio; + unsigned long flags; + char *prop; + int number; + u32 reg; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + + prop = (char *)get_property(node, "AAPL,clock-id", NULL); + if (!prop) + return -ENODEV; + if (strncmp(prop, "usb0u048", 8) == 0) + number = 0; + else if (strncmp(prop, "usb1u148", 8) == 0) + number = 2; + else if (strncmp(prop, "usb2u248", 8) == 0) + number = 4; + else + return -ENODEV; + + /* Sorry for the brute-force locking, but this is only used during + * sleep and the timing seem to be critical + */ + LOCK(flags); + if (value) { + /* Turn ON */ + if (number == 0) { + MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); + (void)MACIO_IN32(KEYLARGO_FCR0); + UNLOCK(flags); + mdelay(1); + LOCK(flags); + MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); + } else if (number == 2) { + MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); + UNLOCK(flags); + (void)MACIO_IN32(KEYLARGO_FCR0); + mdelay(1); + LOCK(flags); + MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); + } else if (number == 4) { + MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); + UNLOCK(flags); + (void)MACIO_IN32(KEYLARGO_FCR1); + mdelay(1); + LOCK(flags); + MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE); + } + if (number < 4) { + reg = MACIO_IN32(KEYLARGO_FCR4); + reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | + KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number)); + reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | + KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1)); + MACIO_OUT32(KEYLARGO_FCR4, reg); + (void)MACIO_IN32(KEYLARGO_FCR4); + udelay(10); + } else { + reg = MACIO_IN32(KEYLARGO_FCR3); + reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | + KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0)); + reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | + KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1)); + MACIO_OUT32(KEYLARGO_FCR3, reg); + (void)MACIO_IN32(KEYLARGO_FCR3); + udelay(10); + } + if (macio->type == macio_intrepid) { + /* wait for clock stopped bits to clear */ + u32 test0 = 0, test1 = 0; + u32 status0, status1; + int timeout = 1000; + + UNLOCK(flags); + switch (number) { + case 0: + test0 = UNI_N_CLOCK_STOPPED_USB0; + test1 = UNI_N_CLOCK_STOPPED_USB0PCI; + break; + case 2: + test0 = UNI_N_CLOCK_STOPPED_USB1; + test1 = UNI_N_CLOCK_STOPPED_USB1PCI; + break; + case 4: + test0 = UNI_N_CLOCK_STOPPED_USB2; + test1 = UNI_N_CLOCK_STOPPED_USB2PCI; + break; + } + do { + if (--timeout <= 0) { + printk(KERN_ERR "core99_usb_enable: " + "Timeout waiting for clocks\n"); + break; + } + mdelay(1); + status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0); + status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1); + } while ((status0 & test0) | (status1 & test1)); + LOCK(flags); + } + } else { + /* Turn OFF */ + if (number < 4) { + reg = MACIO_IN32(KEYLARGO_FCR4); + reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | + KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number); + reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | + KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1); + MACIO_OUT32(KEYLARGO_FCR4, reg); + (void)MACIO_IN32(KEYLARGO_FCR4); + udelay(1); + } else { + reg = MACIO_IN32(KEYLARGO_FCR3); + reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | + KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0); + reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | + KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1); + MACIO_OUT32(KEYLARGO_FCR3, reg); + (void)MACIO_IN32(KEYLARGO_FCR3); + udelay(1); + } + if (number == 0) { + if (macio->type != macio_intrepid) + MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); + (void)MACIO_IN32(KEYLARGO_FCR0); + udelay(1); + MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); + (void)MACIO_IN32(KEYLARGO_FCR0); + } else if (number == 2) { + if (macio->type != macio_intrepid) + MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); + (void)MACIO_IN32(KEYLARGO_FCR0); + udelay(1); + MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); + (void)MACIO_IN32(KEYLARGO_FCR0); + } else if (number == 4) { + udelay(1); + MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); + (void)MACIO_IN32(KEYLARGO_FCR1); + } + udelay(1); + } + UNLOCK(flags); + + return 0; +} + +static long +core99_firewire_enable(struct device_node *node, long param, long value) +{ + unsigned long flags; + struct macio_chip *macio; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) + return -ENODEV; + + LOCK(flags); + if (value) { + UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); + (void)UN_IN(UNI_N_CLOCK_CNTL); + } else { + UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); + (void)UN_IN(UNI_N_CLOCK_CNTL); + } + UNLOCK(flags); + mdelay(1); + + return 0; +} + +static long +core99_firewire_cable_power(struct device_node *node, long param, long value) +{ + unsigned long flags; + struct macio_chip *macio; + + /* Trick: we allow NULL node */ + if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0) + return -ENODEV; + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) + return -ENODEV; + + LOCK(flags); + if (value) { + MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0); + MACIO_IN8(KL_GPIO_FW_CABLE_POWER); + udelay(10); + } else { + MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4); + MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10); + } + UNLOCK(flags); + mdelay(1); + + return 0; +} + +static long +intrepid_aack_delay_enable(struct device_node *node, long param, long value) +{ + unsigned long flags; + + if (uninorth_rev < 0xd2) + return -ENODEV; + + LOCK(flags); + if (param) + UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); + else + UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); + UNLOCK(flags); + + return 0; +} + + +#endif /* CONFIG_POWER4 */ + +static long +core99_read_gpio(struct device_node *node, long param, long value) +{ + struct macio_chip *macio = &macio_chips[0]; + + return MACIO_IN8(param); +} + + +static long +core99_write_gpio(struct device_node *node, long param, long value) +{ + struct macio_chip *macio = &macio_chips[0]; + + MACIO_OUT8(param, (u8)(value & 0xff)); + return 0; +} + +#ifdef CONFIG_POWER4 +static long g5_gmac_enable(struct device_node *node, long param, long value) +{ + struct macio_chip *macio = &macio_chips[0]; + unsigned long flags; + + if (node == NULL) + return -ENODEV; + + LOCK(flags); + if (value) { + MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); + mb(); + k2_skiplist[0] = NULL; + } else { + k2_skiplist[0] = node; + mb(); + MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); + } + + UNLOCK(flags); + mdelay(1); + + return 0; +} + +static long g5_fw_enable(struct device_node *node, long param, long value) +{ + struct macio_chip *macio = &macio_chips[0]; + unsigned long flags; + + if (node == NULL) + return -ENODEV; + + LOCK(flags); + if (value) { + MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); + mb(); + k2_skiplist[1] = NULL; + } else { + k2_skiplist[1] = node; + mb(); + MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); + } + + UNLOCK(flags); + mdelay(1); + + return 0; +} + +static long g5_mpic_enable(struct device_node *node, long param, long value) +{ + unsigned long flags; + + if (node->parent == NULL || strcmp(node->parent->name, "u3")) + return 0; + + LOCK(flags); + UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE); + UNLOCK(flags); + + return 0; +} + +static long g5_eth_phy_reset(struct device_node *node, long param, long value) +{ + struct macio_chip *macio = &macio_chips[0]; + struct device_node *phy; + int need_reset; + + /* + * We must not reset the combo PHYs, only the BCM5221 found in + * the iMac G5. + */ + phy = of_get_next_child(node, NULL); + if (!phy) + return -ENODEV; + need_reset = device_is_compatible(phy, "B5221"); + of_node_put(phy); + if (!need_reset) + return 0; + + /* PHY reset is GPIO 29, not in device-tree unfortunately */ + MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, + KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); + /* Thankfully, this is now always called at a time when we can + * schedule by sungem. + */ + msleep(10); + MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0); + + return 0; +} + +static long g5_i2s_enable(struct device_node *node, long param, long value) +{ + /* Very crude implementation for now */ + struct macio_chip *macio = &macio_chips[0]; + unsigned long flags; + + if (value == 0) + return 0; /* don't disable yet */ + + LOCK(flags); + MACIO_BIS(KEYLARGO_FCR3, KL3_CLK45_ENABLE | KL3_CLK49_ENABLE | + KL3_I2S0_CLK18_ENABLE); + udelay(10); + MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_I2S0_CELL_ENABLE | + K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE); + udelay(10); + MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_I2S0_RESET); + UNLOCK(flags); + udelay(10); + + return 0; +} + + +#ifdef CONFIG_SMP +static long g5_reset_cpu(struct device_node *node, long param, long value) +{ + unsigned int reset_io = 0; + unsigned long flags; + struct macio_chip *macio; + struct device_node *np; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo2) + return -ENODEV; + + np = find_path_device("/cpus"); + if (np == NULL) + return -ENODEV; + for (np = np->child; np != NULL; np = np->sibling) { + u32 *num = (u32 *)get_property(np, "reg", NULL); + u32 *rst = (u32 *)get_property(np, "soft-reset", NULL); + if (num == NULL || rst == NULL) + continue; + if (param == *num) { + reset_io = *rst; + break; + } + } + if (np == NULL || reset_io == 0) + return -ENODEV; + + LOCK(flags); + MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); + (void)MACIO_IN8(reset_io); + udelay(1); + MACIO_OUT8(reset_io, 0); + (void)MACIO_IN8(reset_io); + UNLOCK(flags); + + return 0; +} +#endif /* CONFIG_SMP */ + +/* + * This can be called from pmac_smp so isn't static + * + * This takes the second CPU off the bus on dual CPU machines + * running UP + */ +void g5_phy_disable_cpu1(void) +{ + UN_OUT(U3_API_PHY_CONFIG_1, 0); +} +#endif /* CONFIG_POWER4 */ + +#ifndef CONFIG_POWER4 + +static void +keylargo_shutdown(struct macio_chip *macio, int sleep_mode) +{ + u32 temp; + + if (sleep_mode) { + mdelay(1); + MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND); + (void)MACIO_IN32(KEYLARGO_FCR0); + mdelay(1); + } + + MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | + KL0_SCC_CELL_ENABLE | + KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE | + KL0_IRDA_CLK19_ENABLE); + + MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK); + MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE); + + MACIO_BIC(KEYLARGO_FCR1, + KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | + KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | + KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | + KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | + KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | + KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N | + KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N | + KL1_UIDE_ENABLE); + + MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); + MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE); + + temp = MACIO_IN32(KEYLARGO_FCR3); + if (macio->rev >= 2) { + temp |= KL3_SHUTDOWN_PLL2X; + if (sleep_mode) + temp |= KL3_SHUTDOWN_PLL_TOTAL; + } + + temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | + KL3_SHUTDOWN_PLLKW35; + if (sleep_mode) + temp |= KL3_SHUTDOWN_PLLKW12; + temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE + | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); + if (sleep_mode) + temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE); + MACIO_OUT32(KEYLARGO_FCR3, temp); + + /* Flush posted writes & wait a bit */ + (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); +} + +static void +pangea_shutdown(struct macio_chip *macio, int sleep_mode) +{ + u32 temp; + + MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | + KL0_SCC_CELL_ENABLE | + KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE); + + MACIO_BIC(KEYLARGO_FCR1, + KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | + KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | + KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | + KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | + KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | + KL1_UIDE_ENABLE); + if (pmac_mb.board_flags & PMAC_MB_MOBILE) + MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); + + MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); + + temp = MACIO_IN32(KEYLARGO_FCR3); + temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | + KL3_SHUTDOWN_PLLKW35; + temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE + | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE); + if (sleep_mode) + temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE); + MACIO_OUT32(KEYLARGO_FCR3, temp); + + /* Flush posted writes & wait a bit */ + (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); +} + +static void +intrepid_shutdown(struct macio_chip *macio, int sleep_mode) +{ + u32 temp; + + MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | + KL0_SCC_CELL_ENABLE); + + MACIO_BIC(KEYLARGO_FCR1, + /*KL1_USB2_CELL_ENABLE |*/ + KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | + KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | + KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE); + if (pmac_mb.board_flags & PMAC_MB_MOBILE) + MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); + + temp = MACIO_IN32(KEYLARGO_FCR3); + temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | + KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); + if (sleep_mode) + temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE); + MACIO_OUT32(KEYLARGO_FCR3, temp); + + /* Flush posted writes & wait a bit */ + (void)MACIO_IN32(KEYLARGO_FCR0); + mdelay(10); +} + + +void pmac_tweak_clock_spreading(int enable) +{ + struct macio_chip *macio = &macio_chips[0]; + + /* Hack for doing clock spreading on some machines PowerBooks and + * iBooks. This implements the "platform-do-clockspreading" OF + * property as decoded manually on various models. For safety, we also + * check the product ID in the device-tree in cases we'll whack the i2c + * chip to make reasonably sure we won't set wrong values in there + * + * Of course, ultimately, we have to implement a real parser for + * the platform-do-* stuff... + */ + + if (macio->type == macio_intrepid) { + if (enable) + UN_OUT(UNI_N_CLOCK_SPREADING, 2); + else + UN_OUT(UNI_N_CLOCK_SPREADING, 0); + mdelay(40); + } + + while (machine_is_compatible("PowerBook5,2") || + machine_is_compatible("PowerBook5,3") || + machine_is_compatible("PowerBook6,2") || + machine_is_compatible("PowerBook6,3")) { + struct device_node *ui2c = of_find_node_by_type(NULL, "i2c"); + struct device_node *dt = of_find_node_by_name(NULL, "device-tree"); + u8 buffer[9]; + u32 *productID; + int i, rc, changed = 0; + + if (dt == NULL) + break; + productID = (u32 *)get_property(dt, "pid#", NULL); + if (productID == NULL) + break; + while(ui2c) { + struct device_node *p = of_get_parent(ui2c); + if (p && !strcmp(p->name, "uni-n")) + break; + ui2c = of_find_node_by_type(ui2c, "i2c"); + } + if (ui2c == NULL) + break; + DBG("Trying to bump clock speed for PID: %08x...\n", *productID); + rc = pmac_low_i2c_open(ui2c, 1); + if (rc != 0) + break; + pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined); + rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9); + DBG("read result: %d,", rc); + if (rc != 0) { + pmac_low_i2c_close(ui2c); + break; + } + for (i=0; i<9; i++) + DBG(" %02x", buffer[i]); + DBG("\n"); + + switch(*productID) { + case 0x1182: /* AlBook 12" rev 2 */ + case 0x1183: /* iBook G4 12" */ + buffer[0] = (buffer[0] & 0x8f) | 0x70; + buffer[2] = (buffer[2] & 0x7f) | 0x00; + buffer[5] = (buffer[5] & 0x80) | 0x31; + buffer[6] = (buffer[6] & 0x40) | 0xb0; + buffer[7] = (buffer[7] & 0x00) | (enable ? 0xc0 : 0xba); + buffer[8] = (buffer[8] & 0x00) | 0x30; + changed = 1; + break; + case 0x3142: /* AlBook 15" (ATI M10) */ + case 0x3143: /* AlBook 17" (ATI M10) */ + buffer[0] = (buffer[0] & 0xaf) | 0x50; + buffer[2] = (buffer[2] & 0x7f) | 0x00; + buffer[5] = (buffer[5] & 0x80) | 0x31; + buffer[6] = (buffer[6] & 0x40) | 0xb0; + buffer[7] = (buffer[7] & 0x00) | (enable ? 0xd0 : 0xc0); + buffer[8] = (buffer[8] & 0x00) | 0x30; + changed = 1; + break; + default: + DBG("i2c-hwclock: Machine model not handled\n"); + break; + } + if (!changed) { + pmac_low_i2c_close(ui2c); + break; + } + pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_stdsub); + rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_write, 0x80, buffer, 9); + DBG("write result: %d,", rc); + pmac_low_i2c_setmode(ui2c, pmac_low_i2c_mode_combined); + rc = pmac_low_i2c_xfer(ui2c, 0xd2 | pmac_low_i2c_read, 0x80, buffer, 9); + DBG("read result: %d,", rc); + if (rc != 0) { + pmac_low_i2c_close(ui2c); + break; + } + for (i=0; i<9; i++) + DBG(" %02x", buffer[i]); + pmac_low_i2c_close(ui2c); + break; + } +} + + +static int +core99_sleep(void) +{ + struct macio_chip *macio; + int i; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + + /* We power off the wireless slot in case it was not done + * by the driver. We don't power it on automatically however + */ + if (macio->flags & MACIO_FLAG_AIRPORT_ON) + core99_airport_enable(macio->of_node, 0, 0); + + /* We power off the FW cable. Should be done by the driver... */ + if (macio->flags & MACIO_FLAG_FW_SUPPORTED) { + core99_firewire_enable(NULL, 0, 0); + core99_firewire_cable_power(NULL, 0, 0); + } + + /* We make sure int. modem is off (in case driver lost it) */ + if (macio->type == macio_keylargo) + core99_modem_enable(macio->of_node, 0, 0); + else + pangea_modem_enable(macio->of_node, 0, 0); + + /* We make sure the sound is off as well */ + core99_sound_chip_enable(macio->of_node, 0, 0); + + /* + * Save various bits of KeyLargo + */ + + /* Save the state of the various GPIOs */ + save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0); + save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1); + for (i=0; itype == macio_keylargo) + save_mbcr = MACIO_IN32(KEYLARGO_MBCR); + save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0); + save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1); + save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2); + save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3); + save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4); + if (macio->type == macio_pangea || macio->type == macio_intrepid) + save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5); + + /* Save state & config of DBDMA channels */ + dbdma_save(macio, save_dbdma); + + /* + * Turn off as much as we can + */ + if (macio->type == macio_pangea) + pangea_shutdown(macio, 1); + else if (macio->type == macio_intrepid) + intrepid_shutdown(macio, 1); + else if (macio->type == macio_keylargo) + keylargo_shutdown(macio, 1); + + /* + * Put the host bridge to sleep + */ + + save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL); + /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it + * enabled ! + */ + UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl & + ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/)); + udelay(100); + UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); + UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP); + mdelay(10); + + /* + * FIXME: A bit of black magic with OpenPIC (don't ask me why) + */ + if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { + MACIO_BIS(0x506e0, 0x00400000); + MACIO_BIS(0x506e0, 0x80000000); + } + return 0; +} + +static int +core99_wake_up(void) +{ + struct macio_chip *macio; + int i; + + macio = &macio_chips[0]; + if (macio->type != macio_keylargo && macio->type != macio_pangea && + macio->type != macio_intrepid) + return -ENODEV; + + /* + * Wakeup the host bridge + */ + UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); + udelay(10); + UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); + udelay(10); + + /* + * Restore KeyLargo + */ + + if (macio->type == macio_keylargo) { + MACIO_OUT32(KEYLARGO_MBCR, save_mbcr); + (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10); + } + MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]); + (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10); + MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]); + (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10); + MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]); + (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10); + MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]); + (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10); + MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]); + (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10); + if (macio->type == macio_pangea || macio->type == macio_intrepid) { + MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]); + (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10); + } + + dbdma_restore(macio, save_dbdma); + + MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]); + MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]); + for (i=0; itype) { +#ifndef CONFIG_POWER4 + case macio_grand_central: + pmac_mb.model_id = PMAC_TYPE_PSURGE; + pmac_mb.model_name = "Unknown PowerSurge"; + break; + case macio_ohare: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE; + pmac_mb.model_name = "Unknown OHare-based"; + break; + case macio_heathrow: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW; + pmac_mb.model_name = "Unknown Heathrow-based"; + pmac_mb.features = heathrow_desktop_features; + break; + case macio_paddington: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON; + pmac_mb.model_name = "Unknown Paddington-based"; + pmac_mb.features = paddington_features; + break; + case macio_keylargo: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99; + pmac_mb.model_name = "Unknown Keylargo-based"; + pmac_mb.features = core99_features; + break; + case macio_pangea: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA; + pmac_mb.model_name = "Unknown Pangea-based"; + pmac_mb.features = pangea_features; + break; + case macio_intrepid: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID; + pmac_mb.model_name = "Unknown Intrepid-based"; + pmac_mb.features = intrepid_features; + break; +#else /* CONFIG_POWER4 */ + case macio_keylargo2: + pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2; + pmac_mb.model_name = "Unknown K2-based"; + pmac_mb.features = g5_features; + break; +#endif /* CONFIG_POWER4 */ + default: + return -ENODEV; + } +found: +#ifndef CONFIG_POWER4 + /* Fixup Hooper vs. Comet */ + if (pmac_mb.model_id == PMAC_TYPE_HOOPER) { + u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4); + if (!mach_id_ptr) + return -ENODEV; + /* Here, I used to disable the media-bay on comet. It + * appears this is wrong, the floppy connector is actually + * a kind of media-bay and works with the current driver. + */ + if (__raw_readl(mach_id_ptr) & 0x20000000UL) + pmac_mb.model_id = PMAC_TYPE_COMET; + iounmap(mach_id_ptr); + } +#endif /* CONFIG_POWER4 */ + +#ifdef CONFIG_6xx + /* Set default value of powersave_nap on machines that support it. + * It appears that uninorth rev 3 has a problem with it, we don't + * enable it on those. In theory, the flush-on-lock property is + * supposed to be set when not supported, but I'm not very confident + * that all Apple OF revs did it properly, I do it the paranoid way. + */ + while (uninorth_base && uninorth_rev > 3) { + struct device_node *np = find_path_device("/cpus"); + if (!np || !np->child) { + printk(KERN_WARNING "Can't find CPU(s) in device tree !\n"); + break; + } + np = np->child; + /* Nap mode not supported on SMP */ + if (np->sibling) + break; + /* Nap mode not supported if flush-on-lock property is present */ + if (get_property(np, "flush-on-lock", NULL)) + break; + powersave_nap = 1; + printk(KERN_INFO "Processor NAP mode on idle enabled.\n"); + break; + } + + /* On CPUs that support it (750FX), lowspeed by default during + * NAP mode + */ + powersave_lowspeed = 1; +#endif /* CONFIG_6xx */ +#ifdef CONFIG_POWER4 + powersave_nap = 1; +#endif + /* Check for "mobile" machine */ + if (model && (strncmp(model, "PowerBook", 9) == 0 + || strncmp(model, "iBook", 5) == 0)) + pmac_mb.board_flags |= PMAC_MB_MOBILE; + + + printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name); + return 0; +} + +/* Initialize the Core99 UniNorth host bridge and memory controller + */ +static void __init probe_uninorth(void) +{ + unsigned long actrl; + + /* Locate core99 Uni-N */ + uninorth_node = of_find_node_by_name(NULL, "uni-n"); + /* Locate G5 u3 */ + if (uninorth_node == NULL) { + uninorth_node = of_find_node_by_name(NULL, "u3"); + uninorth_u3 = 1; + } + if (uninorth_node && uninorth_node->n_addrs > 0) { + unsigned long address = uninorth_node->addrs[0].address; + uninorth_base = ioremap(address, 0x40000); + uninorth_rev = in_be32(UN_REG(UNI_N_VERSION)); + if (uninorth_u3) + u3_ht = ioremap(address + U3_HT_CONFIG_BASE, 0x1000); + } else + uninorth_node = NULL; + + if (!uninorth_node) + return; + + printk(KERN_INFO "Found %s memory controller & host bridge, revision: %d\n", + uninorth_u3 ? "U3" : "UniNorth", uninorth_rev); + printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base); + + /* Set the arbitrer QAck delay according to what Apple does + */ + if (uninorth_rev < 0x11) { + actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK; + actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 : + UNI_N_ARB_CTRL_QACK_DELAY) << UNI_N_ARB_CTRL_QACK_DELAY_SHIFT; + UN_OUT(UNI_N_ARB_CTRL, actrl); + } + + /* Some more magic as done by them in recent MacOS X on UniNorth + * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI + * memory timeout + */ + if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || uninorth_rev == 0xc0) + UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff); +} + +static void __init probe_one_macio(const char *name, const char *compat, int type) +{ + struct device_node* node; + int i; + volatile u32 __iomem * base; + u32* revp; + + node = find_devices(name); + if (!node || !node->n_addrs) + return; + if (compat) + do { + if (device_is_compatible(node, compat)) + break; + node = node->next; + } while (node); + if (!node) + return; + for(i=0; i= MAX_MACIO_CHIPS) { + printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); + printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name); + return; + } + base = ioremap(node->addrs[0].address, node->addrs[0].size); + if (!base) { + printk(KERN_ERR "pmac_feature: Can't map mac-io chip !\n"); + return; + } + if (type == macio_keylargo) { + u32 *did = (u32 *)get_property(node, "device-id", NULL); + if (*did == 0x00000025) + type = macio_pangea; + if (*did == 0x0000003e) + type = macio_intrepid; + } + macio_chips[i].of_node = node; + macio_chips[i].type = type; + macio_chips[i].base = base; + macio_chips[i].flags = MACIO_FLAG_SCCB_ON | MACIO_FLAG_SCCB_ON; + macio_chips[i].name = macio_names[type]; + revp = (u32 *)get_property(node, "revision-id", NULL); + if (revp) + macio_chips[i].rev = *revp; + printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", + macio_names[type], macio_chips[i].rev, macio_chips[i].base); +} + +static int __init +probe_macios(void) +{ + /* Warning, ordering is important */ + probe_one_macio("gc", NULL, macio_grand_central); + probe_one_macio("ohare", NULL, macio_ohare); + probe_one_macio("pci106b,7", NULL, macio_ohareII); + probe_one_macio("mac-io", "keylargo", macio_keylargo); + probe_one_macio("mac-io", "paddington", macio_paddington); + probe_one_macio("mac-io", "gatwick", macio_gatwick); + probe_one_macio("mac-io", "heathrow", macio_heathrow); + probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2); + + /* Make sure the "main" macio chip appear first */ + if (macio_chips[0].type == macio_gatwick + && macio_chips[1].type == macio_heathrow) { + struct macio_chip temp = macio_chips[0]; + macio_chips[0] = macio_chips[1]; + macio_chips[1] = temp; + } + if (macio_chips[0].type == macio_ohareII + && macio_chips[1].type == macio_ohare) { + struct macio_chip temp = macio_chips[0]; + macio_chips[0] = macio_chips[1]; + macio_chips[1] = temp; + } + macio_chips[0].lbus.index = 0; + macio_chips[1].lbus.index = 1; + + return (macio_chips[0].of_node == NULL) ? -ENODEV : 0; +} + +static void __init +initial_serial_shutdown(struct device_node *np) +{ + int len; + struct slot_names_prop { + int count; + char name[1]; + } *slots; + char *conn; + int port_type = PMAC_SCC_ASYNC; + int modem = 0; + + slots = (struct slot_names_prop *)get_property(np, "slot-names", &len); + conn = get_property(np, "AAPL,connector", &len); + if (conn && (strcmp(conn, "infrared") == 0)) + port_type = PMAC_SCC_IRDA; + else if (device_is_compatible(np, "cobalt")) + modem = 1; + else if (slots && slots->count > 0) { + if (strcmp(slots->name, "IrDA") == 0) + port_type = PMAC_SCC_IRDA; + else if (strcmp(slots->name, "Modem") == 0) + modem = 1; + } + if (modem) + pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0); + pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0); +} + +static void __init +set_initial_features(void) +{ + struct device_node *np; + + /* That hack appears to be necessary for some StarMax motherboards + * but I'm not too sure it was audited for side-effects on other + * ohare based machines... + * Since I still have difficulties figuring the right way to + * differenciate them all and since that hack was there for a long + * time, I'll keep it around + */ + if (macio_chips[0].type == macio_ohare && !find_devices("via-pmu")) { + struct macio_chip *macio = &macio_chips[0]; + MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES); + } else if (macio_chips[0].type == macio_ohare) { + struct macio_chip *macio = &macio_chips[0]; + MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); + } else if (macio_chips[1].type == macio_ohare) { + struct macio_chip *macio = &macio_chips[1]; + MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); + } + +#ifdef CONFIG_POWER4 + if (macio_chips[0].type == macio_keylargo2) { +#ifndef CONFIG_SMP + /* On SMP machines running UP, we have the second CPU eating + * bus cycles. We need to take it off the bus. This is done + * from pmac_smp for SMP kernels running on one CPU + */ + np = of_find_node_by_type(NULL, "cpu"); + if (np != NULL) + np = of_find_node_by_type(np, "cpu"); + if (np != NULL) { + g5_phy_disable_cpu1(); + of_node_put(np); + } +#endif /* CONFIG_SMP */ + /* Enable GMAC for now for PCI probing. It will be disabled + * later on after PCI probe + */ + np = of_find_node_by_name(NULL, "ethernet"); + while(np) { + if (device_is_compatible(np, "K2-GMAC")) + g5_gmac_enable(np, 0, 1); + np = of_find_node_by_name(np, "ethernet"); + } + + /* Enable FW before PCI probe. Will be disabled later on + * Note: We should have a batter way to check that we are + * dealing with uninorth internal cell and not a PCI cell + * on the external PCI. The code below works though. + */ + np = of_find_node_by_name(NULL, "firewire"); + while(np) { + if (device_is_compatible(np, "pci106b,5811")) { + macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; + g5_fw_enable(np, 0, 1); + } + np = of_find_node_by_name(np, "firewire"); + } + } +#else /* CONFIG_POWER4 */ + + if (macio_chips[0].type == macio_keylargo || + macio_chips[0].type == macio_pangea || + macio_chips[0].type == macio_intrepid) { + /* Enable GMAC for now for PCI probing. It will be disabled + * later on after PCI probe + */ + np = of_find_node_by_name(NULL, "ethernet"); + while(np) { + if (np->parent + && device_is_compatible(np->parent, "uni-north") + && device_is_compatible(np, "gmac")) + core99_gmac_enable(np, 0, 1); + np = of_find_node_by_name(np, "ethernet"); + } + + /* Enable FW before PCI probe. Will be disabled later on + * Note: We should have a batter way to check that we are + * dealing with uninorth internal cell and not a PCI cell + * on the external PCI. The code below works though. + */ + np = of_find_node_by_name(NULL, "firewire"); + while(np) { + if (np->parent + && device_is_compatible(np->parent, "uni-north") + && (device_is_compatible(np, "pci106b,18") || + device_is_compatible(np, "pci106b,30") || + device_is_compatible(np, "pci11c1,5811"))) { + macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; + core99_firewire_enable(np, 0, 1); + } + np = of_find_node_by_name(np, "firewire"); + } + + /* Enable ATA-100 before PCI probe. */ + np = of_find_node_by_name(NULL, "ata-6"); + while(np) { + if (np->parent + && device_is_compatible(np->parent, "uni-north") + && device_is_compatible(np, "kauai-ata")) { + core99_ata100_enable(np, 1); + } + np = of_find_node_by_name(np, "ata-6"); + } + + /* Switch airport off */ + np = find_devices("radio"); + while(np) { + if (np && np->parent == macio_chips[0].of_node) { + macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON; + core99_airport_enable(np, 0, 0); + } + np = np->next; + } + } + + /* On all machines that support sound PM, switch sound off */ + if (macio_chips[0].of_node) + pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE, + macio_chips[0].of_node, 0, 0); + + /* While on some desktop G3s, we turn it back on */ + if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow + && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER || + pmac_mb.model_id == PMAC_TYPE_SILK)) { + struct macio_chip *macio = &macio_chips[0]; + MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); + MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); + } + + /* Some machine models need the clock chip to be properly setup for + * clock spreading now. This should be a platform function but we + * don't do these at the moment + */ + pmac_tweak_clock_spreading(1); + +#endif /* CONFIG_POWER4 */ + + /* On all machines, switch modem & serial ports off */ + np = find_devices("ch-a"); + while(np) { + initial_serial_shutdown(np); + np = np->next; + } + np = find_devices("ch-b"); + while(np) { + initial_serial_shutdown(np); + np = np->next; + } +} + +void __init +pmac_feature_init(void) +{ + /* Detect the UniNorth memory controller */ + probe_uninorth(); + + /* Probe mac-io controllers */ + if (probe_macios()) { + printk(KERN_WARNING "No mac-io chip found\n"); + return; + } + + /* Setup low-level i2c stuffs */ + pmac_init_low_i2c(); + + /* Probe machine type */ + if (probe_motherboard()) + printk(KERN_WARNING "Unknown PowerMac !\n"); + + /* Set some initial features (turn off some chips that will + * be later turned on) + */ + set_initial_features(); +} + +int __init pmac_feature_late_init(void) +{ +#if 0 + struct device_node *np; + + /* Request some resources late */ + if (uninorth_node) + request_OF_resource(uninorth_node, 0, NULL); + np = find_devices("hammerhead"); + if (np) + request_OF_resource(np, 0, NULL); + np = find_devices("interrupt-controller"); + if (np) + request_OF_resource(np, 0, NULL); +#endif + return 0; +} + +device_initcall(pmac_feature_late_init); + +#if 0 +static void dump_HT_speeds(char *name, u32 cfg, u32 frq) +{ + int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 }; + int bits[8] = { 8,16,0,32,2,4,0,0 }; + int freq = (frq >> 8) & 0xf; + + if (freqs[freq] == 0) + printk("%s: Unknown HT link frequency %x\n", name, freq); + else + printk("%s: %d MHz on main link, (%d in / %d out) bits width\n", + name, freqs[freq], + bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]); +} + +void __init pmac_check_ht_link(void) +{ +#if 0 /* Disabled for now */ + u32 ufreq, freq, ucfg, cfg; + struct device_node *pcix_node; + u8 px_bus, px_devfn; + struct pci_controller *px_hose; + + (void)in_be32(u3_ht + U3_HT_LINK_COMMAND); + ucfg = cfg = in_be32(u3_ht + U3_HT_LINK_CONFIG); + ufreq = freq = in_be32(u3_ht + U3_HT_LINK_FREQ); + dump_HT_speeds("U3 HyperTransport", cfg, freq); + + pcix_node = of_find_compatible_node(NULL, "pci", "pci-x"); + if (pcix_node == NULL) { + printk("No PCI-X bridge found\n"); + return; + } + if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) { + printk("PCI-X bridge found but not matched to pci\n"); + return; + } + px_hose = pci_find_hose_for_OF_device(pcix_node); + if (px_hose == NULL) { + printk("PCI-X bridge found but not matched to host\n"); + return; + } + early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg); + early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq); + dump_HT_speeds("PCI-X HT Uplink", cfg, freq); + early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg); + early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq); + dump_HT_speeds("PCI-X HT Downlink", cfg, freq); +#endif +} + +#endif /* CONFIG_POWER4 */ + +/* + * Early video resume hook + */ + +static void (*pmac_early_vresume_proc)(void *data); +static void *pmac_early_vresume_data; + +void pmac_set_early_video_resume(void (*proc)(void *data), void *data) +{ + if (_machine != _MACH_Pmac) + return; + preempt_disable(); + pmac_early_vresume_proc = proc; + pmac_early_vresume_data = data; + preempt_enable(); +} +EXPORT_SYMBOL(pmac_set_early_video_resume); + +void pmac_call_early_video_resume(void) +{ + if (pmac_early_vresume_proc) + pmac_early_vresume_proc(pmac_early_vresume_data); +} + +/* + * AGP related suspend/resume code + */ + +static struct pci_dev *pmac_agp_bridge; +static int (*pmac_agp_suspend)(struct pci_dev *bridge); +static int (*pmac_agp_resume)(struct pci_dev *bridge); + +void pmac_register_agp_pm(struct pci_dev *bridge, + int (*suspend)(struct pci_dev *bridge), + int (*resume)(struct pci_dev *bridge)) +{ + if (suspend || resume) { + pmac_agp_bridge = bridge; + pmac_agp_suspend = suspend; + pmac_agp_resume = resume; + return; + } + if (bridge != pmac_agp_bridge) + return; + pmac_agp_suspend = pmac_agp_resume = NULL; + return; +} +EXPORT_SYMBOL(pmac_register_agp_pm); + +void pmac_suspend_agp_for_card(struct pci_dev *dev) +{ + if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) + return; + if (pmac_agp_bridge->bus != dev->bus) + return; + pmac_agp_suspend(pmac_agp_bridge); +} +EXPORT_SYMBOL(pmac_suspend_agp_for_card); + +void pmac_resume_agp_for_card(struct pci_dev *dev) +{ + if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) + return; + if (pmac_agp_bridge->bus != dev->bus) + return; + pmac_agp_resume(pmac_agp_bridge); +} +EXPORT_SYMBOL(pmac_resume_agp_for_card); diff --git a/arch/powerpc/platforms/powermac/pmac_low_i2c.c b/arch/powerpc/platforms/powermac/pmac_low_i2c.c new file mode 100644 index 00000000000..f3f39e8e337 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_low_i2c.c @@ -0,0 +1,523 @@ +/* + * arch/ppc/platforms/pmac_low_i2c.c + * + * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * This file contains some low-level i2c access routines that + * need to be used by various bits of the PowerMac platform code + * at times where the real asynchronous & interrupt driven driver + * cannot be used. The API borrows some semantics from the darwin + * driver in order to ease the implementation of the platform + * properties parser + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_LOW_I2C_HOST 4 + +#ifdef DEBUG +#define DBG(x...) do {\ + printk(KERN_DEBUG "KW:" x); \ + } while(0) +#else +#define DBG(x...) +#endif + +struct low_i2c_host; + +typedef int (*low_i2c_func_t)(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len); + +struct low_i2c_host +{ + struct device_node *np; /* OF device node */ + struct semaphore mutex; /* Access mutex for use by i2c-keywest */ + low_i2c_func_t func; /* Access function */ + unsigned int is_open : 1; /* Poor man's access control */ + int mode; /* Current mode */ + int channel; /* Current channel */ + int num_channels; /* Number of channels */ + void __iomem *base; /* For keywest-i2c, base address */ + int bsteps; /* And register stepping */ + int speed; /* And speed */ +}; + +static struct low_i2c_host low_i2c_hosts[MAX_LOW_I2C_HOST]; + +/* No locking is necessary on allocation, we are running way before + * anything can race with us + */ +static struct low_i2c_host *find_low_i2c_host(struct device_node *np) +{ + int i; + + for (i = 0; i < MAX_LOW_I2C_HOST; i++) + if (low_i2c_hosts[i].np == np) + return &low_i2c_hosts[i]; + return NULL; +} + +/* + * + * i2c-keywest implementation (UniNorth, U2, U3, Keylargo's) + * + */ + +/* + * Keywest i2c definitions borrowed from drivers/i2c/i2c-keywest.h, + * should be moved somewhere in include/asm-ppc/ + */ +/* Register indices */ +typedef enum { + reg_mode = 0, + reg_control, + reg_status, + reg_isr, + reg_ier, + reg_addr, + reg_subaddr, + reg_data +} reg_t; + + +/* Mode register */ +#define KW_I2C_MODE_100KHZ 0x00 +#define KW_I2C_MODE_50KHZ 0x01 +#define KW_I2C_MODE_25KHZ 0x02 +#define KW_I2C_MODE_DUMB 0x00 +#define KW_I2C_MODE_STANDARD 0x04 +#define KW_I2C_MODE_STANDARDSUB 0x08 +#define KW_I2C_MODE_COMBINED 0x0C +#define KW_I2C_MODE_MODE_MASK 0x0C +#define KW_I2C_MODE_CHAN_MASK 0xF0 + +/* Control register */ +#define KW_I2C_CTL_AAK 0x01 +#define KW_I2C_CTL_XADDR 0x02 +#define KW_I2C_CTL_STOP 0x04 +#define KW_I2C_CTL_START 0x08 + +/* Status register */ +#define KW_I2C_STAT_BUSY 0x01 +#define KW_I2C_STAT_LAST_AAK 0x02 +#define KW_I2C_STAT_LAST_RW 0x04 +#define KW_I2C_STAT_SDA 0x08 +#define KW_I2C_STAT_SCL 0x10 + +/* IER & ISR registers */ +#define KW_I2C_IRQ_DATA 0x01 +#define KW_I2C_IRQ_ADDR 0x02 +#define KW_I2C_IRQ_STOP 0x04 +#define KW_I2C_IRQ_START 0x08 +#define KW_I2C_IRQ_MASK 0x0F + +/* State machine states */ +enum { + state_idle, + state_addr, + state_read, + state_write, + state_stop, + state_dead +}; + +#define WRONG_STATE(name) do {\ + printk(KERN_DEBUG "KW: wrong state. Got %s, state: %s (isr: %02x)\n", \ + name, __kw_state_names[state], isr); \ + } while(0) + +static const char *__kw_state_names[] = { + "state_idle", + "state_addr", + "state_read", + "state_write", + "state_stop", + "state_dead" +}; + +static inline u8 __kw_read_reg(struct low_i2c_host *host, reg_t reg) +{ + return readb(host->base + (((unsigned int)reg) << host->bsteps)); +} + +static inline void __kw_write_reg(struct low_i2c_host *host, reg_t reg, u8 val) +{ + writeb(val, host->base + (((unsigned)reg) << host->bsteps)); + (void)__kw_read_reg(host, reg_subaddr); +} + +#define kw_write_reg(reg, val) __kw_write_reg(host, reg, val) +#define kw_read_reg(reg) __kw_read_reg(host, reg) + + +/* Don't schedule, the g5 fan controller is too + * timing sensitive + */ +static u8 kw_wait_interrupt(struct low_i2c_host* host) +{ + int i, j; + u8 isr; + + for (i = 0; i < 100000; i++) { + isr = kw_read_reg(reg_isr) & KW_I2C_IRQ_MASK; + if (isr != 0) + return isr; + + /* This code is used with the timebase frozen, we cannot rely + * on udelay ! For now, just use a bogus loop + */ + for (j = 1; j < 10000; j++) + mb(); + } + return isr; +} + +static int kw_handle_interrupt(struct low_i2c_host *host, int state, int rw, int *rc, u8 **data, int *len, u8 isr) +{ + u8 ack; + + DBG("kw_handle_interrupt(%s, isr: %x)\n", __kw_state_names[state], isr); + + if (isr == 0) { + if (state != state_stop) { + DBG("KW: Timeout !\n"); + *rc = -EIO; + goto stop; + } + if (state == state_stop) { + ack = kw_read_reg(reg_status); + if (!(ack & KW_I2C_STAT_BUSY)) { + state = state_idle; + kw_write_reg(reg_ier, 0x00); + } + } + return state; + } + + if (isr & KW_I2C_IRQ_ADDR) { + ack = kw_read_reg(reg_status); + if (state != state_addr) { + kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR); + WRONG_STATE("KW_I2C_IRQ_ADDR"); + *rc = -EIO; + goto stop; + } + if ((ack & KW_I2C_STAT_LAST_AAK) == 0) { + *rc = -ENODEV; + DBG("KW: NAK on address\n"); + return state_stop; + } else { + if (rw) { + state = state_read; + if (*len > 1) + kw_write_reg(reg_control, KW_I2C_CTL_AAK); + } else { + state = state_write; + kw_write_reg(reg_data, **data); + (*data)++; (*len)--; + } + } + kw_write_reg(reg_isr, KW_I2C_IRQ_ADDR); + } + + if (isr & KW_I2C_IRQ_DATA) { + if (state == state_read) { + **data = kw_read_reg(reg_data); + (*data)++; (*len)--; + kw_write_reg(reg_isr, KW_I2C_IRQ_DATA); + if ((*len) == 0) + state = state_stop; + else if ((*len) == 1) + kw_write_reg(reg_control, 0); + } else if (state == state_write) { + ack = kw_read_reg(reg_status); + if ((ack & KW_I2C_STAT_LAST_AAK) == 0) { + DBG("KW: nack on data write\n"); + *rc = -EIO; + goto stop; + } else if (*len) { + kw_write_reg(reg_data, **data); + (*data)++; (*len)--; + } else { + kw_write_reg(reg_control, KW_I2C_CTL_STOP); + state = state_stop; + *rc = 0; + } + kw_write_reg(reg_isr, KW_I2C_IRQ_DATA); + } else { + kw_write_reg(reg_isr, KW_I2C_IRQ_DATA); + WRONG_STATE("KW_I2C_IRQ_DATA"); + if (state != state_stop) { + *rc = -EIO; + goto stop; + } + } + } + + if (isr & KW_I2C_IRQ_STOP) { + kw_write_reg(reg_isr, KW_I2C_IRQ_STOP); + if (state != state_stop) { + WRONG_STATE("KW_I2C_IRQ_STOP"); + *rc = -EIO; + } + return state_idle; + } + + if (isr & KW_I2C_IRQ_START) + kw_write_reg(reg_isr, KW_I2C_IRQ_START); + + return state; + + stop: + kw_write_reg(reg_control, KW_I2C_CTL_STOP); + return state_stop; +} + +static int keywest_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 subaddr, u8 *data, int len) +{ + u8 mode_reg = host->speed; + int state = state_addr; + int rc = 0; + + /* Setup mode & subaddress if any */ + switch(host->mode) { + case pmac_low_i2c_mode_dumb: + printk(KERN_ERR "low_i2c: Dumb mode not supported !\n"); + return -EINVAL; + case pmac_low_i2c_mode_std: + mode_reg |= KW_I2C_MODE_STANDARD; + break; + case pmac_low_i2c_mode_stdsub: + mode_reg |= KW_I2C_MODE_STANDARDSUB; + break; + case pmac_low_i2c_mode_combined: + mode_reg |= KW_I2C_MODE_COMBINED; + break; + } + + /* Setup channel & clear pending irqs */ + kw_write_reg(reg_isr, kw_read_reg(reg_isr)); + kw_write_reg(reg_mode, mode_reg | (host->channel << 4)); + kw_write_reg(reg_status, 0); + + /* Set up address and r/w bit */ + kw_write_reg(reg_addr, addr); + + /* Set up the sub address */ + if ((mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB + || (mode_reg & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED) + kw_write_reg(reg_subaddr, subaddr); + + /* Start sending address & disable interrupt*/ + kw_write_reg(reg_ier, 0 /*KW_I2C_IRQ_MASK*/); + kw_write_reg(reg_control, KW_I2C_CTL_XADDR); + + /* State machine, to turn into an interrupt handler */ + while(state != state_idle) { + u8 isr = kw_wait_interrupt(host); + state = kw_handle_interrupt(host, state, addr & 1, &rc, &data, &len, isr); + } + + return rc; +} + +static void keywest_low_i2c_add(struct device_node *np) +{ + struct low_i2c_host *host = find_low_i2c_host(NULL); + u32 *psteps, *prate, steps, aoffset = 0; + struct device_node *parent; + + if (host == NULL) { + printk(KERN_ERR "low_i2c: Can't allocate host for %s\n", + np->full_name); + return; + } + memset(host, 0, sizeof(*host)); + + init_MUTEX(&host->mutex); + host->np = of_node_get(np); + psteps = (u32 *)get_property(np, "AAPL,address-step", NULL); + steps = psteps ? (*psteps) : 0x10; + for (host->bsteps = 0; (steps & 0x01) == 0; host->bsteps++) + steps >>= 1; + parent = of_get_parent(np); + host->num_channels = 1; + if (parent && parent->name[0] == 'u') { + host->num_channels = 2; + aoffset = 3; + } + /* Select interface rate */ + host->speed = KW_I2C_MODE_100KHZ; + prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL); + if (prate) switch(*prate) { + case 100: + host->speed = KW_I2C_MODE_100KHZ; + break; + case 50: + host->speed = KW_I2C_MODE_50KHZ; + break; + case 25: + host->speed = KW_I2C_MODE_25KHZ; + break; + } + + host->mode = pmac_low_i2c_mode_std; + host->base = ioremap(np->addrs[0].address + aoffset, + np->addrs[0].size); + host->func = keywest_low_i2c_func; +} + +/* + * + * PMU implementation + * + */ + + +#ifdef CONFIG_ADB_PMU + +static int pmu_low_i2c_func(struct low_i2c_host *host, u8 addr, u8 sub, u8 *data, int len) +{ + // TODO + return -ENODEV; +} + +static void pmu_low_i2c_add(struct device_node *np) +{ + struct low_i2c_host *host = find_low_i2c_host(NULL); + + if (host == NULL) { + printk(KERN_ERR "low_i2c: Can't allocate host for %s\n", + np->full_name); + return; + } + memset(host, 0, sizeof(*host)); + + init_MUTEX(&host->mutex); + host->np = of_node_get(np); + host->num_channels = 3; + host->mode = pmac_low_i2c_mode_std; + host->func = pmu_low_i2c_func; +} + +#endif /* CONFIG_ADB_PMU */ + +void __init pmac_init_low_i2c(void) +{ + struct device_node *np; + + /* Probe keywest-i2c busses */ + np = of_find_compatible_node(NULL, "i2c", "keywest-i2c"); + while(np) { + keywest_low_i2c_add(np); + np = of_find_compatible_node(np, "i2c", "keywest-i2c"); + } + +#ifdef CONFIG_ADB_PMU + /* Probe PMU busses */ + np = of_find_node_by_name(NULL, "via-pmu"); + if (np) + pmu_low_i2c_add(np); +#endif /* CONFIG_ADB_PMU */ + + /* TODO: Add CUDA support as well */ +} + +int pmac_low_i2c_lock(struct device_node *np) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + down(&host->mutex); + return 0; +} +EXPORT_SYMBOL(pmac_low_i2c_lock); + +int pmac_low_i2c_unlock(struct device_node *np) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + up(&host->mutex); + return 0; +} +EXPORT_SYMBOL(pmac_low_i2c_unlock); + + +int pmac_low_i2c_open(struct device_node *np, int channel) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + + if (channel >= host->num_channels) + return -EINVAL; + + down(&host->mutex); + host->is_open = 1; + host->channel = channel; + + return 0; +} +EXPORT_SYMBOL(pmac_low_i2c_open); + +int pmac_low_i2c_close(struct device_node *np) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + + host->is_open = 0; + up(&host->mutex); + + return 0; +} +EXPORT_SYMBOL(pmac_low_i2c_close); + +int pmac_low_i2c_setmode(struct device_node *np, int mode) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + WARN_ON(!host->is_open); + host->mode = mode; + + return 0; +} +EXPORT_SYMBOL(pmac_low_i2c_setmode); + +int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len) +{ + struct low_i2c_host *host = find_low_i2c_host(np); + + if (!host) + return -ENODEV; + WARN_ON(!host->is_open); + + return host->func(host, addrdir, subaddr, data, len); +} +EXPORT_SYMBOL(pmac_low_i2c_xfer); + diff --git a/arch/powerpc/platforms/powermac/pmac_nvram.c b/arch/powerpc/platforms/powermac/pmac_nvram.c new file mode 100644 index 00000000000..8c9b008c722 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_nvram.c @@ -0,0 +1,584 @@ +/* + * arch/ppc/platforms/pmac_nvram.c + * + * Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Todo: - add support for the OF persistent properties + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +#define NVRAM_SIZE 0x2000 /* 8kB of non-volatile RAM */ + +#define CORE99_SIGNATURE 0x5a +#define CORE99_ADLER_START 0x14 + +/* On Core99, nvram is either a sharp, a micron or an AMD flash */ +#define SM_FLASH_STATUS_DONE 0x80 +#define SM_FLASH_STATUS_ERR 0x38 +#define SM_FLASH_CMD_ERASE_CONFIRM 0xd0 +#define SM_FLASH_CMD_ERASE_SETUP 0x20 +#define SM_FLASH_CMD_RESET 0xff +#define SM_FLASH_CMD_WRITE_SETUP 0x40 +#define SM_FLASH_CMD_CLEAR_STATUS 0x50 +#define SM_FLASH_CMD_READ_STATUS 0x70 + +/* CHRP NVRAM header */ +struct chrp_header { + u8 signature; + u8 cksum; + u16 len; + char name[12]; + u8 data[0]; +}; + +struct core99_header { + struct chrp_header hdr; + u32 adler; + u32 generation; + u32 reserved[2]; +}; + +/* + * Read and write the non-volatile RAM on PowerMacs and CHRP machines. + */ +static int nvram_naddrs; +static volatile unsigned char *nvram_addr; +static volatile unsigned char *nvram_data; +static int nvram_mult, is_core_99; +static int core99_bank = 0; +static int nvram_partitions[3]; +static DEFINE_SPINLOCK(nv_lock); + +extern int pmac_newworld; +extern int system_running; + +static int (*core99_write_bank)(int bank, u8* datas); +static int (*core99_erase_bank)(int bank); + +static char *nvram_image; + + +static unsigned char core99_nvram_read_byte(int addr) +{ + if (nvram_image == NULL) + return 0xff; + return nvram_image[addr]; +} + +static void core99_nvram_write_byte(int addr, unsigned char val) +{ + if (nvram_image == NULL) + return; + nvram_image[addr] = val; +} + + +static unsigned char direct_nvram_read_byte(int addr) +{ + return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]); +} + +static void direct_nvram_write_byte(int addr, unsigned char val) +{ + out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val); +} + + +static unsigned char indirect_nvram_read_byte(int addr) +{ + unsigned char val; + unsigned long flags; + + spin_lock_irqsave(&nv_lock, flags); + out_8(nvram_addr, addr >> 5); + val = in_8(&nvram_data[(addr & 0x1f) << 4]); + spin_unlock_irqrestore(&nv_lock, flags); + + return val; +} + +static void indirect_nvram_write_byte(int addr, unsigned char val) +{ + unsigned long flags; + + spin_lock_irqsave(&nv_lock, flags); + out_8(nvram_addr, addr >> 5); + out_8(&nvram_data[(addr & 0x1f) << 4], val); + spin_unlock_irqrestore(&nv_lock, flags); +} + + +#ifdef CONFIG_ADB_PMU + +static void pmu_nvram_complete(struct adb_request *req) +{ + if (req->arg) + complete((struct completion *)req->arg); +} + +static unsigned char pmu_nvram_read_byte(int addr) +{ + struct adb_request req; + DECLARE_COMPLETION(req_complete); + + req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL; + if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM, + (addr >> 8) & 0xff, addr & 0xff)) + return 0xff; + if (system_state == SYSTEM_RUNNING) + wait_for_completion(&req_complete); + while (!req.complete) + pmu_poll(); + return req.reply[0]; +} + +static void pmu_nvram_write_byte(int addr, unsigned char val) +{ + struct adb_request req; + DECLARE_COMPLETION(req_complete); + + req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL; + if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM, + (addr >> 8) & 0xff, addr & 0xff, val)) + return; + if (system_state == SYSTEM_RUNNING) + wait_for_completion(&req_complete); + while (!req.complete) + pmu_poll(); +} + +#endif /* CONFIG_ADB_PMU */ + + +static u8 chrp_checksum(struct chrp_header* hdr) +{ + u8 *ptr; + u16 sum = hdr->signature; + for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++) + sum += *ptr; + while (sum > 0xFF) + sum = (sum & 0xFF) + (sum>>8); + return sum; +} + +static u32 core99_calc_adler(u8 *buffer) +{ + int cnt; + u32 low, high; + + buffer += CORE99_ADLER_START; + low = 1; + high = 0; + for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) { + if ((cnt % 5000) == 0) { + high %= 65521UL; + high %= 65521UL; + } + low += buffer[cnt]; + high += low; + } + low %= 65521UL; + high %= 65521UL; + + return (high << 16) | low; +} + +static u32 core99_check(u8* datas) +{ + struct core99_header* hdr99 = (struct core99_header*)datas; + + if (hdr99->hdr.signature != CORE99_SIGNATURE) { + DBG("Invalid signature\n"); + return 0; + } + if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) { + DBG("Invalid checksum\n"); + return 0; + } + if (hdr99->adler != core99_calc_adler(datas)) { + DBG("Invalid adler\n"); + return 0; + } + return hdr99->generation; +} + +static int sm_erase_bank(int bank) +{ + int stat, i; + unsigned long timeout; + + u8* base = (u8 *)nvram_data + core99_bank*NVRAM_SIZE; + + DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank); + + out_8(base, SM_FLASH_CMD_ERASE_SETUP); + out_8(base, SM_FLASH_CMD_ERASE_CONFIRM); + timeout = 0; + do { + if (++timeout > 1000000) { + printk(KERN_ERR "nvram: Sharp/Miron flash erase timeout !\n"); + break; + } + out_8(base, SM_FLASH_CMD_READ_STATUS); + stat = in_8(base); + } while (!(stat & SM_FLASH_STATUS_DONE)); + + out_8(base, SM_FLASH_CMD_CLEAR_STATUS); + out_8(base, SM_FLASH_CMD_RESET); + + for (i=0; i 1000000) { + printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n"); + break; + } + out_8(base, SM_FLASH_CMD_READ_STATUS); + stat = in_8(base); + } while (!(stat & SM_FLASH_STATUS_DONE)); + if (!(stat & SM_FLASH_STATUS_DONE)) + break; + } + out_8(base, SM_FLASH_CMD_CLEAR_STATUS); + out_8(base, SM_FLASH_CMD_RESET); + for (i=0; i 1000000) { + printk(KERN_ERR "nvram: AMD flash erase timeout !\n"); + break; + } + stat = in_8(base) ^ in_8(base); + } while (stat != 0); + + /* Reset */ + out_8(base, 0xf0); + udelay(1); + + for (i=0; i 1000000) { + printk(KERN_ERR "nvram: AMD flash write timeout !\n"); + break; + } + stat = in_8(base) ^ in_8(base); + } while (stat != 0); + if (stat != 0) + break; + } + + /* Reset */ + out_8(base, 0xf0); + udelay(1); + + for (i=0; iname, "common")) + nvram_partitions[pmac_nvram_OF] = offset + 0x10; + if (!strcmp(hdr->name, "APL,MacOS75")) { + nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10; + nvram_partitions[pmac_nvram_NR] = offset + 0x110; + } + offset += (hdr->len * 0x10); + } while(offset < NVRAM_SIZE); + } else { + nvram_partitions[pmac_nvram_OF] = 0x1800; + nvram_partitions[pmac_nvram_XPRAM] = 0x1300; + nvram_partitions[pmac_nvram_NR] = 0x1400; + } + DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]); + DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]); + DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]); +} + +static void core99_nvram_sync(void) +{ + struct core99_header* hdr99; + unsigned long flags; + + if (!is_core_99 || !nvram_data || !nvram_image) + return; + + spin_lock_irqsave(&nv_lock, flags); + if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE, + NVRAM_SIZE)) + goto bail; + + DBG("Updating nvram...\n"); + + hdr99 = (struct core99_header*)nvram_image; + hdr99->generation++; + hdr99->hdr.signature = CORE99_SIGNATURE; + hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr); + hdr99->adler = core99_calc_adler(nvram_image); + core99_bank = core99_bank ? 0 : 1; + if (core99_erase_bank) + if (core99_erase_bank(core99_bank)) { + printk("nvram: Error erasing bank %d\n", core99_bank); + goto bail; + } + if (core99_write_bank) + if (core99_write_bank(core99_bank, nvram_image)) + printk("nvram: Error writing bank %d\n", core99_bank); + bail: + spin_unlock_irqrestore(&nv_lock, flags); + +#ifdef DEBUG + mdelay(2000); +#endif +} + +void __init pmac_nvram_init(void) +{ + struct device_node *dp; + + nvram_naddrs = 0; + + dp = find_devices("nvram"); + if (dp == NULL) { + printk(KERN_ERR "Can't find NVRAM device\n"); + return; + } + nvram_naddrs = dp->n_addrs; + is_core_99 = device_is_compatible(dp, "nvram,flash"); + if (is_core_99) { + int i; + u32 gen_bank0, gen_bank1; + + if (nvram_naddrs < 1) { + printk(KERN_ERR "nvram: no address\n"); + return; + } + nvram_image = alloc_bootmem(NVRAM_SIZE); + if (nvram_image == NULL) { + printk(KERN_ERR "nvram: can't allocate ram image\n"); + return; + } + nvram_data = ioremap(dp->addrs[0].address, NVRAM_SIZE*2); + nvram_naddrs = 1; /* Make sure we get the correct case */ + + DBG("nvram: Checking bank 0...\n"); + + gen_bank0 = core99_check((u8 *)nvram_data); + gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE); + core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0; + + DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1); + DBG("nvram: Active bank is: %d\n", core99_bank); + + for (i=0; iaddrs[0].address + isa_mem_base, + dp->addrs[0].size); + nvram_mult = 1; + ppc_md.nvram_read_val = direct_nvram_read_byte; + ppc_md.nvram_write_val = direct_nvram_write_byte; + } else if (nvram_naddrs == 1) { + nvram_data = ioremap(dp->addrs[0].address, dp->addrs[0].size); + nvram_mult = (dp->addrs[0].size + NVRAM_SIZE - 1) / NVRAM_SIZE; + ppc_md.nvram_read_val = direct_nvram_read_byte; + ppc_md.nvram_write_val = direct_nvram_write_byte; + } else if (nvram_naddrs == 2) { + nvram_addr = ioremap(dp->addrs[0].address, dp->addrs[0].size); + nvram_data = ioremap(dp->addrs[1].address, dp->addrs[1].size); + ppc_md.nvram_read_val = indirect_nvram_read_byte; + ppc_md.nvram_write_val = indirect_nvram_write_byte; + } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) { +#ifdef CONFIG_ADB_PMU + nvram_naddrs = -1; + ppc_md.nvram_read_val = pmu_nvram_read_byte; + ppc_md.nvram_write_val = pmu_nvram_write_byte; +#endif /* CONFIG_ADB_PMU */ + } else { + printk(KERN_ERR "Don't know how to access NVRAM with %d addresses\n", + nvram_naddrs); + } + lookup_partitions(); +} + +int pmac_get_partition(int partition) +{ + return nvram_partitions[partition]; +} + +u8 pmac_xpram_read(int xpaddr) +{ + int offset = nvram_partitions[pmac_nvram_XPRAM]; + + if (offset < 0) + return 0xff; + + return ppc_md.nvram_read_val(xpaddr + offset); +} + +void pmac_xpram_write(int xpaddr, u8 data) +{ + int offset = nvram_partitions[pmac_nvram_XPRAM]; + + if (offset < 0) + return; + + ppc_md.nvram_write_val(xpaddr + offset, data); +} + +EXPORT_SYMBOL(pmac_get_partition); +EXPORT_SYMBOL(pmac_xpram_read); +EXPORT_SYMBOL(pmac_xpram_write); diff --git a/arch/powerpc/platforms/powermac/pmac_pci.c b/arch/powerpc/platforms/powermac/pmac_pci.c new file mode 100644 index 00000000000..40bcd3e55af --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_pci.c @@ -0,0 +1,1341 @@ +/* + * Support for PCI bridges found on Power Macintoshes. + * At present the "bandit" and "chaos" bridges are supported. + * Fortunately you access configuration space in the same + * way with either bridge. + * + * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org) + * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#undef DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + +static int add_bridge(struct device_node *dev); +extern void pmac_check_ht_link(void); + +/* XXX Could be per-controller, but I don't think we risk anything by + * assuming we won't have both UniNorth and Bandit */ +static int has_uninorth; +#ifdef CONFIG_POWER4 +static struct pci_controller *u3_agp; +#endif /* CONFIG_POWER4 */ + +extern u8 pci_cache_line_size; +extern int pcibios_assign_bus_offset; + +struct device_node *k2_skiplist[2]; + +/* + * Magic constants for enabling cache coherency in the bandit/PSX bridge. + */ +#define BANDIT_DEVID_2 8 +#define BANDIT_REVID 3 + +#define BANDIT_DEVNUM 11 +#define BANDIT_MAGIC 0x50 +#define BANDIT_COHERENT 0x40 + +static int __init fixup_one_level_bus_range(struct device_node *node, int higher) +{ + for (; node != 0;node = node->sibling) { + int * bus_range; + unsigned int *class_code; + int len; + + /* For PCI<->PCI bridges or CardBus bridges, we go down */ + class_code = (unsigned int *) get_property(node, "class-code", NULL); + if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && + (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) + continue; + bus_range = (int *) get_property(node, "bus-range", &len); + if (bus_range != NULL && len > 2 * sizeof(int)) { + if (bus_range[1] > higher) + higher = bus_range[1]; + } + higher = fixup_one_level_bus_range(node->child, higher); + } + return higher; +} + +/* This routine fixes the "bus-range" property of all bridges in the + * system since they tend to have their "last" member wrong on macs + * + * Note that the bus numbers manipulated here are OF bus numbers, they + * are not Linux bus numbers. + */ +static void __init fixup_bus_range(struct device_node *bridge) +{ + int * bus_range; + int len; + + /* Lookup the "bus-range" property for the hose */ + bus_range = (int *) get_property(bridge, "bus-range", &len); + if (bus_range == NULL || len < 2 * sizeof(int)) { + printk(KERN_WARNING "Can't get bus-range for %s\n", + bridge->full_name); + return; + } + bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); +} + +/* + * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. + * + * The "Bandit" version is present in all early PCI PowerMacs, + * and up to the first ones using Grackle. Some machines may + * have 2 bandit controllers (2 PCI busses). + * + * "Chaos" is used in some "Bandit"-type machines as a bridge + * for the separate display bus. It is accessed the same + * way as bandit, but cannot be probed for devices. It therefore + * has its own config access functions. + * + * The "UniNorth" version is present in all Core99 machines + * (iBook, G4, new IMacs, and all the recent Apple machines). + * It contains 3 controllers in one ASIC. + * + * The U3 is the bridge used on G5 machines. It contains an + * AGP bus which is dealt with the old UniNorth access routines + * and a HyperTransport bus which uses its own set of access + * functions. + */ + +#define MACRISC_CFA0(devfn, off) \ + ((1 << (unsigned long)PCI_SLOT(dev_fn)) \ + | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \ + | (((unsigned long)(off)) & 0xFCUL)) + +#define MACRISC_CFA1(bus, devfn, off) \ + ((((unsigned long)(bus)) << 16) \ + |(((unsigned long)(devfn)) << 8) \ + |(((unsigned long)(off)) & 0xFCUL) \ + |1UL) + +static unsigned long macrisc_cfg_access(struct pci_controller* hose, + u8 bus, u8 dev_fn, u8 offset) +{ + unsigned int caddr; + + if (bus == hose->first_busno) { + if (dev_fn < (11 << 3)) + return 0; + caddr = MACRISC_CFA0(dev_fn, offset); + } else + caddr = MACRISC_CFA1(bus, dev_fn, offset); + + /* Uninorth will return garbage if we don't read back the value ! */ + do { + out_le32(hose->cfg_addr, caddr); + } while (in_le32(hose->cfg_addr) != caddr); + + offset &= has_uninorth ? 0x07 : 0x03; + return ((unsigned long)hose->cfg_data) + offset; +} + +static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = bus->sysdata; + unsigned long addr; + + addr = macrisc_cfg_access(hose, bus->number, devfn, offset); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + switch (len) { + case 1: + *val = in_8((u8 *)addr); + break; + case 2: + *val = in_le16((u16 *)addr); + break; + default: + *val = in_le32((u32 *)addr); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) +{ + struct pci_controller *hose = bus->sysdata; + unsigned long addr; + + addr = macrisc_cfg_access(hose, bus->number, devfn, offset); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + switch (len) { + case 1: + out_8((u8 *)addr, val); + (void) in_8((u8 *)addr); + break; + case 2: + out_le16((u16 *)addr, val); + (void) in_le16((u16 *)addr); + break; + default: + out_le32((u32 *)addr, val); + (void) in_le32((u32 *)addr); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops macrisc_pci_ops = +{ + macrisc_read_config, + macrisc_write_config +}; + +/* + * Verifiy that a specific (bus, dev_fn) exists on chaos + */ +static int +chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) +{ + struct device_node *np; + u32 *vendor, *device; + + np = pci_busdev_to_OF_node(bus, devfn); + if (np == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; + + vendor = (u32 *)get_property(np, "vendor-id", NULL); + device = (u32 *)get_property(np, "device-id", NULL); + if (vendor == NULL || device == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; + + if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) + && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + return PCIBIOS_SUCCESSFUL; +} + +static int +chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 *val) +{ + int result = chaos_validate_dev(bus, devfn, offset); + if (result == PCIBIOS_BAD_REGISTER_NUMBER) + *val = ~0U; + if (result != PCIBIOS_SUCCESSFUL) + return result; + return macrisc_read_config(bus, devfn, offset, len, val); +} + +static int +chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 val) +{ + int result = chaos_validate_dev(bus, devfn, offset); + if (result != PCIBIOS_SUCCESSFUL) + return result; + return macrisc_write_config(bus, devfn, offset, len, val); +} + +static struct pci_ops chaos_pci_ops = +{ + chaos_read_config, + chaos_write_config +}; + +#ifdef CONFIG_POWER4 + +/* + * These versions of U3 HyperTransport config space access ops do not + * implement self-view of the HT host yet + */ + +/* + * This function deals with some "special cases" devices. + * + * 0 -> No special case + * 1 -> Skip the device but act as if the access was successfull + * (return 0xff's on reads, eventually, cache config space + * accesses in a later version) + * -1 -> Hide the device (unsuccessful acess) + */ +static int u3_ht_skip_device(struct pci_controller *hose, + struct pci_bus *bus, unsigned int devfn) +{ + struct device_node *busdn, *dn; + int i; + + /* We only allow config cycles to devices that are in OF device-tree + * as we are apparently having some weird things going on with some + * revs of K2 on recent G5s + */ + if (bus->self) + busdn = pci_device_to_OF_node(bus->self); + else + busdn = hose->arch_data; + for (dn = busdn->child; dn; dn = dn->sibling) + if (dn->data && PCI_DN(dn)->devfn == devfn) + break; + if (dn == NULL) + return -1; + + /* + * When a device in K2 is powered down, we die on config + * cycle accesses. Fix that here. + */ + for (i=0; i<2; i++) + if (k2_skiplist[i] == dn) + return 1; + + return 0; +} + +#define U3_HT_CFA0(devfn, off) \ + ((((unsigned long)devfn) << 8) | offset) +#define U3_HT_CFA1(bus, devfn, off) \ + (U3_HT_CFA0(devfn, off) \ + + (((unsigned long)bus) << 16) \ + + 0x01000000UL) + +static unsigned long u3_ht_cfg_access(struct pci_controller* hose, + u8 bus, u8 devfn, u8 offset) +{ + if (bus == hose->first_busno) { + /* For now, we don't self probe U3 HT bridge */ + if (PCI_SLOT(devfn) == 0) + return 0; + return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset); + } else + return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset); +} + +static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 *val) +{ + struct pci_controller *hose = bus->sysdata; + unsigned long addr; + + struct device_node *np = pci_busdev_to_OF_node(bus, devfn); + if (np == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + + switch (u3_ht_skip_device(hose, bus, devfn)) { + case 0: + break; + case 1: + switch (len) { + case 1: + *val = 0xff; break; + case 2: + *val = 0xffff; break; + default: + *val = 0xfffffffful; break; + } + return PCIBIOS_SUCCESSFUL; + default: + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + switch (len) { + case 1: + *val = in_8((u8 *)addr); + break; + case 2: + *val = in_le16((u16 *)addr); + break; + default: + *val = in_le32((u32 *)addr); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, + int offset, int len, u32 val) +{ + struct pci_controller *hose = bus->sysdata; + unsigned long addr; + + struct device_node *np = pci_busdev_to_OF_node(bus, devfn); + if (np == NULL) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + + switch (u3_ht_skip_device(hose, bus, devfn)) { + case 0: + break; + case 1: + return PCIBIOS_SUCCESSFUL; + default: + return PCIBIOS_DEVICE_NOT_FOUND; + } + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + switch (len) { + case 1: + out_8((u8 *)addr, val); + (void) in_8((u8 *)addr); + break; + case 2: + out_le16((u16 *)addr, val); + (void) in_le16((u16 *)addr); + break; + default: + out_le32((u32 *)addr, val); + (void) in_le32((u32 *)addr); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops u3_ht_pci_ops = +{ + u3_ht_read_config, + u3_ht_write_config +}; + +#endif /* CONFIG_POWER4 */ + +/* + * For a bandit bridge, turn on cache coherency if necessary. + * N.B. we could clean this up using the hose ops directly. + */ +static void __init +init_bandit(struct pci_controller *bp) +{ + unsigned int vendev, magic; + int rev; + + /* read the word at offset 0 in config space for device 11 */ + out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); + udelay(2); + vendev = in_le32(bp->cfg_data); + if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + + PCI_VENDOR_ID_APPLE) { + /* read the revision id */ + out_le32(bp->cfg_addr, + (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); + udelay(2); + rev = in_8(bp->cfg_data); + if (rev != BANDIT_REVID) + printk(KERN_WARNING + "Unknown revision %d for bandit\n", rev); + } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { + printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); + return; + } + + /* read the word at offset 0x50 */ + out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); + udelay(2); + magic = in_le32(bp->cfg_data); + if ((magic & BANDIT_COHERENT) != 0) + return; + magic |= BANDIT_COHERENT; + udelay(2); + out_le32(bp->cfg_data, magic); + printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); +} + + +/* + * Tweak the PCI-PCI bridge chip on the blue & white G3s. + */ +static void __init +init_p2pbridge(void) +{ + struct device_node *p2pbridge; + struct pci_controller* hose; + u8 bus, devfn; + u16 val; + + /* XXX it would be better here to identify the specific + PCI-PCI bridge chip we have. */ + if ((p2pbridge = find_devices("pci-bridge")) == 0 + || p2pbridge->parent == NULL + || strcmp(p2pbridge->parent->name, "pci") != 0) + return; + if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { + DBG("Can't find PCI infos for PCI<->PCI bridge\n"); + return; + } + /* Warning: At this point, we have not yet renumbered all busses. + * So we must use OF walking to find out hose + */ + hose = pci_find_hose_for_OF_device(p2pbridge); + if (!hose) { + DBG("Can't find hose for PCI<->PCI bridge\n"); + return; + } + if (early_read_config_word(hose, bus, devfn, + PCI_BRIDGE_CONTROL, &val) < 0) { + printk(KERN_ERR "init_p2pbridge: couldn't read bridge control\n"); + return; + } + val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; + early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); +} + +/* + * Some Apple desktop machines have a NEC PD720100A USB2 controller + * on the motherboard. Open Firmware, on these, will disable the + * EHCI part of it so it behaves like a pair of OHCI's. This fixup + * code re-enables it ;) + */ +static void __init +fixup_nec_usb2(void) +{ + struct device_node *nec; + + for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { + struct pci_controller *hose; + u32 data, *prop; + u8 bus, devfn; + + prop = (u32 *)get_property(nec, "vendor-id", NULL); + if (prop == NULL) + continue; + if (0x1033 != *prop) + continue; + prop = (u32 *)get_property(nec, "device-id", NULL); + if (prop == NULL) + continue; + if (0x0035 != *prop) + continue; + prop = (u32 *)get_property(nec, "reg", NULL); + if (prop == NULL) + continue; + devfn = (prop[0] >> 8) & 0xff; + bus = (prop[0] >> 16) & 0xff; + if (PCI_FUNC(devfn) != 0) + continue; + hose = pci_find_hose_for_OF_device(nec); + if (!hose) + continue; + early_read_config_dword(hose, bus, devfn, 0xe4, &data); + if (data & 1UL) { + printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n"); + data &= ~1UL; + early_write_config_dword(hose, bus, devfn, 0xe4, data); + early_write_config_byte(hose, bus, devfn | 2, PCI_INTERRUPT_LINE, + nec->intrs[0].line); + } + } +} + +void __init +pmac_find_bridges(void) +{ + struct device_node *np, *root; + struct device_node *ht = NULL; + + root = of_find_node_by_path("/"); + if (root == NULL) { + printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n"); + return; + } + for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { + if (np->name == NULL) + continue; + if (strcmp(np->name, "bandit") == 0 + || strcmp(np->name, "chaos") == 0 + || strcmp(np->name, "pci") == 0) { + if (add_bridge(np) == 0) + of_node_get(np); + } + if (strcmp(np->name, "ht") == 0) { + of_node_get(np); + ht = np; + } + } + of_node_put(root); + + /* Probe HT last as it relies on the agp resources to be already + * setup + */ + if (ht && add_bridge(ht) != 0) + of_node_put(ht); + + init_p2pbridge(); + fixup_nec_usb2(); + + /* We are still having some issues with the Xserve G4, enabling + * some offset between bus number and domains for now when we + * assign all busses should help for now + */ + if (pci_assign_all_busses) + pcibios_assign_bus_offset = 0x10; + +#ifdef CONFIG_POWER4 + /* There is something wrong with DMA on U3/HT. I haven't figured out + * the details yet, but if I set the cache line size to 128 bytes like + * it should, I'm getting memory corruption caused by devices like + * sungem (even without the MWI bit set, but maybe sungem doesn't + * care). Right now, it appears that setting up a 64 bytes line size + * works properly, 64 bytes beeing the max transfer size of HT, I + * suppose this is related the way HT/PCI are hooked together. I still + * need to dive into more specs though to be really sure of what's + * going on. --BenH. + * + * Ok, apparently, it's just that HT can't do more than 64 bytes + * transactions. MWI seem to be meaningless there as well, it may + * be worth nop'ing out pci_set_mwi too though I haven't done that + * yet. + * + * Note that it's a bit different for whatever is in the AGP slot. + * For now, I don't care, but this can become a real issue, we + * should probably hook pci_set_mwi anyway to make sure it sets + * the real cache line size in there. + */ + if (machine_is_compatible("MacRISC4")) + pci_cache_line_size = 16; /* 64 bytes */ + + pmac_check_ht_link(); +#endif /* CONFIG_POWER4 */ +} + +#define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \ + | (((o) & ~3) << 24)) + +#define GRACKLE_PICR1_STG 0x00000040 +#define GRACKLE_PICR1_LOOPSNOOP 0x00000010 + +/* N.B. this is called before bridges is initialized, so we can't + use grackle_pcibios_{read,write}_config_dword. */ +static inline void grackle_set_stg(struct pci_controller* bp, int enable) +{ + unsigned int val; + + out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); + val = in_le32(bp->cfg_data); + val = enable? (val | GRACKLE_PICR1_STG) : + (val & ~GRACKLE_PICR1_STG); + out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); + out_le32(bp->cfg_data, val); + (void)in_le32(bp->cfg_data); +} + +static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) +{ + unsigned int val; + + out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); + val = in_le32(bp->cfg_data); + val = enable? (val | GRACKLE_PICR1_LOOPSNOOP) : + (val & ~GRACKLE_PICR1_LOOPSNOOP); + out_be32(bp->cfg_addr, GRACKLE_CFA(0, 0, 0xa8)); + out_le32(bp->cfg_data, val); + (void)in_le32(bp->cfg_data); +} + +static int __init +setup_uninorth(struct pci_controller* hose, struct reg_property* addr) +{ + pci_assign_all_busses = 1; + has_uninorth = 1; + hose->ops = ¯isc_pci_ops; + hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); + hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); + /* We "know" that the bridge at f2000000 has the PCI slots. */ + return addr->address == 0xf2000000; +} + +static void __init +setup_bandit(struct pci_controller* hose, struct reg_property* addr) +{ + hose->ops = ¯isc_pci_ops; + hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); + hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); + init_bandit(hose); +} + +static void __init +setup_chaos(struct pci_controller* hose, struct reg_property* addr) +{ + /* assume a `chaos' bridge */ + hose->ops = &chaos_pci_ops; + hose->cfg_addr = ioremap(addr->address + 0x800000, 0x1000); + hose->cfg_data = ioremap(addr->address + 0xc00000, 0x1000); +} + +#ifdef CONFIG_POWER4 + +static void __init setup_u3_agp(struct pci_controller* hose) +{ + /* On G5, we move AGP up to high bus number so we don't need + * to reassign bus numbers for HT. If we ever have P2P bridges + * on AGP, we'll have to move pci_assign_all_busses to the + * pci_controller structure so we enable it for AGP and not for + * HT childs. + * We hard code the address because of the different size of + * the reg address cell, we shall fix that by killing struct + * reg_property and using some accessor functions instead + */ + hose->first_busno = 0xf0; + hose->last_busno = 0xff; + has_uninorth = 1; + hose->ops = ¯isc_pci_ops; + hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); + hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); + + u3_agp = hose; +} + +static void __init setup_u3_ht(struct pci_controller* hose) +{ + struct device_node *np = (struct device_node *)hose->arch_data; + int i, cur; + + hose->ops = &u3_ht_pci_ops; + + /* We hard code the address because of the different size of + * the reg address cell, we shall fix that by killing struct + * reg_property and using some accessor functions instead + */ + hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000); + + /* + * /ht node doesn't expose a "ranges" property, so we "remove" regions that + * have been allocated to AGP. So far, this version of the code doesn't assign + * any of the 0xfxxxxxxx "fine" memory regions to /ht. + * We need to fix that sooner or later by either parsing all child "ranges" + * properties or figuring out the U3 address space decoding logic and + * then read its configuration register (if any). + */ + hose->io_base_phys = 0xf4000000; + hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000); + isa_io_base = (unsigned long) hose->io_base_virt; + hose->io_resource.name = np->full_name; + hose->io_resource.start = 0; + hose->io_resource.end = 0x003fffff; + hose->io_resource.flags = IORESOURCE_IO; + hose->pci_mem_offset = 0; + hose->first_busno = 0; + hose->last_busno = 0xef; + hose->mem_resources[0].name = np->full_name; + hose->mem_resources[0].start = 0x80000000; + hose->mem_resources[0].end = 0xefffffff; + hose->mem_resources[0].flags = IORESOURCE_MEM; + + if (u3_agp == NULL) { + DBG("U3 has no AGP, using full resource range\n"); + return; + } + + /* We "remove" the AGP resources from the resources allocated to HT, that + * is we create "holes". However, that code does assumptions that so far + * happen to be true (cross fingers...), typically that resources in the + * AGP node are properly ordered + */ + cur = 0; + for (i=0; i<3; i++) { + struct resource *res = &u3_agp->mem_resources[i]; + if (res->flags != IORESOURCE_MEM) + continue; + /* We don't care about "fine" resources */ + if (res->start >= 0xf0000000) + continue; + /* Check if it's just a matter of "shrinking" us in one direction */ + if (hose->mem_resources[cur].start == res->start) { + DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", + cur, hose->mem_resources[cur].start, res->end + 1); + hose->mem_resources[cur].start = res->end + 1; + continue; + } + if (hose->mem_resources[cur].end == res->end) { + DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", + cur, hose->mem_resources[cur].end, res->start - 1); + hose->mem_resources[cur].end = res->start - 1; + continue; + } + /* No, it's not the case, we need a hole */ + if (cur == 2) { + /* not enough resources to make a hole, we drop part of the range */ + printk(KERN_WARNING "Running out of resources for /ht host !\n"); + hose->mem_resources[cur].end = res->start - 1; + continue; + } + cur++; + DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", + cur-1, res->start - 1, cur, res->end + 1); + hose->mem_resources[cur].name = np->full_name; + hose->mem_resources[cur].flags = IORESOURCE_MEM; + hose->mem_resources[cur].start = res->end + 1; + hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; + hose->mem_resources[cur-1].end = res->start - 1; + } +} + +#endif /* CONFIG_POWER4 */ + +void __init +setup_grackle(struct pci_controller *hose) +{ + setup_indirect_pci(hose, 0xfec00000, 0xfee00000); + if (machine_is_compatible("AAPL,PowerBook1998")) + grackle_set_loop_snoop(hose, 1); +#if 0 /* Disabled for now, HW problems ??? */ + grackle_set_stg(hose, 1); +#endif +} + +static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose, + struct device_node *dev, int primary) +{ + static unsigned int static_lc_ranges[2024]; + unsigned int *dt_ranges, *lc_ranges, *ranges, *prev; + unsigned int size; + int rlen = 0, orig_rlen; + int memno = 0; + struct resource *res; + int np, na = prom_n_addr_cells(dev); + + np = na + 5; + + /* First we try to merge ranges to fix a problem with some pmacs + * that can have more than 3 ranges, fortunately using contiguous + * addresses -- BenH + */ + dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen); + if (!dt_ranges) + return; + /* lc_ranges = alloc_bootmem(rlen);*/ + lc_ranges = static_lc_ranges; + if (!lc_ranges) + return; /* what can we do here ? */ + memcpy(lc_ranges, dt_ranges, rlen); + orig_rlen = rlen; + + /* Let's work on a copy of the "ranges" property instead of damaging + * the device-tree image in memory + */ + ranges = lc_ranges; + prev = NULL; + while ((rlen -= np * sizeof(unsigned int)) >= 0) { + if (prev) { + if (prev[0] == ranges[0] && prev[1] == ranges[1] && + (prev[2] + prev[na+4]) == ranges[2] && + (prev[na+2] + prev[na+4]) == ranges[na+2]) { + prev[na+4] += ranges[na+4]; + ranges[0] = 0; + ranges += np; + continue; + } + } + prev = ranges; + ranges += np; + } + + /* + * The ranges property is laid out as an array of elements, + * each of which comprises: + * cells 0 - 2: a PCI address + * cells 3 or 3+4: a CPU physical address + * (size depending on dev->n_addr_cells) + * cells 4+5 or 5+6: the size of the range + */ + ranges = lc_ranges; + rlen = orig_rlen; + while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) { + res = NULL; + size = ranges[na+4]; + switch (ranges[0] >> 24) { + case 1: /* I/O space */ + if (ranges[2] != 0) + break; + hose->io_base_phys = ranges[na+2]; + /* limit I/O space to 16MB */ + if (size > 0x01000000) + size = 0x01000000; + hose->io_base_virt = ioremap(ranges[na+2], size); + if (primary) + isa_io_base = (unsigned long) hose->io_base_virt; + res = &hose->io_resource; + res->flags = IORESOURCE_IO; + res->start = ranges[2]; + break; + case 2: /* memory space */ + memno = 0; + if (ranges[1] == 0 && ranges[2] == 0 + && ranges[na+4] <= (16 << 20)) { + /* 1st 16MB, i.e. ISA memory area */ +#if 0 + if (primary) + isa_mem_base = ranges[na+2]; +#endif + memno = 1; + } + while (memno < 3 && hose->mem_resources[memno].flags) + ++memno; + if (memno == 0) + hose->pci_mem_offset = ranges[na+2] - ranges[2]; + if (memno < 3) { + res = &hose->mem_resources[memno]; + res->flags = IORESOURCE_MEM; + res->start = ranges[na+2]; + } + break; + } + if (res != NULL) { + res->name = dev->full_name; + res->end = res->start + size - 1; + res->parent = NULL; + res->sibling = NULL; + res->child = NULL; + } + ranges += np; + } +} + +/* + * We assume that if we have a G3 powermac, we have one bridge called + * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, + * if we have one or more bandit or chaos bridges, we don't have a MPC106. + */ +static int __init add_bridge(struct device_node *dev) +{ + int len; + struct pci_controller *hose; + struct reg_property *addr; + char* disp_name; + int *bus_range; + int primary = 1; + + DBG("Adding PCI host bridge %s\n", dev->full_name); + + addr = (struct reg_property *) get_property(dev, "reg", &len); + if (addr == NULL || len < sizeof(*addr)) { + printk(KERN_WARNING "Can't use %s: no address\n", + dev->full_name); + return -ENODEV; + } + bus_range = (int *) get_property(dev, "bus-range", &len); + if (bus_range == NULL || len < 2 * sizeof(int)) { + printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", + dev->full_name); + } + + hose = pcibios_alloc_controller(); + if (!hose) + return -ENOMEM; + hose->arch_data = dev; + hose->first_busno = bus_range ? bus_range[0] : 0; + hose->last_busno = bus_range ? bus_range[1] : 0xff; + + disp_name = NULL; +#ifdef CONFIG_POWER4 + if (device_is_compatible(dev, "u3-agp")) { + setup_u3_agp(hose, addr); + disp_name = "U3-AGP"; + primary = 0; + } else if (device_is_compatible(dev, "u3-ht")) { + setup_u3_ht(hose, addr); + disp_name = "U3-HT"; + primary = 1; + } else +#endif /* CONFIG_POWER4 */ + if (device_is_compatible(dev, "uni-north")) { + primary = setup_uninorth(hose, addr); + disp_name = "UniNorth"; + } else if (strcmp(dev->name, "pci") == 0) { + /* XXX assume this is a mpc106 (grackle) */ + setup_grackle(hose); + disp_name = "Grackle (MPC106)"; + } else if (strcmp(dev->name, "bandit") == 0) { + setup_bandit(hose, addr); + disp_name = "Bandit"; + } else if (strcmp(dev->name, "chaos") == 0) { + setup_chaos(hose, addr); + disp_name = "Chaos"; + primary = 0; + } + printk(KERN_INFO "Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n", + disp_name, addr->address, hose->first_busno, hose->last_busno); + DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", + hose, hose->cfg_addr, hose->cfg_data); + + /* Interpret the "ranges" property */ + /* This also maps the I/O region and sets isa_io/mem_base */ + pci_process_bridge_OF_ranges(hose, dev, primary); + + /* Fixup "bus-range" OF property */ + fixup_bus_range(dev); + + return 0; +} + +static void __init +pcibios_fixup_OF_interrupts(void) +{ + struct pci_dev* dev = NULL; + + /* + * Open Firmware often doesn't initialize the + * PCI_INTERRUPT_LINE config register properly, so we + * should find the device node and apply the interrupt + * obtained from the OF device-tree + */ + for_each_pci_dev(dev) { + struct device_node *node; + node = pci_device_to_OF_node(dev); + /* this is the node, see if it has interrupts */ + if (node && node->n_intrs > 0) + dev->irq = node->intrs[0].line; + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + } +} + +void __init +pmac_pcibios_fixup(void) +{ + /* Fixup interrupts according to OF tree */ + pcibios_fixup_OF_interrupts(); +} + +int +pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) +{ + struct device_node* node; + int updatecfg = 0; + int uninorth_child; + + node = pci_device_to_OF_node(dev); + + /* We don't want to enable USB controllers absent from the OF tree + * (iBook second controller) + */ + if (dev->vendor == PCI_VENDOR_ID_APPLE + && (dev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) + && !node) { + printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", + pci_name(dev)); + return -EINVAL; + } + + if (!node) + return 0; + + uninorth_child = node->parent && + device_is_compatible(node->parent, "uni-north"); + + /* Firewire & GMAC were disabled after PCI probe, the driver is + * claiming them, we must re-enable them now. + */ + if (uninorth_child && !strcmp(node->name, "firewire") && + (device_is_compatible(node, "pci106b,18") || + device_is_compatible(node, "pci106b,30") || + device_is_compatible(node, "pci11c1,5811"))) { + pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); + pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); + updatecfg = 1; + } + if (uninorth_child && !strcmp(node->name, "ethernet") && + device_is_compatible(node, "gmac")) { + pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); + updatecfg = 1; + } + + if (updatecfg) { + u16 cmd; + + /* + * Make sure PCI is correctly configured + * + * We use old pci_bios versions of the function since, by + * default, gmac is not powered up, and so will be absent + * from the kernel initial PCI lookup. + * + * Should be replaced by 2.4 new PCI mechanisms and really + * register the device. + */ + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; + pci_write_config_word(dev, PCI_COMMAND, cmd); + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); + } + + return 0; +} + +/* We power down some devices after they have been probed. They'll + * be powered back on later on + */ +void __init +pmac_pcibios_after_init(void) +{ + struct device_node* nd; + +#ifdef CONFIG_BLK_DEV_IDE + struct pci_dev *dev = NULL; + + /* OF fails to initialize IDE controllers on macs + * (and maybe other machines) + * + * Ideally, this should be moved to the IDE layer, but we need + * to check specifically with Andre Hedrick how to do it cleanly + * since the common IDE code seem to care about the fact that the + * BIOS may have disabled a controller. + * + * -- BenH + */ + for_each_pci_dev(dev) { + if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) + pci_enable_device(dev); + } +#endif /* CONFIG_BLK_DEV_IDE */ + + nd = find_devices("firewire"); + while (nd) { + if (nd->parent && (device_is_compatible(nd, "pci106b,18") || + device_is_compatible(nd, "pci106b,30") || + device_is_compatible(nd, "pci11c1,5811")) + && device_is_compatible(nd->parent, "uni-north")) { + pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); + pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); + } + nd = nd->next; + } + nd = find_devices("ethernet"); + while (nd) { + if (nd->parent && device_is_compatible(nd, "gmac") + && device_is_compatible(nd->parent, "uni-north")) + pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); + nd = nd->next; + } +} + +#ifdef CONFIG_PPC64 +static void __init pmac_fixup_phb_resources(void) +{ + struct pci_controller *hose, *tmp; + + list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { + unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base; + hose->io_resource.start += offset; + hose->io_resource.end += offset; + printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n", + hose->global_number, + hose->io_resource.start, hose->io_resource.end); + } +} + +void __init pmac_pci_init(void) +{ + struct device_node *np, *root; + struct device_node *ht = NULL; + + /* Probe root PCI hosts, that is on U3 the AGP host and the + * HyperTransport host. That one is actually "kept" around + * and actually added last as it's resource management relies + * on the AGP resources to have been setup first + */ + root = of_find_node_by_path("/"); + if (root == NULL) { + printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n"); + return; + } + for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { + if (np->name == NULL) + continue; + if (strcmp(np->name, "pci") == 0) { + if (add_bridge(np) == 0) + of_node_get(np); + } + if (strcmp(np->name, "ht") == 0) { + of_node_get(np); + ht = np; + } + } + of_node_put(root); + + /* Now setup the HyperTransport host if we found any + */ + if (ht && add_bridge(ht) != 0) + of_node_put(ht); + + /* Fixup the IO resources on our host bridges as the common code + * does it only for childs of the host bridges + */ + pmac_fixup_phb_resources(); + + /* Setup the linkage between OF nodes and PHBs */ + pci_devs_phb_init(); + + /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We + * assume there is no P2P bridge on the AGP bus, which should be a + * safe assumptions hopefully. + */ + if (u3_agp) { + struct device_node *np = u3_agp->arch_data; + PCI_DN(np)->busno = 0xf0; + for (np = np->child; np; np = np->sibling) + PCI_DN(np)->busno = 0xf0; + } + + pmac_check_ht_link(); + + /* Tell pci.c to not use the common resource allocation mecanism */ + pci_probe_only = 1; + + /* Allow all IO */ + io_page_mask = -1; +} +#endif + +#ifdef CONFIG_PPC32 +void pmac_pci_fixup_cardbus(struct pci_dev* dev) +{ + if (_machine != _MACH_Pmac) + return; + /* + * Fix the interrupt routing on the various cardbus bridges + * used on powerbooks + */ + if (dev->vendor != PCI_VENDOR_ID_TI) + return; + if (dev->device == PCI_DEVICE_ID_TI_1130 || + dev->device == PCI_DEVICE_ID_TI_1131) { + u8 val; + /* Enable PCI interrupt */ + if (pci_read_config_byte(dev, 0x91, &val) == 0) + pci_write_config_byte(dev, 0x91, val | 0x30); + /* Disable ISA interrupt mode */ + if (pci_read_config_byte(dev, 0x92, &val) == 0) + pci_write_config_byte(dev, 0x92, val & ~0x06); + } + if (dev->device == PCI_DEVICE_ID_TI_1210 || + dev->device == PCI_DEVICE_ID_TI_1211 || + dev->device == PCI_DEVICE_ID_TI_1410 || + dev->device == PCI_DEVICE_ID_TI_1510) { + u8 val; + /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA + signal out the MFUNC0 pin */ + if (pci_read_config_byte(dev, 0x8c, &val) == 0) + pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); + /* Disable ISA interrupt mode */ + if (pci_read_config_byte(dev, 0x92, &val) == 0) + pci_write_config_byte(dev, 0x92, val & ~0x06); + } +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); + +void pmac_pci_fixup_pciata(struct pci_dev* dev) +{ + u8 progif = 0; + + /* + * On PowerMacs, we try to switch any PCI ATA controller to + * fully native mode + */ + if (_machine != _MACH_Pmac) + return; + /* Some controllers don't have the class IDE */ + if (dev->vendor == PCI_VENDOR_ID_PROMISE) + switch(dev->device) { + case PCI_DEVICE_ID_PROMISE_20246: + case PCI_DEVICE_ID_PROMISE_20262: + case PCI_DEVICE_ID_PROMISE_20263: + case PCI_DEVICE_ID_PROMISE_20265: + case PCI_DEVICE_ID_PROMISE_20267: + case PCI_DEVICE_ID_PROMISE_20268: + case PCI_DEVICE_ID_PROMISE_20269: + case PCI_DEVICE_ID_PROMISE_20270: + case PCI_DEVICE_ID_PROMISE_20271: + case PCI_DEVICE_ID_PROMISE_20275: + case PCI_DEVICE_ID_PROMISE_20276: + case PCI_DEVICE_ID_PROMISE_20277: + goto good; + } + /* Others, check PCI class */ + if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) + return; + good: + pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); + if ((progif & 5) != 5) { + printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", pci_name(dev)); + (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); + if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || + (progif & 5) != 5) + printk(KERN_ERR "Rewrite of PROGIF failed !\n"); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); +#endif + +/* + * Disable second function on K2-SATA, it's broken + * and disable IO BARs on first one + */ +static void fixup_k2_sata(struct pci_dev* dev) +{ + int i; + u16 cmd; + + if (PCI_FUNC(dev->devfn) > 0) { + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + pci_write_config_word(dev, PCI_COMMAND, cmd); + for (i = 0; i < 6; i++) { + dev->resource[i].start = dev->resource[i].end = 0; + dev->resource[i].flags = 0; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); + } + } else { + pci_read_config_word(dev, PCI_COMMAND, &cmd); + cmd &= ~PCI_COMMAND_IO; + pci_write_config_word(dev, PCI_COMMAND, cmd); + for (i = 0; i < 5; i++) { + dev->resource[i].start = dev->resource[i].end = 0; + dev->resource[i].flags = 0; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0); + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); + diff --git a/arch/powerpc/platforms/powermac/pmac_pic.c b/arch/powerpc/platforms/powermac/pmac_pic.c new file mode 100644 index 00000000000..bf3e1899a4c --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_pic.c @@ -0,0 +1,655 @@ +/* + * Support for the interrupt controllers found on Power Macintosh, + * currently Apple's "Grand Central" interrupt controller in all + * it's incarnations. OpenPIC support used on newer machines is + * in a separate file + * + * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) + * + * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmac_pic.h" + +/* + * XXX this should be in xmon.h, but putting it there means xmon.h + * has to include (to get irqreturn_t), which + * causes all sorts of problems. -- paulus + */ +extern irqreturn_t xmon_irq(int, void *, struct pt_regs *); + +struct pmac_irq_hw { + unsigned int event; + unsigned int enable; + unsigned int ack; + unsigned int level; +}; + +/* Default addresses */ +static volatile struct pmac_irq_hw *pmac_irq_hw[4] = { + (struct pmac_irq_hw *) 0xf3000020, + (struct pmac_irq_hw *) 0xf3000010, + (struct pmac_irq_hw *) 0xf4000020, + (struct pmac_irq_hw *) 0xf4000010, +}; + +#define GC_LEVEL_MASK 0x3ff00000 +#define OHARE_LEVEL_MASK 0x1ff00000 +#define HEATHROW_LEVEL_MASK 0x1ff00000 + +static int max_irqs; +static int max_real_irqs; +static u32 level_mask[4]; + +static DEFINE_SPINLOCK(pmac_pic_lock); + + +#define GATWICK_IRQ_POOL_SIZE 10 +static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE]; + +/* + * Mark an irq as "lost". This is only used on the pmac + * since it can lose interrupts (see pmac_set_irq_mask). + * -- Cort + */ +void +__set_lost(unsigned long irq_nr, int nokick) +{ + if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) { + atomic_inc(&ppc_n_lost_interrupts); + if (!nokick) + set_dec(1); + } +} + +static void +pmac_mask_and_ack_irq(unsigned int irq_nr) +{ + unsigned long bit = 1UL << (irq_nr & 0x1f); + int i = irq_nr >> 5; + unsigned long flags; + + if ((unsigned)irq_nr >= max_irqs) + return; + + clear_bit(irq_nr, ppc_cached_irq_mask); + if (test_and_clear_bit(irq_nr, ppc_lost_interrupts)) + atomic_dec(&ppc_n_lost_interrupts); + spin_lock_irqsave(&pmac_pic_lock, flags); + out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); + out_le32(&pmac_irq_hw[i]->ack, bit); + do { + /* make sure ack gets to controller before we enable + interrupts */ + mb(); + } while((in_le32(&pmac_irq_hw[i]->enable) & bit) + != (ppc_cached_irq_mask[i] & bit)); + spin_unlock_irqrestore(&pmac_pic_lock, flags); +} + +static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) +{ + unsigned long bit = 1UL << (irq_nr & 0x1f); + int i = irq_nr >> 5; + unsigned long flags; + + if ((unsigned)irq_nr >= max_irqs) + return; + + spin_lock_irqsave(&pmac_pic_lock, flags); + /* enable unmasked interrupts */ + out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); + + do { + /* make sure mask gets to controller before we + return to user */ + mb(); + } while((in_le32(&pmac_irq_hw[i]->enable) & bit) + != (ppc_cached_irq_mask[i] & bit)); + + /* + * Unfortunately, setting the bit in the enable register + * when the device interrupt is already on *doesn't* set + * the bit in the flag register or request another interrupt. + */ + if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) + __set_lost((ulong)irq_nr, nokicklost); + spin_unlock_irqrestore(&pmac_pic_lock, flags); +} + +/* When an irq gets requested for the first client, if it's an + * edge interrupt, we clear any previous one on the controller + */ +static unsigned int pmac_startup_irq(unsigned int irq_nr) +{ + unsigned long bit = 1UL << (irq_nr & 0x1f); + int i = irq_nr >> 5; + + if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0) + out_le32(&pmac_irq_hw[i]->ack, bit); + set_bit(irq_nr, ppc_cached_irq_mask); + pmac_set_irq_mask(irq_nr, 0); + + return 0; +} + +static void pmac_mask_irq(unsigned int irq_nr) +{ + clear_bit(irq_nr, ppc_cached_irq_mask); + pmac_set_irq_mask(irq_nr, 0); + mb(); +} + +static void pmac_unmask_irq(unsigned int irq_nr) +{ + set_bit(irq_nr, ppc_cached_irq_mask); + pmac_set_irq_mask(irq_nr, 0); +} + +static void pmac_end_irq(unsigned int irq_nr) +{ + if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) + && irq_desc[irq_nr].action) { + set_bit(irq_nr, ppc_cached_irq_mask); + pmac_set_irq_mask(irq_nr, 1); + } +} + + +struct hw_interrupt_type pmac_pic = { + .typename = " PMAC-PIC ", + .startup = pmac_startup_irq, + .enable = pmac_unmask_irq, + .disable = pmac_mask_irq, + .ack = pmac_mask_and_ack_irq, + .end = pmac_end_irq, +}; + +struct hw_interrupt_type gatwick_pic = { + .typename = " GATWICK ", + .startup = pmac_startup_irq, + .enable = pmac_unmask_irq, + .disable = pmac_mask_irq, + .ack = pmac_mask_and_ack_irq, + .end = pmac_end_irq, +}; + +static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs) +{ + int irq, bits; + + for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { + int i = irq >> 5; + bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; + /* We must read level interrupts from the level register */ + bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); + bits &= ppc_cached_irq_mask[i]; + if (bits == 0) + continue; + irq += __ilog2(bits); + __do_IRQ(irq, regs); + return IRQ_HANDLED; + } + printk("gatwick irq not from gatwick pic\n"); + return IRQ_NONE; +} + +int +pmac_get_irq(struct pt_regs *regs) +{ + int irq; + unsigned long bits = 0; + +#ifdef CONFIG_SMP + void psurge_smp_message_recv(struct pt_regs *); + + /* IPI's are a hack on the powersurge -- Cort */ + if ( smp_processor_id() != 0 ) { + psurge_smp_message_recv(regs); + return -2; /* ignore, already handled */ + } +#endif /* CONFIG_SMP */ + for (irq = max_real_irqs; (irq -= 32) >= 0; ) { + int i = irq >> 5; + bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; + /* We must read level interrupts from the level register */ + bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); + bits &= ppc_cached_irq_mask[i]; + if (bits == 0) + continue; + irq += __ilog2(bits); + break; + } + + return irq; +} + +/* This routine will fix some missing interrupt values in the device tree + * on the gatwick mac-io controller used by some PowerBooks + */ +static void __init +pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base) +{ + struct device_node *node; + int count; + + memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool)); + node = gw->child; + count = 0; + while(node) + { + /* Fix SCC */ + if (strcasecmp(node->name, "escc") == 0) + if (node->child) { + if (node->child->n_intrs < 3) { + node->child->intrs = &gatwick_int_pool[count]; + count += 3; + } + node->child->n_intrs = 3; + node->child->intrs[0].line = 15+irq_base; + node->child->intrs[1].line = 4+irq_base; + node->child->intrs[2].line = 5+irq_base; + printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n", + node->child->intrs[0].line, + node->child->intrs[1].line, + node->child->intrs[2].line); + } + /* Fix media-bay & left SWIM */ + if (strcasecmp(node->name, "media-bay") == 0) { + struct device_node* ya_node; + + if (node->n_intrs == 0) + node->intrs = &gatwick_int_pool[count++]; + node->n_intrs = 1; + node->intrs[0].line = 29+irq_base; + printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n", + node->intrs[0].line); + + ya_node = node->child; + while(ya_node) + { + if (strcasecmp(ya_node->name, "floppy") == 0) { + if (ya_node->n_intrs < 2) { + ya_node->intrs = &gatwick_int_pool[count]; + count += 2; + } + ya_node->n_intrs = 2; + ya_node->intrs[0].line = 19+irq_base; + ya_node->intrs[1].line = 1+irq_base; + printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n", + ya_node->intrs[0].line, ya_node->intrs[1].line); + } + if (strcasecmp(ya_node->name, "ata4") == 0) { + if (ya_node->n_intrs < 2) { + ya_node->intrs = &gatwick_int_pool[count]; + count += 2; + } + ya_node->n_intrs = 2; + ya_node->intrs[0].line = 14+irq_base; + ya_node->intrs[1].line = 3+irq_base; + printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n", + ya_node->intrs[0].line, ya_node->intrs[1].line); + } + ya_node = ya_node->sibling; + } + } + node = node->sibling; + } + if (count > 10) { + printk("WARNING !! Gatwick interrupt pool overflow\n"); + printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE); + printk(" requested = %d\n", count); + } +} + +/* + * The PowerBook 3400/2400/3500 can have a combo ethernet/modem + * card which includes an ohare chip that acts as a second interrupt + * controller. If we find this second ohare, set it up and fix the + * interrupt value in the device tree for the ethernet chip. + */ +static int __init enable_second_ohare(void) +{ + unsigned char bus, devfn; + unsigned short cmd; + unsigned long addr; + struct device_node *irqctrler = find_devices("pci106b,7"); + struct device_node *ether; + + if (irqctrler == NULL || irqctrler->n_addrs <= 0) + return -1; + addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40); + pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20); + max_irqs = 64; + if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) { + struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler); + if (!hose) + printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); + else { + early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + cmd &= ~PCI_COMMAND_IO; + early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); + } + } + + /* Fix interrupt for the modem/ethernet combo controller. The number + in the device tree (27) is bogus (correct for the ethernet-only + board but not the combo ethernet/modem board). + The real interrupt is 28 on the second controller -> 28+32 = 60. + */ + ether = find_devices("pci1011,14"); + if (ether && ether->n_intrs > 0) { + ether->intrs[0].line = 60; + printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n", + ether->intrs[0].line); + } + + /* Return the interrupt number of the cascade */ + return irqctrler->intrs[0].line; +} + +static int pmac_u3_cascade(struct pt_regs *regs, void *data) +{ + return mpic_get_one_irq((struct mpic *)data, regs); +} + +#ifdef CONFIG_XMON +static struct irqaction xmon_action = { + .handler = xmon_irq, + .flags = 0, + .mask = CPU_MASK_NONE, + .name = "NMI - XMON" +}; +#endif + +static struct irqaction gatwick_cascade_action = { + .handler = gatwick_action, + .flags = SA_INTERRUPT, + .mask = CPU_MASK_NONE, + .name = "cascade", +}; + +void __init pmac_pic_init(void) +{ + int i; + struct device_node *irqctrler = NULL; + struct device_node *irqctrler2 = NULL; + struct device_node *np; + unsigned long addr; + int irq_cascade = -1; + struct mpic *mpic1, *mpic2; + + /* We first try to detect Apple's new Core99 chipset, since mac-io + * is quite different on those machines and contains an IBM MPIC2. + */ + np = find_type_devices("open-pic"); + while (np) { + if (np->parent && !strcmp(np->parent->name, "u3")) + irqctrler2 = np; + else + irqctrler = np; + np = np->next; + } + if (irqctrler != NULL && irqctrler->n_addrs > 0) { + unsigned char senses[128]; + + printk(KERN_INFO "PowerMac using OpenPIC irq controller at 0x%08x\n", + (unsigned int)irqctrler->addrs[0].address); + + prom_get_irq_senses(senses, 0, 128); + mpic1 = mpic_alloc(irqctrler->addrs[0].address, + MPIC_PRIMARY | MPIC_WANTS_RESET, + 0, 0, 128, 256, senses, 128, " K2-MPIC "); + BUG_ON(mpic1 == NULL); + mpic_init(mpic1); + + if (irqctrler2 != NULL && irqctrler2->n_intrs > 0 && + irqctrler2->n_addrs > 0) { + printk(KERN_INFO "Slave OpenPIC at 0x%08x hooked on IRQ %d\n", + (u32)irqctrler2->addrs[0].address, + irqctrler2->intrs[0].line); + + pmac_call_feature(PMAC_FTR_ENABLE_MPIC, irqctrler2, 0, 0); + prom_get_irq_senses(senses, 128, 128 + 128); + + /* We don't need to set MPIC_BROKEN_U3 here since we don't have + * hypertransport interrupts routed to it + */ + mpic2 = mpic_alloc(irqctrler2->addrs[0].address, + MPIC_BIG_ENDIAN | MPIC_WANTS_RESET, + 0, 128, 128, 0, senses, 128, " U3-MPIC "); + BUG_ON(mpic2 == NULL); + mpic_init(mpic2); + mpic_setup_cascade(irqctrler2->intrs[0].line, + pmac_u3_cascade, mpic2); + } + } + + /* Get the level/edge settings, assume if it's not + * a Grand Central nor an OHare, then it's an Heathrow + * (or Paddington). + */ + if (find_devices("gc")) + level_mask[0] = GC_LEVEL_MASK; + else if (find_devices("ohare")) { + level_mask[0] = OHARE_LEVEL_MASK; + /* We might have a second cascaded ohare */ + level_mask[1] = OHARE_LEVEL_MASK; + } else { + level_mask[0] = HEATHROW_LEVEL_MASK; + level_mask[1] = 0; + /* We might have a second cascaded heathrow */ + level_mask[2] = HEATHROW_LEVEL_MASK; + level_mask[3] = 0; + } + + /* + * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts, + * 1998 G3 Series PowerBooks have 128, + * other powermacs have 32. + * The combo ethernet/modem card for the Powerstar powerbooks + * (2400/3400/3500, ohare based) has a second ohare chip + * effectively making a total of 64. + */ + max_irqs = max_real_irqs = 32; + irqctrler = find_devices("mac-io"); + if (irqctrler) + { + max_real_irqs = 64; + if (irqctrler->next) + max_irqs = 128; + else + max_irqs = 64; + } + for ( i = 0; i < max_real_irqs ; i++ ) + irq_desc[i].handler = &pmac_pic; + + /* get addresses of first controller */ + if (irqctrler) { + if (irqctrler->n_addrs > 0) { + addr = (unsigned long) + ioremap(irqctrler->addrs[0].address, 0x40); + for (i = 0; i < 2; ++i) + pmac_irq_hw[i] = (volatile struct pmac_irq_hw*) + (addr + (2 - i) * 0x10); + } + + /* get addresses of second controller */ + irqctrler = irqctrler->next; + if (irqctrler && irqctrler->n_addrs > 0) { + addr = (unsigned long) + ioremap(irqctrler->addrs[0].address, 0x40); + for (i = 2; i < 4; ++i) + pmac_irq_hw[i] = (volatile struct pmac_irq_hw*) + (addr + (4 - i) * 0x10); + irq_cascade = irqctrler->intrs[0].line; + if (device_is_compatible(irqctrler, "gatwick")) + pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs); + } + } else { + /* older powermacs have a GC (grand central) or ohare at + f3000000, with interrupt control registers at f3000020. */ + addr = (unsigned long) ioremap(0xf3000000, 0x40); + pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20); + } + + /* PowerBooks 3400 and 3500 can have a second controller in a second + ohare chip, on the combo ethernet/modem card */ + if (machine_is_compatible("AAPL,3400/2400") + || machine_is_compatible("AAPL,3500")) + irq_cascade = enable_second_ohare(); + + /* disable all interrupts in all controllers */ + for (i = 0; i * 32 < max_irqs; ++i) + out_le32(&pmac_irq_hw[i]->enable, 0); + /* mark level interrupts */ + for (i = 0; i < max_irqs; i++) + if (level_mask[i >> 5] & (1UL << (i & 0x1f))) + irq_desc[i].status = IRQ_LEVEL; + + /* get interrupt line of secondary interrupt controller */ + if (irq_cascade >= 0) { + printk(KERN_INFO "irq: secondary controller on irq %d\n", + (int)irq_cascade); + for ( i = max_real_irqs ; i < max_irqs ; i++ ) + irq_desc[i].handler = &gatwick_pic; + setup_irq(irq_cascade, &gatwick_cascade_action); + } + printk("System has %d possible interrupts\n", max_irqs); + if (max_irqs != max_real_irqs) + printk(KERN_DEBUG "%d interrupts on main controller\n", + max_real_irqs); + +#ifdef CONFIG_XMON + setup_irq(20, &xmon_action); +#endif /* CONFIG_XMON */ +} + +#ifdef CONFIG_PM +/* + * These procedures are used in implementing sleep on the powerbooks. + * sleep_save_intrs() saves the states of all interrupt enables + * and disables all interrupts except for the nominated one. + * sleep_restore_intrs() restores the states of all interrupt enables. + */ +unsigned long sleep_save_mask[2]; + +/* This used to be passed by the PMU driver but that link got + * broken with the new driver model. We use this tweak for now... + */ +static int pmacpic_find_viaint(void) +{ + int viaint = -1; + +#ifdef CONFIG_ADB_PMU + struct device_node *np; + + if (pmu_get_model() != PMU_OHARE_BASED) + goto not_found; + np = of_find_node_by_name(NULL, "via-pmu"); + if (np == NULL) + goto not_found; + viaint = np->intrs[0].line; +#endif /* CONFIG_ADB_PMU */ + +not_found: + return viaint; +} + +static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) +{ + int viaint = pmacpic_find_viaint(); + + sleep_save_mask[0] = ppc_cached_irq_mask[0]; + sleep_save_mask[1] = ppc_cached_irq_mask[1]; + ppc_cached_irq_mask[0] = 0; + ppc_cached_irq_mask[1] = 0; + if (viaint > 0) + set_bit(viaint, ppc_cached_irq_mask); + out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); + if (max_real_irqs > 32) + out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); + (void)in_le32(&pmac_irq_hw[0]->event); + /* make sure mask gets to controller before we return to caller */ + mb(); + (void)in_le32(&pmac_irq_hw[0]->enable); + + return 0; +} + +static int pmacpic_resume(struct sys_device *sysdev) +{ + int i; + + out_le32(&pmac_irq_hw[0]->enable, 0); + if (max_real_irqs > 32) + out_le32(&pmac_irq_hw[1]->enable, 0); + mb(); + for (i = 0; i < max_real_irqs; ++i) + if (test_bit(i, sleep_save_mask)) + pmac_unmask_irq(i); + + return 0; +} + +#endif /* CONFIG_PM */ + +static struct sysdev_class pmacpic_sysclass = { + set_kset_name("pmac_pic"), +}; + +static struct sys_device device_pmacpic = { + .id = 0, + .cls = &pmacpic_sysclass, +}; + +static struct sysdev_driver driver_pmacpic = { +#ifdef CONFIG_PM + .suspend = &pmacpic_suspend, + .resume = &pmacpic_resume, +#endif /* CONFIG_PM */ +}; + +static int __init init_pmacpic_sysfs(void) +{ + if (max_irqs == 0) + return -ENODEV; + + printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); + sysdev_class_register(&pmacpic_sysclass); + sysdev_register(&device_pmacpic); + sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); + return 0; +} + +subsys_initcall(init_pmacpic_sysfs); + diff --git a/arch/powerpc/platforms/powermac/pmac_pic.h b/arch/powerpc/platforms/powermac/pmac_pic.h new file mode 100644 index 00000000000..664103dfeef --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_pic.h @@ -0,0 +1,11 @@ +#ifndef __PPC_PLATFORMS_PMAC_PIC_H +#define __PPC_PLATFORMS_PMAC_PIC_H + +#include + +extern struct hw_interrupt_type pmac_pic; + +void pmac_pic_init(void); +int pmac_get_irq(struct pt_regs *regs); + +#endif /* __PPC_PLATFORMS_PMAC_PIC_H */ diff --git a/arch/powerpc/platforms/powermac/pmac_setup.c b/arch/powerpc/platforms/powermac/pmac_setup.c new file mode 100644 index 00000000000..dbc921a084c --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_setup.c @@ -0,0 +1,662 @@ +/* + * arch/ppc/platforms/setup.c + * + * PowerPC version + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Adapted for Power Macintosh by Paul Mackerras + * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au) + * + * Derived from "arch/alpha/kernel/setup.c" + * Copyright (C) 1995 Linus Torvalds + * + * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +/* + * bootup setup stuff.. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pmac_pic.h" + +#undef SHOW_GATWICK_IRQS + +extern long pmac_time_init(void); +extern unsigned long pmac_get_rtc_time(void); +extern int pmac_set_rtc_time(unsigned long nowtime); +extern void pmac_read_rtc_time(void); +extern void pmac_calibrate_decr(void); +extern void pmac_pcibios_fixup(void); +extern void pmac_find_bridges(void); +extern unsigned long pmac_ide_get_base(int index); +extern void pmac_ide_init_hwif_ports(hw_regs_t *hw, + unsigned long data_port, unsigned long ctrl_port, int *irq); + +extern void pmac_nvram_update(void); +extern unsigned char pmac_nvram_read_byte(int addr); +extern void pmac_nvram_write_byte(int addr, unsigned char val); +extern int pmac_pci_enable_device_hook(struct pci_dev *dev, int initial); +extern void pmac_pcibios_after_init(void); +extern int of_show_percpuinfo(struct seq_file *m, int i); + +unsigned char drive_info; + +int ppc_override_l2cr = 0; +int ppc_override_l2cr_value; +int has_l2cache = 0; + +static int current_root_goodness = -1; + +extern int pmac_newworld; + +#define DEFAULT_ROOT_DEVICE Root_SDA1 /* sda1 - slightly silly choice */ + +extern void zs_kgdb_hook(int tty_num); +static void ohare_init(void); +#ifdef CONFIG_BOOTX_TEXT +static void pmac_progress(char *s, unsigned short hex); +#endif + +sys_ctrler_t sys_ctrler = SYS_CTRLER_UNKNOWN; + +#ifdef CONFIG_SMP +extern struct smp_ops_t psurge_smp_ops; +extern struct smp_ops_t core99_smp_ops; +#endif /* CONFIG_SMP */ + +static int +pmac_show_cpuinfo(struct seq_file *m) +{ + struct device_node *np; + char *pp; + int plen; + int mbmodel = pmac_call_feature(PMAC_FTR_GET_MB_INFO, + NULL, PMAC_MB_INFO_MODEL, 0); + unsigned int mbflags = (unsigned int)pmac_call_feature(PMAC_FTR_GET_MB_INFO, + NULL, PMAC_MB_INFO_FLAGS, 0); + char* mbname; + + if (pmac_call_feature(PMAC_FTR_GET_MB_INFO, NULL, PMAC_MB_INFO_NAME, (int)&mbname) != 0) + mbname = "Unknown"; + + /* find motherboard type */ + seq_printf(m, "machine\t\t: "); + np = find_devices("device-tree"); + if (np != NULL) { + pp = (char *) get_property(np, "model", NULL); + if (pp != NULL) + seq_printf(m, "%s\n", pp); + else + seq_printf(m, "PowerMac\n"); + pp = (char *) get_property(np, "compatible", &plen); + if (pp != NULL) { + seq_printf(m, "motherboard\t:"); + while (plen > 0) { + int l = strlen(pp) + 1; + seq_printf(m, " %s", pp); + plen -= l; + pp += l; + } + seq_printf(m, "\n"); + } + } else + seq_printf(m, "PowerMac\n"); + + /* print parsed model */ + seq_printf(m, "detected as\t: %d (%s)\n", mbmodel, mbname); + seq_printf(m, "pmac flags\t: %08x\n", mbflags); + + /* find l2 cache info */ + np = find_devices("l2-cache"); + if (np == 0) + np = find_type_devices("cache"); + if (np != 0) { + unsigned int *ic = (unsigned int *) + get_property(np, "i-cache-size", NULL); + unsigned int *dc = (unsigned int *) + get_property(np, "d-cache-size", NULL); + seq_printf(m, "L2 cache\t:"); + has_l2cache = 1; + if (get_property(np, "cache-unified", NULL) != 0 && dc) { + seq_printf(m, " %dK unified", *dc / 1024); + } else { + if (ic) + seq_printf(m, " %dK instruction", *ic / 1024); + if (dc) + seq_printf(m, "%s %dK data", + (ic? " +": ""), *dc / 1024); + } + pp = get_property(np, "ram-type", NULL); + if (pp) + seq_printf(m, " %s", pp); + seq_printf(m, "\n"); + } + + /* find ram info */ + np = find_devices("memory"); + if (np != 0) { + int n; + struct reg_property *reg = (struct reg_property *) + get_property(np, "reg", &n); + + if (reg != 0) { + unsigned long total = 0; + + for (n /= sizeof(struct reg_property); n > 0; --n) + total += (reg++)->size; + seq_printf(m, "memory\t\t: %luMB\n", total >> 20); + } + } + + /* Checks "l2cr-value" property in the registry */ + np = find_devices("cpus"); + if (np == 0) + np = find_type_devices("cpu"); + if (np != 0) { + unsigned int *l2cr = (unsigned int *) + get_property(np, "l2cr-value", NULL); + if (l2cr != 0) { + seq_printf(m, "l2cr override\t: 0x%x\n", *l2cr); + } + } + + /* Indicate newworld/oldworld */ + seq_printf(m, "pmac-generation\t: %s\n", + pmac_newworld ? "NewWorld" : "OldWorld"); + + + return 0; +} + +static int +pmac_show_percpuinfo(struct seq_file *m, int i) +{ +#ifdef CONFIG_CPU_FREQ_PMAC + extern unsigned int pmac_get_one_cpufreq(int i); + unsigned int freq = pmac_get_one_cpufreq(i); + if (freq != 0) { + seq_printf(m, "clock\t\t: %dMHz\n", freq/1000); + return 0; + } +#endif /* CONFIG_CPU_FREQ_PMAC */ + return of_show_percpuinfo(m, i); +} + +static volatile u32 *sysctrl_regs; + +void __init +pmac_setup_arch(void) +{ + struct device_node *cpu; + int *fp; + unsigned long pvr; + + pvr = PVR_VER(mfspr(SPRN_PVR)); + + /* Set loops_per_jiffy to a half-way reasonable value, + for use until calibrate_delay gets called. */ + cpu = find_type_devices("cpu"); + if (cpu != 0) { + fp = (int *) get_property(cpu, "clock-frequency", NULL); + if (fp != 0) { + if (pvr == 4 || pvr >= 8) + /* 604, G3, G4 etc. */ + loops_per_jiffy = *fp / HZ; + else + /* 601, 603, etc. */ + loops_per_jiffy = *fp / (2*HZ); + } else + loops_per_jiffy = 50000000 / HZ; + } + + /* this area has the CPU identification register + and some registers used by smp boards */ + sysctrl_regs = (volatile u32 *) ioremap(0xf8000000, 0x1000); + ohare_init(); + + /* Lookup PCI hosts */ + pmac_find_bridges(); + + /* Checks "l2cr-value" property in the registry */ + if (cpu_has_feature(CPU_FTR_L2CR)) { + struct device_node *np = find_devices("cpus"); + if (np == 0) + np = find_type_devices("cpu"); + if (np != 0) { + unsigned int *l2cr = (unsigned int *) + get_property(np, "l2cr-value", NULL); + if (l2cr != 0) { + ppc_override_l2cr = 1; + ppc_override_l2cr_value = *l2cr; + _set_L2CR(0); + _set_L2CR(ppc_override_l2cr_value); + } + } + } + + if (ppc_override_l2cr) + printk(KERN_INFO "L2CR overriden (0x%x), backside cache is %s\n", + ppc_override_l2cr_value, (ppc_override_l2cr_value & 0x80000000) + ? "enabled" : "disabled"); + +#ifdef CONFIG_KGDB + zs_kgdb_hook(0); +#endif + +#ifdef CONFIG_ADB_CUDA + find_via_cuda(); +#else + if (find_devices("via-cuda")) { + printk("WARNING ! Your machine is Cuda based but your kernel\n"); + printk(" wasn't compiled with CONFIG_ADB_CUDA option !\n"); + } +#endif +#ifdef CONFIG_ADB_PMU + find_via_pmu(); +#else + if (find_devices("via-pmu")) { + printk("WARNING ! Your machine is PMU based but your kernel\n"); + printk(" wasn't compiled with CONFIG_ADB_PMU option !\n"); + } +#endif +#ifdef CONFIG_NVRAM + pmac_nvram_init(); +#endif +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = Root_RAM0; + else +#endif + ROOT_DEV = DEFAULT_ROOT_DEVICE; + +#ifdef CONFIG_SMP + /* Check for Core99 */ + if (find_devices("uni-n") || find_devices("u3")) + ppc_md.smp_ops = &core99_smp_ops; + else + ppc_md.smp_ops = &psurge_smp_ops; +#endif /* CONFIG_SMP */ + + pci_create_OF_bus_map(); +} + +static void __init ohare_init(void) +{ + /* + * Turn on the L2 cache. + * We assume that we have a PSX memory controller iff + * we have an ohare I/O controller. + */ + if (find_devices("ohare") != NULL) { + if (((sysctrl_regs[2] >> 24) & 0xf) >= 3) { + if (sysctrl_regs[4] & 0x10) + sysctrl_regs[4] |= 0x04000020; + else + sysctrl_regs[4] |= 0x04000000; + if(has_l2cache) + printk(KERN_INFO "Level 2 cache enabled\n"); + } + } +} + +extern char *bootpath; +extern char *bootdevice; +void *boot_host; +int boot_target; +int boot_part; +extern dev_t boot_dev; + +#ifdef CONFIG_SCSI +void __init +note_scsi_host(struct device_node *node, void *host) +{ + int l; + char *p; + + l = strlen(node->full_name); + if (bootpath != NULL && bootdevice != NULL + && strncmp(node->full_name, bootdevice, l) == 0 + && (bootdevice[l] == '/' || bootdevice[l] == 0)) { + boot_host = host; + /* + * There's a bug in OF 1.0.5. (Why am I not surprised.) + * If you pass a path like scsi/sd@1:0 to canon, it returns + * something like /bandit@F2000000/gc@10/53c94@10000/sd@0,0 + * That is, the scsi target number doesn't get preserved. + * So we pick the target number out of bootpath and use that. + */ + p = strstr(bootpath, "/sd@"); + if (p != NULL) { + p += 4; + boot_target = simple_strtoul(p, NULL, 10); + p = strchr(p, ':'); + if (p != NULL) + boot_part = simple_strtoul(p + 1, NULL, 10); + } + } +} +#endif + +#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC) +static dev_t __init +find_ide_boot(void) +{ + char *p; + int n; + dev_t __init pmac_find_ide_boot(char *bootdevice, int n); + + if (bootdevice == NULL) + return 0; + p = strrchr(bootdevice, '/'); + if (p == NULL) + return 0; + n = p - bootdevice; + + return pmac_find_ide_boot(bootdevice, n); +} +#endif /* CONFIG_BLK_DEV_IDE && CONFIG_BLK_DEV_IDE_PMAC */ + +static void __init +find_boot_device(void) +{ +#if defined(CONFIG_BLK_DEV_IDE) && defined(CONFIG_BLK_DEV_IDE_PMAC) + boot_dev = find_ide_boot(); +#endif +} + +static int initializing = 1; +/* TODO: Merge the suspend-to-ram with the common code !!! + * currently, this is a stub implementation for suspend-to-disk + * only + */ + +#ifdef CONFIG_SOFTWARE_SUSPEND + +static int pmac_pm_prepare(suspend_state_t state) +{ + printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state); + + return 0; +} + +static int pmac_pm_enter(suspend_state_t state) +{ + printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state); + + /* Giveup the lazy FPU & vec so we don't have to back them + * up from the low level code + */ + enable_kernel_fp(); + +#ifdef CONFIG_ALTIVEC + if (cur_cpu_spec[0]->cpu_features & CPU_FTR_ALTIVEC) + enable_kernel_altivec(); +#endif /* CONFIG_ALTIVEC */ + + return 0; +} + +static int pmac_pm_finish(suspend_state_t state) +{ + printk(KERN_DEBUG "%s(%d)\n", __FUNCTION__, state); + + /* Restore userland MMU context */ + set_context(current->active_mm->context, current->active_mm->pgd); + + return 0; +} + +static struct pm_ops pmac_pm_ops = { + .pm_disk_mode = PM_DISK_SHUTDOWN, + .prepare = pmac_pm_prepare, + .enter = pmac_pm_enter, + .finish = pmac_pm_finish, +}; + +#endif /* CONFIG_SOFTWARE_SUSPEND */ + +static int pmac_late_init(void) +{ + initializing = 0; +#ifdef CONFIG_SOFTWARE_SUSPEND + pm_set_ops(&pmac_pm_ops); +#endif /* CONFIG_SOFTWARE_SUSPEND */ + return 0; +} + +late_initcall(pmac_late_init); + +/* can't be __init - can be called whenever a disk is first accessed */ +void +note_bootable_part(dev_t dev, int part, int goodness) +{ + static int found_boot = 0; + char *p; + + if (!initializing) + return; + if ((goodness <= current_root_goodness) && + ROOT_DEV != DEFAULT_ROOT_DEVICE) + return; + p = strstr(saved_command_line, "root="); + if (p != NULL && (p == saved_command_line || p[-1] == ' ')) + return; + + if (!found_boot) { + find_boot_device(); + found_boot = 1; + } + if (!boot_dev || dev == boot_dev) { + ROOT_DEV = dev + part; + boot_dev = 0; + current_root_goodness = goodness; + } +} + +static void +pmac_restart(char *cmd) +{ +#ifdef CONFIG_ADB_CUDA + struct adb_request req; +#endif /* CONFIG_ADB_CUDA */ + + switch (sys_ctrler) { +#ifdef CONFIG_ADB_CUDA + case SYS_CTRLER_CUDA: + cuda_request(&req, NULL, 2, CUDA_PACKET, + CUDA_RESET_SYSTEM); + for (;;) + cuda_poll(); + break; +#endif /* CONFIG_ADB_CUDA */ +#ifdef CONFIG_ADB_PMU + case SYS_CTRLER_PMU: + pmu_restart(); + break; +#endif /* CONFIG_ADB_PMU */ + default: ; + } +} + +static void +pmac_power_off(void) +{ +#ifdef CONFIG_ADB_CUDA + struct adb_request req; +#endif /* CONFIG_ADB_CUDA */ + + switch (sys_ctrler) { +#ifdef CONFIG_ADB_CUDA + case SYS_CTRLER_CUDA: + cuda_request(&req, NULL, 2, CUDA_PACKET, + CUDA_POWERDOWN); + for (;;) + cuda_poll(); + break; +#endif /* CONFIG_ADB_CUDA */ +#ifdef CONFIG_ADB_PMU + case SYS_CTRLER_PMU: + pmu_shutdown(); + break; +#endif /* CONFIG_ADB_PMU */ + default: ; + } +} + +static void +pmac_halt(void) +{ + pmac_power_off(); +} + +void __init +pmac_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + /* isa_io_base gets set in pmac_find_bridges */ + isa_mem_base = PMAC_ISA_MEM_BASE; + pci_dram_offset = PMAC_PCI_DRAM_OFFSET; + ISA_DMA_THRESHOLD = ~0L; + DMA_MODE_READ = 1; + DMA_MODE_WRITE = 2; + + ppc_md.setup_arch = pmac_setup_arch; + ppc_md.show_cpuinfo = pmac_show_cpuinfo; + ppc_md.show_percpuinfo = pmac_show_percpuinfo; + ppc_md.irq_canonicalize = NULL; + ppc_md.init_IRQ = pmac_pic_init; + ppc_md.get_irq = pmac_get_irq; /* Changed later on ... */ + + ppc_md.pcibios_fixup = pmac_pcibios_fixup; + ppc_md.pcibios_enable_device_hook = pmac_pci_enable_device_hook; + ppc_md.pcibios_after_init = pmac_pcibios_after_init; + ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; + + ppc_md.restart = pmac_restart; + ppc_md.power_off = pmac_power_off; + ppc_md.halt = pmac_halt; + + ppc_md.time_init = pmac_time_init; + ppc_md.set_rtc_time = pmac_set_rtc_time; + ppc_md.get_rtc_time = pmac_get_rtc_time; + ppc_md.calibrate_decr = pmac_calibrate_decr; + + ppc_md.feature_call = pmac_do_feature_call; + +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) +#ifdef CONFIG_BLK_DEV_IDE_PMAC + ppc_ide_md.ide_init_hwif = pmac_ide_init_hwif_ports; + ppc_ide_md.default_io_base = pmac_ide_get_base; +#endif /* CONFIG_BLK_DEV_IDE_PMAC */ +#endif /* defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE) */ + +#ifdef CONFIG_BOOTX_TEXT + ppc_md.progress = pmac_progress; +#endif /* CONFIG_BOOTX_TEXT */ + + if (ppc_md.progress) ppc_md.progress("pmac_init(): exit", 0); + +} + +#ifdef CONFIG_BOOTX_TEXT +static void __init +pmac_progress(char *s, unsigned short hex) +{ + if (boot_text_mapped) { + btext_drawstring(s); + btext_drawchar('\n'); + } +} +#endif /* CONFIG_BOOTX_TEXT */ + +static int __init +pmac_declare_of_platform_devices(void) +{ + struct device_node *np; + + np = find_devices("uni-n"); + if (np) { + for (np = np->child; np != NULL; np = np->sibling) + if (strncmp(np->name, "i2c", 3) == 0) { + of_platform_device_create(np, "uni-n-i2c", + NULL); + break; + } + } + np = find_devices("u3"); + if (np) { + for (np = np->child; np != NULL; np = np->sibling) + if (strncmp(np->name, "i2c", 3) == 0) { + of_platform_device_create(np, "u3-i2c", + NULL); + break; + } + } + + np = find_devices("valkyrie"); + if (np) + of_platform_device_create(np, "valkyrie", NULL); + np = find_devices("platinum"); + if (np) + of_platform_device_create(np, "platinum", NULL); + + return 0; +} + +device_initcall(pmac_declare_of_platform_devices); diff --git a/arch/powerpc/platforms/powermac/pmac_sleep.S b/arch/powerpc/platforms/powermac/pmac_sleep.S new file mode 100644 index 00000000000..88419c77ac4 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_sleep.S @@ -0,0 +1,396 @@ +/* + * This file contains sleep low-level functions for PowerBook G3. + * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org) + * and Paul Mackerras (paulus@samba.org). + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAGIC 0x4c617273 /* 'Lars' */ + +/* + * Structure for storing CPU registers on the stack. + */ +#define SL_SP 0 +#define SL_PC 4 +#define SL_MSR 8 +#define SL_SDR1 0xc +#define SL_SPRG0 0x10 /* 4 sprg's */ +#define SL_DBAT0 0x20 +#define SL_IBAT0 0x28 +#define SL_DBAT1 0x30 +#define SL_IBAT1 0x38 +#define SL_DBAT2 0x40 +#define SL_IBAT2 0x48 +#define SL_DBAT3 0x50 +#define SL_IBAT3 0x58 +#define SL_TB 0x60 +#define SL_R2 0x68 +#define SL_CR 0x6c +#define SL_R12 0x70 /* r12 to r31 */ +#define SL_SIZE (SL_R12 + 80) + + .section .text + .align 5 + +#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) + +/* This gets called by via-pmu.c late during the sleep process. + * The PMU was already send the sleep command and will shut us down + * soon. We need to save all that is needed and setup the wakeup + * vector that will be called by the ROM on wakeup + */ +_GLOBAL(low_sleep_handler) +#ifndef CONFIG_6xx + blr +#else + mflr r0 + stw r0,4(r1) + stwu r1,-SL_SIZE(r1) + mfcr r0 + stw r0,SL_CR(r1) + stw r2,SL_R2(r1) + stmw r12,SL_R12(r1) + + /* Save MSR & SDR1 */ + mfmsr r4 + stw r4,SL_MSR(r1) + mfsdr1 r4 + stw r4,SL_SDR1(r1) + + /* Get a stable timebase and save it */ +1: mftbu r4 + stw r4,SL_TB(r1) + mftb r5 + stw r5,SL_TB+4(r1) + mftbu r3 + cmpw r3,r4 + bne 1b + + /* Save SPRGs */ + mfsprg r4,0 + stw r4,SL_SPRG0(r1) + mfsprg r4,1 + stw r4,SL_SPRG0+4(r1) + mfsprg r4,2 + stw r4,SL_SPRG0+8(r1) + mfsprg r4,3 + stw r4,SL_SPRG0+12(r1) + + /* Save BATs */ + mfdbatu r4,0 + stw r4,SL_DBAT0(r1) + mfdbatl r4,0 + stw r4,SL_DBAT0+4(r1) + mfdbatu r4,1 + stw r4,SL_DBAT1(r1) + mfdbatl r4,1 + stw r4,SL_DBAT1+4(r1) + mfdbatu r4,2 + stw r4,SL_DBAT2(r1) + mfdbatl r4,2 + stw r4,SL_DBAT2+4(r1) + mfdbatu r4,3 + stw r4,SL_DBAT3(r1) + mfdbatl r4,3 + stw r4,SL_DBAT3+4(r1) + mfibatu r4,0 + stw r4,SL_IBAT0(r1) + mfibatl r4,0 + stw r4,SL_IBAT0+4(r1) + mfibatu r4,1 + stw r4,SL_IBAT1(r1) + mfibatl r4,1 + stw r4,SL_IBAT1+4(r1) + mfibatu r4,2 + stw r4,SL_IBAT2(r1) + mfibatl r4,2 + stw r4,SL_IBAT2+4(r1) + mfibatu r4,3 + stw r4,SL_IBAT3(r1) + mfibatl r4,3 + stw r4,SL_IBAT3+4(r1) + + /* Backup various CPU config stuffs */ + bl __save_cpu_setup + + /* The ROM can wake us up via 2 different vectors: + * - On wallstreet & lombard, we must write a magic + * value 'Lars' at address 4 and a pointer to a + * memory location containing the PC to resume from + * at address 0. + * - On Core99, we must store the wakeup vector at + * address 0x80 and eventually it's parameters + * at address 0x84. I've have some trouble with those + * parameters however and I no longer use them. + */ + lis r5,grackle_wake_up@ha + addi r5,r5,grackle_wake_up@l + tophys(r5,r5) + stw r5,SL_PC(r1) + lis r4,KERNELBASE@h + tophys(r5,r1) + addi r5,r5,SL_PC + lis r6,MAGIC@ha + addi r6,r6,MAGIC@l + stw r5,0(r4) + stw r6,4(r4) + /* Setup stuffs at 0x80-0x84 for Core99 */ + lis r3,core99_wake_up@ha + addi r3,r3,core99_wake_up@l + tophys(r3,r3) + stw r3,0x80(r4) + stw r5,0x84(r4) + /* Store a pointer to our backup storage into + * a kernel global + */ + lis r3,sleep_storage@ha + addi r3,r3,sleep_storage@l + stw r5,0(r3) + + .globl low_cpu_die +low_cpu_die: + /* Flush & disable all caches */ + bl flush_disable_caches + + /* Turn off data relocation. */ + mfmsr r3 /* Save MSR in r7 */ + rlwinm r3,r3,0,28,26 /* Turn off DR bit */ + sync + mtmsr r3 + isync + +BEGIN_FTR_SECTION + /* Flush any pending L2 data prefetches to work around HW bug */ + sync + lis r3,0xfff0 + lwz r0,0(r3) /* perform cache-inhibited load to ROM */ + sync /* (caches are disabled at this point) */ +END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) + +/* + * Set the HID0 and MSR for sleep. + */ + mfspr r2,SPRN_HID0 + rlwinm r2,r2,0,10,7 /* clear doze, nap */ + oris r2,r2,HID0_SLEEP@h + sync + isync + mtspr SPRN_HID0,r2 + sync + +/* This loop puts us back to sleep in case we have a spurrious + * wakeup so that the host bridge properly stays asleep. The + * CPU will be turned off, either after a known time (about 1 + * second) on wallstreet & lombard, or as soon as the CPU enters + * SLEEP mode on core99 + */ + mfmsr r2 + oris r2,r2,MSR_POW@h +1: sync + mtmsr r2 + isync + b 1b + +/* + * Here is the resume code. + */ + + +/* + * Core99 machines resume here + * r4 has the physical address of SL_PC(sp) (unused) + */ +_GLOBAL(core99_wake_up) + /* Make sure HID0 no longer contains any sleep bit and that data cache + * is disabled + */ + mfspr r3,SPRN_HID0 + rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */ + rlwinm 3,r3,0,18,15 /* clear DCE, ICE */ + mtspr SPRN_HID0,r3 + sync + isync + + /* sanitize MSR */ + mfmsr r3 + ori r3,r3,MSR_EE|MSR_IP + xori r3,r3,MSR_EE|MSR_IP + sync + isync + mtmsr r3 + sync + isync + + /* Recover sleep storage */ + lis r3,sleep_storage@ha + addi r3,r3,sleep_storage@l + tophys(r3,r3) + lwz r1,0(r3) + + /* Pass thru to older resume code ... */ +/* + * Here is the resume code for older machines. + * r1 has the physical address of SL_PC(sp). + */ + +grackle_wake_up: + + /* Restore the kernel's segment registers before + * we do any r1 memory access as we are not sure they + * are in a sane state above the first 256Mb region + */ + li r0,16 /* load up segment register values */ + mtctr r0 /* for context 0 */ + lis r3,0x2000 /* Ku = 1, VSID = 0 */ + li r4,0 +3: mtsrin r3,r4 + addi r3,r3,0x111 /* increment VSID */ + addis r4,r4,0x1000 /* address of next segment */ + bdnz 3b + sync + isync + + subi r1,r1,SL_PC + + /* Restore various CPU config stuffs */ + bl __restore_cpu_setup + + /* Make sure all FPRs have been initialized */ + bl reloc_offset + bl __init_fpu_registers + + /* Invalidate & enable L1 cache, we don't care about + * whatever the ROM may have tried to write to memory + */ + bl __inval_enable_L1 + + /* Restore the BATs, and SDR1. Then we can turn on the MMU. */ + lwz r4,SL_SDR1(r1) + mtsdr1 r4 + lwz r4,SL_SPRG0(r1) + mtsprg 0,r4 + lwz r4,SL_SPRG0+4(r1) + mtsprg 1,r4 + lwz r4,SL_SPRG0+8(r1) + mtsprg 2,r4 + lwz r4,SL_SPRG0+12(r1) + mtsprg 3,r4 + + lwz r4,SL_DBAT0(r1) + mtdbatu 0,r4 + lwz r4,SL_DBAT0+4(r1) + mtdbatl 0,r4 + lwz r4,SL_DBAT1(r1) + mtdbatu 1,r4 + lwz r4,SL_DBAT1+4(r1) + mtdbatl 1,r4 + lwz r4,SL_DBAT2(r1) + mtdbatu 2,r4 + lwz r4,SL_DBAT2+4(r1) + mtdbatl 2,r4 + lwz r4,SL_DBAT3(r1) + mtdbatu 3,r4 + lwz r4,SL_DBAT3+4(r1) + mtdbatl 3,r4 + lwz r4,SL_IBAT0(r1) + mtibatu 0,r4 + lwz r4,SL_IBAT0+4(r1) + mtibatl 0,r4 + lwz r4,SL_IBAT1(r1) + mtibatu 1,r4 + lwz r4,SL_IBAT1+4(r1) + mtibatl 1,r4 + lwz r4,SL_IBAT2(r1) + mtibatu 2,r4 + lwz r4,SL_IBAT2+4(r1) + mtibatl 2,r4 + lwz r4,SL_IBAT3(r1) + mtibatu 3,r4 + lwz r4,SL_IBAT3+4(r1) + mtibatl 3,r4 + +BEGIN_FTR_SECTION + li r4,0 + mtspr SPRN_DBAT4U,r4 + mtspr SPRN_DBAT4L,r4 + mtspr SPRN_DBAT5U,r4 + mtspr SPRN_DBAT5L,r4 + mtspr SPRN_DBAT6U,r4 + mtspr SPRN_DBAT6L,r4 + mtspr SPRN_DBAT7U,r4 + mtspr SPRN_DBAT7L,r4 + mtspr SPRN_IBAT4U,r4 + mtspr SPRN_IBAT4L,r4 + mtspr SPRN_IBAT5U,r4 + mtspr SPRN_IBAT5L,r4 + mtspr SPRN_IBAT6U,r4 + mtspr SPRN_IBAT6L,r4 + mtspr SPRN_IBAT7U,r4 + mtspr SPRN_IBAT7L,r4 +END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) + + /* Flush all TLBs */ + lis r4,0x1000 +1: addic. r4,r4,-0x1000 + tlbie r4 + blt 1b + sync + + /* restore the MSR and turn on the MMU */ + lwz r3,SL_MSR(r1) + bl turn_on_mmu + + /* get back the stack pointer */ + tovirt(r1,r1) + + /* Restore TB */ + li r3,0 + mttbl r3 + lwz r3,SL_TB(r1) + lwz r4,SL_TB+4(r1) + mttbu r3 + mttbl r4 + + /* Restore the callee-saved registers and return */ + lwz r0,SL_CR(r1) + mtcr r0 + lwz r2,SL_R2(r1) + lmw r12,SL_R12(r1) + addi r1,r1,SL_SIZE + lwz r0,4(r1) + mtlr r0 + blr + +turn_on_mmu: + mflr r4 + tovirt(r4,r4) + mtsrr0 r4 + mtsrr1 r3 + sync + isync + rfi + +#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */ + + .section .data + .balign L1_CACHE_LINE_SIZE +sleep_storage: + .long 0 + .balign L1_CACHE_LINE_SIZE, 0 + +#endif /* CONFIG_6xx */ + .section .text diff --git a/arch/powerpc/platforms/powermac/pmac_smp.c b/arch/powerpc/platforms/powermac/pmac_smp.c new file mode 100644 index 00000000000..995e9095d86 --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_smp.c @@ -0,0 +1,716 @@ +/* + * SMP support for power macintosh. + * + * We support both the old "powersurge" SMP architecture + * and the current Core99 (G4 PowerMac) machines. + * + * Note that we don't support the very first rev. of + * Apple/DayStar 2 CPUs board, the one with the funky + * watchdog. Hopefully, none of these should be there except + * maybe internally to Apple. I should probably still add some + * code to detect this card though and disable SMP. --BenH. + * + * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) + * and Ben Herrenschmidt . + * + * Support for DayStar quad CPU cards + * Copyright (C) XLR8, Inc. 1994-2000 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Powersurge (old powermac SMP) support. + */ + +extern void __secondary_start_pmac_0(void); + +/* Addresses for powersurge registers */ +#define HAMMERHEAD_BASE 0xf8000000 +#define HHEAD_CONFIG 0x90 +#define HHEAD_SEC_INTR 0xc0 + +/* register for interrupting the primary processor on the powersurge */ +/* N.B. this is actually the ethernet ROM! */ +#define PSURGE_PRI_INTR 0xf3019000 + +/* register for storing the start address for the secondary processor */ +/* N.B. this is the PCI config space address register for the 1st bridge */ +#define PSURGE_START 0xf2800000 + +/* Daystar/XLR8 4-CPU card */ +#define PSURGE_QUAD_REG_ADDR 0xf8800000 + +#define PSURGE_QUAD_IRQ_SET 0 +#define PSURGE_QUAD_IRQ_CLR 1 +#define PSURGE_QUAD_IRQ_PRIMARY 2 +#define PSURGE_QUAD_CKSTOP_CTL 3 +#define PSURGE_QUAD_PRIMARY_ARB 4 +#define PSURGE_QUAD_BOARD_ID 6 +#define PSURGE_QUAD_WHICH_CPU 7 +#define PSURGE_QUAD_CKSTOP_RDBK 8 +#define PSURGE_QUAD_RESET_CTL 11 + +#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) +#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) +#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) +#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) + +/* virtual addresses for the above */ +static volatile u8 __iomem *hhead_base; +static volatile u8 __iomem *quad_base; +static volatile u32 __iomem *psurge_pri_intr; +static volatile u8 __iomem *psurge_sec_intr; +static volatile u32 __iomem *psurge_start; + +/* values for psurge_type */ +#define PSURGE_NONE -1 +#define PSURGE_DUAL 0 +#define PSURGE_QUAD_OKEE 1 +#define PSURGE_QUAD_COTTON 2 +#define PSURGE_QUAD_ICEGRASS 3 + +/* what sort of powersurge board we have */ +static int psurge_type = PSURGE_NONE; + +/* L2 and L3 cache settings to pass from CPU0 to CPU1 */ +volatile static long int core99_l2_cache; +volatile static long int core99_l3_cache; + +/* Timebase freeze GPIO */ +static unsigned int core99_tb_gpio; + +/* Sync flag for HW tb sync */ +static volatile int sec_tb_reset = 0; +static unsigned int pri_tb_hi, pri_tb_lo; +static unsigned int pri_tb_stamp; + +static void __devinit core99_init_caches(int cpu) +{ + if (!cpu_has_feature(CPU_FTR_L2CR)) + return; + + if (cpu == 0) { + core99_l2_cache = _get_L2CR(); + printk("CPU0: L2CR is %lx\n", core99_l2_cache); + } else { + printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); + _set_L2CR(0); + _set_L2CR(core99_l2_cache); + printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); + } + + if (!cpu_has_feature(CPU_FTR_L3CR)) + return; + + if (cpu == 0){ + core99_l3_cache = _get_L3CR(); + printk("CPU0: L3CR is %lx\n", core99_l3_cache); + } else { + printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); + _set_L3CR(0); + _set_L3CR(core99_l3_cache); + printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); + } +} + +/* + * Set and clear IPIs for powersurge. + */ +static inline void psurge_set_ipi(int cpu) +{ + if (psurge_type == PSURGE_NONE) + return; + if (cpu == 0) + in_be32(psurge_pri_intr); + else if (psurge_type == PSURGE_DUAL) + out_8(psurge_sec_intr, 0); + else + PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); +} + +static inline void psurge_clr_ipi(int cpu) +{ + if (cpu > 0) { + switch(psurge_type) { + case PSURGE_DUAL: + out_8(psurge_sec_intr, ~0); + case PSURGE_NONE: + break; + default: + PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); + } + } +} + +/* + * On powersurge (old SMP powermac architecture) we don't have + * separate IPIs for separate messages like openpic does. Instead + * we have a bitmap for each processor, where a 1 bit means that + * the corresponding message is pending for that processor. + * Ideally each cpu's entry would be in a different cache line. + * -- paulus. + */ +static unsigned long psurge_smp_message[NR_CPUS]; + +void psurge_smp_message_recv(struct pt_regs *regs) +{ + int cpu = smp_processor_id(); + int msg; + + /* clear interrupt */ + psurge_clr_ipi(cpu); + + if (num_online_cpus() < 2) + return; + + /* make sure there is a message there */ + for (msg = 0; msg < 4; msg++) + if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) + smp_message_recv(msg, regs); +} + +irqreturn_t psurge_primary_intr(int irq, void *d, struct pt_regs *regs) +{ + psurge_smp_message_recv(regs); + return IRQ_HANDLED; +} + +static void smp_psurge_message_pass(int target, int msg, unsigned long data, + int wait) +{ + int i; + + if (num_online_cpus() < 2) + return; + + for (i = 0; i < NR_CPUS; i++) { + if (!cpu_online(i)) + continue; + if (target == MSG_ALL + || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) + || target == i) { + set_bit(msg, &psurge_smp_message[i]); + psurge_set_ipi(i); + } + } +} + +/* + * Determine a quad card presence. We read the board ID register, we + * force the data bus to change to something else, and we read it again. + * It it's stable, then the register probably exist (ugh !) + */ +static int __init psurge_quad_probe(void) +{ + int type; + unsigned int i; + + type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); + if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS + || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) + return PSURGE_DUAL; + + /* looks OK, try a slightly more rigorous test */ + /* bogus is not necessarily cacheline-aligned, + though I don't suppose that really matters. -- paulus */ + for (i = 0; i < 100; i++) { + volatile u32 bogus[8]; + bogus[(0+i)%8] = 0x00000000; + bogus[(1+i)%8] = 0x55555555; + bogus[(2+i)%8] = 0xFFFFFFFF; + bogus[(3+i)%8] = 0xAAAAAAAA; + bogus[(4+i)%8] = 0x33333333; + bogus[(5+i)%8] = 0xCCCCCCCC; + bogus[(6+i)%8] = 0xCCCCCCCC; + bogus[(7+i)%8] = 0x33333333; + wmb(); + asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); + mb(); + if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) + return PSURGE_DUAL; + } + return type; +} + +static void __init psurge_quad_init(void) +{ + int procbits; + + if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); + procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); + if (psurge_type == PSURGE_QUAD_ICEGRASS) + PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); + else + PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); + mdelay(33); + out_8(psurge_sec_intr, ~0); + PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); + PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); + if (psurge_type != PSURGE_QUAD_ICEGRASS) + PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); + PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); + mdelay(33); + PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); + mdelay(33); + PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); + mdelay(33); +} + +static int __init smp_psurge_probe(void) +{ + int i, ncpus; + + /* We don't do SMP on the PPC601 -- paulus */ + if (PVR_VER(mfspr(SPRN_PVR)) == 1) + return 1; + + /* + * The powersurge cpu board can be used in the generation + * of powermacs that have a socket for an upgradeable cpu card, + * including the 7500, 8500, 9500, 9600. + * The device tree doesn't tell you if you have 2 cpus because + * OF doesn't know anything about the 2nd processor. + * Instead we look for magic bits in magic registers, + * in the hammerhead memory controller in the case of the + * dual-cpu powersurge board. -- paulus. + */ + if (find_devices("hammerhead") == NULL) + return 1; + + hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); + quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); + psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; + + psurge_type = psurge_quad_probe(); + if (psurge_type != PSURGE_DUAL) { + psurge_quad_init(); + /* All released cards using this HW design have 4 CPUs */ + ncpus = 4; + } else { + iounmap(quad_base); + if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { + /* not a dual-cpu card */ + iounmap(hhead_base); + psurge_type = PSURGE_NONE; + return 1; + } + ncpus = 2; + } + + psurge_start = ioremap(PSURGE_START, 4); + psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); + + /* this is not actually strictly necessary -- paulus. */ + for (i = 1; i < ncpus; ++i) + smp_hw_index[i] = i; + + if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); + + return ncpus; +} + +static void __init smp_psurge_kick_cpu(int nr) +{ + unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; + unsigned long a; + + /* may need to flush here if secondary bats aren't setup */ + for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) + asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); + asm volatile("sync"); + + if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); + + out_be32(psurge_start, start); + mb(); + + psurge_set_ipi(nr); + udelay(10); + psurge_clr_ipi(nr); + + if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); +} + +/* + * With the dual-cpu powersurge board, the decrementers and timebases + * of both cpus are frozen after the secondary cpu is started up, + * until we give the secondary cpu another interrupt. This routine + * uses this to get the timebases synchronized. + * -- paulus. + */ +static void __init psurge_dual_sync_tb(int cpu_nr) +{ + int t; + + set_dec(tb_ticks_per_jiffy); + set_tb(0, 0); + last_jiffy_stamp(cpu_nr) = 0; + + if (cpu_nr > 0) { + mb(); + sec_tb_reset = 1; + return; + } + + /* wait for the secondary to have reset its TB before proceeding */ + for (t = 10000000; t > 0 && !sec_tb_reset; --t) + ; + + /* now interrupt the secondary, starting both TBs */ + psurge_set_ipi(1); + + smp_tb_synchronized = 1; +} + +static struct irqaction psurge_irqaction = { + .handler = psurge_primary_intr, + .flags = SA_INTERRUPT, + .mask = CPU_MASK_NONE, + .name = "primary IPI", +}; + +static void __init smp_psurge_setup_cpu(int cpu_nr) +{ + + if (cpu_nr == 0) { + /* If we failed to start the second CPU, we should still + * send it an IPI to start the timebase & DEC or we might + * have them stuck. + */ + if (num_online_cpus() < 2) { + if (psurge_type == PSURGE_DUAL) + psurge_set_ipi(1); + return; + } + /* reset the entry point so if we get another intr we won't + * try to startup again */ + out_be32(psurge_start, 0x100); + if (setup_irq(30, &psurge_irqaction)) + printk(KERN_ERR "Couldn't get primary IPI interrupt"); + } + + if (psurge_type == PSURGE_DUAL) + psurge_dual_sync_tb(cpu_nr); +} + +void __init smp_psurge_take_timebase(void) +{ + /* Dummy implementation */ +} + +void __init smp_psurge_give_timebase(void) +{ + /* Dummy implementation */ +} + +static int __init smp_core99_probe(void) +{ +#ifdef CONFIG_6xx + extern int powersave_nap; +#endif + struct device_node *cpus, *firstcpu; + int i, ncpus = 0, boot_cpu = -1; + u32 *tbprop = NULL; + + if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); + cpus = firstcpu = find_type_devices("cpu"); + while(cpus != NULL) { + u32 *regprop = (u32 *)get_property(cpus, "reg", NULL); + char *stateprop = (char *)get_property(cpus, "state", NULL); + if (regprop != NULL && stateprop != NULL && + !strncmp(stateprop, "running", 7)) + boot_cpu = *regprop; + ++ncpus; + cpus = cpus->next; + } + if (boot_cpu == -1) + printk(KERN_WARNING "Couldn't detect boot CPU !\n"); + if (boot_cpu != 0) + printk(KERN_WARNING "Boot CPU is %d, unsupported setup !\n", boot_cpu); + + if (machine_is_compatible("MacRISC4")) { + extern struct smp_ops_t core99_smp_ops; + + core99_smp_ops.take_timebase = smp_generic_take_timebase; + core99_smp_ops.give_timebase = smp_generic_give_timebase; + } else { + if (firstcpu != NULL) + tbprop = (u32 *)get_property(firstcpu, "timebase-enable", NULL); + if (tbprop) + core99_tb_gpio = *tbprop; + else + core99_tb_gpio = KL_GPIO_TB_ENABLE; + } + + if (ncpus > 1) { + mpic_request_ipis(); + for (i = 1; i < ncpus; ++i) + smp_hw_index[i] = i; +#ifdef CONFIG_6xx + powersave_nap = 0; +#endif + core99_init_caches(0); + } + + return ncpus; +} + +static void __devinit smp_core99_kick_cpu(int nr) +{ + unsigned long save_vector, new_vector; + unsigned long flags; + + volatile unsigned long *vector + = ((volatile unsigned long *)(KERNELBASE+0x100)); + if (nr < 0 || nr > 3) + return; + if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu", 0x346); + + local_irq_save(flags); + local_irq_disable(); + + /* Save reset vector */ + save_vector = *vector; + + /* Setup fake reset vector that does + * b __secondary_start_pmac_0 + nr*8 - KERNELBASE + */ + new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8; + *vector = 0x48000002 + new_vector - KERNELBASE; + + /* flush data cache and inval instruction cache */ + flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); + + /* Put some life in our friend */ + pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); + + /* FIXME: We wait a bit for the CPU to take the exception, I should + * instead wait for the entry code to set something for me. Well, + * ideally, all that crap will be done in prom.c and the CPU left + * in a RAM-based wait loop like CHRP. + */ + mdelay(1); + + /* Restore our exception vector */ + *vector = save_vector; + flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); + + local_irq_restore(flags); + if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); +} + +static void __devinit smp_core99_setup_cpu(int cpu_nr) +{ + /* Setup L2/L3 */ + if (cpu_nr != 0) + core99_init_caches(cpu_nr); + + /* Setup openpic */ + mpic_setup_this_cpu(); + + if (cpu_nr == 0) { +#ifdef CONFIG_POWER4 + extern void g5_phy_disable_cpu1(void); + + /* If we didn't start the second CPU, we must take + * it off the bus + */ + if (machine_is_compatible("MacRISC4") && + num_online_cpus() < 2) + g5_phy_disable_cpu1(); +#endif /* CONFIG_POWER4 */ + if (ppc_md.progress) ppc_md.progress("core99_setup_cpu 0 done", 0x349); + } +} + +/* not __init, called in sleep/wakeup code */ +void smp_core99_take_timebase(void) +{ + unsigned long flags; + + /* tell the primary we're here */ + sec_tb_reset = 1; + mb(); + + /* wait for the primary to set pri_tb_hi/lo */ + while (sec_tb_reset < 2) + mb(); + + /* set our stuff the same as the primary */ + local_irq_save(flags); + set_dec(1); + set_tb(pri_tb_hi, pri_tb_lo); + last_jiffy_stamp(smp_processor_id()) = pri_tb_stamp; + mb(); + + /* tell the primary we're done */ + sec_tb_reset = 0; + mb(); + local_irq_restore(flags); +} + +/* not __init, called in sleep/wakeup code */ +void smp_core99_give_timebase(void) +{ + unsigned long flags; + unsigned int t; + + /* wait for the secondary to be in take_timebase */ + for (t = 100000; t > 0 && !sec_tb_reset; --t) + udelay(10); + if (!sec_tb_reset) { + printk(KERN_WARNING "Timeout waiting sync on second CPU\n"); + return; + } + + /* freeze the timebase and read it */ + /* disable interrupts so the timebase is disabled for the + shortest possible time */ + local_irq_save(flags); + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); + pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); + mb(); + pri_tb_hi = get_tbu(); + pri_tb_lo = get_tbl(); + pri_tb_stamp = last_jiffy_stamp(smp_processor_id()); + mb(); + + /* tell the secondary we're ready */ + sec_tb_reset = 2; + mb(); + + /* wait for the secondary to have taken it */ + for (t = 100000; t > 0 && sec_tb_reset; --t) + udelay(10); + if (sec_tb_reset) + printk(KERN_WARNING "Timeout waiting sync(2) on second CPU\n"); + else + smp_tb_synchronized = 1; + + /* Now, restart the timebase by leaving the GPIO to an open collector */ + pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); + pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); + local_irq_restore(flags); +} + +void smp_core99_message_pass(int target, int msg, unsigned long data, int wait) +{ + cpumask_t mask = CPU_MASK_ALL; + /* make sure we're sending something that translates to an IPI */ + if (msg > 0x3) { + printk("SMP %d: smp_message_pass: unknown msg %d\n", + smp_processor_id(), msg); + return; + } + switch (target) { + case MSG_ALL: + mpic_send_ipi(msg, mask); + break; + case MSG_ALL_BUT_SELF: + cpu_clear(smp_processor_id(), mask); + mpic_send_ipi(msg, mask); + break; + default: + mpic_send_ipi(msg, cpumask_of_cpu(target)); + break; + } +} + + +/* PowerSurge-style Macs */ +struct smp_ops_t psurge_smp_ops = { + .message_pass = smp_psurge_message_pass, + .probe = smp_psurge_probe, + .kick_cpu = smp_psurge_kick_cpu, + .setup_cpu = smp_psurge_setup_cpu, + .give_timebase = smp_psurge_give_timebase, + .take_timebase = smp_psurge_take_timebase, +}; + +/* Core99 Macs (dual G4s) */ +struct smp_ops_t core99_smp_ops = { + .message_pass = smp_core99_message_pass, + .probe = smp_core99_probe, + .kick_cpu = smp_core99_kick_cpu, + .setup_cpu = smp_core99_setup_cpu, + .give_timebase = smp_core99_give_timebase, + .take_timebase = smp_core99_take_timebase, +}; + +#ifdef CONFIG_HOTPLUG_CPU + +int __cpu_disable(void) +{ + cpu_clear(smp_processor_id(), cpu_online_map); + + /* XXX reset cpu affinity here */ + openpic_set_priority(0xf); + asm volatile("mtdec %0" : : "r" (0x7fffffff)); + mb(); + udelay(20); + asm volatile("mtdec %0" : : "r" (0x7fffffff)); + return 0; +} + +extern void low_cpu_die(void) __attribute__((noreturn)); /* in pmac_sleep.S */ +static int cpu_dead[NR_CPUS]; + +void cpu_die(void) +{ + local_irq_disable(); + cpu_dead[smp_processor_id()] = 1; + mb(); + low_cpu_die(); +} + +void __cpu_die(unsigned int cpu) +{ + int timeout; + + timeout = 1000; + while (!cpu_dead[cpu]) { + if (--timeout == 0) { + printk("CPU %u refused to die!\n", cpu); + break; + } + msleep(1); + } + cpu_callin_map[cpu] = 0; + cpu_dead[cpu] = 0; +} + +#endif diff --git a/arch/powerpc/platforms/powermac/pmac_time.c b/arch/powerpc/platforms/powermac/pmac_time.c new file mode 100644 index 00000000000..ff6adff36cb --- /dev/null +++ b/arch/powerpc/platforms/powermac/pmac_time.c @@ -0,0 +1,291 @@ +/* + * Support for periodic interrupts (100 per second) and for getting + * the current time from the RTC on Power Macintoshes. + * + * We use the decrementer register for our periodic interrupts. + * + * Paul Mackerras August 1996. + * Copyright (C) 1996 Paul Mackerras. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Apparently the RTC stores seconds since 1 Jan 1904 */ +#define RTC_OFFSET 2082844800 + +/* + * Calibrate the decrementer frequency with the VIA timer 1. + */ +#define VIA_TIMER_FREQ_6 4700000 /* time 1 frequency * 6 */ + +/* VIA registers */ +#define RS 0x200 /* skip between registers */ +#define T1CL (4*RS) /* Timer 1 ctr/latch (low 8 bits) */ +#define T1CH (5*RS) /* Timer 1 counter (high 8 bits) */ +#define T1LL (6*RS) /* Timer 1 latch (low 8 bits) */ +#define T1LH (7*RS) /* Timer 1 latch (high 8 bits) */ +#define ACR (11*RS) /* Auxiliary control register */ +#define IFR (13*RS) /* Interrupt flag register */ + +/* Bits in ACR */ +#define T1MODE 0xc0 /* Timer 1 mode */ +#define T1MODE_CONT 0x40 /* continuous interrupts */ + +/* Bits in IFR and IER */ +#define T1_INT 0x40 /* Timer 1 interrupt */ + +extern struct timezone sys_tz; + +long __init +pmac_time_init(void) +{ +#ifdef CONFIG_NVRAM + s32 delta = 0; + int dst; + + delta = ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x9)) << 16; + delta |= ((s32)pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xa)) << 8; + delta |= pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0xb); + if (delta & 0x00800000UL) + delta |= 0xFF000000UL; + dst = ((pmac_xpram_read(PMAC_XPRAM_MACHINE_LOC + 0x8) & 0x80) != 0); + printk("GMT Delta read from XPRAM: %d minutes, DST: %s\n", delta/60, + dst ? "on" : "off"); + return delta; +#else + return 0; +#endif +} + +unsigned long +pmac_get_rtc_time(void) +{ +#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU) + struct adb_request req; + unsigned long now; +#endif + + /* Get the time from the RTC */ + switch (sys_ctrler) { +#ifdef CONFIG_ADB_CUDA + case SYS_CTRLER_CUDA: + if (cuda_request(&req, NULL, 2, CUDA_PACKET, CUDA_GET_TIME) < 0) + return 0; + while (!req.complete) + cuda_poll(); + if (req.reply_len != 7) + printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n", + req.reply_len); + now = (req.reply[3] << 24) + (req.reply[4] << 16) + + (req.reply[5] << 8) + req.reply[6]; + return now - RTC_OFFSET; +#endif /* CONFIG_ADB_CUDA */ +#ifdef CONFIG_ADB_PMU + case SYS_CTRLER_PMU: + if (pmu_request(&req, NULL, 1, PMU_READ_RTC) < 0) + return 0; + while (!req.complete) + pmu_poll(); + if (req.reply_len != 4) + printk(KERN_ERR "pmac_get_rtc_time: got %d byte reply\n", + req.reply_len); + now = (req.reply[0] << 24) + (req.reply[1] << 16) + + (req.reply[2] << 8) + req.reply[3]; + return now - RTC_OFFSET; +#endif /* CONFIG_ADB_PMU */ + default: ; + } + return 0; +} + +int +pmac_set_rtc_time(unsigned long nowtime) +{ +#if defined(CONFIG_ADB_CUDA) || defined(CONFIG_ADB_PMU) + struct adb_request req; +#endif + + nowtime += RTC_OFFSET; + + switch (sys_ctrler) { +#ifdef CONFIG_ADB_CUDA + case SYS_CTRLER_CUDA: + if (cuda_request(&req, NULL, 6, CUDA_PACKET, CUDA_SET_TIME, + nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0) + return 0; + while (!req.complete) + cuda_poll(); + if ((req.reply_len != 3) && (req.reply_len != 7)) + printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n", + req.reply_len); + return 1; +#endif /* CONFIG_ADB_CUDA */ +#ifdef CONFIG_ADB_PMU + case SYS_CTRLER_PMU: + if (pmu_request(&req, NULL, 5, PMU_SET_RTC, + nowtime >> 24, nowtime >> 16, nowtime >> 8, nowtime) < 0) + return 0; + while (!req.complete) + pmu_poll(); + if (req.reply_len != 0) + printk(KERN_ERR "pmac_set_rtc_time: got %d byte reply\n", + req.reply_len); + return 1; +#endif /* CONFIG_ADB_PMU */ + default: + return 0; + } +} + +/* + * Calibrate the decrementer register using VIA timer 1. + * This is used both on powermacs and CHRP machines. + */ +int __init +via_calibrate_decr(void) +{ + struct device_node *vias; + volatile unsigned char __iomem *via; + int count = VIA_TIMER_FREQ_6 / 100; + unsigned int dstart, dend; + + vias = find_devices("via-cuda"); + if (vias == 0) + vias = find_devices("via-pmu"); + if (vias == 0) + vias = find_devices("via"); + if (vias == 0 || vias->n_addrs == 0) + return 0; + via = ioremap(vias->addrs[0].address, vias->addrs[0].size); + + /* set timer 1 for continuous interrupts */ + out_8(&via[ACR], (via[ACR] & ~T1MODE) | T1MODE_CONT); + /* set the counter to a small value */ + out_8(&via[T1CH], 2); + /* set the latch to `count' */ + out_8(&via[T1LL], count); + out_8(&via[T1LH], count >> 8); + /* wait until it hits 0 */ + while ((in_8(&via[IFR]) & T1_INT) == 0) + ; + dstart = get_dec(); + /* clear the interrupt & wait until it hits 0 again */ + in_8(&via[T1CL]); + while ((in_8(&via[IFR]) & T1_INT) == 0) + ; + dend = get_dec(); + + tb_ticks_per_jiffy = (dstart - dend) / (6 * (HZ/100)); + tb_to_us = mulhwu_scale_factor(dstart - dend, 60000); + + printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n", + tb_ticks_per_jiffy, dstart - dend); + + iounmap(via); + + return 1; +} + +#ifdef CONFIG_PM +/* + * Reset the time after a sleep. + */ +static int +time_sleep_notify(struct pmu_sleep_notifier *self, int when) +{ + static unsigned long time_diff; + unsigned long flags; + unsigned long seq; + + switch (when) { + case PBOOK_SLEEP_NOW: + do { + seq = read_seqbegin_irqsave(&xtime_lock, flags); + time_diff = xtime.tv_sec - pmac_get_rtc_time(); + } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); + break; + case PBOOK_WAKE: + write_seqlock_irqsave(&xtime_lock, flags); + xtime.tv_sec = pmac_get_rtc_time() + time_diff; + xtime.tv_nsec = 0; + last_rtc_update = xtime.tv_sec; + write_sequnlock_irqrestore(&xtime_lock, flags); + break; + } + return PBOOK_SLEEP_OK; +} + +static struct pmu_sleep_notifier time_sleep_notifier = { + time_sleep_notify, SLEEP_LEVEL_MISC, +}; +#endif /* CONFIG_PM */ + +/* + * Query the OF and get the decr frequency. + * This was taken from the pmac time_init() when merging the prep/pmac + * time functions. + */ +void __init +pmac_calibrate_decr(void) +{ + struct device_node *cpu; + unsigned int freq, *fp; + +#ifdef CONFIG_PM + pmu_register_sleep_notifier(&time_sleep_notifier); +#endif /* CONFIG_PM */ + + /* We assume MacRISC2 machines have correct device-tree + * calibration. That's better since the VIA itself seems + * to be slightly off. --BenH + */ + if (!machine_is_compatible("MacRISC2") && + !machine_is_compatible("MacRISC3") && + !machine_is_compatible("MacRISC4")) + if (via_calibrate_decr()) + return; + + /* Special case: QuickSilver G4s seem to have a badly calibrated + * timebase-frequency in OF, VIA is much better on these. We should + * probably implement calibration based on the KL timer on these + * machines anyway... -BenH + */ + if (machine_is_compatible("PowerMac3,5")) + if (via_calibrate_decr()) + return; + /* + * The cpu node should have a timebase-frequency property + * to tell us the rate at which the decrementer counts. + */ + cpu = find_type_devices("cpu"); + if (cpu == 0) + panic("can't find cpu node in time_init"); + fp = (unsigned int *) get_property(cpu, "timebase-frequency", NULL); + if (fp == 0) + panic("can't get cpu timebase frequency"); + freq = *fp; + printk("time_init: decrementer frequency = %u.%.6u MHz\n", + freq/1000000, freq%1000000); + tb_ticks_per_jiffy = freq / HZ; + tb_to_us = mulhwu_scale_factor(freq, 1000000); +} diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig new file mode 100644 index 00000000000..673ac47a162 --- /dev/null +++ b/arch/powerpc/platforms/prep/Kconfig @@ -0,0 +1,22 @@ + +config PREP_RESIDUAL + bool "Support for PReP Residual Data" + depends on PPC_PREP + help + Some PReP systems have residual data passed to the kernel by the + firmware. This allows detection of memory size, devices present and + other useful pieces of information. Sometimes this information is + not present or incorrect, in which case it could lead to the machine + behaving incorrectly. If this happens, either disable PREP_RESIDUAL + or pass the 'noresidual' option to the kernel. + + If you are running a PReP system, say Y here, otherwise say N. + +config PROC_PREPRESIDUAL + bool "Support for reading of PReP Residual Data in /proc" + depends on PREP_RESIDUAL && PROC_FS + help + Enabling this option will create a /proc/residual file which allows + you to get at the residual data on PReP systems. You will need a tool + (lsresidual) to parse it. If you aren't on a PReP system, you don't + want this. diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig new file mode 100644 index 00000000000..7a3b6fc4d97 --- /dev/null +++ b/arch/powerpc/platforms/pseries/Kconfig @@ -0,0 +1,47 @@ + +config PPC_SPLPAR + depends on PPC_PSERIES + bool "Support for shared-processor logical partitions" + default n + help + Enabling this option will make the kernel run more efficiently + on logically-partitioned pSeries systems which use shared + processors, that is, which share physical processors between + two or more partitions. + +config HMT + bool "Hardware multithreading" + depends on SMP && PPC_PSERIES && BROKEN + help + This option enables hardware multithreading on RS64 cpus. + pSeries systems p620 and p660 have such a cpu type. + +config EEH + bool "PCI Extended Error Handling (EEH)" if EMBEDDED + depends on PPC_PSERIES + default y if !EMBEDDED + +config PPC_RTAS + bool + depends on PPC_PSERIES || PPC_BPA + default y + +config RTAS_PROC + bool "Proc interface to RTAS" + depends on PPC_RTAS + default y + +config RTAS_FLASH + tristate "Firmware flash interface" + depends on PPC64 && RTAS_PROC + +config SCANLOG + tristate "Scanlog dump interface" + depends on RTAS_PROC && PPC_PSERIES + +config LPARCFG + tristate "LPAR Configuration Data" + depends on PPC_PSERIES || PPC_ISERIES + help + Provide system capacity information via human readable + = pairs through a /proc/ppc64/lparcfg interface. diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile new file mode 100644 index 00000000000..26bdcd9a2a4 --- /dev/null +++ b/arch/powerpc/sysdev/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MPIC) += mpic.o diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c new file mode 100644 index 00000000000..c660e7d7c64 --- /dev/null +++ b/arch/powerpc/sysdev/mpic.c @@ -0,0 +1,904 @@ +/* + * arch/powerpc/kernel/mpic.c + * + * Driver for interrupt controllers following the OpenPIC standard, the + * common implementation beeing IBM's MPIC. This driver also can deal + * with various broken implementations of this HW. + * + * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define DBG(fmt...) printk(fmt) +#else +#define DBG(fmt...) +#endif + +static struct mpic *mpics; +static struct mpic *mpic_primary; +static DEFINE_SPINLOCK(mpic_lock); + + +/* + * Register accessor functions + */ + + +static inline u32 _mpic_read(unsigned int be, volatile u32 __iomem *base, + unsigned int reg) +{ + if (be) + return in_be32(base + (reg >> 2)); + else + return in_le32(base + (reg >> 2)); +} + +static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base, + unsigned int reg, u32 value) +{ + if (be) + out_be32(base + (reg >> 2), value); + else + out_le32(base + (reg >> 2), value); +} + +static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) +{ + unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; + unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); + + if (mpic->flags & MPIC_BROKEN_IPI) + be = !be; + return _mpic_read(be, mpic->gregs, offset); +} + +static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) +{ + unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); + + _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); +} + +static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) +{ + unsigned int cpu = 0; + + if (mpic->flags & MPIC_PRIMARY) + cpu = hard_smp_processor_id(); + + return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg); +} + +static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) +{ + unsigned int cpu = 0; + + if (mpic->flags & MPIC_PRIMARY) + cpu = hard_smp_processor_id(); + + _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->cpuregs[cpu], reg, value); +} + +static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) +{ + unsigned int isu = src_no >> mpic->isu_shift; + unsigned int idx = src_no & mpic->isu_mask; + + return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], + reg + (idx * MPIC_IRQ_STRIDE)); +} + +static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, + unsigned int reg, u32 value) +{ + unsigned int isu = src_no >> mpic->isu_shift; + unsigned int idx = src_no & mpic->isu_mask; + + _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], + reg + (idx * MPIC_IRQ_STRIDE), value); +} + +#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) +#define mpic_write(b,r,v) _mpic_write(mpic->flags & MPIC_BIG_ENDIAN,(b),(r),(v)) +#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) +#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) +#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) +#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) +#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) +#define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v)) + + +/* + * Low level utility functions + */ + + + +/* Check if we have one of those nice broken MPICs with a flipped endian on + * reads from IPI registers + */ +static void __init mpic_test_broken_ipi(struct mpic *mpic) +{ + u32 r; + + mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); + r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); + + if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { + printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); + mpic->flags |= MPIC_BROKEN_IPI; + } +} + +#ifdef CONFIG_MPIC_BROKEN_U3 + +/* Test if an interrupt is sourced from HyperTransport (used on broken U3s) + * to force the edge setting on the MPIC and do the ack workaround. + */ +static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source_no) +{ + if (source_no >= 128 || !mpic->fixups) + return 0; + return mpic->fixups[source_no].base != NULL; +} + +static inline void mpic_apic_end_irq(struct mpic *mpic, unsigned int source_no) +{ + struct mpic_irq_fixup *fixup = &mpic->fixups[source_no]; + u32 tmp; + + spin_lock(&mpic->fixup_lock); + writeb(0x11 + 2 * fixup->irq, fixup->base); + tmp = readl(fixup->base + 2); + writel(tmp | 0x80000000ul, fixup->base + 2); + /* config writes shouldn't be posted but let's be safe ... */ + (void)readl(fixup->base + 2); + spin_unlock(&mpic->fixup_lock); +} + + +static void __init mpic_amd8111_read_irq(struct mpic *mpic, u8 __iomem *devbase) +{ + int i, irq; + u32 tmp; + + printk(KERN_INFO "mpic: - Workarounds on AMD 8111 @ %p\n", devbase); + + for (i=0; i < 24; i++) { + writeb(0x10 + 2*i, devbase + 0xf2); + tmp = readl(devbase + 0xf4); + if ((tmp & 0x1) || !(tmp & 0x20)) + continue; + irq = (tmp >> 16) & 0xff; + mpic->fixups[irq].irq = i; + mpic->fixups[irq].base = devbase + 0xf2; + } +} + +static void __init mpic_amd8131_read_irq(struct mpic *mpic, u8 __iomem *devbase) +{ + int i, irq; + u32 tmp; + + printk(KERN_INFO "mpic: - Workarounds on AMD 8131 @ %p\n", devbase); + + for (i=0; i < 4; i++) { + writeb(0x10 + 2*i, devbase + 0xba); + tmp = readl(devbase + 0xbc); + if ((tmp & 0x1) || !(tmp & 0x20)) + continue; + irq = (tmp >> 16) & 0xff; + mpic->fixups[irq].irq = i; + mpic->fixups[irq].base = devbase + 0xba; + } +} + +static void __init mpic_scan_ioapics(struct mpic *mpic) +{ + unsigned int devfn; + u8 __iomem *cfgspace; + + printk(KERN_INFO "mpic: Setting up IO-APICs workarounds for U3\n"); + + /* Allocate fixups array */ + mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup)); + BUG_ON(mpic->fixups == NULL); + memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup)); + + /* Init spinlock */ + spin_lock_init(&mpic->fixup_lock); + + /* Map u3 config space. We assume all IO-APICs are on the primary bus + * and slot will never be above "0xf" so we only need to map 32k + */ + cfgspace = (unsigned char __iomem *)ioremap(0xf2000000, 0x8000); + BUG_ON(cfgspace == NULL); + + /* Now we scan all slots. We do a very quick scan, we read the header type, + * vendor ID and device ID only, that's plenty enough + */ + for (devfn = 0; devfn < PCI_DEVFN(0x10,0); devfn ++) { + u8 __iomem *devbase = cfgspace + (devfn << 8); + u8 hdr_type = readb(devbase + PCI_HEADER_TYPE); + u32 l = readl(devbase + PCI_VENDOR_ID); + u16 vendor_id, device_id; + int multifunc = 0; + + DBG("devfn %x, l: %x\n", devfn, l); + + /* If no device, skip */ + if (l == 0xffffffff || l == 0x00000000 || + l == 0x0000ffff || l == 0xffff0000) + goto next; + + /* Check if it's a multifunction device (only really used + * to function 0 though + */ + multifunc = !!(hdr_type & 0x80); + vendor_id = l & 0xffff; + device_id = (l >> 16) & 0xffff; + + /* If a known device, go to fixup setup code */ + if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7460) + mpic_amd8111_read_irq(mpic, devbase); + if (vendor_id == PCI_VENDOR_ID_AMD && device_id == 0x7450) + mpic_amd8131_read_irq(mpic, devbase); + next: + /* next device, if function 0 */ + if ((PCI_FUNC(devfn) == 0) && !multifunc) + devfn += 7; + } +} + +#endif /* CONFIG_MPIC_BROKEN_U3 */ + + +/* Find an mpic associated with a given linux interrupt */ +static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi) +{ + struct mpic *mpic = mpics; + + while(mpic) { + /* search IPIs first since they may override the main interrupts */ + if (irq >= mpic->ipi_offset && irq < (mpic->ipi_offset + 4)) { + if (is_ipi) + *is_ipi = 1; + return mpic; + } + if (irq >= mpic->irq_offset && + irq < (mpic->irq_offset + mpic->irq_count)) { + if (is_ipi) + *is_ipi = 0; + return mpic; + } + mpic = mpic -> next; + } + return NULL; +} + +/* Convert a cpu mask from logical to physical cpu numbers. */ +static inline u32 mpic_physmask(u32 cpumask) +{ + int i; + u32 mask = 0; + + for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1) + mask |= (cpumask & 1) << get_hard_smp_processor_id(i); + return mask; +} + +#ifdef CONFIG_SMP +/* Get the mpic structure from the IPI number */ +static inline struct mpic * mpic_from_ipi(unsigned int ipi) +{ + return container_of(irq_desc[ipi].handler, struct mpic, hc_ipi); +} +#endif + +/* Get the mpic structure from the irq number */ +static inline struct mpic * mpic_from_irq(unsigned int irq) +{ + return container_of(irq_desc[irq].handler, struct mpic, hc_irq); +} + +/* Send an EOI */ +static inline void mpic_eoi(struct mpic *mpic) +{ + mpic_cpu_write(MPIC_CPU_EOI, 0); + (void)mpic_cpu_read(MPIC_CPU_WHOAMI); +} + +#ifdef CONFIG_SMP +static irqreturn_t mpic_ipi_action(int irq, void *dev_id, struct pt_regs *regs) +{ + struct mpic *mpic = dev_id; + + smp_message_recv(irq - mpic->ipi_offset, regs); + return IRQ_HANDLED; +} +#endif /* CONFIG_SMP */ + +/* + * Linux descriptor level callbacks + */ + + +static void mpic_enable_irq(unsigned int irq) +{ + unsigned int loops = 100000; + struct mpic *mpic = mpic_from_irq(irq); + unsigned int src = irq - mpic->irq_offset; + + DBG("%s: enable_irq: %d (src %d)\n", mpic->name, irq, src); + + mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, + mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & ~MPIC_VECPRI_MASK); + + /* make sure mask gets to controller before we return to user */ + do { + if (!loops--) { + printk(KERN_ERR "mpic_enable_irq timeout\n"); + break; + } + } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); +} + +static void mpic_disable_irq(unsigned int irq) +{ + unsigned int loops = 100000; + struct mpic *mpic = mpic_from_irq(irq); + unsigned int src = irq - mpic->irq_offset; + + DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); + + mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, + mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | MPIC_VECPRI_MASK); + + /* make sure mask gets to controller before we return to user */ + do { + if (!loops--) { + printk(KERN_ERR "mpic_enable_irq timeout\n"); + break; + } + } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); +} + +static void mpic_end_irq(unsigned int irq) +{ + struct mpic *mpic = mpic_from_irq(irq); + + DBG("%s: end_irq: %d\n", mpic->name, irq); + + /* We always EOI on end_irq() even for edge interrupts since that + * should only lower the priority, the MPIC should have properly + * latched another edge interrupt coming in anyway + */ + +#ifdef CONFIG_MPIC_BROKEN_U3 + if (mpic->flags & MPIC_BROKEN_U3) { + unsigned int src = irq - mpic->irq_offset; + if (mpic_is_ht_interrupt(mpic, src)) + mpic_apic_end_irq(mpic, src); + } +#endif /* CONFIG_MPIC_BROKEN_U3 */ + + mpic_eoi(mpic); +} + +#ifdef CONFIG_SMP + +static void mpic_enable_ipi(unsigned int irq) +{ + struct mpic *mpic = mpic_from_ipi(irq); + unsigned int src = irq - mpic->ipi_offset; + + DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); + mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); +} + +static void mpic_disable_ipi(unsigned int irq) +{ + /* NEVER disable an IPI... that's just plain wrong! */ +} + +static void mpic_end_ipi(unsigned int irq) +{ + struct mpic *mpic = mpic_from_ipi(irq); + + /* + * IPIs are marked IRQ_PER_CPU. This has the side effect of + * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from + * applying to them. We EOI them late to avoid re-entering. + * We mark IPI's with SA_INTERRUPT as they must run with + * irqs disabled. + */ + mpic_eoi(mpic); +} + +#endif /* CONFIG_SMP */ + +static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask) +{ + struct mpic *mpic = mpic_from_irq(irq); + + cpumask_t tmp; + + cpus_and(tmp, cpumask, cpu_online_map); + + mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_DESTINATION, + mpic_physmask(cpus_addr(tmp)[0])); +} + + +/* + * Exported functions + */ + + +struct mpic * __init mpic_alloc(unsigned long phys_addr, + unsigned int flags, + unsigned int isu_size, + unsigned int irq_offset, + unsigned int irq_count, + unsigned int ipi_offset, + unsigned char *senses, + unsigned int senses_count, + const char *name) +{ + struct mpic *mpic; + u32 reg; + const char *vers; + int i; + + mpic = alloc_bootmem(sizeof(struct mpic)); + if (mpic == NULL) + return NULL; + + + memset(mpic, 0, sizeof(struct mpic)); + mpic->name = name; + + mpic->hc_irq.typename = name; + mpic->hc_irq.enable = mpic_enable_irq; + mpic->hc_irq.disable = mpic_disable_irq; + mpic->hc_irq.end = mpic_end_irq; + if (flags & MPIC_PRIMARY) + mpic->hc_irq.set_affinity = mpic_set_affinity; +#ifdef CONFIG_SMP + mpic->hc_ipi.typename = name; + mpic->hc_ipi.enable = mpic_enable_ipi; + mpic->hc_ipi.disable = mpic_disable_ipi; + mpic->hc_ipi.end = mpic_end_ipi; +#endif /* CONFIG_SMP */ + + mpic->flags = flags; + mpic->isu_size = isu_size; + mpic->irq_offset = irq_offset; + mpic->irq_count = irq_count; + mpic->ipi_offset = ipi_offset; + mpic->num_sources = 0; /* so far */ + mpic->senses = senses; + mpic->senses_count = senses_count; + + /* Map the global registers */ + mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); + mpic->tmregs = mpic->gregs + (MPIC_TIMER_BASE >> 2); + BUG_ON(mpic->gregs == NULL); + + /* Reset */ + if (flags & MPIC_WANTS_RESET) { + mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, + mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) + | MPIC_GREG_GCONF_RESET); + while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) + & MPIC_GREG_GCONF_RESET) + mb(); + } + + /* Read feature register, calculate num CPUs and, for non-ISU + * MPICs, num sources as well. On ISU MPICs, sources are counted + * as ISUs are added + */ + reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); + mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) + >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; + if (isu_size == 0) + mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK) + >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1; + + /* Map the per-CPU registers */ + for (i = 0; i < mpic->num_cpus; i++) { + mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + + i * MPIC_CPU_STRIDE, 0x1000); + BUG_ON(mpic->cpuregs[i] == NULL); + } + + /* Initialize main ISU if none provided */ + if (mpic->isu_size == 0) { + mpic->isu_size = mpic->num_sources; + mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, + MPIC_IRQ_STRIDE * mpic->isu_size); + BUG_ON(mpic->isus[0] == NULL); + } + mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); + mpic->isu_mask = (1 << mpic->isu_shift) - 1; + + /* Display version */ + switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) { + case 1: + vers = "1.0"; + break; + case 2: + vers = "1.2"; + break; + case 3: + vers = "1.3"; + break; + default: + vers = ""; + break; + } + printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %lx, max %d CPUs\n", + name, vers, phys_addr, mpic->num_cpus); + printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", mpic->isu_size, + mpic->isu_shift, mpic->isu_mask); + + mpic->next = mpics; + mpics = mpic; + + if (flags & MPIC_PRIMARY) + mpic_primary = mpic; + + return mpic; +} + +void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, + unsigned long phys_addr) +{ + unsigned int isu_first = isu_num * mpic->isu_size; + + BUG_ON(isu_num >= MPIC_MAX_ISU); + + mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); + if ((isu_first + mpic->isu_size) > mpic->num_sources) + mpic->num_sources = isu_first + mpic->isu_size; +} + +void __init mpic_setup_cascade(unsigned int irq, mpic_cascade_t handler, + void *data) +{ + struct mpic *mpic = mpic_find(irq, NULL); + unsigned long flags; + + /* Synchronization here is a bit dodgy, so don't try to replace cascade + * interrupts on the fly too often ... but normally it's set up at boot. + */ + spin_lock_irqsave(&mpic_lock, flags); + if (mpic->cascade) + mpic_disable_irq(mpic->cascade_vec + mpic->irq_offset); + mpic->cascade = NULL; + wmb(); + mpic->cascade_vec = irq - mpic->irq_offset; + mpic->cascade_data = data; + wmb(); + mpic->cascade = handler; + mpic_enable_irq(irq); + spin_unlock_irqrestore(&mpic_lock, flags); +} + +void __init mpic_init(struct mpic *mpic) +{ + int i; + + BUG_ON(mpic->num_sources == 0); + + printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); + + /* Set current processor priority to max */ + mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); + + /* Initialize timers: just disable them all */ + for (i = 0; i < 4; i++) { + mpic_write(mpic->tmregs, + i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); + mpic_write(mpic->tmregs, + i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, + MPIC_VECPRI_MASK | + (MPIC_VEC_TIMER_0 + i)); + } + + /* Initialize IPIs to our reserved vectors and mark them disabled for now */ + mpic_test_broken_ipi(mpic); + for (i = 0; i < 4; i++) { + mpic_ipi_write(i, + MPIC_VECPRI_MASK | + (10 << MPIC_VECPRI_PRIORITY_SHIFT) | + (MPIC_VEC_IPI_0 + i)); +#ifdef CONFIG_SMP + if (!(mpic->flags & MPIC_PRIMARY)) + continue; + irq_desc[mpic->ipi_offset+i].status |= IRQ_PER_CPU; + irq_desc[mpic->ipi_offset+i].handler = &mpic->hc_ipi; + +#endif /* CONFIG_SMP */ + } + + /* Initialize interrupt sources */ + if (mpic->irq_count == 0) + mpic->irq_count = mpic->num_sources; + +#ifdef CONFIG_MPIC_BROKEN_U3 + /* Do the ioapic fixups on U3 broken mpic */ + DBG("MPIC flags: %x\n", mpic->flags); + if ((mpic->flags & MPIC_BROKEN_U3) && (mpic->flags & MPIC_PRIMARY)) + mpic_scan_ioapics(mpic); +#endif /* CONFIG_MPIC_BROKEN_U3 */ + + for (i = 0; i < mpic->num_sources; i++) { + /* start with vector = source number, and masked */ + u32 vecpri = MPIC_VECPRI_MASK | i | (8 << MPIC_VECPRI_PRIORITY_SHIFT); + int level = 0; + + /* if it's an IPI, we skip it */ + if ((mpic->irq_offset + i) >= (mpic->ipi_offset + i) && + (mpic->irq_offset + i) < (mpic->ipi_offset + i + 4)) + continue; + + /* do senses munging */ + if (mpic->senses && i < mpic->senses_count) { + if (mpic->senses[i] & IRQ_SENSE_LEVEL) + vecpri |= MPIC_VECPRI_SENSE_LEVEL; + if (mpic->senses[i] & IRQ_POLARITY_POSITIVE) + vecpri |= MPIC_VECPRI_POLARITY_POSITIVE; + } else + vecpri |= MPIC_VECPRI_SENSE_LEVEL; + + /* remember if it was a level interrupts */ + level = (vecpri & MPIC_VECPRI_SENSE_LEVEL); + + /* deal with broken U3 */ + if (mpic->flags & MPIC_BROKEN_U3) { +#ifdef CONFIG_MPIC_BROKEN_U3 + if (mpic_is_ht_interrupt(mpic, i)) { + vecpri &= ~(MPIC_VECPRI_SENSE_MASK | + MPIC_VECPRI_POLARITY_MASK); + vecpri |= MPIC_VECPRI_POLARITY_POSITIVE; + } +#else + printk(KERN_ERR "mpic: BROKEN_U3 set, but CONFIG doesn't match\n"); +#endif + } + + DBG("setup source %d, vecpri: %08x, level: %d\n", i, vecpri, + (level != 0)); + + /* init hw */ + mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); + mpic_irq_write(i, MPIC_IRQ_DESTINATION, + 1 << hard_smp_processor_id()); + + /* init linux descriptors */ + if (i < mpic->irq_count) { + irq_desc[mpic->irq_offset+i].status = level ? IRQ_LEVEL : 0; + irq_desc[mpic->irq_offset+i].handler = &mpic->hc_irq; + } + } + + /* Init spurrious vector */ + mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); + + /* Disable 8259 passthrough */ + mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, + mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) + | MPIC_GREG_GCONF_8259_PTHROU_DIS); + + /* Set current processor priority to 0 */ + mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); +} + + + +void mpic_irq_set_priority(unsigned int irq, unsigned int pri) +{ + int is_ipi; + struct mpic *mpic = mpic_find(irq, &is_ipi); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mpic_lock, flags); + if (is_ipi) { + reg = mpic_ipi_read(irq - mpic->ipi_offset) & MPIC_VECPRI_PRIORITY_MASK; + mpic_ipi_write(irq - mpic->ipi_offset, + reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); + } else { + reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI) + & MPIC_VECPRI_PRIORITY_MASK; + mpic_irq_write(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI, + reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); + } + spin_unlock_irqrestore(&mpic_lock, flags); +} + +unsigned int mpic_irq_get_priority(unsigned int irq) +{ + int is_ipi; + struct mpic *mpic = mpic_find(irq, &is_ipi); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mpic_lock, flags); + if (is_ipi) + reg = mpic_ipi_read(irq - mpic->ipi_offset); + else + reg = mpic_irq_read(irq - mpic->irq_offset, MPIC_IRQ_VECTOR_PRI); + spin_unlock_irqrestore(&mpic_lock, flags); + return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; +} + +void mpic_setup_this_cpu(void) +{ +#ifdef CONFIG_SMP + struct mpic *mpic = mpic_primary; + unsigned long flags; + u32 msk = 1 << hard_smp_processor_id(); + unsigned int i; + + BUG_ON(mpic == NULL); + + DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); + + spin_lock_irqsave(&mpic_lock, flags); + + /* let the mpic know we want intrs. default affinity is 0xffffffff + * until changed via /proc. That's how it's done on x86. If we want + * it differently, then we should make sure we also change the default + * values of irq_affinity in irq.c. + */ + if (distribute_irqs) { + for (i = 0; i < mpic->num_sources ; i++) + mpic_irq_write(i, MPIC_IRQ_DESTINATION, + mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); + } + + /* Set current processor priority to 0 */ + mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); + + spin_unlock_irqrestore(&mpic_lock, flags); +#endif /* CONFIG_SMP */ +} + +int mpic_cpu_get_priority(void) +{ + struct mpic *mpic = mpic_primary; + + return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); +} + +void mpic_cpu_set_priority(int prio) +{ + struct mpic *mpic = mpic_primary; + + prio &= MPIC_CPU_TASKPRI_MASK; + mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); +} + +/* + * XXX: someone who knows mpic should check this. + * do we need to eoi the ipi including for kexec cpu here (see xics comments)? + * or can we reset the mpic in the new kernel? + */ +void mpic_teardown_this_cpu(int secondary) +{ + struct mpic *mpic = mpic_primary; + unsigned long flags; + u32 msk = 1 << hard_smp_processor_id(); + unsigned int i; + + BUG_ON(mpic == NULL); + + DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); + spin_lock_irqsave(&mpic_lock, flags); + + /* let the mpic know we don't want intrs. */ + for (i = 0; i < mpic->num_sources ; i++) + mpic_irq_write(i, MPIC_IRQ_DESTINATION, + mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); + + /* Set current processor priority to max */ + mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); + + spin_unlock_irqrestore(&mpic_lock, flags); +} + + +void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) +{ + struct mpic *mpic = mpic_primary; + + BUG_ON(mpic == NULL); + + DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); + + mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, + mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); +} + +int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs) +{ + u32 irq; + + irq = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; + DBG("%s: get_one_irq(): %d\n", mpic->name, irq); + + if (mpic->cascade && irq == mpic->cascade_vec) { + DBG("%s: cascading ...\n", mpic->name); + irq = mpic->cascade(regs, mpic->cascade_data); + mpic_eoi(mpic); + return irq; + } + if (unlikely(irq == MPIC_VEC_SPURRIOUS)) + return -1; + if (irq < MPIC_VEC_IPI_0) + return irq + mpic->irq_offset; + DBG("%s: ipi %d !\n", mpic->name, irq - MPIC_VEC_IPI_0); + return irq - MPIC_VEC_IPI_0 + mpic->ipi_offset; +} + +int mpic_get_irq(struct pt_regs *regs) +{ + struct mpic *mpic = mpic_primary; + + BUG_ON(mpic == NULL); + + return mpic_get_one_irq(mpic, regs); +} + + +#ifdef CONFIG_SMP +void mpic_request_ipis(void) +{ + struct mpic *mpic = mpic_primary; + + BUG_ON(mpic == NULL); + + printk("requesting IPIs ... \n"); + + /* IPIs are marked SA_INTERRUPT as they must run with irqs disabled */ + request_irq(mpic->ipi_offset+0, mpic_ipi_action, SA_INTERRUPT, + "IPI0 (call function)", mpic); + request_irq(mpic->ipi_offset+1, mpic_ipi_action, SA_INTERRUPT, + "IPI1 (reschedule)", mpic); + request_irq(mpic->ipi_offset+2, mpic_ipi_action, SA_INTERRUPT, + "IPI2 (unused)", mpic); + request_irq(mpic->ipi_offset+3, mpic_ipi_action, SA_INTERRUPT, + "IPI3 (debugger break)", mpic); + + printk("IPIs requested... \n"); +} +#endif /* CONFIG_SMP */ diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index ce166e3de53..0649540bc7d 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile @@ -1,6 +1,7 @@ # # Makefile for the linux kernel. # +ifneq ($(CONFIG_PPC_MERGE),y) extra-$(CONFIG_PPC_STD_MMU) := head.o extra-$(CONFIG_40x) := head_4xx.o @@ -37,3 +38,23 @@ endif # These are here while we do the architecture merge vecemu-y += ../../powerpc/kernel/vecemu.o + +else +obj-y := entry.o irq.o idle.o time.o misc.o \ + signal.o ptrace.o align.o \ + syscalls.o setup.o \ + cputable.o perfmon.o +obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o +obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o +obj-$(CONFIG_POWER4) += cpu_setup_power4.o +obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o +obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o +obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_KGDB) += ppc-stub.o +obj-$(CONFIG_SMP) += smp.o smp-tbsync.o +obj-$(CONFIG_TAU) += temp.o +ifndef CONFIG_E200 +obj-$(CONFIG_FSL_BOOKE) += perfmon_fsl_booke.o +endif +obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o +endif diff --git a/arch/ppc/kernel/setup.c b/arch/ppc/kernel/setup.c index 77fecfbabe8..1b891b806f3 100644 --- a/arch/ppc/kernel/setup.c +++ b/arch/ppc/kernel/setup.c @@ -83,6 +83,8 @@ extern void pmac_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7); extern void chrp_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7); + +dev_t boot_dev; #endif /* CONFIG_PPC_MULTIPLATFORM */ #ifdef CONFIG_MAGIC_SYSRQ @@ -405,11 +407,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, _machine = _MACH_prep; } +#ifdef CONFIG_PPC_PREP /* not much more to do here, if prep */ if (_machine == _MACH_prep) { prep_init(r3, r4, r5, r6, r7); return; } +#endif /* prom_init has already been called from __start */ if (boot_infos) @@ -480,12 +484,16 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, #endif /* CONFIG_ADB */ switch (_machine) { +#ifdef CONFIG_PPC_PMAC case _MACH_Pmac: pmac_init(r3, r4, r5, r6, r7); break; +#endif +#ifdef CONFIG_PPC_CHRP case _MACH_chrp: chrp_init(r3, r4, r5, r6, r7); break; +#endif } } diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c index fccafbcd4b5..8bc734fe668 100644 --- a/arch/ppc/platforms/prep_setup.c +++ b/arch/ppc/platforms/prep_setup.c @@ -89,9 +89,6 @@ extern void prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi #define cached_21 (((char *)(ppc_cached_irq_mask))[3]) #define cached_A1 (((char *)(ppc_cached_irq_mask))[2]) -/* for the mac fs */ -dev_t boot_dev; - #ifdef CONFIG_SOUND_CS4232 long ppc_cs4232_dma, ppc_cs4232_dma2; #endif diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index b8d08f33f7e..1b0a84931af 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -5,6 +5,7 @@ CFLAGS_prom_init.o += -fPIC CFLAGS_btext.o += -fPIC +ifneq ($(CONFIG_PPC_MERGE),y) wdt-mpc8xx-$(CONFIG_8xx_WDT) += m8xx_wdt.o obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o @@ -109,3 +110,16 @@ obj-$(CONFIG_PPC_MPC52xx) += mpc52xx_setup.o mpc52xx_pic.o \ ifeq ($(CONFIG_PPC_MPC52xx),y) obj-$(CONFIG_PCI) += mpc52xx_pci.o endif + +else +# Stuff still needed by the merged powerpc sources + +obj-$(CONFIG_PPCBUG_NVRAM) += prep_nvram.o +obj-$(CONFIG_PPC_OF) += prom_init.o prom.o of_device.o +obj-$(CONFIG_PPC_PMAC) += indirect_pci.o +obj-$(CONFIG_PPC_CHRP) += indirect_pci.o i8259.o +obj-$(CONFIG_PPC_PREP) += indirect_pci.o i8259.o todc_time.o +obj-$(CONFIG_BOOTX_TEXT) += btext.o +obj-$(CONFIG_MPC10X_BRIDGE) += mpc10x_common.o indirect_pci.o ppc_sys.o + +endif diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c index 76719451e38..50346188452 100644 --- a/drivers/macintosh/via-pmu.c +++ b/drivers/macintosh/via-pmu.c @@ -405,7 +405,7 @@ static int __init via_pmu_start(void) bright_req_2.complete = 1; batt_req.complete = 1; -#ifdef CONFIG_PPC32 +#if defined(CONFIG_PPC32) && !defined(CONFIG_PPC_MERGE) if (pmu_kind == PMU_KEYLARGO_BASED) openpic_set_irq_priority(vias->intrs[0].line, OPENPIC_PRIORITY_DEFAULT + 1); diff --git a/fs/proc/proc_misc.c b/fs/proc/proc_misc.c index a3453555a94..5b6b0b6038a 100644 --- a/fs/proc/proc_misc.c +++ b/fs/proc/proc_misc.c @@ -629,12 +629,4 @@ void __init proc_misc_init(void) if (entry) entry->proc_fops = &proc_sysrq_trigger_operations; #endif -#ifdef CONFIG_PPC32 - { - extern struct file_operations ppc_htab_operations; - entry = create_proc_entry("ppc_htab", S_IRUGO|S_IWUSR, NULL); - if (entry) - entry->proc_fops = &ppc_htab_operations; - } -#endif } diff --git a/include/asm-powerpc/kdebug.h b/include/asm-powerpc/kdebug.h new file mode 100644 index 00000000000..7c55abf597f --- /dev/null +++ b/include/asm-powerpc/kdebug.h @@ -0,0 +1,42 @@ +#ifndef _POWERPC_KDEBUG_H +#define _POWERPC_KDEBUG_H 1 + +/* nearly identical to x86_64/i386 code */ + +#include + +struct pt_regs; + +struct die_args { + struct pt_regs *regs; + const char *str; + long err; + int trapnr; + int signr; +}; + +/* + Note - you should never unregister because that can race with NMIs. + If you really want to do it first unregister - then synchronize_sched - + then free. + */ +int register_die_notifier(struct notifier_block *nb); +extern struct notifier_block *powerpc_die_chain; + +/* Grossly misnamed. */ +enum die_val { + DIE_OOPS = 1, + DIE_IABR_MATCH, + DIE_DABR_MATCH, + DIE_BPT, + DIE_SSTEP, + DIE_PAGE_FAULT, +}; + +static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig) +{ + struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig }; + return notifier_call_chain(&powerpc_die_chain, val, &args); +} + +#endif diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h new file mode 100644 index 00000000000..d9129d2b038 --- /dev/null +++ b/include/asm-powerpc/kprobes.h @@ -0,0 +1,67 @@ +#ifndef _ASM_KPROBES_H +#define _ASM_KPROBES_H +/* + * Kernel Probes (KProbes) + * include/asm-ppc64/kprobes.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) IBM Corporation, 2002, 2004 + * + * 2002-Oct Created by Vamsi Krishna S Kernel + * Probes initial implementation ( includes suggestions from + * Rusty Russell). + * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli + * + */ +#include +#include + +struct pt_regs; + +typedef unsigned int kprobe_opcode_t; +#define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */ +#define MAX_INSN_SIZE 1 + +#define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008) +#define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088) +#define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000) +#define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000) + +#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)((func_descr_t *)pentry) + +#define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \ + IS_TWI(instr) || IS_TDI(instr)) + +#define ARCH_SUPPORTS_KRETPROBES +void kretprobe_trampoline(void); + +/* Architecture specific copy of original instruction */ +struct arch_specific_insn { + /* copy of original instruction */ + kprobe_opcode_t *insn; +}; + +#ifdef CONFIG_KPROBES +extern int kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data); +#else /* !CONFIG_KPROBES */ +static inline int kprobe_exceptions_notify(struct notifier_block *self, + unsigned long val, void *data) +{ + return 0; +} +#endif +#endif /* _ASM_KPROBES_H */ diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h new file mode 100644 index 00000000000..f1e24f4b2d1 --- /dev/null +++ b/include/asm-powerpc/mpic.h @@ -0,0 +1,279 @@ +#include + +/* + * Global registers + */ + +#define MPIC_GREG_BASE 0x01000 + +#define MPIC_GREG_FEATURE_0 0x00000 +#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 +#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 +#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 +#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 +#define MPIC_GREG_FEATURE_VERSION_MASK 0xff +#define MPIC_GREG_FEATURE_1 0x00010 +#define MPIC_GREG_GLOBAL_CONF_0 0x00020 +#define MPIC_GREG_GCONF_RESET 0x80000000 +#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 +#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff +#define MPIC_GREG_GLOBAL_CONF_1 0x00030 +#define MPIC_GREG_VENDOR_0 0x00040 +#define MPIC_GREG_VENDOR_1 0x00050 +#define MPIC_GREG_VENDOR_2 0x00060 +#define MPIC_GREG_VENDOR_3 0x00070 +#define MPIC_GREG_VENDOR_ID 0x00080 +#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 +#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 +#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 +#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 +#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff +#define MPIC_GREG_PROCESSOR_INIT 0x00090 +#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 +#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 +#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 +#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 +#define MPIC_GREG_SPURIOUS 0x000e0 +#define MPIC_GREG_TIMER_FREQ 0x000f0 + +/* + * + * Timer registers + */ +#define MPIC_TIMER_BASE 0x01100 +#define MPIC_TIMER_STRIDE 0x40 + +#define MPIC_TIMER_CURRENT_CNT 0x00000 +#define MPIC_TIMER_BASE_CNT 0x00010 +#define MPIC_TIMER_VECTOR_PRI 0x00020 +#define MPIC_TIMER_DESTINATION 0x00030 + +/* + * Per-Processor registers + */ + +#define MPIC_CPU_THISBASE 0x00000 +#define MPIC_CPU_BASE 0x20000 +#define MPIC_CPU_STRIDE 0x01000 + +#define MPIC_CPU_IPI_DISPATCH_0 0x00040 +#define MPIC_CPU_IPI_DISPATCH_1 0x00050 +#define MPIC_CPU_IPI_DISPATCH_2 0x00060 +#define MPIC_CPU_IPI_DISPATCH_3 0x00070 +#define MPIC_CPU_CURRENT_TASK_PRI 0x00080 +#define MPIC_CPU_TASKPRI_MASK 0x0000000f +#define MPIC_CPU_WHOAMI 0x00090 +#define MPIC_CPU_WHOAMI_MASK 0x0000001f +#define MPIC_CPU_INTACK 0x000a0 +#define MPIC_CPU_EOI 0x000b0 + +/* + * Per-source registers + */ + +#define MPIC_IRQ_BASE 0x10000 +#define MPIC_IRQ_STRIDE 0x00020 +#define MPIC_IRQ_VECTOR_PRI 0x00000 +#define MPIC_VECPRI_MASK 0x80000000 +#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ +#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 +#define MPIC_VECPRI_PRIORITY_SHIFT 16 +#define MPIC_VECPRI_VECTOR_MASK 0x000007ff +#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 +#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 +#define MPIC_VECPRI_POLARITY_MASK 0x00800000 +#define MPIC_VECPRI_SENSE_LEVEL 0x00400000 +#define MPIC_VECPRI_SENSE_EDGE 0x00000000 +#define MPIC_VECPRI_SENSE_MASK 0x00400000 +#define MPIC_IRQ_DESTINATION 0x00010 + +#define MPIC_MAX_IRQ_SOURCES 2048 +#define MPIC_MAX_CPUS 32 +#define MPIC_MAX_ISU 32 + +/* + * Special vector numbers (internal use only) + */ +#define MPIC_VEC_SPURRIOUS 255 +#define MPIC_VEC_IPI_3 254 +#define MPIC_VEC_IPI_2 253 +#define MPIC_VEC_IPI_1 252 +#define MPIC_VEC_IPI_0 251 + +/* unused */ +#define MPIC_VEC_TIMER_3 250 +#define MPIC_VEC_TIMER_2 249 +#define MPIC_VEC_TIMER_1 248 +#define MPIC_VEC_TIMER_0 247 + +/* Type definition of the cascade handler */ +typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data); + +#ifdef CONFIG_MPIC_BROKEN_U3 +/* Fixup table entry */ +struct mpic_irq_fixup +{ + u8 __iomem *base; + unsigned int irq; +}; +#endif /* CONFIG_MPIC_BROKEN_U3 */ + + +/* The instance data of a given MPIC */ +struct mpic +{ + /* The "linux" controller struct */ + hw_irq_controller hc_irq; +#ifdef CONFIG_SMP + hw_irq_controller hc_ipi; +#endif + const char *name; + /* Flags */ + unsigned int flags; + /* How many irq sources in a given ISU */ + unsigned int isu_size; + unsigned int isu_shift; + unsigned int isu_mask; + /* Offset of irq vector numbers */ + unsigned int irq_offset; + unsigned int irq_count; + /* Offset of ipi vector numbers */ + unsigned int ipi_offset; + /* Number of sources */ + unsigned int num_sources; + /* Number of CPUs */ + unsigned int num_cpus; + /* cascade handler */ + mpic_cascade_t cascade; + void *cascade_data; + unsigned int cascade_vec; + /* senses array */ + unsigned char *senses; + unsigned int senses_count; + +#ifdef CONFIG_MPIC_BROKEN_U3 + /* The fixup table */ + struct mpic_irq_fixup *fixups; + spinlock_t fixup_lock; +#endif + + /* The various ioremap'ed bases */ + volatile u32 __iomem *gregs; + volatile u32 __iomem *tmregs; + volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; + volatile u32 __iomem *isus[MPIC_MAX_ISU]; + + /* link */ + struct mpic *next; +}; + +/* This is the primary controller, only that one has IPIs and + * has afinity control. A non-primary MPIC always uses CPU0 + * registers only + */ +#define MPIC_PRIMARY 0x00000001 +/* Set this for a big-endian MPIC */ +#define MPIC_BIG_ENDIAN 0x00000002 +/* Broken U3 MPIC */ +#define MPIC_BROKEN_U3 0x00000004 +/* Broken IPI registers (autodetected) */ +#define MPIC_BROKEN_IPI 0x00000008 +/* MPIC wants a reset */ +#define MPIC_WANTS_RESET 0x00000010 + +/* Allocate the controller structure and setup the linux irq descs + * for the range if interrupts passed in. No HW initialization is + * actually performed. + * + * @phys_addr: physial base address of the MPIC + * @flags: flags, see constants above + * @isu_size: number of interrupts in an ISU. Use 0 to use a + * standard ISU-less setup (aka powermac) + * @irq_offset: first irq number to assign to this mpic + * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 + * to match the number of sources + * @ipi_offset: first irq number to assign to this mpic IPI sources, + * used only on primary mpic + * @senses: array of sense values + * @senses_num: number of entries in the array + * + * Note about the sense array. If none is passed, all interrupts are + * setup to be level negative unless MPIC_BROKEN_U3 is set in which + * case they are edge positive (and the array is ignored anyway). + * The values in the array start at the first source of the MPIC, + * that is senses[0] correspond to linux irq "irq_offset". + */ +extern struct mpic *mpic_alloc(unsigned long phys_addr, + unsigned int flags, + unsigned int isu_size, + unsigned int irq_offset, + unsigned int irq_count, + unsigned int ipi_offset, + unsigned char *senses, + unsigned int senses_num, + const char *name); + +/* Assign ISUs, to call before mpic_init() + * + * @mpic: controller structure as returned by mpic_alloc() + * @isu_num: ISU number + * @phys_addr: physical address of the ISU + */ +extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, + unsigned long phys_addr); + +/* Initialize the controller. After this has been called, none of the above + * should be called again for this mpic + */ +extern void mpic_init(struct mpic *mpic); + +/* Setup a cascade. Currently, only one cascade is supported this + * way, though you can always do a normal request_irq() and add + * other cascades this way. You should call this _after_ having + * added all the ISUs + * + * @irq_no: "linux" irq number of the cascade (that is offset'ed vector) + * @handler: cascade handler function + */ +extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder, + void *data); + +/* + * All of the following functions must only be used after the + * ISUs have been assigned and the controller fully initialized + * with mpic_init() + */ + + +/* Change/Read the priority of an interrupt. Default is 8 for irqs and + * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the + * IPI number is then the offset'ed (linux irq number mapped to the IPI) + */ +extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); +extern unsigned int mpic_irq_get_priority(unsigned int irq); + +/* Setup a non-boot CPU */ +extern void mpic_setup_this_cpu(void); + +/* Clean up for kexec (or cpu offline or ...) */ +extern void mpic_teardown_this_cpu(int secondary); + +/* Get the current cpu priority for this cpu (0..15) */ +extern int mpic_cpu_get_priority(void); + +/* Set the current cpu priority for this cpu */ +extern void mpic_cpu_set_priority(int prio); + +/* Request IPIs on primary mpic */ +extern void mpic_request_ipis(void); + +/* Send an IPI (non offseted number 0..3) */ +extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); + +/* Fetch interrupt from a given mpic */ +extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs); +/* This one gets to the primary mpic */ +extern int mpic_get_irq(struct pt_regs *regs); + +/* global mpic for pSeries */ +extern struct mpic *pSeries_mpic; diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h new file mode 100644 index 00000000000..f97a5f1761b --- /dev/null +++ b/include/asm-powerpc/reg.h @@ -0,0 +1,446 @@ +/* + * Contains the definition of registers common to all PowerPC variants. + * If a register definition has been changed in a different PowerPC + * variant, we will case it in #ifndef XXX ... #endif, and have the + * number used in the Programming Environments Manual For 32-Bit + * Implementations of the PowerPC Architecture (a.k.a. Green Book) here. + */ + +#ifdef __KERNEL__ +#ifndef __ASM_PPC_REGS_H__ +#define __ASM_PPC_REGS_H__ + +#include + +/* Pickup Book E specific registers. */ +#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) +#include +#endif + +/* Machine State Register (MSR) Fields */ +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) +#define MSR_VEC (1<<25) /* Enable AltiVec */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ + +/* Default MSR for kernel mode. */ +#ifdef CONFIG_APUS_FAST_EXCEPT +#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) +#endif + +#ifndef MSR_KERNEL +#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) +#endif + +#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) + +/* Floating Point Status and Control Register (FPSCR) Fields */ +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ + +/* Special Purpose Registers (SPRNs)*/ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#define DABR_TRANSLATION (1UL << 2) +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#define DSISR_NOHPTE 0x40000000 /* no translation found */ +#define DSISR_PROTFAULT 0x08000000 /* protection fault */ +#define DSISR_ISSTORE 0x02000000 /* access was a store */ +#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ +#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ +#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ +#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ +#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ +#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ +#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */ + +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DER 0x095 /* Debug Enable Regsiter */ +#define DER_RSTE 0x40000000 /* Reset Interrupt */ +#define DER_CHSTPE 0x20000000 /* Check Stop */ +#define DER_MCIE 0x10000000 /* Machine Check Interrupt */ +#define DER_EXTIE 0x02000000 /* External Interrupt */ +#define DER_ALIE 0x01000000 /* Alignment Interrupt */ +#define DER_PRIE 0x00800000 /* Program Interrupt */ +#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */ +#define DER_DECIE 0x00200000 /* Decrementer Interrupt */ +#define DER_SYSIE 0x00040000 /* System Call Interrupt */ +#define DER_TRE 0x00020000 /* Trace Interrupt */ +#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */ +#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */ +#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */ +#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */ +#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */ +#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */ +#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */ +#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */ +#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#define SPRN_EAR 0x11A /* External Address Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_TBEN (1<<26) /* Timebase enable - 745x */ +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_STEN (1<<24) /* Software table search enable - 745x */ +#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */ +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ +#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ +#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ +#define HID0_ICE (1<<15) /* Instruction Cache Enable */ +#define HID0_DCE (1<<14) /* Data Cache Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<12) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCI (1<<10) /* Data Cache Invalidate */ +#define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_DAPUEN (1<<8) /* Debug APU enable */ +#define HID0_SGE (1<<7) /* Store Gathering Enable */ +#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ +#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ +#define HID0_LRSTK (1<<4) /* Link register stack - 745x */ +#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ +#define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ +#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ + +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ +#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */ +#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ +#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ +#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ +#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ +#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ +#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ +#define HID1_PS (1<<16) /* 750FX PLL selection */ +#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#define SPRN_HID4 0x3F4 /* 970 HID4 */ +#define SPRN_HID5 0x3F6 /* 970 HID5 */ +#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#endif +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ +#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ +#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */ +#define ICTRL_EICP 0x00000100 /* enable icache par. check */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_L2CR2 0x3f8 +#define L2CR_L2E 0x80000000 /* L2 enable */ +#define L2CR_L2PE 0x40000000 /* L2 parity enable */ +#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */ +#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */ +#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */ +#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */ +#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */ +#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */ +#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */ +#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */ +#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */ +#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */ +#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */ +#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */ +#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */ +#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */ +#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */ +#define L2CR_L2DO 0x00400000 /* L2 data only */ +#define L2CR_L2I 0x00200000 /* L2 global invalidate */ +#define L2CR_L2CTL 0x00100000 /* L2 RAM control */ +#define L2CR_L2WT 0x00080000 /* L2 write-through */ +#define L2CR_L2TS 0x00040000 /* L2 test support */ +#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */ +#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */ +#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */ +#define L2CR_L2SL 0x00008000 /* L2 DLL slow */ +#define L2CR_L2DF 0x00004000 /* L2 differential clock */ +#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ +#define L2CR_L2IP 0x00000001 /* L2 GI in progress */ +#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */ +#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */ +#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */ +#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */ +#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */ +#define L3CR_L3E 0x80000000 /* L3 enable */ +#define L3CR_L3PE 0x40000000 /* L3 data parity enable */ +#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */ +#define L3CR_L3SIZ 0x10000000 /* L3 size */ +#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */ +#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */ +#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */ +#define L3CR_L3IO 0x00400000 /* L3 instruction only */ +#define L3CR_L3SPO 0x00040000 /* L3 sample point override */ +#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */ +#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */ +#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */ +#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */ +#define L3CR_L3I 0x00000400 /* L3 global invalidate */ +#define L3CR_L3RT 0x00000300 /* L3 SRAM type */ +#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */ +#define L3CR_L3DO 0x00000040 /* L3 data only mode */ +#define L3CR_PMEN 0x00000004 /* L3 private memory enable */ +#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */ +#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ +#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ +#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ +#define SPRN_LDSTDB 0x3f4 /* */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#ifndef SPRN_PIR +#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#endif +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ +#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#ifndef SPRN_SVR +#define SPRN_SVR 0x11E /* System Version Register */ +#endif +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +/* these bits were defined in inverted endian sense originally, ugh, confusing */ +#define THRM1_TIN (1 << 31) +#define THRM1_TIV (1 << 30) +#define THRM1_THRES(x) ((x&0x7f)<<23) +#define THRM3_SITV(x) ((x&0x3fff)<<1) +#define THRM1_TID (1<<2) +#define THRM1_TIE (1<<1) +#define THRM1_V (1<<0) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<0) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ + +/* Bit definitions for MMCR0 and PMC1 / PMC2. */ +#define MMCR0_PMC1_CYCLES (1 << 7) +#define MMCR0_PMC1_ICACHEMISS (5 << 7) +#define MMCR0_PMC1_DTLB (6 << 7) +#define MMCR0_PMC2_DCACHEMISS 0x6 +#define MMCR0_PMC2_CYCLES 0x1 +#define MMCR0_PMC2_ITLB 0x7 +#define MMCR0_PMC2_LOADMISSTIME 0x5 +#define MMCR0_PMXE (1 << 26) + +/* Processor Version Register */ + +/* Processor Version Register (PVR) field extraction */ + +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ + +/* + * IBM has further subdivided the standard PowerPC 16-bit version and + * revision subfields of the PVR for the PowerPC 403s into the following: + */ + +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ + +/* Processor Version Numbers */ + +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_STB03XXX 0x40310000 +#define PVR_NP405H 0x41410000 +#define PVR_NP405L 0x41610000 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 +#define PVR_8540 0x80200000 +#define PVR_8560 0x80200000 +/* + * For the 8xx processors, all of them report the same PVR family for + * the PowerPC core. The various versions of these processors must be + * differentiated by the version number in the Communication Processor + * Module (CPM). + */ +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_8240 0x00810100 +#define PVR_8245 0x80811014 +#define PVR_8260 PVR_8240 + +#if 0 +/* Segment Registers */ +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 +#endif + +/* Macros for setting and retrieving special purpose registers */ +#ifndef __ASSEMBLY__ +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," __stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) + +#define mfsrin(v) ({unsigned int rval; \ + asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ + rval;}) + +#define proc_trap() asm volatile("trap") +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_PPC_REGS_H__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h new file mode 100644 index 00000000000..be542efb32d --- /dev/null +++ b/include/asm-powerpc/system.h @@ -0,0 +1,350 @@ +/* + * Copyright (C) 1999 Cort Dougan + */ +#ifndef __PPC_SYSTEM_H +#define __PPC_SYSTEM_H + +#include +#include + +#include +#include + +/* + * Memory barrier. + * The sync instruction guarantees that all memory accesses initiated + * by this processor have been performed (with respect to all other + * mechanisms that access memory). The eieio instruction is a barrier + * providing an ordering (separately) for (a) cacheable stores and (b) + * loads and stores to non-cacheable memory (e.g. I/O devices). + * + * mb() prevents loads and stores being reordered across this point. + * rmb() prevents loads being reordered across this point. + * wmb() prevents stores being reordered across this point. + * read_barrier_depends() prevents data-dependent loads being reordered + * across this point (nop on PPC). + * + * We have to use the sync instructions for mb(), since lwsync doesn't + * order loads with respect to previous stores. Lwsync is fine for + * rmb(), though. Note that lwsync is interpreted as sync by + * 32-bit and older 64-bit CPUs. + * + * For wmb(), we use sync since wmb is used in drivers to order + * stores to system memory with respect to writes to the device. + * However, smp_wmb() can be a lighter-weight eieio barrier on + * SMP since it is only used to order updates to system memory. + */ +#define mb() __asm__ __volatile__ ("sync" : : : "memory") +#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory") +#define wmb() __asm__ __volatile__ ("sync" : : : "memory") +#define read_barrier_depends() do { } while(0) + +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif /* CONFIG_SMP */ + +#ifdef __KERNEL__ +struct task_struct; +struct pt_regs; + +#ifdef CONFIG_DEBUGGER + +extern int (*__debugger)(struct pt_regs *regs); +extern int (*__debugger_ipi)(struct pt_regs *regs); +extern int (*__debugger_bpt)(struct pt_regs *regs); +extern int (*__debugger_sstep)(struct pt_regs *regs); +extern int (*__debugger_iabr_match)(struct pt_regs *regs); +extern int (*__debugger_dabr_match)(struct pt_regs *regs); +extern int (*__debugger_fault_handler)(struct pt_regs *regs); + +#define DEBUGGER_BOILERPLATE(__NAME) \ +static inline int __NAME(struct pt_regs *regs) \ +{ \ + if (unlikely(__ ## __NAME)) \ + return __ ## __NAME(regs); \ + return 0; \ +} + +DEBUGGER_BOILERPLATE(debugger) +DEBUGGER_BOILERPLATE(debugger_ipi) +DEBUGGER_BOILERPLATE(debugger_bpt) +DEBUGGER_BOILERPLATE(debugger_sstep) +DEBUGGER_BOILERPLATE(debugger_iabr_match) +DEBUGGER_BOILERPLATE(debugger_dabr_match) +DEBUGGER_BOILERPLATE(debugger_fault_handler) + +#ifdef CONFIG_XMON +extern void xmon_init(int enable); +#endif + +#else +static inline int debugger(struct pt_regs *regs) { return 0; } +static inline int debugger_ipi(struct pt_regs *regs) { return 0; } +static inline int debugger_bpt(struct pt_regs *regs) { return 0; } +static inline int debugger_sstep(struct pt_regs *regs) { return 0; } +static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } +static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } +static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } +#endif + +extern int set_dabr(unsigned long dabr); +extern void print_backtrace(unsigned long *); +extern void show_regs(struct pt_regs * regs); +extern void flush_instruction_cache(void); +extern void hard_reset_now(void); +extern void poweroff_now(void); + +#ifdef CONFIG_6xx +extern long _get_L2CR(void); +extern long _get_L3CR(void); +extern void _set_L2CR(unsigned long); +extern void _set_L3CR(unsigned long); +#else +#define _get_L2CR() 0L +#define _get_L3CR() 0L +#define _set_L2CR(val) do { } while(0) +#define _set_L3CR(val) do { } while(0) +#endif + +extern void via_cuda_init(void); +extern void pmac_nvram_init(void); +extern void read_rtc_time(void); +extern void pmac_find_display(void); +extern void giveup_fpu(struct task_struct *); +extern void enable_kernel_fp(void); +extern void flush_fp_to_thread(struct task_struct *); +extern void enable_kernel_altivec(void); +extern void giveup_altivec(struct task_struct *); +extern void load_up_altivec(struct task_struct *); +extern void giveup_spe(struct task_struct *); +extern void load_up_spe(struct task_struct *); +extern int fix_alignment(struct pt_regs *); +extern void cvt_fd(float *from, double *to, unsigned long *fpscr); +extern void cvt_df(double *from, float *to, unsigned long *fpscr); + +#ifdef CONFIG_ALTIVEC +extern void flush_altivec_to_thread(struct task_struct *); +#else +static inline void flush_altivec_to_thread(struct task_struct *t) +{ +} +#endif + +#ifdef CONFIG_SPE +extern void flush_spe_to_thread(struct task_struct *); +#else +static inline void flush_spe_to_thread(struct task_struct *t) +{ +} +#endif + +extern int call_rtas(const char *, int, int, unsigned long *, ...); +extern void cacheable_memzero(void *p, unsigned int nb); +extern void *cacheable_memcpy(void *, const void *, unsigned int); +extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); +extern void bad_page_fault(struct pt_regs *, unsigned long, int); +extern int die(const char *, struct pt_regs *, long); +extern void _exception(int, struct pt_regs *, int, unsigned long); +#ifdef CONFIG_BOOKE_WDT +extern u32 booke_wdt_enabled; +extern u32 booke_wdt_period; +#endif /* CONFIG_BOOKE_WDT */ + +/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */ +extern unsigned char e2a(unsigned char); + +struct device_node; +extern void note_scsi_host(struct device_node *, void *); + +extern struct task_struct *__switch_to(struct task_struct *, + struct task_struct *); +#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) + +struct thread_struct; +extern struct task_struct *_switch(struct thread_struct *prev, + struct thread_struct *next); + +extern unsigned int rtas_data; + +/* + * Atomic exchange + * + * Changes the memory location '*ptr' to be val and returns + * the previous value stored there. + */ +static __inline__ unsigned long +__xchg_u32(volatile void *p, unsigned long val) +{ + unsigned long prev; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: lwarx %0,0,%2 \n" + PPC405_ERR77(0,%2) +" stwcx. %3,0,%2 \n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (prev), "=m" (*(volatile unsigned int *)p) + : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p) + : "cc", "memory"); + + return prev; +} + +#ifdef CONFIG_PPC64 +static __inline__ unsigned long +__xchg_u64(volatile void *p, unsigned long val) +{ + unsigned long prev; + + __asm__ __volatile__( + EIEIO_ON_SMP +"1: ldarx %0,0,%2 \n" + PPC405_ERR77(0,%2) +" stdcx. %3,0,%2 \n\ + bne- 1b" + ISYNC_ON_SMP + : "=&r" (prev), "=m" (*(volatile unsigned long *)p) + : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) + : "cc", "memory"); + + return prev; +} +#endif + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid xchg(). + */ +extern void __xchg_called_with_bad_pointer(void); + +static __inline__ unsigned long +__xchg(volatile void *ptr, unsigned long x, unsigned int size) +{ + switch (size) { + case 4: + return __xchg_u32(ptr, x); +#ifdef CONFIG_PPC64 + case 8: + return __xchg_u64(ptr, x); +#endif + } + __xchg_called_with_bad_pointer(); + return x; +} + +#define xchg(ptr,x) \ + ({ \ + __typeof__(*(ptr)) _x_ = (x); \ + (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ + }) + +#define tas(ptr) (xchg((ptr),1)) + +/* + * Compare and exchange - if *p == old, set it to new, + * and return the old value of *p. + */ +#define __HAVE_ARCH_CMPXCHG 1 + +static __inline__ unsigned long +__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new) +{ + unsigned int prev; + + __asm__ __volatile__ ( + EIEIO_ON_SMP +"1: lwarx %0,0,%2 # __cmpxchg_u32\n\ + cmpw 0,%0,%3\n\ + bne- 2f\n" + PPC405_ERR77(0,%2) +" stwcx. %4,0,%2\n\ + bne- 1b" + ISYNC_ON_SMP + "\n\ +2:" + : "=&r" (prev), "=m" (*p) + : "r" (p), "r" (old), "r" (new), "m" (*p) + : "cc", "memory"); + + return prev; +} + +#ifdef CONFIG_PPC64 +static __inline__ unsigned long +__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new) +{ + unsigned long prev; + + __asm__ __volatile__ ( + EIEIO_ON_SMP +"1: ldarx %0,0,%2 # __cmpxchg_u64\n\ + cmpd 0,%0,%3\n\ + bne- 2f\n\ + stdcx. %4,0,%2\n\ + bne- 1b" + ISYNC_ON_SMP + "\n\ +2:" + : "=&r" (prev), "=m" (*p) + : "r" (p), "r" (old), "r" (new), "m" (*p) + : "cc", "memory"); + + return prev; +} +#endif + +/* This function doesn't exist, so you'll get a linker error + if something tries to do an invalid cmpxchg(). */ +extern void __cmpxchg_called_with_bad_pointer(void); + +static __inline__ unsigned long +__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, + unsigned int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); +#ifdef CONFIG_PPC64 + case 8: + return __cmpxchg_u64(ptr, old, new); +#endif + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,o,n) \ + ({ \ + __typeof__(*(ptr)) _o_ = (o); \ + __typeof__(*(ptr)) _n_ = (n); \ + (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ + (unsigned long)_n_, sizeof(*(ptr))); \ + }) + +#ifdef CONFIG_PPC64 +/* + * We handle most unaligned accesses in hardware. On the other hand + * unaligned DMA can be very expensive on some ppc64 IO chips (it does + * powers of 2 writes until it reaches sufficient alignment). + * + * Based on this we disable the IP header alignment in network drivers. + */ +#define NET_IP_ALIGN 0 +#endif + +#define arch_align_stack(x) (x) + +#endif /* __KERNEL__ */ +#endif /* __PPC_SYSTEM_H */ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h index 829481c0a9d..79c1be3dfe6 100644 --- a/include/asm-ppc/smp.h +++ b/include/asm-ppc/smp.h @@ -45,30 +45,21 @@ extern int __cpu_disable(void); extern void __cpu_die(unsigned int cpu); extern void cpu_die(void) __attribute__((noreturn)); -#define NO_PROC_ID 0xFF /* No processor magic marker */ -#define PROC_CHANGE_PENALTY 20 - #define raw_smp_processor_id() (current_thread_info()->cpu) extern int __cpu_up(unsigned int cpu); extern int smp_hw_index[]; -#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) - -struct klock_info_struct { - unsigned long kernel_flag; - unsigned char akp; -}; - -extern struct klock_info_struct klock_info; -#define KLOCK_HELD 0xffffffff -#define KLOCK_CLEAR 0x0 +#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) +#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)]) #endif /* __ASSEMBLY__ */ #else /* !(CONFIG_SMP) */ static inline void cpu_die(void) { } +#define get_hard_smp_processor_id(cpu) 0 +#define hard_smp_processor_id() 0 #endif /* !(CONFIG_SMP) */ -- cgit v1.2.3-70-g09d2 From 6b67f62cf655c80147435544a2f8f6f57e07ec87 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Tue, 27 Sep 2005 14:09:39 +1000 Subject: [PATCH] ppc64 g5: merge tree build fix We removed __pmacdata in the merge. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras --- drivers/macintosh/smu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c index a85ac18dd21..5f283529620 100644 --- a/drivers/macintosh/smu.c +++ b/drivers/macintosh/smu.c @@ -1092,7 +1092,7 @@ static int smu_release(struct inode *inode, struct file *file) } -static struct file_operations smu_device_fops __pmacdata = { +static struct file_operations smu_device_fops = { .llseek = no_llseek, .read = smu_read, .write = smu_write, @@ -1101,7 +1101,7 @@ static struct file_operations smu_device_fops __pmacdata = { .release = smu_release, }; -static struct miscdevice pmu_device __pmacdata = { +static struct miscdevice pmu_device = { MISC_DYNAMIC_MINOR, "smu", &smu_device_fops }; -- cgit v1.2.3-70-g09d2 From 689b9d74b1c00e1316fbb7d1e912fe1227fdb1ab Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 30 Sep 2005 17:09:07 +1000 Subject: drm: add option to force writeback off. In order to get some better debugging from people about certain hangs/crashes we need to be able to turn AGP writeback off permanently... Signed-off-by: Dave Airlie --- drivers/char/drm/radeon_cp.c | 4 ++++ drivers/char/drm/radeon_drv.c | 5 +++++ drivers/char/drm/radeon_drv.h | 1 + 3 files changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 447bfbe0da8..e64d680899f 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c @@ -1205,6 +1205,10 @@ static void radeon_cp_init_ring_buffer(drm_device_t * dev, dev_priv->writeback_works = 0; DRM_DEBUG("writeback test failed\n"); } + if (radeon_no_wb == 1) { + dev_priv->writeback_works = 0; + DRM_DEBUG("writeback forced off\n"); + } dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c index 6c1766120c1..7074d01ed1d 100644 --- a/drivers/char/drm/radeon_drv.c +++ b/drivers/char/drm/radeon_drv.c @@ -37,6 +37,11 @@ #include "drm_pciids.h" +int radeon_no_wb; + +MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers\n"); +module_param_named(no_wb, radeon_no_wb, int, 0444); + static int postinit(struct drm_device *dev, unsigned long flags) { DRM_INFO("Initialized %s %d.%d.%d %s on minor %d: %s\n", diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index e36076981d1..3c747348866 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -281,6 +281,7 @@ typedef struct drm_radeon_buf_priv { u32 age; } drm_radeon_buf_priv_t; +extern int radeon_no_wb; /* radeon_cp.c */ extern int radeon_cp_init(DRM_IOCTL_ARGS); extern int radeon_cp_start(DRM_IOCTL_ARGS); -- cgit v1.2.3-70-g09d2 From b3a83639895a422b25f72eec0a5d1d88c3ac4e9e Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 30 Sep 2005 18:37:36 +1000 Subject: drm: fix all sparse warning on 32-bit x86 Finally cleaned up the sparse warnings for the drm. Signed-off-by: Dave Airlie --- drivers/char/drm/drm_bufs.c | 6 +++--- drivers/char/drm/drm_context.c | 4 ++-- drivers/char/drm/i810_drv.c | 3 --- drivers/char/drm/i810_drv.h | 3 +++ drivers/char/drm/i830_drv.c | 3 --- drivers/char/drm/i830_drv.h | 16 +++++++--------- drivers/char/drm/i915_drv.c | 3 --- drivers/char/drm/i915_drv.h | 3 +++ drivers/char/drm/mga_drv.c | 5 +---- drivers/char/drm/mga_drv.h | 3 +++ drivers/char/drm/r128_drv.c | 3 --- drivers/char/drm/r128_drv.h | 3 +++ drivers/char/drm/r300_cmdbuf.c | 34 +++++++++++++++++----------------- drivers/char/drm/radeon_drv.c | 3 --- drivers/char/drm/radeon_drv.h | 12 +++++++++++- drivers/char/drm/radeon_state.c | 23 +++++++++++------------ drivers/char/drm/savage_drv.c | 3 --- drivers/char/drm/savage_drv.h | 3 +++ drivers/char/drm/savage_state.c | 6 ++---- drivers/char/drm/sis_drv.c | 3 --- drivers/char/drm/sis_drv.h | 3 +++ drivers/char/drm/via_drv.h | 3 +++ 22 files changed, 75 insertions(+), 73 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c index e3d372ad007..58e513a4474 100644 --- a/drivers/char/drm/drm_bufs.c +++ b/drivers/char/drm/drm_bufs.c @@ -117,9 +117,9 @@ static __inline__ unsigned int HandleID(unsigned long lhandle, * type. Adds the map to the map list drm_device::maplist. Adds MTRR's where * applicable and if supported by the kernel. */ -int drm_addmap_core(drm_device_t * dev, unsigned int offset, - unsigned int size, drm_map_type_t type, - drm_map_flags_t flags, drm_map_list_t ** maplist) +static int drm_addmap_core(drm_device_t * dev, unsigned int offset, + unsigned int size, drm_map_type_t type, + drm_map_flags_t flags, drm_map_list_t ** maplist) { drm_map_t *map; drm_map_list_t *list; diff --git a/drivers/char/drm/drm_context.c b/drivers/char/drm/drm_context.c index 6380127be28..bdd168d88f4 100644 --- a/drivers/char/drm/drm_context.c +++ b/drivers/char/drm/drm_context.c @@ -232,7 +232,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp, map = dev->context_sareas[request.ctx_id]; up(&dev->struct_sem); - request.handle = 0; + request.handle = NULL; list_for_each_entry(_entry, &dev->maplist->head, head) { if (_entry->map == map) { request.handle = @@ -240,7 +240,7 @@ int drm_getsareactx(struct inode *inode, struct file *filp, break; } } - if (request.handle == 0) + if (request.handle == NULL) return -EINVAL; if (copy_to_user(argp, &request, sizeof(request))) diff --git a/drivers/char/drm/i810_drv.c b/drivers/char/drm/i810_drv.c index 327e2f1cc99..070cef6c2b4 100644 --- a/drivers/char/drm/i810_drv.c +++ b/drivers/char/drm/i810_drv.c @@ -74,9 +74,6 @@ static struct pci_device_id pciidlist[] = { i810_PCI_IDS }; -extern drm_ioctl_desc_t i810_ioctls[]; -extern int i810_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | diff --git a/drivers/char/drm/i810_drv.h b/drivers/char/drm/i810_drv.h index 2d6b594afa0..c78f36aaa2f 100644 --- a/drivers/char/drm/i810_drv.h +++ b/drivers/char/drm/i810_drv.h @@ -121,6 +121,9 @@ extern void i810_driver_pretakedown(drm_device_t * dev); extern void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp); extern int i810_driver_device_is_agp(drm_device_t * dev); +extern drm_ioctl_desc_t i810_ioctls[]; +extern int i810_max_ioctl; + #define I810_BASE(reg) ((unsigned long) \ dev_priv->mmio_map->handle) #define I810_ADDR(reg) (I810_BASE(reg) + reg) diff --git a/drivers/char/drm/i830_drv.c b/drivers/char/drm/i830_drv.c index 6dad356450b..acd821e8fe4 100644 --- a/drivers/char/drm/i830_drv.c +++ b/drivers/char/drm/i830_drv.c @@ -75,9 +75,6 @@ static struct pci_device_id pciidlist[] = { i830_PCI_IDS }; -extern drm_ioctl_desc_t i830_ioctls[]; -extern int i830_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | diff --git a/drivers/char/drm/i830_drv.h b/drivers/char/drm/i830_drv.h index 99835465c44..bc4bd49fb0c 100644 --- a/drivers/char/drm/i830_drv.h +++ b/drivers/char/drm/i830_drv.h @@ -120,6 +120,9 @@ typedef struct drm_i830_private { } drm_i830_private_t; +extern drm_ioctl_desc_t i830_ioctls[]; +extern int i830_max_ioctl; + /* i830_dma.c */ extern void i830_reclaim_buffers(drm_device_t * dev, struct file *filp); @@ -139,15 +142,10 @@ extern int i830_driver_dma_quiescent(drm_device_t * dev); extern void i830_driver_prerelease(drm_device_t * dev, DRMFILE filp); extern int i830_driver_device_is_agp(drm_device_t * dev); -#define I830_BASE(reg) ((unsigned long) \ - dev_priv->mmio_map->handle) -#define I830_ADDR(reg) (I830_BASE(reg) + reg) -#define I830_DEREF(reg) *(__volatile__ unsigned int *)I830_ADDR(reg) -#define I830_READ(reg) readl((volatile u32 *)I830_ADDR(reg)) -#define I830_WRITE(reg,val) writel(val, (volatile u32 *)I830_ADDR(reg)) -#define I830_DEREF16(reg) *(__volatile__ u16 *)I830_ADDR(reg) -#define I830_READ16(reg) I830_DEREF16(reg) -#define I830_WRITE16(reg,val) do { I830_DEREF16(reg) = val; } while (0) +#define I830_READ(reg) DRM_READ32(dev_priv->mmio_map, reg) +#define I830_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, reg, val) +#define I830_READ16(reg) DRM_READ16(dev_priv->mmio_map, reg) +#define I830_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, reg, val) #define I830_VERBOSE 0 diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c index 665da6ac11c..0508240f4e3 100644 --- a/drivers/char/drm/i915_drv.c +++ b/drivers/char/drm/i915_drv.c @@ -69,9 +69,6 @@ static struct pci_device_id pciidlist[] = { i915_PCI_IDS }; -extern drm_ioctl_desc_t i915_ioctls[]; -extern int i915_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index 511ef1d8763..17e457c73dc 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h @@ -99,6 +99,9 @@ typedef struct drm_i915_private { struct mem_block *agp_heap; } drm_i915_private_t; +extern drm_ioctl_desc_t i915_ioctls[]; +extern int i915_max_ioctl; + /* i915_dma.c */ extern void i915_kernel_lost_context(drm_device_t * dev); extern void i915_driver_pretakedown(drm_device_t * dev); diff --git a/drivers/char/drm/mga_drv.c b/drivers/char/drm/mga_drv.c index 220037a91c0..0cc7c305a7f 100644 --- a/drivers/char/drm/mga_drv.c +++ b/drivers/char/drm/mga_drv.c @@ -78,9 +78,6 @@ static struct pci_device_id pciidlist[] = { mga_PCI_IDS }; -extern drm_ioctl_desc_t mga_ioctls[]; -extern int mga_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | @@ -151,7 +148,7 @@ MODULE_LICENSE("GPL and additional rights"); * \returns * If the device is a PCI G450, zero is returned. Otherwise 2 is returned. */ -int mga_driver_device_is_agp(drm_device_t * dev) +static int mga_driver_device_is_agp(drm_device_t * dev) { const struct pci_dev *const pdev = dev->pdev; diff --git a/drivers/char/drm/mga_drv.h b/drivers/char/drm/mga_drv.h index 05f0f913ded..474853deecf 100644 --- a/drivers/char/drm/mga_drv.h +++ b/drivers/char/drm/mga_drv.h @@ -148,6 +148,9 @@ typedef struct drm_mga_private { unsigned int agp_pages; } drm_mga_private_t; +extern drm_ioctl_desc_t mga_ioctls[]; +extern int mga_max_ioctl; + /* mga_dma.c */ extern int mga_driver_preinit(drm_device_t * dev, unsigned long flags); extern int mga_dma_bootstrap(DRM_IOCTL_ARGS); diff --git a/drivers/char/drm/r128_drv.c b/drivers/char/drm/r128_drv.c index 4d9224645f0..1661e735140 100644 --- a/drivers/char/drm/r128_drv.c +++ b/drivers/char/drm/r128_drv.c @@ -66,9 +66,6 @@ static struct pci_device_id pciidlist[] = { r128_PCI_IDS }; -extern drm_ioctl_desc_t r128_ioctls[]; -extern int r128_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | diff --git a/drivers/char/drm/r128_drv.h b/drivers/char/drm/r128_drv.h index 87c5e1381ba..5c79e40eb88 100644 --- a/drivers/char/drm/r128_drv.h +++ b/drivers/char/drm/r128_drv.h @@ -128,6 +128,9 @@ typedef struct drm_r128_buf_priv { drm_r128_freelist_t *list_entry; } drm_r128_buf_priv_t; +extern drm_ioctl_desc_t r128_ioctls[]; +extern int r128_max_ioctl; + /* r128_cce.c */ extern int r128_cce_init(DRM_IOCTL_ARGS); extern int r128_cce_start(DRM_IOCTL_ARGS); diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c index aa66f46279e..3a1ac5f78b4 100644 --- a/drivers/char/drm/r300_cmdbuf.c +++ b/drivers/char/drm/r300_cmdbuf.c @@ -53,7 +53,7 @@ static const int r300_cliprect_cntl[4] = { * buffer, starting with index n. */ static int r300_emit_cliprects(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf, int n) + drm_radeon_kcmd_buffer_t * cmdbuf, int n) { drm_clip_rect_t box; int nr; @@ -131,7 +131,7 @@ static int r300_emit_cliprects(drm_radeon_private_t * dev_priv, return 0; } -u8 r300_reg_flags[0x10000 >> 2]; +static u8 r300_reg_flags[0x10000 >> 2]; void r300_init_reg_flags(void) { @@ -260,7 +260,7 @@ static __inline__ int r300_check_offset(drm_radeon_private_t * dev_priv, static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t + drm_radeon_kcmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) @@ -281,7 +281,7 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * return DRM_ERR(EINVAL); } for (i = 0; i < sz; i++) { - values[i] = ((int __user *)cmdbuf->buf)[i]; + values[i] = ((int *)cmdbuf->buf)[i]; switch (r300_reg_flags[(reg >> 2) + i]) { case MARK_SAFE: break; @@ -318,7 +318,7 @@ static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t * * Note that checks are performed on contents and addresses of the registers */ static __inline__ int r300_emit_packet0(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf, + drm_radeon_kcmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) { int reg; @@ -349,7 +349,7 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t * dev_priv, BEGIN_RING(1 + sz); OUT_RING(CP_PACKET0(reg, sz - 1)); - OUT_RING_TABLE((int __user *)cmdbuf->buf, sz); + OUT_RING_TABLE((int *)cmdbuf->buf, sz); ADVANCE_RING(); cmdbuf->buf += sz * 4; @@ -364,7 +364,7 @@ static __inline__ int r300_emit_packet0(drm_radeon_private_t * dev_priv, * Called by r300_do_cp_cmdbuf. */ static __inline__ int r300_emit_vpu(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf, + drm_radeon_kcmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) { int sz; @@ -386,7 +386,7 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t * dev_priv, OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0); OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr); OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1)); - OUT_RING_TABLE((int __user *)cmdbuf->buf, sz * 4); + OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4); ADVANCE_RING(); @@ -401,7 +401,7 @@ static __inline__ int r300_emit_vpu(drm_radeon_private_t * dev_priv, * Called by r300_emit_packet3. */ static __inline__ int r300_emit_clear(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t * cmdbuf) { RING_LOCALS; @@ -412,7 +412,7 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t * dev_priv, OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | (1 << R300_PRIM_NUM_VERTICES_SHIFT)); - OUT_RING_TABLE((int __user *)cmdbuf->buf, 8); + OUT_RING_TABLE((int *)cmdbuf->buf, 8); ADVANCE_RING(); cmdbuf->buf += 8 * 4; @@ -422,7 +422,7 @@ static __inline__ int r300_emit_clear(drm_radeon_private_t * dev_priv, } static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf, + drm_radeon_kcmd_buffer_t * cmdbuf, u32 header) { int count, i, k; @@ -490,7 +490,7 @@ static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t * dev_priv, } static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t * cmdbuf) { u32 header; int count; @@ -503,7 +503,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv, We need to be smarter. */ /* obtain first word - actual packet3 header */ - header = *(u32 __user *) cmdbuf->buf; + header = *(u32 *) cmdbuf->buf; /* Is it packet 3 ? */ if ((header >> 30) != 0x3) { @@ -541,7 +541,7 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv, BEGIN_RING(count + 2); OUT_RING(header); - OUT_RING_TABLE((int __user *)(cmdbuf->buf + 4), count + 1); + OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1); ADVANCE_RING(); cmdbuf->buf += (count + 2) * 4; @@ -555,12 +555,12 @@ static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t * dev_priv, * Called by r300_do_cp_cmdbuf. */ static __inline__ int r300_emit_packet3(drm_radeon_private_t * dev_priv, - drm_radeon_cmd_buffer_t * cmdbuf, + drm_radeon_kcmd_buffer_t * cmdbuf, drm_r300_cmd_header_t header) { int n; int ret; - char __user *orig_buf = cmdbuf->buf; + char *orig_buf = cmdbuf->buf; int orig_bufsz = cmdbuf->bufsz; /* This is a do-while-loop so that we run the interior at least once, @@ -659,7 +659,7 @@ static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf) */ int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, - drm_file_t * filp_priv, drm_radeon_cmd_buffer_t * cmdbuf) + drm_file_t * filp_priv, drm_radeon_kcmd_buffer_t * cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; drm_device_dma_t *dma = dev->dma; diff --git a/drivers/char/drm/radeon_drv.c b/drivers/char/drm/radeon_drv.c index 7074d01ed1d..ee49670d816 100644 --- a/drivers/char/drm/radeon_drv.c +++ b/drivers/char/drm/radeon_drv.c @@ -71,9 +71,6 @@ static struct pci_device_id pciidlist[] = { radeon_PCI_IDS }; -extern drm_ioctl_desc_t radeon_ioctls[]; -extern int radeon_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 3c747348866..120ee5a8ebc 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h @@ -281,7 +281,17 @@ typedef struct drm_radeon_buf_priv { u32 age; } drm_radeon_buf_priv_t; +typedef struct drm_radeon_kcmd_buffer { + int bufsz; + char *buf; + int nbox; + drm_clip_rect_t __user *boxes; +} drm_radeon_kcmd_buffer_t; + extern int radeon_no_wb; +extern drm_ioctl_desc_t radeon_ioctls[]; +extern int radeon_max_ioctl; + /* radeon_cp.c */ extern int radeon_cp_init(DRM_IOCTL_ARGS); extern int radeon_cp_start(DRM_IOCTL_ARGS); @@ -340,7 +350,7 @@ extern void r300_init_reg_flags(void); extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, drm_file_t * filp_priv, - drm_radeon_cmd_buffer_t * cmdbuf); + drm_radeon_kcmd_buffer_t * cmdbuf); /* Flags for stats.boxes */ diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 2eae60bd340..231ac1438c6 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c @@ -40,7 +40,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * dev_priv, drm_file_t * filp_priv, - u32 * offset) + u32 *offset) { u32 off = *offset; struct drm_radeon_driver_file_fields *radeon_priv; @@ -66,7 +66,7 @@ static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * dev_priv, drm_file_t * filp_priv, - int id, u32 __user * data) + int id, u32 *data) { switch (id) { @@ -240,8 +240,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * dev_priv, drm_file_t * filp_priv, - drm_radeon_cmd_buffer_t * - cmdbuf, + drm_radeon_kcmd_buffer_t *cmdbuf, unsigned int *cmdsz) { u32 *cmd = (u32 *) cmdbuf->buf; @@ -2564,7 +2563,7 @@ static int radeon_cp_vertex2(DRM_IOCTL_ARGS) static int radeon_emit_packets(drm_radeon_private_t * dev_priv, drm_file_t * filp_priv, drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t *cmdbuf) { int id = (int)header.packet.packet_id; int sz, reg; @@ -2599,7 +2598,7 @@ static int radeon_emit_packets(drm_radeon_private_t * dev_priv, static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv, drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int start = header.scalars.offset; @@ -2621,7 +2620,7 @@ static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv, */ static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv, drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t * cmdbuf) { int sz = header.scalars.count; int start = ((unsigned int)header.scalars.offset) + 0x100; @@ -2641,7 +2640,7 @@ static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv, static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv, drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t * cmdbuf) { int sz = header.vectors.count; int start = header.vectors.offset; @@ -2662,7 +2661,7 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv, static int radeon_emit_packet3(drm_device_t * dev, drm_file_t * filp_priv, - drm_radeon_cmd_buffer_t * cmdbuf) + drm_radeon_kcmd_buffer_t *cmdbuf) { drm_radeon_private_t *dev_priv = dev->dev_private; unsigned int cmdsz; @@ -2688,7 +2687,7 @@ static int radeon_emit_packet3(drm_device_t * dev, static int radeon_emit_packet3_cliprect(drm_device_t * dev, drm_file_t * filp_priv, - drm_radeon_cmd_buffer_t * cmdbuf, + drm_radeon_kcmd_buffer_t *cmdbuf, int orig_nbox) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -2785,7 +2784,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) drm_device_dma_t *dma = dev->dma; drm_buf_t *buf = NULL; int idx; - drm_radeon_cmd_buffer_t cmdbuf; + drm_radeon_kcmd_buffer_t cmdbuf; drm_radeon_cmd_header_t header; int orig_nbox, orig_bufsz; char *kbuf = NULL; @@ -2819,7 +2818,7 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); if (kbuf == NULL) return DRM_ERR(ENOMEM); - if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) { + if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf.buf, cmdbuf.bufsz)) { drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); return DRM_ERR(EFAULT); } diff --git a/drivers/char/drm/savage_drv.c b/drivers/char/drm/savage_drv.c index 0906f9a5d8f..22d799cde41 100644 --- a/drivers/char/drm/savage_drv.c +++ b/drivers/char/drm/savage_drv.c @@ -59,9 +59,6 @@ static struct pci_device_id pciidlist[] = { savage_PCI_IDS }; -extern drm_ioctl_desc_t savage_ioctls[]; -extern int savage_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_PCI_DMA, diff --git a/drivers/char/drm/savage_drv.h b/drivers/char/drm/savage_drv.h index 358f4fb2712..a4b0fa998a9 100644 --- a/drivers/char/drm/savage_drv.h +++ b/drivers/char/drm/savage_drv.h @@ -104,6 +104,9 @@ enum savage_family { S3_LAST }; +extern drm_ioctl_desc_t savage_ioctls[]; +extern int savage_max_ioctl; + #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ diff --git a/drivers/char/drm/savage_state.c b/drivers/char/drm/savage_state.c index 39654cb5d57..e87a5d59b99 100644 --- a/drivers/char/drm/savage_state.c +++ b/drivers/char/drm/savage_state.c @@ -816,10 +816,8 @@ static int savage_dispatch_clear(drm_savage_private_t * dev_priv, if (nbox == 0) return 0; - DRM_GET_USER_UNCHECKED(mask, &((const drm_savage_cmd_header_t *)data) - ->clear1.mask); - DRM_GET_USER_UNCHECKED(value, &((const drm_savage_cmd_header_t *)data) - ->clear1.value); + DRM_GET_USER_UNCHECKED(mask, &data->clear1.mask); + DRM_GET_USER_UNCHECKED(value, &data->clear1.value); clear_cmd = BCI_CMD_RECT | BCI_CMD_RECT_XP | BCI_CMD_RECT_YP | BCI_CMD_SEND_COLOR | BCI_CMD_DEST_PBD_NEW; diff --git a/drivers/char/drm/sis_drv.c b/drivers/char/drm/sis_drv.c index 6d0cb222600..3cef10643a8 100644 --- a/drivers/char/drm/sis_drv.c +++ b/drivers/char/drm/sis_drv.c @@ -61,9 +61,6 @@ static struct pci_device_id pciidlist[] = { sisdrv_PCI_IDS }; -extern drm_ioctl_desc_t sis_ioctls[]; -extern int sis_max_ioctl; - static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR, .context_ctor = sis_init_context, diff --git a/drivers/char/drm/sis_drv.h b/drivers/char/drm/sis_drv.h index 4ef3d622641..b1fddad83a9 100644 --- a/drivers/char/drm/sis_drv.h +++ b/drivers/char/drm/sis_drv.h @@ -49,4 +49,7 @@ typedef struct drm_sis_private { extern int sis_init_context(drm_device_t * dev, int context); extern int sis_final_context(drm_device_t * dev, int context); +extern drm_ioctl_desc_t sis_ioctls[]; +extern int sis_max_ioctl; + #endif diff --git a/drivers/char/drm/via_drv.h b/drivers/char/drm/via_drv.h index d902dc2f4fa..7d5daf43797 100644 --- a/drivers/char/drm/via_drv.h +++ b/drivers/char/drm/via_drv.h @@ -112,4 +112,7 @@ extern void via_init_futex(drm_via_private_t * dev_priv); extern void via_cleanup_futex(drm_via_private_t * dev_priv); extern void via_release_futex(drm_via_private_t * dev_priv, int context); +extern int via_parse_command_stream(drm_device_t * dev, const uint32_t * buf, + unsigned int size); + #endif -- cgit v1.2.3-70-g09d2 From 3d5efad953c6d5ba11d5bcb584ef8e906f953a73 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 30 Sep 2005 19:12:46 +1000 Subject: drm: fix drm PCIGART PCI Express support broke PCIGART Signed-off-by: Dave Airlie --- drivers/char/drm/ati_pcigart.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c index d07ce96e9f4..6d3fec160bf 100644 --- a/drivers/char/drm/ati_pcigart.c +++ b/drivers/char/drm/ati_pcigart.c @@ -205,7 +205,8 @@ int drm_ati_pcigart_init(drm_device_t * dev, drm_ati_pcigart_info * gart_info) if (gart_info->is_pcie) *pci_gart = (cpu_to_le32(page_base) >> 8) | 0xc; else - *pci_gart++ = cpu_to_le32(page_base); + *pci_gart = cpu_to_le32(page_base); + *pci_gart++; page_base += ATI_PCIGART_PAGE_SIZE; } } -- cgit v1.2.3-70-g09d2 From 426c1a11a677e39a8c8ed744a521d0f4cb2e417e Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Fri, 14 Oct 2005 14:51:42 +1000 Subject: powerpc: move iSeries/iSeries_pci.h to platforms/iseries The only real user of this file outside platforms/iseries was drivers/net/iseries_veth.c but all it wanted was ISERIES_HV_ADDR() so we move that to abs_addr.h (and lowercase it). Signed-off-by: Stephen Rothwell --- arch/powerpc/platforms/iseries/iommu.c | 6 ++- arch/powerpc/platforms/iseries/mf.c | 9 ++-- arch/powerpc/platforms/iseries/pci.c | 7 ++-- arch/powerpc/platforms/iseries/pci.h | 59 +++++++++++++++++++++++++++ arch/powerpc/platforms/iseries/vpdinfo.c | 8 ++-- arch/ppc64/kernel/pci_iommu.c | 13 ++---- drivers/net/iseries_veth.c | 11 ++--- include/asm-powerpc/iommu.h | 1 + include/asm-powerpc/prom.h | 1 + include/asm-ppc64/abs_addr.h | 7 ++++ include/asm-ppc64/iSeries/iSeries_pci.h | 70 -------------------------------- include/asm-ppc64/pci-bridge.h | 1 + include/asm-ppc64/prom.h | 1 + 13 files changed, 98 insertions(+), 96 deletions(-) create mode 100644 arch/powerpc/platforms/iseries/pci.h delete mode 100644 include/asm-ppc64/iSeries/iSeries_pci.h (limited to 'drivers') diff --git a/arch/powerpc/platforms/iseries/iommu.c b/arch/powerpc/platforms/iseries/iommu.c index e40c50b7cef..e6f4a4ab57b 100644 --- a/arch/powerpc/platforms/iseries/iommu.c +++ b/arch/powerpc/platforms/iseries/iommu.c @@ -30,8 +30,10 @@ #include #include #include +#include #include -#include + +#include "pci.h" extern struct list_head iSeries_Global_Device_List; @@ -127,7 +129,7 @@ static void iommu_table_getparms(struct device_node *dn, parms->itc_slotno = PCI_DN(dn)->LogicalSlot; parms->itc_virtbus = 0; - HvCallXm_getTceTableParms(ISERIES_HV_ADDR(parms)); + HvCallXm_getTceTableParms(iseries_hv_addr(parms)); if (parms->itc_size == 0) panic("PCI_DMA: parms->size is zero, parms is 0x%p", parms); diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c index 82f5abab9af..3f25f7fc79f 100644 --- a/arch/powerpc/platforms/iseries/mf.c +++ b/arch/powerpc/platforms/iseries/mf.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include @@ -1064,10 +1065,10 @@ static void mf_getSrcHistory(char *buffer, int size) ev->event.data.vsp_cmd.lp_index = HvLpConfig_getLpIndex(); ev->event.data.vsp_cmd.result_code = 0xFF; ev->event.data.vsp_cmd.reserved = 0; - ev->event.data.vsp_cmd.sub_data.page[0] = ISERIES_HV_ADDR(pages[0]); - ev->event.data.vsp_cmd.sub_data.page[1] = ISERIES_HV_ADDR(pages[1]); - ev->event.data.vsp_cmd.sub_data.page[2] = ISERIES_HV_ADDR(pages[2]); - ev->event.data.vsp_cmd.sub_data.page[3] = ISERIES_HV_ADDR(pages[3]); + ev->event.data.vsp_cmd.sub_data.page[0] = iseries_hv_addr(pages[0]); + ev->event.data.vsp_cmd.sub_data.page[1] = iseries_hv_addr(pages[1]); + ev->event.data.vsp_cmd.sub_data.page[2] = iseries_hv_addr(pages[2]); + ev->event.data.vsp_cmd.sub_data.page[3] = iseries_hv_addr(pages[3]); mb(); if (signal_event(ev) != 0) return; diff --git a/arch/powerpc/platforms/iseries/pci.c b/arch/powerpc/platforms/iseries/pci.c index f79c5982446..fe34d117581 100644 --- a/arch/powerpc/platforms/iseries/pci.c +++ b/arch/powerpc/platforms/iseries/pci.c @@ -34,15 +34,16 @@ #include #include #include +#include #include #include -#include #include #include #include "irq.h" +#include "pci.h" extern unsigned long io_page_mask; @@ -368,7 +369,7 @@ static void scan_PHB_slots(struct pci_controller *Phb) */ for (IdSel = 1; IdSel < MaxAgents; ++IdSel) { HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel, - ISERIES_HV_ADDR(DevInfo), + iseries_hv_addr(DevInfo), sizeof(struct HvCallPci_DeviceInfo)); if (HvRc == 0) { if (DevInfo->deviceType == HvCallPci_NodeDevice) @@ -409,7 +410,7 @@ static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus, "PCI:Connect EADs: 0x%02X.%02X.%02X\n", bus, SubBus, AgentId); HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId, - ISERIES_HV_ADDR(BridgeInfo), + iseries_hv_addr(BridgeInfo), sizeof(struct HvCallPci_BridgeInfo)); if (HvRc == 0) { printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n", diff --git a/arch/powerpc/platforms/iseries/pci.h b/arch/powerpc/platforms/iseries/pci.h new file mode 100644 index 00000000000..e7d92504cb0 --- /dev/null +++ b/arch/powerpc/platforms/iseries/pci.h @@ -0,0 +1,59 @@ +#ifndef _PLATFORMS_ISERIES_PCI_H +#define _PLATFORMS_ISERIES_PCI_H + +/* + * Created by Allan Trautman on Tue Feb 20, 2001. + * + * Define some useful macros for the iSeries pci routines. + * Copyright (C) 2001 Allan H Trautman, IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the: + * Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, + * Boston, MA 02111-1307 USA + * + * Change Activity: + * Created Feb 20, 2001 + * Added device reset, March 22, 2001 + * Ported to ppc64, May 25, 2001 + * End Change Activity + */ + +#include + +struct pci_dev; /* For Forward Reference */ + +/* + * Gets iSeries Bus, SubBus, DevFn using device_node structure + */ + +#define ISERIES_BUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.busNumber +#define ISERIES_SUBBUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.subBusNumber + +/* + * Decodes Linux DevFn to iSeries DevFn, bridge device, or function. + * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h + */ + +#define ISERIES_PCI_AGENTID(idsel, func) \ + (((idsel & 0x0F) << 4) | (func & 0x07)) +#define ISERIES_ENCODE_DEVICE(agentid) \ + ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07)) + +#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus) ((subbus >> 5) & 0x7) +#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus) ((subbus >> 2) & 0x7) + +extern void iSeries_Device_Information(struct pci_dev*, int); + +#endif /* _PLATFORMS_ISERIES_PCI_H */ diff --git a/arch/powerpc/platforms/iseries/vpdinfo.c b/arch/powerpc/platforms/iseries/vpdinfo.c index d8a6796924e..6bd8da4f17f 100644 --- a/arch/powerpc/platforms/iseries/vpdinfo.c +++ b/arch/powerpc/platforms/iseries/vpdinfo.c @@ -27,12 +27,14 @@ #include #include #include + #include #include - +#include #include #include -#include + +#include "pci.h" /* * Size of Bus VPD data @@ -212,7 +214,7 @@ static void __init iSeries_Get_Location_Code(u16 bus, HvAgentId agent, printk("PCI: Bus VPD Buffer allocation failure.\n"); return; } - BusVpdLen = HvCallPci_getBusVpd(bus, ISERIES_HV_ADDR(BusVpdPtr), + BusVpdLen = HvCallPci_getBusVpd(bus, iseries_hv_addr(BusVpdPtr), BUS_VPDSIZE); if (BusVpdLen == 0) { printk("PCI: Bus VPD Buffer zero length.\n"); diff --git a/arch/ppc64/kernel/pci_iommu.c b/arch/ppc64/kernel/pci_iommu.c index 2114dc9c59b..bdf15dbbf4f 100644 --- a/arch/ppc64/kernel/pci_iommu.c +++ b/arch/ppc64/kernel/pci_iommu.c @@ -1,8 +1,8 @@ /* * arch/ppc64/kernel/pci_iommu.c * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation - * - * Rewrite, cleanup, new allocation schemes: + * + * Rewrite, cleanup, new allocation schemes: * Copyright (C) 2004 Olof Johansson, IBM Corporation * * Dynamic DMA mapping support, platform-independent parts. @@ -11,19 +11,18 @@ * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include #include #include #include @@ -39,10 +38,6 @@ #include #include -#ifdef CONFIG_PPC_ISERIES -#include -#endif /* CONFIG_PPC_ISERIES */ - /* * We can use ->sysdata directly and avoid the extra work in * pci_device_to_OF_node since ->sysdata will have been initialised diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index 3d56cf5a4e2..db3bc2f6f0f 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c @@ -70,8 +70,9 @@ #include #include #include + +#include #include -#include #include #include @@ -1397,13 +1398,13 @@ static inline void veth_build_dma_list(struct dma_chunk *list, * it just at the granularity of iSeries real->absolute * mapping? Indeed, given the way the allocator works, can we * count on them being absolutely contiguous? */ - list[0].addr = ISERIES_HV_ADDR(p); + list[0].addr = iseries_hv_addr(p); list[0].size = min(length, PAGE_SIZE - ((unsigned long)p & ~PAGE_MASK)); done = list[0].size; while (done < length) { - list[i].addr = ISERIES_HV_ADDR(p + done); + list[i].addr = iseries_hv_addr(p + done); list[i].size = min(length-done, PAGE_SIZE); done += list[i].size; i++; @@ -1496,8 +1497,8 @@ static void veth_receive(struct veth_lpar_connection *cnx, cnx->dst_inst, HvLpDma_AddressType_RealAddress, HvLpDma_AddressType_TceIndex, - ISERIES_HV_ADDR(&local_list), - ISERIES_HV_ADDR(&remote_list), + iseries_hv_addr(&local_list), + iseries_hv_addr(&remote_list), length); if (rc != HvLpDma_Rc_Good) { dev_kfree_skb_irq(skb); diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h index f80ec8daf12..9d91bdd667a 100644 --- a/include/asm-powerpc/iommu.h +++ b/include/asm-powerpc/iommu.h @@ -21,6 +21,7 @@ #ifndef _ASM_IOMMU_H #define _ASM_IOMMU_H +#include #include #include #include diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h index efc40980cb4..8a21791c7ca 100644 --- a/include/asm-powerpc/prom.h +++ b/include/asm-powerpc/prom.h @@ -15,6 +15,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ +#include #include #include #include diff --git a/include/asm-ppc64/abs_addr.h b/include/asm-ppc64/abs_addr.h index 84c24d4cdb7..dc3fc3fefef 100644 --- a/include/asm-ppc64/abs_addr.h +++ b/include/asm-ppc64/abs_addr.h @@ -63,4 +63,11 @@ static inline unsigned long phys_to_abs(unsigned long pa) #define virt_to_abs(va) phys_to_abs(__pa(va)) #define abs_to_virt(aa) __va(aa) +/* + * Converts Virtual Address to Real Address for + * Legacy iSeries Hypervisor calls + */ +#define iseries_hv_addr(virtaddr) \ + (0x8000000000000000 | virt_to_abs(virtaddr)) + #endif /* _ABS_ADDR_H */ diff --git a/include/asm-ppc64/iSeries/iSeries_pci.h b/include/asm-ppc64/iSeries/iSeries_pci.h deleted file mode 100644 index a4d88b49fd9..00000000000 --- a/include/asm-ppc64/iSeries/iSeries_pci.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef _ISERIES_64_PCI_H -#define _ISERIES_64_PCI_H - -/* - * File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001. - * - * Define some useful macros for the iSeries pci routines. - * Copyright (C) 2001 Allan H Trautman, IBM Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the: - * Free Software Foundation, Inc., - * 59 Temple Place, Suite 330, - * Boston, MA 02111-1307 USA - * - * Change Activity: - * Created Feb 20, 2001 - * Added device reset, March 22, 2001 - * Ported to ppc64, May 25, 2001 - * End Change Activity - */ - -#include -#include -#include - -struct pci_dev; /* For Forward Reference */ - -/* - * Gets iSeries Bus, SubBus, DevFn using device_node structure - */ - -#define ISERIES_BUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.busNumber -#define ISERIES_SUBBUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.subBusNumber -#define ISERIES_DEVNODE(PciDev) ((struct device_node *)PciDev->sysdata) - -#define EADsMaxAgents 7 - -/* - * Decodes Linux DevFn to iSeries DevFn, bridge device, or function. - * For Linux, see PCI_SLOT and PCI_FUNC in include/linux/pci.h - */ - -#define ISERIES_PCI_AGENTID(idsel, func) \ - (((idsel & 0x0F) << 4) | (func & 0x07)) -#define ISERIES_ENCODE_DEVICE(agentid) \ - ((0x10) | ((agentid & 0x20) >> 2) | (agentid & 0x07)) - -#define ISERIES_GET_DEVICE_FROM_SUBBUS(subbus) ((subbus >> 5) & 0x7) -#define ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus) ((subbus >> 2) & 0x7) - -/* - * Converts Virtual Address to Real Address for Hypervisor calls - */ -#define ISERIES_HV_ADDR(virtaddr) \ - (0x8000000000000000 | virt_to_abs(virtaddr)) - -extern void iSeries_Device_Information(struct pci_dev*, int); - -#endif /* _ISERIES_64_PCI_H */ diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h index 56863df1823..01bffca61f8 100644 --- a/include/asm-ppc64/pci-bridge.h +++ b/include/asm-ppc64/pci-bridge.h @@ -2,6 +2,7 @@ #ifndef _ASM_PCI_BRIDGE_H #define _ASM_PCI_BRIDGE_H +#include #include #include diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h index cf0284e081e..e8d0d2ab4c0 100644 --- a/include/asm-ppc64/prom.h +++ b/include/asm-ppc64/prom.h @@ -14,6 +14,7 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. */ +#include #include #include -- cgit v1.2.3-70-g09d2 From f2783c15007468c14972e2617db51e9affc7fad9 Mon Sep 17 00:00:00 2001 From: Paul Mackerras Date: Thu, 20 Oct 2005 09:23:26 +1000 Subject: powerpc: Merge time.c and asm/time.h. We now use the merged time.c for both 32-bit and 64-bit compilation with ARCH=powerpc, and for ARCH=ppc64, but not for ARCH=ppc32. This removes setup_default_decr (folds its function into time_init) and moves wakeup_decrementer into time.c. This also makes an asm-powerpc/rtc.h. Signed-off-by: Paul Mackerras --- arch/powerpc/kernel/Makefile | 4 +- arch/powerpc/kernel/misc_32.S | 27 + arch/powerpc/kernel/ppc_ksyms.c | 1 - arch/powerpc/kernel/setup_64.c | 9 - arch/powerpc/kernel/time.c | 978 ++++++++++++++++++++++++++++++ arch/powerpc/platforms/powermac/cpufreq.c | 9 - arch/powerpc/platforms/powermac/time.c | 28 +- arch/ppc/kernel/Makefile | 2 +- arch/ppc/kernel/time.c | 9 + arch/ppc64/kernel/Makefile | 2 +- arch/ppc64/kernel/pmac_time.c | 2 - arch/ppc64/kernel/setup.c | 9 - arch/ppc64/kernel/time.c | 879 --------------------------- drivers/macintosh/via-pmu.c | 11 - include/asm-powerpc/irq.h | 2 + include/asm-powerpc/rtc.h | 80 +++ include/asm-powerpc/time.h | 212 +++++++ include/asm-ppc64/time.h | 124 ---- 18 files changed, 1330 insertions(+), 1058 deletions(-) create mode 100644 arch/powerpc/kernel/time.c delete mode 100644 arch/ppc64/kernel/time.c create mode 100644 include/asm-powerpc/rtc.h create mode 100644 include/asm-powerpc/time.h delete mode 100644 include/asm-ppc64/time.h (limited to 'drivers') diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index 5c5d2b5f3ca..b347ac32025 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -29,7 +29,7 @@ extra-$(CONFIG_PPC64) += entry_64.o extra-$(CONFIG_PPC_FPU) += fpu.o extra-y += vmlinux.lds -obj-y += process.o init_task.o \ +obj-y += process.o init_task.o time.o \ prom.o systbl.o traps.o obj-$(CONFIG_PPC32) += entry_32.o idle_6xx.o setup_32.o misc_32.o obj-$(CONFIG_PPC64) += setup_64.o misc_64.o @@ -44,7 +44,7 @@ endif else # stuff used from here for ARCH=ppc or ARCH=ppc64 -obj-$(CONFIG_PPC64) += traps.o process.o init_task.o +obj-$(CONFIG_PPC64) += traps.o process.o init_task.o time.o fpux-$(CONFIG_PPC32) += fpu.o extra-$(CONFIG_PPC_FPU) += $(fpux-y) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 0b0e908b506..303229b090b 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -35,6 +35,33 @@ _GLOBAL(__delay) 1: bdnz 1b blr +/* + * This returns the high 64 bits of the product of two 64-bit numbers. + */ +_GLOBAL(mulhdu) + cmpwi r6,0 + cmpwi cr1,r3,0 + mr r10,r4 + mulhwu r4,r4,r5 + beq 1f + mulhwu r0,r10,r6 + mullw r7,r10,r5 + addc r7,r0,r7 + addze r4,r4 +1: beqlr cr1 /* all done if high part of A is 0 */ + mr r10,r3 + mullw r9,r3,r5 + mulhwu r3,r3,r5 + beq 2f + mullw r0,r10,r6 + mulhwu r8,r10,r6 + addc r7,r0,r7 + adde r4,r4,r8 + addze r3,r3 +2: addc r4,r4,r9 + addze r3,r3 + blr + /* * Returns (address we're running at) - (address we were linked at) * for use before the text and data are mapped to KERNELBASE. diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c index 010554e5fe4..40c9e67e1b2 100644 --- a/arch/powerpc/kernel/ppc_ksyms.c +++ b/arch/powerpc/kernel/ppc_ksyms.c @@ -260,7 +260,6 @@ EXPORT_SYMBOL(__res); #ifdef CONFIG_PPC32 EXPORT_SYMBOL(next_mmu_context); EXPORT_SYMBOL(set_context); -EXPORT_SYMBOL(disarm_decr); #endif #ifdef CONFIG_PPC_STD_MMU_32 diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index 4fcf67575cb..6f29614c358 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c @@ -1083,15 +1083,6 @@ void ppc64_terminate_msg(unsigned int src, const char *msg) printk("[terminate]%04x %s\n", src, msg); } -/* This should only be called on processor 0 during calibrate decr */ -void __init setup_default_decr(void) -{ - struct paca_struct *lpaca = get_paca(); - - lpaca->default_decr = tb_ticks_per_jiffy; - lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy; -} - #ifndef CONFIG_PPC_ISERIES /* * This function can be used by platforms to "find" legacy serial ports. diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c new file mode 100644 index 00000000000..d1608473075 --- /dev/null +++ b/arch/powerpc/kernel/time.c @@ -0,0 +1,978 @@ +/* + * Common time routines among all ppc machines. + * + * Written by Cort Dougan (cort@cs.nmt.edu) to merge + * Paul Mackerras' version and mine for PReP and Pmac. + * MPC8xx/MBX changes by Dan Malek (dmalek@jlc.net). + * Converted for 64-bit by Mike Corrigan (mikejc@us.ibm.com) + * + * First round of bugfixes by Gabriel Paubert (paubert@iram.es) + * to make clock more stable (2.4.0-test5). The only thing + * that this code assumes is that the timebases have been synchronized + * by firmware on SMP and are never stopped (never do sleep + * on SMP then, nap and doze are OK). + * + * Speeded up do_gettimeofday by getting rid of references to + * xtime (which required locks for consistency). (mikejc@us.ibm.com) + * + * TODO (not necessarily in this file): + * - improve precision and reproducibility of timebase frequency + * measurement at boot time. (for iSeries, we calibrate the timebase + * against the Titan chip's clock.) + * - for astronomical applications: add a new function to get + * non ambiguous timestamps even around leap seconds. This needs + * a new timestamp format and a good name. + * + * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_PPC64 +#include +#include +#endif +#ifdef CONFIG_PPC_ISERIES +#include +#include +#endif + +u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES; + +EXPORT_SYMBOL(jiffies_64); + +/* keep track of when we need to update the rtc */ +time_t last_rtc_update; +extern int piranha_simulator; +#ifdef CONFIG_PPC_ISERIES +unsigned long iSeries_recal_titan = 0; +unsigned long iSeries_recal_tb = 0; +static unsigned long first_settimeofday = 1; +#endif + +/* The decrementer counts down by 128 every 128ns on a 601. */ +#define DECREMENTER_COUNT_601 (1000000000 / HZ) + +#define XSEC_PER_SEC (1024*1024) + +#ifdef CONFIG_PPC64 +#define SCALE_XSEC(xsec, max) (((xsec) * max) / XSEC_PER_SEC) +#else +/* compute ((xsec << 12) * max) >> 32 */ +#define SCALE_XSEC(xsec, max) mulhwu((xsec) << 12, max) +#endif + +unsigned long tb_ticks_per_jiffy; +unsigned long tb_ticks_per_usec = 100; /* sane default */ +EXPORT_SYMBOL(tb_ticks_per_usec); +unsigned long tb_ticks_per_sec; +u64 tb_to_xs; +unsigned tb_to_us; +unsigned long processor_freq; +DEFINE_SPINLOCK(rtc_lock); +EXPORT_SYMBOL_GPL(rtc_lock); + +u64 tb_to_ns_scale; +unsigned tb_to_ns_shift; + +struct gettimeofday_struct do_gtod; + +extern unsigned long wall_jiffies; + +extern struct timezone sys_tz; +static long timezone_offset; + +void ppc_adjtimex(void); + +static unsigned adjusting_time = 0; + +unsigned long ppc_proc_freq; +unsigned long ppc_tb_freq; + +#ifdef CONFIG_PPC32 /* XXX for now */ +#define boot_cpuid 0 +#endif + +static __inline__ void timer_check_rtc(void) +{ + /* + * update the rtc when needed, this should be performed on the + * right fraction of a second. Half or full second ? + * Full second works on mk48t59 clocks, others need testing. + * Note that this update is basically only used through + * the adjtimex system calls. Setting the HW clock in + * any other way is a /dev/rtc and userland business. + * This is still wrong by -0.5/+1.5 jiffies because of the + * timer interrupt resolution and possible delay, but here we + * hit a quantization limit which can only be solved by higher + * resolution timers and decoupling time management from timer + * interrupts. This is also wrong on the clocks + * which require being written at the half second boundary. + * We should have an rtc call that only sets the minutes and + * seconds like on Intel to avoid problems with non UTC clocks. + */ + if (ntp_synced() && + xtime.tv_sec - last_rtc_update >= 659 && + abs((xtime.tv_nsec/1000) - (1000000-1000000/HZ)) < 500000/HZ && + jiffies - wall_jiffies == 1) { + struct rtc_time tm; + to_tm(xtime.tv_sec + 1 + timezone_offset, &tm); + tm.tm_year -= 1900; + tm.tm_mon -= 1; + if (ppc_md.set_rtc_time(&tm) == 0) + last_rtc_update = xtime.tv_sec + 1; + else + /* Try again one minute later */ + last_rtc_update += 60; + } +} + +/* + * This version of gettimeofday has microsecond resolution. + */ +static inline void __do_gettimeofday(struct timeval *tv, u64 tb_val) +{ + unsigned long sec, usec; + u64 tb_ticks, xsec; + struct gettimeofday_vars *temp_varp; + u64 temp_tb_to_xs, temp_stamp_xsec; + + /* + * These calculations are faster (gets rid of divides) + * if done in units of 1/2^20 rather than microseconds. + * The conversion to microseconds at the end is done + * without a divide (and in fact, without a multiply) + */ + temp_varp = do_gtod.varp; + tb_ticks = tb_val - temp_varp->tb_orig_stamp; + temp_tb_to_xs = temp_varp->tb_to_xs; + temp_stamp_xsec = temp_varp->stamp_xsec; + xsec = temp_stamp_xsec + mulhdu(tb_ticks, temp_tb_to_xs); + sec = xsec / XSEC_PER_SEC; + usec = (unsigned long)xsec & (XSEC_PER_SEC - 1); + usec = SCALE_XSEC(usec, 1000000); + + tv->tv_sec = sec; + tv->tv_usec = usec; +} + +void do_gettimeofday(struct timeval *tv) +{ + __do_gettimeofday(tv, get_tb()); +} + +EXPORT_SYMBOL(do_gettimeofday); + +/* Synchronize xtime with do_gettimeofday */ + +static inline void timer_sync_xtime(unsigned long cur_tb) +{ +#ifdef CONFIG_PPC64 + /* why do we do this? */ + struct timeval my_tv; + + __do_gettimeofday(&my_tv, cur_tb); + + if (xtime.tv_sec <= my_tv.tv_sec) { + xtime.tv_sec = my_tv.tv_sec; + xtime.tv_nsec = my_tv.tv_usec * 1000; + } +#endif +} + +/* + * There are two copies of tb_to_xs and stamp_xsec so that no + * lock is needed to access and use these values in + * do_gettimeofday. We alternate the copies and as long as a + * reasonable time elapses between changes, there will never + * be inconsistent values. ntpd has a minimum of one minute + * between updates. + */ +static inline void update_gtod(u64 new_tb_stamp, u64 new_stamp_xsec, + unsigned int new_tb_to_xs) +{ + unsigned temp_idx; + struct gettimeofday_vars *temp_varp; + + temp_idx = (do_gtod.var_idx == 0); + temp_varp = &do_gtod.vars[temp_idx]; + + temp_varp->tb_to_xs = new_tb_to_xs; + temp_varp->tb_orig_stamp = new_tb_stamp; + temp_varp->stamp_xsec = new_stamp_xsec; + smp_mb(); + do_gtod.varp = temp_varp; + do_gtod.var_idx = temp_idx; + +#ifdef CONFIG_PPC64 + /* + * tb_update_count is used to allow the userspace gettimeofday code + * to assure itself that it sees a consistent view of the tb_to_xs and + * stamp_xsec variables. It reads the tb_update_count, then reads + * tb_to_xs and stamp_xsec and then reads tb_update_count again. If + * the two values of tb_update_count match and are even then the + * tb_to_xs and stamp_xsec values are consistent. If not, then it + * loops back and reads them again until this criteria is met. + */ + ++(systemcfg->tb_update_count); + smp_wmb(); + systemcfg->tb_orig_stamp = new_tb_stamp; + systemcfg->stamp_xsec = new_stamp_xsec; + systemcfg->tb_to_xs = new_tb_to_xs; + smp_wmb(); + ++(systemcfg->tb_update_count); +#endif +} + +/* + * When the timebase - tb_orig_stamp gets too big, we do a manipulation + * between tb_orig_stamp and stamp_xsec. The goal here is to keep the + * difference tb - tb_orig_stamp small enough to always fit inside a + * 32 bits number. This is a requirement of our fast 32 bits userland + * implementation in the vdso. If we "miss" a call to this function + * (interrupt latency, CPU locked in a spinlock, ...) and we end up + * with a too big difference, then the vdso will fallback to calling + * the syscall + */ +static __inline__ void timer_recalc_offset(u64 cur_tb) +{ + unsigned long offset; + u64 new_stamp_xsec; + + offset = cur_tb - do_gtod.varp->tb_orig_stamp; + if ((offset & 0x80000000u) == 0) + return; + new_stamp_xsec = do_gtod.varp->stamp_xsec + + mulhdu(offset, do_gtod.varp->tb_to_xs); + update_gtod(cur_tb, new_stamp_xsec, do_gtod.varp->tb_to_xs); +} + +#ifdef CONFIG_SMP +unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + + if (in_lock_functions(pc)) + return regs->link; + + return pc; +} +EXPORT_SYMBOL(profile_pc); +#endif + +#ifdef CONFIG_PPC_ISERIES + +/* + * This function recalibrates the timebase based on the 49-bit time-of-day + * value in the Titan chip. The Titan is much more accurate than the value + * returned by the service processor for the timebase frequency. + */ + +static void iSeries_tb_recal(void) +{ + struct div_result divres; + unsigned long titan, tb; + tb = get_tb(); + titan = HvCallXm_loadTod(); + if ( iSeries_recal_titan ) { + unsigned long tb_ticks = tb - iSeries_recal_tb; + unsigned long titan_usec = (titan - iSeries_recal_titan) >> 12; + unsigned long new_tb_ticks_per_sec = (tb_ticks * USEC_PER_SEC)/titan_usec; + unsigned long new_tb_ticks_per_jiffy = (new_tb_ticks_per_sec+(HZ/2))/HZ; + long tick_diff = new_tb_ticks_per_jiffy - tb_ticks_per_jiffy; + char sign = '+'; + /* make sure tb_ticks_per_sec and tb_ticks_per_jiffy are consistent */ + new_tb_ticks_per_sec = new_tb_ticks_per_jiffy * HZ; + + if ( tick_diff < 0 ) { + tick_diff = -tick_diff; + sign = '-'; + } + if ( tick_diff ) { + if ( tick_diff < tb_ticks_per_jiffy/25 ) { + printk( "Titan recalibrate: new tb_ticks_per_jiffy = %lu (%c%ld)\n", + new_tb_ticks_per_jiffy, sign, tick_diff ); + tb_ticks_per_jiffy = new_tb_ticks_per_jiffy; + tb_ticks_per_sec = new_tb_ticks_per_sec; + div128_by_32( XSEC_PER_SEC, 0, tb_ticks_per_sec, &divres ); + do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; + tb_to_xs = divres.result_low; + do_gtod.varp->tb_to_xs = tb_to_xs; + systemcfg->tb_ticks_per_sec = tb_ticks_per_sec; + systemcfg->tb_to_xs = tb_to_xs; + } + else { + printk( "Titan recalibrate: FAILED (difference > 4 percent)\n" + " new tb_ticks_per_jiffy = %lu\n" + " old tb_ticks_per_jiffy = %lu\n", + new_tb_ticks_per_jiffy, tb_ticks_per_jiffy ); + } + } + } + iSeries_recal_titan = titan; + iSeries_recal_tb = tb; +} +#endif + +/* + * For iSeries shared processors, we have to let the hypervisor + * set the hardware decrementer. We set a virtual decrementer + * in the lppaca and call the hypervisor if the virtual + * decrementer is less than the current value in the hardware + * decrementer. (almost always the new decrementer value will + * be greater than the current hardware decementer so the hypervisor + * call will not be needed) + */ + +u64 tb_last_stamp __cacheline_aligned_in_smp; + +/* + * Note that on ppc32 this only stores the bottom 32 bits of + * the timebase value, but that's enough to tell when a jiffy + * has passed. + */ +DEFINE_PER_CPU(unsigned long, last_jiffy); + +/* + * timer_interrupt - gets called when the decrementer overflows, + * with interrupts disabled. + */ +void timer_interrupt(struct pt_regs * regs) +{ + int next_dec; + int cpu = smp_processor_id(); + unsigned long ticks; + +#ifdef CONFIG_PPC32 + if (atomic_read(&ppc_n_lost_interrupts) != 0) + do_IRQ(regs); +#endif + + irq_enter(); + + profile_tick(CPU_PROFILING, regs); + +#ifdef CONFIG_PPC_ISERIES + get_paca()->lppaca.int_dword.fields.decr_int = 0; +#endif + + while ((ticks = tb_ticks_since(per_cpu(last_jiffy, cpu))) + >= tb_ticks_per_jiffy) { + /* Update last_jiffy */ + per_cpu(last_jiffy, cpu) += tb_ticks_per_jiffy; + /* Handle RTCL overflow on 601 */ + if (__USE_RTC() && per_cpu(last_jiffy, cpu) >= 1000000000) + per_cpu(last_jiffy, cpu) -= 1000000000; + + /* + * We cannot disable the decrementer, so in the period + * between this cpu's being marked offline in cpu_online_map + * and calling stop-self, it is taking timer interrupts. + * Avoid calling into the scheduler rebalancing code if this + * is the case. + */ + if (!cpu_is_offline(cpu)) + update_process_times(user_mode(regs)); + + /* + * No need to check whether cpu is offline here; boot_cpuid + * should have been fixed up by now. + */ + if (cpu != boot_cpuid) + continue; + + write_seqlock(&xtime_lock); + tb_last_stamp += tb_ticks_per_jiffy; + timer_recalc_offset(tb_last_stamp); + do_timer(regs); + timer_sync_xtime(tb_last_stamp); + timer_check_rtc(); + write_sequnlock(&xtime_lock); + if (adjusting_time && (time_adjust == 0)) + ppc_adjtimex(); + } + + next_dec = tb_ticks_per_jiffy - ticks; + set_dec(next_dec); + +#ifdef CONFIG_PPC_ISERIES + if (hvlpevent_is_pending()) + process_hvlpevents(regs); +#endif + +#ifdef CONFIG_PPC64 + /* collect purr register values often, for accurate calculations */ + if (firmware_has_feature(FW_FEATURE_SPLPAR)) { + struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); + cu->current_tb = mfspr(SPRN_PURR); + } +#endif + + irq_exit(); +} + +void wakeup_decrementer(void) +{ + int i; + + set_dec(tb_ticks_per_jiffy); + /* + * We don't expect this to be called on a machine with a 601, + * so using get_tbl is fine. + */ + tb_last_stamp = get_tb(); + for_each_cpu(i) + per_cpu(last_jiffy, i) = tb_last_stamp; +} + +#ifdef CONFIG_SMPxxx +void __init smp_space_timers(unsigned int max_cpus) +{ + int i; + unsigned long offset = tb_ticks_per_jiffy / max_cpus; + unsigned long previous_tb = per_cpu(last_jiffy, boot_cpuid); + + for_each_cpu(i) { + if (i != boot_cpuid) { + previous_tb += offset; + per_cpu(last_jiffy, i) = previous_tb; + } + } +} +#endif + +/* + * Scheduler clock - returns current time in nanosec units. + * + * Note: mulhdu(a, b) (multiply high double unsigned) returns + * the high 64 bits of a * b, i.e. (a * b) >> 64, where a and b + * are 64-bit unsigned numbers. + */ +unsigned long long sched_clock(void) +{ + return mulhdu(get_tb(), tb_to_ns_scale) << tb_to_ns_shift; +} + +int do_settimeofday(struct timespec *tv) +{ + time_t wtm_sec, new_sec = tv->tv_sec; + long wtm_nsec, new_nsec = tv->tv_nsec; + unsigned long flags; + long int tb_delta; + u64 new_xsec; + + if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) + return -EINVAL; + + write_seqlock_irqsave(&xtime_lock, flags); + + /* + * Updating the RTC is not the job of this code. If the time is + * stepped under NTP, the RTC will be updated after STA_UNSYNC + * is cleared. Tools like clock/hwclock either copy the RTC + * to the system time, in which case there is no point in writing + * to the RTC again, or write to the RTC but then they don't call + * settimeofday to perform this operation. + */ +#ifdef CONFIG_PPC_ISERIES + if (first_settimeofday) { + iSeries_tb_recal(); + first_settimeofday = 0; + } +#endif + tb_delta = tb_ticks_since(tb_last_stamp); + tb_delta += (jiffies - wall_jiffies) * tb_ticks_per_jiffy; + + new_nsec -= 1000 * mulhwu(tb_to_us, tb_delta); + + wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - new_sec); + wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - new_nsec); + + set_normalized_timespec(&xtime, new_sec, new_nsec); + set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); + + /* In case of a large backwards jump in time with NTP, we want the + * clock to be updated as soon as the PLL is again in lock. + */ + last_rtc_update = new_sec - 658; + + ntp_clear(); + + new_xsec = (u64)new_nsec * XSEC_PER_SEC; + do_div(new_xsec, NSEC_PER_SEC); + new_xsec += (u64)new_sec * XSEC_PER_SEC; + update_gtod(tb_last_stamp, new_xsec, do_gtod.varp->tb_to_xs); + +#ifdef CONFIG_PPC64 + systemcfg->tz_minuteswest = sys_tz.tz_minuteswest; + systemcfg->tz_dsttime = sys_tz.tz_dsttime; +#endif + + write_sequnlock_irqrestore(&xtime_lock, flags); + clock_was_set(); + return 0; +} + +EXPORT_SYMBOL(do_settimeofday); + +#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_MAPLE) || defined(CONFIG_PPC_BPA) || defined(CONFIG_PPC_ISERIES) +void __init generic_calibrate_decr(void) +{ + struct device_node *cpu; + struct div_result divres; + unsigned int *fp; + int node_found; + + /* + * The cpu node should have a timebase-frequency property + * to tell us the rate at which the decrementer counts. + */ + cpu = of_find_node_by_type(NULL, "cpu"); + + ppc_tb_freq = DEFAULT_TB_FREQ; /* hardcoded default */ + node_found = 0; + if (cpu != 0) { + fp = (unsigned int *)get_property(cpu, "timebase-frequency", + NULL); + if (fp != 0) { + node_found = 1; + ppc_tb_freq = *fp; + } + } + if (!node_found) + printk(KERN_ERR "WARNING: Estimating decrementer frequency " + "(not found)\n"); + + ppc_proc_freq = DEFAULT_PROC_FREQ; + node_found = 0; + if (cpu != 0) { + fp = (unsigned int *)get_property(cpu, "clock-frequency", + NULL); + if (fp != 0) { + node_found = 1; + ppc_proc_freq = *fp; + } + } + if (!node_found) + printk(KERN_ERR "WARNING: Estimating processor frequency " + "(not found)\n"); + + of_node_put(cpu); + + printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", + ppc_tb_freq/1000000, ppc_tb_freq%1000000); + printk(KERN_INFO "time_init: processor frequency = %lu.%.6lu MHz\n", + ppc_proc_freq/1000000, ppc_proc_freq%1000000); + + tb_ticks_per_jiffy = ppc_tb_freq / HZ; + tb_ticks_per_sec = tb_ticks_per_jiffy * HZ; + tb_ticks_per_usec = ppc_tb_freq / 1000000; + tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000); + div128_by_32(1024*1024, 0, tb_ticks_per_sec, &divres); + tb_to_xs = divres.result_low; +} +#endif + +unsigned long get_boot_time(void) +{ + struct rtc_time tm; + + if (ppc_md.get_boot_time) + return ppc_md.get_boot_time(); + if (!ppc_md.get_rtc_time) + return 0; + ppc_md.get_rtc_time(&tm); + return mktime(tm.tm_year+1900, tm.tm_mon+1, tm.tm_mday, + tm.tm_hour, tm.tm_min, tm.tm_sec); +} + +/* This function is only called on the boot processor */ +void __init time_init(void) +{ + unsigned long flags; + unsigned long tm = 0; + struct div_result res; + u64 scale; + unsigned shift; + + if (ppc_md.time_init != NULL) + timezone_offset = ppc_md.time_init(); + + ppc_md.calibrate_decr(); + +#ifdef CONFIG_PPC64 + get_paca()->default_decr = tb_ticks_per_jiffy; +#endif + + /* + * Compute scale factor for sched_clock. + * The calibrate_decr() function has set tb_ticks_per_sec, + * which is the timebase frequency. + * We compute 1e9 * 2^64 / tb_ticks_per_sec and interpret + * the 128-bit result as a 64.64 fixed-point number. + * We then shift that number right until it is less than 1.0, + * giving us the scale factor and shift count to use in + * sched_clock(). + */ + div128_by_32(1000000000, 0, tb_ticks_per_sec, &res); + scale = res.result_low; + for (shift = 0; res.result_high != 0; ++shift) { + scale = (scale >> 1) | (res.result_high << 63); + res.result_high >>= 1; + } + tb_to_ns_scale = scale; + tb_to_ns_shift = shift; + +#ifdef CONFIG_PPC_ISERIES + if (!piranha_simulator) +#endif + tm = get_boot_time(); + + write_seqlock_irqsave(&xtime_lock, flags); + xtime.tv_sec = tm; + xtime.tv_nsec = 0; + tb_last_stamp = get_tb(); + do_gtod.varp = &do_gtod.vars[0]; + do_gtod.var_idx = 0; + do_gtod.varp->tb_orig_stamp = tb_last_stamp; + __get_cpu_var(last_jiffy) = tb_last_stamp; + do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC; + do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; + do_gtod.varp->tb_to_xs = tb_to_xs; + do_gtod.tb_to_us = tb_to_us; +#ifdef CONFIG_PPC64 + systemcfg->tb_orig_stamp = tb_last_stamp; + systemcfg->tb_update_count = 0; + systemcfg->tb_ticks_per_sec = tb_ticks_per_sec; + systemcfg->stamp_xsec = xtime.tv_sec * XSEC_PER_SEC; + systemcfg->tb_to_xs = tb_to_xs; +#endif + + time_freq = 0; + + /* If platform provided a timezone (pmac), we correct the time */ + if (timezone_offset) { + sys_tz.tz_minuteswest = -timezone_offset / 60; + sys_tz.tz_dsttime = 0; + xtime.tv_sec -= timezone_offset; + } + + last_rtc_update = xtime.tv_sec; + set_normalized_timespec(&wall_to_monotonic, + -xtime.tv_sec, -xtime.tv_nsec); + write_sequnlock_irqrestore(&xtime_lock, flags); + + /* Not exact, but the timer interrupt takes care of this */ + set_dec(tb_ticks_per_jiffy); +} + +/* + * After adjtimex is called, adjust the conversion of tb ticks + * to microseconds to keep do_gettimeofday synchronized + * with ntpd. + * + * Use the time_adjust, time_freq and time_offset computed by adjtimex to + * adjust the frequency. + */ + +/* #define DEBUG_PPC_ADJTIMEX 1 */ + +void ppc_adjtimex(void) +{ +#ifdef CONFIG_PPC64 + unsigned long den, new_tb_ticks_per_sec, tb_ticks, old_xsec, + new_tb_to_xs, new_xsec, new_stamp_xsec; + unsigned long tb_ticks_per_sec_delta; + long delta_freq, ltemp; + struct div_result divres; + unsigned long flags; + long singleshot_ppm = 0; + + /* + * Compute parts per million frequency adjustment to + * accomplish the time adjustment implied by time_offset to be + * applied over the elapsed time indicated by time_constant. + * Use SHIFT_USEC to get it into the same units as + * time_freq. + */ + if ( time_offset < 0 ) { + ltemp = -time_offset; + ltemp <<= SHIFT_USEC - SHIFT_UPDATE; + ltemp >>= SHIFT_KG + time_constant; + ltemp = -ltemp; + } else { + ltemp = time_offset; + ltemp <<= SHIFT_USEC - SHIFT_UPDATE; + ltemp >>= SHIFT_KG + time_constant; + } + + /* If there is a single shot time adjustment in progress */ + if ( time_adjust ) { +#ifdef DEBUG_PPC_ADJTIMEX + printk("ppc_adjtimex: "); + if ( adjusting_time == 0 ) + printk("starting "); + printk("single shot time_adjust = %ld\n", time_adjust); +#endif + + adjusting_time = 1; + + /* + * Compute parts per million frequency adjustment + * to match time_adjust + */ + singleshot_ppm = tickadj * HZ; + /* + * The adjustment should be tickadj*HZ to match the code in + * linux/kernel/timer.c, but experiments show that this is too + * large. 3/4 of tickadj*HZ seems about right + */ + singleshot_ppm -= singleshot_ppm / 4; + /* Use SHIFT_USEC to get it into the same units as time_freq */ + singleshot_ppm <<= SHIFT_USEC; + if ( time_adjust < 0 ) + singleshot_ppm = -singleshot_ppm; + } + else { +#ifdef DEBUG_PPC_ADJTIMEX + if ( adjusting_time ) + printk("ppc_adjtimex: ending single shot time_adjust\n"); +#endif + adjusting_time = 0; + } + + /* Add up all of the frequency adjustments */ + delta_freq = time_freq + ltemp + singleshot_ppm; + + /* + * Compute a new value for tb_ticks_per_sec based on + * the frequency adjustment + */ + den = 1000000 * (1 << (SHIFT_USEC - 8)); + if ( delta_freq < 0 ) { + tb_ticks_per_sec_delta = ( tb_ticks_per_sec * ( (-delta_freq) >> (SHIFT_USEC - 8))) / den; + new_tb_ticks_per_sec = tb_ticks_per_sec + tb_ticks_per_sec_delta; + } + else { + tb_ticks_per_sec_delta = ( tb_ticks_per_sec * ( delta_freq >> (SHIFT_USEC - 8))) / den; + new_tb_ticks_per_sec = tb_ticks_per_sec - tb_ticks_per_sec_delta; + } + +#ifdef DEBUG_PPC_ADJTIMEX + printk("ppc_adjtimex: ltemp = %ld, time_freq = %ld, singleshot_ppm = %ld\n", ltemp, time_freq, singleshot_ppm); + printk("ppc_adjtimex: tb_ticks_per_sec - base = %ld new = %ld\n", tb_ticks_per_sec, new_tb_ticks_per_sec); +#endif + + /* + * Compute a new value of tb_to_xs (used to convert tb to + * microseconds) and a new value of stamp_xsec which is the + * time (in 1/2^20 second units) corresponding to + * tb_orig_stamp. This new value of stamp_xsec compensates + * for the change in frequency (implied by the new tb_to_xs) + * which guarantees that the current time remains the same. + */ + write_seqlock_irqsave( &xtime_lock, flags ); + tb_ticks = get_tb() - do_gtod.varp->tb_orig_stamp; + div128_by_32(1024*1024, 0, new_tb_ticks_per_sec, &divres); + new_tb_to_xs = divres.result_low; + new_xsec = mulhdu(tb_ticks, new_tb_to_xs); + + old_xsec = mulhdu(tb_ticks, do_gtod.varp->tb_to_xs); + new_stamp_xsec = do_gtod.varp->stamp_xsec + old_xsec - new_xsec; + + update_gtod(do_gtod.varp->tb_orig_stamp, new_stamp_xsec, new_tb_to_xs); + + write_sequnlock_irqrestore( &xtime_lock, flags ); +#endif /* CONFIG_PPC64 */ +} + + +#define FEBRUARY 2 +#define STARTOFTIME 1970 +#define SECDAY 86400L +#define SECYR (SECDAY * 365) +#define leapyear(year) ((year) % 4 == 0 && \ + ((year) % 100 != 0 || (year) % 400 == 0)) +#define days_in_year(a) (leapyear(a) ? 366 : 365) +#define days_in_month(a) (month_days[(a) - 1]) + +static int month_days[12] = { + 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +/* + * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) + */ +void GregorianDay(struct rtc_time * tm) +{ + int leapsToDate; + int lastYear; + int day; + int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }; + + lastYear = tm->tm_year - 1; + + /* + * Number of leap corrections to apply up to end of last year + */ + leapsToDate = lastYear / 4 - lastYear / 100 + lastYear / 400; + + /* + * This year is a leap year if it is divisible by 4 except when it is + * divisible by 100 unless it is divisible by 400 + * + * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 was + */ + day = tm->tm_mon > 2 && leapyear(tm->tm_year); + + day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + + tm->tm_mday; + + tm->tm_wday = day % 7; +} + +void to_tm(int tim, struct rtc_time * tm) +{ + register int i; + register long hms, day; + + day = tim / SECDAY; + hms = tim % SECDAY; + + /* Hours, minutes, seconds are easy */ + tm->tm_hour = hms / 3600; + tm->tm_min = (hms % 3600) / 60; + tm->tm_sec = (hms % 3600) % 60; + + /* Number of years in days */ + for (i = STARTOFTIME; day >= days_in_year(i); i++) + day -= days_in_year(i); + tm->tm_year = i; + + /* Number of months in days left */ + if (leapyear(tm->tm_year)) + days_in_month(FEBRUARY) = 29; + for (i = 1; day >= days_in_month(i); i++) + day -= days_in_month(i); + days_in_month(FEBRUARY) = 28; + tm->tm_mon = i; + + /* Days are what is left over (+1) from all that. */ + tm->tm_mday = day + 1; + + /* + * Determine the day of week + */ + GregorianDay(tm); +} + +/* Auxiliary function to compute scaling factors */ +/* Actually the choice of a timebase running at 1/4 the of the bus + * frequency giving resolution of a few tens of nanoseconds is quite nice. + * It makes this computation very precise (27-28 bits typically) which + * is optimistic considering the stability of most processor clock + * oscillators and the precision with which the timebase frequency + * is measured but does not harm. + */ +unsigned mulhwu_scale_factor(unsigned inscale, unsigned outscale) +{ + unsigned mlt=0, tmp, err; + /* No concern for performance, it's done once: use a stupid + * but safe and compact method to find the multiplier. + */ + + for (tmp = 1U<<31; tmp != 0; tmp >>= 1) { + if (mulhwu(inscale, mlt|tmp) < outscale) + mlt |= tmp; + } + + /* We might still be off by 1 for the best approximation. + * A side effect of this is that if outscale is too large + * the returned value will be zero. + * Many corner cases have been checked and seem to work, + * some might have been forgotten in the test however. + */ + + err = inscale * (mlt+1); + if (err <= inscale/2) + mlt++; + return mlt; +} + +/* + * Divide a 128-bit dividend by a 32-bit divisor, leaving a 128 bit + * result. + */ +void div128_by_32(u64 dividend_high, u64 dividend_low, + unsigned divisor, struct div_result *dr) +{ + unsigned long a, b, c, d; + unsigned long w, x, y, z; + u64 ra, rb, rc; + + a = dividend_high >> 32; + b = dividend_high & 0xffffffff; + c = dividend_low >> 32; + d = dividend_low & 0xffffffff; + + w = a / divisor; + ra = ((u64)(a - (w * divisor)) << 32) + b; + +#ifdef CONFIG_PPC64 + x = ra / divisor; + rb = ((ra - (x * divisor)) << 32) + c; + + y = rb / divisor; + rc = ((rb - (y * divisor)) << 32) + d; + + z = rc / divisor; +#else + /* for 32-bit, use do_div from div64.h */ + rb = ((u64) do_div(ra, divisor) << 32) + c; + x = ra; + + rc = ((u64) do_div(rb, divisor) << 32) + d; + y = rb; + + do_div(rc, divisor); + z = rc; +#endif + + dr->result_high = ((u64)w << 32) + x; + dr->result_low = ((u64)y << 32) + z; + +} + diff --git a/arch/powerpc/platforms/powermac/cpufreq.c b/arch/powerpc/platforms/powermac/cpufreq.c index bcd9224f3f9..c47f8b69725 100644 --- a/arch/powerpc/platforms/powermac/cpufreq.c +++ b/arch/powerpc/platforms/powermac/cpufreq.c @@ -110,15 +110,6 @@ static inline void local_delay(unsigned long ms) msleep(ms); } -static inline void wakeup_decrementer(void) -{ - set_dec(tb_ticks_per_jiffy); - /* No currently-supported powerbook has a 601, - * so use get_tbl, not native - */ - last_jiffy_stamp(0) = tb_last_stamp = get_tbl(); -} - #ifdef DEBUG_FREQ static inline void debug_calc_bogomips(void) { diff --git a/arch/powerpc/platforms/powermac/time.c b/arch/powerpc/platforms/powermac/time.c index 3ee6d8aa14c..eb9969b52f9 100644 --- a/arch/powerpc/platforms/powermac/time.c +++ b/arch/powerpc/platforms/powermac/time.c @@ -6,6 +6,8 @@ * * Paul Mackerras August 1996. * Copyright (C) 1996 Paul Mackerras. + * Copyright (C) 2003-2005 Benjamin Herrenschmidt. + * */ #include #include @@ -19,7 +21,9 @@ #include #include #include +#include #include +#include #include #include @@ -30,6 +34,14 @@ #include #include +#undef DEBUG + +#ifdef DEBUG +#define DBG(x...) printk(x) +#else +#define DBG(x...) +#endif + /* Apparently the RTC stores seconds since 1 Jan 1904 */ #define RTC_OFFSET 2082844800 @@ -54,10 +66,7 @@ /* Bits in IFR and IER */ #define T1_INT 0x40 /* Timer 1 interrupt */ -extern struct timezone sys_tz; - -long __init -pmac_time_init(void) +long __init pmac_time_init(void) { #ifdef CONFIG_NVRAM s32 delta = 0; @@ -210,7 +219,7 @@ via_calibrate_decr(void) tb_ticks_per_jiffy = (dstart - dend) / ((6 * HZ)/100); tb_to_us = mulhwu_scale_factor(dstart - dend, 60000); - printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %u (%u ticks)\n", + printk(KERN_INFO "via_calibrate_decr: ticks per jiffy = %lu (%u ticks)\n", tb_ticks_per_jiffy, dstart - dend); iounmap(via); @@ -228,6 +237,7 @@ time_sleep_notify(struct pmu_sleep_notifier *self, int when) static unsigned long time_diff; unsigned long flags; unsigned long seq; + struct timespec tv; switch (when) { case PBOOK_SLEEP_NOW: @@ -237,11 +247,9 @@ time_sleep_notify(struct pmu_sleep_notifier *self, int when) } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); break; case PBOOK_WAKE: - write_seqlock_irqsave(&xtime_lock, flags); - xtime.tv_sec = pmac_get_rtc_time() + time_diff; - xtime.tv_nsec = 0; - last_rtc_update = xtime.tv_sec; - write_sequnlock_irqrestore(&xtime_lock, flags); + tv.tv_sec = pmac_get_boot_time() + time_diff; + tv.tv_nsec = 0; + do_settimeofday(&tv); break; } return PBOOK_SLEEP_OK; diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index 5a742c7b050..ccbc442c9ed 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile @@ -37,7 +37,7 @@ endif # These are here while we do the architecture merge else -obj-y := irq.o idle.o time.o \ +obj-y := irq.o idle.o \ align.o perfmon.o obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o obj-$(CONFIG_SOFTWARE_SUSPEND) += swsusp.o diff --git a/arch/ppc/kernel/time.c b/arch/ppc/kernel/time.c index 22d7fd1e0ae..76f44ce4772 100644 --- a/arch/ppc/kernel/time.c +++ b/arch/ppc/kernel/time.c @@ -121,6 +121,15 @@ unsigned long profile_pc(struct pt_regs *regs) EXPORT_SYMBOL(profile_pc); #endif +void wakeup_decrementer(void) +{ + set_dec(tb_ticks_per_jiffy); + /* No currently-supported powerbook has a 601, + * so use get_tbl, not native + */ + last_jiffy_stamp(0) = tb_last_stamp = get_tbl(); +} + /* * timer_interrupt - gets called when the decrementer overflows, * with interrupts disabled. diff --git a/arch/ppc64/kernel/Makefile b/arch/ppc64/kernel/Makefile index 8c9012f0ce6..18f477fa1df 100644 --- a/arch/ppc64/kernel/Makefile +++ b/arch/ppc64/kernel/Makefile @@ -12,7 +12,7 @@ obj-y := setup.o entry.o misc.o prom.o endif obj-y += irq.o idle.o dma.o \ - time.o signal.o \ + signal.o \ align.o bitops.o pacaData.o \ udbg.o ioctl32.o \ rtc.o \ diff --git a/arch/ppc64/kernel/pmac_time.c b/arch/ppc64/kernel/pmac_time.c index c89bfefbbec..56f33511591 100644 --- a/arch/ppc64/kernel/pmac_time.c +++ b/arch/ppc64/kernel/pmac_time.c @@ -180,7 +180,5 @@ void __init pmac_calibrate_decr(void) if (fp == 0) panic("can't get cpu processor frequency"); ppc_proc_freq = *fp; - - setup_default_decr(); } diff --git a/arch/ppc64/kernel/setup.c b/arch/ppc64/kernel/setup.c index 776b55b45e1..3e6c1547b71 100644 --- a/arch/ppc64/kernel/setup.c +++ b/arch/ppc64/kernel/setup.c @@ -1083,15 +1083,6 @@ void ppc64_terminate_msg(unsigned int src, const char *msg) printk("[terminate]%04x %s\n", src, msg); } -/* This should only be called on processor 0 during calibrate decr */ -void __init setup_default_decr(void) -{ - struct paca_struct *lpaca = get_paca(); - - lpaca->default_decr = tb_ticks_per_jiffy; - lpaca->next_jiffy_update_tb = get_tb() + tb_ticks_per_jiffy; -} - #ifndef CONFIG_PPC_ISERIES /* * This function can be used by platforms to "find" legacy serial ports. diff --git a/arch/ppc64/kernel/time.c b/arch/ppc64/kernel/time.c deleted file mode 100644 index 7f63755eddf..00000000000 --- a/arch/ppc64/kernel/time.c +++ /dev/null @@ -1,879 +0,0 @@ -/* - * - * Common time routines among all ppc machines. - * - * Written by Cort Dougan (cort@cs.nmt.edu) to merge - * Paul Mackerras' version and mine for PReP and Pmac. - * MPC8xx/MBX changes by Dan Malek (dmalek@jlc.net). - * Converted for 64-bit by Mike Corrigan (mikejc@us.ibm.com) - * - * First round of bugfixes by Gabriel Paubert (paubert@iram.es) - * to make clock more stable (2.4.0-test5). The only thing - * that this code assumes is that the timebases have been synchronized - * by firmware on SMP and are never stopped (never do sleep - * on SMP then, nap and doze are OK). - * - * Speeded up do_gettimeofday by getting rid of references to - * xtime (which required locks for consistency). (mikejc@us.ibm.com) - * - * TODO (not necessarily in this file): - * - improve precision and reproducibility of timebase frequency - * measurement at boot time. (for iSeries, we calibrate the timebase - * against the Titan chip's clock.) - * - for astronomical applications: add a new function to get - * non ambiguous timestamps even around leap seconds. This needs - * a new timestamp format and a good name. - * - * 1997-09-10 Updated NTP code according to technical memorandum Jan '96 - * "A Kernel Model for Precision Timekeeping" by Dave Mills - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#ifdef CONFIG_PPC_ISERIES -#include -#include -#endif -#include -#include -#include -#include -#include -#include -#include - -u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES; - -EXPORT_SYMBOL(jiffies_64); - -/* keep track of when we need to update the rtc */ -time_t last_rtc_update; -extern int piranha_simulator; -#ifdef CONFIG_PPC_ISERIES -unsigned long iSeries_recal_titan = 0; -unsigned long iSeries_recal_tb = 0; -static unsigned long first_settimeofday = 1; -#endif - -#define XSEC_PER_SEC (1024*1024) - -unsigned long tb_ticks_per_jiffy; -unsigned long tb_ticks_per_usec = 100; /* sane default */ -EXPORT_SYMBOL(tb_ticks_per_usec); -unsigned long tb_ticks_per_sec; -unsigned long tb_to_xs; -unsigned tb_to_us; -unsigned long processor_freq; -DEFINE_SPINLOCK(rtc_lock); -EXPORT_SYMBOL_GPL(rtc_lock); - -unsigned long tb_to_ns_scale; -unsigned long tb_to_ns_shift; - -struct gettimeofday_struct do_gtod; - -extern unsigned long wall_jiffies; -extern int smp_tb_synchronized; - -extern struct timezone sys_tz; - -void ppc_adjtimex(void); - -static unsigned adjusting_time = 0; - -unsigned long ppc_proc_freq; -unsigned long ppc_tb_freq; - -static __inline__ void timer_check_rtc(void) -{ - /* - * update the rtc when needed, this should be performed on the - * right fraction of a second. Half or full second ? - * Full second works on mk48t59 clocks, others need testing. - * Note that this update is basically only used through - * the adjtimex system calls. Setting the HW clock in - * any other way is a /dev/rtc and userland business. - * This is still wrong by -0.5/+1.5 jiffies because of the - * timer interrupt resolution and possible delay, but here we - * hit a quantization limit which can only be solved by higher - * resolution timers and decoupling time management from timer - * interrupts. This is also wrong on the clocks - * which require being written at the half second boundary. - * We should have an rtc call that only sets the minutes and - * seconds like on Intel to avoid problems with non UTC clocks. - */ - if (ntp_synced() && - xtime.tv_sec - last_rtc_update >= 659 && - abs((xtime.tv_nsec/1000) - (1000000-1000000/HZ)) < 500000/HZ && - jiffies - wall_jiffies == 1) { - struct rtc_time tm; - to_tm(xtime.tv_sec+1, &tm); - tm.tm_year -= 1900; - tm.tm_mon -= 1; - if (ppc_md.set_rtc_time(&tm) == 0) - last_rtc_update = xtime.tv_sec+1; - else - /* Try again one minute later */ - last_rtc_update += 60; - } -} - -/* - * This version of gettimeofday has microsecond resolution. - */ -static inline void __do_gettimeofday(struct timeval *tv, unsigned long tb_val) -{ - unsigned long sec, usec, tb_ticks; - unsigned long xsec, tb_xsec; - struct gettimeofday_vars * temp_varp; - unsigned long temp_tb_to_xs, temp_stamp_xsec; - - /* - * These calculations are faster (gets rid of divides) - * if done in units of 1/2^20 rather than microseconds. - * The conversion to microseconds at the end is done - * without a divide (and in fact, without a multiply) - */ - temp_varp = do_gtod.varp; - tb_ticks = tb_val - temp_varp->tb_orig_stamp; - temp_tb_to_xs = temp_varp->tb_to_xs; - temp_stamp_xsec = temp_varp->stamp_xsec; - tb_xsec = mulhdu( tb_ticks, temp_tb_to_xs ); - xsec = temp_stamp_xsec + tb_xsec; - sec = xsec / XSEC_PER_SEC; - xsec -= sec * XSEC_PER_SEC; - usec = (xsec * USEC_PER_SEC)/XSEC_PER_SEC; - - tv->tv_sec = sec; - tv->tv_usec = usec; -} - -void do_gettimeofday(struct timeval *tv) -{ - __do_gettimeofday(tv, get_tb()); -} - -EXPORT_SYMBOL(do_gettimeofday); - -/* Synchronize xtime with do_gettimeofday */ - -static inline void timer_sync_xtime(unsigned long cur_tb) -{ - struct timeval my_tv; - - __do_gettimeofday(&my_tv, cur_tb); - - if (xtime.tv_sec <= my_tv.tv_sec) { - xtime.tv_sec = my_tv.tv_sec; - xtime.tv_nsec = my_tv.tv_usec * 1000; - } -} - -/* - * When the timebase - tb_orig_stamp gets too big, we do a manipulation - * between tb_orig_stamp and stamp_xsec. The goal here is to keep the - * difference tb - tb_orig_stamp small enough to always fit inside a - * 32 bits number. This is a requirement of our fast 32 bits userland - * implementation in the vdso. If we "miss" a call to this function - * (interrupt latency, CPU locked in a spinlock, ...) and we end up - * with a too big difference, then the vdso will fallback to calling - * the syscall - */ -static __inline__ void timer_recalc_offset(unsigned long cur_tb) -{ - struct gettimeofday_vars * temp_varp; - unsigned temp_idx; - unsigned long offset, new_stamp_xsec, new_tb_orig_stamp; - - if (((cur_tb - do_gtod.varp->tb_orig_stamp) & 0x80000000u) == 0) - return; - - temp_idx = (do_gtod.var_idx == 0); - temp_varp = &do_gtod.vars[temp_idx]; - - new_tb_orig_stamp = cur_tb; - offset = new_tb_orig_stamp - do_gtod.varp->tb_orig_stamp; - new_stamp_xsec = do_gtod.varp->stamp_xsec + mulhdu(offset, do_gtod.varp->tb_to_xs); - - temp_varp->tb_to_xs = do_gtod.varp->tb_to_xs; - temp_varp->tb_orig_stamp = new_tb_orig_stamp; - temp_varp->stamp_xsec = new_stamp_xsec; - smp_mb(); - do_gtod.varp = temp_varp; - do_gtod.var_idx = temp_idx; - - ++(systemcfg->tb_update_count); - smp_wmb(); - systemcfg->tb_orig_stamp = new_tb_orig_stamp; - systemcfg->stamp_xsec = new_stamp_xsec; - smp_wmb(); - ++(systemcfg->tb_update_count); -} - -#ifdef CONFIG_SMP -unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - - if (in_lock_functions(pc)) - return regs->link; - - return pc; -} -EXPORT_SYMBOL(profile_pc); -#endif - -#ifdef CONFIG_PPC_ISERIES - -/* - * This function recalibrates the timebase based on the 49-bit time-of-day - * value in the Titan chip. The Titan is much more accurate than the value - * returned by the service processor for the timebase frequency. - */ - -static void iSeries_tb_recal(void) -{ - struct div_result divres; - unsigned long titan, tb; - tb = get_tb(); - titan = HvCallXm_loadTod(); - if ( iSeries_recal_titan ) { - unsigned long tb_ticks = tb - iSeries_recal_tb; - unsigned long titan_usec = (titan - iSeries_recal_titan) >> 12; - unsigned long new_tb_ticks_per_sec = (tb_ticks * USEC_PER_SEC)/titan_usec; - unsigned long new_tb_ticks_per_jiffy = (new_tb_ticks_per_sec+(HZ/2))/HZ; - long tick_diff = new_tb_ticks_per_jiffy - tb_ticks_per_jiffy; - char sign = '+'; - /* make sure tb_ticks_per_sec and tb_ticks_per_jiffy are consistent */ - new_tb_ticks_per_sec = new_tb_ticks_per_jiffy * HZ; - - if ( tick_diff < 0 ) { - tick_diff = -tick_diff; - sign = '-'; - } - if ( tick_diff ) { - if ( tick_diff < tb_ticks_per_jiffy/25 ) { - printk( "Titan recalibrate: new tb_ticks_per_jiffy = %lu (%c%ld)\n", - new_tb_ticks_per_jiffy, sign, tick_diff ); - tb_ticks_per_jiffy = new_tb_ticks_per_jiffy; - tb_ticks_per_sec = new_tb_ticks_per_sec; - div128_by_32( XSEC_PER_SEC, 0, tb_ticks_per_sec, &divres ); - do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; - tb_to_xs = divres.result_low; - do_gtod.varp->tb_to_xs = tb_to_xs; - systemcfg->tb_ticks_per_sec = tb_ticks_per_sec; - systemcfg->tb_to_xs = tb_to_xs; - } - else { - printk( "Titan recalibrate: FAILED (difference > 4 percent)\n" - " new tb_ticks_per_jiffy = %lu\n" - " old tb_ticks_per_jiffy = %lu\n", - new_tb_ticks_per_jiffy, tb_ticks_per_jiffy ); - } - } - } - iSeries_recal_titan = titan; - iSeries_recal_tb = tb; -} -#endif - -/* - * For iSeries shared processors, we have to let the hypervisor - * set the hardware decrementer. We set a virtual decrementer - * in the lppaca and call the hypervisor if the virtual - * decrementer is less than the current value in the hardware - * decrementer. (almost always the new decrementer value will - * be greater than the current hardware decementer so the hypervisor - * call will not be needed) - */ - -unsigned long tb_last_stamp __cacheline_aligned_in_smp; - -/* - * timer_interrupt - gets called when the decrementer overflows, - * with interrupts disabled. - */ -void timer_interrupt(struct pt_regs * regs) -{ - int next_dec; - unsigned long cur_tb; - struct paca_struct *lpaca = get_paca(); - unsigned long cpu = smp_processor_id(); - - irq_enter(); - - profile_tick(CPU_PROFILING, regs); - - lpaca->lppaca.int_dword.fields.decr_int = 0; - - while (lpaca->next_jiffy_update_tb <= (cur_tb = get_tb())) { - /* - * We cannot disable the decrementer, so in the period - * between this cpu's being marked offline in cpu_online_map - * and calling stop-self, it is taking timer interrupts. - * Avoid calling into the scheduler rebalancing code if this - * is the case. - */ - if (!cpu_is_offline(cpu)) - update_process_times(user_mode(regs)); - /* - * No need to check whether cpu is offline here; boot_cpuid - * should have been fixed up by now. - */ - if (cpu == boot_cpuid) { - write_seqlock(&xtime_lock); - tb_last_stamp = lpaca->next_jiffy_update_tb; - timer_recalc_offset(lpaca->next_jiffy_update_tb); - do_timer(regs); - timer_sync_xtime(lpaca->next_jiffy_update_tb); - timer_check_rtc(); - write_sequnlock(&xtime_lock); - if ( adjusting_time && (time_adjust == 0) ) - ppc_adjtimex(); - } - lpaca->next_jiffy_update_tb += tb_ticks_per_jiffy; - } - - next_dec = lpaca->next_jiffy_update_tb - cur_tb; - if (next_dec > lpaca->default_decr) - next_dec = lpaca->default_decr; - set_dec(next_dec); - -#ifdef CONFIG_PPC_ISERIES - if (hvlpevent_is_pending()) - process_hvlpevents(regs); -#endif - - /* collect purr register values often, for accurate calculations */ - if (firmware_has_feature(FW_FEATURE_SPLPAR)) { - struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); - cu->current_tb = mfspr(SPRN_PURR); - } - - irq_exit(); -} - -/* - * Scheduler clock - returns current time in nanosec units. - * - * Note: mulhdu(a, b) (multiply high double unsigned) returns - * the high 64 bits of a * b, i.e. (a * b) >> 64, where a and b - * are 64-bit unsigned numbers. - */ -unsigned long long sched_clock(void) -{ - return mulhdu(get_tb(), tb_to_ns_scale) << tb_to_ns_shift; -} - -int do_settimeofday(struct timespec *tv) -{ - time_t wtm_sec, new_sec = tv->tv_sec; - long wtm_nsec, new_nsec = tv->tv_nsec; - unsigned long flags; - unsigned long delta_xsec; - long int tb_delta; - unsigned long new_xsec; - - if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC) - return -EINVAL; - - write_seqlock_irqsave(&xtime_lock, flags); - /* Updating the RTC is not the job of this code. If the time is - * stepped under NTP, the RTC will be update after STA_UNSYNC - * is cleared. Tool like clock/hwclock either copy the RTC - * to the system time, in which case there is no point in writing - * to the RTC again, or write to the RTC but then they don't call - * settimeofday to perform this operation. - */ -#ifdef CONFIG_PPC_ISERIES - if ( first_settimeofday ) { - iSeries_tb_recal(); - first_settimeofday = 0; - } -#endif - tb_delta = tb_ticks_since(tb_last_stamp); - tb_delta += (jiffies - wall_jiffies) * tb_ticks_per_jiffy; - - new_nsec -= tb_delta / tb_ticks_per_usec / 1000; - - wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - new_sec); - wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - new_nsec); - - set_normalized_timespec(&xtime, new_sec, new_nsec); - set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec); - - /* In case of a large backwards jump in time with NTP, we want the - * clock to be updated as soon as the PLL is again in lock. - */ - last_rtc_update = new_sec - 658; - - ntp_clear(); - - delta_xsec = mulhdu( (tb_last_stamp-do_gtod.varp->tb_orig_stamp), - do_gtod.varp->tb_to_xs ); - - new_xsec = (new_nsec * XSEC_PER_SEC) / NSEC_PER_SEC; - new_xsec += new_sec * XSEC_PER_SEC; - if ( new_xsec > delta_xsec ) { - do_gtod.varp->stamp_xsec = new_xsec - delta_xsec; - systemcfg->stamp_xsec = new_xsec - delta_xsec; - } - else { - /* This is only for the case where the user is setting the time - * way back to a time such that the boot time would have been - * before 1970 ... eg. we booted ten days ago, and we are setting - * the time to Jan 5, 1970 */ - do_gtod.varp->stamp_xsec = new_xsec; - do_gtod.varp->tb_orig_stamp = tb_last_stamp; - systemcfg->stamp_xsec = new_xsec; - systemcfg->tb_orig_stamp = tb_last_stamp; - } - - systemcfg->tz_minuteswest = sys_tz.tz_minuteswest; - systemcfg->tz_dsttime = sys_tz.tz_dsttime; - - write_sequnlock_irqrestore(&xtime_lock, flags); - clock_was_set(); - return 0; -} - -EXPORT_SYMBOL(do_settimeofday); - -#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_MAPLE) || defined(CONFIG_PPC_BPA) || defined(CONFIG_PPC_ISERIES) -void __init generic_calibrate_decr(void) -{ - struct device_node *cpu; - struct div_result divres; - unsigned int *fp; - int node_found; - - /* - * The cpu node should have a timebase-frequency property - * to tell us the rate at which the decrementer counts. - */ - cpu = of_find_node_by_type(NULL, "cpu"); - - ppc_tb_freq = DEFAULT_TB_FREQ; /* hardcoded default */ - node_found = 0; - if (cpu != 0) { - fp = (unsigned int *)get_property(cpu, "timebase-frequency", - NULL); - if (fp != 0) { - node_found = 1; - ppc_tb_freq = *fp; - } - } - if (!node_found) - printk(KERN_ERR "WARNING: Estimating decrementer frequency " - "(not found)\n"); - - ppc_proc_freq = DEFAULT_PROC_FREQ; - node_found = 0; - if (cpu != 0) { - fp = (unsigned int *)get_property(cpu, "clock-frequency", - NULL); - if (fp != 0) { - node_found = 1; - ppc_proc_freq = *fp; - } - } - if (!node_found) - printk(KERN_ERR "WARNING: Estimating processor frequency " - "(not found)\n"); - - of_node_put(cpu); - - printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", - ppc_tb_freq/1000000, ppc_tb_freq%1000000); - printk(KERN_INFO "time_init: processor frequency = %lu.%.6lu MHz\n", - ppc_proc_freq/1000000, ppc_proc_freq%1000000); - - tb_ticks_per_jiffy = ppc_tb_freq / HZ; - tb_ticks_per_sec = tb_ticks_per_jiffy * HZ; - tb_ticks_per_usec = ppc_tb_freq / 1000000; - tb_to_us = mulhwu_scale_factor(ppc_tb_freq, 1000000); - div128_by_32(1024*1024, 0, tb_ticks_per_sec, &divres); - tb_to_xs = divres.result_low; - - setup_default_decr(); -} -#endif - -void __init time_init(void) -{ - /* This function is only called on the boot processor */ - unsigned long flags; - struct rtc_time tm; - struct div_result res; - unsigned long scale, shift; - - ppc_md.calibrate_decr(); - - /* - * Compute scale factor for sched_clock. - * The calibrate_decr() function has set tb_ticks_per_sec, - * which is the timebase frequency. - * We compute 1e9 * 2^64 / tb_ticks_per_sec and interpret - * the 128-bit result as a 64.64 fixed-point number. - * We then shift that number right until it is less than 1.0, - * giving us the scale factor and shift count to use in - * sched_clock(). - */ - div128_by_32(1000000000, 0, tb_ticks_per_sec, &res); - scale = res.result_low; - for (shift = 0; res.result_high != 0; ++shift) { - scale = (scale >> 1) | (res.result_high << 63); - res.result_high >>= 1; - } - tb_to_ns_scale = scale; - tb_to_ns_shift = shift; - -#ifdef CONFIG_PPC_ISERIES - if (!piranha_simulator) -#endif - ppc_md.get_boot_time(&tm); - - write_seqlock_irqsave(&xtime_lock, flags); - xtime.tv_sec = mktime(tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, - tm.tm_hour, tm.tm_min, tm.tm_sec); - tb_last_stamp = get_tb(); - do_gtod.varp = &do_gtod.vars[0]; - do_gtod.var_idx = 0; - do_gtod.varp->tb_orig_stamp = tb_last_stamp; - get_paca()->next_jiffy_update_tb = tb_last_stamp + tb_ticks_per_jiffy; - do_gtod.varp->stamp_xsec = xtime.tv_sec * XSEC_PER_SEC; - do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; - do_gtod.varp->tb_to_xs = tb_to_xs; - do_gtod.tb_to_us = tb_to_us; - systemcfg->tb_orig_stamp = tb_last_stamp; - systemcfg->tb_update_count = 0; - systemcfg->tb_ticks_per_sec = tb_ticks_per_sec; - systemcfg->stamp_xsec = xtime.tv_sec * XSEC_PER_SEC; - systemcfg->tb_to_xs = tb_to_xs; - - time_freq = 0; - - xtime.tv_nsec = 0; - last_rtc_update = xtime.tv_sec; - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); - write_sequnlock_irqrestore(&xtime_lock, flags); - - /* Not exact, but the timer interrupt takes care of this */ - set_dec(tb_ticks_per_jiffy); -} - -/* - * After adjtimex is called, adjust the conversion of tb ticks - * to microseconds to keep do_gettimeofday synchronized - * with ntpd. - * - * Use the time_adjust, time_freq and time_offset computed by adjtimex to - * adjust the frequency. - */ - -/* #define DEBUG_PPC_ADJTIMEX 1 */ - -void ppc_adjtimex(void) -{ - unsigned long den, new_tb_ticks_per_sec, tb_ticks, old_xsec, new_tb_to_xs, new_xsec, new_stamp_xsec; - unsigned long tb_ticks_per_sec_delta; - long delta_freq, ltemp; - struct div_result divres; - unsigned long flags; - struct gettimeofday_vars * temp_varp; - unsigned temp_idx; - long singleshot_ppm = 0; - - /* Compute parts per million frequency adjustment to accomplish the time adjustment - implied by time_offset to be applied over the elapsed time indicated by time_constant. - Use SHIFT_USEC to get it into the same units as time_freq. */ - if ( time_offset < 0 ) { - ltemp = -time_offset; - ltemp <<= SHIFT_USEC - SHIFT_UPDATE; - ltemp >>= SHIFT_KG + time_constant; - ltemp = -ltemp; - } - else { - ltemp = time_offset; - ltemp <<= SHIFT_USEC - SHIFT_UPDATE; - ltemp >>= SHIFT_KG + time_constant; - } - - /* If there is a single shot time adjustment in progress */ - if ( time_adjust ) { -#ifdef DEBUG_PPC_ADJTIMEX - printk("ppc_adjtimex: "); - if ( adjusting_time == 0 ) - printk("starting "); - printk("single shot time_adjust = %ld\n", time_adjust); -#endif - - adjusting_time = 1; - - /* Compute parts per million frequency adjustment to match time_adjust */ - singleshot_ppm = tickadj * HZ; - /* - * The adjustment should be tickadj*HZ to match the code in - * linux/kernel/timer.c, but experiments show that this is too - * large. 3/4 of tickadj*HZ seems about right - */ - singleshot_ppm -= singleshot_ppm / 4; - /* Use SHIFT_USEC to get it into the same units as time_freq */ - singleshot_ppm <<= SHIFT_USEC; - if ( time_adjust < 0 ) - singleshot_ppm = -singleshot_ppm; - } - else { -#ifdef DEBUG_PPC_ADJTIMEX - if ( adjusting_time ) - printk("ppc_adjtimex: ending single shot time_adjust\n"); -#endif - adjusting_time = 0; - } - - /* Add up all of the frequency adjustments */ - delta_freq = time_freq + ltemp + singleshot_ppm; - - /* Compute a new value for tb_ticks_per_sec based on the frequency adjustment */ - den = 1000000 * (1 << (SHIFT_USEC - 8)); - if ( delta_freq < 0 ) { - tb_ticks_per_sec_delta = ( tb_ticks_per_sec * ( (-delta_freq) >> (SHIFT_USEC - 8))) / den; - new_tb_ticks_per_sec = tb_ticks_per_sec + tb_ticks_per_sec_delta; - } - else { - tb_ticks_per_sec_delta = ( tb_ticks_per_sec * ( delta_freq >> (SHIFT_USEC - 8))) / den; - new_tb_ticks_per_sec = tb_ticks_per_sec - tb_ticks_per_sec_delta; - } - -#ifdef DEBUG_PPC_ADJTIMEX - printk("ppc_adjtimex: ltemp = %ld, time_freq = %ld, singleshot_ppm = %ld\n", ltemp, time_freq, singleshot_ppm); - printk("ppc_adjtimex: tb_ticks_per_sec - base = %ld new = %ld\n", tb_ticks_per_sec, new_tb_ticks_per_sec); -#endif - - /* Compute a new value of tb_to_xs (used to convert tb to microseconds and a new value of - stamp_xsec which is the time (in 1/2^20 second units) corresponding to tb_orig_stamp. This - new value of stamp_xsec compensates for the change in frequency (implied by the new tb_to_xs) - which guarantees that the current time remains the same */ - write_seqlock_irqsave( &xtime_lock, flags ); - tb_ticks = get_tb() - do_gtod.varp->tb_orig_stamp; - div128_by_32( 1024*1024, 0, new_tb_ticks_per_sec, &divres ); - new_tb_to_xs = divres.result_low; - new_xsec = mulhdu( tb_ticks, new_tb_to_xs ); - - old_xsec = mulhdu( tb_ticks, do_gtod.varp->tb_to_xs ); - new_stamp_xsec = do_gtod.varp->stamp_xsec + old_xsec - new_xsec; - - /* There are two copies of tb_to_xs and stamp_xsec so that no lock is needed to access and use these - values in do_gettimeofday. We alternate the copies and as long as a reasonable time elapses between - changes, there will never be inconsistent values. ntpd has a minimum of one minute between updates */ - - temp_idx = (do_gtod.var_idx == 0); - temp_varp = &do_gtod.vars[temp_idx]; - - temp_varp->tb_to_xs = new_tb_to_xs; - temp_varp->stamp_xsec = new_stamp_xsec; - temp_varp->tb_orig_stamp = do_gtod.varp->tb_orig_stamp; - smp_mb(); - do_gtod.varp = temp_varp; - do_gtod.var_idx = temp_idx; - - /* - * tb_update_count is used to allow the problem state gettimeofday code - * to assure itself that it sees a consistent view of the tb_to_xs and - * stamp_xsec variables. It reads the tb_update_count, then reads - * tb_to_xs and stamp_xsec and then reads tb_update_count again. If - * the two values of tb_update_count match and are even then the - * tb_to_xs and stamp_xsec values are consistent. If not, then it - * loops back and reads them again until this criteria is met. - */ - ++(systemcfg->tb_update_count); - smp_wmb(); - systemcfg->tb_to_xs = new_tb_to_xs; - systemcfg->stamp_xsec = new_stamp_xsec; - smp_wmb(); - ++(systemcfg->tb_update_count); - - write_sequnlock_irqrestore( &xtime_lock, flags ); - -} - - -#define TICK_SIZE tick -#define FEBRUARY 2 -#define STARTOFTIME 1970 -#define SECDAY 86400L -#define SECYR (SECDAY * 365) -#define leapyear(year) ((year) % 4 == 0) -#define days_in_year(a) (leapyear(a) ? 366 : 365) -#define days_in_month(a) (month_days[(a) - 1]) - -static int month_days[12] = { - 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 -}; - -/* - * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) - */ -void GregorianDay(struct rtc_time * tm) -{ - int leapsToDate; - int lastYear; - int day; - int MonthOffset[] = { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 }; - - lastYear=tm->tm_year-1; - - /* - * Number of leap corrections to apply up to end of last year - */ - leapsToDate = lastYear/4 - lastYear/100 + lastYear/400; - - /* - * This year is a leap year if it is divisible by 4 except when it is - * divisible by 100 unless it is divisible by 400 - * - * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be - */ - if((tm->tm_year%4==0) && - ((tm->tm_year%100!=0) || (tm->tm_year%400==0)) && - (tm->tm_mon>2)) - { - /* - * We are past Feb. 29 in a leap year - */ - day=1; - } - else - { - day=0; - } - - day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + - tm->tm_mday; - - tm->tm_wday=day%7; -} - -void to_tm(int tim, struct rtc_time * tm) -{ - register int i; - register long hms, day; - - day = tim / SECDAY; - hms = tim % SECDAY; - - /* Hours, minutes, seconds are easy */ - tm->tm_hour = hms / 3600; - tm->tm_min = (hms % 3600) / 60; - tm->tm_sec = (hms % 3600) % 60; - - /* Number of years in days */ - for (i = STARTOFTIME; day >= days_in_year(i); i++) - day -= days_in_year(i); - tm->tm_year = i; - - /* Number of months in days left */ - if (leapyear(tm->tm_year)) - days_in_month(FEBRUARY) = 29; - for (i = 1; day >= days_in_month(i); i++) - day -= days_in_month(i); - days_in_month(FEBRUARY) = 28; - tm->tm_mon = i; - - /* Days are what is left over (+1) from all that. */ - tm->tm_mday = day + 1; - - /* - * Determine the day of week - */ - GregorianDay(tm); -} - -/* Auxiliary function to compute scaling factors */ -/* Actually the choice of a timebase running at 1/4 the of the bus - * frequency giving resolution of a few tens of nanoseconds is quite nice. - * It makes this computation very precise (27-28 bits typically) which - * is optimistic considering the stability of most processor clock - * oscillators and the precision with which the timebase frequency - * is measured but does not harm. - */ -unsigned mulhwu_scale_factor(unsigned inscale, unsigned outscale) { - unsigned mlt=0, tmp, err; - /* No concern for performance, it's done once: use a stupid - * but safe and compact method to find the multiplier. - */ - - for (tmp = 1U<<31; tmp != 0; tmp >>= 1) { - if (mulhwu(inscale, mlt|tmp) < outscale) mlt|=tmp; - } - - /* We might still be off by 1 for the best approximation. - * A side effect of this is that if outscale is too large - * the returned value will be zero. - * Many corner cases have been checked and seem to work, - * some might have been forgotten in the test however. - */ - - err = inscale*(mlt+1); - if (err <= inscale/2) mlt++; - return mlt; - } - -/* - * Divide a 128-bit dividend by a 32-bit divisor, leaving a 128 bit - * result. - */ - -void div128_by_32( unsigned long dividend_high, unsigned long dividend_low, - unsigned divisor, struct div_result *dr ) -{ - unsigned long a,b,c,d, w,x,y,z, ra,rb,rc; - - a = dividend_high >> 32; - b = dividend_high & 0xffffffff; - c = dividend_low >> 32; - d = dividend_low & 0xffffffff; - - w = a/divisor; - ra = (a - (w * divisor)) << 32; - - x = (ra + b)/divisor; - rb = ((ra + b) - (x * divisor)) << 32; - - y = (rb + c)/divisor; - rc = ((rb + b) - (y * divisor)) << 32; - - z = (rc + d)/divisor; - - dr->result_high = (w << 32) + x; - dr->result_low = (y << 32) + z; - -} - diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c index 50346188452..91920a1140f 100644 --- a/drivers/macintosh/via-pmu.c +++ b/drivers/macintosh/via-pmu.c @@ -588,17 +588,6 @@ pmu_get_model(void) return pmu_kind; } -#ifndef CONFIG_PPC64 -static inline void wakeup_decrementer(void) -{ - set_dec(tb_ticks_per_jiffy); - /* No currently-supported powerbook has a 601, - * so use get_tbl, not native - */ - last_jiffy_stamp(0) = tb_last_stamp = get_tbl(); -} -#endif - static void pmu_set_server_mode(int server_mode) { struct adb_request req; diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 980393a16be..07c2b3fc4c6 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h @@ -496,5 +496,7 @@ extern int call_handle_IRQ_event(int irq, struct pt_regs *regs, #endif /* CONFIG_IRQSTACKS */ +extern void do_IRQ(struct pt_regs *regs); + #endif /* _ASM_IRQ_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-powerpc/rtc.h b/include/asm-powerpc/rtc.h new file mode 100644 index 00000000000..d38f2a077db --- /dev/null +++ b/include/asm-powerpc/rtc.h @@ -0,0 +1,80 @@ +/* + * Real-time clock definitions and interfaces + * + * Author: Tom Rini + * + * 2002 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Based on: + * include/asm-m68k/rtc.h + * + * Copyright Richard Zidlicky + * implementation details for genrtc/q40rtc driver + * + * And the old drivers/macintosh/rtc.c which was heavily based on: + * Linux/SPARC Real Time Clock Driver + * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu) + * + * With additional work by Paul Mackerras and Franz Sirl. + */ + +#ifndef __ASM_POWERPC_RTC_H__ +#define __ASM_POWERPC_RTC_H__ + +#ifdef __KERNEL__ + +#include + +#include +#include + +#define RTC_PIE 0x40 /* periodic interrupt enable */ +#define RTC_AIE 0x20 /* alarm interrupt enable */ +#define RTC_UIE 0x10 /* update-finished interrupt enable */ + +/* some dummy definitions */ +#define RTC_BATT_BAD 0x100 /* battery bad */ +#define RTC_SQWE 0x08 /* enable square-wave output */ +#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ +#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ +#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ + +static inline unsigned int get_rtc_time(struct rtc_time *time) +{ + if (ppc_md.get_rtc_time) + ppc_md.get_rtc_time(time); + return RTC_24H; +} + +/* Set the current date and time in the real time clock. */ +static inline int set_rtc_time(struct rtc_time *time) +{ + if (ppc_md.get_rtc_time) { + ppc_md.set_rtc_time(time); + return 0; + } + return -EINVAL; +} + +static inline unsigned int get_rtc_ss(void) +{ + struct rtc_time h; + + get_rtc_time(&h); + return h.tm_sec; +} + +static inline int get_rtc_pll(struct rtc_pll_info *pll) +{ + return -EINVAL; +} +static inline int set_rtc_pll(struct rtc_pll_info *pll) +{ + return -EINVAL; +} + +#endif /* __KERNEL__ */ +#endif /* __ASM_POWERPC_RTC_H__ */ diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h new file mode 100644 index 00000000000..4eecc38f709 --- /dev/null +++ b/include/asm-powerpc/time.h @@ -0,0 +1,212 @@ +/* + * Common time prototypes and such for all ppc machines. + * + * Written by Cort Dougan (cort@cs.nmt.edu) to merge + * Paul Mackerras' version and mine for PReP and Pmac. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#ifndef __POWERPC_TIME_H +#define __POWERPC_TIME_H + +#ifdef __KERNEL__ +#include +#include +#include + +#include +#ifdef CONFIG_PPC64 +#include +#include +#endif + +/* time.c */ +extern unsigned long tb_ticks_per_jiffy; +extern unsigned long tb_ticks_per_usec; +extern unsigned long tb_ticks_per_sec; +extern u64 tb_to_xs; +extern unsigned tb_to_us; +extern u64 tb_last_stamp; + +DECLARE_PER_CPU(unsigned long, last_jiffy); + +struct rtc_time; +extern void to_tm(int tim, struct rtc_time * tm); +extern time_t last_rtc_update; + +extern void generic_calibrate_decr(void); +extern void wakeup_decrementer(void); + +/* Some sane defaults: 125 MHz timebase, 1GHz processor */ +extern unsigned long ppc_proc_freq; +#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8) +extern unsigned long ppc_tb_freq; +#define DEFAULT_TB_FREQ 125000000UL + +/* + * By putting all of this stuff into a single struct we + * reduce the number of cache lines touched by do_gettimeofday. + * Both by collecting all of the data in one cache line and + * by touching only one TOC entry on ppc64. + */ +struct gettimeofday_vars { + u64 tb_to_xs; + u64 stamp_xsec; + u64 tb_orig_stamp; +}; + +struct gettimeofday_struct { + unsigned long tb_ticks_per_sec; + struct gettimeofday_vars vars[2]; + struct gettimeofday_vars * volatile varp; + unsigned var_idx; + unsigned tb_to_us; +}; + +struct div_result { + u64 result_high; + u64 result_low; +}; + +/* Accessor functions for the timebase (RTC on 601) registers. */ +/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */ +#ifdef CONFIG_6xx +#define __USE_RTC() cpu_has_feature(CPU_FTR_USE_TB) +#else +#define __USE_RTC() 0 +#endif + +/* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */ +static inline unsigned long get_tbl(void) +{ + unsigned long tbl; + +#if defined(CONFIG_403GCX) + asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); +#else + asm volatile("mftb %0" : "=r" (tbl)); +#endif + return tbl; +} + +static inline unsigned int get_tbu(void) +{ + unsigned int tbu; + +#if defined(CONFIG_403GCX) + asm volatile("mfspr %0, 0x3dc" : "=r" (tbu)); +#else + asm volatile("mftbu %0" : "=r" (tbu)); +#endif + return tbu; +} + +static inline unsigned int get_rtcl(void) +{ + unsigned int rtcl; + + asm volatile("mfrtcl %0" : "=r" (rtcl)); + return rtcl; +} + +#ifdef CONFIG_PPC64 +static inline u64 get_tb(void) +{ + return mftb(); +} +#else +static inline u64 get_tb(void) +{ + unsigned int tbhi, tblo, tbhi2; + + do { + tbhi = get_tbu(); + tblo = get_tbl(); + tbhi2 = get_tbu(); + } while (tbhi != tbhi2); + + return ((u64)tbhi << 32) | tblo; +} +#endif + +static inline void set_tb(unsigned int upper, unsigned int lower) +{ + mtspr(SPRN_TBWL, 0); + mtspr(SPRN_TBWU, upper); + mtspr(SPRN_TBWL, lower); +} + +/* Accessor functions for the decrementer register. + * The 4xx doesn't even have a decrementer. I tried to use the + * generic timer interrupt code, which seems OK, with the 4xx PIT + * in auto-reload mode. The problem is PIT stops counting when it + * hits zero. If it would wrap, we could use it just like a decrementer. + */ +static inline unsigned int get_dec(void) +{ +#if defined(CONFIG_40x) + return (mfspr(SPRN_PIT)); +#else + return (mfspr(SPRN_DEC)); +#endif +} + +static inline void set_dec(int val) +{ +#if defined(CONFIG_40x) + return; /* Have to let it auto-reload */ +#elif defined(CONFIG_8xx_CPU6) + set_dec_cpu6(val); +#else +#ifdef CONFIG_PPC_ISERIES + struct paca_struct *lpaca = get_paca(); + int cur_dec; + + if (lpaca->lppaca.shared_proc) { + lpaca->lppaca.virtual_decr = val; + cur_dec = get_dec(); + if (cur_dec > val) + HvCall_setVirtualDecr(); + } else +#endif + mtspr(SPRN_DEC, val); +#endif /* not 40x or 8xx_CPU6 */ +} + +static inline unsigned long tb_ticks_since(unsigned long tstamp) +{ + if (__USE_RTC()) { + int delta = get_rtcl() - (unsigned int) tstamp; + return delta < 0 ? delta + 1000000000 : delta; + } + return get_tbl() - tstamp; +} + +#define mulhwu(x,y) \ +({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) + +#ifdef CONFIG_PPC64 +#define mulhdu(x,y) \ +({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) +#else +extern u64 mulhdu(u64, u64); +#endif + +unsigned mulhwu_scale_factor(unsigned, unsigned); +void div128_by_32(u64 dividend_high, u64 dividend_low, + unsigned divisor, struct div_result *dr); + +/* Used to store Processor Utilization register (purr) values */ + +struct cpu_usage { + u64 current_tb; /* Holds the current purr register values */ +}; + +DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array); + +#endif /* __KERNEL__ */ +#endif /* __PPC64_TIME_H */ diff --git a/include/asm-ppc64/time.h b/include/asm-ppc64/time.h deleted file mode 100644 index c6c762cad8b..00000000000 --- a/include/asm-ppc64/time.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Common time prototypes and such for all ppc machines. - * - * Written by Cort Dougan (cort@cs.nmt.edu) to merge - * Paul Mackerras' version and mine for PReP and Pmac. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#ifndef __PPC64_TIME_H -#define __PPC64_TIME_H - -#ifdef __KERNEL__ -#include -#include -#include - -#include -#include -#include - -/* time.c */ -extern unsigned long tb_ticks_per_jiffy; -extern unsigned long tb_ticks_per_usec; -extern unsigned long tb_ticks_per_sec; -extern unsigned long tb_to_xs; -extern unsigned tb_to_us; -extern unsigned long tb_last_stamp; - -struct rtc_time; -extern void to_tm(int tim, struct rtc_time * tm); -extern time_t last_rtc_update; - -void generic_calibrate_decr(void); -void setup_default_decr(void); - -/* Some sane defaults: 125 MHz timebase, 1GHz processor */ -extern unsigned long ppc_proc_freq; -#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8) -extern unsigned long ppc_tb_freq; -#define DEFAULT_TB_FREQ 125000000UL - -/* - * By putting all of this stuff into a single struct we - * reduce the number of cache lines touched by do_gettimeofday. - * Both by collecting all of the data in one cache line and - * by touching only one TOC entry - */ -struct gettimeofday_vars { - unsigned long tb_to_xs; - unsigned long stamp_xsec; - unsigned long tb_orig_stamp; -}; - -struct gettimeofday_struct { - unsigned long tb_ticks_per_sec; - struct gettimeofday_vars vars[2]; - struct gettimeofday_vars * volatile varp; - unsigned var_idx; - unsigned tb_to_us; -}; - -struct div_result { - unsigned long result_high; - unsigned long result_low; -}; - -int via_calibrate_decr(void); - -static __inline__ unsigned long get_tb(void) -{ - return mftb(); -} - -/* Accessor functions for the decrementer register. */ -static __inline__ unsigned int get_dec(void) -{ - return (mfspr(SPRN_DEC)); -} - -static __inline__ void set_dec(int val) -{ -#ifdef CONFIG_PPC_ISERIES - struct paca_struct *lpaca = get_paca(); - int cur_dec; - - if (lpaca->lppaca.shared_proc) { - lpaca->lppaca.virtual_decr = val; - cur_dec = get_dec(); - if (cur_dec > val) - HvCall_setVirtualDecr(); - } else -#endif - mtspr(SPRN_DEC, val); -} - -static inline unsigned long tb_ticks_since(unsigned long tstamp) -{ - return get_tb() - tstamp; -} - -#define mulhwu(x,y) \ -({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) -#define mulhdu(x,y) \ -({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;}) - - -unsigned mulhwu_scale_factor(unsigned, unsigned); -void div128_by_32( unsigned long dividend_high, unsigned long dividend_low, - unsigned divisor, struct div_result *dr ); - -/* Used to store Processor Utilization register (purr) values */ - -struct cpu_usage { - u64 current_tb; /* Holds the current purr register values */ -}; - -DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array); - -#endif /* __KERNEL__ */ -#endif /* __PPC64_TIME_H */ -- cgit v1.2.3-70-g09d2 From 5fb4dc9bf5e3af1ae91be97108bc3b1233252ddf Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Sat, 22 Oct 2005 15:25:01 +1000 Subject: merge linus head to drm-mm branch --- drivers/char/drm/drm_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/drm/drm_vm.c b/drivers/char/drm/drm_vm.c index e84a7876a1b..3f73aa774c8 100644 --- a/drivers/char/drm/drm_vm.c +++ b/drivers/char/drm/drm_vm.c @@ -155,7 +155,7 @@ static __inline__ struct page *drm_do_vm_shm_nopage(struct vm_area_struct *vma, offset = address - vma->vm_start; i = (unsigned long)map->handle + offset; page = (map->type == _DRM_CONSISTENT) ? - virt_to_page((void *)i) : vmalloc_to_page((void *)i); + virt_to_page((void *)i) : vmalloc_to_page((void *)i); if (!page) return NOPAGE_OOM; get_page(page); -- cgit v1.2.3-70-g09d2 From 6fdf5392caa4c3cba65add0a4beec9f5eb96b723 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 24 Oct 2005 14:53:21 +1000 Subject: powerpc: don't duplicate name between vio_driver and device_driver Just set the name field directly in the device_driver structure contained in the vio_driver struct. Signed-off-by: Stephen Rothwell --- arch/powerpc/kernel/vio.c | 3 +-- drivers/block/viodasd.c | 6 ++++-- drivers/cdrom/viocd.c | 6 ++++-- drivers/char/hvc_vio.c | 2 +- drivers/char/hvcs.c | 4 +++- drivers/char/viotape.c | 6 ++++-- drivers/net/ibmveth.c | 10 ++++++---- drivers/net/iseries_veth.c | 6 ++++-- drivers/scsi/ibmvscsi/ibmvscsi.c | 6 ++++-- include/asm-powerpc/vio.h | 1 - 10 files changed, 31 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c index 0e555b7a658..3aec492ec76 100644 --- a/arch/powerpc/kernel/vio.c +++ b/arch/powerpc/kernel/vio.c @@ -76,10 +76,9 @@ static int vio_bus_remove(struct device *dev) int vio_register_driver(struct vio_driver *viodrv) { printk(KERN_DEBUG "%s: driver %s registering\n", __FUNCTION__, - viodrv->name); + viodrv->driver.name); /* fill in 'struct driver' fields */ - viodrv->driver.name = viodrv->name; viodrv->driver.bus = &vio_bus_type; viodrv->driver.probe = vio_bus_probe; viodrv->driver.remove = vio_bus_remove; diff --git a/drivers/block/viodasd.c b/drivers/block/viodasd.c index e46ecd23b3a..ea72faa8343 100644 --- a/drivers/block/viodasd.c +++ b/drivers/block/viodasd.c @@ -781,10 +781,12 @@ static struct vio_device_id viodasd_device_table[] __devinitdata = { MODULE_DEVICE_TABLE(vio, viodasd_device_table); static struct vio_driver viodasd_driver = { - .name = "viodasd", .id_table = viodasd_device_table, .probe = viodasd_probe, - .remove = viodasd_remove + .remove = viodasd_remove, + .driver = { + .name = "viodasd", + } }; /* diff --git a/drivers/cdrom/viocd.c b/drivers/cdrom/viocd.c index 0829db58462..255d24ad704 100644 --- a/drivers/cdrom/viocd.c +++ b/drivers/cdrom/viocd.c @@ -739,10 +739,12 @@ static struct vio_device_id viocd_device_table[] __devinitdata = { MODULE_DEVICE_TABLE(vio, viocd_device_table); static struct vio_driver viocd_driver = { - .name = "viocd", .id_table = viocd_device_table, .probe = viocd_probe, - .remove = viocd_remove + .remove = viocd_remove, + .driver = { + .name = "viocd", + } }; static int __init viocd_init(void) diff --git a/drivers/char/hvc_vio.c b/drivers/char/hvc_vio.c index 78d681dc35a..f5212eb2b41 100644 --- a/drivers/char/hvc_vio.c +++ b/drivers/char/hvc_vio.c @@ -95,11 +95,11 @@ static int __devexit hvc_vio_remove(struct vio_dev *vdev) } static struct vio_driver hvc_vio_driver = { - .name = hvc_driver_name, .id_table = hvc_driver_table, .probe = hvc_vio_probe, .remove = hvc_vio_remove, .driver = { + .name = hvc_driver_name, .owner = THIS_MODULE, } }; diff --git a/drivers/char/hvcs.c b/drivers/char/hvcs.c index f47f009f925..8486298c011 100644 --- a/drivers/char/hvcs.c +++ b/drivers/char/hvcs.c @@ -720,10 +720,12 @@ static int __devexit hvcs_remove(struct vio_dev *dev) }; static struct vio_driver hvcs_vio_driver = { - .name = hvcs_driver_name, .id_table = hvcs_driver_table, .probe = hvcs_probe, .remove = hvcs_remove, + .driver = { + .name = hvcs_driver_name, + } }; /* Only called from hvcs_get_pi please */ diff --git a/drivers/char/viotape.c b/drivers/char/viotape.c index 0aff45fac2e..8fc1115c4b6 100644 --- a/drivers/char/viotape.c +++ b/drivers/char/viotape.c @@ -996,10 +996,12 @@ static struct vio_device_id viotape_device_table[] __devinitdata = { MODULE_DEVICE_TABLE(vio, viotape_device_table); static struct vio_driver viotape_driver = { - .name = "viotape", .id_table = viotape_device_table, .probe = viotape_probe, - .remove = viotape_remove + .remove = viotape_remove, + .driver = { + .name = "viotape", + } }; diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index a2c4dd4fb22..fcf6f2c7630 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c @@ -1150,10 +1150,12 @@ static struct vio_device_id ibmveth_device_table[] __devinitdata= { MODULE_DEVICE_TABLE(vio, ibmveth_device_table); static struct vio_driver ibmveth_driver = { - .name = (char *)ibmveth_driver_name, - .id_table = ibmveth_device_table, - .probe = ibmveth_probe, - .remove = ibmveth_remove + .id_table = ibmveth_device_table, + .probe = ibmveth_probe, + .remove = ibmveth_remove, + .driver = { + .name = ibmveth_driver_name, + } }; static int __init ibmveth_module_init(void) diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index db3bc2f6f0f..33613fe9556 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c @@ -1648,10 +1648,12 @@ static struct vio_device_id veth_device_table[] __devinitdata = { MODULE_DEVICE_TABLE(vio, veth_device_table); static struct vio_driver veth_driver = { - .name = DRV_NAME, .id_table = veth_device_table, .probe = veth_probe, - .remove = veth_remove + .remove = veth_remove, + .driver = { + .name = DRV_NAME, + } }; /* diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c b/drivers/scsi/ibmvscsi/ibmvscsi.c index ff25210b00b..965e5373538 100644 --- a/drivers/scsi/ibmvscsi/ibmvscsi.c +++ b/drivers/scsi/ibmvscsi/ibmvscsi.c @@ -1546,10 +1546,12 @@ static struct vio_device_id ibmvscsi_device_table[] __devinitdata = { MODULE_DEVICE_TABLE(vio, ibmvscsi_device_table); static struct vio_driver ibmvscsi_driver = { - .name = "ibmvscsi", .id_table = ibmvscsi_device_table, .probe = ibmvscsi_probe, - .remove = ibmvscsi_remove + .remove = ibmvscsi_remove, + .driver = { + .name = "ibmvscsi", + } }; int __init ibmvscsi_module_init(void) diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h index f10f72f24fd..104c58501d0 100644 --- a/include/asm-powerpc/vio.h +++ b/include/asm-powerpc/vio.h @@ -55,7 +55,6 @@ struct vio_dev { struct vio_driver { struct list_head node; - char *name; const struct vio_device_id *id_table; int (*probe)(struct vio_dev *dev, const struct vio_device_id *id); int (*remove)(struct vio_dev *dev); -- cgit v1.2.3-70-g09d2 From 915124d8114ec8c3825b10a39151bf9e851593bb Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Mon, 24 Oct 2005 15:12:22 +1000 Subject: powerpc: set the driver.owner field for all vio drivers Signed-off-by: Stephen Rothwell --- drivers/block/viodasd.c | 3 ++- drivers/cdrom/viocd.c | 3 ++- drivers/char/hvcs.c | 1 + drivers/char/viotape.c | 3 ++- drivers/net/ibmveth.c | 2 +- drivers/net/iseries_veth.c | 1 + drivers/scsi/ibmvscsi/ibmvscsi.c | 3 ++- 7 files changed, 11 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/block/viodasd.c b/drivers/block/viodasd.c index ea72faa8343..709f809f79f 100644 --- a/drivers/block/viodasd.c +++ b/drivers/block/viodasd.c @@ -778,14 +778,15 @@ static struct vio_device_id viodasd_device_table[] __devinitdata = { { "viodasd", "" }, { "", "" } }; - MODULE_DEVICE_TABLE(vio, viodasd_device_table); + static struct vio_driver viodasd_driver = { .id_table = viodasd_device_table, .probe = viodasd_probe, .remove = viodasd_remove, .driver = { .name = "viodasd", + .owner = THIS_MODULE, } }; diff --git a/drivers/cdrom/viocd.c b/drivers/cdrom/viocd.c index 255d24ad704..36f31d20222 100644 --- a/drivers/cdrom/viocd.c +++ b/drivers/cdrom/viocd.c @@ -736,14 +736,15 @@ static struct vio_device_id viocd_device_table[] __devinitdata = { { "viocd", "" }, { "", "" } }; - MODULE_DEVICE_TABLE(vio, viocd_device_table); + static struct vio_driver viocd_driver = { .id_table = viocd_device_table, .probe = viocd_probe, .remove = viocd_remove, .driver = { .name = "viocd", + .owner = THIS_MODULE, } }; diff --git a/drivers/char/hvcs.c b/drivers/char/hvcs.c index 8486298c011..53dc77c760f 100644 --- a/drivers/char/hvcs.c +++ b/drivers/char/hvcs.c @@ -725,6 +725,7 @@ static struct vio_driver hvcs_vio_driver = { .remove = hvcs_remove, .driver = { .name = hvcs_driver_name, + .owner = THIS_MODULE, } }; diff --git a/drivers/char/viotape.c b/drivers/char/viotape.c index 8fc1115c4b6..d92a0564500 100644 --- a/drivers/char/viotape.c +++ b/drivers/char/viotape.c @@ -993,14 +993,15 @@ static struct vio_device_id viotape_device_table[] __devinitdata = { { "viotape", "" }, { "", "" } }; - MODULE_DEVICE_TABLE(vio, viotape_device_table); + static struct vio_driver viotape_driver = { .id_table = viotape_device_table, .probe = viotape_probe, .remove = viotape_remove, .driver = { .name = "viotape", + .owner = THIS_MODULE, } }; diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index fcf6f2c7630..f5dc632452f 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c @@ -1146,7 +1146,6 @@ static struct vio_device_id ibmveth_device_table[] __devinitdata= { { "network", "IBM,l-lan"}, { "", "" } }; - MODULE_DEVICE_TABLE(vio, ibmveth_device_table); static struct vio_driver ibmveth_driver = { @@ -1155,6 +1154,7 @@ static struct vio_driver ibmveth_driver = { .remove = ibmveth_remove, .driver = { .name = ibmveth_driver_name, + .owner = THIS_MODULE, } }; diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index 33613fe9556..f5ea39ff101 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c @@ -1653,6 +1653,7 @@ static struct vio_driver veth_driver = { .remove = veth_remove, .driver = { .name = DRV_NAME, + .owner = THIS_MODULE, } }; diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c b/drivers/scsi/ibmvscsi/ibmvscsi.c index 965e5373538..822b9fa706f 100644 --- a/drivers/scsi/ibmvscsi/ibmvscsi.c +++ b/drivers/scsi/ibmvscsi/ibmvscsi.c @@ -1543,14 +1543,15 @@ static struct vio_device_id ibmvscsi_device_table[] __devinitdata = { {"vscsi", "IBM,v-scsi"}, { "", "" } }; - MODULE_DEVICE_TABLE(vio, ibmvscsi_device_table); + static struct vio_driver ibmvscsi_driver = { .id_table = ibmvscsi_device_table, .probe = ibmvscsi_probe, .remove = ibmvscsi_remove, .driver = { .name = "ibmvscsi", + .owner = THIS_MODULE, } }; -- cgit v1.2.3-70-g09d2 From 67e1a014fbc0e472ccc55766a63640a767ede3bf Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 24 Oct 2005 18:41:39 +1000 Subject: drm: fix warning on 64-bit platforms.. This looks ugly, but it is the only thing that makes sense that doesn't change the API. Signed-off-by: Dave Airlie --- drivers/char/drm/drm_bufs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/char/drm/drm_bufs.c b/drivers/char/drm/drm_bufs.c index 58e513a4474..319bdea8de8 100644 --- a/drivers/char/drm/drm_bufs.c +++ b/drivers/char/drm/drm_bufs.c @@ -309,7 +309,9 @@ int drm_addmap_ioctl(struct inode *inode, struct file *filp, if (copy_to_user(argp, maplist->map, sizeof(drm_map_t))) return -EFAULT; - if (put_user((void *)maplist->user_token, &argp->handle)) + + /* avoid a warning on 64-bit, this casting isn't very nice, but the API is set so too late */ + if (put_user((void *)(unsigned long)maplist->user_token, &argp->handle)) return -EFAULT; return 0; } -- cgit v1.2.3-70-g09d2 From a4e62fa031a9681477207b08391c3a5c5c831ce7 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 24 Oct 2005 18:45:11 +1000 Subject: drm: remove unused components of drm structures These haven't been used in quite a long time, takes 1K buffer out of structures. Signed-off-by: Dave Airlie --- drivers/char/drm/drmP.h | 5 ----- drivers/char/drm/drm_fops.c | 3 --- 2 files changed, 8 deletions(-) (limited to 'drivers') diff --git a/drivers/char/drm/drmP.h b/drivers/char/drm/drmP.h index 255a21783d1..3dc3c9d79ae 100644 --- a/drivers/char/drm/drmP.h +++ b/drivers/char/drm/drmP.h @@ -108,7 +108,6 @@ #define DRM_KERNEL_CONTEXT 0 /**< Change drm_resctx if changed */ #define DRM_RESERVED_CONTEXTS 1 /**< Change drm_resctx if changed */ #define DRM_LOOPING_LIMIT 5000000 -#define DRM_BSZ 1024 /**< Buffer size for /dev/drm? output */ #define DRM_TIME_SLICE (HZ/20) /**< Time slice for GLXContexts */ #define DRM_LOCK_SLICE 1 /**< Time slice for lock, in jiffies */ @@ -707,10 +706,6 @@ typedef struct drm_device { cycles_t ctx_start; cycles_t lck_start; - char buf[DRM_BSZ]; /**< Output buffer */ - char *buf_rp; /**< Read pointer */ - char *buf_wp; /**< Write pointer */ - char *buf_end; /**< End pointer */ struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */ wait_queue_head_t buf_readers; /**< Processes waiting to read */ wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */ diff --git a/drivers/char/drm/drm_fops.c b/drivers/char/drm/drm_fops.c index e0124a9ba14..bf0a740122b 100644 --- a/drivers/char/drm/drm_fops.c +++ b/drivers/char/drm/drm_fops.c @@ -96,9 +96,6 @@ static int drm_setup(drm_device_t * dev) dev->ctx_start = 0; dev->lck_start = 0; - dev->buf_rp = dev->buf; - dev->buf_wp = dev->buf; - dev->buf_end = dev->buf + DRM_BSZ; dev->buf_async = NULL; init_waitqueue_head(&dev->buf_readers); init_waitqueue_head(&dev->buf_writers); -- cgit v1.2.3-70-g09d2 From 8168f902fa9c2ca8930ea8d72cce283234df03b8 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Tue, 25 Oct 2005 16:56:43 +1000 Subject: [PATCH] ppc64: make dma_addr_t 64 bits There has been a need expressed for dma_addr_t to be 64 bits on PPC64. This patch does that. Signed-off-by: Stephen Rothwell Signed-off-by: Paul Mackerras --- drivers/net/ibmveth.c | 2 +- include/asm-powerpc/types.h | 4 ++++ include/asm-ppc64/scatterlist.h | 2 +- 3 files changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index f5dc632452f..cbe9368a4d5 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c @@ -532,7 +532,7 @@ static int ibmveth_open(struct net_device *netdev) if(lpar_rc != H_Success) { ibmveth_error_printk("h_register_logical_lan failed with %ld\n", lpar_rc); - ibmveth_error_printk("buffer TCE:0x%x filter TCE:0x%x rxq desc:0x%lx MAC:0x%lx\n", + ibmveth_error_printk("buffer TCE:0x%lx filter TCE:0x%lx rxq desc:0x%lx MAC:0x%lx\n", adapter->buffer_list_dma, adapter->filter_list_dma, rxq_desc.desc, diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h index f70cd3fb32d..ec3c2ee8bf8 100644 --- a/include/asm-powerpc/types.h +++ b/include/asm-powerpc/types.h @@ -85,7 +85,11 @@ typedef unsigned long long u64; typedef __vector128 vector128; +#ifdef __powerpc64__ +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef u64 dma64_addr_t; typedef struct { diff --git a/include/asm-ppc64/scatterlist.h b/include/asm-ppc64/scatterlist.h index cecce6c6dfb..65a2a027ac9 100644 --- a/include/asm-ppc64/scatterlist.h +++ b/include/asm-ppc64/scatterlist.h @@ -19,7 +19,7 @@ struct scatterlist { unsigned int length; /* For TCE support */ - u32 dma_address; + dma_addr_t dma_address; u32 dma_length; }; -- cgit v1.2.3-70-g09d2 From de957c89b7dadb3147e885d7b6eb9db73d0eea57 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Fri, 28 Oct 2005 17:46:13 -0700 Subject: [PATCH] MPC8xx PCMCIA driver Here is an uptodated version of the MPC8xx PCMCIA driver for v2.6, addressing comments by Jeff and Dominik: - use IO accessors instead of direct device memory referencing - avoid usage of non-standard "uint/uchar" data types - kill struct typedef's Will submit it for inclusion once v2.6.14 is out. Testing on 8xx platforms is more than welcome! Works like a charm on our custom hardware (CONFIG_PRxK). Cc: Dominik Brodowski Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- drivers/pcmcia/Kconfig | 10 + drivers/pcmcia/Makefile | 1 + drivers/pcmcia/m8xx_pcmcia.c | 1290 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1301 insertions(+) create mode 100644 drivers/pcmcia/m8xx_pcmcia.c (limited to 'drivers') diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 36cc9a96a33..ccf20039e90 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -154,6 +154,16 @@ config TCIC "Bridge" is the name used for the hardware inside your computer that PCMCIA cards are plugged into. If unsure, say N. +config PCMCIA_M8XX + tristate "MPC8xx PCMCIA support" + depends on PCMCIA && PPC + select PCCARD_NONSTATIC + help + Say Y here to include support for PowerPC 8xx series PCMCIA + controller. + + This driver is also available as a module called m8xx_pcmcia. + config HD64465_PCMCIA tristate "HD64465 host bridge support" depends on HD64465 && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index a41fbb38fdc..cb4861d9cb8 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_PD6729) += pd6729.o obj-$(CONFIG_I82365) += i82365.o obj-$(CONFIG_I82092) += i82092.o obj-$(CONFIG_TCIC) += tcic.o +obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o obj-$(CONFIG_HD64465_PCMCIA) += hd64465_ss.o obj-$(CONFIG_PCMCIA_SA1100) += sa11xx_core.o sa1100_cs.o obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_core.o sa1111_cs.o diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c new file mode 100644 index 00000000000..f8bed87cf2f --- /dev/null +++ b/drivers/pcmcia/m8xx_pcmcia.c @@ -0,0 +1,1290 @@ +/* + * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. + * + * (C) 1999-2000 Magnus Damm + * (C) 2001-2002 Montavista Software, Inc. + * + * + * Support for two slots by Cyclades Corporation + * + * Further fixes, v2.6 kernel port + * + * + * "The ExCA standard specifies that socket controllers should provide + * two IO and five memory windows per socket, which can be independently + * configured and positioned in the host address space and mapped to + * arbitrary segments of card address space. " - David A Hinds. 1999 + * + * This controller does _not_ meet the ExCA standard. + * + * m8xx pcmcia controller brief info: + * + 8 windows (attrib, mem, i/o) + * + up to two slots (SLOT_A and SLOT_B) + * + inputpins, outputpins, event and mask registers. + * - no offset register. sigh. + * + * Because of the lacking offset register we must map the whole card. + * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. + * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO + * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. + * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. + * They are maximum 64KByte each... + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#ifdef PCMCIA_DEBUG +static int pc_debug = PCMCIA_DEBUG; +module_param(pc_debug, int, 0); +#define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args); +#else +#define dprintk(args...) +#endif + +#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) +#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) + +static const char *version = "Version 0.06, Aug 2005"; +MODULE_LICENSE("Dual MPL/GPL"); + +#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) + +/* The RPX series use SLOT_B */ +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) +#define CONFIG_PCMCIA_SLOT_B +#define CONFIG_BD_IS_MHZ +#endif + +/* The ADS board use SLOT_A */ +#ifdef CONFIG_ADS +#define CONFIG_PCMCIA_SLOT_A +#define CONFIG_BD_IS_MHZ +#endif + +/* The FADS series are a mess */ +#ifdef CONFIG_FADS +#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) +#define CONFIG_PCMCIA_SLOT_A +#else +#define CONFIG_PCMCIA_SLOT_B +#endif +#endif + +/* Cyclades ACS uses both slots */ +#ifdef CONFIG_PRxK +#define CONFIG_PCMCIA_SLOT_A +#define CONFIG_PCMCIA_SLOT_B +#endif + +#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ + +#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) + +#define PCMCIA_SOCKETS_NO 2 +/* We have only 8 windows, dualsocket support will be limited. */ +#define PCMCIA_MEM_WIN_NO 2 +#define PCMCIA_IO_WIN_NO 2 +#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" + +#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) + +#define PCMCIA_SOCKETS_NO 1 +/* full support for one slot */ +#define PCMCIA_MEM_WIN_NO 5 +#define PCMCIA_IO_WIN_NO 2 + +/* define _slot_ to be able to optimize macros */ + +#ifdef CONFIG_PCMCIA_SLOT_A +#define _slot_ 0 +#define PCMCIA_SLOT_MSG "SLOT_A" +#else +#define _slot_ 1 +#define PCMCIA_SLOT_MSG "SLOT_B" +#endif + +#else +#error m8xx_pcmcia: Bad configuration! +#endif + +/* ------------------------------------------------------------------------- */ + +#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ +#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ +#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ + +#define PCMCIA_SCHLVL PCMCIA_INTERRUPT /* Status Change Interrupt Level */ + +/* ------------------------------------------------------------------------- */ + +/* 2.4.x and newer has this always in HZ */ +#define M8XX_BUSFREQ ((((bd_t *)&(__res))->bi_busfreq)) + +static int pcmcia_schlvl = PCMCIA_SCHLVL; + +static spinlock_t events_lock = SPIN_LOCK_UNLOCKED; + + +#define PCMCIA_SOCKET_KEY_5V 1 +#define PCMCIA_SOCKET_KEY_LV 2 + +/* look up table for pgcrx registers */ +static u32 *m8xx_pgcrx[2] = { + &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcra, + &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pgcrb +}; + +/* + * This structure is used to address each window in the PCMCIA controller. + * + * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly + * after pcmcia_win[n]... + */ + +struct pcmcia_win { + u32 br; + u32 or; +}; + +/* + * For some reason the hardware guys decided to make both slots share + * some registers. + * + * Could someone invent object oriented hardware ? + * + * The macros are used to get the right bit from the registers. + * SLOT_A : slot = 0 + * SLOT_B : slot = 1 + */ + +#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) +#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) +#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) +#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) + +#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) +#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) +#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) +#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) +#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) +#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) +#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) +#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) +#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) +#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) +#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) + +#define M8XX_PCMCIA_POR_VALID 0x00000001 +#define M8XX_PCMCIA_POR_WRPROT 0x00000002 +#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 +#define M8XX_PCMCIA_POR_IO 0x00000018 +#define M8XX_PCMCIA_POR_16BIT 0x00000040 + +#define M8XX_PGCRX(slot) m8xx_pgcrx[slot] + +#define M8XX_PGCRX_CXOE 0x00000080 +#define M8XX_PGCRX_CXRESET 0x00000040 + +/* we keep one lookup table per socket to check flags */ + +#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ + +struct event_table { + u32 regbit; + u32 eventbit; +}; + +struct socket_info { + void (*handler)(void *info, u32 events); + void *info; + + u32 slot; + + socket_state_t state; + struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; + struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; + struct event_table events[PCMCIA_EVENTS_MAX]; + struct pcmcia_socket socket; +}; + +static struct socket_info socket[PCMCIA_SOCKETS_NO]; + +/* + * Search this table to see if the windowsize is + * supported... + */ + +#define M8XX_SIZES_NO 32 + +static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = +{ + 0x00000001, 0x00000002, 0x00000008, 0x00000004, + 0x00000080, 0x00000040, 0x00000010, 0x00000020, + 0x00008000, 0x00004000, 0x00001000, 0x00002000, + 0x00000100, 0x00000200, 0x00000800, 0x00000400, + + 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x01000000, 0x02000000, 0xffffffff, 0x04000000, + 0x00010000, 0x00020000, 0x00080000, 0x00040000, + 0x00800000, 0x00400000, 0x00100000, 0x00200000 +}; + +/* ------------------------------------------------------------------------- */ + +static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs); + +#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ + +/* ------------------------------------------------------------------------- */ +/* board specific stuff: */ +/* voltage_set(), hardware_enable() and hardware_disable() */ +/* ------------------------------------------------------------------------- */ +/* RPX Boards from Embedded Planet */ + +#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) + +/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks. + * SYPCR is write once only, therefore must the slowest memory be faster + * than the bus monitor or we will get a machine check due to the bus timeout. + */ + +#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" + +#undef PCMCIA_BMT_LIMIT +#define PCMCIA_BMT_LIMIT (6*8) + +static int voltage_set(int slot, int vcc, int vpp) +{ + u32 reg = 0; + + switch(vcc) { + case 0: break; + case 33: + reg |= BCSR1_PCVCTL4; + break; + case 50: + reg |= BCSR1_PCVCTL5; + break; + default: + return 1; + } + + switch(vpp) { + case 0: break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCVCTL6; + else + return 1; + break; + case 120: + reg |= BCSR1_PCVCTL7; + default: + return 1; + } + + if(!((vcc == 50) || (vcc == 0))) + return 1; + + /* first, turn off all power */ + + out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7)); + + /* enable new powersettings */ + + out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg); + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V +#define hardware_enable(_slot_) /* No hardware to enable */ +#define hardware_disable(_slot_) /* No hardware to disable */ + +#endif /* CONFIG_RPXCLASSIC */ + +/* FADS Boards from Motorola */ + +#if defined(CONFIG_FADS) + +#define PCMCIA_BOARD_MSG "FADS" + +static int voltage_set(int slot, int vcc, int vpp) +{ + u32 reg = 0; + + switch(vcc) { + case 0: + break; + case 33: + reg |= BCSR1_PCCVCC0; + break; + case 50: + reg |= BCSR1_PCCVCC1; + break; + default: + return 1; + } + + switch(vpp) { + case 0: + break; + case 33: + case 50: + if(vcc == vpp) + reg |= BCSR1_PCCVPP1; + else + return 1; + break; + case 120: + if ((vcc == 33) || (vcc == 50)) + reg |= BCSR1_PCCVPP0; + else + return 1; + default: + return 1; + } + + /* first, turn off all power */ + out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK)); + + /* enable new powersettings */ + out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | reg); + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V + +static void hardware_enable(int slot) +{ + out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) & ~BCSR1_PCCEN); +} + +static void hardware_disable(int slot) +{ + out_be32(&((u32 *)BCSR1), in_be32(&((u32 *)BCSR1)) | BCSR1_PCCEN); +} + +#endif + +/* ------------------------------------------------------------------------- */ +/* Motorola MBX860 */ + +#if defined(CONFIG_MBX) + +#define PCMCIA_BOARD_MSG "MBX" + +static int voltage_set(int slot, int vcc, int vpp) +{ + u8 reg = 0; + + switch(vcc) { + case 0: + break; + case 33: + reg |= CSR2_VCC_33; + break; + case 50: + reg |= CSR2_VCC_50; + break; + default: + return 1; + } + + switch(vpp) { + case 0: + break; + case 33: + case 50: + if(vcc == vpp) + reg |= CSR2_VPP_VCC; + else + return 1; + break; + case 120: + if ((vcc == 33) || (vcc == 50)) + reg |= CSR2_VPP_12; + else + return 1; + default: + return 1; + } + + /* first, turn off all power */ + out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK)); + + /* enable new powersettings */ + out_8(&((u8 *)MBX_CSR2_ADDR), in_8(&((u8 *)MBX_CSR2_ADDR)) | reg); + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V +#define hardware_enable(_slot_) /* No hardware to enable */ +#define hardware_disable(_slot_) /* No hardware to disable */ + +#endif /* CONFIG_MBX */ + +#if defined(CONFIG_PRxK) +#include +extern volatile fpga_pc_regs *fpga_pc; + +#define PCMCIA_BOARD_MSG "MPC855T" + +static int voltage_set(int slot, int vcc, int vpp) +{ + u8 reg = 0; + u8 regread; + cpld_regs *ccpld = get_cpld(); + + switch(vcc) { + case 0: + break; + case 33: + reg |= PCMCIA_VCC_33; + break; + case 50: + reg |= PCMCIA_VCC_50; + break; + default: + return 1; + } + + switch(vpp) { + case 0: + break; + case 33: + case 50: + if(vcc == vpp) + reg |= PCMCIA_VPP_VCC; + else + return 1; + break; + case 120: + if ((vcc == 33) || (vcc == 50)) + reg |= PCMCIA_VPP_12; + else + return 1; + default: + return 1; + } + + reg = reg >> (slot << 2); + regread = in_8(&ccpld->fpga_pc_ctl); + if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { + /* enable new powersettings */ + regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)); + out_8(&ccpld->fpga_pc_ctl, reg | regread); + msleep(100); + } + + return 0; +} + +#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV +#define hardware_enable(_slot_) /* No hardware to enable */ +#define hardware_disable(_slot_) /* No hardware to disable */ + +#endif /* CONFIG_PRxK */ + +static void m8xx_shutdown(void) +{ + u32 m, i; + struct pcmcia_win *w; + + for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ + w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, M8XX_PCMCIA_MASK(i)); + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & ~M8XX_PCMCIA_MASK(i)); + + /* turn off interrupt and disable CxOE */ + out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); + + /* turn off memory windows */ + for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { + out_be32(&w->or, 0); /* set to not valid */ + w++; + } + + /* turn off voltage */ + voltage_set(i, 0, 0); + + /* disable external hardware */ + hardware_disable(i); + } + + free_irq(pcmcia_schlvl, NULL); +} + +/* copied from tcic.c */ + +static int m8xx_drv_suspend(struct device *dev, pm_message_t state, u32 level) +{ + int ret = 0; + if (level == SUSPEND_SAVE_STATE) + ret = pcmcia_socket_dev_suspend(dev, state); + return ret; +} + +static int m8xx_drv_resume(struct device *dev, u32 level) +{ + int ret = 0; + if (level == RESUME_RESTORE_STATE) + ret = pcmcia_socket_dev_resume(dev); + return ret; +} + +static struct device_driver m8xx_driver = { + .name = "m8xx-pcmcia", + .bus = &platform_bus_type, + .suspend = m8xx_drv_suspend, + .resume = m8xx_drv_resume, +}; + +static struct platform_device m8xx_device = { + .name = "m8xx-pcmcia", + .id = 0, +}; + +static u32 pending_events[PCMCIA_SOCKETS_NO]; +static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED; + +static irqreturn_t m8xx_interrupt(int irq, void *dev, struct pt_regs *regs) +{ + struct socket_info *s; + struct event_table *e; + unsigned int i, events, pscr, pipr, per; + + dprintk("Interrupt!\n"); + /* get interrupt sources */ + + pscr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr); + pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); + per = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per); + + for(i = 0; i < PCMCIA_SOCKETS_NO; i++) { + s = &socket[i]; + e = &s->events[0]; + events = 0; + + while(e->regbit) { + if(pscr & e->regbit) + events |= e->eventbit; + + e++; + } + + /* + * report only if both card detect signals are the same + * not too nice done, + * we depend on that CD2 is the bit to the left of CD1... + */ + if(events & SS_DETECT) + if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ + (pipr & M8XX_PCMCIA_CD1(i))) + { + events &= ~SS_DETECT; + } + +#ifdef PCMCIA_GLITCHY_CD + /* + * I've experienced CD problems with my ADS board. + * We make an extra check to see if there was a + * real change of Card detection. + */ + + if((events & SS_DETECT) && + ((pipr & + (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && + (s->state.Vcc | s->state.Vpp)) { + events &= ~SS_DETECT; + /*printk( "CD glitch workaround - CD = 0x%08x!\n", + (pipr & (M8XX_PCMCIA_CD2(i) + | M8XX_PCMCIA_CD1(i))));*/ + } +#endif + + /* call the handler */ + + dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, " + "pipr = 0x%08x\n", + i, events, pscr, pipr); + + if(events) { + spin_lock(&pending_event_lock); + pending_events[i] |= events; + spin_unlock(&pending_event_lock); + /* + * Turn off RDY_L bits in the PER mask on + * CD interrupt receival. + * + * They can generate bad interrupts on the + * ACS4,8,16,32. - marcelo + */ + per &= ~M8XX_PCMCIA_RDY_L(0); + per &= ~M8XX_PCMCIA_RDY_L(1); + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, per); + + if (events) + pcmcia_parse_events(&socket[i].socket, events); + } + } + + /* clear the interrupt sources */ + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, pscr); + + dprintk("Interrupt done.\n"); + + return IRQ_HANDLED; +} + +static u32 m8xx_get_graycode(u32 size) +{ + u32 k; + + for(k = 0; k < M8XX_SIZES_NO; k++) + if(m8xx_size_to_gray[k] == size) + break; + + if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) + k = -1; + + return k; +} + +static u32 m8xx_get_speed(u32 ns, u32 is_io) +{ + u32 reg, clocks, psst, psl, psht; + + if(!ns) { + + /* + * We get called with IO maps setup to 0ns + * if not specified by the user. + * They should be 255ns. + */ + + if(is_io) + ns = 255; + else + ns = 100; /* fast memory if 0 */ + } + + /* + * In PSST, PSL, PSHT fields we tell the controller + * timing parameters in CLKOUT clock cycles. + * CLKOUT is the same as GCLK2_50. + */ + +/* how we want to adjust the timing - in percent */ + +#define ADJ 180 /* 80 % longer accesstime - to be sure */ + + clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000; + clocks = (clocks * ADJ) / (100*1000); + if(clocks >= PCMCIA_BMT_LIMIT) { + printk( "Max access time limit reached\n"); + clocks = PCMCIA_BMT_LIMIT-1; + } + + psst = clocks / 7; /* setup time */ + psht = clocks / 7; /* hold time */ + psl = (clocks * 5) / 7; /* strobe length */ + + psst += clocks - (psst + psht + psl); + + reg = psst << 12; + reg |= psl << 7; + reg |= psht << 16; + + return reg; +} + +static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) +{ + int lsock = container_of(sock, struct socket_info, socket)->slot; + struct socket_info *s = &socket[lsock]; + unsigned int pipr, reg; + + pipr = in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr); + + *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) + | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; + *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; + + if (s->state.flags & SS_IOCARD) + *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; + else { + *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; + *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; + *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; + } + + if (s->state.Vcc | s->state.Vpp) + *value |= SS_POWERON; + + /* + * Voltage detection: + * This driver only supports 16-Bit pc-cards. + * Cardbus is not handled here. + * + * To determine what voltage to use we must read the VS1 and VS2 pin. + * Depending on what socket type is present, + * different combinations mean different things. + * + * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse + * + * 5V 5V, LV* NC NC 5V only 5V (if available) + * + * 5V 5V, LV* GND NC 5 or 3.3V as low as possible + * + * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible + * + * LV* 5V - - shall not fit into socket + * + * LV* LV* GND NC 3.3V only 3.3V + * + * LV* LV* NC GND x.xV x.xV (if avail.) + * + * LV* LV* GND GND 3.3 or x.xV as low as possible + * + * *LV means Low Voltage + * + * + * That gives us the following table: + * + * Socket VS1 VS2 Voltage + * + * 5V NC NC 5V + * 5V NC GND none (should not be possible) + * 5V GND NC >= 3.3V + * 5V GND GND >= x.xV + * + * LV NC NC 5V (if available) + * LV NC GND x.xV (if available) + * LV GND NC 3.3V + * LV GND GND >= x.xV + * + * So, how do I determine if I have a 5V or a LV + * socket on my board? Look at the socket! + * + * + * Socket with 5V key: + * ++--------------------------------------------+ + * || | + * || || + * || || + * | | + * +---------------------------------------------+ + * + * Socket with LV key: + * ++--------------------------------------------+ + * || | + * | || + * | || + * | | + * +---------------------------------------------+ + * + * + * With other words - LV only cards does not fit + * into the 5V socket! + */ + + /* read out VS1 and VS2 */ + + reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) + >> M8XX_PCMCIA_VS_SHIFT(lsock); + + if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { + switch(reg) { + case 1: + *value |= SS_3VCARD; + break; /* GND, NC - 3.3V only */ + case 2: + *value |= SS_XVCARD; + break; /* NC. GND - x.xV only */ + }; + } + + dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value); + return 0; +} + +static int m8xx_get_socket(struct pcmcia_socket *sock, socket_state_t *state) +{ + int lsock = container_of(sock, struct socket_info, socket)->slot; + *state = socket[lsock].state; /* copy the whole structure */ + + dprintk("GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, " + "io_irq %d, csc_mask %#2.2x\n", lsock, state->flags, + state->Vcc, state->Vpp, state->io_irq, state->csc_mask); + return 0; +} + +static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state) +{ + int lsock = container_of(sock, struct socket_info, socket)->slot; + struct socket_info *s = &socket[lsock]; + struct event_table *e; + unsigned int reg; + unsigned long flags; + + dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " + "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, + state->Vcc, state->Vpp, state->io_irq, state->csc_mask); + + /* First, set voltage - bail out if invalid */ + if(voltage_set(lsock, state->Vcc, state->Vpp)) + return -EINVAL; + + /* Take care of reset... */ + if(state->flags & SS_RESET) + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ + else + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); + + /* ... and output enable. */ + + /* The CxOE signal is connected to a 74541 on the ADS. + I guess most other boards used the ADS as a reference. + I tried to control the CxOE signal with SS_OUTPUT_ENA, + but the reset signal seems connected via the 541. + If the CxOE is left high are some signals tristated and + no pullups are present -> the cards act wierd. + So right now the buffers are enabled if the power is on. */ + + if(state->Vcc || state->Vpp) + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ + else + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); + + /* + * We'd better turn off interrupts before + * we mess with the events-table.. + */ + + spin_lock_irqsave(&events_lock, flags); + + /* + * Play around with the interrupt mask to be able to + * give the events the generic pcmcia driver wants us to. + */ + + e = &s->events[0]; + reg = 0; + + if(state->csc_mask & SS_DETECT) { + e->eventbit = SS_DETECT; + reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) + | M8XX_PCMCIA_CD1(lsock)); + e++; + } + if(state->flags & SS_IOCARD) { + /* + * I/O card + */ + if(state->csc_mask & SS_STSCHG) { + e->eventbit = SS_STSCHG; + reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); + e++; + } + /* + * If io_irq is non-zero we should enable irq. + */ + if(state->io_irq) { + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(state->io_irq) << 24); + /* + * Strange thing here: + * The manual does not tell us which interrupt + * the sources generate. + * Anyhow, I found out that RDY_L generates IREQLVL. + * + * We use level triggerd interrupts, and they don't + * have to be cleared in PSCR in the interrupt handler. + */ + reg |= M8XX_PCMCIA_RDY_L(lsock); + } + else + out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); + } + else { + /* + * Memory card + */ + if(state->csc_mask & SS_BATDEAD) { + e->eventbit = SS_BATDEAD; + reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); + e++; + } + if(state->csc_mask & SS_BATWARN) { + e->eventbit = SS_BATWARN; + reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); + e++; + } + /* What should I trigger on - low/high,raise,fall? */ + if(state->csc_mask & SS_READY) { + e->eventbit = SS_READY; + reg |= e->regbit = 0; //?? + e++; + } + } + + e->regbit = 0; /* terminate list */ + + /* + * Clear the status changed . + * Port A and Port B share the same port. + * Writing ones will clear the bits. + */ + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, reg); + + /* + * Write the mask. + * Port A and Port B share the same port. + * Need for read-modify-write. + * Ones will enable the interrupt. + */ + + /* + reg |= ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per + & M8XX_PCMCIA_MASK(lsock); + */ + + reg |= in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & + (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, reg); + + spin_unlock_irqrestore(&events_lock, flags); + + /* copy the struct and modify the copy */ + + s->state = *state; + + return 0; +} + +static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) +{ + int lsock = container_of(sock, struct socket_info, socket)->slot; + + struct socket_info *s = &socket[lsock]; + struct pcmcia_win *w; + unsigned int reg, winnr; + +#define M8XX_SIZE (io->stop - io->start + 1) +#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) + + dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, " + "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags, + io->speed, io->start, io->stop); + + if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) + || (io->stop > 0xffff) || (io->stop < io->start)) + return -EINVAL; + + if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) + return -EINVAL; + + if(io->flags & MAP_ACTIVE) { + + dprintk( "io->flags & MAP_ACTIVE\n"); + + winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) + + (lsock * PCMCIA_IO_WIN_NO) + io->map; + + /* setup registers */ + + w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; + w += winnr; + + out_be32(&w->or, 0); /* turn off window first */ + out_be32(&w->br, M8XX_BASE); + + reg <<= 27; + reg |= M8XX_PCMCIA_POR_IO |(lsock << 2); + + reg |= m8xx_get_speed(io->speed, 1); + + if(io->flags & MAP_WRPROT) + reg |= M8XX_PCMCIA_POR_WRPROT; + + /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/ + if(io->flags & MAP_16BIT) + reg |= M8XX_PCMCIA_POR_16BIT; + + if(io->flags & MAP_ACTIVE) + reg |= M8XX_PCMCIA_POR_VALID; + + out_be32(&w->or, reg); + + dprintk("Socket %u: Mapped io window %u at %#8.8x, " + "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); + } else { + /* shutdown IO window */ + winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) + + (lsock * PCMCIA_IO_WIN_NO) + io->map; + + /* setup registers */ + + w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; + w += winnr; + + out_be32(&w->or, 0); /* turn off window */ + out_be32(&w->br, 0); /* turn off base address */ + + dprintk("Socket %u: Unmapped io window %u at %#8.8x, " + "OR = %#8.8x.\n", lsock, io->map, w->br, w->or); + } + + /* copy the struct and modify the copy */ + s->io_win[io->map] = *io; + s->io_win[io->map].flags &= (MAP_WRPROT + | MAP_16BIT + | MAP_ACTIVE); + dprintk("SetIOMap exit\n"); + + return 0; +} + +static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem) +{ + int lsock = container_of(sock, struct socket_info, socket)->slot; + struct socket_info *s = &socket[lsock]; + struct pcmcia_win *w; + struct pccard_mem_map *old; + unsigned int reg, winnr; + + dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, " + "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, + mem->speed, mem->static_start, mem->card_start); + + if ((mem->map >= PCMCIA_MEM_WIN_NO) +// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) + || (mem->card_start >= 0x04000000) + || (mem->static_start & 0xfff) /* 4KByte resolution */ + || (mem->card_start & 0xfff)) + return -EINVAL; + + if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { + printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); + return -EINVAL; + } + reg <<= 27; + + winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; + + /* Setup the window in the pcmcia controller */ + + w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; + w += winnr; + + reg |= lsock << 2; + + reg |= m8xx_get_speed(mem->speed, 0); + + if(mem->flags & MAP_ATTRIB) + reg |= M8XX_PCMCIA_POR_ATTRMEM; + + if(mem->flags & MAP_WRPROT) + reg |= M8XX_PCMCIA_POR_WRPROT; + + if(mem->flags & MAP_16BIT) + reg |= M8XX_PCMCIA_POR_16BIT; + + if(mem->flags & MAP_ACTIVE) + reg |= M8XX_PCMCIA_POR_VALID; + + out_be32(&w->or, reg); + + dprintk("Socket %u: Mapped memory window %u at %#8.8x, " + "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); + + if(mem->flags & MAP_ACTIVE) { + /* get the new base address */ + mem->static_start = PCMCIA_MEM_WIN_BASE + + (PCMCIA_MEM_WIN_SIZE * winnr) + + mem->card_start; + } + + dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, " + "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags, + mem->speed, mem->static_start, mem->card_start); + + /* copy the struct and modify the copy */ + + old = &s->mem_win[mem->map]; + + *old = *mem; + old->flags &= (MAP_ATTRIB + | MAP_WRPROT + | MAP_16BIT + | MAP_ACTIVE); + + return 0; +} + +static int m8xx_sock_init(struct pcmcia_socket *sock) +{ + int i; + pccard_io_map io = { 0, 0, 0, 0, 1 }; + pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; + + dprintk( "sock_init(%d)\n", s); + + m8xx_set_socket(sock, &dead_socket); + for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { + io.map = i; + m8xx_set_io_map(sock, &io); + } + for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { + mem.map = i; + m8xx_set_mem_map(sock, &mem); + } + + return 0; + +} + +static int m8xx_suspend(struct pcmcia_socket *sock) +{ + return m8xx_set_socket(sock, &dead_socket); +} + +static struct pccard_operations m8xx_services = { + .init = m8xx_sock_init, + .suspend = m8xx_suspend, + .get_status = m8xx_get_status, + .get_socket = m8xx_get_socket, + .set_socket = m8xx_set_socket, + .set_io_map = m8xx_set_io_map, + .set_mem_map = m8xx_set_mem_map, +}; + +static int __init m8xx_init(void) +{ + struct pcmcia_win *w; + unsigned int i,m; + + pcmcia_info("%s\n", version); + + if (driver_register(&m8xx_driver)) + return -1; + + pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG + " with IRQ %u.\n", pcmcia_schlvl); + + /* Configure Status change interrupt */ + + if(request_irq(pcmcia_schlvl, m8xx_interrupt, 0, + "m8xx_pcmcia", NULL)) { + pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", + pcmcia_schlvl); + return -1; + } + + w = (void *) &((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0; + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr, + M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1)); + + out_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per, + in_be32(&((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_per) & + ~(M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1))); + +/* connect interrupt and disable CxOE */ + + out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); + out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(pcmcia_schlvl) << 16)); + +/* intialize the fixed memory windows */ + + for(i = 0; i < PCMCIA_SOCKETS_NO; i++){ + for(m = 0; m < PCMCIA_MEM_WIN_NO; m++) { + out_be32(&w->br, PCMCIA_MEM_WIN_BASE + + (PCMCIA_MEM_WIN_SIZE + * (m + i * PCMCIA_MEM_WIN_NO))); + + out_be32(&w->or, 0); /* set to not valid */ + + w++; + } + } + +/* turn off voltage */ + voltage_set(0, 0, 0); + voltage_set(1, 0, 0); + +/* Enable external hardware */ + hardware_enable(0); + hardware_enable(1); + + platform_device_register(&m8xx_device); + + for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) { + socket[i].slot = i; + socket[i].socket.owner = THIS_MODULE; + socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; + socket[i].socket.irq_mask = 0x000; + socket[i].socket.map_size = 0x1000; + socket[i].socket.io_offset = 0; + socket[i].socket.pci_irq = i ? 7 : 9; + socket[i].socket.ops = &m8xx_services; + socket[i].socket.resource_ops = &pccard_nonstatic_ops; + socket[i].socket.cb_dev = NULL; + socket[i].socket.dev.dev = &m8xx_device.dev; + } + + for (i = 0; i < PCMCIA_SOCKETS_NO; i++) + pcmcia_register_socket(&socket[i].socket); + + return 0; +} + +static void __exit m8xx_exit(void) +{ + int i; + + for (i = 0; i < PCMCIA_SOCKETS_NO; i++) + pcmcia_unregister_socket(&socket[i].socket); + + m8xx_shutdown(); + + platform_device_unregister(&m8xx_device); + driver_unregister(&m8xx_driver); +} + +module_init(m8xx_init); +module_exit(m8xx_exit); -- cgit v1.2.3-70-g09d2 From 8b150478aeb1a8edb9015c2f7ac4da637ff65c45 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Fri, 28 Oct 2005 17:46:18 -0700 Subject: [PATCH] ppc: make phys_mem_access_prot() work with pfns instead of addresses Change the phys_mem_access_prot() function to take a pfn instead of an address. This allows mmap64() to work on /dev/mem for addresses above 4G on 32-bit architectures. We start with a pfn in mmap_mem(), so there's no need to convert to an address; in fact, it's actively bad, since the conversion can overflow when the address is above 4G. Similarly fix the ppc32 page_is_ram() function to avoid a conversion to an address by directly comparing to max_pfn. Working with max_pfn instead of high_memory fixes page_is_ram() to give the right answer for highmem pages. Signed-off-by: Roland Dreier Cc: Anton Blanchard Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- arch/powerpc/mm/mem.c | 6 +++--- arch/ppc/kernel/pci.c | 5 +++-- arch/ppc/mm/init.c | 10 ++++------ arch/ppc64/kernel/pci.c | 5 +++-- drivers/char/mem.c | 4 +--- drivers/video/fbmem.c | 2 +- include/asm-powerpc/machdep.h | 2 +- include/asm-ppc/machdep.h | 2 +- include/asm-ppc/pci.h | 2 +- include/asm-ppc/pgtable.h | 2 +- include/asm-ppc64/pci.h | 2 +- include/asm-ppc64/pgtable.h | 2 +- 12 files changed, 21 insertions(+), 23 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index 695db6a588c..3ca331728d2 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -88,13 +88,13 @@ int page_is_ram(unsigned long pfn) } EXPORT_SYMBOL(page_is_ram); -pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, +pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { if (ppc_md.phys_mem_access_prot) - return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot); + return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot); - if (!page_is_ram(addr >> PAGE_SHIFT)) + if (!page_is_ram(pfn)) vma_prot = __pgprot(pgprot_val(vma_prot) | _PAGE_GUARDED | _PAGE_NO_CACHE); return vma_prot; diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c index ad4ef2aaa6a..e8f4e576750 100644 --- a/arch/ppc/kernel/pci.c +++ b/arch/ppc/kernel/pci.c @@ -1594,16 +1594,17 @@ static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, * above routine */ pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t protection) { struct pci_dev *pdev = NULL; struct resource *found = NULL; unsigned long prot = pgprot_val(protection); + unsigned long offset = pfn << PAGE_SHIFT; int i; - if (page_is_ram(offset >> PAGE_SHIFT)) + if (page_is_ram(pfn)) return prot; prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; diff --git a/arch/ppc/mm/init.c b/arch/ppc/mm/init.c index db94efd2536..99b48abd329 100644 --- a/arch/ppc/mm/init.c +++ b/arch/ppc/mm/init.c @@ -637,18 +637,16 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, */ int page_is_ram(unsigned long pfn) { - unsigned long paddr = (pfn << PAGE_SHIFT); - - return paddr < __pa(high_memory); + return pfn < max_pfn; } -pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, +pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot) { if (ppc_md.phys_mem_access_prot) - return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot); + return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot); - if (!page_is_ram(addr >> PAGE_SHIFT)) + if (!page_is_ram(pfn)) vma_prot = __pgprot(pgprot_val(vma_prot) | _PAGE_GUARDED | _PAGE_NO_CACHE); return vma_prot; diff --git a/arch/ppc64/kernel/pci.c b/arch/ppc64/kernel/pci.c index b2fb6746f00..3d2106b022a 100644 --- a/arch/ppc64/kernel/pci.c +++ b/arch/ppc64/kernel/pci.c @@ -726,16 +726,17 @@ static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, * above routine */ pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t protection) { struct pci_dev *pdev = NULL; struct resource *found = NULL; unsigned long prot = pgprot_val(protection); + unsigned long offset = pfn << PAGE_SHIFT; int i; - if (page_is_ram(offset >> PAGE_SHIFT)) + if (page_is_ram(pfn)) return __pgprot(prot); prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; diff --git a/drivers/char/mem.c b/drivers/char/mem.c index f182752fe91..9df928d4f68 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -231,9 +231,7 @@ static ssize_t write_mem(struct file * file, const char __user * buf, static int mmap_mem(struct file * file, struct vm_area_struct * vma) { #if defined(__HAVE_PHYS_MEM_ACCESS_PROT) - unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; - - vma->vm_page_prot = phys_mem_access_prot(file, offset, + vma->vm_page_prot = phys_mem_access_prot(file, vma->vm_pgoff, vma->vm_end - vma->vm_start, vma->vm_page_prot); #elif defined(pgprot_noncached) diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 70be7009f8a..ca02aa2bfce 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -918,7 +918,7 @@ fb_mmap(struct file *file, struct vm_area_struct * vma) } #endif #elif defined(__powerpc__) - vma->vm_page_prot = phys_mem_access_prot(file, off, + vma->vm_page_prot = phys_mem_access_prot(file, off >> PAGE_SHIFT, vma->vm_end - vma->vm_start, vma->vm_page_prot); #elif defined(__alpha__) diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h index 706508b1b04..451b345cfc7 100644 --- a/include/asm-powerpc/machdep.h +++ b/include/asm-powerpc/machdep.h @@ -144,7 +144,7 @@ struct machdep_calls { /* Get access protection for /dev/mem */ pgprot_t (*phys_mem_access_prot)(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t vma_prot); diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h index 6c6d23abbe9..f01255bd1dc 100644 --- a/include/asm-ppc/machdep.h +++ b/include/asm-ppc/machdep.h @@ -98,7 +98,7 @@ struct machdep_calls { /* Get access protection for /dev/mem */ pgprot_t (*phys_mem_access_prot)(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t vma_prot); diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index 643740dd727..61434edbad7 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev); struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t prot); diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index eee601bb9ad..b28a713ba86 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -705,7 +705,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) struct file; -extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, +extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot); #define __HAVE_PHYS_MEM_ACCESS_PROT diff --git a/include/asm-ppc64/pci.h b/include/asm-ppc64/pci.h index a88bbfc2696..342e2d75555 100644 --- a/include/asm-ppc64/pci.h +++ b/include/asm-ppc64/pci.h @@ -168,7 +168,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev); struct file; extern pgprot_t pci_phys_mem_access_prot(struct file *file, - unsigned long offset, + unsigned long pfn, unsigned long size, pgprot_t prot); diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index c83679c9d2b..8cf5991540e 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -471,7 +471,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty) #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) struct file; -extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, +extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, unsigned long size, pgprot_t vma_prot); #define __HAVE_PHYS_MEM_ACCESS_PROT -- cgit v1.2.3-70-g09d2 From dcb34abb4d9bae0588c5c11101ed6afcee71f895 Mon Sep 17 00:00:00 2001 From: "scwhab@suse.de" Date: Fri, 28 Oct 2005 17:46:20 -0700 Subject: [PATCH] Add modalias to macio sysfs attributes Provide a "compatible" entry in /sys/bus/macio/devices/*/ This can be used to load drivers via the modules.alias file. Signed-off-by: Olaf Hering Acked-by: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- drivers/macintosh/macio_sysfs.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'drivers') diff --git a/drivers/macintosh/macio_sysfs.c b/drivers/macintosh/macio_sysfs.c index 97d22bb4516..7f7d4eaca87 100644 --- a/drivers/macintosh/macio_sysfs.c +++ b/drivers/macintosh/macio_sysfs.c @@ -39,6 +39,31 @@ compatible_show (struct device *dev, struct device_attribute *attr, char *buf) return length; } +static ssize_t modalias_show (struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct of_device *of; + char *compat; + int cplen; + int length; + + of = &to_macio_device (dev)->ofdev; + compat = (char *) get_property (of->node, "compatible", &cplen); + if (!compat) compat = "", cplen = 1; + length = sprintf (buf, "of:N%sT%s", of->node->name, of->node->type); + buf += length; + while (cplen > 0) { + int l; + length += sprintf (buf, "C%s", compat); + buf += length; + l = strlen (compat) + 1; + compat += l; + cplen -= l; + } + + return length; +} + macio_config_of_attr (name, "%s\n"); macio_config_of_attr (type, "%s\n"); @@ -46,5 +71,6 @@ struct device_attribute macio_dev_attrs[] = { __ATTR_RO(name), __ATTR_RO(type), __ATTR_RO(compatible), + __ATTR_RO(modalias), __ATTR_NULL }; -- cgit v1.2.3-70-g09d2 From 8c9795ba01d02b043ce2d9eeb0fa908c07e5fb42 Mon Sep 17 00:00:00 2001 From: Olaf Hering Date: Fri, 28 Oct 2005 17:46:21 -0700 Subject: [PATCH] Add modalias for pmac network drivers mesh, mac53c94 and airport already have an entry. Add the network drivers for pmac. Signed-off-by: Olaf Hering Acked-by: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- drivers/net/bmac.c | 1 + drivers/net/mace.c | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/bmac.c b/drivers/net/bmac.c index 60dba4a1ca5..0ee28899fb8 100644 --- a/drivers/net/bmac.c +++ b/drivers/net/bmac.c @@ -1658,6 +1658,7 @@ static struct of_device_id bmac_match[] = }, {}, }; +MODULE_DEVICE_TABLE (of, bmac_match); static struct macio_driver bmac_driver = { diff --git a/drivers/net/mace.c b/drivers/net/mace.c index 81d0a26e4f4..f2fc1f26cd4 100644 --- a/drivers/net/mace.c +++ b/drivers/net/mace.c @@ -1016,6 +1016,7 @@ static struct of_device_id mace_match[] = }, {}, }; +MODULE_DEVICE_TABLE (of, mace_match); static struct macio_driver mace_driver = { -- cgit v1.2.3-70-g09d2 From b1529871f4270d10a0d1a9c998be162f0123d8f1 Mon Sep 17 00:00:00 2001 From: Nicolas DET Date: Fri, 28 Oct 2005 17:46:30 -0700 Subject: [PATCH] mv643xx_eth_showsram: Added information message when using the SRAM Added information message when using the SRAM in mv643xx_eth_probe() Signed-off-by: Nicolas DET Signed-off-by: Sven Luther Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- drivers/net/mv643xx_eth.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 25c9a99c377..8fbba21d975 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -1533,6 +1533,9 @@ static int mv643xx_eth_probe(struct device *ddev) printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name); #endif + if (mp->tx_sram_size > 0) + printk(KERN_NOTICE "%s: Using SRAM\n", dev->name); + return 0; out: -- cgit v1.2.3-70-g09d2 From 08124f958997ac14bb2284af787752125a892e9f Mon Sep 17 00:00:00 2001 From: Olaf Hering Date: Fri, 28 Oct 2005 17:46:51 -0700 Subject: [PATCH] ppc64: AC Power handling broken for desktops Currently, AC Power is 0 on a desktop G4. No batteries present should mean AC Power == 1. Signed-off-by: Olaf Hering Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Paul Mackerras --- drivers/macintosh/apm_emu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/macintosh/apm_emu.c b/drivers/macintosh/apm_emu.c index 19d3e05d682..e5a2bbf9939 100644 --- a/drivers/macintosh/apm_emu.c +++ b/drivers/macintosh/apm_emu.c @@ -430,8 +430,8 @@ static int apm_emu_get_info(char *buf, char **start, off_t fpos, int length) -1: Unknown 8) min = minutes; sec = seconds */ - unsigned short ac_line_status = 0xff; - unsigned short battery_status = 0xff; + unsigned short ac_line_status; + unsigned short battery_status = 0; unsigned short battery_flag = 0xff; int percentage = -1; int time_units = -1; @@ -446,6 +446,7 @@ static int apm_emu_get_info(char *buf, char **start, off_t fpos, int length) ac_line_status = ((pmu_power_flags & PMU_PWR_AC_PRESENT) != 0); for (i=0; i Date: Sat, 29 Oct 2005 07:39:42 -0700 Subject: [IB] mthca: report asynchronous CQ events Implement reporting asynchronous CQ events in Mellanox HCA driver. Signed-off-by: Michael S. Tsirkin Signed-off-by: Roland Dreier --- drivers/infiniband/hw/mthca/mthca_cq.c | 31 ++++++++++++++++++++++++++++++- drivers/infiniband/hw/mthca/mthca_dev.h | 4 +++- drivers/infiniband/hw/mthca/mthca_eq.c | 4 +++- 3 files changed, 36 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/infiniband/hw/mthca/mthca_cq.c b/drivers/infiniband/hw/mthca/mthca_cq.c index 8600b6c3e0c..f98e2355582 100644 --- a/drivers/infiniband/hw/mthca/mthca_cq.c +++ b/drivers/infiniband/hw/mthca/mthca_cq.c @@ -208,7 +208,7 @@ static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq, } } -void mthca_cq_event(struct mthca_dev *dev, u32 cqn) +void mthca_cq_completion(struct mthca_dev *dev, u32 cqn) { struct mthca_cq *cq; @@ -224,6 +224,35 @@ void mthca_cq_event(struct mthca_dev *dev, u32 cqn) cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); } +void mthca_cq_event(struct mthca_dev *dev, u32 cqn, + enum ib_event_type event_type) +{ + struct mthca_cq *cq; + struct ib_event event; + + spin_lock(&dev->cq_table.lock); + + cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1)); + + if (cq) + atomic_inc(&cq->refcount); + spin_unlock(&dev->cq_table.lock); + + if (!cq) { + mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn); + return; + } + + event.device = &dev->ib_dev; + event.event = event_type; + event.element.cq = &cq->ibcq; + if (cq->ibcq.event_handler) + cq->ibcq.event_handler(&event, cq->ibcq.cq_context); + + if (atomic_dec_and_test(&cq->refcount)) + wake_up(&cq->wait); +} + void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn, struct mthca_srq *srq) { diff --git a/drivers/infiniband/hw/mthca/mthca_dev.h b/drivers/infiniband/hw/mthca/mthca_dev.h index 7e68bd4a378..e7e5d3b4f00 100644 --- a/drivers/infiniband/hw/mthca/mthca_dev.h +++ b/drivers/infiniband/hw/mthca/mthca_dev.h @@ -460,7 +460,9 @@ int mthca_init_cq(struct mthca_dev *dev, int nent, struct mthca_cq *cq); void mthca_free_cq(struct mthca_dev *dev, struct mthca_cq *cq); -void mthca_cq_event(struct mthca_dev *dev, u32 cqn); +void mthca_cq_completion(struct mthca_dev *dev, u32 cqn); +void mthca_cq_event(struct mthca_dev *dev, u32 cqn, + enum ib_event_type event_type); void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn, struct mthca_srq *srq); diff --git a/drivers/infiniband/hw/mthca/mthca_eq.c b/drivers/infiniband/hw/mthca/mthca_eq.c index e5a047a6dbe..34d68e5a72d 100644 --- a/drivers/infiniband/hw/mthca/mthca_eq.c +++ b/drivers/infiniband/hw/mthca/mthca_eq.c @@ -292,7 +292,7 @@ static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) case MTHCA_EVENT_TYPE_COMP: disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; disarm_cq(dev, eq->eqn, disarm_cqn); - mthca_cq_event(dev, disarm_cqn); + mthca_cq_completion(dev, disarm_cqn); break; case MTHCA_EVENT_TYPE_PATH_MIG: @@ -364,6 +364,8 @@ static int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) eqe->event.cq_err.syndrome == 1 ? "overrun" : "access violation", be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); + mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn), + IB_EVENT_CQ_ERR); break; case MTHCA_EVENT_TYPE_EQ_OVERFLOW: -- cgit v1.2.3-70-g09d2 From d052d1beff706920e82c5d55006b08e256b5df09 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 29 Oct 2005 19:07:23 +0100 Subject: Create platform_device.h to contain all the platform device details. Convert everyone who uses platform_bus_type to include linux/platform_device.h. Signed-off-by: Russell King Acked-by: Greg Kroah-Hartman --- arch/arm/common/locomo.c | 2 +- arch/arm/common/sa1111.c | 2 +- arch/arm/common/scoop.c | 2 +- arch/arm/mach-aaec2000/core.c | 2 +- arch/arm/mach-h720x/h7202-eval.c | 2 +- arch/arm/mach-imx/generic.c | 2 +- arch/arm/mach-imx/mx1ads.c | 1 + arch/arm/mach-integrator/integrator_ap.c | 2 +- arch/arm/mach-integrator/integrator_cp.c | 2 +- arch/arm/mach-iop3xx/iop321-setup.c | 2 +- arch/arm/mach-iop3xx/iop331-setup.c | 2 +- arch/arm/mach-ixp2000/enp2611.c | 2 +- arch/arm/mach-ixp2000/ixdp2x00.c | 2 +- arch/arm/mach-ixp2000/ixdp2x01.c | 2 +- arch/arm/mach-ixp4xx/common.c | 1 + arch/arm/mach-lh7a40x/arch-lpd7a40x.c | 2 +- arch/arm/mach-omap1/board-h2.c | 2 +- arch/arm/mach-omap1/board-h3.c | 2 +- arch/arm/mach-omap1/board-innovator.c | 2 +- arch/arm/mach-omap1/board-netstar.c | 2 +- arch/arm/mach-omap1/board-osk.c | 2 +- arch/arm/mach-omap1/board-perseus2.c | 2 +- arch/arm/mach-omap1/board-voiceblue.c | 2 +- arch/arm/mach-omap1/devices.c | 2 +- arch/arm/mach-pxa/corgi.c | 2 +- arch/arm/mach-pxa/corgi_lcd.c | 2 +- arch/arm/mach-pxa/corgi_ssp.c | 2 +- arch/arm/mach-pxa/generic.c | 2 +- arch/arm/mach-pxa/idp.c | 2 +- arch/arm/mach-pxa/lubbock.c | 2 +- arch/arm/mach-pxa/mainstone.c | 2 +- arch/arm/mach-pxa/poodle.c | 2 +- arch/arm/mach-pxa/pxa27x.c | 2 +- arch/arm/mach-pxa/spitz.c | 2 +- arch/arm/mach-s3c2410/clock.c | 2 +- arch/arm/mach-s3c2410/cpu.c | 2 +- arch/arm/mach-s3c2410/devs.c | 2 +- arch/arm/mach-s3c2410/devs.h | 1 + arch/arm/mach-s3c2410/mach-anubis.c | 2 +- arch/arm/mach-s3c2410/mach-bast.c | 2 +- arch/arm/mach-s3c2410/mach-h1940.c | 1 + arch/arm/mach-s3c2410/mach-n30.c | 2 +- arch/arm/mach-s3c2410/mach-nexcoder.c | 2 +- arch/arm/mach-s3c2410/mach-otom.c | 2 +- arch/arm/mach-s3c2410/mach-rx3715.c | 1 + arch/arm/mach-s3c2410/mach-smdk2410.c | 1 + arch/arm/mach-s3c2410/mach-smdk2440.c | 1 + arch/arm/mach-s3c2410/s3c2410.c | 2 +- arch/arm/mach-s3c2410/s3c2440.c | 2 +- arch/arm/mach-sa1100/badge4.c | 2 +- arch/arm/mach-sa1100/cerf.c | 2 +- arch/arm/mach-sa1100/collie.c | 2 +- arch/arm/mach-sa1100/generic.c | 1 + arch/arm/mach-sa1100/jornada720.c | 2 +- arch/arm/mach-sa1100/neponset.c | 2 +- arch/arm/mach-sa1100/pleb.c | 2 +- arch/arm/mach-sa1100/simpad.c | 2 +- arch/arm/mach-versatile/core.c | 1 + arch/arm/plat-omap/usb.c | 2 +- arch/m32r/kernel/setup_m32700ut.c | 2 +- arch/m32r/kernel/setup_mappi.c | 2 +- arch/m32r/kernel/setup_mappi2.c | 2 +- arch/m32r/kernel/setup_mappi3.c | 2 +- arch/m32r/kernel/setup_opsput.c | 2 +- arch/mips/au1000/common/platform.c | 2 +- arch/ppc/platforms/4xx/ibm440ep.c | 1 + arch/ppc/platforms/4xx/ibmstb4.c | 1 + arch/ppc/platforms/4xx/redwood5.c | 2 +- arch/ppc/platforms/4xx/redwood6.c | 2 +- arch/ppc/platforms/chrp_pegasos_eth.c | 2 +- arch/ppc/platforms/cpci690.c | 1 + arch/ppc/platforms/ev64260.c | 1 + arch/ppc/platforms/ev64360.c | 1 + arch/ppc/platforms/hdpu.c | 1 + arch/ppc/platforms/katana.c | 1 + arch/ppc/platforms/radstone_ppc7d.c | 1 + arch/ppc/syslib/mpc52xx_devices.c | 1 + arch/ppc/syslib/mv64x60.c | 1 + arch/ppc/syslib/pq2_devices.c | 2 +- arch/sh/boards/superh/microdev/setup.c | 2 +- arch/um/drivers/net_kern.c | 1 + arch/um/drivers/ubd_kern.c | 1 + arch/xtensa/platform-iss/network.c | 1 + drivers/base/platform.c | 2 +- drivers/block/floppy.c | 2 +- drivers/char/s3c2410-rtc.c | 2 +- drivers/char/sonypi.c | 1 + drivers/char/tb0219.c | 2 +- drivers/char/vr41xx_giu.c | 2 +- drivers/char/vr41xx_rtc.c | 2 +- drivers/char/watchdog/mpcore_wdt.c | 2 +- drivers/char/watchdog/mv64x60_wdt.c | 2 ++ drivers/char/watchdog/s3c2410_wdt.c | 2 +- drivers/eisa/virtual_root.c | 2 +- drivers/firmware/dcdbas.c | 2 +- drivers/firmware/dell_rbu.c | 2 +- drivers/hwmon/hdaps.c | 2 +- drivers/i2c/busses/i2c-iop3xx.c | 2 +- drivers/i2c/busses/i2c-isa.c | 1 + drivers/i2c/busses/i2c-ixp2000.c | 2 +- drivers/i2c/busses/i2c-ixp4xx.c | 2 +- drivers/i2c/busses/i2c-mpc.c | 2 ++ drivers/i2c/busses/i2c-mv64xxx.c | 2 ++ drivers/i2c/busses/i2c-pxa.c | 1 + drivers/i2c/busses/i2c-s3c2410.c | 2 +- drivers/i2c/chips/isp1301_omap.c | 2 +- drivers/i2c/i2c-core.c | 1 + drivers/i2c/i2c-dev.c | 1 + drivers/input/keyboard/corgikbd.c | 2 +- drivers/input/keyboard/spitzkbd.c | 2 +- drivers/input/serio/ct82c710.c | 1 + drivers/input/serio/i8042.c | 1 + drivers/input/serio/maceps2.c | 2 +- drivers/input/serio/q40kbd.c | 1 + drivers/input/serio/rpckbd.c | 1 + drivers/input/touchscreen/corgi_ts.c | 2 +- drivers/mfd/mcp-sa11x0.c | 2 +- drivers/misc/hdpuftrs/hdpu_cpustate.c | 2 +- drivers/misc/hdpuftrs/hdpu_nexus.c | 2 +- drivers/mmc/pxamci.c | 2 +- drivers/mmc/wbsd.c | 2 +- drivers/mtd/maps/bast-flash.c | 2 +- drivers/mtd/maps/integrator-flash.c | 2 +- drivers/mtd/maps/ixp2000.c | 2 +- drivers/mtd/maps/ixp4xx.c | 2 +- drivers/mtd/maps/omap_nor.c | 2 +- drivers/mtd/maps/plat-ram.c | 2 +- drivers/mtd/maps/sa1100-flash.c | 2 +- drivers/mtd/nand/s3c2410.c | 2 +- drivers/net/depca.c | 2 +- drivers/net/dm9000.c | 1 + drivers/net/gianfar.c | 2 +- drivers/net/gianfar_mii.c | 1 + drivers/net/irda/pxaficp_ir.c | 1 + drivers/net/irda/sa1100_ir.c | 2 +- drivers/net/irda/smsc-ircc2.c | 1 + drivers/net/jazzsonic.c | 2 +- drivers/net/macsonic.c | 2 +- drivers/net/mipsnet.c | 1 + drivers/net/mv643xx_eth.c | 2 ++ drivers/net/smc91x.c | 2 +- drivers/net/tokenring/proteon.c | 1 + drivers/net/tokenring/skisa.c | 1 + drivers/pcmcia/au1000_generic.c | 2 +- drivers/pcmcia/hd64465_ss.c | 2 +- drivers/pcmcia/i82365.c | 2 +- drivers/pcmcia/m32r_cfc.c | 2 +- drivers/pcmcia/m32r_pcc.c | 2 +- drivers/pcmcia/omap_cf.c | 2 +- drivers/pcmcia/pxa2xx_base.c | 1 + drivers/pcmcia/pxa2xx_mainstone.c | 2 +- drivers/pcmcia/pxa2xx_sharpsl.c | 2 +- drivers/pcmcia/sa1100_generic.c | 1 + drivers/pcmcia/tcic.c | 2 +- drivers/pcmcia/vrc4171_card.c | 1 + drivers/scsi/hosts.c | 1 + drivers/serial/8250.c | 2 +- drivers/serial/imx.c | 2 +- drivers/serial/mpc52xx_uart.c | 2 +- drivers/serial/mpsc.c | 2 ++ drivers/serial/pxa.c | 2 +- drivers/serial/s3c2410.c | 2 +- drivers/serial/sa1100.c | 2 +- drivers/serial/vr41xx_siu.c | 2 +- drivers/usb/gadget/dummy_hcd.c | 2 +- drivers/usb/gadget/lh7a40x_udc.c | 2 ++ drivers/usb/gadget/omap_udc.c | 2 +- drivers/usb/gadget/pxa2xx_udc.c | 2 +- drivers/usb/host/isp116x-hcd.c | 1 + drivers/usb/host/ohci-au1xxx.c | 2 ++ drivers/usb/host/ohci-lh7a404.c | 2 ++ drivers/usb/host/ohci-omap.c | 2 ++ drivers/usb/host/ohci-ppc-soc.c | 2 ++ drivers/usb/host/ohci-pxa27x.c | 2 +- drivers/usb/host/ohci-s3c2410.c | 2 ++ drivers/usb/host/sl811-hcd.c | 1 + drivers/usb/host/sl811_cs.c | 1 + drivers/video/acornfb.c | 2 +- drivers/video/arcfb.c | 1 + drivers/video/backlight/corgi_bl.c | 2 +- drivers/video/dnfb.c | 2 ++ drivers/video/epson1355fb.c | 2 ++ drivers/video/gbefb.c | 2 +- drivers/video/imxfb.c | 2 +- drivers/video/pxafb.c | 2 +- drivers/video/q40fb.c | 1 + drivers/video/s1d13xxxfb.c | 2 +- drivers/video/s3c2410fb.c | 1 + drivers/video/sa1100fb.c | 2 +- drivers/video/sgivwfb.c | 2 ++ drivers/video/vesafb.c | 2 ++ drivers/video/vfb.c | 2 ++ drivers/video/w100fb.c | 2 +- include/asm-ppc/ppc_sys.h | 2 +- include/linux/device.h | 26 -------------------------- include/linux/serial_8250.h | 2 +- sound/arm/pxa2xx-ac97.c | 2 +- sound/core/init.c | 2 ++ 198 files changed, 214 insertions(+), 158 deletions(-) (limited to 'drivers') diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 5cdb4122f05..ad55680726e 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 21e2a518ad3..174aa86ee81 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index e8356b76d7c..68b06d16f25 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -11,7 +11,7 @@ * */ -#include +#include #include #include diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c index 0c53dab8090..4e706d9ad36 100644 --- a/arch/arm/mach-aaec2000/core.c +++ b/arch/arm/mach-aaec2000/core.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c index db9078ad008..d75c8221d2a 100644 --- a/arch/arm/mach-h720x/h7202-eval.c +++ b/arch/arm/mach-h720x/h7202-eval.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c index cb14b0682ce..60e2361e98e 100644 --- a/arch/arm/mach-imx/generic.c +++ b/arch/arm/mach-imx/generic.c @@ -22,7 +22,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */ -#include +#include #include #include #include diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c index 4cbdc1fe04b..708e1b3faa1 100644 --- a/arch/arm/mach-imx/mx1ads.c +++ b/arch/arm/mach-imx/mx1ads.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index f368b85f044..1f9061ca7ef 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index aa34c58b96c..93f7ccb22c2 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-iop3xx/iop321-setup.c b/arch/arm/mach-iop3xx/iop321-setup.c index bb5091223b6..80770233b8d 100644 --- a/arch/arm/mach-iop3xx/iop321-setup.c +++ b/arch/arm/mach-iop3xx/iop321-setup.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-iop3xx/iop331-setup.c b/arch/arm/mach-iop3xx/iop331-setup.c index a2533c3ab42..53f60614498 100644 --- a/arch/arm/mach-iop3xx/iop331-setup.c +++ b/arch/arm/mach-iop3xx/iop331-setup.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c index 9aa54de4474..643f5e1c3d9 100644 --- a/arch/arm/mach-ixp2000/enp2611.c +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c index 8b4a839b627..05dfcb48c2b 100644 --- a/arch/arm/mach-ixp2000/ixdp2x00.c +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c index fee1d7b7350..b21249908ae 100644 --- a/arch/arm/mach-ixp2000/ixdp2x01.c +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c index 6c396447c4e..f3c687cf007 100644 --- a/arch/arm/mach-ixp4xx/common.c +++ b/arch/arm/mach-ixp4xx/common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c index a20eabc132b..4eb962fdb3a 100644 --- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c +++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index d46a70063b0..4ee6bd8a50b 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 2798613696f..fc824361430 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index fd9183ff2ed..a2eac853b2d 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-netstar.c b/arch/arm/mach-omap1/board-netstar.c index d904e643f5e..c851c2e4dfc 100644 --- a/arch/arm/mach-omap1/board-netstar.c +++ b/arch/arm/mach-omap1/board-netstar.c @@ -11,7 +11,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 21103df5041..a88524e7c31 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c index 2ba26e23910..354b157acb3 100644 --- a/arch/arm/mach-omap1/board-perseus2.c +++ b/arch/arm/mach-omap1/board-perseus2.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index bf30b1acda0..3f018b29686 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c @@ -13,7 +13,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index e8b3981444c..3c5d901efea 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 60c8b9d8bb9..247147f29b9 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index 370df113dc0..54162ba9541 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 136c269db0b..591e5f32dbe 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 3248bc9b949..afd5063b0eb 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 01a83ab09ac..7de159e2ab4 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index beccf455f79..1f6857d7747 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a48c64026e1..887a8cb7b72 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index f2563881001..86326307ab9 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -16,7 +16,7 @@ */ #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 09a5d593f04..c722a9a91fc 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index d0ab428c2d7..4182ddf330d 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index 8b3d5dc35de..82e8253b1fa 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c index ca366e9e264..687fe371369 100644 --- a/arch/arm/mach-s3c2410/cpu.c +++ b/arch/arm/mach-s3c2410/cpu.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c index 08bc7d95a45..f58406e6ef5 100644 --- a/arch/arm/mach-s3c2410/devs.c +++ b/arch/arm/mach-s3c2410/devs.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/devs.h b/arch/arm/mach-s3c2410/devs.h index d6328f96728..52c4bab5c76 100644 --- a/arch/arm/mach-s3c2410/devs.h +++ b/arch/arm/mach-s3c2410/devs.h @@ -15,6 +15,7 @@ * 10-Feb-2005 BJD Added camera from guillaume.gourat@nexvision.tv */ #include +#include extern struct platform_device *s3c24xx_uart_devs[]; diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c index 5ae80f4e3e6..8390b685c2b 100644 --- a/arch/arm/mach-s3c2410/mach-anubis.c +++ b/arch/arm/mach-s3c2410/mach-anubis.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index c1b5c63ec24..0b71c896bbd 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 7efeaaad236..0aa8760598f 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 5c0f2b091f9..378d640ab00 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-nexcoder.c b/arch/arm/mach-s3c2410/mach-nexcoder.c index c22f8216032..42b0eeff2e0 100644 --- a/arch/arm/mach-s3c2410/mach-nexcoder.c +++ b/arch/arm/mach-s3c2410/mach-nexcoder.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index ad1459e402e..a2eb9ed48fc 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c index 22d9e070fd6..8f2a90bf940 100644 --- a/arch/arm/mach-s3c2410/mach-rx3715.c +++ b/arch/arm/mach-s3c2410/mach-rx3715.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 2eda55a6b67..2c91965ee1c 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c index 6950e61b791..d666c621ad0 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2440.c +++ b/arch/arm/mach-s3c2410/mach-smdk2440.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index a8bf5ec8260..0a2013a7654 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c index 833fa36bce0..4d63e7133b4 100644 --- a/arch/arm/mach-s3c2410/s3c2440.c +++ b/arch/arm/mach-s3c2410/s3c2440.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index c92cebff7f8..edccd5eb06b 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index 23cb7488527..508593722bc 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 7fd6e29c36b..522abc036d3 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index 93619497779..976380bde41 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 9c363bfcf31..9fb65cffa57 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 052e4caedb8..69f1970646c 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c index e17b58fb9c9..58c18f9e9b7 100644 --- a/arch/arm/mach-sa1100/pleb.c +++ b/arch/arm/mach-sa1100/pleb.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c index cfb6658e5cd..439ddc9b06d 100644 --- a/arch/arm/mach-sa1100/simpad.c +++ b/arch/arm/mach-sa1100/simpad.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 7e4bdd07f4a..a1ca46630dd 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index 14a836d7ac2..205e2d0b826 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/m32r/kernel/setup_m32700ut.c b/arch/m32r/kernel/setup_m32700ut.c index 708634b685e..cb76916b014 100644 --- a/arch/m32r/kernel/setup_m32700ut.c +++ b/arch/m32r/kernel/setup_m32700ut.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/m32r/kernel/setup_mappi.c b/arch/m32r/kernel/setup_mappi.c index 4e709809efc..501d798cf05 100644 --- a/arch/m32r/kernel/setup_mappi.c +++ b/arch/m32r/kernel/setup_mappi.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/m32r/kernel/setup_mappi2.c b/arch/m32r/kernel/setup_mappi2.c index a1d801598aa..7f2db5bfd62 100644 --- a/arch/m32r/kernel/setup_mappi2.c +++ b/arch/m32r/kernel/setup_mappi2.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/m32r/kernel/setup_mappi3.c b/arch/m32r/kernel/setup_mappi3.c index a76412e883e..9c79341a7b4 100644 --- a/arch/m32r/kernel/setup_mappi3.c +++ b/arch/m32r/kernel/setup_mappi3.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/m32r/kernel/setup_opsput.c b/arch/m32r/kernel/setup_opsput.c index d7b7ec6d30f..1fbb140854e 100644 --- a/arch/m32r/kernel/setup_opsput.c +++ b/arch/m32r/kernel/setup_opsput.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 0776b2db564..3c778d0f58a 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -7,7 +7,7 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ -#include +#include #include #include #include diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c index 4712de8ff80..65ac0b9c2d0 100644 --- a/arch/ppc/platforms/4xx/ibm440ep.c +++ b/arch/ppc/platforms/4xx/ibm440ep.c @@ -14,6 +14,7 @@ */ #include #include +#include #include #include #include diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c index d90627b68fa..7e33bb63544 100644 --- a/arch/ppc/platforms/4xx/ibmstb4.c +++ b/arch/ppc/platforms/4xx/ibmstb4.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c index bee8b4ac8af..611ac861804 100644 --- a/arch/ppc/platforms/4xx/redwood5.c +++ b/arch/ppc/platforms/4xx/redwood5.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c index 8b1012994df..b1311669128 100644 --- a/arch/ppc/platforms/4xx/redwood6.c +++ b/arch/ppc/platforms/4xx/redwood6.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/ppc/platforms/chrp_pegasos_eth.c b/arch/ppc/platforms/chrp_pegasos_eth.c index cad5bfa153b..d1af11c73ea 100644 --- a/arch/ppc/platforms/chrp_pegasos_eth.c +++ b/arch/ppc/platforms/chrp_pegasos_eth.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c index f64ac2acb60..6ca7bcac947 100644 --- a/arch/ppc/platforms/cpci690.c +++ b/arch/ppc/platforms/cpci690.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c index aa50637a5cf..32358b3fb23 100644 --- a/arch/ppc/platforms/ev64260.c +++ b/arch/ppc/platforms/ev64260.c @@ -33,6 +33,7 @@ #include #include #include +#include #if !defined(CONFIG_SERIAL_MPSC_CONSOLE) #include #include diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c index 9811a8a52c2..4e6cc64b3ef 100644 --- a/arch/ppc/platforms/ev64360.c +++ b/arch/ppc/platforms/ev64360.c @@ -25,6 +25,7 @@ #include #include #include +#include #ifdef CONFIG_BOOTIMG #include #endif diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c index ff379686012..0f07e963de3 100644 --- a/arch/ppc/platforms/hdpu.c +++ b/arch/ppc/platforms/hdpu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c index 2b53afae0e9..beb61714145 100644 --- a/arch/ppc/platforms/katana.c +++ b/arch/ppc/platforms/katana.c @@ -29,6 +29,7 @@ #include #include #include +#include #ifdef CONFIG_BOOTIMG #include #endif diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c index 0376c8cff5d..7e65b7f1f62 100644 --- a/arch/ppc/platforms/radstone_ppc7d.c +++ b/arch/ppc/platforms/radstone_ppc7d.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include diff --git a/arch/ppc/syslib/mpc52xx_devices.c b/arch/ppc/syslib/mpc52xx_devices.c index ad5182efca1..da3c74bfdc9 100644 --- a/arch/ppc/syslib/mpc52xx_devices.c +++ b/arch/ppc/syslib/mpc52xx_devices.c @@ -15,6 +15,7 @@ #include #include +#include #include #include diff --git a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c index 4849850a59e..1227521c0da 100644 --- a/arch/ppc/syslib/mv64x60.c +++ b/arch/ppc/syslib/mv64x60.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/arch/ppc/syslib/pq2_devices.c b/arch/ppc/syslib/pq2_devices.c index 1d3869768f9..61668aad86e 100644 --- a/arch/ppc/syslib/pq2_devices.c +++ b/arch/ppc/syslib/pq2_devices.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/sh/boards/superh/microdev/setup.c b/arch/sh/boards/superh/microdev/setup.c index c18919941ec..1c1d65fb12d 100644 --- a/arch/sh/boards/superh/microdev/setup.c +++ b/arch/sh/boards/superh/microdev/setup.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c index 1495007bf6c..721e2601a75 100644 --- a/arch/um/drivers/net_kern.c +++ b/arch/um/drivers/net_kern.c @@ -20,6 +20,7 @@ #include "linux/ctype.h" #include "linux/bootmem.h" #include "linux/ethtool.h" +#include "linux/platform_device.h" #include "asm/uaccess.h" #include "user_util.h" #include "kern_util.h" diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c index f73134333f6..b2c86257b0f 100644 --- a/arch/um/drivers/ubd_kern.c +++ b/arch/um/drivers/ubd_kern.c @@ -35,6 +35,7 @@ #include "linux/blkpg.h" #include "linux/genhd.h" #include "linux/spinlock.h" +#include "linux/platform_device.h" #include "asm/segment.h" #include "asm/uaccess.h" #include "asm/irq.h" diff --git a/arch/xtensa/platform-iss/network.c b/arch/xtensa/platform-iss/network.c index 498d7dced1f..0682ffd3817 100644 --- a/arch/xtensa/platform-iss/network.c +++ b/arch/xtensa/platform-iss/network.c @@ -33,6 +33,7 @@ #include #include #include +#include #include diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 75ce8711bca..95f2af322c8 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -10,7 +10,7 @@ * information. */ -#include +#include #include #include #include diff --git a/drivers/block/floppy.c b/drivers/block/floppy.c index 00895477155..5eadbb9d4d7 100644 --- a/drivers/block/floppy.c +++ b/drivers/block/floppy.c @@ -177,7 +177,7 @@ static int print_unex = 1; #include #include #include -#include +#include #include /* for invalidate_buffers() */ /* diff --git a/drivers/char/s3c2410-rtc.c b/drivers/char/s3c2410-rtc.c index 887b8b2d788..d724c0de4f2 100644 --- a/drivers/char/s3c2410-rtc.c +++ b/drivers/char/s3c2410-rtc.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/char/sonypi.c b/drivers/char/sonypi.c index f86c1558723..d05067dcea0 100644 --- a/drivers/char/sonypi.c +++ b/drivers/char/sonypi.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include diff --git a/drivers/char/tb0219.c b/drivers/char/tb0219.c index eb7058cbf01..24355b23b2c 100644 --- a/drivers/char/tb0219.c +++ b/drivers/char/tb0219.c @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#include #include #include #include diff --git a/drivers/char/vr41xx_giu.c b/drivers/char/vr41xx_giu.c index 683278bc524..94641085faf 100644 --- a/drivers/char/vr41xx_giu.c +++ b/drivers/char/vr41xx_giu.c @@ -19,7 +19,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#include #include #include #include diff --git a/drivers/char/vr41xx_rtc.c b/drivers/char/vr41xx_rtc.c index a6dbe4da030..5e3292df69d 100644 --- a/drivers/char/vr41xx_rtc.c +++ b/drivers/char/vr41xx_rtc.c @@ -17,7 +17,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ -#include +#include #include #include #include diff --git a/drivers/char/watchdog/mpcore_wdt.c b/drivers/char/watchdog/mpcore_wdt.c index 75ca84ed4ad..47a5f6ab487 100644 --- a/drivers/char/watchdog/mpcore_wdt.c +++ b/drivers/char/watchdog/mpcore_wdt.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/char/watchdog/mv64x60_wdt.c b/drivers/char/watchdog/mv64x60_wdt.c index 6d3ff0836c4..04e0d7e9680 100644 --- a/drivers/char/watchdog/mv64x60_wdt.c +++ b/drivers/char/watchdog/mv64x60_wdt.c @@ -22,6 +22,8 @@ #include #include #include +#include + #include #include #include diff --git a/drivers/char/watchdog/s3c2410_wdt.c b/drivers/char/watchdog/s3c2410_wdt.c index b732020acad..e7e20a6d64b 100644 --- a/drivers/char/watchdog/s3c2410_wdt.c +++ b/drivers/char/watchdog/s3c2410_wdt.c @@ -44,7 +44,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/eisa/virtual_root.c b/drivers/eisa/virtual_root.c index 15677f20bd8..0f97a0cb0ff 100644 --- a/drivers/eisa/virtual_root.c +++ b/drivers/eisa/virtual_root.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/firmware/dcdbas.c b/drivers/firmware/dcdbas.c index 955537fe995..8ed6ddbb9c5 100644 --- a/drivers/firmware/dcdbas.c +++ b/drivers/firmware/dcdbas.c @@ -20,7 +20,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/drivers/firmware/dell_rbu.c b/drivers/firmware/dell_rbu.c index 4f4ba9b6d18..125929c9048 100644 --- a/drivers/firmware/dell_rbu.c +++ b/drivers/firmware/dell_rbu.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/hwmon/hdaps.c b/drivers/hwmon/hdaps.c index 0015da5668a..1e5dfc7805e 100644 --- a/drivers/hwmon/hdaps.c +++ b/drivers/hwmon/hdaps.c @@ -27,7 +27,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c index 9888fae1f37..13752bcb2af 100644 --- a/drivers/i2c/busses/i2c-iop3xx.c +++ b/drivers/i2c/busses/i2c-iop3xx.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/i2c/busses/i2c-isa.c b/drivers/i2c/busses/i2c-isa.c index 4fdc0241160..03672c9ca40 100644 --- a/drivers/i2c/busses/i2c-isa.c +++ b/drivers/i2c/busses/i2c-isa.c @@ -38,6 +38,7 @@ #include #include #include +#include static u32 isa_func(struct i2c_adapter *adapter); diff --git a/drivers/i2c/busses/i2c-ixp2000.c b/drivers/i2c/busses/i2c-ixp2000.c index 42016ee6ef1..64552a376f2 100644 --- a/drivers/i2c/busses/i2c-ixp2000.c +++ b/drivers/i2c/busses/i2c-ixp2000.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/i2c/busses/i2c-ixp4xx.c b/drivers/i2c/busses/i2c-ixp4xx.c index 69303ab65e0..cc652c35081 100644 --- a/drivers/i2c/busses/i2c-ixp4xx.c +++ b/drivers/i2c/busses/i2c-ixp4xx.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 8491633005b..65b939a059e 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include #include #include diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index d0d2a6f1386..6b48027b2ee 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c @@ -17,6 +17,8 @@ #include #include #include +#include + #include /* Register defines */ diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index 44b595d90a4..67ccbea24ba 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index 6ced28e9007..a1268e53425 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c index eaa4742e04f..9dbb72fffbe 100644 --- a/drivers/i2c/chips/isp1301_omap.c +++ b/drivers/i2c/chips/isp1301_omap.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c index 02e335a04f0..82ea1b7ec91 100644 --- a/drivers/i2c/i2c-core.c +++ b/drivers/i2c/i2c-core.c @@ -30,6 +30,7 @@ #include #include #include +#include #include diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c index ea14c8f1c82..8af0bd1424d 100644 --- a/drivers/i2c/i2c-dev.c +++ b/drivers/i2c/i2c-dev.c @@ -34,6 +34,7 @@ #include #include #include +#include #include static struct i2c_client i2cdev_client_template; diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c index 3210d298b3b..d00d14bb637 100644 --- a/drivers/input/keyboard/corgikbd.c +++ b/drivers/input/keyboard/corgikbd.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c index cee9c734a04..0fa38a559cd 100644 --- a/drivers/input/keyboard/spitzkbd.c +++ b/drivers/input/keyboard/spitzkbd.c @@ -12,7 +12,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/input/serio/ct82c710.c b/drivers/input/serio/ct82c710.c index dd0f5bd9024..4da6c86b5d7 100644 --- a/drivers/input/serio/ct82c710.c +++ b/drivers/input/serio/ct82c710.c @@ -37,6 +37,7 @@ #include #include #include +#include #include diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index 4bc40f15999..01e18642202 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -20,6 +20,7 @@ #include #include #include +#include #include diff --git a/drivers/input/serio/maceps2.c b/drivers/input/serio/maceps2.c index 9880fc145d9..d857f7081ad 100644 --- a/drivers/input/serio/maceps2.c +++ b/drivers/input/serio/maceps2.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/input/serio/q40kbd.c b/drivers/input/serio/q40kbd.c index 46093c50798..b44d255596c 100644 --- a/drivers/input/serio/q40kbd.c +++ b/drivers/input/serio/q40kbd.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c index 106f5eefd89..52c49258f8a 100644 --- a/drivers/input/serio/rpckbd.c +++ b/drivers/input/serio/rpckbd.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c index 0ba3e6562bf..15e88eeae8d 100644 --- a/drivers/input/touchscreen/corgi_ts.c +++ b/drivers/input/touchscreen/corgi_ts.c @@ -11,7 +11,7 @@ #include -#include +#include #include #include #include diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c index 720e7a32630..7daa0ed7331 100644 --- a/drivers/mfd/mcp-sa11x0.c +++ b/drivers/mfd/mcp-sa11x0.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/misc/hdpuftrs/hdpu_cpustate.c b/drivers/misc/hdpuftrs/hdpu_cpustate.c index 46de5c94055..9c4dd682ac7 100644 --- a/drivers/misc/hdpuftrs/hdpu_cpustate.c +++ b/drivers/misc/hdpuftrs/hdpu_cpustate.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/misc/hdpuftrs/hdpu_nexus.c b/drivers/misc/hdpuftrs/hdpu_nexus.c index c203b27269e..165f3405df2 100644 --- a/drivers/misc/hdpuftrs/hdpu_nexus.c +++ b/drivers/misc/hdpuftrs/hdpu_nexus.c @@ -21,7 +21,7 @@ #include #include -#include +#include static int hdpu_nexus_probe(struct device *ddev); static int hdpu_nexus_remove(struct device *ddev); diff --git a/drivers/mmc/pxamci.c b/drivers/mmc/pxamci.c index 8eba373d42d..4da4a98bd59 100644 --- a/drivers/mmc/pxamci.c +++ b/drivers/mmc/pxamci.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mmc/wbsd.c b/drivers/mmc/wbsd.c index 3ace875decc..942668e93a7 100644 --- a/drivers/mmc/wbsd.c +++ b/drivers/mmc/wbsd.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/mtd/maps/bast-flash.c b/drivers/mtd/maps/bast-flash.c index 0ba0ff7d43b..5f248ebe68e 100644 --- a/drivers/mtd/maps/bast-flash.c +++ b/drivers/mtd/maps/bast-flash.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c index e39a98a0171..d14a0185b8f 100644 --- a/drivers/mtd/maps/integrator-flash.c +++ b/drivers/mtd/maps/integrator-flash.c @@ -32,7 +32,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/maps/ixp2000.c b/drivers/mtd/maps/ixp2000.c index a9f86c7fbd5..6815baee89d 100644 --- a/drivers/mtd/maps/ixp2000.c +++ b/drivers/mtd/maps/ixp2000.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c index 3fcc3288407..06e1c7fffed 100644 --- a/drivers/mtd/maps/ixp4xx.c +++ b/drivers/mtd/maps/ixp4xx.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c index b17bca657da..9c9f4116e50 100644 --- a/drivers/mtd/maps/omap_nor.c +++ b/drivers/mtd/maps/omap_nor.c @@ -30,7 +30,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include +#include #include #include #include diff --git a/drivers/mtd/maps/plat-ram.c b/drivers/mtd/maps/plat-ram.c index 118b04544ca..e751e05fcc6 100644 --- a/drivers/mtd/maps/plat-ram.c +++ b/drivers/mtd/maps/plat-ram.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c index 6a8e0caf9fd..66b4c2780ad 100644 --- a/drivers/mtd/maps/sa1100-flash.c +++ b/drivers/mtd/maps/sa1100-flash.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index b47ebcb31e0..bf2325df80c 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -48,7 +48,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/depca.c b/drivers/net/depca.c index c4aa5fe2840..4d26e5e7d18 100644 --- a/drivers/net/depca.c +++ b/drivers/net/depca.c @@ -254,7 +254,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c index abce1f730d0..c0af6fb1fbb 100644 --- a/drivers/net/dm9000.c +++ b/drivers/net/dm9000.c @@ -66,6 +66,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index ae5a2ed3b26..962580f2c4a 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c @@ -81,7 +81,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/net/gianfar_mii.c b/drivers/net/gianfar_mii.c index 1eca1dbca7f..5a74d3d3dbe 100644 --- a/drivers/net/gianfar_mii.c +++ b/drivers/net/gianfar_mii.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index aef80f5e7c9..9571145c209 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c index 06883309916..76e0b9fb5e9 100644 --- a/drivers/net/irda/sa1100_ir.c +++ b/drivers/net/irda/sa1100_ir.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c index bbac720cca6..424515d3593 100644 --- a/drivers/net/irda/smsc-ircc2.c +++ b/drivers/net/irda/smsc-ircc2.c @@ -53,6 +53,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/jazzsonic.c b/drivers/net/jazzsonic.c index 8423cb6875f..a74a5cfaf5b 100644 --- a/drivers/net/jazzsonic.c +++ b/drivers/net/jazzsonic.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/macsonic.c b/drivers/net/macsonic.c index 405e18365ed..e9c999d7eb3 100644 --- a/drivers/net/macsonic.c +++ b/drivers/net/macsonic.c @@ -47,7 +47,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/mipsnet.c b/drivers/net/mipsnet.c index f79f7ee72ab..bbffb585b3b 100644 --- a/drivers/net/mipsnet.c +++ b/drivers/net/mipsnet.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 25c9a99c377..6fe948c10e7 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c @@ -39,6 +39,8 @@ #include #include #include +#include + #include #include #include diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c index 0ddaa611cc6..901c960d342 100644 --- a/drivers/net/smc91x.c +++ b/drivers/net/smc91x.c @@ -77,7 +77,7 @@ static const char version[] = #include #include #include -#include +#include #include #include #include diff --git a/drivers/net/tokenring/proteon.c b/drivers/net/tokenring/proteon.c index eb1423ede75..d04c918ebef 100644 --- a/drivers/net/tokenring/proteon.c +++ b/drivers/net/tokenring/proteon.c @@ -29,6 +29,7 @@ static const char version[] = "proteon.c: v1.00 02/01/2003 by Jochen Friedrich\n #include #include #include +#include #include #include diff --git a/drivers/net/tokenring/skisa.c b/drivers/net/tokenring/skisa.c index 3c7c66204f7..72cf708396b 100644 --- a/drivers/net/tokenring/skisa.c +++ b/drivers/net/tokenring/skisa.c @@ -36,6 +36,7 @@ static const char version[] = "skisa.c: v1.03 09/12/2002 by Jochen Friedrich\n"; #include #include #include +#include #include #include diff --git a/drivers/pcmcia/au1000_generic.c b/drivers/pcmcia/au1000_generic.c index d90a634cebf..f591839ab9c 100644 --- a/drivers/pcmcia/au1000_generic.c +++ b/drivers/pcmcia/au1000_generic.c @@ -42,7 +42,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/pcmcia/hd64465_ss.c b/drivers/pcmcia/hd64465_ss.c index b57a0b98b4d..561706ba449 100644 --- a/drivers/pcmcia/hd64465_ss.c +++ b/drivers/pcmcia/hd64465_ss.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/pcmcia/i82365.c b/drivers/pcmcia/i82365.c index 4a41f67d185..7ce455d01cc 100644 --- a/drivers/pcmcia/i82365.c +++ b/drivers/pcmcia/i82365.c @@ -47,7 +47,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pcmcia/m32r_cfc.c b/drivers/pcmcia/m32r_cfc.c index c6ed70ea481..2c22b4b3619 100644 --- a/drivers/pcmcia/m32r_cfc.c +++ b/drivers/pcmcia/m32r_cfc.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pcmcia/m32r_pcc.c b/drivers/pcmcia/m32r_pcc.c index 3397ff28de6..356a6fb416a 100644 --- a/drivers/pcmcia/m32r_pcc.c +++ b/drivers/pcmcia/m32r_pcc.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index 2558c3cc91e..47b5ade95bd 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index c2a12d53f6c..7fa18fb814b 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index bbe69b07ce5..5209d8c7764 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c index a1178a600e3..b54a8b8c0fc 100644 --- a/drivers/pcmcia/pxa2xx_sharpsl.c +++ b/drivers/pcmcia/pxa2xx_sharpsl.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/pcmcia/sa1100_generic.c b/drivers/pcmcia/sa1100_generic.c index b768fa81f04..122fb29b1e3 100644 --- a/drivers/pcmcia/sa1100_generic.c +++ b/drivers/pcmcia/sa1100_generic.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/drivers/pcmcia/tcic.c b/drivers/pcmcia/tcic.c index f158b67f661..e3126386437 100644 --- a/drivers/pcmcia/tcic.c +++ b/drivers/pcmcia/tcic.c @@ -44,7 +44,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/pcmcia/vrc4171_card.c b/drivers/pcmcia/vrc4171_card.c index 3d2dca675e0..38a028c725d 100644 --- a/drivers/pcmcia/vrc4171_card.c +++ b/drivers/pcmcia/vrc4171_card.c @@ -24,6 +24,7 @@ #include #include #include +#include #include diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index f24d84538fd..71dd1ebbe58 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index afb7ddf200e..f47d2c454e3 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 5b3933b0c99..b9a1f523c9a 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c index 8a79968f8ce..0dd08a09e7e 100644 --- a/drivers/serial/mpc52xx_uart.c +++ b/drivers/serial/mpc52xx_uart.c @@ -45,7 +45,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c index efe79b1fd43..f4c709bc464 100644 --- a/drivers/serial/mpsc.c +++ b/drivers/serial/mpsc.c @@ -52,6 +52,8 @@ * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. */ +#include + #include "mpsc.h" /* diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index 8cc4cedadd9..16b2f9417af 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c @@ -39,7 +39,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c index 06a17dff1a7..036792328d4 100644 --- a/drivers/serial/s3c2410.c +++ b/drivers/serial/s3c2410.c @@ -63,7 +63,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c index c4a789e6af4..ed618cc7ae9 100644 --- a/drivers/serial/sa1100.c +++ b/drivers/serial/sa1100.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/serial/vr41xx_siu.c b/drivers/serial/vr41xx_siu.c index 2b623ab0e36..01696b3e3f6 100644 --- a/drivers/serial/vr41xx_siu.c +++ b/drivers/serial/vr41xx_siu.c @@ -26,7 +26,7 @@ #endif #include -#include +#include #include #include #include diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c index 02106bebd5c..975ace3f5b1 100644 --- a/drivers/usb/gadget/dummy_hcd.c +++ b/drivers/usb/gadget/dummy_hcd.c @@ -50,7 +50,7 @@ #include #include #include - +#include #include #include diff --git a/drivers/usb/gadget/lh7a40x_udc.c b/drivers/usb/gadget/lh7a40x_udc.c index 9b3673904da..bc6269f10cb 100644 --- a/drivers/usb/gadget/lh7a40x_udc.c +++ b/drivers/usb/gadget/lh7a40x_udc.c @@ -21,6 +21,8 @@ * */ +#include + #include "lh7a40x_udc.h" //#define DEBUG printk diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 41c96b0afbb..387692a3611 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c index f83a9262f95..ee9cd7869d9 100644 --- a/drivers/usb/gadget/pxa2xx_udc.c +++ b/drivers/usb/gadget/pxa2xx_udc.c @@ -43,7 +43,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index ddb8fc59146..f9c3f5b8dd1 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -70,6 +70,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c index a277e258eb6..f0c78cf14b6 100644 --- a/drivers/usb/host/ohci-au1xxx.c +++ b/drivers/usb/host/ohci-au1xxx.c @@ -18,6 +18,8 @@ * This file is licenced under the GPL. */ +#include + #include #define USBH_ENABLE_BE (1<<0) diff --git a/drivers/usb/host/ohci-lh7a404.c b/drivers/usb/host/ohci-lh7a404.c index 238fa4ade61..336c766c6e2 100644 --- a/drivers/usb/host/ohci-lh7a404.c +++ b/drivers/usb/host/ohci-lh7a404.c @@ -16,6 +16,8 @@ * This file is licenced under the GPL. */ +#include + #include diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 45efeed1fcc..277bcb902d3 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -14,6 +14,8 @@ * This file is licenced under the GPL. */ +#include + #include #include #include diff --git a/drivers/usb/host/ohci-ppc-soc.c b/drivers/usb/host/ohci-ppc-soc.c index 4832e57ae57..92cf6f4a137 100644 --- a/drivers/usb/host/ohci-ppc-soc.c +++ b/drivers/usb/host/ohci-ppc-soc.c @@ -14,6 +14,8 @@ * This file is licenced under the GPL. */ +#include + /* configure so an HC device and id are always provided */ /* always called with process context; sleeping is OK */ diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index d287dcccd41..5181999c56c 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -19,7 +19,7 @@ * This file is licenced under the GPL. */ -#include +#include #include #include #include diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c index fab420a2ce7..ee1fc605b40 100644 --- a/drivers/usb/host/ohci-s3c2410.c +++ b/drivers/usb/host/ohci-s3c2410.c @@ -19,6 +19,8 @@ * This file is licenced under the GPL. */ +#include + #include #include #include diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c index 40169d9cf2b..5607c0ae683 100644 --- a/drivers/usb/host/sl811-hcd.c +++ b/drivers/usb/host/sl811-hcd.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include diff --git a/drivers/usb/host/sl811_cs.c b/drivers/usb/host/sl811_cs.c index 38aebe361ca..e73faf831b2 100644 --- a/drivers/usb/host/sl811_cs.c +++ b/drivers/usb/host/sl811_cs.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index f02965f3950..9b6a39348f8 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/video/arcfb.c b/drivers/video/arcfb.c index d28457e0c06..126daff1c84 100644 --- a/drivers/video/arcfb.c +++ b/drivers/video/arcfb.c @@ -47,6 +47,7 @@ #include #include #include +#include #include diff --git a/drivers/video/backlight/corgi_bl.c b/drivers/video/backlight/corgi_bl.c index 1991fdb32df..4867498f68e 100644 --- a/drivers/video/backlight/corgi_bl.c +++ b/drivers/video/backlight/corgi_bl.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/video/dnfb.c b/drivers/video/dnfb.c index 1dbb82dca40..1785686a7f1 100644 --- a/drivers/video/dnfb.c +++ b/drivers/video/dnfb.c @@ -6,6 +6,8 @@ #include #include #include +#include + #include #include #include diff --git a/drivers/video/epson1355fb.c b/drivers/video/epson1355fb.c index 116e808d71c..7363d0b25fd 100644 --- a/drivers/video/epson1355fb.c +++ b/drivers/video/epson1355fb.c @@ -54,6 +54,8 @@ #include #include #include +#include + #include #include #include diff --git a/drivers/video/gbefb.c b/drivers/video/gbefb.c index d3c1922cb13..fc0a1beef96 100644 --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index 0b9301facbd..64d9bcc38da 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 6206da9dd5d..efd9333b05c 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/video/q40fb.c b/drivers/video/q40fb.c index 162012bb926..8416b2e2b50 100644 --- a/drivers/video/q40fb.c +++ b/drivers/video/q40fb.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/drivers/video/s1d13xxxfb.c b/drivers/video/s1d13xxxfb.c index cb2f7a1de94..f4437430dc5 100644 --- a/drivers/video/s1d13xxxfb.c +++ b/drivers/video/s1d13xxxfb.c @@ -30,7 +30,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c index 3862d3cb1fb..3cef90456a4 100644 --- a/drivers/video/s3c2410fb.c +++ b/drivers/video/s3c2410fb.c @@ -86,6 +86,7 @@ #include #include #include +#include #include #include diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index 78e5f194b0d..3d35b28aaac 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c @@ -173,7 +173,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/video/sgivwfb.c b/drivers/video/sgivwfb.c index 8413907b379..cf5106eab2d 100644 --- a/drivers/video/sgivwfb.c +++ b/drivers/video/sgivwfb.c @@ -18,6 +18,8 @@ #include #include #include +#include + #include #include diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c index b1243da55fc..3cc23106641 100644 --- a/drivers/video/vesafb.c +++ b/drivers/video/vesafb.c @@ -19,6 +19,8 @@ #include #include #include +#include + #include