From 21a035db897975a5195dfb1525433637f30aeebf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 8 Apr 2013 11:06:39 +0200 Subject: pinctrl: u300 device tree support This adds a simple device tree compat string for the U300 pin controller. The base address is already passed properly as a resource and everything works fine. Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-u300.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c index 6a3a7503e6a..06bfa09bb15 100644 --- a/drivers/pinctrl/pinctrl-u300.c +++ b/drivers/pinctrl/pinctrl-u300.c @@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id u300_pinctrl_match[] = { + { .compatible = "stericsson,pinctrl-u300" }, + {}, +}; + + static struct platform_driver u300_pmx_driver = { .driver = { .name = DRIVER_NAME, .owner = THIS_MODULE, + .of_match_table = u300_pinctrl_match, }, .probe = u300_pmx_probe, .remove = u300_pmx_remove, -- cgit v1.2.3-70-g09d2 From 351c2163f918e2a4218e0206f854dbec7799fda8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 10 Apr 2013 10:49:31 +0200 Subject: pinctrl: coh901: add device tree support This makes it possible to probe the COH901 pinctrl driver from the device tree, and assigned the device tree node in the gpio_chip so we can look up cross-references from the device tree. Start grabbing the per-port (bank) IRQs by index instead of by name so we don't have to look up the IRQs by name going forward. Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/gpio-stericsson-coh901.txt | 7 +++++++ drivers/pinctrl/pinctrl-coh901.c | 12 ++++++++++-- 2 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt new file mode 100644 index 00000000000..fd665b44d76 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt @@ -0,0 +1,7 @@ +ST-Ericsson COH 901 571/3 GPIO controller + +Required properties: +- compatible: Compatible property value should be "stericsson,gpio-coh901" +- reg: Physical base address of the controller and length of memory mapped + region. +- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks. diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index edde3acc418..d4f8afdad1a 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -773,8 +773,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev) port->number = portno; port->gpio = gpio; - port->irq = platform_get_irq_byname(pdev, - port->name); + port->irq = platform_get_irq(pdev, portno); dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq, port->name); @@ -811,6 +810,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev) } dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); +#ifdef CONFIG_OF_GPIO + gpio->chip.of_node = pdev->dev.of_node; +#endif err = gpiochip_add(&gpio->chip); if (err) { dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); @@ -864,9 +866,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id u300_gpio_match[] = { + { .compatible = "stericsson,gpio-coh901" }, + {}, +}; + static struct platform_driver u300_gpio_driver = { .driver = { .name = "u300-gpio", + .of_match_table = u300_gpio_match, }, .remove = __exit_p(u300_gpio_remove), }; -- cgit v1.2.3-70-g09d2 From 8c58d891576c726bb8217842e955827ba8bb405a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 11 Apr 2013 14:59:47 +0200 Subject: i2c: stu300: device tree support This adds device tree support for the ST DDC I2C driver known as "stu300" in the kernel tree. Reviewed-by: Wolfram Sang Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt | 15 +++++++++++++++ drivers/i2c/busses/i2c-stu300.c | 12 ++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt new file mode 100644 index 00000000000..bd81a482634 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt @@ -0,0 +1,15 @@ +ST Microelectronics DDC I2C + +Required properties : +- compatible : Must be "st,ddci2c" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: interrupt number to the cpu. +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties: +- Child nodes conforming to i2c bus binding + +Examples : + diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c index 0a6f941133f..1beaa05a3d2 100644 --- a/drivers/i2c/busses/i2c-stu300.c +++ b/drivers/i2c/busses/i2c-stu300.c @@ -17,6 +17,7 @@ #include #include #include +#include /* the name of this kernel module */ #define NAME "stu300" @@ -923,6 +924,7 @@ stu300_probe(struct platform_device *pdev) adap->nr = bus_nr; adap->algo = &stu300_algo; adap->dev.parent = &pdev->dev; + adap->dev.of_node = pdev->dev.of_node; i2c_set_adapdata(adap, dev); /* i2c device drivers may be active on return from add_adapter() */ @@ -934,6 +936,10 @@ stu300_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, dev); + dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n", + dev->virtbase, dev->irq); + of_i2c_register_devices(adap); + return 0; } @@ -978,11 +984,17 @@ stu300_remove(struct platform_device *pdev) return 0; } +static const struct of_device_id stu300_dt_match[] = { + { .compatible = "st,ddci2c" }, + {}, +}; + static struct platform_driver stu300_i2c_driver = { .driver = { .name = NAME, .owner = THIS_MODULE, .pm = STU300_I2C_PM, + .of_match_table = stu300_dt_match, }, .remove = __exit_p(stu300_remove), -- cgit v1.2.3-70-g09d2 From c83c199199b9d68c56b5cc53b01b8f513f91b93a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Apr 2013 12:56:36 +0200 Subject: watchdog: coh901327: devicetree support This adds support for probing the COH 901 327 watchdog from the device tree and also adds associated bindings. Acked-by: Wim Van Sebroeck Reviewed-by: Guenter Roeck Signed-off-by: Linus Walleij --- .../bindings/watchdog/stericsson-coh901327.txt | 19 +++++++++++++++++++ drivers/watchdog/coh901327_wdt.c | 12 +++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt new file mode 100644 index 00000000000..8ffb88e39e7 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt @@ -0,0 +1,19 @@ +ST-Ericsson COH 901 327 Watchdog timer + +Required properties: +- compatible: must be "stericsson,coh901327". +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: the interrupt used for the watchdog timeout warning. + +Optional properties: +- timeout-sec: contains the watchdog timeout in seconds. + +Example: + +watchdog: watchdog@c0012000 { + compatible = "stericsson,coh901327"; + reg = <0xc0012000 0x1000>; + interrupts = <3>; + timeout-sec = <60>; +}; diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c index b9b8a8be6f1..4bd070f524e 100644 --- a/drivers/watchdog/coh901327_wdt.c +++ b/drivers/watchdog/coh901327_wdt.c @@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev) clk_disable(clk); - if (margin < 1 || margin > 327) - margin = 60; - coh901327_wdt.timeout = margin; + ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev); + if (ret < 0) + coh901327_wdt.timeout = 60; ret = watchdog_register_device(&coh901327_wdt); if (ret == 0) @@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void) /* Return and await doom */ } +static const struct of_device_id coh901327_dt_match[] = { + { .compatible = "stericsson,coh901327" }, + {}, +}; + static struct platform_driver coh901327_driver = { .driver = { .owner = THIS_MODULE, .name = "coh901327_wdog", + .of_match_table = coh901327_dt_match, }, .remove = __exit_p(coh901327_remove), .suspend = coh901327_suspend, -- cgit v1.2.3-70-g09d2 From a16b6c630ff8f291639c4cd0f8e57543735a1b5c Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Apr 2013 13:03:13 +0200 Subject: rtc: coh901331: add devicetree support This add devicetree probe support to the COH 901 331 RTC driver. Cc: Alessandro Zummo Signed-off-by: Linus Walleij --- drivers/rtc/rtc-coh901331.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c index 93c06588ddc..ad6863a76af 100644 --- a/drivers/rtc/rtc-coh901331.c +++ b/drivers/rtc/rtc-coh901331.c @@ -274,11 +274,17 @@ static void coh901331_shutdown(struct platform_device *pdev) clk_disable_unprepare(rtap->clk); } +static const struct of_device_id coh901331_dt_match[] = { + { .compatible = "stericsson,coh901331" }, + {}, +}; + static struct platform_driver coh901331_driver = { .driver = { .name = "rtc-coh901331", .owner = THIS_MODULE, .pm = &coh901331_pm_ops, + .of_match_table = coh901331_dt_match, }, .remove = __exit_p(coh901331_remove), .shutdown = coh901331_shutdown, -- cgit v1.2.3-70-g09d2 From faadc6e3d5e0ab718dc1e131fb14bbb52f144238 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Apr 2013 13:42:55 +0200 Subject: dma: coh901318: add devicetree support This adds support for probing the COH 901 318 DMA controller and channels from the device tree. Contains portions of a sketch patch from Arnd Bergmann. Cc: Arnd Bergmann Acked-by: Vinod Koul Signed-off-by: Linus Walleij --- .../devicetree/bindings/dma/ste-coh901318.txt | 32 ++++++++++++++++ drivers/dma/coh901318.c | 43 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/ste-coh901318.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt new file mode 100644 index 00000000000..091ad057e9c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/ste-coh901318.txt @@ -0,0 +1,32 @@ +ST-Ericsson COH 901 318 DMA Controller + +This is a DMA controller which has begun as a fork of the +ARM PL08x PrimeCell VHDL code. + +Required properties: +- compatible: should be "stericsson,coh901318" +- reg: register locations and length +- interrupts: the single DMA IRQ +- #dma-cells: must be set to <1>, as the channels on the + COH 901 318 are simple and identified by a single number +- dma-channels: the number of DMA channels handled + +Example: + +dmac: dma-controller@c00020000 { + compatible = "stericsson,coh901318"; + reg = <0xc0020000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <2>; + #dma-cells = <1>; + dma-channels = <40>; +}; + +Consumers example: + +uart0: serial@c0013000 { + compatible = "..."; + (...) + dmas = <&dmac 17 &dmac 18>; + dma-names = "tx", "rx"; +}; diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index 3b23061cdb4..9bfaddd57ef 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "coh901318.h" #include "dmaengine.h" @@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) } EXPORT_SYMBOL(coh901318_filter_id); +struct coh901318_filter_args { + struct coh901318_base *base; + unsigned int ch_nr; +}; + +static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data) +{ + struct coh901318_filter_args *args = data; + + if (&args->base->dma_slave == chan->device && + args->ch_nr == to_coh901318_chan(chan)->id) + return true; + + return false; +} + +static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct coh901318_filter_args args = { + .base = ofdma->of_dma_data, + .ch_nr = dma_spec->args[0], + }; + dma_cap_mask_t cap; + dma_cap_zero(cap); + dma_cap_set(DMA_SLAVE, cap); + + return dma_request_channel(cap, coh901318_filter_base_and_id, &args); +} /* * DMA channel allocation */ @@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev) if (err) goto err_register_memcpy; + err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate, + base); + if (err) + goto err_register_of_dma; + platform_set_drvdata(pdev, base); dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n", (u32) base->virtbase); return err; + err_register_of_dma: + dma_async_device_unregister(&base->dma_memcpy); err_register_memcpy: dma_async_device_unregister(&base->dma_slave); err_register_slave: @@ -2752,17 +2789,23 @@ static int coh901318_remove(struct platform_device *pdev) { struct coh901318_base *base = platform_get_drvdata(pdev); + of_dma_controller_free(pdev->dev.of_node); dma_async_device_unregister(&base->dma_memcpy); dma_async_device_unregister(&base->dma_slave); coh901318_pool_destroy(&base->pool); return 0; } +static const struct of_device_id coh901318_dt_match[] = { + { .compatible = "stericsson,coh901318" }, + {}, +}; static struct platform_driver coh901318_driver = { .remove = coh901318_remove, .driver = { .name = "coh901318", + .of_match_table = coh901318_dt_match, }, }; -- cgit v1.2.3-70-g09d2 From 0004b017fe65eff60a9b403c52acc03521108c21 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 2 May 2013 16:56:15 +0200 Subject: ARM: u300: push down syscon registers Get rid of the header as a prerequisite for multiplatform support. Do this by pushing the registers down to their respective drivers and deleting the unused remainder. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- arch/arm/mach-u300/core.c | 26 +- arch/arm/mach-u300/include/mach/syscon.h | 592 ------------------------------- arch/arm/mach-u300/regulator.c | 9 +- drivers/clk/clk-u300.c | 343 +++++++++++++++++- 4 files changed, 373 insertions(+), 597 deletions(-) delete mode 100644 arch/arm/mach-u300/include/mach/syscon.h (limited to 'drivers') diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 13d48125b89..254fe922457 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -22,7 +22,31 @@ #include #include -#include + +/* + * SYSCON addresses applicable to the core machine. + */ + +/* Chip ID register 16bit (R/-) */ +#define U300_SYSCON_CIDR (0x400) +/* SMCR */ +#define U300_SYSCON_SMCR (0x4d0) +#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) +#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) +#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) +#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) +/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ +#define U300_SYSCON_CSDR (0x4f0) +#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) +/* PRINT_CONTROL Print Control 16bit (R/-) */ +#define U300_SYSCON_PCR (0x4f8) +#define U300_SYSCON_PCR_SERV_IND (0x0001) +/* BOOT_CONTROL 16bit (R/-) */ +#define U300_SYSCON_BCR (0x4fc) +#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) +#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) +#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) +#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) /* * Static I/O mappings that are needed for booting the U300 platforms. The diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h deleted file mode 100644 index 10bdd0be977..00000000000 --- a/arch/arm/mach-u300/include/mach/syscon.h +++ /dev/null @@ -1,592 +0,0 @@ -/* - * - * arch/arm/mach-u300/include/mach/syscon.h - * - * - * Copyright (C) 2008-2012 ST-Ericsson AB - * - * Author: Rickard Andersson - */ - -#ifndef __MACH_SYSCON_H -#define __MACH_SYSCON_H - -/* - * All register defines for SYSCON registers that concerns individual - * block clocks and reset lines are registered here. This is because - * we don't want any other file to try to fool around with this stuff. - */ - -/* APP side SYSCON registers */ -/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */ -/* CLK Control Register 16bit (R/W) */ -#define U300_SYSCON_CCR (0x0000) -#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) -#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) -#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) -#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) -/* CLK Status Register 16bit (R/W) */ -#define U300_SYSCON_CSR (0x0004) -#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) -#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) -/* Reset lines for SLOW devices 16bit (R/W) */ -#define U300_SYSCON_RSR (0x0014) -#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) -#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) -#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) -#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) -#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) -#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) -#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) -#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) -#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) -#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) -/* Reset lines for FAST devices 16bit (R/W) */ -#define U300_SYSCON_RFR (0x0018) -#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) -#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) -#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) -#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) -#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) -#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) -#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) -#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) -/* Reset lines for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_RRR (0x001c) -#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) -#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) -#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) -#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) -#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) -#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) -#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) -#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) -#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) -#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) -#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) -#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) -#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) -/* Clock enable for SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CESR (0x0020) -#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) -#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) -#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) -#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) -#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) -#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) -#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) -#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) -#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) -/* Clock enable for FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CEFR (0x0024) -#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) -#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) -#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) -#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) -#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) -#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) -#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) -#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) -#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) -#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) -/* Clock enable for the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CERR (0x0028) -#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) -#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) -#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) -#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) -#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) -#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) -#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) -#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) -#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) -#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) -#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) -#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) -#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) -#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) -/* Single block clock enable 16bit (-/W) */ -#define U300_SYSCON_SBCER (0x002c) -#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) -#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) -#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) -#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) -#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) -#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) -#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) -#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) -#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) -#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) -#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) -#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) -#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) -#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) -#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) -#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) -#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) -#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) -#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) -#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) -#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) -#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) -#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) -#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) -#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) -#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) -#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) -#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) -#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) -#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) -#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) -#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) -#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) -/* Single block clock disable 16bit (-/W) */ -#define U300_SYSCON_SBCDR (0x0030) -/* Same values as above for SBCER */ -/* Clock force SLOW peripherals 16bit (R/W) */ -#define U300_SYSCON_CFSR (0x003c) -#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) -/* Clock force FAST peripherals 16bit (R/W) */ -#define U300_SYSCON_CFFR (0x40) -/* Values not defined. Define if you want to use them. */ -/* Clock force the rest of the peripherals 16bit (R/W) */ -#define U300_SYSCON_CFRR (0x44) -#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) -#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) -#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) -#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) -#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) -#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) -#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) -#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) -#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) -#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) -#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) -#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) -#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) -#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) -/* PLL208 Frequency Control 16bit (R/W) */ -#define U300_SYSCON_PFCR (0x48) -#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) -/* Power Management Control 16bit (R/W) */ -#define U300_SYSCON_PMCR (0x50) -#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) -#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) -/* - * All other clocking registers moved to clock.c! - */ -/* Reset Out 16bit (R/W) */ -#define U300_SYSCON_RCR (0x6c) -#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) -/* EMIF Slew Rate Control 16bit (R/W) */ -#define U300_SYSCON_SRCLR (0x70) -#define U300_SYSCON_SRCLR_MASK (0x03FF) -#define U300_SYSCON_SRCLR_VALUE (0x03FF) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) -#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) -/* EMIF Clock Control Register 16bit (R/W) */ -#define U300_SYSCON_ECCR (0x0078) -#define U300_SYSCON_ECCR_MASK (0x000F) -#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) -#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) -#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) -#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) -/* Step one for killing the applications system 16bit (-/W) */ -#define U300_SYSCON_KA1R (0x0080) -#define U300_SYSCON_KA1R_MASK (0xFFFF) -#define U300_SYSCON_KA1R_VALUE (0xFFFF) -/* Step two for killing the application system 16bit (-/W) */ -#define U300_SYSCON_KA2R (0x0084) -#define U300_SYSCON_KA2R_MASK (0xFFFF) -#define U300_SYSCON_KA2R_VALUE (0xFFFF) -/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ -#define U300_SYSCON_MMF0R (0x90) -#define U300_SYSCON_MMF0R_MASK (0x00FF) -#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) -/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ -#define U300_SYSCON_MMF1R (0x94) -#define U300_SYSCON_MMF1R_MASK (0x00FF) -#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) -#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) -/* AAIF control register 16 bit (R/W) */ -#define U300_SYSCON_AAIFCR (0x98) -#define U300_SYSCON_AAIFCR_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003) -#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000) -#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001) -#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002) -#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003) -/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ -#define U300_SYSCON_MMCR (0x9C) -#define U300_SYSCON_MMCR_MASK (0x0003) -#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) -#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) -/* Pull up/down control (R/W) */ -#define U300_SYSCON_PUCR (0x104) -#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200) -#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100) -#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080) -#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040) -#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F) -/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ -#define U300_SYSCON_S0CCR (0x120) -#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ -#define U300_SYSCON_S1CCR (0x124) -#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) -#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ -#define U300_SYSCON_S2CCR (0x128) -#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) -#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) -#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) -#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) -#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) -#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) -#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) -#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) -#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) -#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) -#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) -#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) -#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) -#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) -/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */ -#define U300_SYSCON_MCR (0x12c) -#define U300_SYSCON_MCR_FIELD_MASK (0x00FF) -#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040) -#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0) -#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010) -#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020) -#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030) -#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008) -#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C) -#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002) -#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001) -/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ -#define U300_SYSCON_PICR (0x0130) -#define U300_SYSCON_PICR_MASK (0x00FF) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) -#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) -#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) -#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) -#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) -#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) -#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) -/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ -#define U300_SYSCON_PISR (0x0134) -#define U300_SYSCON_PISR_MASK (0x000F) -#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) -#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) -#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) -#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) -/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ -#define U300_SYSCON_PICLR (0x0138) -#define U300_SYSCON_PICLR_MASK (0x000F) -#define U300_SYSCON_PICLR_RWMASK (0x0000) -#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) -#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) -#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) -#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) -/* CAMIF_CONTROL 16 bit (-/W) */ -#define U300_SYSCON_CICR (0x013C) -#define U300_SYSCON_CICR_MASK (0x0FFF) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00) -#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0) -#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C) -#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003) -/* Clock activity observability register 0 */ -#define U300_SYSCON_C0OAR (0x140) -#define U300_SYSCON_C0OAR_MASK (0xFFFF) -#define U300_SYSCON_C0OAR_VALUE (0xFFFF) -#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) -#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) -#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) -#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) -#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) -#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) -#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) -#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) -#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) -#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) -#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) -#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) -#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) -#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) -#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) -#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) -/* Clock activity observability register 1 */ -#define U300_SYSCON_C1OAR (0x144) -#define U300_SYSCON_C1OAR_MASK (0x3FFE) -#define U300_SYSCON_C1OAR_VALUE (0x3FFE) -#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) -#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) -#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) -#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) -#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) -#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) -#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) -#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) -#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) -#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) -#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) -#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) -#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) -/* Clock activity observability register 2 */ -#define U300_SYSCON_C2OAR (0x148) -#define U300_SYSCON_C2OAR_MASK (0x0FFF) -#define U300_SYSCON_C2OAR_VALUE (0x0FFF) -#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) -#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) -#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) -#define U300_SYSCON_C2OAR_VC_CLK (0x0100) -#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) -#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) -#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) -#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) -#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) -#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) -#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) -#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) - -/* Chip ID register 16bit (R/-) */ -#define U300_SYSCON_CIDR (0x400) -/* Video IRQ clear 16bit (R/W) */ -#define U300_SYSCON_VICR (0x404) -#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002) -#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001) -/* SMCR */ -#define U300_SYSCON_SMCR (0x4d0) -#define U300_SYSCON_SMCR_FIELD_MASK (0x000e) -#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008) -#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004) -#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002) -/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */ -#define U300_SYSCON_CSDR (0x4f0) -#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001) -/* PRINT_CONTROL Print Control 16bit (R/-) */ -#define U300_SYSCON_PCR (0x4f8) -#define U300_SYSCON_PCR_SERV_IND (0x0001) -/* BOOT_CONTROL 16bit (R/-) */ -#define U300_SYSCON_BCR (0x4fc) -#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400) -#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200) -#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC) -#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003) - - -/* CPU clock defines */ -/** - * CPU high frequency in MHz - */ -#define SYSCON_CPU_CLOCK_HIGH 208 -/** - * CPU medium frequency in MHz - */ -#define SYSCON_CPU_CLOCK_MEDIUM 52 -/** - * CPU low frequency in MHz - */ -#define SYSCON_CPU_CLOCK_LOW 13 - -/* EMIF clock defines */ -/** - * EMIF high frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_HIGH 104 -/** - * EMIF medium frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_MEDIUM 52 -/** - * EMIF low frequency in MHz - */ -#define SYSCON_EMIF_CLOCK_LOW 13 - -/* AHB clock defines */ -/** - * AHB high frequency in MHz - */ -#define SYSCON_AHB_CLOCK_HIGH 52 -/** - * AHB medium frequency in MHz - */ -#define SYSCON_AHB_CLOCK_MEDIUM 26 -/** - * AHB low frequency in MHz - */ -#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */ - -enum syscon_busmaster { - SYSCON_BM_DMAC, - SYSCON_BM_XGAM, - SYSCON_BM_VIDEO_ENC -}; - -/* Selectr a resistor or a set of resistors */ -enum syscon_pull_up_down { - SYSCON_PU_KEY_IN_EN, - SYSCON_PU_EMIF_1_8_BIT_EN, - SYSCON_PU_EMIF_1_16_BIT_EN, - SYSCON_PU_EMIF_1_NFIF_READY_EN, - SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN, -}; - -/* - * Note that this array must match the order of the array "clk_reg" - * in syscon.c - */ -enum syscon_clk { - SYSCON_CLKCONTROL_SLOW_BRIDGE, - SYSCON_CLKCONTROL_UART, - SYSCON_CLKCONTROL_BTR, - SYSCON_CLKCONTROL_EH, - SYSCON_CLKCONTROL_GPIO, - SYSCON_CLKCONTROL_KEYPAD, - SYSCON_CLKCONTROL_APP_TIMER, - SYSCON_CLKCONTROL_ACC_TIMER, - SYSCON_CLKCONTROL_FAST_BRIDGE, - SYSCON_CLKCONTROL_I2C0, - SYSCON_CLKCONTROL_I2C1, - SYSCON_CLKCONTROL_I2S0, - SYSCON_CLKCONTROL_I2S1, - SYSCON_CLKCONTROL_MMC, - SYSCON_CLKCONTROL_SPI, - SYSCON_CLKCONTROL_I2S0_CORE, - SYSCON_CLKCONTROL_I2S1_CORE, - SYSCON_CLKCONTROL_UART1, - SYSCON_CLKCONTROL_AAIF, - SYSCON_CLKCONTROL_AHB, - SYSCON_CLKCONTROL_APEX, - SYSCON_CLKCONTROL_CPU, - SYSCON_CLKCONTROL_DMA, - SYSCON_CLKCONTROL_EMIF, - SYSCON_CLKCONTROL_NAND_IF, - SYSCON_CLKCONTROL_VIDEO_ENC, - SYSCON_CLKCONTROL_XGAM, - SYSCON_CLKCONTROL_SEMI, - SYSCON_CLKCONTROL_AHB_SUBSYS, - SYSCON_CLKCONTROL_MSPRO -}; - -enum syscon_sysclk_mode { - SYSCON_SYSCLK_DISABLED, - SYSCON_SYSCLK_M_CLK, - SYSCON_SYSCLK_ACC_FSM, - SYSCON_SYSCLK_PLL60_48, - SYSCON_SYSCLK_PLL60_60, - SYSCON_SYSCLK_ACC_PLL208, - SYSCON_SYSCLK_APP_PLL13, - SYSCON_SYSCLK_APP_FSM, - SYSCON_SYSCLK_RTC, - SYSCON_SYSCLK_APP_PLL208 -}; - -enum syscon_sysclk_req { - SYSCON_SYSCLKREQ_DISABLED, - SYSCON_SYSCLKREQ_ACTIVE_LOW, - SYSCON_SYSCLKREQ_MONITOR -}; - -enum syscon_clk_mode { - SYSCON_CLKMODE_OFF, - SYSCON_CLKMODE_DEFAULT, - SYSCON_CLKMODE_LOW, - SYSCON_CLKMODE_MEDIUM, - SYSCON_CLKMODE_HIGH, - SYSCON_CLKMODE_PERMANENT, - SYSCON_CLKMODE_ON, -}; - -enum syscon_call_mode { - SYSCON_CLKCALL_NOWAIT, - SYSCON_CLKCALL_WAIT, -}; - -int syscon_dc_on(bool keep_power_on); -int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster, - bool active); -bool syscon_get_busmaster_active_state(void); -int syscon_set_sleep_mask(enum syscon_clk, - bool sleep_ctrl); -int syscon_config_sysclk(u32 sysclk, - enum syscon_sysclk_mode sysclkmode, - bool inverse, - u32 divisor, - enum syscon_sysclk_req sysclkreq); -bool syscon_can_turn_off_semi_clock(void); - -/* This function is restricted to core.c */ -int syscon_request_normal_power(bool req); - -/* This function is restricted to be used by platform_speed.c */ -int syscon_speed_request(enum syscon_call_mode wait_mode, - enum syscon_clk_mode req_clk_mode); -#endif /* __MACH_SYSCON_H */ diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c index bbda954e00f..ab7d7a519b2 100644 --- a/arch/arm/mach-u300/regulator.c +++ b/arch/arm/mach-u300/regulator.c @@ -17,9 +17,12 @@ #include /* Those are just for writing in syscon */ #include -#include -#include -#include +#include + +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) /* * Regulators that power the board and chip and which are diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index a15f7928fb1..a41e42ec091 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -11,7 +11,348 @@ #include #include #include -#include + +/* APP side SYSCON registers */ +/* CLK Control Register 16bit (R/W) */ +#define U300_SYSCON_CCR (0x0000) +#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040) +#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020) +#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01) +#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00) +/* CLK Status Register 16bit (R/W) */ +#define U300_SYSCON_CSR (0x0004) +#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002) +#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001) +/* Reset lines for SLOW devices 16bit (R/W) */ +#define U300_SYSCON_RSR (0x0014) +#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200) +#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100) +#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080) +#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040) +#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020) +#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010) +#define U300_SYSCON_RSR_EH_RESET_EN (0x0008) +#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004) +#define U300_SYSCON_RSR_UART_RESET_EN (0x0002) +#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001) +/* Reset lines for FAST devices 16bit (R/W) */ +#define U300_SYSCON_RFR (0x0018) +#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080) +#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040) +#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020) +#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010) +#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008) +#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004) +#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002) +#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001) +/* Reset lines for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_RRR (0x001c) +#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000) +#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000) +#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000) +#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800) +#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100) +#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080) +#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040) +#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020) +#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010) +#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008) +#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004) +#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002) +#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001) +/* Clock enable for SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CESR (0x0020) +#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200) +#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100) +#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080) +#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040) +#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010) +#define U300_SYSCON_CESR_EH_CLK_EN (0x0008) +#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004) +#define U300_SYSCON_CESR_UART_CLK_EN (0x0002) +#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001) +/* Clock enable for FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CEFR (0x0024) +#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200) +#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100) +#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080) +#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040) +#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020) +#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010) +#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008) +#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004) +#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002) +#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001) +/* Clock enable for the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CERR (0x0028) +#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000) +#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000) +#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800) +#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400) +#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200) +#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100) +#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080) +#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040) +#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020) +#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010) +#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008) +#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004) +#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002) +#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001) +/* Single block clock enable 16bit (-/W) */ +#define U300_SYSCON_SBCER (0x002c) +#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009) +#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008) +#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007) +#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006) +#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004) +#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003) +#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002) +#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001) +#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000) +#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019) +#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018) +#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017) +#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016) +#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015) +#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014) +#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013) +#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012) +#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011) +#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010) +#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D) +#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C) +#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B) +#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A) +#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029) +#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028) +#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027) +#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026) +#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025) +#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024) +#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023) +#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022) +#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021) +#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020) +/* Single block clock disable 16bit (-/W) */ +#define U300_SYSCON_SBCDR (0x0030) +/* Same values as above for SBCER */ +/* Clock force SLOW peripherals 16bit (R/W) */ +#define U300_SYSCON_CFSR (0x003c) +#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200) +#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001) +/* Clock force FAST peripherals 16bit (R/W) */ +#define U300_SYSCON_CFFR (0x40) +/* Values not defined. Define if you want to use them. */ +/* Clock force the rest of the peripherals 16bit (R/W) */ +#define U300_SYSCON_CFRR (0x44) +#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000) +#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000) +#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800) +#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400) +#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200) +#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100) +#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080) +#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040) +#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020) +#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010) +#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008) +#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004) +#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002) +#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001) +/* PLL208 Frequency Control 16bit (R/W) */ +#define U300_SYSCON_PFCR (0x48) +#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F) +/* Power Management Control 16bit (R/W) */ +#define U300_SYSCON_PMCR (0x50) +#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002) +#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001) +/* Reset Out 16bit (R/W) */ +#define U300_SYSCON_RCR (0x6c) +#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001) +/* EMIF Slew Rate Control 16bit (R/W) */ +#define U300_SYSCON_SRCLR (0x70) +#define U300_SYSCON_SRCLR_MASK (0x03FF) +#define U300_SYSCON_SRCLR_VALUE (0x03FF) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002) +#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001) +/* EMIF Clock Control Register 16bit (R/W) */ +#define U300_SYSCON_ECCR (0x0078) +#define U300_SYSCON_ECCR_MASK (0x000F) +#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008) +#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004) +#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002) +#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001) +/* MMC/MSPRO frequency divider register 0 16bit (R/W) */ +#define U300_SYSCON_MMF0R (0x90) +#define U300_SYSCON_MMF0R_MASK (0x00FF) +#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F) +/* MMC/MSPRO frequency divider register 1 16bit (R/W) */ +#define U300_SYSCON_MMF1R (0x94) +#define U300_SYSCON_MMF1R_MASK (0x00FF) +#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0) +#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F) +/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */ +#define U300_SYSCON_MMCR (0x9C) +#define U300_SYSCON_MMCR_MASK (0x0003) +#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002) +#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001) +/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */ +#define U300_SYSCON_S0CCR (0x120) +#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000) +#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ +#define U300_SYSCON_S1CCR (0x124) +#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) +#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000) +#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ +#define U300_SYSCON_S2CCR (0x128) +#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) +#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) +#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000) +#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000) +#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200) +#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) +#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) +#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) +#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) +#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) +#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) +#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) +#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) +#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) +/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ +#define U300_SYSCON_PICR (0x0130) +#define U300_SYSCON_PICR_MASK (0x00FF) +#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080) +#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040) +#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020) +#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010) +#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008) +#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004) +#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002) +#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001) +/* SC_PLL_IRQ_STATUS 16 bit (R/-) */ +#define U300_SYSCON_PISR (0x0134) +#define U300_SYSCON_PISR_MASK (0x000F) +#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008) +#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004) +#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002) +#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001) +/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */ +#define U300_SYSCON_PICLR (0x0138) +#define U300_SYSCON_PICLR_MASK (0x000F) +#define U300_SYSCON_PICLR_RWMASK (0x0000) +#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008) +#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004) +#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002) +#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001) +/* Clock activity observability register 0 */ +#define U300_SYSCON_C0OAR (0x140) +#define U300_SYSCON_C0OAR_MASK (0xFFFF) +#define U300_SYSCON_C0OAR_VALUE (0xFFFF) +#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000) +#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000) +#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000) +#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000) +#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800) +#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400) +#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200) +#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100) +#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080) +#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040) +#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020) +#define U300_SYSCON_C0OAR_APEX_CLK (0x0010) +#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008) +#define U300_SYSCON_C0OAR_AHB_CLK (0x0004) +#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002) +#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001) +/* Clock activity observability register 1 */ +#define U300_SYSCON_C1OAR (0x144) +#define U300_SYSCON_C1OAR_MASK (0x3FFE) +#define U300_SYSCON_C1OAR_VALUE (0x3FFE) +#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000) +#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000) +#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800) +#define U300_SYSCON_C1OAR_MMC_CLK (0x0400) +#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200) +#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100) +#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080) +#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040) +#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020) +#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010) +#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008) +#define U300_SYSCON_C1OAR_PPM_CLK (0x0004) +#define U300_SYSCON_C1OAR_DMA_CLK (0x0002) +/* Clock activity observability register 2 */ +#define U300_SYSCON_C2OAR (0x148) +#define U300_SYSCON_C2OAR_MASK (0x0FFF) +#define U300_SYSCON_C2OAR_VALUE (0x0FFF) +#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800) +#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400) +#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200) +#define U300_SYSCON_C2OAR_VC_CLK (0x0100) +#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080) +#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040) +#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020) +#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010) +#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008) +#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004) +#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002) +#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001) + /* * The clocking hierarchy currently looks like this. -- cgit v1.2.3-70-g09d2 From 14c2607144c11653b27a423ead0703ffaa65d0b1 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 11:09:57 +0200 Subject: clk: move the U300 fixed and fixed-factor to DT This converts the fixed and fixed-factor clocks in the U300 platform to register themselves from the device tree. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-u300.dts | 44 ++++++++++++++++++++++++++++++++++++++++++ drivers/clk/clk-u300.c | 33 +++++++++++++------------------ 2 files changed, 57 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 644befd5ea8..203ec1fcbc1 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -33,6 +33,49 @@ syscon: syscon@c0011000 { compatible = "stericsson,u300-syscon"; reg = <0xc0011000 0x1000>; + clk32: app_32_clk@32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + pll13: pll13@13M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <13000000>; + }; + pll208: pll208@208M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <208000000>; + }; + app208: app_208_clk@208M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&pll208>; + }; + app104: app_104_clk@104M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll208>; + }; + app52: app_52_clk@52M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll208>; + }; + app26: app_26_clk@26M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <2>; + clock-mult = <1>; + clocks = <&app52>; + }; }; timer: timer@c0014000 { @@ -65,6 +108,7 @@ reg = <0xc0012000 0x1000>; interrupt-parent = <&vicb>; interrupts = <3>; + clocks = <&clk32>; }; rtc: rtc@c0017000 { diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index a41e42ec091..bebd6c973d4 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -11,6 +11,7 @@ #include #include #include +#include /* APP side SYSCON registers */ /* CLK Control Register 16bit (R/W) */ @@ -931,6 +932,17 @@ mclk_clk_register(struct device *dev, const char *name, return clk; } +static const __initconst struct of_device_id u300_clk_match[] = { + { + .compatible = "fixed-clock", + .data = of_fixed_clk_setup, + }, + { + .compatible = "fixed-factor-clock", + .data = of_fixed_factor_clk_setup, + }, +}; + void __init u300_clk_init(void __iomem *base) { u16 val; @@ -951,26 +963,7 @@ void __init u300_clk_init(void __iomem *base) val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE; writew(val, syscon_vbase + U300_SYSCON_PMCR); - /* These are always available (RTC and PLL13) */ - clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL, - CLK_IS_ROOT, 32768); - /* The watchdog sits directly on the 32 kHz clock */ - clk_register_clkdev(clk, NULL, "coh901327_wdog"); - clk = clk_register_fixed_rate(NULL, "pll13", NULL, - CLK_IS_ROOT, 13000000); - - /* These derive from PLL208 */ - clk = clk_register_fixed_rate(NULL, "pll208", NULL, - CLK_IS_ROOT, 208000000); - clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208", - 0, 1, 1); - clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208", - 0, 1, 2); - clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208", - 0, 1, 4); - /* The 52 MHz is divided down to 26 MHz */ - clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk", - 0, 1, 2); + of_clk_init(u300_clk_match); /* Directly on the AMBA interconnect */ clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true, -- cgit v1.2.3-70-g09d2 From 2165f836c8f7036491fae41e9bc327a3cdf2fea3 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 15:26:29 +0200 Subject: i2c: stu300: do not request a specific clock name We have used the default clock associated with the block for a long time, only heuristics in the clock system has made this work anyway. This needs to be done away with as we start probing this driver and its clocks exclusively from the device tree. Acked-by: Wolfram Sang Signed-off-by: Linus Walleij --- drivers/i2c/busses/i2c-stu300.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c index 1beaa05a3d2..d1a6b204af0 100644 --- a/drivers/i2c/busses/i2c-stu300.c +++ b/drivers/i2c/busses/i2c-stu300.c @@ -868,7 +868,6 @@ stu300_probe(struct platform_device *pdev) struct resource *res; int bus_nr; int ret = 0; - char clk_name[] = "I2C0"; dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL); if (!dev) { @@ -877,8 +876,7 @@ stu300_probe(struct platform_device *pdev) } bus_nr = pdev->id; - clk_name[3] += (char)bus_nr; - dev->clk = devm_clk_get(&pdev->dev, clk_name); + dev->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(dev->clk)) { dev_err(&pdev->dev, "could not retrieve i2c bus clock\n"); return PTR_ERR(dev->clk); -- cgit v1.2.3-70-g09d2 From bba5f2cc2f0fe4191ad2699c7c03a6def31f54e2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 15:42:33 +0200 Subject: ARM: u300: move the gated system controller clocks to DT This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- .../bindings/clock/ste-u300-syscon-clock.txt | 57 ++++ arch/arm/boot/dts/ste-u300.dts | 149 ++++++++++ arch/arm/mach-u300/timer.c | 2 +- drivers/clk/clk-u300.c | 320 ++++++++++++++------- 4 files changed, 418 insertions(+), 110 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt new file mode 100644 index 00000000000..b6a30f5eb58 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt @@ -0,0 +1,57 @@ +Clock bindings for ST-Ericsson U300 System Controller Clocks + +Bindings for the gated system controller clocks: + +Required properties: +- compatible: must be "stericsson,u300-syscon-clk" +- #clock-cells: must be <0> +- clock-type: specifies the type of clock: + 0 = slow clock + 1 = fast clock + 2 = rest/remaining clock +- clock-id: specifies the clock in the type range + +Optional properties: +- clocks: parent clock(s) + +The available clocks per type are as follows: + +Type: ID: Clock: +------------------- +0 0 Slow peripheral bridge clock +0 1 UART0 clock +0 4 GPIO clock +0 6 RTC clock +0 7 Application timer clock +0 8 Access timer clock + +1 0 Fast peripheral bridge clock +1 1 I2C bus 0 clock +1 2 I2C bus 1 clock +1 5 MMC interface peripheral (silicon) clock +1 6 SPI clock + +2 3 CPU clock +2 4 DMA controller clock +2 5 External Memory Interface (EMIF) clock +2 6 NAND flask interface clock +2 8 XGAM graphics engine clock +2 9 Shared External Memory Interface (SEMI) clock +2 10 AHB Subsystem Bridge clock +2 12 Interrupt controller clock + +Example: + +gpio_clk: gpio_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <4>; + clocks = <&slow_clk>; +}; + +gpio: gpio@c0016000 { + compatible = "stericsson,gpio-coh901"; + (...) + clocks = <&gpio_clk>; +}; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 203ec1fcbc1..7edc5e58a5a 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -43,6 +43,49 @@ compatible = "fixed-clock"; clock-frequency = <13000000>; }; + /* Slow bridge clocks under PLL13 */ + slow_clk: slow_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <0>; + clocks = <&pll13>; + }; + uart0_clk: uart0_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <1>; + clocks = <&slow_clk>; + }; + gpio_clk: gpio_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <4>; + clocks = <&slow_clk>; + }; + rtc_clk: rtc_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <6>; + clocks = <&slow_clk>; + }; + apptimer_clk: app_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <7>; + clocks = <&slow_clk>; + }; + acc_tmr_clk@13M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <0>; /* Slow */ + clock-id = <8>; + clocks = <&slow_clk>; + }; pll208: pll208@208M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -55,6 +98,13 @@ clock-mult = <1>; clocks = <&pll208>; }; + cpu_clk@208M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <3>; + clocks = <&app208>; + }; app104: app_104_clk@104M { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -62,6 +112,13 @@ clock-mult = <1>; clocks = <&pll208>; }; + semi_clk@104M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <9>; + clocks = <&app104>; + }; app52: app_52_clk@52M { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -69,6 +126,49 @@ clock-mult = <1>; clocks = <&pll208>; }; + /* AHB subsystem clocks */ + ahb_clk: ahb_subsys_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <10>; + clocks = <&app52>; + }; + intcon_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <12>; + clocks = <&ahb_clk>; + }; + emif_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <5>; + clocks = <&ahb_clk>; + }; + dmac_clk: dmac_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <4>; + clocks = <&app52>; + }; + fsmc_clk: fsmc_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <6>; + clocks = <&app52>; + }; + xgam_clk: xgam_clk@52M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <2>; /* Rest */ + clock-id = <8>; + clocks = <&app52>; + }; app26: app_26_clk@26M { #clock-cells = <0>; compatible = "fixed-factor-clock"; @@ -76,6 +176,42 @@ clock-mult = <1>; clocks = <&app52>; }; + /* Fast bridge clocks */ + fast_clk: fast_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <0>; + clocks = <&app26>; + }; + i2c0_clk: i2c0_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <1>; + clocks = <&fast_clk>; + }; + i2c1_clk: i2c1_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <2>; + clocks = <&fast_clk>; + }; + mmc_pclk: mmc_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <5>; + clocks = <&fast_clk>; + }; + spi_clk: spi_p_clk@26M { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-clk"; + clock-type = <1>; /* Fast */ + clock-id = <6>; + clocks = <&fast_clk>; + }; }; timer: timer@c0014000 { @@ -83,6 +219,7 @@ reg = <0xc0014000 0x1000>; interrupt-parent = <&vica>; interrupts = <24 25 26 27>; + clocks = <&apptimer_clk>; }; gpio: gpio@c0016000 { @@ -90,6 +227,7 @@ reg = <0xc0016000 0x1000>; interrupt-parent = <&vicb>; interrupts = <0 1 2 18 21 22 23>; + clocks = <&gpio_clk>; interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6"; interrupt-controller; @@ -116,6 +254,7 @@ reg = <0xc0017000 0x1000>; interrupt-parent = <&vicb>; interrupts = <10>; + clocks = <&rtc_clk>; }; dmac: dma-controller@c00020000 { @@ -125,6 +264,7 @@ interrupts = <2>; #dma-cells = <1>; dma-channels = <40>; + clocks = <&dmac_clk>; }; /* A NAND flash of 128 MiB */ @@ -138,6 +278,7 @@ <0x80010000 0x4000>; /* NAND Base CMD */ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; nand-skip-bbtscan; + clocks = <&fsmc_clk>; partition@0 { label = "boot records"; @@ -158,6 +299,7 @@ reg = <0xc0004000 0x1000>; interrupt-parent = <&vicb>; interrupts = <8>; + clocks = <&i2c0_clk>; #address-cells = <1>; #size-cells = <0>; ab3100: ab3100@0x48 { @@ -235,6 +377,7 @@ reg = <0xc0005000 0x1000>; interrupt-parent = <&vicb>; interrupts = <9>; + clocks = <&i2c1_clk>; #address-cells = <1>; #size-cells = <0>; fwcam0: fwcam@0x10 { @@ -270,6 +413,8 @@ reg = <0xc0013000 0x1000>; interrupt-parent = <&vica>; interrupts = <22>; + clocks = <&uart0_clk>, <&uart0_clk>; + clock-names = "apb_pclk", "uart0_clk"; dmas = <&dmac 17 &dmac 18>; dma-names = "tx", "rx"; }; @@ -288,6 +433,8 @@ reg = <0xc0001000 0x1000>; interrupt-parent = <&vicb>; interrupts = <6 7>; + clocks = <&mmc_pclk>; + clock-names = "apb_pclk"; max-frequency = <24000000>; bus-width = <4>; // SD-card slot mmc-cap-mmc-highspeed; @@ -304,6 +451,8 @@ reg = <0xc0006000 0x1000>; interrupt-parent = <&vica>; interrupts = <23>; + clocks = <&spi_clk>, <&spi_clk>; + clock-names = "apb_pclk", "spi_clk"; dmas = <&dmac 27 &dmac 28>; dma-names = "tx", "rx"; num-cs = <3>; diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c index 2e1c81daf3c..390ae5feb1d 100644 --- a/arch/arm/mach-u300/timer.c +++ b/arch/arm/mach-u300/timer.c @@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np) pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); /* Clock the interrupt controller */ - clk = clk_get_sys("apptimer", NULL); + clk = of_clk_get(np, 0); BUG_ON(IS_ERR(clk)); clk_prepare_enable(clk); rate = clk_get_rate(clk); diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index bebd6c973d4..5f234d37ccb 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name, return clk; } +#define U300_CLK_TYPE_SLOW 0 +#define U300_CLK_TYPE_FAST 1 +#define U300_CLK_TYPE_REST 2 + +/** + * struct u300_clock - defines the bits and pieces for a certain clock + * @type: the clock type, slow fast or rest + * @id: the bit in the slow/fast/rest register for this clock + * @hw_ctrld: whether the clock is hardware controlled + * @clk_val: a value to poke in the one-write enable/disable registers + */ +struct u300_clock { + u8 type; + u8 id; + bool hw_ctrld; + u16 clk_val; +}; + +struct u300_clock const __initconst u300_clk_lookup[] = { + { + .type = U300_CLK_TYPE_REST, + .id = 3, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 4, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 5, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 6, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 8, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 9, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 10, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN, + }, + { + .type = U300_CLK_TYPE_REST, + .id = 12, + .hw_ctrld = false, + /* INTCON: cannot be enabled, just taken out of reset */ + .clk_val = 0xFFFFU, + }, + { + .type = U300_CLK_TYPE_FAST, + .id = 0, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN, + }, + { + .type = U300_CLK_TYPE_FAST, + .id = 1, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN, + }, + { + .type = U300_CLK_TYPE_FAST, + .id = 2, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN, + }, + { + .type = U300_CLK_TYPE_FAST, + .id = 5, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN, + }, + { + .type = U300_CLK_TYPE_FAST, + .id = 6, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 0, + .hw_ctrld = true, + .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 1, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_UART_CLK_EN, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 4, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 6, + .hw_ctrld = true, + /* No clock enable register bit */ + .clk_val = 0xFFFFU, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 7, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN, + }, + { + .type = U300_CLK_TYPE_SLOW, + .id = 8, + .hw_ctrld = false, + .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN, + }, +}; + +static void __init of_u300_syscon_clk_init(struct device_node *np) +{ + struct clk *clk = ERR_PTR(-EINVAL); + const char *clk_name = np->name; + const char *parent_name; + void __iomem *res_reg; + void __iomem *en_reg; + u32 clk_type; + u32 clk_id; + int i; + + if (of_property_read_u32(np, "clock-type", &clk_type)) { + pr_err("%s: syscon clock \"%s\" missing clock-type property\n", + __func__, clk_name); + return; + } + if (of_property_read_u32(np, "clock-id", &clk_id)) { + pr_err("%s: syscon clock \"%s\" missing clock-id property\n", + __func__, clk_name); + return; + } + parent_name = of_clk_get_parent_name(np, 0); + + switch (clk_type) { + case U300_CLK_TYPE_SLOW: + res_reg = syscon_vbase + U300_SYSCON_RSR; + en_reg = syscon_vbase + U300_SYSCON_CESR; + break; + case U300_CLK_TYPE_FAST: + res_reg = syscon_vbase + U300_SYSCON_RFR; + en_reg = syscon_vbase + U300_SYSCON_CEFR; + break; + case U300_CLK_TYPE_REST: + res_reg = syscon_vbase + U300_SYSCON_RRR; + en_reg = syscon_vbase + U300_SYSCON_CERR; + break; + default: + pr_err("unknown clock type %x specified\n", clk_type); + return; + } + + for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) { + const struct u300_clock *u3clk = &u300_clk_lookup[i]; + + if (u3clk->type == clk_type && u3clk->id == clk_id) + clk = syscon_clk_register(NULL, + clk_name, parent_name, + 0, u3clk->hw_ctrld, + res_reg, u3clk->id, + en_reg, u3clk->id, + u3clk->clk_val); + } + + if (!IS_ERR(clk)) { + of_clk_add_provider(np, of_clk_src_simple_get, clk); + + /* + * Some few system clocks - device tree does not + * represent clocks without a corresponding device node. + * for now we add these three clocks here. + */ + if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) + clk_register_clkdev(clk, NULL, "pl172"); + if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) + clk_register_clkdev(clk, NULL, "semi"); + if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) + clk_register_clkdev(clk, NULL, "intcon"); + } +} + /** * struct clk_mclk - U300 MCLK clock (MMC/SD clock) * @hw: corresponding clock hardware entry @@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = { .compatible = "fixed-factor-clock", .data = of_fixed_factor_clk_setup, }, + { + .compatible = "stericsson,u300-syscon-clk", + .data = of_u300_syscon_clk_init, + }, }; void __init u300_clk_init(void __iomem *base) @@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base) of_clk_init(u300_clk_match); - /* Directly on the AMBA interconnect */ - clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true, - syscon_vbase + U300_SYSCON_RRR, 3, - syscon_vbase + U300_SYSCON_CERR, 3, - U300_SYSCON_SBCER_CPU_CLK_EN); - clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true, - syscon_vbase + U300_SYSCON_RRR, 4, - syscon_vbase + U300_SYSCON_CERR, 4, - U300_SYSCON_SBCER_DMAC_CLK_EN); - clk_register_clkdev(clk, NULL, "dma"); - clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false, - syscon_vbase + U300_SYSCON_RRR, 6, - syscon_vbase + U300_SYSCON_CERR, 6, - U300_SYSCON_SBCER_NANDIF_CLK_EN); - clk_register_clkdev(clk, NULL, "fsmc-nand"); - clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true, - syscon_vbase + U300_SYSCON_RRR, 8, - syscon_vbase + U300_SYSCON_CERR, 8, - U300_SYSCON_SBCER_XGAM_CLK_EN); - clk_register_clkdev(clk, NULL, "xgam"); - clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false, - syscon_vbase + U300_SYSCON_RRR, 9, - syscon_vbase + U300_SYSCON_CERR, 9, - U300_SYSCON_SBCER_SEMI_CLK_EN); - clk_register_clkdev(clk, NULL, "semi"); - - /* AHB bridge clocks */ - clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true, - syscon_vbase + U300_SYSCON_RRR, 10, - syscon_vbase + U300_SYSCON_CERR, 10, - U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN); - clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false, - syscon_vbase + U300_SYSCON_RRR, 12, - syscon_vbase + U300_SYSCON_CERR, 12, - /* Cannot be enabled, just taken out of reset */ - 0xFFFFU); - clk_register_clkdev(clk, NULL, "intcon"); - clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false, - syscon_vbase + U300_SYSCON_RRR, 5, - syscon_vbase + U300_SYSCON_CERR, 5, - U300_SYSCON_SBCER_EMIF_CLK_EN); - clk_register_clkdev(clk, NULL, "pl172"); - - /* FAST bridge clocks */ - clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true, - syscon_vbase + U300_SYSCON_RFR, 0, - syscon_vbase + U300_SYSCON_CEFR, 0, - U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN); - clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false, - syscon_vbase + U300_SYSCON_RFR, 1, - syscon_vbase + U300_SYSCON_CEFR, 1, - U300_SYSCON_SBCER_I2C0_CLK_EN); - clk_register_clkdev(clk, NULL, "stu300.0"); - clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false, - syscon_vbase + U300_SYSCON_RFR, 2, - syscon_vbase + U300_SYSCON_CEFR, 2, - U300_SYSCON_SBCER_I2C1_CLK_EN); - clk_register_clkdev(clk, NULL, "stu300.1"); - clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false, - syscon_vbase + U300_SYSCON_RFR, 5, - syscon_vbase + U300_SYSCON_CEFR, 5, - U300_SYSCON_SBCER_MMC_CLK_EN); - clk_register_clkdev(clk, "apb_pclk", "mmci"); - clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false, - syscon_vbase + U300_SYSCON_RFR, 6, - syscon_vbase + U300_SYSCON_CEFR, 6, - U300_SYSCON_SBCER_SPI_CLK_EN); - /* The SPI has no external clock for the outward bus, uses the pclk */ - clk_register_clkdev(clk, NULL, "pl022"); - clk_register_clkdev(clk, "apb_pclk", "pl022"); - - /* SLOW bridge clocks */ - clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true, - syscon_vbase + U300_SYSCON_RSR, 0, - syscon_vbase + U300_SYSCON_CESR, 0, - U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN); - clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false, - syscon_vbase + U300_SYSCON_RSR, 1, - syscon_vbase + U300_SYSCON_CESR, 1, - U300_SYSCON_SBCER_UART_CLK_EN); - /* Same clock is used for APB and outward bus */ - clk_register_clkdev(clk, NULL, "uart0"); - clk_register_clkdev(clk, "apb_pclk", "uart0"); - clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false, - syscon_vbase + U300_SYSCON_RSR, 4, - syscon_vbase + U300_SYSCON_CESR, 4, - U300_SYSCON_SBCER_GPIO_CLK_EN); - clk_register_clkdev(clk, NULL, "u300-gpio"); - clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false, - syscon_vbase + U300_SYSCON_RSR, 5, - syscon_vbase + U300_SYSCON_CESR, 6, - U300_SYSCON_SBCER_KEYPAD_CLK_EN); - clk_register_clkdev(clk, NULL, "coh901461-keypad"); - clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true, - syscon_vbase + U300_SYSCON_RSR, 6, - /* No clock enable register bit */ - NULL, 0, 0xFFFFU); - clk_register_clkdev(clk, NULL, "rtc-coh901331"); - clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false, - syscon_vbase + U300_SYSCON_RSR, 7, - syscon_vbase + U300_SYSCON_CESR, 7, - U300_SYSCON_SBCER_APP_TMR_CLK_EN); - clk_register_clkdev(clk, NULL, "apptimer"); - clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false, - syscon_vbase + U300_SYSCON_RSR, 8, - syscon_vbase + U300_SYSCON_CESR, 8, - U300_SYSCON_SBCER_ACC_TMR_CLK_EN); - clk_register_clkdev(clk, NULL, "timer"); - /* Then this special MMC/SD clock */ clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false); clk_register_clkdev(clk, NULL, "mmci"); -- cgit v1.2.3-70-g09d2 From 85fb28bed813469ba56706a7e48fba596f47c253 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 19:18:28 +0200 Subject: ARM: u300: convert MMC/SD clock to device tree This converts the last of the U300 clocks to being probed from the device tree. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- .../bindings/clock/ste-u300-syscon-clock.txt | 23 ++++++++++++++++++++++ arch/arm/boot/dts/ste-u300.dts | 9 +++++++-- drivers/clk/clk-u300.c | 22 ++++++++++++++++----- 3 files changed, 47 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt index b6a30f5eb58..7cafcb98ead 100644 --- a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt +++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt @@ -55,3 +55,26 @@ gpio: gpio@c0016000 { (...) clocks = <&gpio_clk>; }; + + +Bindings for the MMC/SD card clock: + +Required properties: +- compatible: must be "stericsson,u300-syscon-mclk" +- #clock-cells: must be <0> + +Optional properties: +- clocks: parent clock(s) + +mmc_mclk: mmc_mclk { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-mclk"; + clocks = <&mmc_pclk>; +}; + +mmcsd: mmcsd@c0001000 { + compatible = "arm,pl18x", "arm,primecell"; + clocks = <&mmc_pclk>, <&mmc_mclk>; + clock-names = "apb_pclk", "mclk"; + (...) +}; diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts index 7edc5e58a5a..05a082164c1 100644 --- a/arch/arm/boot/dts/ste-u300.dts +++ b/arch/arm/boot/dts/ste-u300.dts @@ -205,6 +205,11 @@ clock-id = <5>; clocks = <&fast_clk>; }; + mmc_mclk: mmc_mclk { + #clock-cells = <0>; + compatible = "stericsson,u300-syscon-mclk"; + clocks = <&mmc_pclk>; + }; spi_clk: spi_p_clk@26M { #clock-cells = <0>; compatible = "stericsson,u300-syscon-clk"; @@ -433,8 +438,8 @@ reg = <0xc0001000 0x1000>; interrupt-parent = <&vicb>; interrupts = <6 7>; - clocks = <&mmc_pclk>; - clock-names = "apb_pclk"; + clocks = <&mmc_pclk>, <&mmc_mclk>; + clock-names = "apb_pclk", "mclk"; max-frequency = <24000000>; bus-width = <4>; // SD-card slot mmc-cap-mmc-highspeed; diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c index 5f234d37ccb..8774e058cb6 100644 --- a/drivers/clk/clk-u300.c +++ b/drivers/clk/clk-u300.c @@ -1139,6 +1139,18 @@ mclk_clk_register(struct device *dev, const char *name, return clk; } +static void __init of_u300_syscon_mclk_init(struct device_node *np) +{ + struct clk *clk = ERR_PTR(-EINVAL); + const char *clk_name = np->name; + const char *parent_name; + + parent_name = of_clk_get_parent_name(np, 0); + clk = mclk_clk_register(NULL, clk_name, parent_name, false); + if (!IS_ERR(clk)) + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} + static const __initconst struct of_device_id u300_clk_match[] = { { .compatible = "fixed-clock", @@ -1152,12 +1164,16 @@ static const __initconst struct of_device_id u300_clk_match[] = { .compatible = "stericsson,u300-syscon-clk", .data = of_u300_syscon_clk_init, }, + { + .compatible = "stericsson,u300-syscon-mclk", + .data = of_u300_syscon_mclk_init, + }, }; + void __init u300_clk_init(void __iomem *base) { u16 val; - struct clk *clk; syscon_vbase = base; @@ -1175,8 +1191,4 @@ void __init u300_clk_init(void __iomem *base) writew(val, syscon_vbase + U300_SYSCON_PMCR); of_clk_init(u300_clk_match); - - /* Then this special MMC/SD clock */ - clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false); - clk_register_clkdev(clk, NULL, "mmci"); } -- cgit v1.2.3-70-g09d2 From b263e9b88746c6902c36d35a2dd83c119f8510a2 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 20:09:43 +0200 Subject: pinctrl: get rid of all platform data for coh901 This deletes the dependency on any platform data for the COH901 pin controller. There is only one user in the kernel, and if we at some point want to support more variants, they shall provide their variant info through the device tree. Signed-off-by: Linus Walleij --- arch/arm/mach-u300/core.c | 12 +----------- drivers/pinctrl/pinctrl-coh901.c | 23 +++++++++-------------- include/linux/platform_data/pinctrl-coh901.h | 22 ---------------------- 3 files changed, 10 insertions(+), 47 deletions(-) delete mode 100644 include/linux/platform_data/pinctrl-coh901.h (limited to 'drivers') diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c index 6e5744a2b85..4f7ac2a1145 100644 --- a/arch/arm/mach-u300/core.c +++ b/arch/arm/mach-u300/core.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -194,15 +193,6 @@ static void __init u300_map_io(void) iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); } -/* - * The different variants have a few different versions of the - * GPIO block, with different number of ports. - */ -static struct u300_gpio_platform u300_gpio_plat = { - .ports = 7, - .gpio_base = 0, -}; - static unsigned long pin_pullup_conf[] = { PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1), }; @@ -332,7 +322,7 @@ static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE, "pinctrl-u300", NULL), OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE, - "u300-gpio", &u300_gpio_plat), + "u300-gpio", NULL), OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE, "coh901327_wdog", NULL), OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE, diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c index d4f8afdad1a..46ff140cfa7 100644 --- a/drivers/pinctrl/pinctrl-coh901.c +++ b/drivers/pinctrl/pinctrl-coh901.c @@ -22,7 +22,6 @@ #include #include #include -#include #include "pinctrl-coh901.h" #define U300_GPIO_PORT_STRIDE (0x30) @@ -58,8 +57,9 @@ #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) /* 8 bits per port, no version has more than 7 ports */ +#define U300_GPIO_NUM_PORTS 7 #define U300_GPIO_PINS_PER_PORT 8 -#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7) +#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) struct u300_gpio { struct gpio_chip chip; @@ -111,9 +111,6 @@ struct u300_gpio_confdata { int outval; }; -/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ -#define BS335_GPIO_NUM_PORTS 7 - #define U300_FLOATING_INPUT { \ .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ .output = false, \ @@ -136,7 +133,7 @@ struct u300_gpio_confdata { /* Initial configuration */ static const struct __initconst u300_gpio_confdata -bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { +bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { /* Port 0, pins 0-7 */ { U300_FLOATING_INPUT, @@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio, } } -static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio, - struct u300_gpio_platform *plat) +static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) { int i, j; /* Write default config and values to all pins */ - for (i = 0; i < plat->ports; i++) { + for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { for (j = 0; j < 8; j++) { const struct u300_gpio_confdata *conf; int offset = (i*8) + j; @@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = { static int __init u300_gpio_probe(struct platform_device *pdev) { - struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev); struct u300_gpio *gpio; struct resource *memres; int err = 0; @@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev) return -ENOMEM; gpio->chip = u300_gpio_chip; - gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT; + gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; gpio->chip.dev = &pdev->dev; - gpio->chip.base = plat->gpio_base; + gpio->chip.base = 0; gpio->dev = &pdev->dev; memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -755,11 +750,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev) ((val & 0x0000FE00) >> 9) * 8); writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, gpio->base + U300_GPIO_CR); - u300_gpio_init_coh901571(gpio, plat); + u300_gpio_init_coh901571(gpio); /* Add each port with its IRQ separately */ INIT_LIST_HEAD(&gpio->port_list); - for (portno = 0 ; portno < plat->ports; portno++) { + for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { struct u300_gpio_port *port = kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL); diff --git a/include/linux/platform_data/pinctrl-coh901.h b/include/linux/platform_data/pinctrl-coh901.h deleted file mode 100644 index dfbc65d1048..00000000000 --- a/include/linux/platform_data/pinctrl-coh901.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2007-2012 ST-Ericsson AB - * License terms: GNU General Public License (GPL) version 2 - * GPIO block resgister definitions and inline macros for - * U300 GPIO COH 901 335 or COH 901 571/3 - * Author: Linus Walleij - */ - -#ifndef __MACH_U300_GPIO_U300_H -#define __MACH_U300_GPIO_U300_H - -/** - * struct u300_gpio_platform - U300 GPIO platform data - * @ports: number of GPIO block ports - * @gpio_base: first GPIO number for this block (use a free range) - */ -struct u300_gpio_platform { - u8 ports; - int gpio_base; -}; - -#endif /* __MACH_U300_GPIO_U300_H */ -- cgit v1.2.3-70-g09d2 From dbd897b9c6fac8bcb38e378e12c2790f293ae1fe Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 23 May 2013 19:46:40 +0200 Subject: spi: pl022: use DMA by default when probing from DT In the past we controlled the selection of DMA for a certain host by a boolean switch in the platform data. Currently there is no way to enable DMA on a PL022 probed from the device tree. Let's default to trying to obtain DMA channels in the DT case, and then we can always fail (and thus fall back to PIO mode). Signed-off-by: Linus Walleij --- drivers/spi/spi-pl022.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index 371cc66f1a0..3b246543282 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -2083,6 +2083,7 @@ pl022_platform_data_dt_get(struct device *dev) } pd->bus_id = -1; + pd->enable_dma = 1; of_property_read_u32(np, "num-cs", &tmp); pd->num_chipselect = tmp; of_property_read_u32(np, "pl022,autosuspend-delay", -- cgit v1.2.3-70-g09d2