From fa43cd8b100e9c6182f872d0fc4bb3964e100808 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 13 Nov 2007 00:31:33 +0800 Subject: Blackfin arch: add a compatible DOUBLE_FAULT define to enable resets on double faults in either core Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf561/defBF561.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) (limited to 'include/asm-blackfin/mach-bf561/defBF561.h') diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 7945e8a3a84..66f19960844 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -55,6 +55,7 @@ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ #define SWRST SICA_SWRST #define SYSCR SICA_SYSCR +#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A) #define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) #define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) #define RESET_SOFTWARE (SWRST_OCCURRED) @@ -877,12 +878,14 @@ #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* SWRST Mask */ -#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ -#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ -#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ -#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ -#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ -#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ +#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ +#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ +#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ +#define SWRST_DBL_FAULT_B 0x0800 /* SWRST Core B Double Fault */ +#define SWRST_DBL_FAULT_A 0x1000 /* SWRST Core A Double Fault */ +#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ +#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ +#define SWRST_OCCURRED 0x8000 /* SWRST Status */ /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ -- cgit v1.2.3-70-g09d2 From b33d51877726b066699b9ee40b5f512c77bdca38 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Thu, 15 Nov 2007 21:15:47 +0800 Subject: Blackfin arch: fix double fault definition for BF561 core A and core B VDSP has double fault on core a/b inverted for BF561 -- bit 11 is core a while bit 12 is core b Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- include/asm-blackfin/mach-bf561/defBF561.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/asm-blackfin/mach-bf561/defBF561.h') diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index 66f19960844..c3c0eb13c81 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -881,8 +881,8 @@ #define SYSTEM_RESET 0x0007 /* Initiates a system software reset */ #define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */ #define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */ -#define SWRST_DBL_FAULT_B 0x0800 /* SWRST Core B Double Fault */ -#define SWRST_DBL_FAULT_A 0x1000 /* SWRST Core A Double Fault */ +#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */ +#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */ #define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */ #define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */ #define SWRST_OCCURRED 0x8000 /* SWRST Status */ -- cgit v1.2.3-70-g09d2