From 1d67953f2bda8876045c24ae58841f27d9bb7572 Mon Sep 17 00:00:00 2001 From: Venki Pallipadi Date: Wed, 11 Jul 2007 12:18:32 -0700 Subject: Use a new CPU feature word to cover features that are spread around Some Intel features are spread around in different CPUID leafs like 0x5, 0x6 and 0xA. Make this feature detection code common across i386 and x86_64. Display Intel Dynamic Acceleration feature in /proc/cpuinfo. This feature will be enabled automatically by current acpi-cpufreq driver. Refer to Intel Software Developer's Manual for more details about the feature. Thanks to hpa (H Peter Anvin) for the making the actual code detecting the scattered features data-driven. Signed-off-by: Venkatesh Pallipadi Signed-off-by: H. Peter Anvin Signed-off-by: Linus Torvalds --- include/asm-i386/cpufeature.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'include/asm-i386/cpufeature.h') diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index 7ea5f4a6706..c961c03cf1e 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -12,7 +12,7 @@ #endif #include -#define NCAPINTS 7 /* N 32-bit words worth of info */ +#define NCAPINTS 8 /* N 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ @@ -109,6 +109,12 @@ #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ +/* + * Auxiliary flags: Linux defined - For features scattered in various + * CPUID levels like 0x6, 0xA etc + */ +#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ + #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && \ ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ @@ -117,7 +123,8 @@ (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ - (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) ) \ + (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ + (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ ? 1 : \ test_bit(bit, (c)->x86_capability)) #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) -- cgit v1.2.3-70-g09d2