From bbad8123f3a40a7b262e8e52d0bc10da67d719bb Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Wed, 15 Feb 2006 13:06:34 +0000
Subject: [MIPS] MIPS64 R2 optimizations for 64-bit endianess swapping.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
include/asm-mips/byteorder.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
(limited to 'include/asm-mips/byteorder.h')
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
index 584f8128fff..aefc02f16fd 100644
--- a/include/asm-mips/byteorder.h
+++ b/include/asm-mips/byteorder.h
@@ -39,6 +39,24 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
}
#define __arch__swab32(x) ___arch__swab32(x)
+#ifdef CONFIG_CPU_MIPS64_R2
+
+static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
+{
+ __asm__(
+ " dsbh %0, %1 \n"
+ " dshd %0, %0 \n"
+ " drotr %0, %0, 32 \n"
+ : "=r" (x)
+ : "r" (x));
+
+ return x;
+}
+
+#define __arch__swab64(x) ___arch__swab64(x)
+
+#endif /* CONFIG_CPU_MIPS64_R2 */
+
#endif /* CONFIG_CPU_MIPSR2 */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
--
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