From fc5d2d279ff820172a698706d33e733d4578bd6c Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 6 Jul 2006 13:04:01 +0100 Subject: [MIPS] Use the proper technical term for naming some of the cache macros. Signed-off-by: Ralf Baechle --- include/asm-mips/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/asm-mips/cpu.h') diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dff2a0a52f8..d38fdbf845b 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -242,7 +242,7 @@ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ -- cgit v1.2.3-70-g09d2