From f629b38beddf2ff8bc3fda1754bbd6cc7d3acc03 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Sat, 26 Apr 2008 22:25:22 +0200 Subject: au1xxx-ide: fix MWDMA support Always use "fast" MWDMA support and remove dma_{black,white}_list (they were based on completely bogus ->ide_dma_check implementation which didn't set neither the host controller timings nor the device for the desired transfer mode). Signed-off-by: Bartlomiej Zolnierkiewicz --- include/asm-mips/mach-au1x00/au1xxx_ide.h | 42 ------------------------------- 1 file changed, 42 deletions(-) (limited to 'include/asm-mips/mach-au1x00') diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h index 89655c0cdcd..b493a5e46c6 100644 --- a/include/asm-mips/mach-au1x00/au1xxx_ide.h +++ b/include/asm-mips/mach-au1x00/au1xxx_ide.h @@ -70,7 +70,6 @@ typedef struct ide_hwif_t *hwif; #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA ide_drive_t *drive; - u8 white_list, black_list; struct dbdma_cmd *dma_table_cpu; dma_addr_t dma_table_dma; #endif @@ -81,47 +80,6 @@ typedef struct #endif } _auide_hwif; -#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA -/* HD white list */ -static const struct drive_list_entry dma_white_list [] = { -/* - * Hitachi - */ - { "HITACHI_DK14FA-20" , NULL }, - { "HTS726060M9AT00" , NULL }, -/* - * Maxtor - */ - { "Maxtor 6E040L0" , NULL }, - { "Maxtor 6Y080P0" , NULL }, - { "Maxtor 6Y160P0" , NULL }, -/* - * Seagate - */ - { "ST3120026A" , NULL }, - { "ST320014A" , NULL }, - { "ST94011A" , NULL }, - { "ST340016A" , NULL }, -/* - * Western Digital - */ - { "WDC WD400UE-00HCT0" , NULL }, - { "WDC WD400JB-00JJC0" , NULL }, - { NULL , NULL } -}; - -/* HD black list */ -static const struct drive_list_entry dma_black_list [] = { -/* - * Western Digital - */ - { "WDC WD100EB-00CGH0" , NULL }, - { "WDC WD200BB-00AUA1" , NULL }, - { "WDC AC24300L" , NULL }, - { NULL , NULL } -}; -#endif - /******************************************************************************* * PIO Mode timing calculation : * * * -- cgit v1.2.3-70-g09d2 From 0167509574ef1cdb516906db5e8b6ad5ca64ab61 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 24 Mar 2008 23:15:50 +0300 Subject: [MIPS] Alchemy: don't unmask timer IRQ early Defer the unmasking of the count/compare interrupt (IRQ5) till the clockevent driver initialization: - only enable the cascaded IRQs 0 thru 4 in arch_init_irq(); kill the ALLINTS macro -- this change is blessed by AMD as I saw it in their own patch; :-) - do not force IRQ5 enabled in plat_time_init() if PM is enabled and there's no 32 KHz crystal. Update the copyrights (taking into account my prior changes), also removing Pete Popov's old email... Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- arch/mips/au1000/common/irq.c | 7 +++---- arch/mips/au1000/common/time.c | 8 ++------ include/asm-mips/mach-au1x00/au1000.h | 12 ++---------- 3 files changed, 7 insertions(+), 20 deletions(-) (limited to 'include/asm-mips/mach-au1x00') diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 3c7714f057a..5528e1412b5 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -1,7 +1,6 @@ /* - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2001, 2007-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) * @@ -591,7 +590,7 @@ void __init arch_init_irq(void) imp++; } - set_c0_status(ALLINTS); + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); /* Board specific IRQ initialization. */ diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index e122bbc6cd8..1966964590a 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com + * Copyright (C) 2001, 2006, 2008 MontaVista Software, * Copied and modified Carsten Langgaard's time.c * * Carsten Langgaard, carstenl@mips.com @@ -265,12 +265,8 @@ void __init plat_time_init(void) * Check to ensure we really have a 32KHz oscillator before * we do this. */ - if (no_au1xxx_32khz) { + if (no_au1xxx_32khz) printk("WARNING: no 32KHz clock found.\n"); - - /* Ensure we get CPO_COUNTER interrupts. */ - set_c0_status(IE_IRQ5); - } else { while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); au_writel(0, SYS_TOYWRITE); diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 5bb57bf2b9d..a88637a93e0 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -3,9 +3,8 @@ * BRIEF MODULE DESCRIPTION * Include file for Alchemy Semiconductor's Au1k CPU. * - * Copyright 2000,2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com + * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. + * Author: MontaVista Software, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -117,13 +116,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[]; #endif /* !defined (_LANGUAGE_ASSEMBLY) */ -#ifdef CONFIG_PM -/* no CP0 timer irq */ -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) -#else -#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) -#endif - /* * SDRAM Register Offsets */ -- cgit v1.2.3-70-g09d2 From 6ed436932d1417534aa1a738fd9585795f954304 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 22 Apr 2008 23:28:57 +0400 Subject: [MIPS] Alchemy: kill unused PCI_IRQ_TABLE_LOOKUP macro Signed-off-by: Sergei Shtylyov Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/au1000.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'include/asm-mips/mach-au1x00') diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index a88637a93e0..a05555165d0 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1685,20 +1685,6 @@ enum soc_au1200_ints { #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff - /* - * Borrowed from the PPC arch: - * The following macro is used to lookup irqs in a standard table - * format for those PPC systems that do not already have PCI - * interrupts properly routed. - */ - /* FIXME - double check this from asm-ppc/pci-bridge.h */ -#define PCI_IRQ_TABLE_LOOKUP \ - ({ long _ctl_ = -1; \ - if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ - _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ - _ctl_; }) - - #else /* Au1000 and Au1100 and Au1200 */ /* don't allow any legacy ports probing */ -- cgit v1.2.3-70-g09d2