From 1c0c13eb935c95fd2ca0b0aca6dd4860487fb242 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:40:12 +0200 Subject: [MIPS] Add support for BCM47XX CPUs. Note that the BCM4710 does not support the wait instruction, this is not a mistake in the code. It originally comes from the OpenWrt patches. Cc: Michael Buesch Cc: Felix Fietkau Cc: Florian Schirmer Signed-off-by: Aurelien Jarno Signed-off-by: Andrew Morton Signed-off-by: Ralf Baechle --- include/asm-mips/mach-bcm47xx/bcm47xx.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 include/asm-mips/mach-bcm47xx/bcm47xx.h (limited to 'include/asm-mips/mach-bcm47xx') diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h new file mode 100644 index 00000000000..a2fb5e8dd6c --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2007 Aurelien Jarno + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef __ASM_BCM47XX_H +#define __ASM_BCM47XX_H + +/* SSB bus */ +extern struct ssb_bus ssb_bcm47xx; + +extern void bcm47xx_time_init(void); + +#endif /* __ASM_BCM47XX_H */ -- cgit v1.2.3-70-g09d2 From 34cc662f8aae0ce1db5c64d55a39a5081f9e3cd8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 25 Sep 2007 15:42:09 +0200 Subject: [MIPS] Add gpio support to the BCM47XX platform Add GPIO support to the BCM47XX platform. It will be used by a GPIO LED driver. Signed-off-by: Aurelien Jarno Signed-off-by: Ralf Baechle --- arch/mips/bcm47xx/Makefile | 2 +- arch/mips/bcm47xx/gpio.c | 79 ++++++++++++++++++++++++++++++++++++ include/asm-mips/mach-bcm47xx/gpio.h | 59 +++++++++++++++++++++++++++ 3 files changed, 139 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm47xx/gpio.c create mode 100644 include/asm-mips/mach-bcm47xx/gpio.h (limited to 'include/asm-mips/mach-bcm47xx') diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile index dc035f90d36..0afe09703e3 100644 --- a/arch/mips/bcm47xx/Makefile +++ b/arch/mips/bcm47xx/Makefile @@ -3,4 +3,4 @@ # under Linux. # -obj-y := irq.o prom.o serial.o setup.o time.o +obj-y := gpio.o irq.o prom.o serial.o setup.o time.o diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c new file mode 100644 index 00000000000..f5a53acf995 --- /dev/null +++ b/arch/mips/bcm47xx/gpio.c @@ -0,0 +1,79 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#include +#include +#include +#include +#include + +int bcm47xx_gpio_to_irq(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev) + return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; + else if (ssb_bcm47xx.extif.dev) + return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; + else + return -EINVAL; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq); + +int bcm47xx_gpio_get_value(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev) + return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio); + else if (ssb_bcm47xx.extif.dev) + return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio); + else + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value); + +void bcm47xx_gpio_set_value(unsigned gpio, int value) +{ + if (ssb_bcm47xx.chipco.dev) + ssb_chipco_gpio_out(&ssb_bcm47xx.chipco, + 1 << gpio, + value ? 1 << gpio : 0); + else if (ssb_bcm47xx.extif.dev) + ssb_extif_gpio_out(&ssb_bcm47xx.extif, + 1 << gpio, + value ? 1 << gpio : 0); +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value); + +int bcm47xx_gpio_direction_input(unsigned gpio) +{ + if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES)) + ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco, + 1 << gpio, 0); + else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES)) + ssb_extif_gpio_outen(&ssb_bcm47xx.extif, + 1 << gpio, 0); + else + return -EINVAL; + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input); + +int bcm47xx_gpio_direction_output(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); + + if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES)) + ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco, + 1 << gpio, 1 << gpio); + else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES)) + ssb_extif_gpio_outen(&ssb_bcm47xx.extif, + 1 << gpio, 1 << gpio); + else + return -EINVAL; + return 0; +} +EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output); + diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h new file mode 100644 index 00000000000..cfc8f4d618c --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/gpio.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 Aurelien Jarno + */ + +#ifndef __BCM47XX_GPIO_H +#define __BCM47XX_GPIO_H + +#define BCM47XX_EXTIF_GPIO_LINES 5 +#define BCM47XX_CHIPCO_GPIO_LINES 16 + +extern int bcm47xx_gpio_to_irq(unsigned gpio); +extern int bcm47xx_gpio_get_value(unsigned gpio); +extern void bcm47xx_gpio_set_value(unsigned gpio, int value); +extern int bcm47xx_gpio_direction_input(unsigned gpio); +extern int bcm47xx_gpio_direction_output(unsigned gpio, int value); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return bcm47xx_gpio_to_irq(gpio); +} + +static inline int gpio_get_value(unsigned gpio) +{ + return bcm47xx_gpio_get_value(gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + bcm47xx_gpio_set_value(gpio, value); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + return bcm47xx_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + return bcm47xx_gpio_direction_output(gpio, value); +} + + +/* cansleep wrappers */ +#include + +#endif /* __BCM47XX_GPIO_H */ -- cgit v1.2.3-70-g09d2 From baf22c1e7aedf264e264b15d2595e5e76564bd4e Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 11 Oct 2007 23:46:07 +0100 Subject: [MIPS] Split up war.h It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle --- include/asm-mips/mach-au1x00/war.h | 25 +++++++ include/asm-mips/mach-bcm47xx/war.h | 25 +++++++ include/asm-mips/mach-cobalt/war.h | 25 +++++++ include/asm-mips/mach-dec/war.h | 25 +++++++ include/asm-mips/mach-emma2rh/war.h | 25 +++++++ include/asm-mips/mach-excite/war.h | 25 +++++++ include/asm-mips/mach-ip22/war.h | 29 ++++++++ include/asm-mips/mach-ip27/war.h | 25 +++++++ include/asm-mips/mach-ip32/war.h | 25 +++++++ include/asm-mips/mach-jazz/war.h | 25 +++++++ include/asm-mips/mach-jmr3927/war.h | 25 +++++++ include/asm-mips/mach-lasat/war.h | 25 +++++++ include/asm-mips/mach-lemote/war.h | 25 +++++++ include/asm-mips/mach-mips/war.h | 25 +++++++ include/asm-mips/mach-mipssim/war.h | 25 +++++++ include/asm-mips/mach-pnx8550/war.h | 25 +++++++ include/asm-mips/mach-qemu/war.h | 25 +++++++ include/asm-mips/mach-rm/war.h | 29 ++++++++ include/asm-mips/mach-sibyte/war.h | 37 ++++++++++ include/asm-mips/mach-tx49xx/war.h | 25 +++++++ include/asm-mips/mach-vr41xx/war.h | 25 +++++++ include/asm-mips/mach-wrppmc/war.h | 25 +++++++ include/asm-mips/mach-yosemite/war.h | 25 +++++++ include/asm-mips/war.h | 127 +++++++++-------------------------- 24 files changed, 625 insertions(+), 97 deletions(-) create mode 100644 include/asm-mips/mach-au1x00/war.h create mode 100644 include/asm-mips/mach-bcm47xx/war.h create mode 100644 include/asm-mips/mach-cobalt/war.h create mode 100644 include/asm-mips/mach-dec/war.h create mode 100644 include/asm-mips/mach-emma2rh/war.h create mode 100644 include/asm-mips/mach-excite/war.h create mode 100644 include/asm-mips/mach-ip22/war.h create mode 100644 include/asm-mips/mach-ip27/war.h create mode 100644 include/asm-mips/mach-ip32/war.h create mode 100644 include/asm-mips/mach-jazz/war.h create mode 100644 include/asm-mips/mach-jmr3927/war.h create mode 100644 include/asm-mips/mach-lasat/war.h create mode 100644 include/asm-mips/mach-lemote/war.h create mode 100644 include/asm-mips/mach-mips/war.h create mode 100644 include/asm-mips/mach-mipssim/war.h create mode 100644 include/asm-mips/mach-pnx8550/war.h create mode 100644 include/asm-mips/mach-qemu/war.h create mode 100644 include/asm-mips/mach-rm/war.h create mode 100644 include/asm-mips/mach-sibyte/war.h create mode 100644 include/asm-mips/mach-tx49xx/war.h create mode 100644 include/asm-mips/mach-vr41xx/war.h create mode 100644 include/asm-mips/mach-wrppmc/war.h create mode 100644 include/asm-mips/mach-yosemite/war.h (limited to 'include/asm-mips/mach-bcm47xx') diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h new file mode 100644 index 00000000000..dd57d03d68b --- /dev/null +++ b/include/asm-mips/mach-au1x00/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H +#define __ASM_MIPS_MACH_AU1X00_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h new file mode 100644 index 00000000000..4a2b7986b58 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H +#define __ASM_MIPS_MACH_BCM947XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h new file mode 100644 index 00000000000..97884fd18ac --- /dev/null +++ b/include/asm-mips/mach-cobalt/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_COBALT_WAR_H +#define __ASM_MIPS_MACH_COBALT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h new file mode 100644 index 00000000000..ca5e2ef909a --- /dev/null +++ b/include/asm-mips/mach-dec/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_DEC_WAR_H +#define __ASM_MIPS_MACH_DEC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_DEC_WAR_H */ diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h new file mode 100644 index 00000000000..b660a4c30e6 --- /dev/null +++ b/include/asm-mips/mach-emma2rh/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H +#define __ASM_MIPS_MACH_EMMA2RH_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h new file mode 100644 index 00000000000..1f82180c159 --- /dev/null +++ b/include/asm-mips/mach-excite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H +#define __ASM_MIPS_MACH_EXCITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 00000000000..a44fa9656a8 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP22_WAR_H +#define __ASM_MIPS_MACH_IP22_WAR_H + +/* + * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 1 +#define R4600_V1_HIT_CACHEOP_WAR 1 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP22_WAR_H */ diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h new file mode 100644 index 00000000000..e2ddcc9b1ff --- /dev/null +++ b/include/asm-mips/mach-ip27/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP27_WAR_H +#define __ASM_MIPS_MACH_IP27_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 1 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP27_WAR_H */ diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h new file mode 100644 index 00000000000..d194056dcd7 --- /dev/null +++ b/include/asm-mips/mach-ip32/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_IP32_WAR_H +#define __ASM_MIPS_MACH_IP32_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_IP32_WAR_H */ diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h new file mode 100644 index 00000000000..6158ee861bf --- /dev/null +++ b/include/asm-mips/mach-jazz/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H +#define __ASM_MIPS_MACH_JAZZ_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h new file mode 100644 index 00000000000..1ff55fb3fbc --- /dev/null +++ b/include/asm-mips/mach-jmr3927/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H +#define __ASM_MIPS_MACH_JMR3927_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h new file mode 100644 index 00000000000..bb1e0325c9b --- /dev/null +++ b/include/asm-mips/mach-lasat/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_LASAT_WAR_H +#define __ASM_MIPS_MACH_LASAT_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h new file mode 100644 index 00000000000..05f89e0f2a1 --- /dev/null +++ b/include/asm-mips/mach-lemote/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H +#define __ASM_MIPS_MACH_LEMOTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h new file mode 100644 index 00000000000..7c6931d5f45 --- /dev/null +++ b/include/asm-mips/mach-mips/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h new file mode 100644 index 00000000000..c8a74a3515e --- /dev/null +++ b/include/asm-mips/mach-mipssim/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H +#define __ASM_MIPS_MACH_MIPSSIM_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h new file mode 100644 index 00000000000..d0458dd082f --- /dev/null +++ b/include/asm-mips/mach-pnx8550/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H +#define __ASM_MIPS_MACH_PNX8550_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h new file mode 100644 index 00000000000..0eaf0c548a4 --- /dev/null +++ b/include/asm-mips/mach-qemu/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_QEMU_WAR_H +#define __ASM_MIPS_MACH_QEMU_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h new file mode 100644 index 00000000000..948d3129a11 --- /dev/null +++ b/include/asm-mips/mach-rm/war.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_RM_WAR_H +#define __ASM_MIPS_MACH_RM_WAR_H + +/* + * The RM200C seems to have been shipped only with V2.0 R4600s + */ + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 1 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_RM_WAR_H */ diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h new file mode 100644 index 00000000000..7950ef4f032 --- /dev/null +++ b/include/asm-mips/mach-sibyte/war.h @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H +#define __ASM_MIPS_MACH_SIBYTE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 + +#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ + defined(CONFIG_SB1_PASS_2_WORKAROUNDS) + +#define BCM1250_M3_WAR 1 +#define SIBYTE_1956_WAR 1 + +#else + +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 + +#endif + +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h new file mode 100644 index 00000000000..39b5d1177c5 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H +#define __ASM_MIPS_MACH_TX49XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h new file mode 100644 index 00000000000..56a38926412 --- /dev/null +++ b/include/asm-mips/mach-vr41xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H +#define __ASM_MIPS_MACH_VR41XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h new file mode 100644 index 00000000000..ac48629bb1c --- /dev/null +++ b/include/asm-mips/mach-wrppmc/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H +#define __ASM_MIPS_MACH_WRPPMC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h new file mode 100644 index 00000000000..e5c6d53efc8 --- /dev/null +++ b/include/asm-mips/mach-yosemite/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H +#define __ASM_MIPS_MACH_YOSEMITE_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c0715d0a6b2..d2808edfd4e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -3,20 +3,22 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002, 2004 by Ralf Baechle + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle */ #ifndef _ASM_WAR_H #define _ASM_WAR_H +#include /* * Another R4600 erratum. Due to the lack of errata information the exact * technical details aren't known. I've experimentally found that disabling * interrupts during indexed I-cache flushes seems to be sufficient to deal * with the issue. - * - * #define R4600_V1_INDEX_ICACHEOP_WAR 1 */ +#ifndef R4600_V1_INDEX_ICACHEOP_WAR +#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform +#endif /* * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: @@ -43,9 +45,10 @@ * nop * nop * cache Hit_Writeback_Invalidate_D - * - * #define R4600_V1_HIT_CACHEOP_WAR 1 */ +#ifndef R4600_V1_HIT_CACHEOP_WAR +#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform +#endif /* @@ -58,32 +61,11 @@ * by a load instruction to an uncached address to empty the response buffer." * (Revision 2.0 device errata from IDT available on http://www.idt.com/ * in .pdf format.) - * - * #define R4600_V2_HIT_CACHEOP_WAR 1 - */ - -/* - * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. - */ -#ifdef CONFIG_SGI_IP22 - -#define R4600_V1_INDEX_ICACHEOP_WAR 1 -#define R4600_V1_HIT_CACHEOP_WAR 1 -#define R4600_V2_HIT_CACHEOP_WAR 1 - -#endif - -/* - * But the RM200C seems to have been shipped only with V2.0 R4600s */ -#ifdef CONFIG_SNI_RM - -#define R4600_V2_HIT_CACHEOP_WAR 1 - +#ifndef R4600_V2_HIT_CACHEOP_WAR +#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform #endif -#ifdef CONFIG_CPU_R5432 - /* * When an interrupt happens on a CP0 register read instruction, CPU may * lock up or read corrupted values of CP0 registers after it enters @@ -93,13 +75,10 @@ * first thing in the exception handler, which breaks one of the * pre-conditions for this problem. */ -#define R5432_CP0_INTERRUPT_WAR 1 - +#ifndef R5432_CP0_INTERRUPT_WAR +#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform #endif -#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ - defined(CONFIG_SB1_PASS_2_WORKAROUNDS) - /* * Workaround for the Sibyte M3 errata the text of which can be found at * @@ -110,13 +89,15 @@ * will just return and take the exception again if the information was * found to be inconsistent. */ -#define BCM1250_M3_WAR 1 +#ifndef BCM1250_M3_WAR +#error Check setting of BCM1250_M3_WAR for your platform +#endif /* * This is a DUART workaround related to glitches around register accesses */ -#define SIBYTE_1956_WAR 1 - +#ifndef SIBYTE_1956_WAR +#error Check setting of SIBYTE_1956_WAR for your platform #endif /* @@ -131,9 +112,8 @@ * Affects: * MIPS 4K RTL revision <3.0, PRID revision <4 */ -#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ - defined(CONFIG_MIPS_SEAD) -#define MIPS4K_ICACHE_REFILL_WAR 1 +#ifndef MIPS4K_ICACHE_REFILL_WAR +#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform #endif /* @@ -151,9 +131,8 @@ * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 * MIPS 20Kc RTL revision <4.0, PRID revision Date: Thu, 11 Oct 2007 23:46:08 +0100 Subject: [MIPS] Deforest the function pointer jungle in the time code. Hard to follow who is pointing what to where and why so it's simply getting in the way of the time code renovation. Signed-off-by: Ralf Baechle --- arch/mips/au1000/common/setup.c | 2 -- arch/mips/au1000/common/time.c | 4 --- arch/mips/basler/excite/excite_setup.c | 5 +-- arch/mips/bcm47xx/setup.c | 1 - arch/mips/bcm47xx/time.c | 3 +- arch/mips/dec/setup.c | 4 --- arch/mips/dec/time.c | 12 +++---- arch/mips/emma2rh/markeins/setup.c | 4 +-- arch/mips/gt64120/wrppmc/setup.c | 4 --- arch/mips/gt64120/wrppmc/time.c | 2 +- arch/mips/jmr3927/rbhma3100/setup.c | 4 +-- arch/mips/kernel/time.c | 45 ++++++++----------------- arch/mips/lasat/ds1603.c | 6 ++-- arch/mips/lasat/ds1603.h | 2 -- arch/mips/lasat/setup.c | 6 +--- arch/mips/lasat/sysctl.c | 10 +++--- arch/mips/lemote/lm2e/setup.c | 7 ++-- arch/mips/mips-boards/atlas/atlas_setup.c | 5 --- arch/mips/mips-boards/generic/time.c | 4 +-- arch/mips/mips-boards/malta/malta_setup.c | 4 --- arch/mips/mips-boards/sead/sead_setup.c | 3 -- arch/mips/mipssim/sim_setup.c | 2 -- arch/mips/mipssim/sim_time.c | 2 +- arch/mips/philips/pnx8550/common/setup.c | 3 -- arch/mips/philips/pnx8550/common/time.c | 7 ++-- arch/mips/pmc-sierra/msp71xx/msp_setup.c | 3 -- arch/mips/pmc-sierra/msp71xx/msp_time.c | 3 +- arch/mips/pmc-sierra/yosemite/setup.c | 18 ++-------- arch/mips/sgi-ip22/ip22-setup.c | 2 -- arch/mips/sgi-ip22/ip22-time.c | 15 ++------- arch/mips/sgi-ip27/ip27-init.c | 3 -- arch/mips/sgi-ip27/ip27-timer.c | 6 ++-- arch/mips/sgi-ip32/ip32-setup.c | 12 +++---- arch/mips/sibyte/swarm/setup.c | 56 ++++++++++++++++++++++++------- arch/mips/sni/pcimt.c | 1 - arch/mips/sni/pcit.c | 1 - arch/mips/sni/rm200.c | 1 - arch/mips/sni/time.c | 8 ++++- arch/mips/tx4927/common/tx4927_setup.c | 9 +---- arch/mips/tx4938/common/setup.c | 9 ----- arch/mips/tx4938/toshiba_rbtx4938/setup.c | 3 +- arch/mips/vr41xx/common/init.c | 8 +---- include/asm-mips/mach-bcm47xx/bcm47xx.h | 2 -- include/asm-mips/time.h | 12 +++---- 44 files changed, 114 insertions(+), 209 deletions(-) (limited to 'include/asm-mips/mach-bcm47xx') diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index a95b3777319..b212c072612 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -50,7 +50,6 @@ extern void au1000_halt(void); extern void au1000_power_off(void); extern void au1x_time_init(void); extern void au1x_timer_setup(struct irqaction *irq); -extern void au1xxx_time_init(void); extern void set_cpuspec(void); void __init plat_mem_setup(void) @@ -112,7 +111,6 @@ void __init plat_mem_setup(void) _machine_restart = au1000_restart; _machine_halt = au1000_halt; pm_power_off = au1000_power_off; - board_time_init = au1xxx_time_init; /* IO/MEM resources. */ set_io_port_base(0); diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 8fc29982d70..fb1fd50f19a 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -329,7 +329,3 @@ void __init plat_timer_setup(struct irqaction *irq) #endif } - -void __init au1xxx_time_init(void) -{ -} diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 56003188f17..68be19d1802 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c @@ -68,7 +68,7 @@ DEFINE_SPINLOCK(titan_lock); int titan_irqflags; -static void excite_timer_init(void) +void __init plat_time_init(void) { const u32 modebit5 = ocd_readl(0x00e4); unsigned int @@ -261,9 +261,6 @@ void __init plat_mem_setup(void) /* Announce RAM to system */ add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); - /* Set up timer initialization hooks */ - board_time_init = excite_timer_init; - /* Set up the peripheral address map */ *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c index f48aa5aa9bf..1b6b0fa5028 100644 --- a/arch/mips/bcm47xx/setup.c +++ b/arch/mips/bcm47xx/setup.c @@ -119,6 +119,5 @@ void __init plat_mem_setup(void) _machine_restart = bcm47xx_machine_restart; _machine_halt = bcm47xx_machine_halt; pm_power_off = bcm47xx_machine_halt; - board_time_init = bcm47xx_time_init; } diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index b27d07f2905..0ab4676c8bd 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -28,8 +28,7 @@ #include #include -void __init -bcm47xx_time_init(void) +void __init plat_time_init(void) { unsigned long hz; diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c index 3e634f2f544..bd5431e1f40 100644 --- a/arch/mips/dec/setup.c +++ b/arch/mips/dec/setup.c @@ -145,13 +145,9 @@ static void __init dec_be_init(void) } } - -extern void dec_time_init(void); - void __init plat_mem_setup(void) { board_be_init = dec_be_init; - board_time_init = dec_time_init; wbflush_setup(); diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index e2973a432b9..820e5331205 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -35,7 +35,7 @@ #include #include -static unsigned long dec_rtc_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, mon, day, hour, min, sec, real_year; unsigned long flags; @@ -74,13 +74,13 @@ static unsigned long dec_rtc_get_time(void) } /* - * In order to set the CMOS clock precisely, dec_rtc_set_mmss has to + * In order to set the CMOS clock precisely, rtc_mips_set_mmss has to * be called 500 ms after the second nowtime has started, because when * nowtime is written into the registers of the CMOS clock, it will * jump to the next second precisely 500 ms later. Check the Dallas * DS1287 data sheet for details. */ -static int dec_rtc_set_mmss(unsigned long nowtime) +int rtc_mips_set_mmss(unsigned long nowtime) { int retval = 0; int real_seconds, real_minutes, cmos_minutes; @@ -139,7 +139,6 @@ static int dec_rtc_set_mmss(unsigned long nowtime) return retval; } - static int dec_timer_state(void) { return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; @@ -160,11 +159,8 @@ static cycle_t dec_ioasic_hpt_read(void) } -void __init dec_time_init(void) +void __init plat_time_init(void) { - rtc_mips_get_time = dec_rtc_get_time; - rtc_mips_set_mmss = dec_rtc_set_mmss; - mips_timer_state = dec_timer_state; mips_timer_ack = dec_timer_ack; diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c index 2f060e1ed36..5e1da53b04a 100644 --- a/arch/mips/emma2rh/markeins/setup.c +++ b/arch/mips/emma2rh/markeins/setup.c @@ -88,7 +88,7 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base) return clock[reg]; } -static void __init emma2rh_time_init(void) +void __init plat_time_init(void) { u32 reg; if (bus_frequency == 0) @@ -124,8 +124,6 @@ void __init plat_mem_setup(void) set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); - board_time_init = emma2rh_time_init; - _machine_restart = markeins_machine_restart; _machine_halt = markeins_machine_halt; pm_power_off = markeins_machine_power_off; diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index 238b5087fbb..f2ccf101e6d 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -126,7 +126,6 @@ static void wrppmc_setup_serial(void) void __init plat_mem_setup(void) { - extern void wrppmc_time_init(void); extern void wrppmc_machine_restart(char *command); extern void wrppmc_machine_halt(void); extern void wrppmc_machine_power_off(void); @@ -135,9 +134,6 @@ void __init plat_mem_setup(void) _machine_halt = wrppmc_machine_halt; pm_power_off = wrppmc_machine_power_off; - /* Use MIPS Count/Compare Timer */ - board_time_init = wrppmc_time_init; - /* This makes the operations of 'in/out[bwl]' to the * physical address ( < KSEG0) can work via KSEG1 */ diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 5b440859bce..faf164e7e0d 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -38,7 +38,7 @@ void __init plat_timer_setup(struct irqaction *irq) * NOTE: We disable all GT64120 timers, and use MIPS processor internal * timer as the source of kernel clock tick. */ -void __init wrppmc_time_init(void) +void __init plat_time_init(void) { /* Disable GT64120 timers */ GT_WRITE(GT_TC_CONTROL_OFS, 0x00); diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c index fde56e86c2a..7f14f70a1b8 100644 --- a/arch/mips/jmr3927/rbhma3100/setup.c +++ b/arch/mips/jmr3927/rbhma3100/setup.c @@ -109,7 +109,7 @@ static void jmr3927_timer_ack(void) jmr3927_tmrptr->tisr = 0; /* ack interrupt */ } -static void __init jmr3927_time_init(void) +void __init plat_time_init(void) { clocksource_mips.read = jmr3927_hpt_read; mips_timer_ack = jmr3927_timer_ack; @@ -141,8 +141,6 @@ void __init plat_mem_setup(void) set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); - board_time_init = jmr3927_time_init; - _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; pm_power_off = jmr3927_machine_power_off; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 628a8ba6da5..9bbbd9b327f 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -49,24 +49,19 @@ * forward reference */ DEFINE_SPINLOCK(rtc_lock); +EXPORT_SYMBOL(rtc_lock); -/* - * By default we provide the null RTC ops - */ -static unsigned long null_rtc_get_time(void) +int __weak rtc_mips_set_time(unsigned long sec) { - return mktime(2000, 1, 1, 0, 0, 0); + return 0; } +EXPORT_SYMBOL(rtc_mips_set_time); -static int null_rtc_set_time(unsigned long sec) +int __weak rtc_mips_set_mmss(unsigned long nowtime) { - return 0; + return rtc_mips_set_time(nowtime); } -unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time; -int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time; -int (*rtc_mips_set_mmss)(unsigned long); - int update_persistent_clock(struct timespec now) { return rtc_mips_set_mmss(now.tv_sec); @@ -247,21 +242,18 @@ asmlinkage void ll_local_timer_interrupt(int irq) /* * time_init() - it does the following things. * - * 1) board_time_init() - + * 1) plat_time_init() - * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_hpt_frequency * (only needed if you intended to use cpu counter as timer interrupt * source) - * 2) setup xtime based on rtc_mips_get_time(). - * 3) calculate a couple of cached variables for later usage - * 4) plat_timer_setup() - + * 2) calculate a couple of cached variables for later usage + * 3) plat_timer_setup() - * a) (optional) over-write any choices made above by time_init(). * b) machine specific code should setup the timer irqaction. * c) enable the timer interrupt */ -void (*board_time_init)(void); - unsigned int mips_hpt_frequency; static struct irqaction timer_irqaction = { @@ -341,19 +333,13 @@ static void __init init_mips_clocksource(void) clocksource_register(&clocksource_mips); } -void __init time_init(void) +void __init __weak plat_time_init(void) { - if (board_time_init) - board_time_init(); - - if (!rtc_mips_set_mmss) - rtc_mips_set_mmss = rtc_mips_set_time; - - xtime.tv_sec = rtc_mips_get_time(); - xtime.tv_nsec = 0; +} - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); +void __init time_init(void) +{ + plat_time_init(); /* Choose appropriate high precision timer routines. */ if (!cpu_has_counter && !clocksource_mips.read) @@ -459,7 +445,4 @@ void to_tm(unsigned long tim, struct rtc_time *tm) tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */ } -EXPORT_SYMBOL(rtc_lock); EXPORT_SYMBOL(to_tm); -EXPORT_SYMBOL(rtc_mips_set_time); -EXPORT_SYMBOL(rtc_mips_get_time); diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c index 0b315f51d62..52cb1436a12 100644 --- a/arch/mips/lasat/ds1603.c +++ b/arch/mips/lasat/ds1603.c @@ -135,8 +135,7 @@ static void rtc_end_op(void) lasat_ndelay(1000); } -/* interface */ -unsigned long ds1603_read(void) +unsigned long read_persistent_clock(void) { unsigned long word; unsigned long flags; @@ -147,10 +146,11 @@ unsigned long ds1603_read(void) word = rtc_read_word(); rtc_end_op(); spin_unlock_irqrestore(&rtc_lock, flags); + return word; } -int ds1603_set(unsigned long time) +int rtc_mips_set_mmss(unsigned long time) { unsigned long flags; diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h index c2e5c76a379..2da3704044f 100644 --- a/arch/mips/lasat/ds1603.h +++ b/arch/mips/lasat/ds1603.h @@ -20,8 +20,6 @@ struct ds_defs { extern struct ds_defs *ds1603; -unsigned long ds1603_read(void); -int ds1603_set(unsigned long); void ds1603_set_trimmer(unsigned int); void ds1603_enable(void); void ds1603_disable(void); diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c index 187e37821d9..54827d0174b 100644 --- a/arch/mips/lasat/setup.c +++ b/arch/mips/lasat/setup.c @@ -117,7 +117,7 @@ static struct notifier_block lasat_panic_block[] = } }; -static void lasat_time_init(void) +void plat_time_init(void) { mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2; } @@ -142,12 +142,8 @@ void __init plat_mem_setup(void) lasat_reboot_setup(); - board_time_init = lasat_time_init; - #ifdef CONFIG_DS1603 ds1603 = &ds_defs[mips_machtype]; - rtc_mips_get_time = ds1603_read; - rtc_mips_set_time = ds1603_set; #endif #ifdef DYNAMIC_SERIAL_INIT diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c index 4575a829766..389336c4ecc 100644 --- a/arch/mips/lasat/sysctl.c +++ b/arch/mips/lasat/sysctl.c @@ -32,6 +32,8 @@ #include #include +#include + #include "sysctl.h" #include "ds1603.h" @@ -106,7 +108,7 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, mutex_lock(&lasat_info_mutex); if (!write) { - rtctmp = ds1603_read(); + rtctmp = read_persistent_clock(); /* check for time < 0 and set to 0 */ if (rtctmp < 0) rtctmp = 0; @@ -116,7 +118,7 @@ int proc_dolasatrtc(ctl_table *table, int write, struct file *filp, mutex_unlock(&lasat_info_mutex); return r; } - ds1603_set(rtctmp); + rtc_mips_set_mmss(rtctmp); mutex_unlock(&lasat_info_mutex); return 0; @@ -152,7 +154,7 @@ int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, int r; mutex_lock(&lasat_info_mutex); - rtctmp = ds1603_read(); + rtctmp = read_persistent_clock(); if (rtctmp < 0) rtctmp = 0; r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen); @@ -161,7 +163,7 @@ int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen, return r; } if (newval && newlen) - ds1603_set(rtctmp); + rtc_mips_set_mmss(rtctmp); mutex_unlock(&lasat_info_mutex); return 1; diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index f34350a4f27..09314a20f9f 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -58,13 +58,13 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); } -static void __init loongson2e_time_init(void) +void __init plat_time_init(void) { /* setup mips r4k timer */ mips_hpt_frequency = cpu_clock_freq / 2; } -static unsigned long __init mips_rtc_get_time(void) +unsigned long read_persistent_clock(void) { return mc146818_get_cmos_time(); } @@ -89,9 +89,6 @@ void __init plat_mem_setup(void) mips_reboot_setup(); - board_time_init = loongson2e_time_init; - rtc_mips_get_time = mips_rtc_get_time; - __wbflush = wbflush_loongson2e; add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c index c68358a476d..86bfc054816 100644 --- a/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/arch/mips/mips-boards/atlas/atlas_setup.c @@ -35,8 +35,6 @@ #include extern void mips_reboot_setup(void); -extern void mips_time_init(void); -extern unsigned long mips_rtc_get_time(void); #ifdef CONFIG_KGDB extern void kgdb_config(void); @@ -63,9 +61,6 @@ void __init plat_mem_setup(void) kgdb_config(); #endif mips_reboot_setup(); - - board_time_init = mips_time_init; - rtc_mips_get_time = mips_rtc_get_time; } static void __init serial_init(void) diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c index d7bff9ca535..075f9d46f40 100644 --- a/arch/mips/mips-boards/generic/time.c +++ b/arch/mips/mips-boards/generic/time.c @@ -224,12 +224,12 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -unsigned long __init mips_rtc_get_time(void) +unsigned long read_persistent_clock(void) { return mc146818_get_cmos_time(); } -void __init mips_time_init(void) +void __init plat_time_init(void) { unsigned int est_freq; diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c index 8f1b78dfd89..a5a5a43a198 100644 --- a/arch/mips/mips-boards/malta/malta_setup.c +++ b/arch/mips/mips-boards/malta/malta_setup.c @@ -36,7 +36,6 @@ #endif extern void mips_reboot_setup(void); -extern void mips_time_init(void); extern unsigned long mips_rtc_get_time(void); #ifdef CONFIG_KGDB @@ -185,7 +184,4 @@ void __init plat_mem_setup(void) #endif #endif mips_reboot_setup(); - - board_time_init = mips_time_init; - rtc_mips_get_time = mips_rtc_get_time; } diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c index 5f70eaf01fa..fad58972f3a 100644 --- a/arch/mips/mips-boards/sead/sead_setup.c +++ b/arch/mips/mips-boards/sead/sead_setup.c @@ -35,7 +35,6 @@ #include extern void mips_reboot_setup(void); -extern void mips_time_init(void); static void __init serial_init(void); @@ -52,8 +51,6 @@ void __init plat_mem_setup(void) serial_init (); - board_time_init = mips_time_init; - mips_reboot_setup(); } diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c index d012719c4d2..452c129d02c 100644 --- a/arch/mips/mipssim/sim_setup.c +++ b/arch/mips/mipssim/sim_setup.c @@ -36,7 +36,6 @@ #include -extern void sim_time_init(void); static void __init serial_init(void); unsigned int _isbonito = 0; @@ -54,7 +53,6 @@ void __init plat_mem_setup(void) serial_init(); - board_time_init = sim_time_init; pr_info("Linux started...\n"); #ifdef CONFIG_MIPS_MT_SMP diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index a0f5a5dca1b..9a355e77952 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c @@ -146,7 +146,7 @@ static unsigned int __init estimate_cpu_frequency(void) return count; } -void __init sim_time_init(void) +void __init plat_time_init(void) { unsigned int est_freq, flags; diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c index 5bd73747768..2ce298f4d19 100644 --- a/arch/mips/philips/pnx8550/common/setup.c +++ b/arch/mips/philips/pnx8550/common/setup.c @@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void); extern void pnx8550_machine_power_off(void); extern struct resource ioport_resource; extern struct resource iomem_resource; -extern void pnx8550_time_init(void); extern void rs_kgdb_hook(int tty_no); extern char *prom_getcmdline(void); @@ -104,8 +103,6 @@ void __init plat_mem_setup(void) _machine_halt = pnx8550_machine_halt; pm_power_off = pnx8550_machine_power_off; - board_time_init = pnx8550_time_init; - /* Clear the Global 2 Register, PCI Inta Output Enable Registers Bit 1:Enable DAC Powerdown -> 0:DACs are enabled and are working normally diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c index 68def3880a1..e818fd0f158 100644 --- a/arch/mips/philips/pnx8550/common/time.c +++ b/arch/mips/philips/pnx8550/common/time.c @@ -1,6 +1,7 @@ /* * Copyright 2001, 2002, 2003 MontaVista Software Inc. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) * * Common time service routines for MIPS machines. See * Documents/MIPS/README.txt. @@ -46,16 +47,16 @@ static void timer_ack(void) } /* - * pnx8550_time_init() - it does the following things: + * plat_time_init() - it does the following things: * - * 1) board_time_init() - + * 1) plat_time_init() - * a) (optional) set up RTC routines, * b) (optional) calibrate and set the mips_hpt_frequency * (only needed if you intended to use cpu counter as timer interrupt * source) */ -void pnx8550_time_init(void) +__init void plat_time_init(void) { unsigned int n; unsigned int m; diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c index e4cc5482447..c93675615f5 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c @@ -25,7 +25,6 @@ #define MSP_BOARD_RESET_GPIO 9 #endif -extern void msp_timer_init(void); extern void msp_serial_setup(void); extern void pmctwiled_setup(void); @@ -149,8 +148,6 @@ void __init plat_mem_setup(void) _machine_restart = msp_restart; _machine_halt = msp_halt; pm_power_off = msp_power_off; - - board_time_init = msp_timer_init; } void __init prom_init(void) diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c index 2a2beac5a4f..f221d476362 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_time.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c @@ -36,7 +36,7 @@ #include #include -void __init msp_timer_init(void) +void __init plat_time_init(void) { char *endp, *s; unsigned long cpu_rate = 0; @@ -81,7 +81,6 @@ void __init msp_timer_init(void) mips_hpt_frequency = cpu_rate/2; } - void __init plat_timer_setup(struct irqaction *irq) { #ifdef CONFIG_IRQ_MSP_CIC diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 58862c8d1d0..56bf69595da 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -70,7 +70,7 @@ void __init bus_error_init(void) } -unsigned long m48t37y_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, month, day, hour, min, sec; unsigned long flags; @@ -95,7 +95,7 @@ unsigned long m48t37y_get_time(void) return mktime(year, month, day, hour, min, sec); } -int m48t37y_set_time(unsigned long sec) +int rtc_mips_set_time(unsigned long tim) { struct rtc_time tm; unsigned long flags; @@ -138,7 +138,7 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(7, irq); } -void yosemite_time_init(void) +void __init plat_time_init(void) { mips_hpt_frequency = cpu_clock_freq / 2; mips_hpt_frequency = 33000000 * 3 * 5; @@ -198,17 +198,6 @@ static void __init py_rtc_setup(void) m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE); if (!m48t37_base) printk(KERN_ERR "Mapping the RTC failed\n"); - - rtc_mips_get_time = m48t37y_get_time; - rtc_mips_set_time = m48t37y_set_time; - - write_seqlock(&xtime_lock); - xtime.tv_sec = m48t37y_get_time(); - xtime.tv_nsec = 0; - - set_normalized_timespec(&wall_to_monotonic, - -xtime.tv_sec, -xtime.tv_nsec); - write_sequnlock(&xtime_lock); } /* Not only time init but that's what the hook it's called through is named */ @@ -221,7 +210,6 @@ static void __init py_late_time_init(void) void __init plat_mem_setup(void) { - board_time_init = yosemite_time_init; late_time_init = py_late_time_init; /* Add memory regions */ diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index e7ce7982db7..174f09e42f6 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -51,7 +51,6 @@ void ip22_do_break(void) EXPORT_SYMBOL(ip22_do_break); extern void ip22_be_init(void) __init; -extern void ip22_time_init(void) __init; void __init plat_mem_setup(void) { @@ -59,7 +58,6 @@ void __init plat_mem_setup(void) char *cserial; board_be_init = ip22_be_init; - ip22_time_init(); /* Init the INDY HPC I/O controller. Need to call this before * fucking with the memory controller because it needs to know the diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index de3d01823ad..0387c385b4b 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -32,7 +32,7 @@ * note that mktime uses month from 1 to 12 while to_tm * uses 0 to 11. */ -static unsigned long indy_rtc_get_time(void) +unsigned long read_persistent_clock(void) { unsigned int yrs, mon, day, hrs, min, sec; unsigned int save_control; @@ -60,7 +60,7 @@ static unsigned long indy_rtc_get_time(void) return mktime(yrs + 1900, mon, day, hrs, min, sec); } -static int indy_rtc_set_time(unsigned long tim) +int rtc_mips_set_time(unsigned long tim) { struct rtc_time tm; unsigned int save_control; @@ -128,7 +128,7 @@ static unsigned long dosample(void) /* * Here we need to calibrate the cycle counter to at least be close. */ -static __init void indy_time_init(void) +__init void plat_time_init(void) { unsigned long r4k_ticks[3]; unsigned long r4k_tick; @@ -207,12 +207,3 @@ void __init plat_timer_setup(struct irqaction *irq) /* setup irqaction */ setup_irq(SGI_TIMER_IRQ, irq); } - -void __init ip22_time_init(void) -{ - /* setup hookup functions */ - rtc_mips_get_time = indy_rtc_get_time; - rtc_mips_set_time = indy_rtc_set_time; - - board_time_init = indy_time_init; -} diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c index af08c41d6aa..681b593071c 100644 --- a/arch/mips/sgi-ip27/ip27-init.c +++ b/arch/mips/sgi-ip27/ip27-init.c @@ -194,7 +194,6 @@ static inline void ioc3_eth_init(void) ioc3->eier = 0; } -extern void ip27_time_init(void); extern void ip27_reboot_setup(void); void __init plat_mem_setup(void) @@ -241,6 +240,4 @@ void __init plat_mem_setup(void) per_cpu_init(); set_io_port_base(IO_BASE); - - board_time_init = ip27_time_init; } diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 31346162e9f..9c1700e85be 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -123,7 +123,7 @@ again: #include #include -static __init unsigned long get_m48t35_time(void) +unsigned long read_persistent_clock(void) { unsigned int year, month, date, hour, min, sec; struct m48t35_rtc *rtc; @@ -205,12 +205,10 @@ static cycle_t ip27_hpt_read(void) return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); } -void __init ip27_time_init(void) +void __init plat_time_init(void) { clocksource_mips.read = ip27_hpt_read; mips_hpt_frequency = CYCLES_PER_SEC; - xtime.tv_sec = get_m48t35_time(); - xtime.tv_nsec = 0; } void __init cpu_time_init(void) diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index bbba066cb40..4125a5ba119 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c @@ -62,10 +62,15 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) } #endif +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + /* An arbitrary time; this can be decreased if reliability looks good */ #define WAIT_MS 10 -void __init ip32_time_init(void) +void __init plat_time_init(void) { printk(KERN_INFO "Calibrating system timer... "); write_c0_count(0); @@ -85,11 +90,6 @@ void __init plat_mem_setup(void) { board_be_init = ip32_be_init; - rtc_mips_get_time = mc146818_get_cmos_time; - rtc_mips_set_mmss = mc146818_set_rtc_mmss; - - board_time_init = ip32_time_init; - #ifdef CONFIG_SGI_O2MACE_ETH { char *mac = ArcGetEnvironmentVariable("eaddr"); diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 83572d8f3e1..8b3ef0e4cd5 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -69,7 +69,7 @@ const char *get_system_type(void) return "SiByte " SIBYTE_BOARD_NAME; } -void __init swarm_time_init(void) +void __init plat_time_init(void) { #if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) /* Setup HPT */ @@ -104,6 +104,44 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup) return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); } +enum swarm_rtc_type { + RTC_NONE, + RTC_XICOR, + RTC_M4LT81 +}; + +enum swarm_rtc_type swarm_rtc_type; + +unsigned long read_persistent_clock(void) +{ + switch (swarm_rtc_type) { + case RTC_XICOR: + return xicor_get_time(); + + case RTC_M4LT81: + return m41t81_get_time(); + + case RTC_NONE: + default: + return mktime(2000, 1, 1, 0, 0, 0); + } +} + +int rtc_mips_set_time(unsigned long sec) +{ + switch (swarm_rtc_type) { + case RTC_XICOR: + return xicor_set_time(sec); + + case RTC_M4LT81: + return m41t81_set_time(sec); + + case RTC_NONE: + default: + return -1; + } +} + void __init plat_mem_setup(void) { #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) @@ -116,20 +154,12 @@ void __init plat_mem_setup(void) panic_timeout = 5; /* For debug. */ - board_time_init = swarm_time_init; board_be_handler = swarm_be_handler; - if (xicor_probe()) { - printk("swarm setup: Xicor 1241 RTC detected.\n"); - rtc_mips_get_time = xicor_get_time; - rtc_mips_set_time = xicor_set_time; - } - - if (m41t81_probe()) { - printk("swarm setup: M41T81 RTC detected.\n"); - rtc_mips_get_time = m41t81_get_time; - rtc_mips_set_time = m41t81_set_time; - } + if (xicor_probe()) + swarm_rtc_type = RTC_XICOR; + if (m41t81_probe()) + swarm_rtc_type = RTC_M4LT81; printk("This kernel optimized for " #ifdef CONFIG_SIMULATION diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 44b1ae62aa4..25cf646329a 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -313,7 +313,6 @@ void __init sni_pcimt_init(void) { sni_pcimt_detect(); sni_pcimt_sc_init(); - board_time_init = sni_cpu_time_init; ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI PCIBIOS_MIN_IO = 0x9000; diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 2480c478dcb..3361bdd240e 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -263,7 +263,6 @@ void __init sni_pcit_cplus_irq_init(void) void __init sni_pcit_init(void) { - board_time_init = sni_cpu_time_init; ioport_resource.end = sni_io_resource.end; #ifdef CONFIG_PCI PCIBIOS_MIN_IO = 0x9000; diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 28a11d8605c..94f115c6b2e 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -194,5 +194,4 @@ void __init sni_rm200_init(void) { set_io_port_base(SNI_PORT_BASE + 0x02000000); ioport_resource.end += 0x02000000; - board_time_init = sni_cpu_time_init; } diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 20028fc7757..92452d677d8 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -4,6 +4,7 @@ #include #include +#include #define SNI_CLOCK_TICK_RATE 3686400 #define SNI_COUNTER2_DIV 64 @@ -71,7 +72,7 @@ static __init unsigned long dosample(void) /* * Here we need to calibrate the cycle counter to at least be close. */ -__init void sni_cpu_time_init(void) +void __init plat_time_init(void) { unsigned long r4k_ticks[3]; unsigned long r4k_tick; @@ -146,3 +147,8 @@ void __init plat_timer_setup(struct irqaction *irq) break; } } + +unsigned long read_persistent_clock(void) +{ + return -1; +} diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c index b18ed58f88a..8ce0989671d 100644 --- a/arch/mips/tx4927/common/tx4927_setup.c +++ b/arch/mips/tx4927/common/tx4927_setup.c @@ -49,14 +49,11 @@ #undef DEBUG -void __init tx4927_time_init(void); void dump_cp0(char *key); void __init plat_mem_setup(void) { - board_time_init = tx4927_time_init; - #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_setup(void); @@ -65,20 +62,16 @@ void __init plat_mem_setup(void) #endif } -void __init tx4927_time_init(void) +void __init plat_time_init(void) { - #ifdef CONFIG_TOSHIBA_RBTX4927 { extern void toshiba_rbtx4927_time_init(void); toshiba_rbtx4927_time_init(); } #endif - - return; } - void __init plat_timer_setup(struct irqaction *irq) { setup_irq(TX4927_IRQ_CPU_TIMER, irq); diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c index 142abf453e4..ab408226755 100644 --- a/arch/mips/tx4938/common/setup.c +++ b/arch/mips/tx4938/common/setup.c @@ -34,25 +34,16 @@ #include extern void toshiba_rbtx4938_setup(void); -extern void rbtx4938_time_init(void); void __init tx4938_setup(void); -void __init tx4938_time_init(void); void dump_cp0(char *key); void __init plat_mem_setup(void) { - board_time_init = tx4938_time_init; toshiba_rbtx4938_setup(); } -void __init -tx4938_time_init(void) -{ - rbtx4938_time_init(); -} - void __init plat_timer_setup(struct irqaction *irq) { setup_irq(TX4938_IRQ_CPU_TIMER, irq); diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c index f236b1ff892..304b406fcb9 100644 --- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c +++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c @@ -39,7 +39,6 @@ #include #include -extern void rbtx4938_time_init(void) __init; extern char * __init prom_getcmdline(void); static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); @@ -856,7 +855,7 @@ void tx4938_report_pcic_status(void) /* We use onchip r4k counter or TMR timer as our system wide timer * interrupt running at 100HZ. */ -void __init rbtx4938_time_init(void) +void __init plat_time_init(void) { mips_hpt_frequency = txx9_cpu_clock / 2; } diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index 4f97e0ba9e2..407cec203b2 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -36,7 +36,7 @@ static void __init iomem_resource_init(void) iomem_resource.end = IO_MEM_RESOURCE_END; } -static void __init setup_timer_frequency(void) +void __init plat_time_init(void) { unsigned long tclock; @@ -53,16 +53,10 @@ void __init plat_timer_setup(struct irqaction *irq) setup_irq(TIMER_IRQ, irq); } -static void __init timer_init(void) -{ - board_time_init = setup_timer_frequency; -} - void __init plat_mem_setup(void) { vr41xx_calculate_clock_frequency(); - timer_init(); iomem_resource_init(); } diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h index a2fb5e8dd6c..d008f47a28b 100644 --- a/include/asm-mips/mach-bcm47xx/bcm47xx.h +++ b/include/asm-mips/mach-bcm47xx/bcm47xx.h @@ -22,6 +22,4 @@ /* SSB bus */ extern struct ssb_bus ssb_bcm47xx; -extern void bcm47xx_time_init(void); - #endif /* __ASM_BCM47XX_H */ diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index a632cef830a..74ab33157d6 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -26,15 +26,13 @@ extern spinlock_t rtc_lock; /* - * RTC ops. By default, they point to no-RTC functions. - * rtc_mips_get_time - mktime(year, mon, day, hour, min, sec) in seconds. + * RTC ops. By default, they point to weak no-op RTC functions. * rtc_mips_set_time - reverse the above translation and set time to RTC. * rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need * to be set. Used by RTC sync-up. */ -extern unsigned long (*rtc_mips_get_time)(void); -extern int (*rtc_mips_set_time)(unsigned long); -extern int (*rtc_mips_set_mmss)(unsigned long); +extern int rtc_mips_set_time(unsigned long); +extern int rtc_mips_set_mmss(unsigned long); /* * Timer interrupt functions. @@ -75,11 +73,9 @@ extern asmlinkage void ll_local_timer_interrupt(int irq); /* * board specific routines required by time_init(). - * board_time_init is defaulted to NULL and can remain so. - * plat_timer_setup must be setup properly in machine setup routine. */ struct irqaction; -extern void (*board_time_init)(void); +extern void plat_time_init(void); extern void plat_timer_setup(struct irqaction *irq); /* -- cgit v1.2.3-70-g09d2