From 17099b1142f6c0359fca60a3464dea8fb30badea Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 14 Jul 2007 13:24:05 +0100 Subject: [MIPS] Make support for weakly ordered LL/SC a config option. None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle --- include/asm-mips/system.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/asm-mips/system.h') diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 76339165bc2..eba2e3da9ab 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } @@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, raw_local_irq_restore(flags); /* implies memory barrier */ } - smp_mb(); + smp_llsc_mb(); return retval; } -- cgit v1.2.3-70-g09d2