From 3a0a401b40abe31b34673a190c57697e7eced149 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Sat, 3 Sep 2005 15:55:53 -0700 Subject: [PATCH] ppc32: add dcr_base field to ocp_func_mal_data Add dcr_base field to ocp_func_mal_data. This is preparation step for the new EMAC driver. Signed-off-by: Eugene Surovegin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-ppc/ibm_ocp.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/asm-ppc/ibm_ocp.h') diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h index 7fd4b6ce327..bd7656fa202 100644 --- a/include/asm-ppc/ibm_ocp.h +++ b/include/asm-ppc/ibm_ocp.h @@ -147,6 +147,7 @@ struct ocp_func_mal_data { int txde_irq; /* TX Descriptor Error IRQ */ int rxde_irq; /* RX Descriptor Error IRQ */ int serr_irq; /* MAL System Error IRQ */ + int dcr_base; /* MALx_CFG DCR number */ }; #define OCP_SYSFS_MAL_DATA() \ @@ -157,6 +158,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \ +OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, dcr_base) \ \ void ocp_show_mal_data(struct device *dev) \ { \ @@ -167,6 +169,7 @@ void ocp_show_mal_data(struct device *dev) \ device_create_file(dev, &dev_attr_mal_txde_irq); \ device_create_file(dev, &dev_attr_mal_rxde_irq); \ device_create_file(dev, &dev_attr_mal_serr_irq); \ + device_create_file(dev, &dev_attr_mal_dcr_base); \ } /* -- cgit v1.2.3-70-g09d2