From a439fe51a1f8eb087c22dd24d69cebae4a3addac Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 27 Jul 2008 23:00:59 +0200 Subject: sparc, sparc64: use arch/sparc/include The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg --- include/asm-sparc/psr.h | 93 ------------------------------------------------- 1 file changed, 93 deletions(-) delete mode 100644 include/asm-sparc/psr.h (limited to 'include/asm-sparc/psr.h') diff --git a/include/asm-sparc/psr.h b/include/asm-sparc/psr.h deleted file mode 100644 index b8c0e5f0a66..00000000000 --- a/include/asm-sparc/psr.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * psr.h: This file holds the macros for masking off various parts of - * the processor status register on the Sparc. This is valid - * for Version 8. On the V9 this is renamed to the PSTATE - * register and its members are accessed as fields like - * PSTATE.PRIV for the current CPU privilege level. - * - * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu) - */ - -#ifndef __LINUX_SPARC_PSR_H -#define __LINUX_SPARC_PSR_H - -/* The Sparc PSR fields are laid out as the following: - * - * ------------------------------------------------------------------------ - * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP | - * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 | - * ------------------------------------------------------------------------ - */ -#define PSR_CWP 0x0000001f /* current window pointer */ -#define PSR_ET 0x00000020 /* enable traps field */ -#define PSR_PS 0x00000040 /* previous privilege level */ -#define PSR_S 0x00000080 /* current privilege level */ -#define PSR_PIL 0x00000f00 /* processor interrupt level */ -#define PSR_EF 0x00001000 /* enable floating point */ -#define PSR_EC 0x00002000 /* enable co-processor */ -#define PSR_SYSCALL 0x00004000 /* inside of a syscall */ -#define PSR_LE 0x00008000 /* SuperSparcII little-endian */ -#define PSR_ICC 0x00f00000 /* integer condition codes */ -#define PSR_C 0x00100000 /* carry bit */ -#define PSR_V 0x00200000 /* overflow bit */ -#define PSR_Z 0x00400000 /* zero bit */ -#define PSR_N 0x00800000 /* negative bit */ -#define PSR_VERS 0x0f000000 /* cpu-version field */ -#define PSR_IMPL 0xf0000000 /* cpu-implementation field */ - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ -/* Get the %psr register. */ -static inline unsigned int get_psr(void) -{ - unsigned int psr; - __asm__ __volatile__( - "rd %%psr, %0\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (psr) - : /* no inputs */ - : "memory"); - - return psr; -} - -static inline void put_psr(unsigned int new_psr) -{ - __asm__ __volatile__( - "wr %0, 0x0, %%psr\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : /* no outputs */ - : "r" (new_psr) - : "memory", "cc"); -} - -/* Get the %fsr register. Be careful, make sure the floating point - * enable bit is set in the %psr when you execute this or you will - * incur a trap. - */ - -extern unsigned int fsr_storage; - -static inline unsigned int get_fsr(void) -{ - unsigned int fsr = 0; - - __asm__ __volatile__( - "st %%fsr, %1\n\t" - "ld %1, %0\n\t" - : "=r" (fsr) - : "m" (fsr_storage)); - - return fsr; -} - -#endif /* !(__ASSEMBLY__) */ - -#endif /* (__KERNEL__) */ - -#endif /* !(__LINUX_SPARC_PSR_H) */ -- cgit v1.2.3-70-g09d2