From 302b4215daa0a704c843da40fd2529e5757a72da Mon Sep 17 00:00:00 2001 From: Yu Zhao Date: Mon, 18 May 2009 13:51:32 +0800 Subject: PCI: support the ATS capability The PCIe ATS capability makes the Endpoint be able to request the DMA address translation from the IOMMU and cache the translation in the device side, thus alleviate IOMMU pressure and improve the hardware performance in the I/O virtualization environment. Signed-off-by: Yu Zhao Acked-by: Jesse Barnes Signed-off-by: David Woodhouse --- include/linux/pci_regs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/linux/pci_regs.h') diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index e4d08c1b2e0..c03189c56c7 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -501,6 +501,7 @@ #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 #define PCI_EXT_CAP_ID_ARI 14 +#define PCI_EXT_CAP_ID_ATS 15 #define PCI_EXT_CAP_ID_SRIOV 16 /* Advanced Error Reporting */ @@ -619,6 +620,15 @@ #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ +/* Address Translation Service */ +#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ +#define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) /* Invalidate Queue Depth */ +#define PCI_ATS_MAX_QDEP 32 /* Max Invalidate Queue Depth */ +#define PCI_ATS_CTRL 0x06 /* ATS Control Register */ +#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ +#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ +#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ + /* Single Root I/O Virtualization */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ -- cgit v1.2.3-70-g09d2 From 04846b5b8112e53b588038349b3e92b8485c1807 Mon Sep 17 00:00:00 2001 From: Hidetoshi Seto Date: Mon, 20 Apr 2009 10:54:52 +0900 Subject: PCI MSI: Remove unused/obsolete macros and definitions Impact: cleanup, spec compliance This patch does: - Remove unused msi/msix_enable/disable macros. User should use msi/msix_set_enable() functions instead. - Remove unused msix_mask/unmask/pending macros. These macros are useless because they are not based on any of the PCI Local Bus Specifications properly. It seems that they were written based on a draft of PCI spec, and that the draft was the MSI-X ECN that underwent membership review in September 2002. (* In the draft, the size of a entry in MSI-X table was 64bit, containing 32bit message data and DWORD aligned lower address plus a pending bit and a mask bit.(30+1+1bit) The higher address was placed in MSI-X capability structure and shared by all entries.) - Remove PCI_MSIX_FLAGS_BITMASK. This definition also come from the draft ECN. Signed-off-by: Hidetoshi Seto Reviewed-by: Matthew Wilcox Signed-off-by: Jesse Barnes --- drivers/pci/msi.h | 8 +------- include/linux/pci_regs.h | 1 - 2 files changed, 1 insertion(+), 8 deletions(-) (limited to 'include/linux/pci_regs.h') diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h index 71f4df2ef65..4fed5926195 100644 --- a/drivers/pci/msi.h +++ b/drivers/pci/msi.h @@ -19,18 +19,12 @@ ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 ) #define msi_mask_bits_reg(base, is64bit) \ ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4) -#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) #define msix_table_offset_reg(base) (base + 0x04) #define msix_pba_offset_reg(base) (base + 0x08) -#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE -#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) -#define multi_msix_capable msix_table_size -#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK) -#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK) -#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK) +#define multi_msix_capable(control) msix_table_size((control)) #endif /* MSI_H */ diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 616bf8b3c8b..dcba7668e0c 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -304,7 +304,6 @@ #define PCI_MSIX_FLAGS_ENABLE (1 << 15) #define PCI_MSIX_FLAGS_MASKALL (1 << 14) #define PCI_MSIX_FLAGS_BIRMASK (7 << 0) -#define PCI_MSIX_FLAGS_BITMASK (1 << 0) /* CompactPCI Hotswap Register */ -- cgit v1.2.3-70-g09d2 From 67b5db6502ddd27d65dea43bf036abbd82d0dfc9 Mon Sep 17 00:00:00 2001 From: Hidetoshi Seto Date: Mon, 20 Apr 2009 10:54:59 +0900 Subject: PCI MSI: Define PCI_MSI_MASK_32/64 Impact: cleanup, improve readability Define PCI_MSI_MASK_32/64 for 32/64bit devices, instead of using implicit offset (-4), "PCI_MSI_MASK_BIT - 4" and "PCI_MSI_MASK_BIT". Signed-off-by: Hidetoshi Seto Reviewed-by: Matthew Wilcox Signed-off-by: Jesse Barnes --- drivers/pci/msi.c | 2 +- drivers/pci/msi.h | 6 +++--- include/linux/pci_regs.h | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-) (limited to 'include/linux/pci_regs.h') diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 362773247fb..7ffac27d5d4 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -381,7 +381,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec) entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */ entry->msi_attrib.pos = pos; - entry->mask_pos = msi_mask_bits_reg(pos, entry->msi_attrib.is_64); + entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64); /* All MSIs are unmasked by default, Mask them all */ if (entry->msi_attrib.maskbit) pci_read_config_dword(dev, entry->mask_pos, &entry->masked); diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h index 4fed5926195..a0662842550 100644 --- a/drivers/pci/msi.h +++ b/drivers/pci/msi.h @@ -16,9 +16,9 @@ #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) #define msi_data_reg(base, is64bit) \ - ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 ) -#define msi_mask_bits_reg(base, is64bit) \ - ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4) + (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32)) +#define msi_mask_reg(base, is64bit) \ + (base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32)) #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index dcba7668e0c..83b02f5a25b 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -295,8 +295,9 @@ #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ +#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ -#define PCI_MSI_MASK_BIT 16 /* Mask bits register */ +#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ /* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ #define PCI_MSIX_FLAGS 2 -- cgit v1.2.3-70-g09d2