From a6c0c37db654444dfce91cd75ad8a56bb15a0d25 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Wed, 15 Oct 2008 22:03:44 -0700 Subject: radeonfb: misc cleanup of engine and dst cache handling Fix a couple of incomplete tests of the chip families in the engine init/reset code and proper initialization of the destination cache mode. The result should better match what the latest X radeon driver does. Signed-off-by: Benjamin Herrenschmidt Acked-by: David S. Miller Cc: Krzysztof Halasa Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/video/radeon.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/video/radeon.h b/include/video/radeon.h index 099ffa5e5be..1cd09cc5b16 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h @@ -386,7 +386,7 @@ #define SC_BOTTOM_RIGHT 0x16F0 #define SRC_SC_BOTTOM_RIGHT 0x16F4 #define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */ #define LVDS_GEN_CNTL 0x02d0 #define LVDS_PLL_CNTL 0x02d4 #define FP2_GEN_CNTL 0x0288 @@ -532,6 +532,9 @@ #define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D) #define RB2D_DC_BUSY (1 << 31) +/* DSTCACHE_MODE bits constants */ +#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) +#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) /* CRTC_GEN_CNTL bit constants */ #define CRTC_DBL_SCAN_EN 0x00000001 -- cgit v1.2.3-70-g09d2