From 06109f47f2c33fdd2b10194ee53235e72b8fbfe7 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 29 May 2014 15:08:03 +0100 Subject: ASoC: wm8804: Allow control of master clock divider in PLL generation WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider. Signed-off-by: Daniel Matuschek Tested-by: Florian Meier Signed-off-by: Charles Keepax Signed-off-by: Mark Brown --- sound/soc/codecs/wm8804.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'sound/soc/codecs/wm8804.h') diff --git a/sound/soc/codecs/wm8804.h b/sound/soc/codecs/wm8804.h index 8ec14f5573c..e72d4f4ba6b 100644 --- a/sound/soc/codecs/wm8804.h +++ b/sound/soc/codecs/wm8804.h @@ -57,5 +57,9 @@ #define WM8804_CLKOUT_SRC_OSCCLK 4 #define WM8804_CLKOUT_DIV 1 +#define WM8804_MCLK_DIV 2 + +#define WM8804_MCLKDIV_256FS 0 +#define WM8804_MCLKDIV_128FS 1 #endif /* _WM8804_H */ -- cgit v1.2.3-70-g09d2