From f74c95c20bad8e183e41283475f68a3e7b247af4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Thu, 30 Oct 2008 10:14:36 +0000 Subject: [ARM] S3C: Move regs-ac97.h to arch/arm/plat-s3c/include/plat. Move regs-ac97.h to arch/arm/plat-s3c/include/plat ready to clean out old include directories. Signed-off-by: Ben Dooks --- sound/soc/s3c24xx/s3c2443-ac97.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/s3c24xx/s3c2443-ac97.c b/sound/soc/s3c24xx/s3c2443-ac97.c index 19c5c3cf5d8..c473a3b97b5 100644 --- a/sound/soc/s3c24xx/s3c2443-ac97.c +++ b/sound/soc/s3c24xx/s3c2443-ac97.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include #include -- cgit v1.2.3-70-g09d2 From afb5b5c9adb66c73b83dc39319efbacb6fb26a7d Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Mon, 1 Dec 2008 11:43:08 +0800 Subject: [ARM] pxa: explicit #include in various drivers Where 'pxa_dma_desc' and 'pxa_{request,free}_dma' are referenced. Signed-off-by: Eric Miao --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- drivers/net/smc911x.h | 3 +++ sound/arm/pxa2xx-pcm.h | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index c0fa9c9edf0..64b3be1ea0a 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -20,8 +20,8 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index cc7d85bdfb3..870b4c33f10 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h @@ -200,6 +200,9 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg, #ifdef SMC_USE_PXA_DMA + +#include + /* * Define the request and free functions * These are unfortunately architecture specific as no generic allocation diff --git a/sound/arm/pxa2xx-pcm.h b/sound/arm/pxa2xx-pcm.h index 5c4a4d38a08..65f86b56ba4 100644 --- a/sound/arm/pxa2xx-pcm.h +++ b/sound/arm/pxa2xx-pcm.h @@ -9,7 +9,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include +#include struct pxa2xx_runtime_data { int dma_ch; -- cgit v1.2.3-70-g09d2 From 1f017a9964c5b3b9581d3a5732110cb1e0444281 Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 28 Nov 2008 14:19:33 +0800 Subject: [ARM] pxa: move AC97 register definitions into dedicated regs-ac97.h The optimal change would be to move the AC97 register definitions into the AC97 driver, unfortunately, the registers are shared between several files. Move them into a dedicated regs-ac97.h first. Signed-off-by: Eric Miao --- arch/arm/mach-pxa/include/mach/pxa-regs.h | 96 --------------------------- arch/arm/mach-pxa/include/mach/regs-ac97.h | 99 ++++++++++++++++++++++++++++ drivers/input/touchscreen/mainstone-wm97xx.c | 2 +- sound/arm/pxa2xx-ac97-lib.c | 2 +- sound/arm/pxa2xx-ac97.c | 1 + sound/soc/pxa/pxa2xx-ac97.c | 1 + 6 files changed, 103 insertions(+), 98 deletions(-) create mode 100644 arch/arm/mach-pxa/include/mach/regs-ac97.h (limited to 'sound') diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h index cb9b46de97c..a5650289803 100644 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -131,102 +131,6 @@ * Serial Audio Controller - moved into sound/soc/pxa/pxa2xx-i2s.c */ -/* - * AC97 Controller registers - */ - -#define POCR __REG(0x40500000) /* PCM Out Control Register */ -#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define PICR __REG(0x40500004) /* PCM In Control Register */ -#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MCCR __REG(0x40500008) /* Mic In Control Register */ -#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define GCR __REG(0x4050000C) /* Global Control Register */ -#ifdef CONFIG_PXA3xx -#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ -#endif -#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ -#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ -#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ -#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ -#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ -#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ -#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ -#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ -#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ -#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ -#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ - -#define POSR __REG(0x40500010) /* PCM Out Status Register */ -#define POSR_FIFOE (1 << 4) /* FIFO error */ -#define POSR_FSR (1 << 2) /* FIFO Service Request */ - -#define PISR __REG(0x40500014) /* PCM In Status Register */ -#define PISR_FIFOE (1 << 4) /* FIFO error */ -#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define PISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MCSR __REG(0x40500018) /* Mic In Status Register */ -#define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MCSR_FSR (1 << 2) /* FIFO Service Request */ - -#define GSR __REG(0x4050001C) /* Global Status Register */ -#define GSR_CDONE (1 << 19) /* Command Done */ -#define GSR_SDONE (1 << 18) /* Status Done */ -#define GSR_RDCS (1 << 15) /* Read Completion Status */ -#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ -#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ -#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ -#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ -#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ -#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ -#define GSR_PCR (1 << 8) /* Primary Codec Ready */ -#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ -#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ -#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ -#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ -#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ -#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ -#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ - -#define CAR __REG(0x40500020) /* CODEC Access Register */ -#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ - -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ - -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ -#define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MICR __REG(0x40500108) /* Modem In Control Register */ -#define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ - -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ -#define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MOSR_FSR (1 << 2) /* FIFO Service Request */ - -#define MISR __REG(0x40500118) /* Modem In Status Register */ -#define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ -#define MISR_FSR (1 << 2) /* FIFO Service Request */ - -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ - -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ - - /* * Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c */ diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/mach-pxa/include/mach/regs-ac97.h new file mode 100644 index 00000000000..e41b9d202b8 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ac97.h @@ -0,0 +1,99 @@ +#ifndef __ASM_ARCH_REGS_AC97_H +#define __ASM_ARCH_REGS_AC97_H + +/* + * AC97 Controller registers + */ + +#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ +#define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif +#define GCR_nDMAEN (1 << 24) /* non DMA Enable */ +#define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ +#define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ +#define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ +#define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ +#define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ +#define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ +#define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ +#define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ +#define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ +#define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ + +#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR_FIFOE (1 << 4) /* FIFO error */ +#define POSR_FSR (1 << 2) /* FIFO Service Request */ + +#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR_FIFOE (1 << 4) /* FIFO error */ +#define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define PISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR_FIFOE (1 << 4) /* FIFO error */ +#define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MCSR_FSR (1 << 2) /* FIFO Service Request */ + +#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR_CDONE (1 << 19) /* Command Done */ +#define GSR_SDONE (1 << 18) /* Status Done */ +#define GSR_RDCS (1 << 15) /* Read Completion Status */ +#define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ +#define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ +#define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ +#define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ +#define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ +#define GSR_SCR (1 << 9) /* Secondary Codec Ready */ +#define GSR_PCR (1 << 8) /* Primary Codec Ready */ +#define GSR_MCINT (1 << 7) /* Mic In Interrupt */ +#define GSR_POINT (1 << 6) /* PCM Out Interrupt */ +#define GSR_PIINT (1 << 5) /* PCM In Interrupt */ +#define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ +#define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ +#define GSR_MIINT (1 << 1) /* Modem In Interrupt */ +#define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ + +#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR_CAIP (1 << 0) /* Codec Access In Progress */ + +#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ +#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ + +#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR_FEIE (1 << 3) /* FIFO Error */ +#define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR_FEIE (1 << 3) /* FIFO Error */ +#define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ + +#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR_FIFOE (1 << 4) /* FIFO error */ +#define MOSR_FSR (1 << 2) /* FIFO Service Request */ + +#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR_FIFOE (1 << 4) /* FIFO error */ +#define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ +#define MISR_FSR (1 << 2) /* FIFO Service Request */ + +#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ + +#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ +#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ +#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ +#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ + +#endif /* __ASM_ARCH_REGS_AC97_H */ diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c index ba648750a8d..1d11e2be9ef 100644 --- a/drivers/input/touchscreen/mainstone-wm97xx.c +++ b/drivers/input/touchscreen/mainstone-wm97xx.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #define VERSION "0.13" diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 34c1d94f921..ef6539eea57 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c @@ -22,7 +22,7 @@ #include #include -#include +#include #include #include diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index c2635beb4c8..85cf591d4e1 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c @@ -22,6 +22,7 @@ #include #include +#include #include #include "pxa2xx-pcm.h" diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c index a7a3a9c5c6f..5e727393cfd 100644 --- a/sound/soc/pxa/pxa2xx-ac97.c +++ b/sound/soc/pxa/pxa2xx-ac97.c @@ -21,6 +21,7 @@ #include #include +#include #include "pxa2xx-pcm.h" #include "pxa2xx-ac97.h" -- cgit v1.2.3-70-g09d2 From 70d13e083c8589dd3edc2313777655da39cb3568 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 6 Dec 2008 08:25:16 +0000 Subject: [ARM] netwinder: clean up GPIO naming Netwinder was using gpio_xxx names which could clash with the GPIO layer. Add a 'nw_' prefix to ensure that these remain separate. Signed-off-by: Russell King --- arch/arm/mach-footbridge/cats-hw.c | 1 + arch/arm/mach-footbridge/common.c | 1 + arch/arm/mach-footbridge/dc21285-timer.c | 1 + arch/arm/mach-footbridge/dc21285.c | 1 + arch/arm/mach-footbridge/dma.c | 1 + arch/arm/mach-footbridge/ebsa285.c | 1 + arch/arm/mach-footbridge/include/mach/hardware.h | 9 ++-- arch/arm/mach-footbridge/isa-irq.c | 1 + arch/arm/mach-footbridge/netwinder-hw.c | 54 ++++++++++++------------ arch/arm/mach-footbridge/netwinder-leds.c | 7 ++- arch/arm/mach-footbridge/personal.c | 1 + drivers/char/ds1620.c | 25 ++++++----- drivers/char/nwflash.c | 8 ++-- drivers/mtd/maps/dc21285.c | 7 ++- sound/oss/waveartist.c | 8 ++-- 15 files changed, 64 insertions(+), 62 deletions(-) (limited to 'sound') diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c index 6a5b437ab86..1b996b26d2e 100644 --- a/arch/arm/mach-footbridge/cats-hw.c +++ b/arch/arm/mach-footbridge/cats-hw.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 818014e09f4..36ff06d4df1 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c index b2a21189dd8..da35bc5c5cc 100644 --- a/arch/arm/mach-footbridge/dc21285-timer.c +++ b/arch/arm/mach-footbridge/dc21285-timer.c @@ -7,6 +7,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index d4c1e526f59..133086019e3 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c index b653e9cfa3f..4f350634696 100644 --- a/arch/arm/mach-footbridge/dma.c +++ b/arch/arm/mach-footbridge/dma.c @@ -12,6 +12,7 @@ */ #include #include +#include #include #include diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c index b1d3bf20a41..30040fd588c 100644 --- a/arch/arm/mach-footbridge/ebsa285.c +++ b/arch/arm/mach-footbridge/ebsa285.c @@ -4,6 +4,7 @@ * EBSA285 machine fixup */ #include +#include #include #include diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index ff44e0ce2e1..51dd902043a 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -86,10 +86,11 @@ #define CPLD_FLASH_WR_ENABLE 1 #ifndef __ASSEMBLY__ -extern void gpio_modify_op(int mask, int set); -extern void gpio_modify_io(int mask, int in); -extern int gpio_read(void); -extern void cpld_modify(int mask, int set); +extern spinlock_t nw_gpio_lock; +extern void nw_gpio_modify_op(unsigned int mask, unsigned int set); +extern void nw_gpio_modify_io(unsigned int mask, unsigned int in); +extern unsigned int nw_gpio_read(void); +extern void nw_cpld_modify(unsigned int mask, unsigned int set); #endif #define pcibios_assign_all_busses() 1 diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c index 54fec9ae28b..9ee80a211d3 100644 --- a/arch/arm/mach-footbridge/isa-irq.c +++ b/arch/arm/mach-footbridge/isa-irq.c @@ -19,6 +19,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c index 00b0ddcac28..ac7ffa6fc41 100644 --- a/arch/arm/mach-footbridge/netwinder-hw.c +++ b/arch/arm/mach-footbridge/netwinder-hw.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -67,13 +68,14 @@ static inline void wb977_ww(int reg, int val) /* * This is a lock for accessing ports GP1_IO_BASE and GP2_IO_BASE */ -DEFINE_SPINLOCK(gpio_lock); +DEFINE_SPINLOCK(nw_gpio_lock); +EXPORT_SYMBOL(nw_gpio_lock); static unsigned int current_gpio_op; static unsigned int current_gpio_io; static unsigned int current_cpld; -void gpio_modify_op(int mask, int set) +void nw_gpio_modify_op(unsigned int mask, unsigned int set) { unsigned int new_gpio, changed; @@ -86,6 +88,7 @@ void gpio_modify_op(int mask, int set) if (changed & 0xff00) outb(new_gpio >> 8, GP2_IO_BASE); } +EXPORT_SYMBOL(nw_gpio_modify_op); static inline void __gpio_modify_io(int mask, int in) { @@ -118,7 +121,7 @@ static inline void __gpio_modify_io(int mask, int in) } } -void gpio_modify_io(int mask, int in) +void nw_gpio_modify_io(unsigned int mask, unsigned int in) { /* Open up the SuperIO chip */ wb977_open(); @@ -128,11 +131,13 @@ void gpio_modify_io(int mask, int in) /* Close up the EFER gate */ wb977_close(); } +EXPORT_SYMBOL(nw_gpio_modify_io); -int gpio_read(void) +unsigned int nw_gpio_read(void) { return inb(GP1_IO_BASE) | inb(GP2_IO_BASE) << 8; } +EXPORT_SYMBOL(nw_gpio_read); /* * Initialise the Winbond W83977F global registers @@ -322,9 +327,9 @@ static inline void wb977_init_gpio(void) /* * Set Group1/Group2 outputs */ - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(-1, GPIO_RED_LED | GPIO_FAN); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } /* @@ -359,34 +364,35 @@ static void __init wb977_init(void) wb977_close(); } -void cpld_modify(int mask, int set) +void nw_cpld_modify(unsigned int mask, unsigned int set) { int msk; current_cpld = (current_cpld & ~mask) | set; - gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0); - gpio_modify_op(GPIO_IOLOAD, 0); + nw_gpio_modify_io(GPIO_DATA | GPIO_IOCLK | GPIO_IOLOAD, 0); + nw_gpio_modify_op(GPIO_IOLOAD, 0); for (msk = 8; msk; msk >>= 1) { int bit = current_cpld & msk; - gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0); - gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK); + nw_gpio_modify_op(GPIO_DATA | GPIO_IOCLK, bit ? GPIO_DATA : 0); + nw_gpio_modify_op(GPIO_IOCLK, GPIO_IOCLK); } - gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0); - gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK); - gpio_modify_op(GPIO_IOLOAD, 0); + nw_gpio_modify_op(GPIO_IOCLK|GPIO_DATA, 0); + nw_gpio_modify_op(GPIO_IOLOAD|GPIO_DSCLK, GPIO_IOLOAD|GPIO_DSCLK); + nw_gpio_modify_op(GPIO_IOLOAD, 0); } +EXPORT_SYMBOL(nw_cpld_modify); static void __init cpld_init(void) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(-1, CPLD_UNMUTE | CPLD_7111_DISABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static unsigned char rwa_unlock[] __initdata = @@ -596,12 +602,6 @@ static void __init rwa010_init(void) rwa010_soundblaster_reset(); } -EXPORT_SYMBOL(gpio_lock); -EXPORT_SYMBOL(gpio_modify_op); -EXPORT_SYMBOL(gpio_modify_io); -EXPORT_SYMBOL(cpld_modify); -EXPORT_SYMBOL(gpio_read); - /* * Initialise any other hardware after we've got the PCI bus * initialised. We may need the PCI bus to talk to this other @@ -616,9 +616,9 @@ static int __init nw_hw_init(void) cpld_init(); rwa010_init(); - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_RED_LED|GPIO_GREEN_LED, DEFAULT_LEDS); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } return 0; } diff --git a/arch/arm/mach-footbridge/netwinder-leds.c b/arch/arm/mach-footbridge/netwinder-leds.c index d91a4f4a32d..00269fe0be8 100644 --- a/arch/arm/mach-footbridge/netwinder-leds.c +++ b/arch/arm/mach-footbridge/netwinder-leds.c @@ -32,7 +32,6 @@ static char led_state; static char hw_led_state; static DEFINE_SPINLOCK(leds_lock); -extern spinlock_t gpio_lock; static void netwinder_leds_event(led_event_t evt) { @@ -121,9 +120,9 @@ static void netwinder_leds_event(led_event_t evt) spin_unlock_irqrestore(&leds_lock, flags); if (led_state & LED_STATE_ENABLED) { - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_RED_LED | GPIO_GREEN_LED, hw_led_state); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } } diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c index c4f843fc099..e2c9f0690b1 100644 --- a/arch/arm/mach-footbridge/personal.c +++ b/arch/arm/mach-footbridge/personal.c @@ -4,6 +4,7 @@ * Personal server (Skiff) machine fixup */ #include +#include #include #include diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c index 74e9cd81b5b..61f0146e215 100644 --- a/drivers/char/ds1620.c +++ b/drivers/char/ds1620.c @@ -43,52 +43,51 @@ static const char *fan_state[] = { "off", "on", "on (hardwired)" }; * chance that the WaveArtist driver could touch these bits to * enable or disable the speaker. */ -extern spinlock_t gpio_lock; extern unsigned int system_rev; static inline void netwinder_ds1620_set_clk(int clk) { - gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); + nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0); } static inline void netwinder_ds1620_set_data(int dat) { - gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0); + nw_gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0); } static inline int netwinder_ds1620_get_data(void) { - return gpio_read() & GPIO_DATA; + return nw_gpio_read() & GPIO_DATA; } static inline void netwinder_ds1620_set_data_dir(int dir) { - gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0); + nw_gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0); } static inline void netwinder_ds1620_reset(void) { - cpld_modify(CPLD_DS_ENABLE, 0); - cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE); + nw_cpld_modify(CPLD_DS_ENABLE, 0); + nw_cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE); } static inline void netwinder_lock(unsigned long *flags) { - spin_lock_irqsave(&gpio_lock, *flags); + spin_lock_irqsave(&nw_gpio_lock, *flags); } static inline void netwinder_unlock(unsigned long *flags) { - spin_unlock_irqrestore(&gpio_lock, *flags); + spin_unlock_irqrestore(&nw_gpio_lock, *flags); } static inline void netwinder_set_fan(int i) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static inline int netwinder_get_fan(void) @@ -96,7 +95,7 @@ static inline int netwinder_get_fan(void) if ((system_rev & 0xf000) == 0x4000) return FAN_ALWAYS_ON; - return (gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF; + return (nw_gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF; } /* diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c index 006be92ee3f..8c7df5ba088 100644 --- a/drivers/char/nwflash.c +++ b/drivers/char/nwflash.c @@ -58,8 +58,6 @@ static volatile unsigned char *FLASH_BASE; static int gbFlashSize = KFLASH_SIZE; static DEFINE_MUTEX(nwflash_mutex); -extern spinlock_t gpio_lock; - static int get_flash_id(void) { volatile unsigned int c1, c2; @@ -616,9 +614,9 @@ static void kick_open(void) * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(1, 1); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c index 3aa018c092f..42969fe051b 100644 --- a/drivers/mtd/maps/dc21285.c +++ b/drivers/mtd/maps/dc21285.c @@ -32,16 +32,15 @@ static struct mtd_info *dc21285_mtd; */ static void nw_en_write(void) { - extern spinlock_t gpio_lock; unsigned long flags; /* * we want to write a bit pattern XXX1 to Xilinx to enable * the write gate, which will be open for about the next 2ms. */ - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(1, 1); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); /* * let the ISA bus to catch on... diff --git a/sound/oss/waveartist.c b/sound/oss/waveartist.c index c47842fad65..2c63bb9da74 100644 --- a/sound/oss/waveartist.c +++ b/sound/oss/waveartist.c @@ -1483,16 +1483,14 @@ static void __exit unload_waveartist(struct address_info *hw) #define VNC_HANDSET_DETECT 0x40 #define VNC_DISABLE_AUTOSWITCH 0x80 -extern spinlock_t gpio_lock; - static inline void vnc_mute_spkr(wavnc_info *devc) { unsigned long flags; - spin_lock_irqsave(&gpio_lock, flags); - cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE); - spin_unlock_irqrestore(&gpio_lock, flags); + spin_lock_irqsave(&nw_gpio_lock, flags); + nw_cpld_modify(CPLD_UNMUTE, devc->spkr_mute_state ? 0 : CPLD_UNMUTE); + spin_unlock_irqrestore(&nw_gpio_lock, flags); } static void -- cgit v1.2.3-70-g09d2