/* * Device Tree file for Marvell Armada 375 evaluation board * (DB-88F6720) * * Copyright (C) 2014 Marvell * * Gregory CLEMENT * Thomas Petazzoni * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ /dts-v1/; #include #include "armada-375.dtsi" / { model = "Marvell Armada 375 Development Board"; compatible = "marvell,a375-db", "marvell,armada375"; chosen { bootargs = "console=ttyS0,115200 earlyprintk"; }; memory { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; soc { ranges = ; internal-regs { spi@10600 { pinctrl-0 = <&spi0_pins>; pinctrl-names = "default"; /* * SPI conflicts with NAND, so we disable it * here, and select NAND as the enabled device * by default. */ status = "disabled"; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13"; reg = <0>; /* Chip select 0 */ spi-max-frequency = <108000000>; }; }; i2c@11000 { status = "okay"; clock-frequency = <100000>; pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; }; i2c@11100 { status = "okay"; clock-frequency = <100000>; pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; }; serial@12000 { status = "okay"; }; pinctrl { sdio_st_pins: sdio-st-pins { marvell,pins = "mpp44", "mpp45"; marvell,function = "gpio"; }; }; nand: nand@d0000 { pinctrl-0 = <&nand_pins>; pinctrl-names = "default"; status = "okay"; num-cs = <1>; marvell,nand-keep-config; marvell,nand-enable-arbiter; nand-on-flash-bbt; partition@0 { label = "U-Boot"; reg = <0 0x800000>; }; partition@800000 { label = "Linux"; reg = <0x800000 0x800000>; }; partition@1000000 { label = "Filesystem"; reg = <0x1000000 0x3f000000>; }; }; usb@54000 { status = "okay"; }; usb3@58000 { status = "okay"; }; mvsdio@d4000 { pinctrl-0 = <&sdio_pins &sdio_st_pins>; pinctrl-names = "default"; status = "okay"; cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; }; pcie-controller { status = "okay"; /* * The two PCIe units are accessible through * standard PCIe slots on the board. */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; }; pcie@2,0 { /* Port 1, Lane 0 */ status = "okay"; }; }; }; };